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-rw-r--r--arch/arm/mach-at91/Kconfig17
-rw-r--r--arch/arm/mach-at91/Makefile5
-rw-r--r--arch/arm/mach-at91/at91rm9200_devices.c3
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c3
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c3
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c3
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c341
-rw-r--r--arch/arm/mach-at91/at91sam9rl_devices.c630
-rw-r--r--arch/arm/mach-at91/board-sam9261ek.c3
-rw-r--r--arch/arm/mach-at91/board-sam9rlek.c204
-rw-r--r--arch/arm/mach-at91/generic.h2
11 files changed, 1202 insertions, 12 deletions
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 018d637f87fc..a31157f1655a 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -17,6 +17,9 @@ config ARCH_AT91SAM9261
17config ARCH_AT91SAM9263 17config ARCH_AT91SAM9263
18 bool "AT91SAM9263" 18 bool "AT91SAM9263"
19 19
20config ARCH_AT91SAM9RL
21 bool "AT91SAM9RL"
22
20endchoice 23endchoice
21 24
22# ---------------------------------------------------------- 25# ----------------------------------------------------------
@@ -152,6 +155,20 @@ endif
152 155
153# ---------------------------------------------------------- 156# ----------------------------------------------------------
154 157
158if ARCH_AT91SAM9RL
159
160comment "AT91SAM9RL Board Type"
161
162config MACH_AT91SAM9RLEK
163 bool "Atmel AT91SAM9RL-EK Evaluation Kit"
164 depends on ARCH_AT91SAM9RL
165 help
166 Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
167
168endif
169
170# ----------------------------------------------------------
171
155comment "AT91 Board Options" 172comment "AT91 Board Options"
156 173
157config MTD_AT91_DATAFLASH_CARD 174config MTD_AT91_DATAFLASH_CARD
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index a412ae18a421..a4d80eb056ee 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devic
14obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o 14obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o
15obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o 15obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
16obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o 16obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o
17obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o
17 18
18# AT91RM9200 board-specific support 19# AT91RM9200 board-specific support
19obj-$(CONFIG_MACH_ONEARM) += board-1arm.o 20obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
@@ -36,9 +37,13 @@ obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
36# AT91SAM9263 board-specific support 37# AT91SAM9263 board-specific support
37obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o 38obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
38 39
40# AT91SAM9RL board-specific support
41obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
42
39# LEDs support 43# LEDs support
40led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o 44led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o
41led-$(CONFIG_MACH_AT91RM9200EK) += leds.o 45led-$(CONFIG_MACH_AT91RM9200EK) += leds.o
46led-$(CONFIG_MACH_AT91SAM9261EK)+= leds.o
42led-$(CONFIG_MACH_CSB337) += leds.o 47led-$(CONFIG_MACH_CSB337) += leds.o
43led-$(CONFIG_MACH_CSB637) += leds.o 48led-$(CONFIG_MACH_CSB637) += leds.o
44led-$(CONFIG_MACH_KB9200) += leds.o 49led-$(CONFIG_MACH_KB9200) += leds.o
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 2624a4f22d61..70599bcf451c 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -22,9 +22,6 @@
22 22
23#include "generic.h" 23#include "generic.h"
24 24
25#define SZ_512 0x00000200
26#define SZ_256 0x00000100
27#define SZ_16 0x00000010
28 25
29/* -------------------------------------------------------------------- 26/* --------------------------------------------------------------------
30 * USB Host 27 * USB Host
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 40586e22cd38..ffd3154c1e54 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -22,9 +22,6 @@
22 22
23#include "generic.h" 23#include "generic.h"
24 24
25#define SZ_512 0x00000200
26#define SZ_256 0x00000100
27#define SZ_16 0x00000010
28 25
29/* -------------------------------------------------------------------- 26/* --------------------------------------------------------------------
30 * USB Host 27 * USB Host
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 8e781997716a..9db58da04754 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -23,9 +23,6 @@
23 23
24#include "generic.h" 24#include "generic.h"
25 25
26#define SZ_512 0x00000200
27#define SZ_256 0x00000100
28#define SZ_16 0x00000010
29 26
30/* -------------------------------------------------------------------- 27/* --------------------------------------------------------------------
31 * USB Host 28 * USB Host
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 2b2e18a67128..635695787f91 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -22,9 +22,6 @@
22 22
23#include "generic.h" 23#include "generic.h"
24 24
25#define SZ_512 0x00000200
26#define SZ_256 0x00000100
27#define SZ_16 0x00000010
28 25
29/* -------------------------------------------------------------------- 26/* --------------------------------------------------------------------
30 * USB Host 27 * USB Host
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
new file mode 100644
index 000000000000..4813a35f6cf5
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -0,0 +1,341 @@
1/*
2 * arch/arm/mach-at91/at91sam9rl.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 */
11
12#include <linux/module.h>
13
14#include <asm/mach/arch.h>
15#include <asm/mach/map.h>
16#include <asm/arch/cpu.h>
17#include <asm/arch/at91sam9rl.h>
18#include <asm/arch/at91_pmc.h>
19#include <asm/arch/at91_rstc.h>
20
21#include "generic.h"
22#include "clock.h"
23
24static struct map_desc at91sam9rl_io_desc[] __initdata = {
25 {
26 .virtual = AT91_VA_BASE_SYS,
27 .pfn = __phys_to_pfn(AT91_BASE_SYS),
28 .length = SZ_16K,
29 .type = MT_DEVICE,
30 },
31};
32
33static struct map_desc at91sam9rl_sram_desc[] __initdata = {
34 {
35 .pfn = __phys_to_pfn(AT91SAM9RL_SRAM_BASE),
36 .type = MT_DEVICE,
37 }
38};
39
40/* --------------------------------------------------------------------
41 * Clocks
42 * -------------------------------------------------------------------- */
43
44/*
45 * The peripheral clocks.
46 */
47static struct clk pioA_clk = {
48 .name = "pioA_clk",
49 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
50 .type = CLK_TYPE_PERIPHERAL,
51};
52static struct clk pioB_clk = {
53 .name = "pioB_clk",
54 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
55 .type = CLK_TYPE_PERIPHERAL,
56};
57static struct clk pioC_clk = {
58 .name = "pioC_clk",
59 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
60 .type = CLK_TYPE_PERIPHERAL,
61};
62static struct clk pioD_clk = {
63 .name = "pioD_clk",
64 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
65 .type = CLK_TYPE_PERIPHERAL,
66};
67static struct clk usart0_clk = {
68 .name = "usart0_clk",
69 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
70 .type = CLK_TYPE_PERIPHERAL,
71};
72static struct clk usart1_clk = {
73 .name = "usart1_clk",
74 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
75 .type = CLK_TYPE_PERIPHERAL,
76};
77static struct clk usart2_clk = {
78 .name = "usart2_clk",
79 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
80 .type = CLK_TYPE_PERIPHERAL,
81};
82static struct clk usart3_clk = {
83 .name = "usart3_clk",
84 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
85 .type = CLK_TYPE_PERIPHERAL,
86};
87static struct clk mmc_clk = {
88 .name = "mci_clk",
89 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
90 .type = CLK_TYPE_PERIPHERAL,
91};
92static struct clk twi0_clk = {
93 .name = "twi0_clk",
94 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
95 .type = CLK_TYPE_PERIPHERAL,
96};
97static struct clk twi1_clk = {
98 .name = "twi1_clk",
99 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
100 .type = CLK_TYPE_PERIPHERAL,
101};
102static struct clk spi_clk = {
103 .name = "spi_clk",
104 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
105 .type = CLK_TYPE_PERIPHERAL,
106};
107static struct clk ssc0_clk = {
108 .name = "ssc0_clk",
109 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
110 .type = CLK_TYPE_PERIPHERAL,
111};
112static struct clk ssc1_clk = {
113 .name = "ssc1_clk",
114 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
115 .type = CLK_TYPE_PERIPHERAL,
116};
117static struct clk tc0_clk = {
118 .name = "tc0_clk",
119 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
120 .type = CLK_TYPE_PERIPHERAL,
121};
122static struct clk tc1_clk = {
123 .name = "tc1_clk",
124 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
125 .type = CLK_TYPE_PERIPHERAL,
126};
127static struct clk tc2_clk = {
128 .name = "tc2_clk",
129 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
130 .type = CLK_TYPE_PERIPHERAL,
131};
132static struct clk pwmc_clk = {
133 .name = "pwmc_clk",
134 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
135 .type = CLK_TYPE_PERIPHERAL,
136};
137static struct clk tsc_clk = {
138 .name = "tsc_clk",
139 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
140 .type = CLK_TYPE_PERIPHERAL,
141};
142static struct clk dma_clk = {
143 .name = "dma_clk",
144 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
145 .type = CLK_TYPE_PERIPHERAL,
146};
147static struct clk udphs_clk = {
148 .name = "udphs_clk",
149 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
150 .type = CLK_TYPE_PERIPHERAL,
151};
152static struct clk lcdc_clk = {
153 .name = "lcdc_clk",
154 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
155 .type = CLK_TYPE_PERIPHERAL,
156};
157static struct clk ac97_clk = {
158 .name = "ac97_clk",
159 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
160 .type = CLK_TYPE_PERIPHERAL,
161};
162
163static struct clk *periph_clocks[] __initdata = {
164 &pioA_clk,
165 &pioB_clk,
166 &pioC_clk,
167 &pioD_clk,
168 &usart0_clk,
169 &usart1_clk,
170 &usart2_clk,
171 &usart3_clk,
172 &mmc_clk,
173 &twi0_clk,
174 &twi1_clk,
175 &spi_clk,
176 &ssc0_clk,
177 &ssc1_clk,
178 &tc0_clk,
179 &tc1_clk,
180 &tc2_clk,
181 &pwmc_clk,
182 &tsc_clk,
183 &dma_clk,
184 &udphs_clk,
185 &lcdc_clk,
186 &ac97_clk,
187 // irq0
188};
189
190/*
191 * The two programmable clocks.
192 * You must configure pin multiplexing to bring these signals out.
193 */
194static struct clk pck0 = {
195 .name = "pck0",
196 .pmc_mask = AT91_PMC_PCK0,
197 .type = CLK_TYPE_PROGRAMMABLE,
198 .id = 0,
199};
200static struct clk pck1 = {
201 .name = "pck1",
202 .pmc_mask = AT91_PMC_PCK1,
203 .type = CLK_TYPE_PROGRAMMABLE,
204 .id = 1,
205};
206
207static void __init at91sam9rl_register_clocks(void)
208{
209 int i;
210
211 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
212 clk_register(periph_clocks[i]);
213
214 clk_register(&pck0);
215 clk_register(&pck1);
216}
217
218/* --------------------------------------------------------------------
219 * GPIO
220 * -------------------------------------------------------------------- */
221
222static struct at91_gpio_bank at91sam9rl_gpio[] = {
223 {
224 .id = AT91SAM9RL_ID_PIOA,
225 .offset = AT91_PIOA,
226 .clock = &pioA_clk,
227 }, {
228 .id = AT91SAM9RL_ID_PIOB,
229 .offset = AT91_PIOB,
230 .clock = &pioB_clk,
231 }, {
232 .id = AT91SAM9RL_ID_PIOC,
233 .offset = AT91_PIOC,
234 .clock = &pioC_clk,
235 }, {
236 .id = AT91SAM9RL_ID_PIOD,
237 .offset = AT91_PIOD,
238 .clock = &pioD_clk,
239 }
240};
241
242static void at91sam9rl_reset(void)
243{
244 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
245}
246
247
248/* --------------------------------------------------------------------
249 * AT91SAM9RL processor initialization
250 * -------------------------------------------------------------------- */
251
252void __init at91sam9rl_initialize(unsigned long main_clock)
253{
254 unsigned long cidr, sram_size;
255
256 /* Map peripherals */
257 iotable_init(at91sam9rl_io_desc, ARRAY_SIZE(at91sam9rl_io_desc));
258
259 cidr = at91_sys_read(AT91_DBGU_CIDR);
260
261 switch (cidr & AT91_CIDR_SRAMSIZ) {
262 case AT91_CIDR_SRAMSIZ_32K:
263 sram_size = 2 * SZ_16K;
264 break;
265 case AT91_CIDR_SRAMSIZ_16K:
266 default:
267 sram_size = SZ_16K;
268 }
269
270 at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
271 at91sam9rl_sram_desc->length = sram_size;
272
273 /* Map SRAM */
274 iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
275
276 at91_arch_reset = at91sam9rl_reset;
277 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
278
279 /* Init clock subsystem */
280 at91_clock_init(main_clock);
281
282 /* Register the processor-specific clocks */
283 at91sam9rl_register_clocks();
284
285 /* Register GPIO subsystem */
286 at91_gpio_init(at91sam9rl_gpio, 4);
287}
288
289/* --------------------------------------------------------------------
290 * Interrupt initialization
291 * -------------------------------------------------------------------- */
292
293/*
294 * The default interrupt priority levels (0 = lowest, 7 = highest).
295 */
296static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
297 7, /* Advanced Interrupt Controller */
298 7, /* System Peripherals */
299 1, /* Parallel IO Controller A */
300 1, /* Parallel IO Controller B */
301 1, /* Parallel IO Controller C */
302 1, /* Parallel IO Controller D */
303 5, /* USART 0 */
304 5, /* USART 1 */
305 5, /* USART 2 */
306 5, /* USART 3 */
307 0, /* Multimedia Card Interface */
308 6, /* Two-Wire Interface 0 */
309 6, /* Two-Wire Interface 1 */
310 5, /* Serial Peripheral Interface */
311 4, /* Serial Synchronous Controller 0 */
312 4, /* Serial Synchronous Controller 1 */
313 0, /* Timer Counter 0 */
314 0, /* Timer Counter 1 */
315 0, /* Timer Counter 2 */
316 0,
317 0, /* Touch Screen Controller */
318 0, /* DMA Controller */
319 2, /* USB Device High speed port */
320 2, /* LCD Controller */
321 6, /* AC97 Controller */
322 0,
323 0,
324 0,
325 0,
326 0,
327 0,
328 0, /* Advanced Interrupt Controller */
329};
330
331void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS])
332{
333 if (!priority)
334 priority = at91sam9rl_default_irq_priority;
335
336 /* Initialize the AIC interrupt controller */
337 at91_aic_init(priority);
338
339 /* Enable GPIO interrupts */
340 at91_gpio_irq_setup();
341}
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
new file mode 100644
index 000000000000..cd7532bcd4e5
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -0,0 +1,630 @@
1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
6 * more details.
7 */
8
9#include <asm/mach/arch.h>
10#include <asm/mach/map.h>
11
12#include <linux/platform_device.h>
13#include <linux/fb.h>
14
15#include <video/atmel_lcdc.h>
16
17#include <asm/arch/board.h>
18#include <asm/arch/gpio.h>
19#include <asm/arch/at91sam9rl.h>
20#include <asm/arch/at91sam9rl_matrix.h>
21#include <asm/arch/at91sam926x_mc.h>
22
23#include "generic.h"
24
25
26/* --------------------------------------------------------------------
27 * MMC / SD
28 * -------------------------------------------------------------------- */
29
30#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
31static u64 mmc_dmamask = 0xffffffffUL;
32static struct at91_mmc_data mmc_data;
33
34static struct resource mmc_resources[] = {
35 [0] = {
36 .start = AT91SAM9RL_BASE_MCI,
37 .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
38 .flags = IORESOURCE_MEM,
39 },
40 [1] = {
41 .start = AT91SAM9RL_ID_MCI,
42 .end = AT91SAM9RL_ID_MCI,
43 .flags = IORESOURCE_IRQ,
44 },
45};
46
47static struct platform_device at91sam9rl_mmc_device = {
48 .name = "at91_mci",
49 .id = -1,
50 .dev = {
51 .dma_mask = &mmc_dmamask,
52 .coherent_dma_mask = 0xffffffff,
53 .platform_data = &mmc_data,
54 },
55 .resource = mmc_resources,
56 .num_resources = ARRAY_SIZE(mmc_resources),
57};
58
59void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
60{
61 if (!data)
62 return;
63
64 /* input/irq */
65 if (data->det_pin) {
66 at91_set_gpio_input(data->det_pin, 1);
67 at91_set_deglitch(data->det_pin, 1);
68 }
69 if (data->wp_pin)
70 at91_set_gpio_input(data->wp_pin, 1);
71 if (data->vcc_pin)
72 at91_set_gpio_output(data->vcc_pin, 0);
73
74 /* CLK */
75 at91_set_A_periph(AT91_PIN_PA2, 0);
76
77 /* CMD */
78 at91_set_A_periph(AT91_PIN_PA1, 1);
79
80 /* DAT0, maybe DAT1..DAT3 */
81 at91_set_A_periph(AT91_PIN_PA0, 1);
82 if (data->wire4) {
83 at91_set_A_periph(AT91_PIN_PA3, 1);
84 at91_set_A_periph(AT91_PIN_PA4, 1);
85 at91_set_A_periph(AT91_PIN_PA5, 1);
86 }
87
88 mmc_data = *data;
89 platform_device_register(&at91sam9rl_mmc_device);
90}
91#else
92void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
93#endif
94
95
96/* --------------------------------------------------------------------
97 * NAND / SmartMedia
98 * -------------------------------------------------------------------- */
99
100#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
101static struct at91_nand_data nand_data;
102
103#define NAND_BASE AT91_CHIPSELECT_3
104
105static struct resource nand_resources[] = {
106 {
107 .start = NAND_BASE,
108 .end = NAND_BASE + SZ_256M - 1,
109 .flags = IORESOURCE_MEM,
110 }
111};
112
113static struct platform_device at91_nand_device = {
114 .name = "at91_nand",
115 .id = -1,
116 .dev = {
117 .platform_data = &nand_data,
118 },
119 .resource = nand_resources,
120 .num_resources = ARRAY_SIZE(nand_resources),
121};
122
123void __init at91_add_device_nand(struct at91_nand_data *data)
124{
125 unsigned long csa;
126
127 if (!data)
128 return;
129
130 csa = at91_sys_read(AT91_MATRIX_EBICSA);
131 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
132
133 /* set the bus interface characteristics */
134 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
135 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
136
137 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
138 | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
139
140 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
141
142 at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
143
144 /* enable pin */
145 if (data->enable_pin)
146 at91_set_gpio_output(data->enable_pin, 1);
147
148 /* ready/busy pin */
149 if (data->rdy_pin)
150 at91_set_gpio_input(data->rdy_pin, 1);
151
152 /* card detect pin */
153 if (data->det_pin)
154 at91_set_gpio_input(data->det_pin, 1);
155
156 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
157 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
158
159 nand_data = *data;
160 platform_device_register(&at91_nand_device);
161}
162
163#else
164void __init at91_add_device_nand(struct at91_nand_data *data) {}
165#endif
166
167
168/* --------------------------------------------------------------------
169 * TWI (i2c)
170 * -------------------------------------------------------------------- */
171
172#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
173
174static struct resource twi_resources[] = {
175 [0] = {
176 .start = AT91SAM9RL_BASE_TWI0,
177 .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
178 .flags = IORESOURCE_MEM,
179 },
180 [1] = {
181 .start = AT91SAM9RL_ID_TWI0,
182 .end = AT91SAM9RL_ID_TWI0,
183 .flags = IORESOURCE_IRQ,
184 },
185};
186
187static struct platform_device at91sam9rl_twi_device = {
188 .name = "at91_i2c",
189 .id = -1,
190 .resource = twi_resources,
191 .num_resources = ARRAY_SIZE(twi_resources),
192};
193
194void __init at91_add_device_i2c(void)
195{
196 /* pins used for TWI interface */
197 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
198 at91_set_multi_drive(AT91_PIN_PA23, 1);
199
200 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
201 at91_set_multi_drive(AT91_PIN_PA24, 1);
202
203 platform_device_register(&at91sam9rl_twi_device);
204}
205#else
206void __init at91_add_device_i2c(void) {}
207#endif
208
209
210/* --------------------------------------------------------------------
211 * SPI
212 * -------------------------------------------------------------------- */
213
214#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
215static u64 spi_dmamask = 0xffffffffUL;
216
217static struct resource spi_resources[] = {
218 [0] = {
219 .start = AT91SAM9RL_BASE_SPI,
220 .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
221 .flags = IORESOURCE_MEM,
222 },
223 [1] = {
224 .start = AT91SAM9RL_ID_SPI,
225 .end = AT91SAM9RL_ID_SPI,
226 .flags = IORESOURCE_IRQ,
227 },
228};
229
230static struct platform_device at91sam9rl_spi_device = {
231 .name = "atmel_spi",
232 .id = 0,
233 .dev = {
234 .dma_mask = &spi_dmamask,
235 .coherent_dma_mask = 0xffffffff,
236 },
237 .resource = spi_resources,
238 .num_resources = ARRAY_SIZE(spi_resources),
239};
240
241static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
242
243
244void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
245{
246 int i;
247 unsigned long cs_pin;
248
249 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
250 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
251 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
252
253 /* Enable SPI chip-selects */
254 for (i = 0; i < nr_devices; i++) {
255 if (devices[i].controller_data)
256 cs_pin = (unsigned long) devices[i].controller_data;
257 else
258 cs_pin = spi_standard_cs[devices[i].chip_select];
259
260 /* enable chip-select pin */
261 at91_set_gpio_output(cs_pin, 1);
262
263 /* pass chip-select pin to driver */
264 devices[i].controller_data = (void *) cs_pin;
265 }
266
267 spi_register_board_info(devices, nr_devices);
268 platform_device_register(&at91sam9rl_spi_device);
269}
270#else
271void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
272#endif
273
274
275/* --------------------------------------------------------------------
276 * LCD Controller
277 * -------------------------------------------------------------------- */
278
279#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
280static u64 lcdc_dmamask = 0xffffffffUL;
281static struct atmel_lcdfb_info lcdc_data;
282
283static struct resource lcdc_resources[] = {
284 [0] = {
285 .start = AT91SAM9RL_LCDC_BASE,
286 .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
287 .flags = IORESOURCE_MEM,
288 },
289 [1] = {
290 .start = AT91SAM9RL_ID_LCDC,
291 .end = AT91SAM9RL_ID_LCDC,
292 .flags = IORESOURCE_IRQ,
293 },
294#if defined(CONFIG_FB_INTSRAM)
295 [2] = {
296 .start = AT91SAM9RL_SRAM_BASE,
297 .end = AT91SAM9RL_SRAM_BASE + AT91SAM9RL_SRAM_SIZE - 1,
298 .flags = IORESOURCE_MEM,
299 },
300#endif
301};
302
303static struct platform_device at91_lcdc_device = {
304 .name = "atmel_lcdfb",
305 .id = 0,
306 .dev = {
307 .dma_mask = &lcdc_dmamask,
308 .coherent_dma_mask = 0xffffffff,
309 .platform_data = &lcdc_data,
310 },
311 .resource = lcdc_resources,
312 .num_resources = ARRAY_SIZE(lcdc_resources),
313};
314
315void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
316{
317 if (!data) {
318 return;
319 }
320
321 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
322 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
323 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
324 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
325 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
326 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
327 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
328 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
329 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
330 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
331 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
332 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
333 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
334 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
335 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
336 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
337 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
338 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
339 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
340 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
341 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
342
343 lcdc_data = *data;
344 platform_device_register(&at91_lcdc_device);
345}
346#else
347void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
348#endif
349
350
351/* --------------------------------------------------------------------
352 * LEDs
353 * -------------------------------------------------------------------- */
354
355#if defined(CONFIG_LEDS)
356u8 at91_leds_cpu;
357u8 at91_leds_timer;
358
359void __init at91_init_leds(u8 cpu_led, u8 timer_led)
360{
361 /* Enable GPIO to access the LEDs */
362 at91_set_gpio_output(cpu_led, 1);
363 at91_set_gpio_output(timer_led, 1);
364
365 at91_leds_cpu = cpu_led;
366 at91_leds_timer = timer_led;
367}
368#else
369void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
370#endif
371
372
373/* --------------------------------------------------------------------
374 * UART
375 * -------------------------------------------------------------------- */
376
377#if defined(CONFIG_SERIAL_ATMEL)
378static struct resource dbgu_resources[] = {
379 [0] = {
380 .start = AT91_VA_BASE_SYS + AT91_DBGU,
381 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
382 .flags = IORESOURCE_MEM,
383 },
384 [1] = {
385 .start = AT91_ID_SYS,
386 .end = AT91_ID_SYS,
387 .flags = IORESOURCE_IRQ,
388 },
389};
390
391static struct atmel_uart_data dbgu_data = {
392 .use_dma_tx = 0,
393 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
394 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
395};
396
397static struct platform_device at91sam9rl_dbgu_device = {
398 .name = "atmel_usart",
399 .id = 0,
400 .dev = {
401 .platform_data = &dbgu_data,
402 .coherent_dma_mask = 0xffffffff,
403 },
404 .resource = dbgu_resources,
405 .num_resources = ARRAY_SIZE(dbgu_resources),
406};
407
408static inline void configure_dbgu_pins(void)
409{
410 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
411 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
412}
413
414static struct resource uart0_resources[] = {
415 [0] = {
416 .start = AT91SAM9RL_BASE_US0,
417 .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
418 .flags = IORESOURCE_MEM,
419 },
420 [1] = {
421 .start = AT91SAM9RL_ID_US0,
422 .end = AT91SAM9RL_ID_US0,
423 .flags = IORESOURCE_IRQ,
424 },
425};
426
427static struct atmel_uart_data uart0_data = {
428 .use_dma_tx = 1,
429 .use_dma_rx = 1,
430};
431
432static struct platform_device at91sam9rl_uart0_device = {
433 .name = "atmel_usart",
434 .id = 1,
435 .dev = {
436 .platform_data = &uart0_data,
437 .coherent_dma_mask = 0xffffffff,
438 },
439 .resource = uart0_resources,
440 .num_resources = ARRAY_SIZE(uart0_resources),
441};
442
443static inline void configure_usart0_pins(void)
444{
445 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
446 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
447 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
448 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
449}
450
451static struct resource uart1_resources[] = {
452 [0] = {
453 .start = AT91SAM9RL_BASE_US1,
454 .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
455 .flags = IORESOURCE_MEM,
456 },
457 [1] = {
458 .start = AT91SAM9RL_ID_US1,
459 .end = AT91SAM9RL_ID_US1,
460 .flags = IORESOURCE_IRQ,
461 },
462};
463
464static struct atmel_uart_data uart1_data = {
465 .use_dma_tx = 1,
466 .use_dma_rx = 1,
467};
468
469static struct platform_device at91sam9rl_uart1_device = {
470 .name = "atmel_usart",
471 .id = 2,
472 .dev = {
473 .platform_data = &uart1_data,
474 .coherent_dma_mask = 0xffffffff,
475 },
476 .resource = uart1_resources,
477 .num_resources = ARRAY_SIZE(uart1_resources),
478};
479
480static inline void configure_usart1_pins(void)
481{
482 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
483 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
484}
485
486static struct resource uart2_resources[] = {
487 [0] = {
488 .start = AT91SAM9RL_BASE_US2,
489 .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
490 .flags = IORESOURCE_MEM,
491 },
492 [1] = {
493 .start = AT91SAM9RL_ID_US2,
494 .end = AT91SAM9RL_ID_US2,
495 .flags = IORESOURCE_IRQ,
496 },
497};
498
499static struct atmel_uart_data uart2_data = {
500 .use_dma_tx = 1,
501 .use_dma_rx = 1,
502};
503
504static struct platform_device at91sam9rl_uart2_device = {
505 .name = "atmel_usart",
506 .id = 3,
507 .dev = {
508 .platform_data = &uart2_data,
509 .coherent_dma_mask = 0xffffffff,
510 },
511 .resource = uart2_resources,
512 .num_resources = ARRAY_SIZE(uart2_resources),
513};
514
515static inline void configure_usart2_pins(void)
516{
517 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
518 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
519}
520
521static struct resource uart3_resources[] = {
522 [0] = {
523 .start = AT91SAM9RL_BASE_US3,
524 .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
525 .flags = IORESOURCE_MEM,
526 },
527 [1] = {
528 .start = AT91SAM9RL_ID_US3,
529 .end = AT91SAM9RL_ID_US3,
530 .flags = IORESOURCE_IRQ,
531 },
532};
533
534static struct atmel_uart_data uart3_data = {
535 .use_dma_tx = 1,
536 .use_dma_rx = 1,
537};
538
539static struct platform_device at91sam9rl_uart3_device = {
540 .name = "atmel_usart",
541 .id = 4,
542 .dev = {
543 .platform_data = &uart3_data,
544 .coherent_dma_mask = 0xffffffff,
545 },
546 .resource = uart3_resources,
547 .num_resources = ARRAY_SIZE(uart3_resources),
548};
549
550static inline void configure_usart3_pins(void)
551{
552 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
553 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
554}
555
556struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
557struct platform_device *atmel_default_console_device; /* the serial console device */
558
559void __init at91_init_serial(struct at91_uart_config *config)
560{
561 int i;
562
563 /* Fill in list of supported UARTs */
564 for (i = 0; i < config->nr_tty; i++) {
565 switch (config->tty_map[i]) {
566 case 0:
567 configure_usart0_pins();
568 at91_uarts[i] = &at91sam9rl_uart0_device;
569 at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device.dev, "usart");
570 break;
571 case 1:
572 configure_usart1_pins();
573 at91_uarts[i] = &at91sam9rl_uart1_device;
574 at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device.dev, "usart");
575 break;
576 case 2:
577 configure_usart2_pins();
578 at91_uarts[i] = &at91sam9rl_uart2_device;
579 at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device.dev, "usart");
580 break;
581 case 3:
582 configure_usart3_pins();
583 at91_uarts[i] = &at91sam9rl_uart3_device;
584 at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device.dev, "usart");
585 break;
586 case 4:
587 configure_dbgu_pins();
588 at91_uarts[i] = &at91sam9rl_dbgu_device;
589 at91_clock_associate("mck", &at91sam9rl_dbgu_device.dev, "usart");
590 break;
591 default:
592 continue;
593 }
594 at91_uarts[i]->id = i; /* update ID number to mapped ID */
595 }
596
597 /* Set serial console device */
598 if (config->console_tty < ATMEL_MAX_UART)
599 atmel_default_console_device = at91_uarts[config->console_tty];
600 if (!atmel_default_console_device)
601 printk(KERN_INFO "AT91: No default serial console defined.\n");
602}
603
604void __init at91_add_device_serial(void)
605{
606 int i;
607
608 for (i = 0; i < ATMEL_MAX_UART; i++) {
609 if (at91_uarts[i])
610 platform_device_register(at91_uarts[i]);
611 }
612}
613#else
614void __init at91_init_serial(struct at91_uart_config *config) {}
615void __init at91_add_device_serial(void) {}
616#endif
617
618
619/* -------------------------------------------------------------------- */
620
621/*
622 * These devices are always present and don't need any board-specific
623 * setup.
624 */
625static int __init at91_add_standard_devices(void)
626{
627 return 0;
628}
629
630arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index bcf71536cc6d..1f0c8a400b3a 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -60,6 +60,9 @@ static void __init ek_map_io(void)
60 /* Initialize processor: 18.432 MHz crystal */ 60 /* Initialize processor: 18.432 MHz crystal */
61 at91sam9261_initialize(18432000); 61 at91sam9261_initialize(18432000);
62 62
63 /* Setup the LEDs */
64 at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
65
63 /* Setup the serial ports and console */ 66 /* Setup the serial ports and console */
64 at91_init_serial(&ek_uart_config); 67 at91_init_serial(&ek_uart_config);
65} 68}
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
new file mode 100644
index 000000000000..30c79aca84d4
--- /dev/null
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -0,0 +1,204 @@
1/*
2 * Copyright (C) 2005 SAN People
3 * Copyright (C) 2007 Atmel Corporation
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive for
7 * more details.
8 */
9
10#include <linux/types.h>
11#include <linux/init.h>
12#include <linux/mm.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/spi/spi.h>
16#include <linux/fb.h>
17#include <linux/clk.h>
18
19#include <video/atmel_lcdc.h>
20
21#include <asm/hardware.h>
22#include <asm/setup.h>
23#include <asm/mach-types.h>
24#include <asm/irq.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <asm/arch/board.h>
31#include <asm/arch/gpio.h>
32#include <asm/arch/at91sam926x_mc.h>
33
34#include "generic.h"
35
36
37/*
38 * Serial port configuration.
39 * 0 .. 3 = USART0 .. USART3
40 * 4 = DBGU
41 */
42static struct at91_uart_config __initdata ek_uart_config = {
43 .console_tty = 0, /* ttyS0 */
44 .nr_tty = 2,
45 .tty_map = { 4, 0, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
46};
47
48static void __init ek_map_io(void)
49{
50 /* Initialize processor: 12.000 MHz crystal */
51 at91sam9rl_initialize(12000000);
52
53 /* Setup the serial ports and console */
54 at91_init_serial(&ek_uart_config);
55}
56
57static void __init ek_init_irq(void)
58{
59 at91sam9rl_init_interrupts(NULL);
60}
61
62
63/*
64 * MCI (SD/MMC)
65 */
66static struct at91_mmc_data __initdata ek_mmc_data = {
67 .wire4 = 1,
68 .det_pin = AT91_PIN_PA15,
69// .wp_pin = ... not connected
70// .vcc_pin = ... not connected
71};
72
73
74/*
75 * NAND flash
76 */
77static struct mtd_partition __initdata ek_nand_partition[] = {
78 {
79 .name = "Partition 1",
80 .offset = 0,
81 .size = 256 * 1024,
82 },
83 {
84 .name = "Partition 2",
85 .offset = 256 * 1024 ,
86 .size = MTDPART_SIZ_FULL,
87 },
88};
89
90static struct mtd_partition *nand_partitions(int size, int *num_partitions)
91{
92 *num_partitions = ARRAY_SIZE(ek_nand_partition);
93 return ek_nand_partition;
94}
95
96static struct at91_nand_data __initdata ek_nand_data = {
97 .ale = 21,
98 .cle = 22,
99// .det_pin = ... not connected
100 .rdy_pin = AT91_PIN_PD17,
101 .enable_pin = AT91_PIN_PB6,
102 .partition_info = nand_partitions,
103 .bus_width_16 = 0,
104};
105
106
107/*
108 * SPI devices
109 */
110static struct spi_board_info ek_spi_devices[] = {
111 { /* DataFlash chip */
112 .modalias = "mtd_dataflash",
113 .chip_select = 0,
114 .max_speed_hz = 15 * 1000 * 1000,
115 .bus_num = 0,
116 },
117};
118
119
120/*
121 * LCD Controller
122 */
123#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
124static struct fb_videomode at91_tft_vga_modes[] = {
125 {
126 .name = "TX09D50VM1CCA @ 60",
127 .refresh = 60,
128 .xres = 240, .yres = 320,
129 .pixclock = KHZ2PICOS(4965),
130
131 .left_margin = 1, .right_margin = 33,
132 .upper_margin = 1, .lower_margin = 0,
133 .hsync_len = 5, .vsync_len = 1,
134
135 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
136 .vmode = FB_VMODE_NONINTERLACED,
137 },
138};
139
140static struct fb_monspecs at91fb_default_monspecs = {
141 .manufacturer = "HIT",
142 .monitor = "TX09D50VM1CCA",
143
144 .modedb = at91_tft_vga_modes,
145 .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
146 .hfmin = 15000,
147 .hfmax = 64000,
148 .vfmin = 50,
149 .vfmax = 150,
150};
151
152#define AT91SAM9RL_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
153 | ATMEL_LCDC_DISTYPE_TFT \
154 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
155
156static void at91_lcdc_power_control(int on)
157{
158 if (on)
159 at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */
160 else
161 at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */
162}
163
164/* Driver datas */
165static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
166 .default_bpp = 16,
167 .default_dmacon = ATMEL_LCDC_DMAEN,
168 .default_lcdcon2 = AT91SAM9RL_DEFAULT_LCDCON2,
169 .default_monspecs = &at91fb_default_monspecs,
170 .atmel_lcdfb_power_control = at91_lcdc_power_control,
171 .guard_time = 1,
172};
173
174#else
175static struct atmel_lcdfb_info __initdata ek_lcdc_data;
176#endif
177
178
179static void __init ek_board_init(void)
180{
181 /* Serial */
182 at91_add_device_serial();
183 /* I2C */
184 at91_add_device_i2c();
185 /* NAND */
186 at91_add_device_nand(&ek_nand_data);
187 /* SPI */
188 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
189 /* MMC */
190 at91_add_device_mmc(0, &ek_mmc_data);
191 /* LCD Controller */
192 at91_add_device_lcdc(&ek_lcdc_data);
193}
194
195MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
196 /* Maintainer: Atmel */
197 .phys_io = AT91_BASE_SYS,
198 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
199 .boot_params = AT91_SDRAM_BASE + 0x100,
200 .timer = &at91sam926x_timer,
201 .map_io = ek_map_io,
202 .init_irq = ek_init_irq,
203 .init_machine = ek_board_init,
204MACHINE_END
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index bda26221c522..68ed71a3e6c6 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -13,12 +13,14 @@ extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned shor
13extern void __init at91sam9260_initialize(unsigned long main_clock); 13extern void __init at91sam9260_initialize(unsigned long main_clock);
14extern void __init at91sam9261_initialize(unsigned long main_clock); 14extern void __init at91sam9261_initialize(unsigned long main_clock);
15extern void __init at91sam9263_initialize(unsigned long main_clock); 15extern void __init at91sam9263_initialize(unsigned long main_clock);
16extern void __init at91sam9rl_initialize(unsigned long main_clock);
16 17
17 /* Interrupts */ 18 /* Interrupts */
18extern void __init at91rm9200_init_interrupts(unsigned int priority[]); 19extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
19extern void __init at91sam9260_init_interrupts(unsigned int priority[]); 20extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
20extern void __init at91sam9261_init_interrupts(unsigned int priority[]); 21extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
21extern void __init at91sam9263_init_interrupts(unsigned int priority[]); 22extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
23extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
22extern void __init at91_aic_init(unsigned int priority[]); 24extern void __init at91_aic_init(unsigned int priority[]);
23 25
24 /* Timer */ 26 /* Timer */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 14:07:52 -0500