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-rw-r--r--arch/arm/mach-at91/sama5d3.c346
1 files changed, 0 insertions, 346 deletions
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index f3313b9d084a..3d775d08de08 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -21,349 +21,6 @@
21#include "generic.h" 21#include "generic.h"
22#include "sam9_smc.h" 22#include "sam9_smc.h"
23 23
24#if defined(CONFIG_OLD_CLK_AT91)
25#include "clock.h"
26/* --------------------------------------------------------------------
27 * Clocks
28 * -------------------------------------------------------------------- */
29
30/*
31 * The peripheral clocks.
32 */
33
34static struct clk pioA_clk = {
35 .name = "pioA_clk",
36 .pid = SAMA5D3_ID_PIOA,
37 .type = CLK_TYPE_PERIPHERAL,
38};
39static struct clk pioB_clk = {
40 .name = "pioB_clk",
41 .pid = SAMA5D3_ID_PIOB,
42 .type = CLK_TYPE_PERIPHERAL,
43};
44static struct clk pioC_clk = {
45 .name = "pioC_clk",
46 .pid = SAMA5D3_ID_PIOC,
47 .type = CLK_TYPE_PERIPHERAL,
48};
49static struct clk pioD_clk = {
50 .name = "pioD_clk",
51 .pid = SAMA5D3_ID_PIOD,
52 .type = CLK_TYPE_PERIPHERAL,
53};
54static struct clk pioE_clk = {
55 .name = "pioE_clk",
56 .pid = SAMA5D3_ID_PIOE,
57 .type = CLK_TYPE_PERIPHERAL,
58};
59static struct clk usart0_clk = {
60 .name = "usart0_clk",
61 .pid = SAMA5D3_ID_USART0,
62 .type = CLK_TYPE_PERIPHERAL,
63 .div = AT91_PMC_PCR_DIV2,
64};
65static struct clk usart1_clk = {
66 .name = "usart1_clk",
67 .pid = SAMA5D3_ID_USART1,
68 .type = CLK_TYPE_PERIPHERAL,
69 .div = AT91_PMC_PCR_DIV2,
70};
71static struct clk usart2_clk = {
72 .name = "usart2_clk",
73 .pid = SAMA5D3_ID_USART2,
74 .type = CLK_TYPE_PERIPHERAL,
75 .div = AT91_PMC_PCR_DIV2,
76};
77static struct clk usart3_clk = {
78 .name = "usart3_clk",
79 .pid = SAMA5D3_ID_USART3,
80 .type = CLK_TYPE_PERIPHERAL,
81 .div = AT91_PMC_PCR_DIV2,
82};
83static struct clk uart0_clk = {
84 .name = "uart0_clk",
85 .pid = SAMA5D3_ID_UART0,
86 .type = CLK_TYPE_PERIPHERAL,
87 .div = AT91_PMC_PCR_DIV2,
88};
89static struct clk uart1_clk = {
90 .name = "uart1_clk",
91 .pid = SAMA5D3_ID_UART1,
92 .type = CLK_TYPE_PERIPHERAL,
93 .div = AT91_PMC_PCR_DIV2,
94};
95static struct clk twi0_clk = {
96 .name = "twi0_clk",
97 .pid = SAMA5D3_ID_TWI0,
98 .type = CLK_TYPE_PERIPHERAL,
99 .div = AT91_PMC_PCR_DIV2,
100};
101static struct clk twi1_clk = {
102 .name = "twi1_clk",
103 .pid = SAMA5D3_ID_TWI1,
104 .type = CLK_TYPE_PERIPHERAL,
105 .div = AT91_PMC_PCR_DIV2,
106};
107static struct clk twi2_clk = {
108 .name = "twi2_clk",
109 .pid = SAMA5D3_ID_TWI2,
110 .type = CLK_TYPE_PERIPHERAL,
111 .div = AT91_PMC_PCR_DIV2,
112};
113static struct clk mmc0_clk = {
114 .name = "mci0_clk",
115 .pid = SAMA5D3_ID_HSMCI0,
116 .type = CLK_TYPE_PERIPHERAL,
117};
118static struct clk mmc1_clk = {
119 .name = "mci1_clk",
120 .pid = SAMA5D3_ID_HSMCI1,
121 .type = CLK_TYPE_PERIPHERAL,
122};
123static struct clk mmc2_clk = {
124 .name = "mci2_clk",
125 .pid = SAMA5D3_ID_HSMCI2,
126 .type = CLK_TYPE_PERIPHERAL,
127};
128static struct clk spi0_clk = {
129 .name = "spi0_clk",
130 .pid = SAMA5D3_ID_SPI0,
131 .type = CLK_TYPE_PERIPHERAL,
132};
133static struct clk spi1_clk = {
134 .name = "spi1_clk",
135 .pid = SAMA5D3_ID_SPI1,
136 .type = CLK_TYPE_PERIPHERAL,
137};
138static struct clk tcb0_clk = {
139 .name = "tcb0_clk",
140 .pid = SAMA5D3_ID_TC0,
141 .type = CLK_TYPE_PERIPHERAL,
142 .div = AT91_PMC_PCR_DIV2,
143};
144static struct clk tcb1_clk = {
145 .name = "tcb1_clk",
146 .pid = SAMA5D3_ID_TC1,
147 .type = CLK_TYPE_PERIPHERAL,
148 .div = AT91_PMC_PCR_DIV2,
149};
150static struct clk adc_clk = {
151 .name = "adc_clk",
152 .pid = SAMA5D3_ID_ADC,
153 .type = CLK_TYPE_PERIPHERAL,
154 .div = AT91_PMC_PCR_DIV2,
155};
156static struct clk adc_op_clk = {
157 .name = "adc_op_clk",
158 .type = CLK_TYPE_PERIPHERAL,
159 .rate_hz = 5000000,
160};
161static struct clk dma0_clk = {
162 .name = "dma0_clk",
163 .pid = SAMA5D3_ID_DMA0,
164 .type = CLK_TYPE_PERIPHERAL,
165};
166static struct clk dma1_clk = {
167 .name = "dma1_clk",
168 .pid = SAMA5D3_ID_DMA1,
169 .type = CLK_TYPE_PERIPHERAL,
170};
171static struct clk uhphs_clk = {
172 .name = "uhphs",
173 .pid = SAMA5D3_ID_UHPHS,
174 .type = CLK_TYPE_PERIPHERAL,
175};
176static struct clk udphs_clk = {
177 .name = "udphs_clk",
178 .pid = SAMA5D3_ID_UDPHS,
179 .type = CLK_TYPE_PERIPHERAL,
180};
181/* gmac only for sama5d33, sama5d34, sama5d35 */
182static struct clk macb0_clk = {
183 .name = "macb0_clk",
184 .pid = SAMA5D3_ID_GMAC,
185 .type = CLK_TYPE_PERIPHERAL,
186};
187/* emac only for sama5d31, sama5d35 */
188static struct clk macb1_clk = {
189 .name = "macb1_clk",
190 .pid = SAMA5D3_ID_EMAC,
191 .type = CLK_TYPE_PERIPHERAL,
192};
193/* lcd only for sama5d31, sama5d33, sama5d34 */
194static struct clk lcdc_clk = {
195 .name = "lcdc_clk",
196 .pid = SAMA5D3_ID_LCDC,
197 .type = CLK_TYPE_PERIPHERAL,
198};
199/* isi only for sama5d33, sama5d35 */
200static struct clk isi_clk = {
201 .name = "isi_clk",
202 .pid = SAMA5D3_ID_ISI,
203 .type = CLK_TYPE_PERIPHERAL,
204};
205static struct clk can0_clk = {
206 .name = "can0_clk",
207 .pid = SAMA5D3_ID_CAN0,
208 .type = CLK_TYPE_PERIPHERAL,
209 .div = AT91_PMC_PCR_DIV2,
210};
211static struct clk can1_clk = {
212 .name = "can1_clk",
213 .pid = SAMA5D3_ID_CAN1,
214 .type = CLK_TYPE_PERIPHERAL,
215 .div = AT91_PMC_PCR_DIV2,
216};
217static struct clk ssc0_clk = {
218 .name = "ssc0_clk",
219 .pid = SAMA5D3_ID_SSC0,
220 .type = CLK_TYPE_PERIPHERAL,
221 .div = AT91_PMC_PCR_DIV2,
222};
223static struct clk ssc1_clk = {
224 .name = "ssc1_clk",
225 .pid = SAMA5D3_ID_SSC1,
226 .type = CLK_TYPE_PERIPHERAL,
227 .div = AT91_PMC_PCR_DIV2,
228};
229static struct clk sha_clk = {
230 .name = "sha_clk",
231 .pid = SAMA5D3_ID_SHA,
232 .type = CLK_TYPE_PERIPHERAL,
233 .div = AT91_PMC_PCR_DIV8,
234};
235static struct clk aes_clk = {
236 .name = "aes_clk",
237 .pid = SAMA5D3_ID_AES,
238 .type = CLK_TYPE_PERIPHERAL,
239};
240static struct clk tdes_clk = {
241 .name = "tdes_clk",
242 .pid = SAMA5D3_ID_TDES,
243 .type = CLK_TYPE_PERIPHERAL,
244};
245
246static struct clk *periph_clocks[] __initdata = {
247 &pioA_clk,
248 &pioB_clk,
249 &pioC_clk,
250 &pioD_clk,
251 &pioE_clk,
252 &usart0_clk,
253 &usart1_clk,
254 &usart2_clk,
255 &usart3_clk,
256 &uart0_clk,
257 &uart1_clk,
258 &twi0_clk,
259 &twi1_clk,
260 &twi2_clk,
261 &mmc0_clk,
262 &mmc1_clk,
263 &mmc2_clk,
264 &spi0_clk,
265 &spi1_clk,
266 &tcb0_clk,
267 &tcb1_clk,
268 &adc_clk,
269 &adc_op_clk,
270 &dma0_clk,
271 &dma1_clk,
272 &uhphs_clk,
273 &udphs_clk,
274 &macb0_clk,
275 &macb1_clk,
276 &lcdc_clk,
277 &isi_clk,
278 &can0_clk,
279 &can1_clk,
280 &ssc0_clk,
281 &ssc1_clk,
282 &sha_clk,
283 &aes_clk,
284 &tdes_clk,
285};
286
287static struct clk pck0 = {
288 .name = "pck0",
289 .pmc_mask = AT91_PMC_PCK0,
290 .type = CLK_TYPE_PROGRAMMABLE,
291 .id = 0,
292};
293
294static struct clk pck1 = {
295 .name = "pck1",
296 .pmc_mask = AT91_PMC_PCK1,
297 .type = CLK_TYPE_PROGRAMMABLE,
298 .id = 1,
299};
300
301static struct clk pck2 = {
302 .name = "pck2",
303 .pmc_mask = AT91_PMC_PCK2,
304 .type = CLK_TYPE_PROGRAMMABLE,
305 .id = 2,
306};
307
308static struct clk_lookup periph_clocks_lookups[] = {
309 /* lookup table for DT entries */
310 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
311 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
312 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
313 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
314 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk),
315 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk),
316 CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk),
317 CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk),
318 CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk),
319 CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk),
320 CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk),
321 CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk),
322 CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk),
323 CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk),
324 CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk),
325 CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk),
326 CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk),
327 CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk),
328 CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk),
329 CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk),
330 CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk),
331 CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk),
332 CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk),
333 CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
334 CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
335 CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
336 CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
337 CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
338 CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk),
339 CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk),
340 CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk),
341 CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk),
342 CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk),
343 CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk),
344 CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk),
345 CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk),
346 CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk),
347 CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk),
348 CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk),
349};
350
351static void __init sama5d3_register_clocks(void)
352{
353 int i;
354
355 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
356 clk_register(periph_clocks[i]);
357
358 clkdev_add_table(periph_clocks_lookups,
359 ARRAY_SIZE(periph_clocks_lookups));
360
361 clk_register(&pck0);
362 clk_register(&pck1);
363 clk_register(&pck2);
364}
365#endif
366
367/* -------------------------------------------------------------------- 24/* --------------------------------------------------------------------
368 * AT91SAM9x5 processor initialization 25 * AT91SAM9x5 processor initialization
369 * -------------------------------------------------------------------- */ 26 * -------------------------------------------------------------------- */
@@ -380,8 +37,5 @@ static void __init sama5d3_initialize(void)
380 37
381AT91_SOC_START(sama5d3) 38AT91_SOC_START(sama5d3)
382 .map_io = sama5d3_map_io, 39 .map_io = sama5d3_map_io,
383#if defined(CONFIG_OLD_CLK_AT91)
384 .register_clocks = sama5d3_register_clocks,
385#endif
386 .init = sama5d3_initialize, 40 .init = sama5d3_initialize,
387AT91_SOC_END 41AT91_SOC_END
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 04:31:18 -0500