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-rw-r--r--arch/arm/mach-at91/pm.c15
1 files changed, 11 insertions, 4 deletions
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 615668986480..dafbacc25eb1 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -258,16 +258,23 @@ static int at91_pm_enter(suspend_state_t state)
258 * NOTE: the Wait-for-Interrupt instruction needs to be 258 * NOTE: the Wait-for-Interrupt instruction needs to be
259 * in icache so no SDRAM accesses are needed until the 259 * in icache so no SDRAM accesses are needed until the
260 * wakeup IRQ occurs and self-refresh is terminated. 260 * wakeup IRQ occurs and self-refresh is terminated.
261 * For ARM 926 based chips, this requirement is weaker
262 * as at91sam9 can access a RAM in self-refresh mode.
261 */ 263 */
262 asm("b 1f; .align 5; 1:"); 264 asm volatile ( "mov r0, #0\n\t"
263 asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */ 265 "b 1f\n\t"
266 ".align 5\n\t"
267 "1: mcr p15, 0, r0, c7, c10, 4\n\t"
268 : /* no output */
269 : /* no input */
270 : "r0");
264 saved_lpr = sdram_selfrefresh_enable(); 271 saved_lpr = sdram_selfrefresh_enable();
265 asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */ 272 wait_for_interrupt_enable();
266 sdram_selfrefresh_disable(saved_lpr); 273 sdram_selfrefresh_disable(saved_lpr);
267 break; 274 break;
268 275
269 case PM_SUSPEND_ON: 276 case PM_SUSPEND_ON:
270 asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */ 277 cpu_do_idle();
271 break; 278 break;
272 279
273 default: 280 default: