diff options
Diffstat (limited to 'arch/arm/mach-at91/irq.c')
-rw-r--r-- | arch/arm/mach-at91/irq.c | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c index 8e210262aeee..e0ca59171022 100644 --- a/arch/arm/mach-at91/irq.c +++ b/arch/arm/mach-at91/irq.c | |||
@@ -92,23 +92,21 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value) | |||
92 | 92 | ||
93 | void at91_irq_suspend(void) | 93 | void at91_irq_suspend(void) |
94 | { | 94 | { |
95 | int i = 0, bit; | 95 | int bit = -1; |
96 | 96 | ||
97 | if (has_aic5()) { | 97 | if (has_aic5()) { |
98 | /* disable enabled irqs */ | 98 | /* disable enabled irqs */ |
99 | while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) { | 99 | while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) { |
100 | at91_aic_write(AT91_AIC5_SSR, | 100 | at91_aic_write(AT91_AIC5_SSR, |
101 | bit & AT91_AIC5_INTSEL_MSK); | 101 | bit & AT91_AIC5_INTSEL_MSK); |
102 | at91_aic_write(AT91_AIC5_IDCR, 1); | 102 | at91_aic_write(AT91_AIC5_IDCR, 1); |
103 | i = bit; | ||
104 | } | 103 | } |
105 | /* enable wakeup irqs */ | 104 | /* enable wakeup irqs */ |
106 | i = 0; | 105 | bit = -1; |
107 | while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) { | 106 | while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) { |
108 | at91_aic_write(AT91_AIC5_SSR, | 107 | at91_aic_write(AT91_AIC5_SSR, |
109 | bit & AT91_AIC5_INTSEL_MSK); | 108 | bit & AT91_AIC5_INTSEL_MSK); |
110 | at91_aic_write(AT91_AIC5_IECR, 1); | 109 | at91_aic_write(AT91_AIC5_IECR, 1); |
111 | i = bit; | ||
112 | } | 110 | } |
113 | } else { | 111 | } else { |
114 | at91_aic_write(AT91_AIC_IDCR, *backups); | 112 | at91_aic_write(AT91_AIC_IDCR, *backups); |
@@ -118,23 +116,21 @@ void at91_irq_suspend(void) | |||
118 | 116 | ||
119 | void at91_irq_resume(void) | 117 | void at91_irq_resume(void) |
120 | { | 118 | { |
121 | int i = 0, bit; | 119 | int bit = -1; |
122 | 120 | ||
123 | if (has_aic5()) { | 121 | if (has_aic5()) { |
124 | /* disable wakeup irqs */ | 122 | /* disable wakeup irqs */ |
125 | while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) { | 123 | while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) { |
126 | at91_aic_write(AT91_AIC5_SSR, | 124 | at91_aic_write(AT91_AIC5_SSR, |
127 | bit & AT91_AIC5_INTSEL_MSK); | 125 | bit & AT91_AIC5_INTSEL_MSK); |
128 | at91_aic_write(AT91_AIC5_IDCR, 1); | 126 | at91_aic_write(AT91_AIC5_IDCR, 1); |
129 | i = bit; | ||
130 | } | 127 | } |
131 | /* enable irqs disabled for suspend */ | 128 | /* enable irqs disabled for suspend */ |
132 | i = 0; | 129 | bit = -1; |
133 | while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) { | 130 | while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) { |
134 | at91_aic_write(AT91_AIC5_SSR, | 131 | at91_aic_write(AT91_AIC5_SSR, |
135 | bit & AT91_AIC5_INTSEL_MSK); | 132 | bit & AT91_AIC5_INTSEL_MSK); |
136 | at91_aic_write(AT91_AIC5_IECR, 1); | 133 | at91_aic_write(AT91_AIC5_IECR, 1); |
137 | i = bit; | ||
138 | } | 134 | } |
139 | } else { | 135 | } else { |
140 | at91_aic_write(AT91_AIC_IDCR, *wakeups); | 136 | at91_aic_write(AT91_AIC_IDCR, *wakeups); |