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Diffstat (limited to 'arch/arm/mach-at91/include/mach/at572d940hf.h')
-rw-r--r--arch/arm/mach-at91/include/mach/at572d940hf.h123
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diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h
deleted file mode 100644
index be510cfc56be..000000000000
--- a/arch/arm/mach-at91/include/mach/at572d940hf.h
+++ /dev/null
@@ -1,123 +0,0 @@
1/*
2 * include/mach/at572d940hf.h
3 *
4 * Antonio R. Costa <costa.antonior@gmail.com>
5 * Copyright (C) 2008 Atmel
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#ifndef AT572D940HF_H
24#define AT572D940HF_H
25
26/*
27 * Peripheral identifiers/interrupts.
28 */
29#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
30#define AT91_ID_SYS 1 /* System Peripherals */
31#define AT572D940HF_ID_PIOA 2 /* Parallel IO Controller A */
32#define AT572D940HF_ID_PIOB 3 /* Parallel IO Controller B */
33#define AT572D940HF_ID_PIOC 4 /* Parallel IO Controller C */
34#define AT572D940HF_ID_EMAC 5 /* MACB ethernet controller */
35#define AT572D940HF_ID_US0 6 /* USART 0 */
36#define AT572D940HF_ID_US1 7 /* USART 1 */
37#define AT572D940HF_ID_US2 8 /* USART 2 */
38#define AT572D940HF_ID_MCI 9 /* Multimedia Card Interface */
39#define AT572D940HF_ID_UDP 10 /* USB Device Port */
40#define AT572D940HF_ID_TWI0 11 /* Two-Wire Interface 0 */
41#define AT572D940HF_ID_SPI0 12 /* Serial Peripheral Interface 0 */
42#define AT572D940HF_ID_SPI1 13 /* Serial Peripheral Interface 1 */
43#define AT572D940HF_ID_SSC0 14 /* Serial Synchronous Controller 0 */
44#define AT572D940HF_ID_SSC1 15 /* Serial Synchronous Controller 1 */
45#define AT572D940HF_ID_SSC2 16 /* Serial Synchronous Controller 2 */
46#define AT572D940HF_ID_TC0 17 /* Timer Counter 0 */
47#define AT572D940HF_ID_TC1 18 /* Timer Counter 1 */
48#define AT572D940HF_ID_TC2 19 /* Timer Counter 2 */
49#define AT572D940HF_ID_UHP 20 /* USB Host port */
50#define AT572D940HF_ID_SSC3 21 /* Serial Synchronous Controller 3 */
51#define AT572D940HF_ID_TWI1 22 /* Two-Wire Interface 1 */
52#define AT572D940HF_ID_CAN0 23 /* CAN Controller 0 */
53#define AT572D940HF_ID_CAN1 24 /* CAN Controller 1 */
54#define AT572D940HF_ID_MHALT 25 /* mAgicV HALT line */
55#define AT572D940HF_ID_MSIRQ0 26 /* mAgicV SIRQ0 line */
56#define AT572D940HF_ID_MEXC 27 /* mAgicV exception line */
57#define AT572D940HF_ID_MEDMA 28 /* mAgicV end of DMA line */
58#define AT572D940HF_ID_IRQ0 29 /* External Interrupt Source (IRQ0) */
59#define AT572D940HF_ID_IRQ1 30 /* External Interrupt Source (IRQ1) */
60#define AT572D940HF_ID_IRQ2 31 /* External Interrupt Source (IRQ2) */
61
62
63/*
64 * User Peripheral physical base addresses.
65 */
66#define AT572D940HF_BASE_TCB 0xfffa0000
67#define AT572D940HF_BASE_TC0 0xfffa0000
68#define AT572D940HF_BASE_TC1 0xfffa0040
69#define AT572D940HF_BASE_TC2 0xfffa0080
70#define AT572D940HF_BASE_UDP 0xfffa4000
71#define AT572D940HF_BASE_MCI 0xfffa8000
72#define AT572D940HF_BASE_TWI0 0xfffac000
73#define AT572D940HF_BASE_US0 0xfffb0000
74#define AT572D940HF_BASE_US1 0xfffb4000
75#define AT572D940HF_BASE_US2 0xfffb8000
76#define AT572D940HF_BASE_SSC0 0xfffbc000
77#define AT572D940HF_BASE_SSC1 0xfffc0000
78#define AT572D940HF_BASE_SSC2 0xfffc4000
79#define AT572D940HF_BASE_SPI0 0xfffc8000
80#define AT572D940HF_BASE_SPI1 0xfffcc000
81#define AT572D940HF_BASE_SSC3 0xfffd0000
82#define AT572D940HF_BASE_TWI1 0xfffd4000
83#define AT572D940HF_BASE_EMAC 0xfffd8000
84#define AT572D940HF_BASE_CAN0 0xfffdc000
85#define AT572D940HF_BASE_CAN1 0xfffe0000
86#define AT91_BASE_SYS 0xffffea00
87
88
89/*
90 * System Peripherals (offset from AT91_BASE_SYS)
91 */
92#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
93#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
94#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
95#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
96#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
97#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
98#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
99#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
100#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
101#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
102#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
103#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
104#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
105
106#define AT91_USART0 AT572D940HF_ID_US0
107#define AT91_USART1 AT572D940HF_ID_US1
108#define AT91_USART2 AT572D940HF_ID_US2
109
110
111/*
112 * Internal Memory.
113 */
114#define AT572D940HF_SRAM_BASE 0x00300000 /* Internal SRAM base address */
115#define AT572D940HF_SRAM_SIZE (48 * SZ_1K) /* Internal SRAM size (48Kb) */
116
117#define AT572D940HF_ROM_BASE 0x00400000 /* Internal ROM base address */
118#define AT572D940HF_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
119
120#define AT572D940HF_UHP_BASE 0x00500000 /* USB Host controller */
121
122
123#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 05:50:40 -0500