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Diffstat (limited to 'arch/arm/mach-at91/clock.c')
-rw-r--r--arch/arm/mach-at91/clock.c30
1 files changed, 23 insertions, 7 deletions
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index da841885d01c..6b2630a92f71 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -75,7 +75,7 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
75#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ 75#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
76 || cpu_is_at91sam9g45() \ 76 || cpu_is_at91sam9g45() \
77 || cpu_is_at91sam9x5() \ 77 || cpu_is_at91sam9x5() \
78 || cpu_is_at91sam9n12())) 78 || cpu_is_sama5d3()))
79 79
80#define cpu_has_upll() (cpu_is_at91sam9g45() \ 80#define cpu_has_upll() (cpu_is_at91sam9g45() \
81 || cpu_is_at91sam9x5() \ 81 || cpu_is_at91sam9x5() \
@@ -489,7 +489,7 @@ static int at91_clk_show(struct seq_file *s, void *unused)
489 seq_printf(s, "UCKR = %8x\n", uckr); 489 seq_printf(s, "UCKR = %8x\n", uckr);
490 } 490 }
491 seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR)); 491 seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
492 if (cpu_has_upll()) 492 if (cpu_has_upll() || cpu_is_at91sam9n12())
493 seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB)); 493 seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
494 seq_printf(s, "SR = %8x\n", sr); 494 seq_printf(s, "SR = %8x\n", sr);
495 495
@@ -614,6 +614,8 @@ static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
614{ 614{
615 if (pll == &pllb && (reg & AT91_PMC_USB96M)) 615 if (pll == &pllb && (reg & AT91_PMC_USB96M))
616 return freq / 2; 616 return freq / 2;
617 else if (pll == &utmi_clk || cpu_is_at91sam9n12())
618 return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8));
617 else 619 else
618 return freq; 620 return freq;
619} 621}
@@ -683,6 +685,8 @@ static struct clk *const standard_pmc_clocks[] __initconst = {
683/* PLLB generated USB full speed clock init */ 685/* PLLB generated USB full speed clock init */
684static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock) 686static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
685{ 687{
688 unsigned int reg;
689
686 /* 690 /*
687 * USB clock init: choose 48 MHz PLLB value, 691 * USB clock init: choose 48 MHz PLLB value,
688 * disable 48MHz clock during usb peripheral suspend. 692 * disable 48MHz clock during usb peripheral suspend.
@@ -691,22 +695,35 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
691 */ 695 */
692 uhpck.parent = &pllb; 696 uhpck.parent = &pllb;
693 697
694 at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; 698 reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2);
695 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); 699 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
696 if (cpu_is_at91rm9200()) { 700 if (cpu_is_at91rm9200()) {
701 reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
697 uhpck.pmc_mask = AT91RM9200_PMC_UHP; 702 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
698 udpck.pmc_mask = AT91RM9200_PMC_UDP; 703 udpck.pmc_mask = AT91RM9200_PMC_UDP;
699 at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); 704 at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
700 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || 705 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
701 cpu_is_at91sam9263() || cpu_is_at91sam9g20() || 706 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
702 cpu_is_at91sam9g10()) { 707 cpu_is_at91sam9g10()) {
708 reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
709 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
710 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
711 } else if (cpu_is_at91sam9n12()) {
712 /* Divider for USB clock is in USB clock register for 9n12 */
713 reg = AT91_PMC_USBS_PLLB;
714
715 /* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */
716 reg |= AT91_PMC_OHCIUSBDIV_2;
717 at91_pmc_write(AT91_PMC_USB, reg);
718
719 /* Still setup masks */
703 uhpck.pmc_mask = AT91SAM926x_PMC_UHP; 720 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
704 udpck.pmc_mask = AT91SAM926x_PMC_UDP; 721 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
705 } 722 }
706 at91_pmc_write(AT91_CKGR_PLLBR, 0); 723 at91_pmc_write(AT91_CKGR_PLLBR, 0);
707 724
708 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); 725 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
709 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); 726 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
710} 727}
711 728
712/* UPLL generated USB full speed clock init */ 729/* UPLL generated USB full speed clock init */
@@ -725,8 +742,7 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
725 /* Now set uhpck values */ 742 /* Now set uhpck values */
726 uhpck.parent = &utmi_clk; 743 uhpck.parent = &utmi_clk;
727 uhpck.pmc_mask = AT91SAM926x_PMC_UHP; 744 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
728 uhpck.rate_hz = utmi_clk.rate_hz; 745 uhpck.rate_hz = at91_usb_rate(&utmi_clk, utmi_clk.rate_hz, usbr);
729 uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
730} 746}
731 747
732static int __init at91_pmc_init(unsigned long main_clock) 748static int __init at91_pmc_init(unsigned long main_clock)