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-rw-r--r--arch/arm/mach-at91/at91cap9.c404
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diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
deleted file mode 100644
index 8967d75c2ea3..000000000000
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1/*
2 * arch/arm/mach-at91/at91cap9.c
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14
15#include <linux/module.h>
16
17#include <asm/proc-fns.h>
18#include <asm/irq.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21
22#include <mach/cpu.h>
23#include <mach/at91cap9.h>
24#include <mach/at91_pmc.h>
25
26#include "soc.h"
27#include "generic.h"
28#include "clock.h"
29#include "sam9_smc.h"
30
31/* --------------------------------------------------------------------
32 * Clocks
33 * -------------------------------------------------------------------- */
34
35/*
36 * The peripheral clocks.
37 */
38static struct clk pioABCD_clk = {
39 .name = "pioABCD_clk",
40 .pmc_mask = 1 << AT91CAP9_ID_PIOABCD,
41 .type = CLK_TYPE_PERIPHERAL,
42};
43static struct clk mpb0_clk = {
44 .name = "mpb0_clk",
45 .pmc_mask = 1 << AT91CAP9_ID_MPB0,
46 .type = CLK_TYPE_PERIPHERAL,
47};
48static struct clk mpb1_clk = {
49 .name = "mpb1_clk",
50 .pmc_mask = 1 << AT91CAP9_ID_MPB1,
51 .type = CLK_TYPE_PERIPHERAL,
52};
53static struct clk mpb2_clk = {
54 .name = "mpb2_clk",
55 .pmc_mask = 1 << AT91CAP9_ID_MPB2,
56 .type = CLK_TYPE_PERIPHERAL,
57};
58static struct clk mpb3_clk = {
59 .name = "mpb3_clk",
60 .pmc_mask = 1 << AT91CAP9_ID_MPB3,
61 .type = CLK_TYPE_PERIPHERAL,
62};
63static struct clk mpb4_clk = {
64 .name = "mpb4_clk",
65 .pmc_mask = 1 << AT91CAP9_ID_MPB4,
66 .type = CLK_TYPE_PERIPHERAL,
67};
68static struct clk usart0_clk = {
69 .name = "usart0_clk",
70 .pmc_mask = 1 << AT91CAP9_ID_US0,
71 .type = CLK_TYPE_PERIPHERAL,
72};
73static struct clk usart1_clk = {
74 .name = "usart1_clk",
75 .pmc_mask = 1 << AT91CAP9_ID_US1,
76 .type = CLK_TYPE_PERIPHERAL,
77};
78static struct clk usart2_clk = {
79 .name = "usart2_clk",
80 .pmc_mask = 1 << AT91CAP9_ID_US2,
81 .type = CLK_TYPE_PERIPHERAL,
82};
83static struct clk mmc0_clk = {
84 .name = "mci0_clk",
85 .pmc_mask = 1 << AT91CAP9_ID_MCI0,
86 .type = CLK_TYPE_PERIPHERAL,
87};
88static struct clk mmc1_clk = {
89 .name = "mci1_clk",
90 .pmc_mask = 1 << AT91CAP9_ID_MCI1,
91 .type = CLK_TYPE_PERIPHERAL,
92};
93static struct clk can_clk = {
94 .name = "can_clk",
95 .pmc_mask = 1 << AT91CAP9_ID_CAN,
96 .type = CLK_TYPE_PERIPHERAL,
97};
98static struct clk twi_clk = {
99 .name = "twi_clk",
100 .pmc_mask = 1 << AT91CAP9_ID_TWI,
101 .type = CLK_TYPE_PERIPHERAL,
102};
103static struct clk spi0_clk = {
104 .name = "spi0_clk",
105 .pmc_mask = 1 << AT91CAP9_ID_SPI0,
106 .type = CLK_TYPE_PERIPHERAL,
107};
108static struct clk spi1_clk = {
109 .name = "spi1_clk",
110 .pmc_mask = 1 << AT91CAP9_ID_SPI1,
111 .type = CLK_TYPE_PERIPHERAL,
112};
113static struct clk ssc0_clk = {
114 .name = "ssc0_clk",
115 .pmc_mask = 1 << AT91CAP9_ID_SSC0,
116 .type = CLK_TYPE_PERIPHERAL,
117};
118static struct clk ssc1_clk = {
119 .name = "ssc1_clk",
120 .pmc_mask = 1 << AT91CAP9_ID_SSC1,
121 .type = CLK_TYPE_PERIPHERAL,
122};
123static struct clk ac97_clk = {
124 .name = "ac97_clk",
125 .pmc_mask = 1 << AT91CAP9_ID_AC97C,
126 .type = CLK_TYPE_PERIPHERAL,
127};
128static struct clk tcb_clk = {
129 .name = "tcb_clk",
130 .pmc_mask = 1 << AT91CAP9_ID_TCB,
131 .type = CLK_TYPE_PERIPHERAL,
132};
133static struct clk pwm_clk = {
134 .name = "pwm_clk",
135 .pmc_mask = 1 << AT91CAP9_ID_PWMC,
136 .type = CLK_TYPE_PERIPHERAL,
137};
138static struct clk macb_clk = {
139 .name = "pclk",
140 .pmc_mask = 1 << AT91CAP9_ID_EMAC,
141 .type = CLK_TYPE_PERIPHERAL,
142};
143static struct clk aestdes_clk = {
144 .name = "aestdes_clk",
145 .pmc_mask = 1 << AT91CAP9_ID_AESTDES,
146 .type = CLK_TYPE_PERIPHERAL,
147};
148static struct clk adc_clk = {
149 .name = "adc_clk",
150 .pmc_mask = 1 << AT91CAP9_ID_ADC,
151 .type = CLK_TYPE_PERIPHERAL,
152};
153static struct clk isi_clk = {
154 .name = "isi_clk",
155 .pmc_mask = 1 << AT91CAP9_ID_ISI,
156 .type = CLK_TYPE_PERIPHERAL,
157};
158static struct clk lcdc_clk = {
159 .name = "lcdc_clk",
160 .pmc_mask = 1 << AT91CAP9_ID_LCDC,
161 .type = CLK_TYPE_PERIPHERAL,
162};
163static struct clk dma_clk = {
164 .name = "dma_clk",
165 .pmc_mask = 1 << AT91CAP9_ID_DMA,
166 .type = CLK_TYPE_PERIPHERAL,
167};
168static struct clk udphs_clk = {
169 .name = "udphs_clk",
170 .pmc_mask = 1 << AT91CAP9_ID_UDPHS,
171 .type = CLK_TYPE_PERIPHERAL,
172};
173static struct clk ohci_clk = {
174 .name = "ohci_clk",
175 .pmc_mask = 1 << AT91CAP9_ID_UHP,
176 .type = CLK_TYPE_PERIPHERAL,
177};
178
179static struct clk *periph_clocks[] __initdata = {
180 &pioABCD_clk,
181 &mpb0_clk,
182 &mpb1_clk,
183 &mpb2_clk,
184 &mpb3_clk,
185 &mpb4_clk,
186 &usart0_clk,
187 &usart1_clk,
188 &usart2_clk,
189 &mmc0_clk,
190 &mmc1_clk,
191 &can_clk,
192 &twi_clk,
193 &spi0_clk,
194 &spi1_clk,
195 &ssc0_clk,
196 &ssc1_clk,
197 &ac97_clk,
198 &tcb_clk,
199 &pwm_clk,
200 &macb_clk,
201 &aestdes_clk,
202 &adc_clk,
203 &isi_clk,
204 &lcdc_clk,
205 &dma_clk,
206 &udphs_clk,
207 &ohci_clk,
208 // irq0 .. irq1
209};
210
211static struct clk_lookup periph_clocks_lookups[] = {
212 /* One additional fake clock for macb_hclk */
213 CLKDEV_CON_ID("hclk", &macb_clk),
214 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
215 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
216 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
217 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
218 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
219 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
220 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
221 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
222 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
223 /* fake hclk clock */
224 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
225 CLKDEV_CON_ID("pioA", &pioABCD_clk),
226 CLKDEV_CON_ID("pioB", &pioABCD_clk),
227 CLKDEV_CON_ID("pioC", &pioABCD_clk),
228 CLKDEV_CON_ID("pioD", &pioABCD_clk),
229};
230
231static struct clk_lookup usart_clocks_lookups[] = {
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
234 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
235 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
236};
237
238/*
239 * The four programmable clocks.
240 * You must configure pin multiplexing to bring these signals out.
241 */
242static struct clk pck0 = {
243 .name = "pck0",
244 .pmc_mask = AT91_PMC_PCK0,
245 .type = CLK_TYPE_PROGRAMMABLE,
246 .id = 0,
247};
248static struct clk pck1 = {
249 .name = "pck1",
250 .pmc_mask = AT91_PMC_PCK1,
251 .type = CLK_TYPE_PROGRAMMABLE,
252 .id = 1,
253};
254static struct clk pck2 = {
255 .name = "pck2",
256 .pmc_mask = AT91_PMC_PCK2,
257 .type = CLK_TYPE_PROGRAMMABLE,
258 .id = 2,
259};
260static struct clk pck3 = {
261 .name = "pck3",
262 .pmc_mask = AT91_PMC_PCK3,
263 .type = CLK_TYPE_PROGRAMMABLE,
264 .id = 3,
265};
266
267static void __init at91cap9_register_clocks(void)
268{
269 int i;
270
271 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
272 clk_register(periph_clocks[i]);
273
274 clkdev_add_table(periph_clocks_lookups,
275 ARRAY_SIZE(periph_clocks_lookups));
276 clkdev_add_table(usart_clocks_lookups,
277 ARRAY_SIZE(usart_clocks_lookups));
278
279 clk_register(&pck0);
280 clk_register(&pck1);
281 clk_register(&pck2);
282 clk_register(&pck3);
283}
284
285static struct clk_lookup console_clock_lookup;
286
287void __init at91cap9_set_console_clock(int id)
288{
289 if (id >= ARRAY_SIZE(usart_clocks_lookups))
290 return;
291
292 console_clock_lookup.con_id = "usart";
293 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
294 clkdev_add(&console_clock_lookup);
295}
296
297/* --------------------------------------------------------------------
298 * GPIO
299 * -------------------------------------------------------------------- */
300
301static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
302 {
303 .id = AT91CAP9_ID_PIOABCD,
304 .regbase = AT91CAP9_BASE_PIOA,
305 }, {
306 .id = AT91CAP9_ID_PIOABCD,
307 .regbase = AT91CAP9_BASE_PIOB,
308 }, {
309 .id = AT91CAP9_ID_PIOABCD,
310 .regbase = AT91CAP9_BASE_PIOC,
311 }, {
312 .id = AT91CAP9_ID_PIOABCD,
313 .regbase = AT91CAP9_BASE_PIOD,
314 }
315};
316
317static void at91cap9_idle(void)
318{
319 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
320 cpu_do_idle();
321}
322
323/* --------------------------------------------------------------------
324 * AT91CAP9 processor initialization
325 * -------------------------------------------------------------------- */
326
327static void __init at91cap9_map_io(void)
328{
329 at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
330}
331
332static void __init at91cap9_ioremap_registers(void)
333{
334 at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
335 at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
336 at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
337 at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
338}
339
340static void __init at91cap9_initialize(void)
341{
342 arm_pm_idle = at91cap9_idle;
343 arm_pm_restart = at91sam9g45_restart;
344 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
345
346 /* Register GPIO subsystem */
347 at91_gpio_init(at91cap9_gpio, 4);
348
349 /* Remember the silicon revision */
350 if (cpu_is_at91cap9_revB())
351 system_rev = 0xB;
352 else if (cpu_is_at91cap9_revC())
353 system_rev = 0xC;
354}
355
356/* --------------------------------------------------------------------
357 * Interrupt initialization
358 * -------------------------------------------------------------------- */
359
360/*
361 * The default interrupt priority levels (0 = lowest, 7 = highest).
362 */
363static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
364 7, /* Advanced Interrupt Controller (FIQ) */
365 7, /* System Peripherals */
366 1, /* Parallel IO Controller A, B, C and D */
367 0, /* MP Block Peripheral 0 */
368 0, /* MP Block Peripheral 1 */
369 0, /* MP Block Peripheral 2 */
370 0, /* MP Block Peripheral 3 */
371 0, /* MP Block Peripheral 4 */
372 5, /* USART 0 */
373 5, /* USART 1 */
374 5, /* USART 2 */
375 0, /* Multimedia Card Interface 0 */
376 0, /* Multimedia Card Interface 1 */
377 3, /* CAN */
378 6, /* Two-Wire Interface */
379 5, /* Serial Peripheral Interface 0 */
380 5, /* Serial Peripheral Interface 1 */
381 4, /* Serial Synchronous Controller 0 */
382 4, /* Serial Synchronous Controller 1 */
383 5, /* AC97 Controller */
384 0, /* Timer Counter 0, 1 and 2 */
385 0, /* Pulse Width Modulation Controller */
386 3, /* Ethernet */
387 0, /* Advanced Encryption Standard, Triple DES*/
388 0, /* Analog-to-Digital Converter */
389 0, /* Image Sensor Interface */
390 3, /* LCD Controller */
391 0, /* DMA Controller */
392 2, /* USB Device Port */
393 2, /* USB Host port */
394 0, /* Advanced Interrupt Controller (IRQ0) */
395 0, /* Advanced Interrupt Controller (IRQ1) */
396};
397
398struct at91_init_soc __initdata at91cap9_soc = {
399 .map_io = at91cap9_map_io,
400 .default_irq_priority = at91cap9_default_irq_priority,
401 .ioremap_registers = at91cap9_ioremap_registers,
402 .register_clocks = at91cap9_register_clocks,
403 .init = at91cap9_initialize,
404};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-05 18:58:14 -0500