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-rw-r--r--arch/arm/mach-at91/at572d940hf_devices.c964
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diff --git a/arch/arm/mach-at91/at572d940hf_devices.c b/arch/arm/mach-at91/at572d940hf_devices.c
deleted file mode 100644
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1/*
2 * arch/arm/mach-at91/at572d940hf_devices.c
3 *
4 * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
5 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
6 * Copyright (C) 2005 David Brownell
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
29
30#include <mach/board.h>
31#include <mach/gpio.h>
32#include <mach/at572d940hf.h>
33#include <mach/at572d940hf_matrix.h>
34#include <mach/at91sam9_smc.h>
35
36#include "generic.h"
37#include "sam9_smc.h"
38
39
40/* --------------------------------------------------------------------
41 * USB Host
42 * -------------------------------------------------------------------- */
43
44#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
45static u64 ohci_dmamask = DMA_BIT_MASK(32);
46static struct at91_usbh_data usbh_data;
47
48static struct resource usbh_resources[] = {
49 [0] = {
50 .start = AT572D940HF_UHP_BASE,
51 .end = AT572D940HF_UHP_BASE + SZ_1M - 1,
52 .flags = IORESOURCE_MEM,
53 },
54 [1] = {
55 .start = AT572D940HF_ID_UHP,
56 .end = AT572D940HF_ID_UHP,
57 .flags = IORESOURCE_IRQ,
58 },
59};
60
61static struct platform_device at572d940hf_usbh_device = {
62 .name = "at91_ohci",
63 .id = -1,
64 .dev = {
65 .dma_mask = &ohci_dmamask,
66 .coherent_dma_mask = DMA_BIT_MASK(32),
67 .platform_data = &usbh_data,
68 },
69 .resource = usbh_resources,
70 .num_resources = ARRAY_SIZE(usbh_resources),
71};
72
73void __init at91_add_device_usbh(struct at91_usbh_data *data)
74{
75 if (!data)
76 return;
77
78 usbh_data = *data;
79 platform_device_register(&at572d940hf_usbh_device);
80
81}
82#else
83void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
84#endif
85
86
87/* --------------------------------------------------------------------
88 * USB Device (Gadget)
89 * -------------------------------------------------------------------- */
90
91#ifdef CONFIG_USB_GADGET_AT91
92static struct at91_udc_data udc_data;
93
94static struct resource udc_resources[] = {
95 [0] = {
96 .start = AT572D940HF_BASE_UDP,
97 .end = AT572D940HF_BASE_UDP + SZ_16K - 1,
98 .flags = IORESOURCE_MEM,
99 },
100 [1] = {
101 .start = AT572D940HF_ID_UDP,
102 .end = AT572D940HF_ID_UDP,
103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107static struct platform_device at572d940hf_udc_device = {
108 .name = "at91_udc",
109 .id = -1,
110 .dev = {
111 .platform_data = &udc_data,
112 },
113 .resource = udc_resources,
114 .num_resources = ARRAY_SIZE(udc_resources),
115};
116
117void __init at91_add_device_udc(struct at91_udc_data *data)
118{
119 if (!data)
120 return;
121
122 if (data->vbus_pin) {
123 at91_set_gpio_input(data->vbus_pin, 0);
124 at91_set_deglitch(data->vbus_pin, 1);
125 }
126
127 /* Pullup pin is handled internally */
128
129 udc_data = *data;
130 platform_device_register(&at572d940hf_udc_device);
131}
132#else
133void __init at91_add_device_udc(struct at91_udc_data *data) {}
134#endif
135
136
137/* --------------------------------------------------------------------
138 * Ethernet
139 * -------------------------------------------------------------------- */
140
141#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
142static u64 eth_dmamask = DMA_BIT_MASK(32);
143static struct at91_eth_data eth_data;
144
145static struct resource eth_resources[] = {
146 [0] = {
147 .start = AT572D940HF_BASE_EMAC,
148 .end = AT572D940HF_BASE_EMAC + SZ_16K - 1,
149 .flags = IORESOURCE_MEM,
150 },
151 [1] = {
152 .start = AT572D940HF_ID_EMAC,
153 .end = AT572D940HF_ID_EMAC,
154 .flags = IORESOURCE_IRQ,
155 },
156};
157
158static struct platform_device at572d940hf_eth_device = {
159 .name = "macb",
160 .id = -1,
161 .dev = {
162 .dma_mask = &eth_dmamask,
163 .coherent_dma_mask = DMA_BIT_MASK(32),
164 .platform_data = &eth_data,
165 },
166 .resource = eth_resources,
167 .num_resources = ARRAY_SIZE(eth_resources),
168};
169
170void __init at91_add_device_eth(struct at91_eth_data *data)
171{
172 if (!data)
173 return;
174
175 if (data->phy_irq_pin) {
176 at91_set_gpio_input(data->phy_irq_pin, 0);
177 at91_set_deglitch(data->phy_irq_pin, 1);
178 }
179
180 /* Only RMII is supported */
181 data->is_rmii = 1;
182
183 /* Pins used for RMII */
184 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXCK_EREFCK */
185 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
186 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERX0 */
187 at91_set_A_periph(AT91_PIN_PA19, 0); /* ERX1 */
188 at91_set_A_periph(AT91_PIN_PA20, 0); /* ERXER */
189 at91_set_A_periph(AT91_PIN_PA23, 0); /* ETXEN */
190 at91_set_A_periph(AT91_PIN_PA21, 0); /* ETX0 */
191 at91_set_A_periph(AT91_PIN_PA22, 0); /* ETX1 */
192 at91_set_A_periph(AT91_PIN_PA13, 0); /* EMDIO */
193 at91_set_A_periph(AT91_PIN_PA14, 0); /* EMDC */
194
195 eth_data = *data;
196 platform_device_register(&at572d940hf_eth_device);
197}
198#else
199void __init at91_add_device_eth(struct at91_eth_data *data) {}
200#endif
201
202
203/* --------------------------------------------------------------------
204 * MMC / SD
205 * -------------------------------------------------------------------- */
206
207#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
208static u64 mmc_dmamask = DMA_BIT_MASK(32);
209static struct at91_mmc_data mmc_data;
210
211static struct resource mmc_resources[] = {
212 [0] = {
213 .start = AT572D940HF_BASE_MCI,
214 .end = AT572D940HF_BASE_MCI + SZ_16K - 1,
215 .flags = IORESOURCE_MEM,
216 },
217 [1] = {
218 .start = AT572D940HF_ID_MCI,
219 .end = AT572D940HF_ID_MCI,
220 .flags = IORESOURCE_IRQ,
221 },
222};
223
224static struct platform_device at572d940hf_mmc_device = {
225 .name = "at91_mci",
226 .id = -1,
227 .dev = {
228 .dma_mask = &mmc_dmamask,
229 .coherent_dma_mask = DMA_BIT_MASK(32),
230 .platform_data = &mmc_data,
231 },
232 .resource = mmc_resources,
233 .num_resources = ARRAY_SIZE(mmc_resources),
234};
235
236void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
237{
238 if (!data)
239 return;
240
241 /* input/irq */
242 if (data->det_pin) {
243 at91_set_gpio_input(data->det_pin, 1);
244 at91_set_deglitch(data->det_pin, 1);
245 }
246 if (data->wp_pin)
247 at91_set_gpio_input(data->wp_pin, 1);
248 if (data->vcc_pin)
249 at91_set_gpio_output(data->vcc_pin, 0);
250
251 /* CLK */
252 at91_set_A_periph(AT91_PIN_PC22, 0);
253
254 /* CMD */
255 at91_set_A_periph(AT91_PIN_PC23, 1);
256
257 /* DAT0, maybe DAT1..DAT3 */
258 at91_set_A_periph(AT91_PIN_PC24, 1);
259 if (data->wire4) {
260 at91_set_A_periph(AT91_PIN_PC25, 1);
261 at91_set_A_periph(AT91_PIN_PC26, 1);
262 at91_set_A_periph(AT91_PIN_PC27, 1);
263 }
264
265 mmc_data = *data;
266 platform_device_register(&at572d940hf_mmc_device);
267}
268#else
269void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
270#endif
271
272
273/* --------------------------------------------------------------------
274 * NAND / SmartMedia
275 * -------------------------------------------------------------------- */
276
277#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
278static struct atmel_nand_data nand_data;
279
280#define NAND_BASE AT91_CHIPSELECT_3
281
282static struct resource nand_resources[] = {
283 {
284 .start = NAND_BASE,
285 .end = NAND_BASE + SZ_256M - 1,
286 .flags = IORESOURCE_MEM,
287 }
288};
289
290static struct platform_device at572d940hf_nand_device = {
291 .name = "atmel_nand",
292 .id = -1,
293 .dev = {
294 .platform_data = &nand_data,
295 },
296 .resource = nand_resources,
297 .num_resources = ARRAY_SIZE(nand_resources),
298};
299
300void __init at91_add_device_nand(struct atmel_nand_data *data)
301{
302 unsigned long csa;
303
304 if (!data)
305 return;
306
307 csa = at91_sys_read(AT91_MATRIX_EBICSA);
308 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
309
310 /* enable pin */
311 if (data->enable_pin)
312 at91_set_gpio_output(data->enable_pin, 1);
313
314 /* ready/busy pin */
315 if (data->rdy_pin)
316 at91_set_gpio_input(data->rdy_pin, 1);
317
318 /* card detect pin */
319 if (data->det_pin)
320 at91_set_gpio_input(data->det_pin, 1);
321
322 at91_set_A_periph(AT91_PIN_PB28, 0); /* A[22] */
323 at91_set_B_periph(AT91_PIN_PA28, 0); /* NANDOE */
324 at91_set_B_periph(AT91_PIN_PA29, 0); /* NANDWE */
325
326 nand_data = *data;
327 platform_device_register(&at572d940hf_nand_device);
328}
329
330#else
331void __init at91_add_device_nand(struct atmel_nand_data *data) {}
332#endif
333
334
335/* --------------------------------------------------------------------
336 * TWI (i2c)
337 * -------------------------------------------------------------------- */
338
339/*
340 * Prefer the GPIO code since the TWI controller isn't robust
341 * (gets overruns and underruns under load) and can only issue
342 * repeated STARTs in one scenario (the driver doesn't yet handle them).
343 */
344
345#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
346
347static struct i2c_gpio_platform_data pdata = {
348 .sda_pin = AT91_PIN_PC7,
349 .sda_is_open_drain = 1,
350 .scl_pin = AT91_PIN_PC8,
351 .scl_is_open_drain = 1,
352 .udelay = 2, /* ~100 kHz */
353};
354
355static struct platform_device at572d940hf_twi_device {
356 .name = "i2c-gpio",
357 .id = -1,
358 .dev.platform_data = &pdata,
359};
360
361void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
362{
363 at91_set_GPIO_periph(AT91_PIN_PC7, 1); /* TWD (SDA) */
364 at91_set_multi_drive(AT91_PIN_PC7, 1);
365
366 at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */
367 at91_set_multi_drive(AT91_PIN_PC8, 1);
368
369 i2c_register_board_info(0, devices, nr_devices);
370 platform_device_register(&at572d940hf_twi_device);
371}
372
373#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
374
375static struct resource twi0_resources[] = {
376 [0] = {
377 .start = AT572D940HF_BASE_TWI0,
378 .end = AT572D940HF_BASE_TWI0 + SZ_16K - 1,
379 .flags = IORESOURCE_MEM,
380 },
381 [1] = {
382 .start = AT572D940HF_ID_TWI0,
383 .end = AT572D940HF_ID_TWI0,
384 .flags = IORESOURCE_IRQ,
385 },
386};
387
388static struct platform_device at572d940hf_twi0_device = {
389 .name = "at91_i2c",
390 .id = 0,
391 .resource = twi0_resources,
392 .num_resources = ARRAY_SIZE(twi0_resources),
393};
394
395static struct resource twi1_resources[] = {
396 [0] = {
397 .start = AT572D940HF_BASE_TWI1,
398 .end = AT572D940HF_BASE_TWI1 + SZ_16K - 1,
399 .flags = IORESOURCE_MEM,
400 },
401 [1] = {
402 .start = AT572D940HF_ID_TWI1,
403 .end = AT572D940HF_ID_TWI1,
404 .flags = IORESOURCE_IRQ,
405 },
406};
407
408static struct platform_device at572d940hf_twi1_device = {
409 .name = "at91_i2c",
410 .id = 1,
411 .resource = twi1_resources,
412 .num_resources = ARRAY_SIZE(twi1_resources),
413};
414
415void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
416{
417 /* pins used for TWI0 interface */
418 at91_set_A_periph(AT91_PIN_PC7, 0); /* TWD */
419 at91_set_multi_drive(AT91_PIN_PC7, 1);
420
421 at91_set_A_periph(AT91_PIN_PC8, 0); /* TWCK */
422 at91_set_multi_drive(AT91_PIN_PC8, 1);
423
424 /* pins used for TWI1 interface */
425 at91_set_A_periph(AT91_PIN_PC20, 0); /* TWD */
426 at91_set_multi_drive(AT91_PIN_PC20, 1);
427
428 at91_set_A_periph(AT91_PIN_PC21, 0); /* TWCK */
429 at91_set_multi_drive(AT91_PIN_PC21, 1);
430
431 i2c_register_board_info(0, devices, nr_devices);
432 platform_device_register(&at572d940hf_twi0_device);
433 platform_device_register(&at572d940hf_twi1_device);
434}
435#else
436void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
437#endif
438
439
440/* --------------------------------------------------------------------
441 * SPI
442 * -------------------------------------------------------------------- */
443
444#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
445static u64 spi_dmamask = DMA_BIT_MASK(32);
446
447static struct resource spi0_resources[] = {
448 [0] = {
449 .start = AT572D940HF_BASE_SPI0,
450 .end = AT572D940HF_BASE_SPI0 + SZ_16K - 1,
451 .flags = IORESOURCE_MEM,
452 },
453 [1] = {
454 .start = AT572D940HF_ID_SPI0,
455 .end = AT572D940HF_ID_SPI0,
456 .flags = IORESOURCE_IRQ,
457 },
458};
459
460static struct platform_device at572d940hf_spi0_device = {
461 .name = "atmel_spi",
462 .id = 0,
463 .dev = {
464 .dma_mask = &spi_dmamask,
465 .coherent_dma_mask = DMA_BIT_MASK(32),
466 },
467 .resource = spi0_resources,
468 .num_resources = ARRAY_SIZE(spi0_resources),
469};
470
471static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
472
473static struct resource spi1_resources[] = {
474 [0] = {
475 .start = AT572D940HF_BASE_SPI1,
476 .end = AT572D940HF_BASE_SPI1 + SZ_16K - 1,
477 .flags = IORESOURCE_MEM,
478 },
479 [1] = {
480 .start = AT572D940HF_ID_SPI1,
481 .end = AT572D940HF_ID_SPI1,
482 .flags = IORESOURCE_IRQ,
483 },
484};
485
486static struct platform_device at572d940hf_spi1_device = {
487 .name = "atmel_spi",
488 .id = 1,
489 .dev = {
490 .dma_mask = &spi_dmamask,
491 .coherent_dma_mask = DMA_BIT_MASK(32),
492 },
493 .resource = spi1_resources,
494 .num_resources = ARRAY_SIZE(spi1_resources),
495};
496
497static const unsigned spi1_standard_cs[4] = { AT91_PIN_PC3, AT91_PIN_PC4, AT91_PIN_PC5, AT91_PIN_PC6 };
498
499void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
500{
501 int i;
502 unsigned long cs_pin;
503 short enable_spi0 = 0;
504 short enable_spi1 = 0;
505
506 /* Choose SPI chip-selects */
507 for (i = 0; i < nr_devices; i++) {
508 if (devices[i].controller_data)
509 cs_pin = (unsigned long) devices[i].controller_data;
510 else if (devices[i].bus_num == 0)
511 cs_pin = spi0_standard_cs[devices[i].chip_select];
512 else
513 cs_pin = spi1_standard_cs[devices[i].chip_select];
514
515 if (devices[i].bus_num == 0)
516 enable_spi0 = 1;
517 else
518 enable_spi1 = 1;
519
520 /* enable chip-select pin */
521 at91_set_gpio_output(cs_pin, 1);
522
523 /* pass chip-select pin to driver */
524 devices[i].controller_data = (void *) cs_pin;
525 }
526
527 spi_register_board_info(devices, nr_devices);
528
529 /* Configure SPI bus(es) */
530 if (enable_spi0) {
531 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
532 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
533 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
534
535 platform_device_register(&at572d940hf_spi0_device);
536 }
537 if (enable_spi1) {
538 at91_set_A_periph(AT91_PIN_PC0, 0); /* SPI1_MISO */
539 at91_set_A_periph(AT91_PIN_PC1, 0); /* SPI1_MOSI */
540 at91_set_A_periph(AT91_PIN_PC2, 0); /* SPI1_SPCK */
541
542 platform_device_register(&at572d940hf_spi1_device);
543 }
544}
545#else
546void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
547#endif
548
549
550/* --------------------------------------------------------------------
551 * Timer/Counter blocks
552 * -------------------------------------------------------------------- */
553
554#ifdef CONFIG_ATMEL_TCLIB
555
556static struct resource tcb_resources[] = {
557 [0] = {
558 .start = AT572D940HF_BASE_TCB,
559 .end = AT572D940HF_BASE_TCB + SZ_16K - 1,
560 .flags = IORESOURCE_MEM,
561 },
562 [1] = {
563 .start = AT572D940HF_ID_TC0,
564 .end = AT572D940HF_ID_TC0,
565 .flags = IORESOURCE_IRQ,
566 },
567 [2] = {
568 .start = AT572D940HF_ID_TC1,
569 .end = AT572D940HF_ID_TC1,
570 .flags = IORESOURCE_IRQ,
571 },
572 [3] = {
573 .start = AT572D940HF_ID_TC2,
574 .end = AT572D940HF_ID_TC2,
575 .flags = IORESOURCE_IRQ,
576 },
577};
578
579static struct platform_device at572d940hf_tcb_device = {
580 .name = "atmel_tcb",
581 .id = 0,
582 .resource = tcb_resources,
583 .num_resources = ARRAY_SIZE(tcb_resources),
584};
585
586static void __init at91_add_device_tc(void)
587{
588 platform_device_register(&at572d940hf_tcb_device);
589}
590#else
591static void __init at91_add_device_tc(void) { }
592#endif
593
594
595/* --------------------------------------------------------------------
596 * RTT
597 * -------------------------------------------------------------------- */
598
599static struct resource rtt_resources[] = {
600 {
601 .start = AT91_BASE_SYS + AT91_RTT,
602 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
603 .flags = IORESOURCE_MEM,
604 }
605};
606
607static struct platform_device at572d940hf_rtt_device = {
608 .name = "at91_rtt",
609 .id = 0,
610 .resource = rtt_resources,
611 .num_resources = ARRAY_SIZE(rtt_resources),
612};
613
614static void __init at91_add_device_rtt(void)
615{
616 platform_device_register(&at572d940hf_rtt_device);
617}
618
619
620/* --------------------------------------------------------------------
621 * Watchdog
622 * -------------------------------------------------------------------- */
623
624#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
625static struct platform_device at572d940hf_wdt_device = {
626 .name = "at91_wdt",
627 .id = -1,
628 .num_resources = 0,
629};
630
631static void __init at91_add_device_watchdog(void)
632{
633 platform_device_register(&at572d940hf_wdt_device);
634}
635#else
636static void __init at91_add_device_watchdog(void) {}
637#endif
638
639
640/* --------------------------------------------------------------------
641 * UART
642 * -------------------------------------------------------------------- */
643
644#if defined(CONFIG_SERIAL_ATMEL)
645static struct resource dbgu_resources[] = {
646 [0] = {
647 .start = AT91_VA_BASE_SYS + AT91_DBGU,
648 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
649 .flags = IORESOURCE_MEM,
650 },
651 [1] = {
652 .start = AT91_ID_SYS,
653 .end = AT91_ID_SYS,
654 .flags = IORESOURCE_IRQ,
655 },
656};
657
658static struct atmel_uart_data dbgu_data = {
659 .use_dma_tx = 0,
660 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
661 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
662};
663
664static u64 dbgu_dmamask = DMA_BIT_MASK(32);
665
666static struct platform_device at572d940hf_dbgu_device = {
667 .name = "atmel_usart",
668 .id = 0,
669 .dev = {
670 .dma_mask = &dbgu_dmamask,
671 .coherent_dma_mask = DMA_BIT_MASK(32),
672 .platform_data = &dbgu_data,
673 },
674 .resource = dbgu_resources,
675 .num_resources = ARRAY_SIZE(dbgu_resources),
676};
677
678static inline void configure_dbgu_pins(void)
679{
680 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
681 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
682}
683
684static struct resource uart0_resources[] = {
685 [0] = {
686 .start = AT572D940HF_BASE_US0,
687 .end = AT572D940HF_BASE_US0 + SZ_16K - 1,
688 .flags = IORESOURCE_MEM,
689 },
690 [1] = {
691 .start = AT572D940HF_ID_US0,
692 .end = AT572D940HF_ID_US0,
693 .flags = IORESOURCE_IRQ,
694 },
695};
696
697static struct atmel_uart_data uart0_data = {
698 .use_dma_tx = 1,
699 .use_dma_rx = 1,
700};
701
702static u64 uart0_dmamask = DMA_BIT_MASK(32);
703
704static struct platform_device at572d940hf_uart0_device = {
705 .name = "atmel_usart",
706 .id = 1,
707 .dev = {
708 .dma_mask = &uart0_dmamask,
709 .coherent_dma_mask = DMA_BIT_MASK(32),
710 .platform_data = &uart0_data,
711 },
712 .resource = uart0_resources,
713 .num_resources = ARRAY_SIZE(uart0_resources),
714};
715
716static inline void configure_usart0_pins(unsigned pins)
717{
718 at91_set_A_periph(AT91_PIN_PA8, 1); /* TXD0 */
719 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
720
721 if (pins & ATMEL_UART_RTS)
722 at91_set_A_periph(AT91_PIN_PA10, 0); /* RTS0 */
723 if (pins & ATMEL_UART_CTS)
724 at91_set_A_periph(AT91_PIN_PA9, 0); /* CTS0 */
725}
726
727static struct resource uart1_resources[] = {
728 [0] = {
729 .start = AT572D940HF_BASE_US1,
730 .end = AT572D940HF_BASE_US1 + SZ_16K - 1,
731 .flags = IORESOURCE_MEM,
732 },
733 [1] = {
734 .start = AT572D940HF_ID_US1,
735 .end = AT572D940HF_ID_US1,
736 .flags = IORESOURCE_IRQ,
737 },
738};
739
740static struct atmel_uart_data uart1_data = {
741 .use_dma_tx = 1,
742 .use_dma_rx = 1,
743};
744
745static u64 uart1_dmamask = DMA_BIT_MASK(32);
746
747static struct platform_device at572d940hf_uart1_device = {
748 .name = "atmel_usart",
749 .id = 2,
750 .dev = {
751 .dma_mask = &uart1_dmamask,
752 .coherent_dma_mask = DMA_BIT_MASK(32),
753 .platform_data = &uart1_data,
754 },
755 .resource = uart1_resources,
756 .num_resources = ARRAY_SIZE(uart1_resources),
757};
758
759static inline void configure_usart1_pins(unsigned pins)
760{
761 at91_set_A_periph(AT91_PIN_PC10, 1); /* TXD1 */
762 at91_set_A_periph(AT91_PIN_PC9 , 0); /* RXD1 */
763
764 if (pins & ATMEL_UART_RTS)
765 at91_set_A_periph(AT91_PIN_PC12, 0); /* RTS1 */
766 if (pins & ATMEL_UART_CTS)
767 at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS1 */
768}
769
770static struct resource uart2_resources[] = {
771 [0] = {
772 .start = AT572D940HF_BASE_US2,
773 .end = AT572D940HF_BASE_US2 + SZ_16K - 1,
774 .flags = IORESOURCE_MEM,
775 },
776 [1] = {
777 .start = AT572D940HF_ID_US2,
778 .end = AT572D940HF_ID_US2,
779 .flags = IORESOURCE_IRQ,
780 },
781};
782
783static struct atmel_uart_data uart2_data = {
784 .use_dma_tx = 1,
785 .use_dma_rx = 1,
786};
787
788static u64 uart2_dmamask = DMA_BIT_MASK(32);
789
790static struct platform_device at572d940hf_uart2_device = {
791 .name = "atmel_usart",
792 .id = 3,
793 .dev = {
794 .dma_mask = &uart2_dmamask,
795 .coherent_dma_mask = DMA_BIT_MASK(32),
796 .platform_data = &uart2_data,
797 },
798 .resource = uart2_resources,
799 .num_resources = ARRAY_SIZE(uart2_resources),
800};
801
802static inline void configure_usart2_pins(unsigned pins)
803{
804 at91_set_A_periph(AT91_PIN_PC15, 1); /* TXD2 */
805 at91_set_A_periph(AT91_PIN_PC14, 0); /* RXD2 */
806
807 if (pins & ATMEL_UART_RTS)
808 at91_set_A_periph(AT91_PIN_PC17, 0); /* RTS2 */
809 if (pins & ATMEL_UART_CTS)
810 at91_set_A_periph(AT91_PIN_PC16, 0); /* CTS2 */
811}
812
813static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
814struct platform_device *atmel_default_console_device; /* the serial console device */
815
816void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
817{
818 struct platform_device *pdev;
819 struct atmel_uart_data *pdata;
820
821 switch (id) {
822 case 0: /* DBGU */
823 pdev = &at572d940hf_dbgu_device;
824 configure_dbgu_pins();
825 break;
826 case AT572D940HF_ID_US0:
827 pdev = &at572d940hf_uart0_device;
828 configure_usart0_pins(pins);
829 break;
830 case AT572D940HF_ID_US1:
831 pdev = &at572d940hf_uart1_device;
832 configure_usart1_pins(pins);
833 break;
834 case AT572D940HF_ID_US2:
835 pdev = &at572d940hf_uart2_device;
836 configure_usart2_pins(pins);
837 break;
838 default:
839 return;
840 }
841 pdata = pdev->dev.platform_data;
842 pdata->num = portnr; /* update to mapped ID */
843
844 if (portnr < ATMEL_MAX_UART)
845 at91_uarts[portnr] = pdev;
846}
847
848void __init at91_set_serial_console(unsigned portnr)
849{
850 if (portnr < ATMEL_MAX_UART) {
851 atmel_default_console_device = at91_uarts[portnr];
852 at572d940hf_set_console_clock(portnr);
853 }
854}
855
856void __init at91_add_device_serial(void)
857{
858 int i;
859
860 for (i = 0; i < ATMEL_MAX_UART; i++) {
861 if (at91_uarts[i])
862 platform_device_register(at91_uarts[i]);
863 }
864
865 if (!atmel_default_console_device)
866 printk(KERN_INFO "AT91: No default serial console defined.\n");
867}
868
869#else
870void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
871void __init at91_set_serial_console(unsigned portnr) {}
872void __init at91_add_device_serial(void) {}
873#endif
874
875
876/* --------------------------------------------------------------------
877 * mAgic
878 * -------------------------------------------------------------------- */
879
880#ifdef CONFIG_MAGICV
881static struct resource mAgic_resources[] = {
882 {
883 .start = AT91_MAGIC_PM_BASE,
884 .end = AT91_MAGIC_PM_BASE + AT91_MAGIC_PM_SIZE - 1,
885 .flags = IORESOURCE_MEM,
886 },
887 {
888 .start = AT91_MAGIC_DM_I_BASE,
889 .end = AT91_MAGIC_DM_I_BASE + AT91_MAGIC_DM_I_SIZE - 1,
890 .flags = IORESOURCE_MEM,
891 },
892 {
893 .start = AT91_MAGIC_DM_F_BASE,
894 .end = AT91_MAGIC_DM_F_BASE + AT91_MAGIC_DM_F_SIZE - 1,
895 .flags = IORESOURCE_MEM,
896 },
897 {
898 .start = AT91_MAGIC_DM_DB_BASE,
899 .end = AT91_MAGIC_DM_DB_BASE + AT91_MAGIC_DM_DB_SIZE - 1,
900 .flags = IORESOURCE_MEM,
901 },
902 {
903 .start = AT91_MAGIC_REGS_BASE,
904 .end = AT91_MAGIC_REGS_BASE + AT91_MAGIC_REGS_SIZE - 1,
905 .flags = IORESOURCE_MEM,
906 },
907 {
908 .start = AT91_MAGIC_EXTPAGE_BASE,
909 .end = AT91_MAGIC_EXTPAGE_BASE + AT91_MAGIC_EXTPAGE_SIZE - 1,
910 .flags = IORESOURCE_MEM,
911 },
912 {
913 .start = AT572D940HF_ID_MSIRQ0,
914 .end = AT572D940HF_ID_MSIRQ0,
915 .flags = IORESOURCE_IRQ,
916 },
917 {
918 .start = AT572D940HF_ID_MHALT,
919 .end = AT572D940HF_ID_MHALT,
920 .flags = IORESOURCE_IRQ,
921 },
922 {
923 .start = AT572D940HF_ID_MEXC,
924 .end = AT572D940HF_ID_MEXC,
925 .flags = IORESOURCE_IRQ,
926 },
927 {
928 .start = AT572D940HF_ID_MEDMA,
929 .end = AT572D940HF_ID_MEDMA,
930 .flags = IORESOURCE_IRQ,
931 },
932};
933
934static struct platform_device mAgic_device = {
935 .name = "mAgic",
936 .id = -1,
937 .num_resources = ARRAY_SIZE(mAgic_resources),
938 .resource = mAgic_resources,
939};
940
941void __init at91_add_device_mAgic(void)
942{
943 platform_device_register(&mAgic_device);
944}
945#else
946void __init at91_add_device_mAgic(void) {}
947#endif
948
949
950/* -------------------------------------------------------------------- */
951
952/*
953 * These devices are always present and don't need any board-specific
954 * setup.
955 */
956static int __init at91_add_standard_devices(void)
957{
958 at91_add_device_rtt();
959 at91_add_device_watchdog();
960 at91_add_device_tc();
961 return 0;
962}
963
964arch_initcall(at91_add_standard_devices);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-03 21:16:56 -0500