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-rw-r--r--arch/arm/lib/io-acorn.S4
-rw-r--r--arch/arm/lib/io-readsb.S24
-rw-r--r--arch/arm/lib/io-readsw-armv3.S30
-rw-r--r--arch/arm/lib/io-readsw-armv4.S24
-rw-r--r--arch/arm/lib/io-writesb.S25
-rw-r--r--arch/arm/lib/io-writesw-armv3.S30
-rw-r--r--arch/arm/lib/io-writesw-armv4.S25
7 files changed, 82 insertions, 80 deletions
diff --git a/arch/arm/lib/io-acorn.S b/arch/arm/lib/io-acorn.S
index 3aacd01d40e1..b153523631c3 100644
--- a/arch/arm/lib/io-acorn.S
+++ b/arch/arm/lib/io-acorn.S
@@ -17,7 +17,7 @@
17 .text 17 .text
18 .align 18 .align
19 19
20.iosl_warning: 20.Liosl_warning:
21 .ascii "<4>insl/outsl not implemented, called from %08lX\0" 21 .ascii "<4>insl/outsl not implemented, called from %08lX\0"
22 .align 22 .align
23 23
@@ -27,6 +27,6 @@
27 */ 27 */
28ENTRY(insl) 28ENTRY(insl)
29ENTRY(outsl) 29ENTRY(outsl)
30 adr r0, .iosl_warning 30 adr r0, .Liosl_warning
31 mov r1, lr 31 mov r1, lr
32 b printk 32 b printk
diff --git a/arch/arm/lib/io-readsb.S b/arch/arm/lib/io-readsb.S
index 081ef749298a..d3d8de71a2c8 100644
--- a/arch/arm/lib/io-readsb.S
+++ b/arch/arm/lib/io-readsb.S
@@ -10,7 +10,7 @@
10#include <linux/linkage.h> 10#include <linux/linkage.h>
11#include <asm/assembler.h> 11#include <asm/assembler.h>
12 12
13.insb_align: rsb ip, ip, #4 13.Linsb_align: rsb ip, ip, #4
14 cmp ip, r2 14 cmp ip, r2
15 movgt ip, r2 15 movgt ip, r2
16 cmp ip, #2 16 cmp ip, #2
@@ -21,20 +21,20 @@
21 ldrgtb r3, [r0] 21 ldrgtb r3, [r0]
22 strgtb r3, [r1], #1 22 strgtb r3, [r1], #1
23 subs r2, r2, ip 23 subs r2, r2, ip
24 bne .insb_aligned 24 bne .Linsb_aligned
25 25
26ENTRY(__raw_readsb) 26ENTRY(__raw_readsb)
27 teq r2, #0 @ do we have to check for the zero len? 27 teq r2, #0 @ do we have to check for the zero len?
28 moveq pc, lr 28 moveq pc, lr
29 ands ip, r1, #3 29 ands ip, r1, #3
30 bne .insb_align 30 bne .Linsb_align
31 31
32.insb_aligned: stmfd sp!, {r4 - r6, lr} 32.Linsb_aligned: stmfd sp!, {r4 - r6, lr}
33 33
34 subs r2, r2, #16 34 subs r2, r2, #16
35 bmi .insb_no_16 35 bmi .Linsb_no_16
36 36
37.insb_16_lp: ldrb r3, [r0] 37.Linsb_16_lp: ldrb r3, [r0]
38 ldrb r4, [r0] 38 ldrb r4, [r0]
39 ldrb r5, [r0] 39 ldrb r5, [r0]
40 mov r3, r3, put_byte_0 40 mov r3, r3, put_byte_0
@@ -69,13 +69,13 @@ ENTRY(__raw_readsb)
69 stmia r1!, {r3 - r6} 69 stmia r1!, {r3 - r6}
70 70
71 subs r2, r2, #16 71 subs r2, r2, #16
72 bpl .insb_16_lp 72 bpl .Linsb_16_lp
73 73
74 tst r2, #15 74 tst r2, #15
75 LOADREGS(eqfd, sp!, {r4 - r6, pc}) 75 LOADREGS(eqfd, sp!, {r4 - r6, pc})
76 76
77.insb_no_16: tst r2, #8 77.Linsb_no_16: tst r2, #8
78 beq .insb_no_8 78 beq .Linsb_no_8
79 79
80 ldrb r3, [r0] 80 ldrb r3, [r0]
81 ldrb r4, [r0] 81 ldrb r4, [r0]
@@ -95,8 +95,8 @@ ENTRY(__raw_readsb)
95 orr r4, r4, ip, put_byte_3 95 orr r4, r4, ip, put_byte_3
96 stmia r1!, {r3, r4} 96 stmia r1!, {r3, r4}
97 97
98.insb_no_8: tst r2, #4 98.Linsb_no_8: tst r2, #4
99 beq .insb_no_4 99 beq .Linsb_no_4
100 100
101 ldrb r3, [r0] 101 ldrb r3, [r0]
102 ldrb r4, [r0] 102 ldrb r4, [r0]
@@ -108,7 +108,7 @@ ENTRY(__raw_readsb)
108 orr r3, r3, r6, put_byte_3 108 orr r3, r3, r6, put_byte_3
109 str r3, [r1], #4 109 str r3, [r1], #4
110 110
111.insb_no_4: ands r2, r2, #3 111.Linsb_no_4: ands r2, r2, #3
112 LOADREGS(eqfd, sp!, {r4 - r6, pc}) 112 LOADREGS(eqfd, sp!, {r4 - r6, pc})
113 113
114 cmp r2, #2 114 cmp r2, #2
diff --git a/arch/arm/lib/io-readsw-armv3.S b/arch/arm/lib/io-readsw-armv3.S
index 476cf7f8a633..146d47c15455 100644
--- a/arch/arm/lib/io-readsw-armv3.S
+++ b/arch/arm/lib/io-readsw-armv3.S
@@ -11,16 +11,16 @@
11#include <asm/assembler.h> 11#include <asm/assembler.h>
12#include <asm/hardware.h> 12#include <asm/hardware.h>
13 13
14.insw_bad_alignment: 14.Linsw_bad_alignment:
15 adr r0, .insw_bad_align_msg 15 adr r0, .Linsw_bad_align_msg
16 mov r2, lr 16 mov r2, lr
17 b panic 17 b panic
18.insw_bad_align_msg: 18.Linsw_bad_align_msg:
19 .asciz "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n" 19 .asciz "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
20 .align 20 .align
21 21
22.insw_align: tst r1, #1 22.Linsw_align: tst r1, #1
23 bne .insw_bad_alignment 23 bne .Linsw_bad_alignment
24 24
25 ldr r3, [r0] 25 ldr r3, [r0]
26 strb r3, [r1], #1 26 strb r3, [r1], #1
@@ -34,16 +34,16 @@ ENTRY(__raw_readsw)
34 teq r2, #0 @ do we have to check for the zero len? 34 teq r2, #0 @ do we have to check for the zero len?
35 moveq pc, lr 35 moveq pc, lr
36 tst r1, #3 36 tst r1, #3
37 bne .insw_align 37 bne .Linsw_align
38 38
39.insw_aligned: mov ip, #0xff 39.Linsw_aligned: mov ip, #0xff
40 orr ip, ip, ip, lsl #8 40 orr ip, ip, ip, lsl #8
41 stmfd sp!, {r4, r5, r6, lr} 41 stmfd sp!, {r4, r5, r6, lr}
42 42
43 subs r2, r2, #8 43 subs r2, r2, #8
44 bmi .no_insw_8 44 bmi .Lno_insw_8
45 45
46.insw_8_lp: ldr r3, [r0] 46.Linsw_8_lp: ldr r3, [r0]
47 and r3, r3, ip 47 and r3, r3, ip
48 ldr r4, [r0] 48 ldr r4, [r0]
49 orr r3, r3, r4, lsl #16 49 orr r3, r3, r4, lsl #16
@@ -66,13 +66,13 @@ ENTRY(__raw_readsw)
66 stmia r1!, {r3 - r6} 66 stmia r1!, {r3 - r6}
67 67
68 subs r2, r2, #8 68 subs r2, r2, #8
69 bpl .insw_8_lp 69 bpl .Linsw_8_lp
70 70
71 tst r2, #7 71 tst r2, #7
72 LOADREGS(eqfd, sp!, {r4, r5, r6, pc}) 72 LOADREGS(eqfd, sp!, {r4, r5, r6, pc})
73 73
74.no_insw_8: tst r2, #4 74.Lno_insw_8: tst r2, #4
75 beq .no_insw_4 75 beq .Lno_insw_4
76 76
77 ldr r3, [r0] 77 ldr r3, [r0]
78 and r3, r3, ip 78 and r3, r3, ip
@@ -86,8 +86,8 @@ ENTRY(__raw_readsw)
86 86
87 stmia r1!, {r3, r4} 87 stmia r1!, {r3, r4}
88 88
89.no_insw_4: tst r2, #2 89.Lno_insw_4: tst r2, #2
90 beq .no_insw_2 90 beq .Lno_insw_2
91 91
92 ldr r3, [r0] 92 ldr r3, [r0]
93 and r3, r3, ip 93 and r3, r3, ip
@@ -96,7 +96,7 @@ ENTRY(__raw_readsw)
96 96
97 str r3, [r1], #4 97 str r3, [r1], #4
98 98
99.no_insw_2: tst r2, #1 99.Lno_insw_2: tst r2, #1
100 ldrne r3, [r0] 100 ldrne r3, [r0]
101 strneb r3, [r1], #1 101 strneb r3, [r1], #1
102 movne r3, r3, lsr #8 102 movne r3, r3, lsr #8
diff --git a/arch/arm/lib/io-readsw-armv4.S b/arch/arm/lib/io-readsw-armv4.S
index c92b66ecbe86..4db1c5f0b219 100644
--- a/arch/arm/lib/io-readsw-armv4.S
+++ b/arch/arm/lib/io-readsw-armv4.S
@@ -18,8 +18,8 @@
18#endif 18#endif
19 .endm 19 .endm
20 20
21.insw_align: movs ip, r1, lsl #31 21.Linsw_align: movs ip, r1, lsl #31
22 bne .insw_noalign 22 bne .Linsw_noalign
23 ldrh ip, [r0] 23 ldrh ip, [r0]
24 sub r2, r2, #1 24 sub r2, r2, #1
25 strh ip, [r1], #2 25 strh ip, [r1], #2
@@ -28,14 +28,14 @@ ENTRY(__raw_readsw)
28 teq r2, #0 28 teq r2, #0
29 moveq pc, lr 29 moveq pc, lr
30 tst r1, #3 30 tst r1, #3
31 bne .insw_align 31 bne .Linsw_align
32 32
33 stmfd sp!, {r4, r5, lr} 33 stmfd sp!, {r4, r5, lr}
34 34
35 subs r2, r2, #8 35 subs r2, r2, #8
36 bmi .no_insw_8 36 bmi .Lno_insw_8
37 37
38.insw_8_lp: ldrh r3, [r0] 38.Linsw_8_lp: ldrh r3, [r0]
39 ldrh r4, [r0] 39 ldrh r4, [r0]
40 pack r3, r3, r4 40 pack r3, r3, r4
41 41
@@ -53,10 +53,10 @@ ENTRY(__raw_readsw)
53 53
54 subs r2, r2, #8 54 subs r2, r2, #8
55 stmia r1!, {r3 - r5, ip} 55 stmia r1!, {r3 - r5, ip}
56 bpl .insw_8_lp 56 bpl .Linsw_8_lp
57 57
58.no_insw_8: tst r2, #4 58.Lno_insw_8: tst r2, #4
59 beq .no_insw_4 59 beq .Lno_insw_4
60 60
61 ldrh r3, [r0] 61 ldrh r3, [r0]
62 ldrh r4, [r0] 62 ldrh r4, [r0]
@@ -68,15 +68,15 @@ ENTRY(__raw_readsw)
68 68
69 stmia r1!, {r3, r4} 69 stmia r1!, {r3, r4}
70 70
71.no_insw_4: movs r2, r2, lsl #31 71.Lno_insw_4: movs r2, r2, lsl #31
72 bcc .no_insw_2 72 bcc .Lno_insw_2
73 73
74 ldrh r3, [r0] 74 ldrh r3, [r0]
75 ldrh ip, [r0] 75 ldrh ip, [r0]
76 pack r3, r3, ip 76 pack r3, r3, ip
77 str r3, [r1], #4 77 str r3, [r1], #4
78 78
79.no_insw_2: ldrneh r3, [r0] 79.Lno_insw_2: ldrneh r3, [r0]
80 strneh r3, [r1] 80 strneh r3, [r1]
81 81
82 ldmfd sp!, {r4, r5, pc} 82 ldmfd sp!, {r4, r5, pc}
@@ -93,7 +93,7 @@ ENTRY(__raw_readsw)
93#define pull_hbyte1 lsr #8 93#define pull_hbyte1 lsr #8
94#endif 94#endif
95 95
96.insw_noalign: stmfd sp!, {r4, lr} 96.Linsw_noalign: stmfd sp!, {r4, lr}
97 ldrccb ip, [r1, #-1]! 97 ldrccb ip, [r1, #-1]!
98 bcc 1f 98 bcc 1f
99 99
diff --git a/arch/arm/lib/io-writesb.S b/arch/arm/lib/io-writesb.S
index 70b2561bdb09..08209fc640ea 100644
--- a/arch/arm/lib/io-writesb.S
+++ b/arch/arm/lib/io-writesb.S
@@ -30,7 +30,7 @@
30#endif 30#endif
31 .endm 31 .endm
32 32
33.outsb_align: rsb ip, ip, #4 33.Loutsb_align: rsb ip, ip, #4
34 cmp ip, r2 34 cmp ip, r2
35 movgt ip, r2 35 movgt ip, r2
36 cmp ip, #2 36 cmp ip, #2
@@ -41,44 +41,45 @@
41 ldrgtb r3, [r1], #1 41 ldrgtb r3, [r1], #1
42 strgtb r3, [r0] 42 strgtb r3, [r0]
43 subs r2, r2, ip 43 subs r2, r2, ip
44 bne .outsb_aligned 44 bne .Loutsb_aligned
45 45
46ENTRY(__raw_writesb) 46ENTRY(__raw_writesb)
47 teq r2, #0 @ do we have to check for the zero len? 47 teq r2, #0 @ do we have to check for the zero len?
48 moveq pc, lr 48 moveq pc, lr
49 ands ip, r1, #3 49 ands ip, r1, #3
50 bne .outsb_align 50 bne .Loutsb_align
51 51
52.outsb_aligned: stmfd sp!, {r4, r5, lr} 52.Loutsb_aligned:
53 stmfd sp!, {r4, r5, lr}
53 54
54 subs r2, r2, #16 55 subs r2, r2, #16
55 bmi .outsb_no_16 56 bmi .Loutsb_no_16
56 57
57.outsb_16_lp: ldmia r1!, {r3, r4, r5, ip} 58.Loutsb_16_lp: ldmia r1!, {r3, r4, r5, ip}
58 outword r3 59 outword r3
59 outword r4 60 outword r4
60 outword r5 61 outword r5
61 outword ip 62 outword ip
62 subs r2, r2, #16 63 subs r2, r2, #16
63 bpl .outsb_16_lp 64 bpl .Loutsb_16_lp
64 65
65 tst r2, #15 66 tst r2, #15
66 LOADREGS(eqfd, sp!, {r4, r5, pc}) 67 LOADREGS(eqfd, sp!, {r4, r5, pc})
67 68
68.outsb_no_16: tst r2, #8 69.Loutsb_no_16: tst r2, #8
69 beq .outsb_no_8 70 beq .Loutsb_no_8
70 71
71 ldmia r1!, {r3, r4} 72 ldmia r1!, {r3, r4}
72 outword r3 73 outword r3
73 outword r4 74 outword r4
74 75
75.outsb_no_8: tst r2, #4 76.Loutsb_no_8: tst r2, #4
76 beq .outsb_no_4 77 beq .Loutsb_no_4
77 78
78 ldr r3, [r1], #4 79 ldr r3, [r1], #4
79 outword r3 80 outword r3
80 81
81.outsb_no_4: ands r2, r2, #3 82.Loutsb_no_4: ands r2, r2, #3
82 LOADREGS(eqfd, sp!, {r4, r5, pc}) 83 LOADREGS(eqfd, sp!, {r4, r5, pc})
83 84
84 cmp r2, #2 85 cmp r2, #2
diff --git a/arch/arm/lib/io-writesw-armv3.S b/arch/arm/lib/io-writesw-armv3.S
index 950e7e310f1a..52d62b481295 100644
--- a/arch/arm/lib/io-writesw-armv3.S
+++ b/arch/arm/lib/io-writesw-armv3.S
@@ -11,16 +11,16 @@
11#include <asm/assembler.h> 11#include <asm/assembler.h>
12#include <asm/hardware.h> 12#include <asm/hardware.h>
13 13
14.outsw_bad_alignment: 14.Loutsw_bad_alignment:
15 adr r0, .outsw_bad_align_msg 15 adr r0, .Loutsw_bad_align_msg
16 mov r2, lr 16 mov r2, lr
17 b panic 17 b panic
18.outsw_bad_align_msg: 18.Loutsw_bad_align_msg:
19 .asciz "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n" 19 .asciz "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
20 .align 20 .align
21 21
22.outsw_align: tst r1, #1 22.Loutsw_align: tst r1, #1
23 bne .outsw_bad_alignment 23 bne .Loutsw_bad_alignment
24 24
25 add r1, r1, #2 25 add r1, r1, #2
26 26
@@ -35,14 +35,14 @@ ENTRY(__raw_writesw)
35 teq r2, #0 @ do we have to check for the zero len? 35 teq r2, #0 @ do we have to check for the zero len?
36 moveq pc, lr 36 moveq pc, lr
37 tst r1, #3 37 tst r1, #3
38 bne .outsw_align 38 bne .Loutsw_align
39 39
40.outsw_aligned: stmfd sp!, {r4, r5, r6, lr} 40 stmfd sp!, {r4, r5, r6, lr}
41 41
42 subs r2, r2, #8 42 subs r2, r2, #8
43 bmi .no_outsw_8 43 bmi .Lno_outsw_8
44 44
45.outsw_8_lp: ldmia r1!, {r3, r4, r5, r6} 45.Loutsw_8_lp: ldmia r1!, {r3, r4, r5, r6}
46 46
47 mov ip, r3, lsl #16 47 mov ip, r3, lsl #16
48 orr ip, ip, ip, lsr #16 48 orr ip, ip, ip, lsr #16
@@ -77,13 +77,13 @@ ENTRY(__raw_writesw)
77 str ip, [r0] 77 str ip, [r0]
78 78
79 subs r2, r2, #8 79 subs r2, r2, #8
80 bpl .outsw_8_lp 80 bpl .Loutsw_8_lp
81 81
82 tst r2, #7 82 tst r2, #7
83 LOADREGS(eqfd, sp!, {r4, r5, r6, pc}) 83 LOADREGS(eqfd, sp!, {r4, r5, r6, pc})
84 84
85.no_outsw_8: tst r2, #4 85.Lno_outsw_8: tst r2, #4
86 beq .no_outsw_4 86 beq .Lno_outsw_4
87 87
88 ldmia r1!, {r3, r4} 88 ldmia r1!, {r3, r4}
89 89
@@ -103,8 +103,8 @@ ENTRY(__raw_writesw)
103 orr ip, ip, ip, lsl #16 103 orr ip, ip, ip, lsl #16
104 str ip, [r0] 104 str ip, [r0]
105 105
106.no_outsw_4: tst r2, #2 106.Lno_outsw_4: tst r2, #2
107 beq .no_outsw_2 107 beq .Lno_outsw_2
108 108
109 ldr r3, [r1], #4 109 ldr r3, [r1], #4
110 110
@@ -116,7 +116,7 @@ ENTRY(__raw_writesw)
116 orr ip, ip, ip, lsl #16 116 orr ip, ip, ip, lsl #16
117 str ip, [r0] 117 str ip, [r0]
118 118
119.no_outsw_2: tst r2, #1 119.Lno_outsw_2: tst r2, #1
120 120
121 ldrne r3, [r1] 121 ldrne r3, [r1]
122 122
diff --git a/arch/arm/lib/io-writesw-armv4.S b/arch/arm/lib/io-writesw-armv4.S
index 5e240e452af6..c8e85bd653b7 100644
--- a/arch/arm/lib/io-writesw-armv4.S
+++ b/arch/arm/lib/io-writesw-armv4.S
@@ -22,8 +22,8 @@
22#endif 22#endif
23 .endm 23 .endm
24 24
25.outsw_align: movs ip, r1, lsl #31 25.Loutsw_align: movs ip, r1, lsl #31
26 bne .outsw_noalign 26 bne .Loutsw_noalign
27 27
28 ldrh r3, [r1], #2 28 ldrh r3, [r1], #2
29 sub r2, r2, #1 29 sub r2, r2, #1
@@ -33,35 +33,35 @@ ENTRY(__raw_writesw)
33 teq r2, #0 33 teq r2, #0
34 moveq pc, lr 34 moveq pc, lr
35 ands r3, r1, #3 35 ands r3, r1, #3
36 bne .outsw_align 36 bne .Loutsw_align
37 37
38 stmfd sp!, {r4, r5, lr} 38 stmfd sp!, {r4, r5, lr}
39 39
40 subs r2, r2, #8 40 subs r2, r2, #8
41 bmi .no_outsw_8 41 bmi .Lno_outsw_8
42 42
43.outsw_8_lp: ldmia r1!, {r3, r4, r5, ip} 43.Loutsw_8_lp: ldmia r1!, {r3, r4, r5, ip}
44 subs r2, r2, #8 44 subs r2, r2, #8
45 outword r3 45 outword r3
46 outword r4 46 outword r4
47 outword r5 47 outword r5
48 outword ip 48 outword ip
49 bpl .outsw_8_lp 49 bpl .Loutsw_8_lp
50 50
51.no_outsw_8: tst r2, #4 51.Lno_outsw_8: tst r2, #4
52 beq .no_outsw_4 52 beq .Lno_outsw_4
53 53
54 ldmia r1!, {r3, ip} 54 ldmia r1!, {r3, ip}
55 outword r3 55 outword r3
56 outword ip 56 outword ip
57 57
58.no_outsw_4: movs r2, r2, lsl #31 58.Lno_outsw_4: movs r2, r2, lsl #31
59 bcc .no_outsw_2 59 bcc .Lno_outsw_2
60 60
61 ldr r3, [r1], #4 61 ldr r3, [r1], #4
62 outword r3 62 outword r3
63 63
64.no_outsw_2: ldrneh r3, [r1] 64.Lno_outsw_2: ldrneh r3, [r1]
65 strneh r3, [r0] 65 strneh r3, [r0]
66 66
67 ldmfd sp!, {r4, r5, pc} 67 ldmfd sp!, {r4, r5, pc}
@@ -74,7 +74,8 @@ ENTRY(__raw_writesw)
74#define push_hbyte1 lsl #8 74#define push_hbyte1 lsl #8
75#endif 75#endif
76 76
77.outsw_noalign: ldr r3, [r1, -r3]! 77.Loutsw_noalign:
78 ldr r3, [r1, -r3]!
78 subcs r2, r2, #1 79 subcs r2, r2, #1
79 bcs 2f 80 bcs 2f
80 subs r2, r2, #2 81 subs r2, r2, #2
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 15:24:58 -0500