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-rw-r--r--arch/arm/lib/io-writesw-armv3.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/lib/io-writesw-armv3.S b/arch/arm/lib/io-writesw-armv3.S
index 52d62b481295..1607a29f49b7 100644
--- a/arch/arm/lib/io-writesw-armv3.S
+++ b/arch/arm/lib/io-writesw-armv3.S
@@ -29,7 +29,7 @@
29 orr r3, r3, r3, lsl #16 29 orr r3, r3, r3, lsl #16
30 str r3, [r0] 30 str r3, [r0]
31 subs r2, r2, #1 31 subs r2, r2, #1
32 RETINSTR(moveq, pc, lr) 32 moveq pc, lr
33 33
34ENTRY(__raw_writesw) 34ENTRY(__raw_writesw)
35 teq r2, #0 @ do we have to check for the zero len? 35 teq r2, #0 @ do we have to check for the zero len?
@@ -80,7 +80,7 @@ ENTRY(__raw_writesw)
80 bpl .Loutsw_8_lp 80 bpl .Loutsw_8_lp
81 81
82 tst r2, #7 82 tst r2, #7
83 LOADREGS(eqfd, sp!, {r4, r5, r6, pc}) 83 ldmeqfd sp!, {r4, r5, r6, pc}
84 84
85.Lno_outsw_8: tst r2, #4 85.Lno_outsw_8: tst r2, #4
86 beq .Lno_outsw_4 86 beq .Lno_outsw_4
@@ -124,4 +124,4 @@ ENTRY(__raw_writesw)
124 orrne ip, ip, ip, lsr #16 124 orrne ip, ip, ip, lsr #16
125 strne ip, [r0] 125 strne ip, [r0]
126 126
127 LOADREGS(fd, sp!, {r4, r5, r6, pc}) 127 ldmfd sp!, {r4, r5, r6, pc}