1 files changed, 92 insertions, 106 deletions

diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index ecbb0288e5dd..ad19c276b10f 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -221,46 +221,56 @@ again:
 }
 
 static void
-armpmu_disable(struct perf_event *event)
+armpmu_read(struct perf_event *event)
 {
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
         struct hw_perf_event *hwc = &event->hw;
-        int idx = hwc->idx;
-
-        WARN_ON(idx < 0);
-
-        clear_bit(idx, cpuc->active_mask);
-        armpmu->disable(hwc, idx);
-
-        barrier();
 
-        armpmu_event_update(event, hwc, idx);
-        cpuc->events[idx] = NULL;
-        clear_bit(idx, cpuc->used_mask);
+        /* Don't read disabled counters! */
+        if (hwc->idx < 0)
+                return;
 
-        perf_event_update_userpage(event);
+        armpmu_event_update(event, hwc, hwc->idx);
 }
 
 static void
-armpmu_read(struct perf_event *event)
+armpmu_stop(struct perf_event *event, int flags)
 {
         struct hw_perf_event *hwc = &event->hw;
 
-        /* Don't read disabled counters! */
-        if (hwc->idx < 0)
+        if (!armpmu)
                 return;
 
-        armpmu_event_update(event, hwc, hwc->idx);
+        /*
+         * ARM pmu always has to update the counter, so ignore
+         * PERF_EF_UPDATE, see comments in armpmu_start().
+         */
+        if (!(hwc->state & PERF_HES_STOPPED)) {
+                armpmu->disable(hwc, hwc->idx);
+                barrier(); /* why? */
+                armpmu_event_update(event, hwc, hwc->idx);
+                hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
+        }
 }
 
 static void
-armpmu_unthrottle(struct perf_event *event)
+armpmu_start(struct perf_event *event, int flags)
 {
         struct hw_perf_event *hwc = &event->hw;
 
+        if (!armpmu)
+                return;
+
+        /*
+         * ARM pmu always has to reprogram the period, so ignore
+         * PERF_EF_RELOAD, see the comment below.
+         */
+        if (flags & PERF_EF_RELOAD)
+                WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
+
+        hwc->state = 0;
         /*
          * Set the period again. Some counters can't be stopped, so when we
-         * were throttled we simply disabled the IRQ source and the counter
+         * were stopped we simply disabled the IRQ source and the counter
          * may have been left counting. If we don't do this step then we may
          * get an interrupt too soon or *way* too late if the overflow has
          * happened since disabling.
@@ -269,14 +279,33 @@ armpmu_unthrottle(struct perf_event *event)
         armpmu->enable(hwc, hwc->idx);
 }
 
+static void
+armpmu_del(struct perf_event *event, int flags)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+
+        WARN_ON(idx < 0);
+
+        clear_bit(idx, cpuc->active_mask);
+        armpmu_stop(event, PERF_EF_UPDATE);
+        cpuc->events[idx] = NULL;
+        clear_bit(idx, cpuc->used_mask);
+
+        perf_event_update_userpage(event);
+}
+
 static int
-armpmu_enable(struct perf_event *event)
+armpmu_add(struct perf_event *event, int flags)
 {
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
         struct hw_perf_event *hwc = &event->hw;
         int idx;
         int err = 0;
 
+        perf_pmu_disable(event->pmu);
+
         /* If we don't have a space for the counter then finish early. */
         idx = armpmu->get_event_idx(cpuc, hwc);
         if (idx < 0) {
@@ -293,25 +322,19 @@ armpmu_enable(struct perf_event *event)
         cpuc->events[idx] = event;
         set_bit(idx, cpuc->active_mask);
 
-        /* Set the period for the event. */
-        armpmu_event_set_period(event, hwc, idx);
-
-        /* Enable the event. */
-        armpmu->enable(hwc, idx);
+        hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
+        if (flags & PERF_EF_START)
+                armpmu_start(event, PERF_EF_RELOAD);
 
         /* Propagate our changes to the userspace mapping. */
         perf_event_update_userpage(event);
 
 out:
+        perf_pmu_enable(event->pmu);
         return err;
 }
 
-static struct pmu pmu = {
-        .enable     = armpmu_enable,
-        .disable    = armpmu_disable,
-        .unthrottle = armpmu_unthrottle,
-        .read       = armpmu_read,
-};
+static struct pmu pmu;
 
 static int
 validate_event(struct cpu_hw_events *cpuc,
@@ -491,20 +514,29 @@ __hw_perf_event_init(struct perf_event *event)
         return err;
 }
 
-const struct pmu *
-hw_perf_event_init(struct perf_event *event)
+static int armpmu_event_init(struct perf_event *event)
 {
         int err = 0;
 
+        switch (event->attr.type) {
+        case PERF_TYPE_RAW:
+        case PERF_TYPE_HARDWARE:
+        case PERF_TYPE_HW_CACHE:
+                break;
+
+        default:
+                return -ENOENT;
+        }
+
         if (!armpmu)
-                return ERR_PTR(-ENODEV);
+                return -ENODEV;
 
         event->destroy = hw_perf_event_destroy;
 
         if (!atomic_inc_not_zero(&active_events)) {
-                if (atomic_read(&active_events) > perf_max_events) {
+                if (atomic_read(&active_events) > armpmu.num_events) {
                         atomic_dec(&active_events);
-                        return ERR_PTR(-ENOSPC);
+                        return -ENOSPC;
                 }
 
                 mutex_lock(&pmu_reserve_mutex);
@@ -518,17 +550,16 @@ hw_perf_event_init(struct perf_event *event)
         }
 
         if (err)
-                return ERR_PTR(err);
+                return err;
 
         err = __hw_perf_event_init(event);
         if (err)
                 hw_perf_event_destroy(event);
 
-        return err ? ERR_PTR(err) : &pmu;
+        return err;
 }
 
-void
-hw_perf_enable(void)
+static void armpmu_enable(struct pmu *pmu)
 {
         /* Enable all of the perf events on hardware. */
         int idx;
@@ -549,13 +580,23 @@ hw_perf_enable(void)
         armpmu->start();
 }
 
-void
-hw_perf_disable(void)
+static void armpmu_disable(struct pmu *pmu)
 {
         if (armpmu)
                 armpmu->stop();
 }
 
+static struct pmu pmu = {
+        .pmu_enable     = armpmu_enable,
+        .pmu_disable    = armpmu_disable,
+        .event_init     = armpmu_event_init,
+        .add            = armpmu_add,
+        .del            = armpmu_del,
+        .start          = armpmu_start,
+        .stop           = armpmu_stop,
+        .read           = armpmu_read,
+};
+
 /*
  * ARMv6 Performance counter handling code.
  *
@@ -2933,14 +2974,12 @@ init_hw_perf_events(void)
                         armpmu = &armv6pmu;
                         memcpy(armpmu_perf_cache_map, armv6_perf_cache_map,
                                         sizeof(armv6_perf_cache_map));
-                        perf_max_events = armv6pmu.num_events;
                         break;
                 case 0xB020:    /* ARM11mpcore */
                         armpmu = &armv6mpcore_pmu;
                         memcpy(armpmu_perf_cache_map,
                                armv6mpcore_perf_cache_map,
                                sizeof(armv6mpcore_perf_cache_map));
-                        perf_max_events = armv6mpcore_pmu.num_events;
                         break;
                 case 0xC080:    /* Cortex-A8 */
                         armv7pmu.id = ARM_PERF_PMU_ID_CA8;
@@ -2952,7 +2991,6 @@ init_hw_perf_events(void)
                         /* Reset PMNC and read the nb of CNTx counters
                             supported */
                         armv7pmu.num_events = armv7_reset_read_pmnc();
-                        perf_max_events = armv7pmu.num_events;
                         break;
                 case 0xC090:    /* Cortex-A9 */
                         armv7pmu.id = ARM_PERF_PMU_ID_CA9;
@@ -2964,7 +3002,6 @@ init_hw_perf_events(void)
                         /* Reset PMNC and read the nb of CNTx counters
                             supported */
                         armv7pmu.num_events = armv7_reset_read_pmnc();
-                        perf_max_events = armv7pmu.num_events;
                         break;
                 }
         /* Intel CPUs [xscale]. */
@@ -2975,13 +3012,11 @@ init_hw_perf_events(void)
                         armpmu = &xscale1pmu;
                         memcpy(armpmu_perf_cache_map, xscale_perf_cache_map,
                                         sizeof(xscale_perf_cache_map));
-                        perf_max_events = xscale1pmu.num_events;
                         break;
                 case 2:
                         armpmu = &xscale2pmu;
                         memcpy(armpmu_perf_cache_map, xscale_perf_cache_map,
                                         sizeof(xscale_perf_cache_map));
-                        perf_max_events = xscale2pmu.num_events;
                         break;
                 }
         }
@@ -2991,9 +3026,10 @@ init_hw_perf_events(void)
                                 arm_pmu_names[armpmu->id], armpmu->num_events);
         } else {
                 pr_info("no hardware support available\n");
-                perf_max_events = -1;
         }
 
+        perf_pmu_register(&pmu);
+
         return 0;
 }
 arch_initcall(init_hw_perf_events);
@@ -3001,13 +3037,6 @@ arch_initcall(init_hw_perf_events);
 /*
  * Callchain handling code.
  */
-static inline void
-callchain_store(struct perf_callchain_entry *entry,
-                u64 ip)
-{
-        if (entry->nr < PERF_MAX_STACK_DEPTH)
-                entry->ip[entry->nr++] = ip;
-}
 
 /*
  * The registers we're interested in are at the end of the variable
@@ -3039,7 +3068,7 @@ user_backtrace(struct frame_tail *tail,
         if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
                 return NULL;
 
-        callchain_store(entry, buftail.lr);
+        perf_callchain_store(entry, buftail.lr);
 
         /*
          * Frame pointers should strictly progress back up the stack
@@ -3051,16 +3080,11 @@ user_backtrace(struct frame_tail *tail,
         return buftail.fp - 1;
 }
 
-static void
-perf_callchain_user(struct pt_regs *regs,
-                    struct perf_callchain_entry *entry)
+void
+perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
 {
         struct frame_tail *tail;
 
-        callchain_store(entry, PERF_CONTEXT_USER);
-
-        if (!user_mode(regs))
-                regs = task_pt_regs(current);
 
         tail = (struct frame_tail *)regs->ARM_fp - 1;
 
@@ -3078,56 +3102,18 @@ callchain_trace(struct stackframe *fr,
                 void *data)
 {
         struct perf_callchain_entry *entry = data;
-        callchain_store(entry, fr->pc);
+        perf_callchain_store(entry, fr->pc);
         return 0;
 }
 
-static void
-perf_callchain_kernel(struct pt_regs *regs,
-                      struct perf_callchain_entry *entry)
+void
+perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
 {
         struct stackframe fr;
 
-        callchain_store(entry, PERF_CONTEXT_KERNEL);
         fr.fp = regs->ARM_fp;
         fr.sp = regs->ARM_sp;
         fr.lr = regs->ARM_lr;
         fr.pc = regs->ARM_pc;
         walk_stackframe(&fr, callchain_trace, entry);
 }
-
-static void
-perf_do_callchain(struct pt_regs *regs,
-                  struct perf_callchain_entry *entry)
-{
-        int is_user;
-
-        if (!regs)
-                return;
-
-        is_user = user_mode(regs);
-
-        if (!current || !current->pid)
-                return;
-
-        if (is_user && current->state != TASK_RUNNING)
-                return;
-
-        if (!is_user)
-                perf_callchain_kernel(regs, entry);
-
-        if (current->mm)
-                perf_callchain_user(regs, entry);
-}
-
-static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
-
-struct perf_callchain_entry *
-perf_callchain(struct pt_regs *regs)
-{
-        struct perf_callchain_entry *entry = &__get_cpu_var(pmc_irq_entry);
-
-        entry->nr = 0;
-        perf_do_callchain(regs, entry);
-        return entry;
-}