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-rw-r--r--arch/arm/kernel/signal.c29
1 files changed, 19 insertions, 10 deletions
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 931919fd5121..07ddeed61766 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -19,6 +19,7 @@
19#include <asm/unistd.h> 19#include <asm/unistd.h>
20 20
21#include "ptrace.h" 21#include "ptrace.h"
22#include "signal.h"
22 23
23#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) 24#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
24 25
@@ -35,7 +36,7 @@
35#define SWI_THUMB_SIGRETURN (0xdf00 << 16 | 0x2700 | (__NR_sigreturn - __NR_SYSCALL_BASE)) 36#define SWI_THUMB_SIGRETURN (0xdf00 << 16 | 0x2700 | (__NR_sigreturn - __NR_SYSCALL_BASE))
36#define SWI_THUMB_RT_SIGRETURN (0xdf00 << 16 | 0x2700 | (__NR_rt_sigreturn - __NR_SYSCALL_BASE)) 37#define SWI_THUMB_RT_SIGRETURN (0xdf00 << 16 | 0x2700 | (__NR_rt_sigreturn - __NR_SYSCALL_BASE))
37 38
38static const unsigned long retcodes[4] = { 39const unsigned long sigreturn_codes[4] = {
39 SWI_SYS_SIGRETURN, SWI_THUMB_SIGRETURN, 40 SWI_SYS_SIGRETURN, SWI_THUMB_SIGRETURN,
40 SWI_SYS_RT_SIGRETURN, SWI_THUMB_RT_SIGRETURN 41 SWI_SYS_RT_SIGRETURN, SWI_THUMB_RT_SIGRETURN
41}; 42};
@@ -500,17 +501,25 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
500 if (ka->sa.sa_flags & SA_SIGINFO) 501 if (ka->sa.sa_flags & SA_SIGINFO)
501 idx += 2; 502 idx += 2;
502 503
503 if (__put_user(retcodes[idx], rc)) 504 if (__put_user(sigreturn_codes[idx], rc))
504 return 1; 505 return 1;
505 506
506 /* 507 if (cpsr & MODE32_BIT) {
507 * Ensure that the instruction cache sees 508 /*
508 * the return code written onto the stack. 509 * 32-bit code can use the new high-page
509 */ 510 * signal return code support.
510 flush_icache_range((unsigned long)rc, 511 */
511 (unsigned long)(rc + 1)); 512 retcode = KERN_SIGRETURN_CODE + (idx << 2) + thumb;
512 513 } else {
513 retcode = ((unsigned long)rc) + thumb; 514 /*
515 * Ensure that the instruction cache sees
516 * the return code written onto the stack.
517 */
518 flush_icache_range((unsigned long)rc,
519 (unsigned long)(rc + 1));
520
521 retcode = ((unsigned long)rc) + thumb;
522 }
514 } 523 }
515 524
516 regs->ARM_r0 = usig; 525 regs->ARM_r0 = usig;