diff options
Diffstat (limited to 'arch/arm/kernel/head.S')
-rw-r--r-- | arch/arm/kernel/head.S | 50 |
1 files changed, 31 insertions, 19 deletions
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 6bd82d25683c..f17d9a09e8fb 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S | |||
@@ -91,6 +91,11 @@ ENTRY(stext) | |||
91 | movs r8, r5 @ invalid machine (r5=0)? | 91 | movs r8, r5 @ invalid machine (r5=0)? |
92 | THUMB( it eq ) @ force fixup-able long branch encoding | 92 | THUMB( it eq ) @ force fixup-able long branch encoding |
93 | beq __error_a @ yes, error 'a' | 93 | beq __error_a @ yes, error 'a' |
94 | |||
95 | /* | ||
96 | * r1 = machine no, r2 = atags, | ||
97 | * r8 = machinfo, r9 = cpuid, r10 = procinfo | ||
98 | */ | ||
94 | bl __vet_atags | 99 | bl __vet_atags |
95 | #ifdef CONFIG_SMP_ON_UP | 100 | #ifdef CONFIG_SMP_ON_UP |
96 | bl __fixup_smp | 101 | bl __fixup_smp |
@@ -387,19 +392,19 @@ ENDPROC(__turn_mmu_on) | |||
387 | 392 | ||
388 | #ifdef CONFIG_SMP_ON_UP | 393 | #ifdef CONFIG_SMP_ON_UP |
389 | __fixup_smp: | 394 | __fixup_smp: |
390 | mov r7, #0x00070000 | 395 | mov r4, #0x00070000 |
391 | orr r6, r7, #0xff000000 @ mask 0xff070000 | 396 | orr r3, r4, #0xff000000 @ mask 0xff070000 |
392 | orr r7, r7, #0x41000000 @ val 0x41070000 | 397 | orr r4, r4, #0x41000000 @ val 0x41070000 |
393 | and r0, r9, r6 | 398 | and r0, r9, r3 |
394 | teq r0, r7 @ ARM CPU and ARMv6/v7? | 399 | teq r0, r4 @ ARM CPU and ARMv6/v7? |
395 | bne __fixup_smp_on_up @ no, assume UP | 400 | bne __fixup_smp_on_up @ no, assume UP |
396 | 401 | ||
397 | orr r6, r6, #0x0000ff00 | 402 | orr r3, r3, #0x0000ff00 |
398 | orr r6, r6, #0x000000f0 @ mask 0xff07fff0 | 403 | orr r3, r3, #0x000000f0 @ mask 0xff07fff0 |
399 | orr r7, r7, #0x0000b000 | 404 | orr r4, r4, #0x0000b000 |
400 | orr r7, r7, #0x00000020 @ val 0x4107b020 | 405 | orr r4, r4, #0x00000020 @ val 0x4107b020 |
401 | and r0, r9, r6 | 406 | and r0, r9, r3 |
402 | teq r0, r7 @ ARM 11MPCore? | 407 | teq r0, r4 @ ARM 11MPCore? |
403 | moveq pc, lr @ yes, assume SMP | 408 | moveq pc, lr @ yes, assume SMP |
404 | 409 | ||
405 | mrc p15, 0, r0, c0, c0, 5 @ read MPIDR | 410 | mrc p15, 0, r0, c0, c0, 5 @ read MPIDR |
@@ -408,15 +413,22 @@ __fixup_smp: | |||
408 | 413 | ||
409 | __fixup_smp_on_up: | 414 | __fixup_smp_on_up: |
410 | adr r0, 1f | 415 | adr r0, 1f |
411 | ldmia r0, {r3, r6, r7} | 416 | ldmia r0, {r3 - r5} |
412 | sub r3, r0, r3 | 417 | sub r3, r0, r3 |
413 | add r6, r6, r3 | 418 | add r4, r4, r3 |
414 | add r7, r7, r3 | 419 | add r5, r5, r3 |
415 | 2: cmp r6, r7 | 420 | 2: cmp r4, r5 |
416 | ldmia r6!, {r0, r4} | 421 | movhs pc, lr |
417 | strlo r4, [r0, r3] | 422 | ldmia r4!, {r0, r6} |
418 | blo 2b | 423 | ARM( str r6, [r0, r3] ) |
419 | mov pc, lr | 424 | THUMB( add r0, r0, r3 ) |
425 | #ifdef __ARMEB__ | ||
426 | THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. | ||
427 | #endif | ||
428 | THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords | ||
429 | THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. | ||
430 | THUMB( strh r6, [r0] ) | ||
431 | b 2b | ||
420 | ENDPROC(__fixup_smp) | 432 | ENDPROC(__fixup_smp) |
421 | 433 | ||
422 | .align | 434 | .align |