diff options
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/mmu.h | 8 | ||||
-rw-r--r-- | arch/arm/include/asm/mmu_context.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/tlbflush.h | 34 | ||||
-rw-r--r-- | arch/arm/include/asm/xen/events.h | 25 | ||||
-rw-r--r-- | arch/arm/include/uapi/asm/unistd.h | 2 |
5 files changed, 38 insertions, 33 deletions
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h index 9f77e7804f3b..e3d55547e755 100644 --- a/arch/arm/include/asm/mmu.h +++ b/arch/arm/include/asm/mmu.h | |||
@@ -5,15 +5,15 @@ | |||
5 | 5 | ||
6 | typedef struct { | 6 | typedef struct { |
7 | #ifdef CONFIG_CPU_HAS_ASID | 7 | #ifdef CONFIG_CPU_HAS_ASID |
8 | u64 id; | 8 | atomic64_t id; |
9 | #endif | 9 | #endif |
10 | unsigned int vmalloc_seq; | 10 | unsigned int vmalloc_seq; |
11 | } mm_context_t; | 11 | } mm_context_t; |
12 | 12 | ||
13 | #ifdef CONFIG_CPU_HAS_ASID | 13 | #ifdef CONFIG_CPU_HAS_ASID |
14 | #define ASID_BITS 8 | 14 | #define ASID_BITS 8 |
15 | #define ASID_MASK ((~0ULL) << ASID_BITS) | 15 | #define ASID_MASK ((~0ULL) << ASID_BITS) |
16 | #define ASID(mm) ((mm)->context.id & ~ASID_MASK) | 16 | #define ASID(mm) ((mm)->context.id.counter & ~ASID_MASK) |
17 | #else | 17 | #else |
18 | #define ASID(mm) (0) | 18 | #define ASID(mm) (0) |
19 | #endif | 19 | #endif |
@@ -26,7 +26,7 @@ typedef struct { | |||
26 | * modified for 2.6 by Hyok S. Choi <hyok.choi@samsung.com> | 26 | * modified for 2.6 by Hyok S. Choi <hyok.choi@samsung.com> |
27 | */ | 27 | */ |
28 | typedef struct { | 28 | typedef struct { |
29 | unsigned long end_brk; | 29 | unsigned long end_brk; |
30 | } mm_context_t; | 30 | } mm_context_t; |
31 | 31 | ||
32 | #endif | 32 | #endif |
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h index e1f644bc7cc5..863a6611323c 100644 --- a/arch/arm/include/asm/mmu_context.h +++ b/arch/arm/include/asm/mmu_context.h | |||
@@ -25,7 +25,7 @@ void __check_vmalloc_seq(struct mm_struct *mm); | |||
25 | #ifdef CONFIG_CPU_HAS_ASID | 25 | #ifdef CONFIG_CPU_HAS_ASID |
26 | 26 | ||
27 | void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk); | 27 | void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk); |
28 | #define init_new_context(tsk,mm) ({ mm->context.id = 0; }) | 28 | #define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; }) |
29 | 29 | ||
30 | #else /* !CONFIG_CPU_HAS_ASID */ | 30 | #else /* !CONFIG_CPU_HAS_ASID */ |
31 | 31 | ||
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 6e924d3a77eb..4db8c8820f0d 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h | |||
@@ -34,10 +34,13 @@ | |||
34 | #define TLB_V6_D_ASID (1 << 17) | 34 | #define TLB_V6_D_ASID (1 << 17) |
35 | #define TLB_V6_I_ASID (1 << 18) | 35 | #define TLB_V6_I_ASID (1 << 18) |
36 | 36 | ||
37 | #define TLB_V6_BP (1 << 19) | ||
38 | |||
37 | /* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */ | 39 | /* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */ |
38 | #define TLB_V7_UIS_PAGE (1 << 19) | 40 | #define TLB_V7_UIS_PAGE (1 << 20) |
39 | #define TLB_V7_UIS_FULL (1 << 20) | 41 | #define TLB_V7_UIS_FULL (1 << 21) |
40 | #define TLB_V7_UIS_ASID (1 << 21) | 42 | #define TLB_V7_UIS_ASID (1 << 22) |
43 | #define TLB_V7_UIS_BP (1 << 23) | ||
41 | 44 | ||
42 | #define TLB_BARRIER (1 << 28) | 45 | #define TLB_BARRIER (1 << 28) |
43 | #define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ | 46 | #define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ |
@@ -150,7 +153,8 @@ | |||
150 | #define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ | 153 | #define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ |
151 | TLB_V6_I_FULL | TLB_V6_D_FULL | \ | 154 | TLB_V6_I_FULL | TLB_V6_D_FULL | \ |
152 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | \ | 155 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | \ |
153 | TLB_V6_I_ASID | TLB_V6_D_ASID) | 156 | TLB_V6_I_ASID | TLB_V6_D_ASID | \ |
157 | TLB_V6_BP) | ||
154 | 158 | ||
155 | #ifdef CONFIG_CPU_TLB_V6 | 159 | #ifdef CONFIG_CPU_TLB_V6 |
156 | # define v6wbi_possible_flags v6wbi_tlb_flags | 160 | # define v6wbi_possible_flags v6wbi_tlb_flags |
@@ -166,9 +170,11 @@ | |||
166 | #endif | 170 | #endif |
167 | 171 | ||
168 | #define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ | 172 | #define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ |
169 | TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID) | 173 | TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | \ |
174 | TLB_V7_UIS_ASID | TLB_V7_UIS_BP) | ||
170 | #define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ | 175 | #define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ |
171 | TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID) | 176 | TLB_V6_U_FULL | TLB_V6_U_PAGE | \ |
177 | TLB_V6_U_ASID | TLB_V6_BP) | ||
172 | 178 | ||
173 | #ifdef CONFIG_CPU_TLB_V7 | 179 | #ifdef CONFIG_CPU_TLB_V7 |
174 | 180 | ||
@@ -430,6 +436,20 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) | |||
430 | } | 436 | } |
431 | } | 437 | } |
432 | 438 | ||
439 | static inline void local_flush_bp_all(void) | ||
440 | { | ||
441 | const int zero = 0; | ||
442 | const unsigned int __tlb_flag = __cpu_tlb_flags; | ||
443 | |||
444 | if (tlb_flag(TLB_V7_UIS_BP)) | ||
445 | asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero)); | ||
446 | else if (tlb_flag(TLB_V6_BP)) | ||
447 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); | ||
448 | |||
449 | if (tlb_flag(TLB_BARRIER)) | ||
450 | isb(); | ||
451 | } | ||
452 | |||
433 | /* | 453 | /* |
434 | * flush_pmd_entry | 454 | * flush_pmd_entry |
435 | * | 455 | * |
@@ -480,6 +500,7 @@ static inline void clean_pmd_entry(void *pmd) | |||
480 | #define flush_tlb_kernel_page local_flush_tlb_kernel_page | 500 | #define flush_tlb_kernel_page local_flush_tlb_kernel_page |
481 | #define flush_tlb_range local_flush_tlb_range | 501 | #define flush_tlb_range local_flush_tlb_range |
482 | #define flush_tlb_kernel_range local_flush_tlb_kernel_range | 502 | #define flush_tlb_kernel_range local_flush_tlb_kernel_range |
503 | #define flush_bp_all local_flush_bp_all | ||
483 | #else | 504 | #else |
484 | extern void flush_tlb_all(void); | 505 | extern void flush_tlb_all(void); |
485 | extern void flush_tlb_mm(struct mm_struct *mm); | 506 | extern void flush_tlb_mm(struct mm_struct *mm); |
@@ -487,6 +508,7 @@ extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr); | |||
487 | extern void flush_tlb_kernel_page(unsigned long kaddr); | 508 | extern void flush_tlb_kernel_page(unsigned long kaddr); |
488 | extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); | 509 | extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); |
489 | extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); | 510 | extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); |
511 | extern void flush_bp_all(void); | ||
490 | #endif | 512 | #endif |
491 | 513 | ||
492 | /* | 514 | /* |
diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h index 5c27696de14f..8b1f37bfeeec 100644 --- a/arch/arm/include/asm/xen/events.h +++ b/arch/arm/include/asm/xen/events.h | |||
@@ -2,6 +2,7 @@ | |||
2 | #define _ASM_ARM_XEN_EVENTS_H | 2 | #define _ASM_ARM_XEN_EVENTS_H |
3 | 3 | ||
4 | #include <asm/ptrace.h> | 4 | #include <asm/ptrace.h> |
5 | #include <asm/atomic.h> | ||
5 | 6 | ||
6 | enum ipi_vector { | 7 | enum ipi_vector { |
7 | XEN_PLACEHOLDER_VECTOR, | 8 | XEN_PLACEHOLDER_VECTOR, |
@@ -15,26 +16,8 @@ static inline int xen_irqs_disabled(struct pt_regs *regs) | |||
15 | return raw_irqs_disabled_flags(regs->ARM_cpsr); | 16 | return raw_irqs_disabled_flags(regs->ARM_cpsr); |
16 | } | 17 | } |
17 | 18 | ||
18 | /* | 19 | #define xchg_xen_ulong(ptr, val) atomic64_xchg(container_of((ptr), \ |
19 | * We cannot use xchg because it does not support 8-byte | 20 | atomic64_t, \ |
20 | * values. However it is safe to use {ldr,dtd}exd directly because all | 21 | counter), (val)) |
21 | * platforms which Xen can run on support those instructions. | ||
22 | */ | ||
23 | static inline xen_ulong_t xchg_xen_ulong(xen_ulong_t *ptr, xen_ulong_t val) | ||
24 | { | ||
25 | xen_ulong_t oldval; | ||
26 | unsigned int tmp; | ||
27 | |||
28 | wmb(); | ||
29 | asm volatile("@ xchg_xen_ulong\n" | ||
30 | "1: ldrexd %0, %H0, [%3]\n" | ||
31 | " strexd %1, %2, %H2, [%3]\n" | ||
32 | " teq %1, #0\n" | ||
33 | " bne 1b" | ||
34 | : "=&r" (oldval), "=&r" (tmp) | ||
35 | : "r" (val), "r" (ptr) | ||
36 | : "memory", "cc"); | ||
37 | return oldval; | ||
38 | } | ||
39 | 22 | ||
40 | #endif /* _ASM_ARM_XEN_EVENTS_H */ | 23 | #endif /* _ASM_ARM_XEN_EVENTS_H */ |
diff --git a/arch/arm/include/uapi/asm/unistd.h b/arch/arm/include/uapi/asm/unistd.h index 4da7cde70b5d..af33b44990ed 100644 --- a/arch/arm/include/uapi/asm/unistd.h +++ b/arch/arm/include/uapi/asm/unistd.h | |||
@@ -404,7 +404,7 @@ | |||
404 | #define __NR_setns (__NR_SYSCALL_BASE+375) | 404 | #define __NR_setns (__NR_SYSCALL_BASE+375) |
405 | #define __NR_process_vm_readv (__NR_SYSCALL_BASE+376) | 405 | #define __NR_process_vm_readv (__NR_SYSCALL_BASE+376) |
406 | #define __NR_process_vm_writev (__NR_SYSCALL_BASE+377) | 406 | #define __NR_process_vm_writev (__NR_SYSCALL_BASE+377) |
407 | /* 378 for kcmp */ | 407 | #define __NR_kcmp (__NR_SYSCALL_BASE+378) |
408 | #define __NR_finit_module (__NR_SYSCALL_BASE+379) | 408 | #define __NR_finit_module (__NR_SYSCALL_BASE+379) |
409 | 409 | ||
410 | /* | 410 | /* |