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-rw-r--r--arch/arm/include/asm/arch_timer.h11
-rw-r--r--arch/arm/include/asm/assembler.h17
-rw-r--r--arch/arm/include/asm/cp15.h19
-rw-r--r--arch/arm/include/asm/cputype.h45
-rw-r--r--arch/arm/include/asm/div64.h2
-rw-r--r--arch/arm/include/asm/glue-cache.h27
-rw-r--r--arch/arm/include/asm/glue-df.h8
-rw-r--r--arch/arm/include/asm/glue-proc.h9
-rw-r--r--arch/arm/include/asm/hardware/iop3xx.h3
-rw-r--r--arch/arm/include/asm/hardware/pci_v3.h186
-rw-r--r--arch/arm/include/asm/hugetlb-3level.h71
-rw-r--r--arch/arm/include/asm/hugetlb.h84
-rw-r--r--arch/arm/include/asm/io.h8
-rw-r--r--arch/arm/include/asm/irqflags.h22
-rw-r--r--arch/arm/include/asm/kvm_arch_timer.h85
-rw-r--r--arch/arm/include/asm/kvm_arm.h1
-rw-r--r--arch/arm/include/asm/kvm_asm.h24
-rw-r--r--arch/arm/include/asm/kvm_emulate.h5
-rw-r--r--arch/arm/include/asm/kvm_host.h13
-rw-r--r--arch/arm/include/asm/kvm_vgic.h220
-rw-r--r--arch/arm/include/asm/mach/arch.h10
-rw-r--r--arch/arm/include/asm/mach/pci.h17
-rw-r--r--arch/arm/include/asm/memory.h24
-rw-r--r--arch/arm/include/asm/mmu_context.h23
-rw-r--r--arch/arm/include/asm/mpu.h76
-rw-r--r--arch/arm/include/asm/page.h2
-rw-r--r--arch/arm/include/asm/pgtable-3level-hwdef.h24
-rw-r--r--arch/arm/include/asm/pgtable-3level.h96
-rw-r--r--arch/arm/include/asm/pgtable-nommu.h2
-rw-r--r--arch/arm/include/asm/pgtable.h10
-rw-r--r--arch/arm/include/asm/proc-fns.h30
-rw-r--r--arch/arm/include/asm/psci.h9
-rw-r--r--arch/arm/include/asm/ptrace.h4
-rw-r--r--arch/arm/include/asm/sched_clock.h18
-rw-r--r--arch/arm/include/asm/smp.h5
-rw-r--r--arch/arm/include/asm/smp_plat.h22
-rw-r--r--arch/arm/include/asm/smp_scu.h13
-rw-r--r--arch/arm/include/asm/spinlock.h25
-rw-r--r--arch/arm/include/asm/suspend.h5
-rw-r--r--arch/arm/include/asm/system_info.h1
-rw-r--r--arch/arm/include/asm/system_misc.h3
-rw-r--r--arch/arm/include/asm/thread_info.h2
-rw-r--r--arch/arm/include/asm/tlb.h6
-rw-r--r--arch/arm/include/asm/tlbflush.h27
-rw-r--r--arch/arm/include/asm/tls.h40
-rw-r--r--arch/arm/include/asm/v7m.h44
-rw-r--r--arch/arm/include/asm/xen/hypercall.h1
-rw-r--r--arch/arm/include/asm/xen/page.h3
-rw-r--r--arch/arm/include/debug/imx-uart.h10
-rw-r--r--arch/arm/include/debug/keystone.S43
-rw-r--r--arch/arm/include/debug/mvebu.S5
-rw-r--r--arch/arm/include/debug/nspire.S28
-rw-r--r--arch/arm/include/debug/rockchip.S42
-rw-r--r--arch/arm/include/debug/sti.S61
-rw-r--r--arch/arm/include/debug/u300.S18
-rw-r--r--arch/arm/include/debug/vexpress.S10
-rw-r--r--arch/arm/include/uapi/asm/hwcap.h2
-rw-r--r--arch/arm/include/uapi/asm/ptrace.h35
58 files changed, 1022 insertions, 634 deletions
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 7c1bfc0aea0c..e406d575c94f 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -80,15 +80,6 @@ static inline u32 arch_timer_get_cntfrq(void)
80 return val; 80 return val;
81} 81}
82 82
83static inline u64 arch_counter_get_cntpct(void)
84{
85 u64 cval;
86
87 isb();
88 asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
89 return cval;
90}
91
92static inline u64 arch_counter_get_cntvct(void) 83static inline u64 arch_counter_get_cntvct(void)
93{ 84{
94 u64 cval; 85 u64 cval;
@@ -98,7 +89,7 @@ static inline u64 arch_counter_get_cntvct(void)
98 return cval; 89 return cval;
99} 90}
100 91
101static inline void __cpuinit arch_counter_set_user_access(void) 92static inline void arch_counter_set_user_access(void)
102{ 93{
103 u32 cntkctl; 94 u32 cntkctl;
104 95
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 05ee9eebad6b..a5fef710af32 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -136,7 +136,11 @@
136 * assumes FIQs are enabled, and that the processor is in SVC mode. 136 * assumes FIQs are enabled, and that the processor is in SVC mode.
137 */ 137 */
138 .macro save_and_disable_irqs, oldcpsr 138 .macro save_and_disable_irqs, oldcpsr
139#ifdef CONFIG_CPU_V7M
140 mrs \oldcpsr, primask
141#else
139 mrs \oldcpsr, cpsr 142 mrs \oldcpsr, cpsr
143#endif
140 disable_irq 144 disable_irq
141 .endm 145 .endm
142 146
@@ -150,7 +154,11 @@
150 * guarantee that this will preserve the flags. 154 * guarantee that this will preserve the flags.
151 */ 155 */
152 .macro restore_irqs_notrace, oldcpsr 156 .macro restore_irqs_notrace, oldcpsr
157#ifdef CONFIG_CPU_V7M
158 msr primask, \oldcpsr
159#else
153 msr cpsr_c, \oldcpsr 160 msr cpsr_c, \oldcpsr
161#endif
154 .endm 162 .endm
155 163
156 .macro restore_irqs, oldcpsr 164 .macro restore_irqs, oldcpsr
@@ -229,7 +237,14 @@
229#endif 237#endif
230 .endm 238 .endm
231 239
232#ifdef CONFIG_THUMB2_KERNEL 240#if defined(CONFIG_CPU_V7M)
241 /*
242 * setmode is used to assert to be in svc mode during boot. For v7-M
243 * this is done in __v7m_setup, so setmode can be empty here.
244 */
245 .macro setmode, mode, reg
246 .endm
247#elif defined(CONFIG_THUMB2_KERNEL)
233 .macro setmode, mode, reg 248 .macro setmode, mode, reg
234 mov \reg, #\mode 249 mov \reg, #\mode
235 msr cpsr_c, \reg 250 msr cpsr_c, \reg
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index 1f3262e99d81..6493802f880a 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -23,6 +23,11 @@
23#define CR_RR (1 << 14) /* Round Robin cache replacement */ 23#define CR_RR (1 << 14) /* Round Robin cache replacement */
24#define CR_L4 (1 << 15) /* LDR pc can set T bit */ 24#define CR_L4 (1 << 15) /* LDR pc can set T bit */
25#define CR_DT (1 << 16) 25#define CR_DT (1 << 16)
26#ifdef CONFIG_MMU
27#define CR_HA (1 << 17) /* Hardware management of Access Flag */
28#else
29#define CR_BR (1 << 17) /* MPU Background region enable (PMSA) */
30#endif
26#define CR_IT (1 << 18) 31#define CR_IT (1 << 18)
27#define CR_ST (1 << 19) 32#define CR_ST (1 << 19)
28#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ 33#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
@@ -61,6 +66,20 @@ static inline void set_cr(unsigned int val)
61 isb(); 66 isb();
62} 67}
63 68
69static inline unsigned int get_auxcr(void)
70{
71 unsigned int val;
72 asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val));
73 return val;
74}
75
76static inline void set_auxcr(unsigned int val)
77{
78 asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
79 : : "r" (val));
80 isb();
81}
82
64#ifndef CONFIG_SMP 83#ifndef CONFIG_SMP
65extern void adjust_cr(unsigned long mask, unsigned long set); 84extern void adjust_cr(unsigned long mask, unsigned long set);
66#endif 85#endif
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index dba62cb1ad08..8c25dc4e9851 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -8,8 +8,25 @@
8#define CPUID_CACHETYPE 1 8#define CPUID_CACHETYPE 1
9#define CPUID_TCM 2 9#define CPUID_TCM 2
10#define CPUID_TLBTYPE 3 10#define CPUID_TLBTYPE 3
11#define CPUID_MPUIR 4
11#define CPUID_MPIDR 5 12#define CPUID_MPIDR 5
12 13
14#ifdef CONFIG_CPU_V7M
15#define CPUID_EXT_PFR0 0x40
16#define CPUID_EXT_PFR1 0x44
17#define CPUID_EXT_DFR0 0x48
18#define CPUID_EXT_AFR0 0x4c
19#define CPUID_EXT_MMFR0 0x50
20#define CPUID_EXT_MMFR1 0x54
21#define CPUID_EXT_MMFR2 0x58
22#define CPUID_EXT_MMFR3 0x5c
23#define CPUID_EXT_ISAR0 0x60
24#define CPUID_EXT_ISAR1 0x64
25#define CPUID_EXT_ISAR2 0x68
26#define CPUID_EXT_ISAR3 0x6c
27#define CPUID_EXT_ISAR4 0x70
28#define CPUID_EXT_ISAR5 0x74
29#else
13#define CPUID_EXT_PFR0 "c1, 0" 30#define CPUID_EXT_PFR0 "c1, 0"
14#define CPUID_EXT_PFR1 "c1, 1" 31#define CPUID_EXT_PFR1 "c1, 1"
15#define CPUID_EXT_DFR0 "c1, 2" 32#define CPUID_EXT_DFR0 "c1, 2"
@@ -24,6 +41,7 @@
24#define CPUID_EXT_ISAR3 "c2, 3" 41#define CPUID_EXT_ISAR3 "c2, 3"
25#define CPUID_EXT_ISAR4 "c2, 4" 42#define CPUID_EXT_ISAR4 "c2, 4"
26#define CPUID_EXT_ISAR5 "c2, 5" 43#define CPUID_EXT_ISAR5 "c2, 5"
44#endif
27 45
28#define MPIDR_SMP_BITMASK (0x3 << 30) 46#define MPIDR_SMP_BITMASK (0x3 << 30)
29#define MPIDR_SMP_VALUE (0x2 << 30) 47#define MPIDR_SMP_VALUE (0x2 << 30)
@@ -81,7 +99,23 @@ extern unsigned int processor_id;
81 __val; \ 99 __val; \
82 }) 100 })
83 101
84#else /* ifdef CONFIG_CPU_CP15 */ 102#elif defined(CONFIG_CPU_V7M)
103
104#include <asm/io.h>
105#include <asm/v7m.h>
106
107#define read_cpuid(reg) \
108 ({ \
109 WARN_ON_ONCE(1); \
110 0; \
111 })
112
113static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
114{
115 return readl(BASEADDR_V7M_SCB + offset);
116}
117
118#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
85 119
86/* 120/*
87 * read_cpuid and read_cpuid_ext should only ever be called on machines that 121 * read_cpuid and read_cpuid_ext should only ever be called on machines that
@@ -108,7 +142,14 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
108 return read_cpuid(CPUID_ID); 142 return read_cpuid(CPUID_ID);
109} 143}
110 144
111#else /* ifdef CONFIG_CPU_CP15 */ 145#elif defined(CONFIG_CPU_V7M)
146
147static inline unsigned int __attribute_const__ read_cpuid_id(void)
148{
149 return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
150}
151
152#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
112 153
113static inline unsigned int __attribute_const__ read_cpuid_id(void) 154static inline unsigned int __attribute_const__ read_cpuid_id(void)
114{ 155{
diff --git a/arch/arm/include/asm/div64.h b/arch/arm/include/asm/div64.h
index fe92ccf1d0b0..191ada6e4d2d 100644
--- a/arch/arm/include/asm/div64.h
+++ b/arch/arm/include/asm/div64.h
@@ -46,7 +46,7 @@
46 __rem; \ 46 __rem; \
47}) 47})
48 48
49#if __GNUC__ < 4 49#if __GNUC__ < 4 || !defined(CONFIG_AEABI)
50 50
51/* 51/*
52 * gcc versions earlier than 4.0 are simply too problematic for the 52 * gcc versions earlier than 4.0 are simply too problematic for the
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index ea289e1435e7..c81adc08b3fb 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -117,10 +117,37 @@
117# endif 117# endif
118#endif 118#endif
119 119
120#if defined(CONFIG_CPU_V7M)
121# ifdef _CACHE
122# define MULTI_CACHE 1
123# else
124# define _CACHE nop
125# endif
126#endif
127
120#if !defined(_CACHE) && !defined(MULTI_CACHE) 128#if !defined(_CACHE) && !defined(MULTI_CACHE)
121#error Unknown cache maintenance model 129#error Unknown cache maintenance model
122#endif 130#endif
123 131
132#ifndef __ASSEMBLER__
133extern inline void nop_flush_icache_all(void) { }
134extern inline void nop_flush_kern_cache_all(void) { }
135extern inline void nop_flush_kern_cache_louis(void) { }
136extern inline void nop_flush_user_cache_all(void) { }
137extern inline void nop_flush_user_cache_range(unsigned long a,
138 unsigned long b, unsigned int c) { }
139
140extern inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
141extern inline int nop_coherent_user_range(unsigned long a,
142 unsigned long b) { return 0; }
143extern inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
144
145extern inline void nop_dma_flush_range(const void *a, const void *b) { }
146
147extern inline void nop_dma_map_area(const void *s, size_t l, int f) { }
148extern inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
149#endif
150
124#ifndef MULTI_CACHE 151#ifndef MULTI_CACHE
125#define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all) 152#define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all)
126#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) 153#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h
index b6e9f2c108b5..6b70f1b46a6e 100644
--- a/arch/arm/include/asm/glue-df.h
+++ b/arch/arm/include/asm/glue-df.h
@@ -95,6 +95,14 @@
95# endif 95# endif
96#endif 96#endif
97 97
98#ifdef CONFIG_CPU_ABRT_NOMMU
99# ifdef CPU_DABORT_HANDLER
100# define MULTI_DABORT 1
101# else
102# define CPU_DABORT_HANDLER nommu_early_abort
103# endif
104#endif
105
98#ifndef CPU_DABORT_HANDLER 106#ifndef CPU_DABORT_HANDLER
99#error Unknown data abort handler type 107#error Unknown data abort handler type
100#endif 108#endif
diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h
index 8017e94acc5e..74a8b84f3cb1 100644
--- a/arch/arm/include/asm/glue-proc.h
+++ b/arch/arm/include/asm/glue-proc.h
@@ -230,6 +230,15 @@
230# endif 230# endif
231#endif 231#endif
232 232
233#ifdef CONFIG_CPU_V7M
234# ifdef CPU_NAME
235# undef MULTI_CPU
236# define MULTI_CPU
237# else
238# define CPU_NAME cpu_v7m
239# endif
240#endif
241
233#ifdef CONFIG_CPU_PJ4B 242#ifdef CONFIG_CPU_PJ4B
234# ifdef CPU_NAME 243# ifdef CPU_NAME
235# undef MULTI_CPU 244# undef MULTI_CPU
diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index ed94b1a366ae..423744bf18eb 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -223,11 +223,12 @@ extern int iop3xx_get_init_atu(void);
223#ifndef __ASSEMBLY__ 223#ifndef __ASSEMBLY__
224 224
225#include <linux/types.h> 225#include <linux/types.h>
226#include <linux/reboot.h>
226 227
227void iop3xx_map_io(void); 228void iop3xx_map_io(void);
228void iop_init_cp6_handler(void); 229void iop_init_cp6_handler(void);
229void iop_init_time(unsigned long tickrate); 230void iop_init_time(unsigned long tickrate);
230void iop3xx_restart(char, const char *); 231void iop3xx_restart(enum reboot_mode, const char *);
231 232
232static inline u32 read_tmr0(void) 233static inline u32 read_tmr0(void)
233{ 234{
diff --git a/arch/arm/include/asm/hardware/pci_v3.h b/arch/arm/include/asm/hardware/pci_v3.h
deleted file mode 100644
index 2811c7e2cfdf..000000000000
--- a/arch/arm/include/asm/hardware/pci_v3.h
+++ /dev/null
@@ -1,186 +0,0 @@
1/*
2 * arch/arm/include/asm/hardware/pci_v3.h
3 *
4 * Internal header file PCI V3 chip
5 *
6 * Copyright (C) ARM Limited
7 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef ASM_ARM_HARDWARE_PCI_V3_H
24#define ASM_ARM_HARDWARE_PCI_V3_H
25
26/* -------------------------------------------------------------------------------
27 * V3 Local Bus to PCI Bridge definitions
28 * -------------------------------------------------------------------------------
29 * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
30 * All V3 register names are prefaced by V3_ to avoid clashing with any other
31 * PCI definitions. Their names match the user's manual.
32 *
33 * I'm assuming that I20 is disabled.
34 *
35 */
36#define V3_PCI_VENDOR 0x00000000
37#define V3_PCI_DEVICE 0x00000002
38#define V3_PCI_CMD 0x00000004
39#define V3_PCI_STAT 0x00000006
40#define V3_PCI_CC_REV 0x00000008
41#define V3_PCI_HDR_CFG 0x0000000C
42#define V3_PCI_IO_BASE 0x00000010
43#define V3_PCI_BASE0 0x00000014
44#define V3_PCI_BASE1 0x00000018
45#define V3_PCI_SUB_VENDOR 0x0000002C
46#define V3_PCI_SUB_ID 0x0000002E
47#define V3_PCI_ROM 0x00000030
48#define V3_PCI_BPARAM 0x0000003C
49#define V3_PCI_MAP0 0x00000040
50#define V3_PCI_MAP1 0x00000044
51#define V3_PCI_INT_STAT 0x00000048
52#define V3_PCI_INT_CFG 0x0000004C
53#define V3_LB_BASE0 0x00000054
54#define V3_LB_BASE1 0x00000058
55#define V3_LB_MAP0 0x0000005E
56#define V3_LB_MAP1 0x00000062
57#define V3_LB_BASE2 0x00000064
58#define V3_LB_MAP2 0x00000066
59#define V3_LB_SIZE 0x00000068
60#define V3_LB_IO_BASE 0x0000006E
61#define V3_FIFO_CFG 0x00000070
62#define V3_FIFO_PRIORITY 0x00000072
63#define V3_FIFO_STAT 0x00000074
64#define V3_LB_ISTAT 0x00000076
65#define V3_LB_IMASK 0x00000077
66#define V3_SYSTEM 0x00000078
67#define V3_LB_CFG 0x0000007A
68#define V3_PCI_CFG 0x0000007C
69#define V3_DMA_PCI_ADR0 0x00000080
70#define V3_DMA_PCI_ADR1 0x00000090
71#define V3_DMA_LOCAL_ADR0 0x00000084
72#define V3_DMA_LOCAL_ADR1 0x00000094
73#define V3_DMA_LENGTH0 0x00000088
74#define V3_DMA_LENGTH1 0x00000098
75#define V3_DMA_CSR0 0x0000008B
76#define V3_DMA_CSR1 0x0000009B
77#define V3_DMA_CTLB_ADR0 0x0000008C
78#define V3_DMA_CTLB_ADR1 0x0000009C
79#define V3_DMA_DELAY 0x000000E0
80#define V3_MAIL_DATA 0x000000C0
81#define V3_PCI_MAIL_IEWR 0x000000D0
82#define V3_PCI_MAIL_IERD 0x000000D2
83#define V3_LB_MAIL_IEWR 0x000000D4
84#define V3_LB_MAIL_IERD 0x000000D6
85#define V3_MAIL_WR_STAT 0x000000D8
86#define V3_MAIL_RD_STAT 0x000000DA
87#define V3_QBA_MAP 0x000000DC
88
89/* PCI COMMAND REGISTER bits
90 */
91#define V3_COMMAND_M_FBB_EN (1 << 9)
92#define V3_COMMAND_M_SERR_EN (1 << 8)
93#define V3_COMMAND_M_PAR_EN (1 << 6)
94#define V3_COMMAND_M_MASTER_EN (1 << 2)
95#define V3_COMMAND_M_MEM_EN (1 << 1)
96#define V3_COMMAND_M_IO_EN (1 << 0)
97
98/* SYSTEM REGISTER bits
99 */
100#define V3_SYSTEM_M_RST_OUT (1 << 15)
101#define V3_SYSTEM_M_LOCK (1 << 14)
102
103/* PCI_CFG bits
104 */
105#define V3_PCI_CFG_M_I2O_EN (1 << 15)
106#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
107#define V3_PCI_CFG_M_IO_DIS (1 << 13)
108#define V3_PCI_CFG_M_EN3V (1 << 12)
109#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
110#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
111#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
112
113/* PCI_BASE register bits (PCI -> Local Bus)
114 */
115#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
116#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
117#define V3_PCI_BASE_M_PREFETCH (1 << 3)
118#define V3_PCI_BASE_M_TYPE (3 << 1)
119#define V3_PCI_BASE_M_IO (1 << 0)
120
121/* PCI MAP register bits (PCI -> Local bus)
122 */
123#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
124#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
125#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
126#define V3_PCI_MAP_M_SWAP (3 << 8)
127#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
128#define V3_PCI_MAP_M_REG_EN (1 << 1)
129#define V3_PCI_MAP_M_ENABLE (1 << 0)
130
131/*
132 * LB_BASE0,1 register bits (Local bus -> PCI)
133 */
134#define V3_LB_BASE_ADR_BASE 0xfff00000
135#define V3_LB_BASE_SWAP (3 << 8)
136#define V3_LB_BASE_ADR_SIZE (15 << 4)
137#define V3_LB_BASE_PREFETCH (1 << 3)
138#define V3_LB_BASE_ENABLE (1 << 0)
139
140#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
141#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
142#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
143#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
144#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
145#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
146#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
147#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
148#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
149#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
150#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
151#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
152
153#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
154
155/*
156 * LB_MAP0,1 register bits (Local bus -> PCI)
157 */
158#define V3_LB_MAP_MAP_ADR 0xfff0
159#define V3_LB_MAP_TYPE (7 << 1)
160#define V3_LB_MAP_AD_LOW_EN (1 << 0)
161
162#define V3_LB_MAP_TYPE_IACK (0 << 1)
163#define V3_LB_MAP_TYPE_IO (1 << 1)
164#define V3_LB_MAP_TYPE_MEM (3 << 1)
165#define V3_LB_MAP_TYPE_CONFIG (5 << 1)
166#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
167
168#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
169
170/*
171 * LB_BASE2 register bits (Local bus -> PCI IO)
172 */
173#define V3_LB_BASE2_ADR_BASE 0xff00
174#define V3_LB_BASE2_SWAP (3 << 6)
175#define V3_LB_BASE2_ENABLE (1 << 0)
176
177#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
178
179/*
180 * LB_MAP2 register bits (Local bus -> PCI IO)
181 */
182#define V3_LB_MAP2_MAP_ADR 0xff00
183
184#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
185
186#endif
diff --git a/arch/arm/include/asm/hugetlb-3level.h b/arch/arm/include/asm/hugetlb-3level.h
new file mode 100644
index 000000000000..d4014fbe5ea3
--- /dev/null
+++ b/arch/arm/include/asm/hugetlb-3level.h
@@ -0,0 +1,71 @@
1/*
2 * arch/arm/include/asm/hugetlb-3level.h
3 *
4 * Copyright (C) 2012 ARM Ltd.
5 *
6 * Based on arch/x86/include/asm/hugetlb.h.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef _ASM_ARM_HUGETLB_3LEVEL_H
23#define _ASM_ARM_HUGETLB_3LEVEL_H
24
25
26/*
27 * If our huge pte is non-zero then mark the valid bit.
28 * This allows pte_present(huge_ptep_get(ptep)) to return true for non-zero
29 * ptes.
30 * (The valid bit is automatically cleared by set_pte_at for PROT_NONE ptes).
31 */
32static inline pte_t huge_ptep_get(pte_t *ptep)
33{
34 pte_t retval = *ptep;
35 if (pte_val(retval))
36 pte_val(retval) |= L_PTE_VALID;
37 return retval;
38}
39
40static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
41 pte_t *ptep, pte_t pte)
42{
43 set_pte_at(mm, addr, ptep, pte);
44}
45
46static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
47 unsigned long addr, pte_t *ptep)
48{
49 ptep_clear_flush(vma, addr, ptep);
50}
51
52static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
53 unsigned long addr, pte_t *ptep)
54{
55 ptep_set_wrprotect(mm, addr, ptep);
56}
57
58static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
59 unsigned long addr, pte_t *ptep)
60{
61 return ptep_get_and_clear(mm, addr, ptep);
62}
63
64static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
65 unsigned long addr, pte_t *ptep,
66 pte_t pte, int dirty)
67{
68 return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
69}
70
71#endif /* _ASM_ARM_HUGETLB_3LEVEL_H */
diff --git a/arch/arm/include/asm/hugetlb.h b/arch/arm/include/asm/hugetlb.h
new file mode 100644
index 000000000000..1f1b1cd112f3
--- /dev/null
+++ b/arch/arm/include/asm/hugetlb.h
@@ -0,0 +1,84 @@
1/*
2 * arch/arm/include/asm/hugetlb.h
3 *
4 * Copyright (C) 2012 ARM Ltd.
5 *
6 * Based on arch/x86/include/asm/hugetlb.h
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef _ASM_ARM_HUGETLB_H
23#define _ASM_ARM_HUGETLB_H
24
25#include <asm/page.h>
26#include <asm-generic/hugetlb.h>
27
28#include <asm/hugetlb-3level.h>
29
30static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
31 unsigned long addr, unsigned long end,
32 unsigned long floor,
33 unsigned long ceiling)
34{
35 free_pgd_range(tlb, addr, end, floor, ceiling);
36}
37
38
39static inline int is_hugepage_only_range(struct mm_struct *mm,
40 unsigned long addr, unsigned long len)
41{
42 return 0;
43}
44
45static inline int prepare_hugepage_range(struct file *file,
46 unsigned long addr, unsigned long len)
47{
48 struct hstate *h = hstate_file(file);
49 if (len & ~huge_page_mask(h))
50 return -EINVAL;
51 if (addr & ~huge_page_mask(h))
52 return -EINVAL;
53 return 0;
54}
55
56static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
57{
58}
59
60static inline int huge_pte_none(pte_t pte)
61{
62 return pte_none(pte);
63}
64
65static inline pte_t huge_pte_wrprotect(pte_t pte)
66{
67 return pte_wrprotect(pte);
68}
69
70static inline int arch_prepare_hugepage(struct page *page)
71{
72 return 0;
73}
74
75static inline void arch_release_hugepage(struct page *page)
76{
77}
78
79static inline void arch_clear_hugepage_flags(struct page *page)
80{
81 clear_bit(PG_dcache_clean, &page->flags);
82}
83
84#endif /* _ASM_ARM_HUGETLB_H */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 652b56086de7..d070741b2b37 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -130,16 +130,16 @@ static inline u32 __raw_readl(const volatile void __iomem *addr)
130 */ 130 */
131extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long, 131extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
132 size_t, unsigned int, void *); 132 size_t, unsigned int, void *);
133extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int, 133extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
134 void *); 134 void *);
135 135
136extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int); 136extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
137extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int); 137extern void __iomem *__arm_ioremap(phys_addr_t, size_t, unsigned int);
138extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached); 138extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
139extern void __iounmap(volatile void __iomem *addr); 139extern void __iounmap(volatile void __iomem *addr);
140extern void __arm_iounmap(volatile void __iomem *addr); 140extern void __arm_iounmap(volatile void __iomem *addr);
141 141
142extern void __iomem * (*arch_ioremap_caller)(unsigned long, size_t, 142extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
143 unsigned int, void *); 143 unsigned int, void *);
144extern void (*arch_iounmap)(volatile void __iomem *); 144extern void (*arch_iounmap)(volatile void __iomem *);
145 145
diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h
index 1e6cca55c750..3b763d6652a0 100644
--- a/arch/arm/include/asm/irqflags.h
+++ b/arch/arm/include/asm/irqflags.h
@@ -8,6 +8,16 @@
8/* 8/*
9 * CPU interrupt mask handling. 9 * CPU interrupt mask handling.
10 */ 10 */
11#ifdef CONFIG_CPU_V7M
12#define IRQMASK_REG_NAME_R "primask"
13#define IRQMASK_REG_NAME_W "primask"
14#define IRQMASK_I_BIT 1
15#else
16#define IRQMASK_REG_NAME_R "cpsr"
17#define IRQMASK_REG_NAME_W "cpsr_c"
18#define IRQMASK_I_BIT PSR_I_BIT
19#endif
20
11#if __LINUX_ARM_ARCH__ >= 6 21#if __LINUX_ARM_ARCH__ >= 6
12 22
13static inline unsigned long arch_local_irq_save(void) 23static inline unsigned long arch_local_irq_save(void)
@@ -15,7 +25,7 @@ static inline unsigned long arch_local_irq_save(void)
15 unsigned long flags; 25 unsigned long flags;
16 26
17 asm volatile( 27 asm volatile(
18 " mrs %0, cpsr @ arch_local_irq_save\n" 28 " mrs %0, " IRQMASK_REG_NAME_R " @ arch_local_irq_save\n"
19 " cpsid i" 29 " cpsid i"
20 : "=r" (flags) : : "memory", "cc"); 30 : "=r" (flags) : : "memory", "cc");
21 return flags; 31 return flags;
@@ -129,7 +139,7 @@ static inline unsigned long arch_local_save_flags(void)
129{ 139{
130 unsigned long flags; 140 unsigned long flags;
131 asm volatile( 141 asm volatile(
132 " mrs %0, cpsr @ local_save_flags" 142 " mrs %0, " IRQMASK_REG_NAME_R " @ local_save_flags"
133 : "=r" (flags) : : "memory", "cc"); 143 : "=r" (flags) : : "memory", "cc");
134 return flags; 144 return flags;
135} 145}
@@ -140,7 +150,7 @@ static inline unsigned long arch_local_save_flags(void)
140static inline void arch_local_irq_restore(unsigned long flags) 150static inline void arch_local_irq_restore(unsigned long flags)
141{ 151{
142 asm volatile( 152 asm volatile(
143 " msr cpsr_c, %0 @ local_irq_restore" 153 " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore"
144 : 154 :
145 : "r" (flags) 155 : "r" (flags)
146 : "memory", "cc"); 156 : "memory", "cc");
@@ -148,8 +158,8 @@ static inline void arch_local_irq_restore(unsigned long flags)
148 158
149static inline int arch_irqs_disabled_flags(unsigned long flags) 159static inline int arch_irqs_disabled_flags(unsigned long flags)
150{ 160{
151 return flags & PSR_I_BIT; 161 return flags & IRQMASK_I_BIT;
152} 162}
153 163
154#endif 164#endif /* ifdef __KERNEL__ */
155#endif 165#endif /* ifndef __ASM_ARM_IRQFLAGS_H */
diff --git a/arch/arm/include/asm/kvm_arch_timer.h b/arch/arm/include/asm/kvm_arch_timer.h
deleted file mode 100644
index 68cb9e1dfb81..000000000000
--- a/arch/arm/include/asm/kvm_arch_timer.h
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __ASM_ARM_KVM_ARCH_TIMER_H
20#define __ASM_ARM_KVM_ARCH_TIMER_H
21
22#include <linux/clocksource.h>
23#include <linux/hrtimer.h>
24#include <linux/workqueue.h>
25
26struct arch_timer_kvm {
27#ifdef CONFIG_KVM_ARM_TIMER
28 /* Is the timer enabled */
29 bool enabled;
30
31 /* Virtual offset */
32 cycle_t cntvoff;
33#endif
34};
35
36struct arch_timer_cpu {
37#ifdef CONFIG_KVM_ARM_TIMER
38 /* Registers: control register, timer value */
39 u32 cntv_ctl; /* Saved/restored */
40 cycle_t cntv_cval; /* Saved/restored */
41
42 /*
43 * Anything that is not used directly from assembly code goes
44 * here.
45 */
46
47 /* Background timer used when the guest is not running */
48 struct hrtimer timer;
49
50 /* Work queued with the above timer expires */
51 struct work_struct expired;
52
53 /* Background timer active */
54 bool armed;
55
56 /* Timer IRQ */
57 const struct kvm_irq_level *irq;
58#endif
59};
60
61#ifdef CONFIG_KVM_ARM_TIMER
62int kvm_timer_hyp_init(void);
63int kvm_timer_init(struct kvm *kvm);
64void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu);
65void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu);
66void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu);
67void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu);
68#else
69static inline int kvm_timer_hyp_init(void)
70{
71 return 0;
72};
73
74static inline int kvm_timer_init(struct kvm *kvm)
75{
76 return 0;
77}
78
79static inline void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) {}
80static inline void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu) {}
81static inline void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu) {}
82static inline void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu) {}
83#endif
84
85#endif
diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
index 124623e5ef14..64e96960de29 100644
--- a/arch/arm/include/asm/kvm_arm.h
+++ b/arch/arm/include/asm/kvm_arm.h
@@ -135,7 +135,6 @@
135#define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1ULL) 135#define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1ULL)
136#define PTRS_PER_S2_PGD (1ULL << (KVM_PHYS_SHIFT - 30)) 136#define PTRS_PER_S2_PGD (1ULL << (KVM_PHYS_SHIFT - 30))
137#define S2_PGD_ORDER get_order(PTRS_PER_S2_PGD * sizeof(pgd_t)) 137#define S2_PGD_ORDER get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
138#define S2_PGD_SIZE (1 << S2_PGD_ORDER)
139 138
140/* Virtualization Translation Control Register (VTCR) bits */ 139/* Virtualization Translation Control Register (VTCR) bits */
141#define VTCR_SH0 (3 << 12) 140#define VTCR_SH0 (3 << 12)
diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
index 18d50322a9e2..a2f43ddcc300 100644
--- a/arch/arm/include/asm/kvm_asm.h
+++ b/arch/arm/include/asm/kvm_asm.h
@@ -37,16 +37,18 @@
37#define c5_AIFSR 15 /* Auxilary Instrunction Fault Status R */ 37#define c5_AIFSR 15 /* Auxilary Instrunction Fault Status R */
38#define c6_DFAR 16 /* Data Fault Address Register */ 38#define c6_DFAR 16 /* Data Fault Address Register */
39#define c6_IFAR 17 /* Instruction Fault Address Register */ 39#define c6_IFAR 17 /* Instruction Fault Address Register */
40#define c9_L2CTLR 18 /* Cortex A15 L2 Control Register */ 40#define c7_PAR 18 /* Physical Address Register */
41#define c10_PRRR 19 /* Primary Region Remap Register */ 41#define c7_PAR_high 19 /* PAR top 32 bits */
42#define c10_NMRR 20 /* Normal Memory Remap Register */ 42#define c9_L2CTLR 20 /* Cortex A15 L2 Control Register */
43#define c12_VBAR 21 /* Vector Base Address Register */ 43#define c10_PRRR 21 /* Primary Region Remap Register */
44#define c13_CID 22 /* Context ID Register */ 44#define c10_NMRR 22 /* Normal Memory Remap Register */
45#define c13_TID_URW 23 /* Thread ID, User R/W */ 45#define c12_VBAR 23 /* Vector Base Address Register */
46#define c13_TID_URO 24 /* Thread ID, User R/O */ 46#define c13_CID 24 /* Context ID Register */
47#define c13_TID_PRIV 25 /* Thread ID, Privileged */ 47#define c13_TID_URW 25 /* Thread ID, User R/W */
48#define c14_CNTKCTL 26 /* Timer Control Register (PL1) */ 48#define c13_TID_URO 26 /* Thread ID, User R/O */
49#define NR_CP15_REGS 27 /* Number of regs (incl. invalid) */ 49#define c13_TID_PRIV 27 /* Thread ID, Privileged */
50#define c14_CNTKCTL 28 /* Timer Control Register (PL1) */
51#define NR_CP15_REGS 29 /* Number of regs (incl. invalid) */
50 52
51#define ARM_EXCEPTION_RESET 0 53#define ARM_EXCEPTION_RESET 0
52#define ARM_EXCEPTION_UNDEFINED 1 54#define ARM_EXCEPTION_UNDEFINED 1
@@ -72,8 +74,6 @@ extern char __kvm_hyp_vector[];
72extern char __kvm_hyp_code_start[]; 74extern char __kvm_hyp_code_start[];
73extern char __kvm_hyp_code_end[]; 75extern char __kvm_hyp_code_end[];
74 76
75extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
76
77extern void __kvm_flush_vm_context(void); 77extern void __kvm_flush_vm_context(void);
78extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa); 78extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
79 79
diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
index 82b4babead2c..a464e8d7b6c5 100644
--- a/arch/arm/include/asm/kvm_emulate.h
+++ b/arch/arm/include/asm/kvm_emulate.h
@@ -65,11 +65,6 @@ static inline bool vcpu_mode_priv(struct kvm_vcpu *vcpu)
65 return cpsr_mode > USR_MODE;; 65 return cpsr_mode > USR_MODE;;
66} 66}
67 67
68static inline bool kvm_vcpu_reg_is_pc(struct kvm_vcpu *vcpu, int reg)
69{
70 return reg == 15;
71}
72
73static inline u32 kvm_vcpu_get_hsr(struct kvm_vcpu *vcpu) 68static inline u32 kvm_vcpu_get_hsr(struct kvm_vcpu *vcpu)
74{ 69{
75 return vcpu->arch.fault.hsr; 70 return vcpu->arch.fault.hsr;
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 57cb786a6203..7d22517d8071 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -23,9 +23,14 @@
23#include <asm/kvm_asm.h> 23#include <asm/kvm_asm.h>
24#include <asm/kvm_mmio.h> 24#include <asm/kvm_mmio.h>
25#include <asm/fpstate.h> 25#include <asm/fpstate.h>
26#include <asm/kvm_arch_timer.h> 26#include <kvm/arm_arch_timer.h>
27 27
28#if defined(CONFIG_KVM_ARM_MAX_VCPUS)
28#define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS 29#define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
30#else
31#define KVM_MAX_VCPUS 0
32#endif
33
29#define KVM_USER_MEM_SLOTS 32 34#define KVM_USER_MEM_SLOTS 32
30#define KVM_PRIVATE_MEM_SLOTS 4 35#define KVM_PRIVATE_MEM_SLOTS 4
31#define KVM_COALESCED_MMIO_PAGE_OFFSET 1 36#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
@@ -38,7 +43,7 @@
38#define KVM_NR_PAGE_SIZES 1 43#define KVM_NR_PAGE_SIZES 1
39#define KVM_PAGES_PER_HPAGE(x) (1UL<<31) 44#define KVM_PAGES_PER_HPAGE(x) (1UL<<31)
40 45
41#include <asm/kvm_vgic.h> 46#include <kvm/arm_vgic.h>
42 47
43struct kvm_vcpu; 48struct kvm_vcpu;
44u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode); 49u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
@@ -190,8 +195,8 @@ int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
190int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, 195int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
191 int exception_index); 196 int exception_index);
192 197
193static inline void __cpu_init_hyp_mode(unsigned long long boot_pgd_ptr, 198static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr,
194 unsigned long long pgd_ptr, 199 phys_addr_t pgd_ptr,
195 unsigned long hyp_stack_ptr, 200 unsigned long hyp_stack_ptr,
196 unsigned long vector_ptr) 201 unsigned long vector_ptr)
197{ 202{
diff --git a/arch/arm/include/asm/kvm_vgic.h b/arch/arm/include/asm/kvm_vgic.h
deleted file mode 100644
index 343744e4809c..000000000000
--- a/arch/arm/include/asm/kvm_vgic.h
+++ /dev/null
@@ -1,220 +0,0 @@
1/*
2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __ASM_ARM_KVM_VGIC_H
20#define __ASM_ARM_KVM_VGIC_H
21
22#include <linux/kernel.h>
23#include <linux/kvm.h>
24#include <linux/irqreturn.h>
25#include <linux/spinlock.h>
26#include <linux/types.h>
27#include <linux/irqchip/arm-gic.h>
28
29#define VGIC_NR_IRQS 128
30#define VGIC_NR_SGIS 16
31#define VGIC_NR_PPIS 16
32#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
33#define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
34#define VGIC_MAX_CPUS KVM_MAX_VCPUS
35#define VGIC_MAX_LRS (1 << 6)
36
37/* Sanity checks... */
38#if (VGIC_MAX_CPUS > 8)
39#error Invalid number of CPU interfaces
40#endif
41
42#if (VGIC_NR_IRQS & 31)
43#error "VGIC_NR_IRQS must be a multiple of 32"
44#endif
45
46#if (VGIC_NR_IRQS > 1024)
47#error "VGIC_NR_IRQS must be <= 1024"
48#endif
49
50/*
51 * The GIC distributor registers describing interrupts have two parts:
52 * - 32 per-CPU interrupts (SGI + PPI)
53 * - a bunch of shared interrupts (SPI)
54 */
55struct vgic_bitmap {
56 union {
57 u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
58 DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
59 } percpu[VGIC_MAX_CPUS];
60 union {
61 u32 reg[VGIC_NR_SHARED_IRQS / 32];
62 DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
63 } shared;
64};
65
66struct vgic_bytemap {
67 u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
68 u32 shared[VGIC_NR_SHARED_IRQS / 4];
69};
70
71struct vgic_dist {
72#ifdef CONFIG_KVM_ARM_VGIC
73 spinlock_t lock;
74 bool ready;
75
76 /* Virtual control interface mapping */
77 void __iomem *vctrl_base;
78
79 /* Distributor and vcpu interface mapping in the guest */
80 phys_addr_t vgic_dist_base;
81 phys_addr_t vgic_cpu_base;
82
83 /* Distributor enabled */
84 u32 enabled;
85
86 /* Interrupt enabled (one bit per IRQ) */
87 struct vgic_bitmap irq_enabled;
88
89 /* Interrupt 'pin' level */
90 struct vgic_bitmap irq_state;
91
92 /* Level-triggered interrupt in progress */
93 struct vgic_bitmap irq_active;
94
95 /* Interrupt priority. Not used yet. */
96 struct vgic_bytemap irq_priority;
97
98 /* Level/edge triggered */
99 struct vgic_bitmap irq_cfg;
100
101 /* Source CPU per SGI and target CPU */
102 u8 irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
103
104 /* Target CPU for each IRQ */
105 u8 irq_spi_cpu[VGIC_NR_SHARED_IRQS];
106 struct vgic_bitmap irq_spi_target[VGIC_MAX_CPUS];
107
108 /* Bitmap indicating which CPU has something pending */
109 unsigned long irq_pending_on_cpu;
110#endif
111};
112
113struct vgic_cpu {
114#ifdef CONFIG_KVM_ARM_VGIC
115 /* per IRQ to LR mapping */
116 u8 vgic_irq_lr_map[VGIC_NR_IRQS];
117
118 /* Pending interrupts on this VCPU */
119 DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
120 DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
121
122 /* Bitmap of used/free list registers */
123 DECLARE_BITMAP( lr_used, VGIC_MAX_LRS);
124
125 /* Number of list registers on this CPU */
126 int nr_lr;
127
128 /* CPU vif control registers for world switch */
129 u32 vgic_hcr;
130 u32 vgic_vmcr;
131 u32 vgic_misr; /* Saved only */
132 u32 vgic_eisr[2]; /* Saved only */
133 u32 vgic_elrsr[2]; /* Saved only */
134 u32 vgic_apr;
135 u32 vgic_lr[VGIC_MAX_LRS];
136#endif
137};
138
139#define LR_EMPTY 0xff
140
141struct kvm;
142struct kvm_vcpu;
143struct kvm_run;
144struct kvm_exit_mmio;
145
146#ifdef CONFIG_KVM_ARM_VGIC
147int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr);
148int kvm_vgic_hyp_init(void);
149int kvm_vgic_init(struct kvm *kvm);
150int kvm_vgic_create(struct kvm *kvm);
151int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
152void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
153void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
154int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
155 bool level);
156int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
157bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
158 struct kvm_exit_mmio *mmio);
159
160#define irqchip_in_kernel(k) (!!((k)->arch.vgic.vctrl_base))
161#define vgic_initialized(k) ((k)->arch.vgic.ready)
162
163#else
164static inline int kvm_vgic_hyp_init(void)
165{
166 return 0;
167}
168
169static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
170{
171 return 0;
172}
173
174static inline int kvm_vgic_init(struct kvm *kvm)
175{
176 return 0;
177}
178
179static inline int kvm_vgic_create(struct kvm *kvm)
180{
181 return 0;
182}
183
184static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
185{
186 return 0;
187}
188
189static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
190static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
191
192static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
193 unsigned int irq_num, bool level)
194{
195 return 0;
196}
197
198static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
199{
200 return 0;
201}
202
203static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
204 struct kvm_exit_mmio *mmio)
205{
206 return false;
207}
208
209static inline int irqchip_in_kernel(struct kvm *kvm)
210{
211 return 0;
212}
213
214static inline bool vgic_initialized(struct kvm *kvm)
215{
216 return true;
217}
218#endif
219
220#endif
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 308ad7d6f98b..441efc491b50 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -8,7 +8,10 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#include <linux/types.h>
12
11#ifndef __ASSEMBLY__ 13#ifndef __ASSEMBLY__
14#include <linux/reboot.h>
12 15
13struct tag; 16struct tag;
14struct meminfo; 17struct meminfo;
@@ -16,8 +19,10 @@ struct pt_regs;
16struct smp_operations; 19struct smp_operations;
17#ifdef CONFIG_SMP 20#ifdef CONFIG_SMP
18#define smp_ops(ops) (&(ops)) 21#define smp_ops(ops) (&(ops))
22#define smp_init_ops(ops) (&(ops))
19#else 23#else
20#define smp_ops(ops) (struct smp_operations *)NULL 24#define smp_ops(ops) (struct smp_operations *)NULL
25#define smp_init_ops(ops) (bool (*)(void))NULL
21#endif 26#endif
22 27
23struct machine_desc { 28struct machine_desc {
@@ -39,8 +44,9 @@ struct machine_desc {
39 unsigned char reserve_lp0 :1; /* never has lp0 */ 44 unsigned char reserve_lp0 :1; /* never has lp0 */
40 unsigned char reserve_lp1 :1; /* never has lp1 */ 45 unsigned char reserve_lp1 :1; /* never has lp1 */
41 unsigned char reserve_lp2 :1; /* never has lp2 */ 46 unsigned char reserve_lp2 :1; /* never has lp2 */
42 char restart_mode; /* default restart mode */ 47 enum reboot_mode reboot_mode; /* default restart mode */
43 struct smp_operations *smp; /* SMP operations */ 48 struct smp_operations *smp; /* SMP operations */
49 bool (*smp_init)(void);
44 void (*fixup)(struct tag *, char **, 50 void (*fixup)(struct tag *, char **,
45 struct meminfo *); 51 struct meminfo *);
46 void (*reserve)(void);/* reserve mem blocks */ 52 void (*reserve)(void);/* reserve mem blocks */
@@ -53,7 +59,7 @@ struct machine_desc {
53#ifdef CONFIG_MULTI_IRQ_HANDLER 59#ifdef CONFIG_MULTI_IRQ_HANDLER
54 void (*handle_irq)(struct pt_regs *); 60 void (*handle_irq)(struct pt_regs *);
55#endif 61#endif
56 void (*restart)(char, const char *); 62 void (*restart)(enum reboot_mode, const char *);
57}; 63};
58 64
59/* 65/*
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 7d2c3c843801..a1c90d7feb0e 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -16,6 +16,7 @@
16struct pci_sys_data; 16struct pci_sys_data;
17struct pci_ops; 17struct pci_ops;
18struct pci_bus; 18struct pci_bus;
19struct device;
19 20
20struct hw_pci { 21struct hw_pci {
21#ifdef CONFIG_PCI_DOMAINS 22#ifdef CONFIG_PCI_DOMAINS
@@ -68,7 +69,16 @@ struct pci_sys_data {
68/* 69/*
69 * Call this with your hw_pci struct to initialise the PCI system. 70 * Call this with your hw_pci struct to initialise the PCI system.
70 */ 71 */
71void pci_common_init(struct hw_pci *); 72void pci_common_init_dev(struct device *, struct hw_pci *);
73
74/*
75 * Compatibility wrapper for older platforms that do not care about
76 * passing the parent device.
77 */
78static inline void pci_common_init(struct hw_pci *hw)
79{
80 pci_common_init_dev(NULL, hw);
81}
72 82
73/* 83/*
74 * Setup early fixed I/O mapping. 84 * Setup early fixed I/O mapping.
@@ -96,9 +106,4 @@ extern struct pci_ops via82c505_ops;
96extern int via82c505_setup(int nr, struct pci_sys_data *); 106extern int via82c505_setup(int nr, struct pci_sys_data *);
97extern void via82c505_init(void *sysdata); 107extern void via82c505_init(void *sysdata);
98 108
99extern struct pci_ops pci_v3_ops;
100extern int pci_v3_setup(int nr, struct pci_sys_data *);
101extern void pci_v3_preinit(void);
102extern void pci_v3_postinit(void);
103
104#endif /* __ASM_MACH_PCI_H */ 109#endif /* __ASM_MACH_PCI_H */
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 57870ab313c5..e750a938fd3c 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -18,6 +18,8 @@
18#include <linux/types.h> 18#include <linux/types.h>
19#include <linux/sizes.h> 19#include <linux/sizes.h>
20 20
21#include <asm/cache.h>
22
21#ifdef CONFIG_NEED_MACH_MEMORY_H 23#ifdef CONFIG_NEED_MACH_MEMORY_H
22#include <mach/memory.h> 24#include <mach/memory.h>
23#endif 25#endif
@@ -141,6 +143,20 @@
141#define page_to_phys(page) (__pfn_to_phys(page_to_pfn(page))) 143#define page_to_phys(page) (__pfn_to_phys(page_to_pfn(page)))
142#define phys_to_page(phys) (pfn_to_page(__phys_to_pfn(phys))) 144#define phys_to_page(phys) (pfn_to_page(__phys_to_pfn(phys)))
143 145
146/*
147 * Minimum guaranted alignment in pgd_alloc(). The page table pointers passed
148 * around in head.S and proc-*.S are shifted by this amount, in order to
149 * leave spare high bits for systems with physical address extension. This
150 * does not fully accomodate the 40-bit addressing capability of ARM LPAE, but
151 * gives us about 38-bits or so.
152 */
153#ifdef CONFIG_ARM_LPAE
154#define ARCH_PGD_SHIFT L1_CACHE_SHIFT
155#else
156#define ARCH_PGD_SHIFT 0
157#endif
158#define ARCH_PGD_MASK ((1 << ARCH_PGD_SHIFT) - 1)
159
144#ifndef __ASSEMBLY__ 160#ifndef __ASSEMBLY__
145 161
146/* 162/*
@@ -207,7 +223,7 @@ static inline unsigned long __phys_to_virt(unsigned long x)
207 * direct-mapped view. We assume this is the first page 223 * direct-mapped view. We assume this is the first page
208 * of RAM in the mem_map as well. 224 * of RAM in the mem_map as well.
209 */ 225 */
210#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT) 226#define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
211 227
212/* 228/*
213 * These are *only* valid on the kernel direct mapped RAM memory. 229 * These are *only* valid on the kernel direct mapped RAM memory.
@@ -260,12 +276,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
260/* 276/*
261 * Conversion between a struct page and a physical address. 277 * Conversion between a struct page and a physical address.
262 * 278 *
263 * Note: when converting an unknown physical address to a
264 * struct page, the resulting pointer must be validated
265 * using VALID_PAGE(). It must return an invalid struct page
266 * for any physical address not corresponding to a system
267 * RAM address.
268 *
269 * page_to_pfn(page) convert a struct page * to a PFN number 279 * page_to_pfn(page) convert a struct page * to a PFN number
270 * pfn_to_page(pfn) convert a _valid_ PFN number to struct page * 280 * pfn_to_page(pfn) convert a _valid_ PFN number to struct page *
271 * 281 *
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index a7b85e0d0cc1..b5792b7fd8d3 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -18,6 +18,7 @@
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/cachetype.h> 19#include <asm/cachetype.h>
20#include <asm/proc-fns.h> 20#include <asm/proc-fns.h>
21#include <asm/smp_plat.h>
21#include <asm-generic/mm_hooks.h> 22#include <asm-generic/mm_hooks.h>
22 23
23void __check_vmalloc_seq(struct mm_struct *mm); 24void __check_vmalloc_seq(struct mm_struct *mm);
@@ -27,7 +28,15 @@ void __check_vmalloc_seq(struct mm_struct *mm);
27void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk); 28void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
28#define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; }) 29#define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; })
29 30
30DECLARE_PER_CPU(atomic64_t, active_asids); 31#ifdef CONFIG_ARM_ERRATA_798181
32void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
33 cpumask_t *mask);
34#else /* !CONFIG_ARM_ERRATA_798181 */
35static inline void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
36 cpumask_t *mask)
37{
38}
39#endif /* CONFIG_ARM_ERRATA_798181 */
31 40
32#else /* !CONFIG_CPU_HAS_ASID */ 41#else /* !CONFIG_CPU_HAS_ASID */
33 42
@@ -98,12 +107,16 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
98#ifdef CONFIG_MMU 107#ifdef CONFIG_MMU
99 unsigned int cpu = smp_processor_id(); 108 unsigned int cpu = smp_processor_id();
100 109
101#ifdef CONFIG_SMP 110 /*
102 /* check for possible thread migration */ 111 * __sync_icache_dcache doesn't broadcast the I-cache invalidation,
103 if (!cpumask_empty(mm_cpumask(next)) && 112 * so check for possible thread migration and invalidate the I-cache
113 * if we're new to this CPU.
114 */
115 if (cache_ops_need_broadcast() &&
116 !cpumask_empty(mm_cpumask(next)) &&
104 !cpumask_test_cpu(cpu, mm_cpumask(next))) 117 !cpumask_test_cpu(cpu, mm_cpumask(next)))
105 __flush_icache_all(); 118 __flush_icache_all();
106#endif 119
107 if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) { 120 if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
108 check_and_switch_context(next, tsk); 121 check_and_switch_context(next, tsk);
109 if (cache_is_vivt()) 122 if (cache_is_vivt())
diff --git a/arch/arm/include/asm/mpu.h b/arch/arm/include/asm/mpu.h
new file mode 100644
index 000000000000..c3247cc2fe08
--- /dev/null
+++ b/arch/arm/include/asm/mpu.h
@@ -0,0 +1,76 @@
1#ifndef __ARM_MPU_H
2#define __ARM_MPU_H
3
4#ifdef CONFIG_ARM_MPU
5
6/* MPUIR layout */
7#define MPUIR_nU 1
8#define MPUIR_DREGION 8
9#define MPUIR_IREGION 16
10#define MPUIR_DREGION_SZMASK (0xFF << MPUIR_DREGION)
11#define MPUIR_IREGION_SZMASK (0xFF << MPUIR_IREGION)
12
13/* ID_MMFR0 data relevant to MPU */
14#define MMFR0_PMSA (0xF << 4)
15#define MMFR0_PMSAv7 (3 << 4)
16
17/* MPU D/I Size Register fields */
18#define MPU_RSR_SZ 1
19#define MPU_RSR_EN 0
20
21/* The D/I RSR value for an enabled region spanning the whole of memory */
22#define MPU_RSR_ALL_MEM 63
23
24/* Individual bits in the DR/IR ACR */
25#define MPU_ACR_XN (1 << 12)
26#define MPU_ACR_SHARED (1 << 2)
27
28/* C, B and TEX[2:0] bits only have semantic meanings when grouped */
29#define MPU_RGN_CACHEABLE 0xB
30#define MPU_RGN_SHARED_CACHEABLE (MPU_RGN_CACHEABLE | MPU_ACR_SHARED)
31#define MPU_RGN_STRONGLY_ORDERED 0
32
33/* Main region should only be shared for SMP */
34#ifdef CONFIG_SMP
35#define MPU_RGN_NORMAL (MPU_RGN_CACHEABLE | MPU_ACR_SHARED)
36#else
37#define MPU_RGN_NORMAL MPU_RGN_CACHEABLE
38#endif
39
40/* Access permission bits of ACR (only define those that we use)*/
41#define MPU_AP_PL1RW_PL0RW (0x3 << 8)
42#define MPU_AP_PL1RW_PL0R0 (0x2 << 8)
43#define MPU_AP_PL1RW_PL0NA (0x1 << 8)
44
45/* For minimal static MPU region configurations */
46#define MPU_PROBE_REGION 0
47#define MPU_BG_REGION 1
48#define MPU_RAM_REGION 2
49#define MPU_VECTORS_REGION 3
50
51/* Maximum number of regions Linux is interested in */
52#define MPU_MAX_REGIONS 16
53
54#define MPU_DATA_SIDE 0
55#define MPU_INSTR_SIDE 1
56
57#ifndef __ASSEMBLY__
58
59struct mpu_rgn {
60 /* Assume same attributes for d/i-side */
61 u32 drbar;
62 u32 drsr;
63 u32 dracr;
64};
65
66struct mpu_rgn_info {
67 u32 mpuir;
68 struct mpu_rgn rgns[MPU_MAX_REGIONS];
69};
70extern struct mpu_rgn_info mpu_rgn_info;
71
72#endif /* __ASSEMBLY__ */
73
74#endif /* CONFIG_ARM_MPU */
75
76#endif
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index 812a4944e783..6363f3d1d505 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -13,7 +13,7 @@
13/* PAGE_SHIFT determines the page size */ 13/* PAGE_SHIFT determines the page size */
14#define PAGE_SHIFT 12 14#define PAGE_SHIFT 12
15#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) 15#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
16#define PAGE_MASK (~(PAGE_SIZE-1)) 16#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
17 17
18#ifndef __ASSEMBLY__ 18#ifndef __ASSEMBLY__
19 19
diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
index 18f5cef82ad5..626989fec4d3 100644
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -30,6 +30,7 @@
30#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 30#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0)
31#define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 31#define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0)
32#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 32#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
33#define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1)
33#define PMD_BIT4 (_AT(pmdval_t, 0)) 34#define PMD_BIT4 (_AT(pmdval_t, 0))
34#define PMD_DOMAIN(x) (_AT(pmdval_t, 0)) 35#define PMD_DOMAIN(x) (_AT(pmdval_t, 0))
35#define PMD_APTABLE_SHIFT (61) 36#define PMD_APTABLE_SHIFT (61)
@@ -41,6 +42,8 @@
41 */ 42 */
42#define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2) 43#define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2)
43#define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3) 44#define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3)
45#define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */
46#define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */
44#define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 47#define PMD_SECT_S (_AT(pmdval_t, 3) << 8)
45#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 48#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10)
46#define PMD_SECT_nG (_AT(pmdval_t, 1) << 11) 49#define PMD_SECT_nG (_AT(pmdval_t, 1) << 11)
@@ -66,6 +69,7 @@
66#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 69#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0)
67#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 70#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0)
68#define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 71#define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0)
72#define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1)
69#define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */ 73#define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */
70#define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */ 74#define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */
71#define PTE_EXT_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 75#define PTE_EXT_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
@@ -79,4 +83,24 @@
79#define PHYS_MASK_SHIFT (40) 83#define PHYS_MASK_SHIFT (40)
80#define PHYS_MASK ((1ULL << PHYS_MASK_SHIFT) - 1) 84#define PHYS_MASK ((1ULL << PHYS_MASK_SHIFT) - 1)
81 85
86/*
87 * TTBR0/TTBR1 split (PAGE_OFFSET):
88 * 0x40000000: T0SZ = 2, T1SZ = 0 (not used)
89 * 0x80000000: T0SZ = 0, T1SZ = 1
90 * 0xc0000000: T0SZ = 0, T1SZ = 2
91 *
92 * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
93 * booting secondary CPUs would end up using TTBR1 for the identity
94 * mapping set up in TTBR0.
95 */
96#if defined CONFIG_VMSPLIT_2G
97#define TTBR1_OFFSET 16 /* skip two L1 entries */
98#elif defined CONFIG_VMSPLIT_3G
99#define TTBR1_OFFSET (4096 * (1 + 3)) /* only L2, skip pgd + 3*pmd */
100#else
101#define TTBR1_OFFSET 0
102#endif
103
104#define TTBR1_SIZE (((PAGE_OFFSET >> 30) - 1) << 16)
105
82#endif 106#endif
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 86b8fe398b95..5689c18c85f5 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -33,7 +33,7 @@
33#define PTRS_PER_PMD 512 33#define PTRS_PER_PMD 512
34#define PTRS_PER_PGD 4 34#define PTRS_PER_PGD 4
35 35
36#define PTE_HWTABLE_PTRS (PTRS_PER_PTE) 36#define PTE_HWTABLE_PTRS (0)
37#define PTE_HWTABLE_OFF (0) 37#define PTE_HWTABLE_OFF (0)
38#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64)) 38#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64))
39 39
@@ -48,20 +48,28 @@
48#define PMD_SHIFT 21 48#define PMD_SHIFT 21
49 49
50#define PMD_SIZE (1UL << PMD_SHIFT) 50#define PMD_SIZE (1UL << PMD_SHIFT)
51#define PMD_MASK (~(PMD_SIZE-1)) 51#define PMD_MASK (~((1 << PMD_SHIFT) - 1))
52#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 52#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
53#define PGDIR_MASK (~(PGDIR_SIZE-1)) 53#define PGDIR_MASK (~((1 << PGDIR_SHIFT) - 1))
54 54
55/* 55/*
56 * section address mask and size definitions. 56 * section address mask and size definitions.
57 */ 57 */
58#define SECTION_SHIFT 21 58#define SECTION_SHIFT 21
59#define SECTION_SIZE (1UL << SECTION_SHIFT) 59#define SECTION_SIZE (1UL << SECTION_SHIFT)
60#define SECTION_MASK (~(SECTION_SIZE-1)) 60#define SECTION_MASK (~((1 << SECTION_SHIFT) - 1))
61 61
62#define USER_PTRS_PER_PGD (PAGE_OFFSET / PGDIR_SIZE) 62#define USER_PTRS_PER_PGD (PAGE_OFFSET / PGDIR_SIZE)
63 63
64/* 64/*
65 * Hugetlb definitions.
66 */
67#define HPAGE_SHIFT PMD_SHIFT
68#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
69#define HPAGE_MASK (~(HPAGE_SIZE - 1))
70#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
71
72/*
65 * "Linux" PTE definitions for LPAE. 73 * "Linux" PTE definitions for LPAE.
66 * 74 *
67 * These bits overlap with the hardware bits but the naming is preserved for 75 * These bits overlap with the hardware bits but the naming is preserved for
@@ -79,6 +87,11 @@
79#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 56) /* unused */ 87#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 56) /* unused */
80#define L_PTE_NONE (_AT(pteval_t, 1) << 57) /* PROT_NONE */ 88#define L_PTE_NONE (_AT(pteval_t, 1) << 57) /* PROT_NONE */
81 89
90#define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0)
91#define PMD_SECT_DIRTY (_AT(pmdval_t, 1) << 55)
92#define PMD_SECT_SPLITTING (_AT(pmdval_t, 1) << 56)
93#define PMD_SECT_NONE (_AT(pmdval_t, 1) << 57)
94
82/* 95/*
83 * To be used in assembly code with the upper page attributes. 96 * To be used in assembly code with the upper page attributes.
84 */ 97 */
@@ -166,8 +179,83 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
166 clean_pmd_entry(pmdp); \ 179 clean_pmd_entry(pmdp); \
167 } while (0) 180 } while (0)
168 181
182/*
183 * For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes
184 * that are written to a page table but not for ptes created with mk_pte.
185 *
186 * In hugetlb_no_page, a new huge pte (new_pte) is generated and passed to
187 * hugetlb_cow, where it is compared with an entry in a page table.
188 * This comparison test fails erroneously leading ultimately to a memory leak.
189 *
190 * To correct this behaviour, we mask off PTE_EXT_NG for any pte that is
191 * present before running the comparison.
192 */
193#define __HAVE_ARCH_PTE_SAME
194#define pte_same(pte_a,pte_b) ((pte_present(pte_a) ? pte_val(pte_a) & ~PTE_EXT_NG \
195 : pte_val(pte_a)) \
196 == (pte_present(pte_b) ? pte_val(pte_b) & ~PTE_EXT_NG \
197 : pte_val(pte_b)))
198
169#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext))) 199#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
170 200
201#define pte_huge(pte) (pte_val(pte) && !(pte_val(pte) & PTE_TABLE_BIT))
202#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
203
204#define pmd_young(pmd) (pmd_val(pmd) & PMD_SECT_AF)
205
206#define __HAVE_ARCH_PMD_WRITE
207#define pmd_write(pmd) (!(pmd_val(pmd) & PMD_SECT_RDONLY))
208
209#ifdef CONFIG_TRANSPARENT_HUGEPAGE
210#define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
211#define pmd_trans_splitting(pmd) (pmd_val(pmd) & PMD_SECT_SPLITTING)
212#endif
213
214#define PMD_BIT_FUNC(fn,op) \
215static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
216
217PMD_BIT_FUNC(wrprotect, |= PMD_SECT_RDONLY);
218PMD_BIT_FUNC(mkold, &= ~PMD_SECT_AF);
219PMD_BIT_FUNC(mksplitting, |= PMD_SECT_SPLITTING);
220PMD_BIT_FUNC(mkwrite, &= ~PMD_SECT_RDONLY);
221PMD_BIT_FUNC(mkdirty, |= PMD_SECT_DIRTY);
222PMD_BIT_FUNC(mkyoung, |= PMD_SECT_AF);
223
224#define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
225
226#define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
227#define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
228#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
229
230/* represent a notpresent pmd by zero, this is used by pmdp_invalidate */
231#define pmd_mknotpresent(pmd) (__pmd(0))
232
233static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
234{
235 const pmdval_t mask = PMD_SECT_USER | PMD_SECT_XN | PMD_SECT_RDONLY |
236 PMD_SECT_VALID | PMD_SECT_NONE;
237 pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
238 return pmd;
239}
240
241static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
242 pmd_t *pmdp, pmd_t pmd)
243{
244 BUG_ON(addr >= TASK_SIZE);
245
246 /* create a faulting entry if PROT_NONE protected */
247 if (pmd_val(pmd) & PMD_SECT_NONE)
248 pmd_val(pmd) &= ~PMD_SECT_VALID;
249
250 *pmdp = __pmd(pmd_val(pmd) | PMD_SECT_nG);
251 flush_pmd_entry(pmdp);
252}
253
254static inline int has_transparent_hugepage(void)
255{
256 return 1;
257}
258
171#endif /* __ASSEMBLY__ */ 259#endif /* __ASSEMBLY__ */
172 260
173#endif /* _ASM_PGTABLE_3LEVEL_H */ 261#endif /* _ASM_PGTABLE_3LEVEL_H */
diff --git a/arch/arm/include/asm/pgtable-nommu.h b/arch/arm/include/asm/pgtable-nommu.h
index 7ec60d6075bf..0642228ff785 100644
--- a/arch/arm/include/asm/pgtable-nommu.h
+++ b/arch/arm/include/asm/pgtable-nommu.h
@@ -79,8 +79,6 @@ extern unsigned int kobjsize(const void *objp);
79 * No page table caches to initialise. 79 * No page table caches to initialise.
80 */ 80 */
81#define pgtable_cache_init() do { } while (0) 81#define pgtable_cache_init() do { } while (0)
82#define io_remap_pfn_range remap_pfn_range
83
84 82
85/* 83/*
86 * All 32bit addresses are effectively valid for vmalloc... 84 * All 32bit addresses are effectively valid for vmalloc...
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 9bcd262a9008..04aeb02d2e11 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -24,6 +24,9 @@
24#include <asm/memory.h> 24#include <asm/memory.h>
25#include <asm/pgtable-hwdef.h> 25#include <asm/pgtable-hwdef.h>
26 26
27
28#include <asm/tlbflush.h>
29
27#ifdef CONFIG_ARM_LPAE 30#ifdef CONFIG_ARM_LPAE
28#include <asm/pgtable-3level.h> 31#include <asm/pgtable-3level.h>
29#else 32#else
@@ -318,13 +321,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
318#define HAVE_ARCH_UNMAPPED_AREA 321#define HAVE_ARCH_UNMAPPED_AREA
319#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 322#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
320 323
321/*
322 * remap a physical page `pfn' of size `size' with page protection `prot'
323 * into virtual address `from'
324 */
325#define io_remap_pfn_range(vma,from,pfn,size,prot) \
326 remap_pfn_range(vma, from, pfn, size, prot)
327
328#define pgtable_cache_init() do { } while (0) 324#define pgtable_cache_init() do { } while (0)
329 325
330#endif /* !__ASSEMBLY__ */ 326#endif /* !__ASSEMBLY__ */
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index f3628fb3d2b3..5324c1112f3a 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -60,7 +60,7 @@ extern struct processor {
60 /* 60 /*
61 * Set the page table 61 * Set the page table
62 */ 62 */
63 void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm); 63 void (*switch_mm)(phys_addr_t pgd_phys, struct mm_struct *mm);
64 /* 64 /*
65 * Set a possibly extended PTE. Non-extended PTEs should 65 * Set a possibly extended PTE. Non-extended PTEs should
66 * ignore 'ext'. 66 * ignore 'ext'.
@@ -82,7 +82,7 @@ extern void cpu_proc_init(void);
82extern void cpu_proc_fin(void); 82extern void cpu_proc_fin(void);
83extern int cpu_do_idle(void); 83extern int cpu_do_idle(void);
84extern void cpu_dcache_clean_area(void *, int); 84extern void cpu_dcache_clean_area(void *, int);
85extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm); 85extern void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
86#ifdef CONFIG_ARM_LPAE 86#ifdef CONFIG_ARM_LPAE
87extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte); 87extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte);
88#else 88#else
@@ -116,13 +116,25 @@ extern void cpu_resume(void);
116#define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm) 116#define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
117 117
118#ifdef CONFIG_ARM_LPAE 118#ifdef CONFIG_ARM_LPAE
119
120#define cpu_get_ttbr(nr) \
121 ({ \
122 u64 ttbr; \
123 __asm__("mrrc p15, " #nr ", %Q0, %R0, c2" \
124 : "=r" (ttbr)); \
125 ttbr; \
126 })
127
128#define cpu_set_ttbr(nr, val) \
129 do { \
130 u64 ttbr = val; \
131 __asm__("mcrr p15, " #nr ", %Q0, %R0, c2" \
132 : : "r" (ttbr)); \
133 } while (0)
134
119#define cpu_get_pgd() \ 135#define cpu_get_pgd() \
120 ({ \ 136 ({ \
121 unsigned long pg, pg2; \ 137 u64 pg = cpu_get_ttbr(0); \
122 __asm__("mrrc p15, 0, %0, %1, c2" \
123 : "=r" (pg), "=r" (pg2) \
124 : \
125 : "cc"); \
126 pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1); \ 138 pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1); \
127 (pgd_t *)phys_to_virt(pg); \ 139 (pgd_t *)phys_to_virt(pg); \
128 }) 140 })
@@ -137,6 +149,10 @@ extern void cpu_resume(void);
137 }) 149 })
138#endif 150#endif
139 151
152#else /*!CONFIG_MMU */
153
154#define cpu_switch_mm(pgd,mm) { }
155
140#endif 156#endif
141 157
142#endif /* __ASSEMBLY__ */ 158#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index ce0dbe7c1625..c4ae171850f8 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -32,5 +32,14 @@ struct psci_operations {
32}; 32};
33 33
34extern struct psci_operations psci_ops; 34extern struct psci_operations psci_ops;
35extern struct smp_operations psci_smp_ops;
36
37#ifdef CONFIG_ARM_PSCI
38void psci_init(void);
39bool psci_smp_available(void);
40#else
41static inline void psci_init(void) { }
42static inline bool psci_smp_available(void) { return false; }
43#endif
35 44
36#endif /* __ASM_ARM_PSCI_H */ 45#endif /* __ASM_ARM_PSCI_H */
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 3d52ee1bfb31..04c99f36ff7f 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -45,6 +45,7 @@ struct pt_regs {
45 */ 45 */
46static inline int valid_user_regs(struct pt_regs *regs) 46static inline int valid_user_regs(struct pt_regs *regs)
47{ 47{
48#ifndef CONFIG_CPU_V7M
48 unsigned long mode = regs->ARM_cpsr & MODE_MASK; 49 unsigned long mode = regs->ARM_cpsr & MODE_MASK;
49 50
50 /* 51 /*
@@ -67,6 +68,9 @@ static inline int valid_user_regs(struct pt_regs *regs)
67 regs->ARM_cpsr |= USR_MODE; 68 regs->ARM_cpsr |= USR_MODE;
68 69
69 return 0; 70 return 0;
71#else /* ifndef CONFIG_CPU_V7M */
72 return 1;
73#endif
70} 74}
71 75
72static inline long regs_return_value(struct pt_regs *regs) 76static inline long regs_return_value(struct pt_regs *regs)
diff --git a/arch/arm/include/asm/sched_clock.h b/arch/arm/include/asm/sched_clock.h
index 3d520ddca61b..2389b71a8e7c 100644
--- a/arch/arm/include/asm/sched_clock.h
+++ b/arch/arm/include/asm/sched_clock.h
@@ -1,16 +1,4 @@
1/* 1/* You shouldn't include this file. Use linux/sched_clock.h instead.
2 * sched_clock.h: support for extending counters to full 64-bit ns counter 2 * Temporary file until all asm/sched_clock.h users are gone
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */ 3 */
8#ifndef ASM_SCHED_CLOCK 4#include <linux/sched_clock.h>
9#define ASM_SCHED_CLOCK
10
11extern void sched_clock_postinit(void);
12extern void setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate);
13
14extern unsigned long long (*sched_clock_func)(void);
15
16#endif
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index d3a22bebe6ce..a8cae71caceb 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -65,7 +65,10 @@ asmlinkage void secondary_start_kernel(void);
65 * Initial data for bringing up a secondary CPU. 65 * Initial data for bringing up a secondary CPU.
66 */ 66 */
67struct secondary_data { 67struct secondary_data {
68 unsigned long pgdir; 68 union {
69 unsigned long mpu_rgn_szr;
70 unsigned long pgdir;
71 };
69 unsigned long swapper_pg_dir; 72 unsigned long swapper_pg_dir;
70 void *stack; 73 void *stack;
71}; 74};
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index e78983202737..6462a721ebd4 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -26,6 +26,9 @@ static inline bool is_smp(void)
26} 26}
27 27
28/* all SMP configurations have the extended CPUID registers */ 28/* all SMP configurations have the extended CPUID registers */
29#ifndef CONFIG_MMU
30#define tlb_ops_need_broadcast() 0
31#else
29static inline int tlb_ops_need_broadcast(void) 32static inline int tlb_ops_need_broadcast(void)
30{ 33{
31 if (!is_smp()) 34 if (!is_smp())
@@ -33,6 +36,7 @@ static inline int tlb_ops_need_broadcast(void)
33 36
34 return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2; 37 return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
35} 38}
39#endif
36 40
37#if !defined(CONFIG_SMP) || __LINUX_ARM_ARCH__ >= 7 41#if !defined(CONFIG_SMP) || __LINUX_ARM_ARCH__ >= 7
38#define cache_ops_need_broadcast() 0 42#define cache_ops_need_broadcast() 0
@@ -66,4 +70,22 @@ static inline int get_logical_index(u32 mpidr)
66 return -EINVAL; 70 return -EINVAL;
67} 71}
68 72
73/*
74 * NOTE ! Assembly code relies on the following
75 * structure memory layout in order to carry out load
76 * multiple from its base address. For more
77 * information check arch/arm/kernel/sleep.S
78 */
79struct mpidr_hash {
80 u32 mask; /* used by sleep.S */
81 u32 shift_aff[3]; /* used by sleep.S */
82 u32 bits;
83};
84
85extern struct mpidr_hash mpidr_hash;
86
87static inline u32 mpidr_hash_size(void)
88{
89 return 1 << mpidr_hash.bits;
90}
69#endif 91#endif
diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index 18d169373612..0393fbab8dd5 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -23,10 +23,21 @@ static inline unsigned long scu_a9_get_base(void)
23 return pa; 23 return pa;
24} 24}
25 25
26#ifdef CONFIG_HAVE_ARM_SCU
26unsigned int scu_get_core_count(void __iomem *); 27unsigned int scu_get_core_count(void __iomem *);
27int scu_power_mode(void __iomem *, unsigned int); 28int scu_power_mode(void __iomem *, unsigned int);
29#else
30static inline unsigned int scu_get_core_count(void __iomem *scu_base)
31{
32 return 0;
33}
34static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode)
35{
36 return -EINVAL;
37}
38#endif
28 39
29#ifdef CONFIG_SMP 40#if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU)
30void scu_enable(void __iomem *scu_base); 41void scu_enable(void __iomem *scu_base);
31#else 42#else
32static inline void scu_enable(void __iomem *scu_base) {} 43static inline void scu_enable(void __iomem *scu_base) {}
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index 6220e9fdf4c7..f8b8965666e9 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -97,19 +97,22 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
97 97
98static inline int arch_spin_trylock(arch_spinlock_t *lock) 98static inline int arch_spin_trylock(arch_spinlock_t *lock)
99{ 99{
100 unsigned long tmp; 100 unsigned long contended, res;
101 u32 slock; 101 u32 slock;
102 102
103 __asm__ __volatile__( 103 do {
104" ldrex %0, [%2]\n" 104 __asm__ __volatile__(
105" subs %1, %0, %0, ror #16\n" 105 " ldrex %0, [%3]\n"
106" addeq %0, %0, %3\n" 106 " mov %2, #0\n"
107" strexeq %1, %0, [%2]" 107 " subs %1, %0, %0, ror #16\n"
108 : "=&r" (slock), "=&r" (tmp) 108 " addeq %0, %0, %4\n"
109 : "r" (&lock->slock), "I" (1 << TICKET_SHIFT) 109 " strexeq %2, %0, [%3]"
110 : "cc"); 110 : "=&r" (slock), "=&r" (contended), "=r" (res)
111 111 : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
112 if (tmp == 0) { 112 : "cc");
113 } while (res);
114
115 if (!contended) {
113 smp_mb(); 116 smp_mb();
114 return 1; 117 return 1;
115 } else { 118 } else {
diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h
index 1c0a551ae375..cd20029bcd94 100644
--- a/arch/arm/include/asm/suspend.h
+++ b/arch/arm/include/asm/suspend.h
@@ -1,6 +1,11 @@
1#ifndef __ASM_ARM_SUSPEND_H 1#ifndef __ASM_ARM_SUSPEND_H
2#define __ASM_ARM_SUSPEND_H 2#define __ASM_ARM_SUSPEND_H
3 3
4struct sleep_save_sp {
5 u32 *save_ptr_stash;
6 u32 save_ptr_stash_phys;
7};
8
4extern void cpu_resume(void); 9extern void cpu_resume(void);
5extern int cpu_suspend(unsigned long, int (*)(unsigned long)); 10extern int cpu_suspend(unsigned long, int (*)(unsigned long));
6 11
diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
index dfd386d0c022..720ea0320a6d 100644
--- a/arch/arm/include/asm/system_info.h
+++ b/arch/arm/include/asm/system_info.h
@@ -11,6 +11,7 @@
11#define CPU_ARCH_ARMv5TEJ 7 11#define CPU_ARCH_ARMv5TEJ 7
12#define CPU_ARCH_ARMv6 8 12#define CPU_ARCH_ARMv6 8
13#define CPU_ARCH_ARMv7 9 13#define CPU_ARCH_ARMv7 9
14#define CPU_ARCH_ARMv7M 10
14 15
15#ifndef __ASSEMBLY__ 16#ifndef __ASSEMBLY__
16 17
diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
index 21a23e378bbe..a3d61ad984af 100644
--- a/arch/arm/include/asm/system_misc.h
+++ b/arch/arm/include/asm/system_misc.h
@@ -6,11 +6,12 @@
6#include <linux/compiler.h> 6#include <linux/compiler.h>
7#include <linux/linkage.h> 7#include <linux/linkage.h>
8#include <linux/irqflags.h> 8#include <linux/irqflags.h>
9#include <linux/reboot.h>
9 10
10extern void cpu_init(void); 11extern void cpu_init(void);
11 12
12void soft_restart(unsigned long); 13void soft_restart(unsigned long);
13extern void (*arm_pm_restart)(char str, const char *cmd); 14extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
14extern void (*arm_pm_idle)(void); 15extern void (*arm_pm_idle)(void);
15 16
16#define UDBG_UNDEFINED (1 << 0) 17#define UDBG_UNDEFINED (1 << 0)
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 1995d1a84060..214d4158089a 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -58,7 +58,7 @@ struct thread_info {
58 struct cpu_context_save cpu_context; /* cpu context */ 58 struct cpu_context_save cpu_context; /* cpu context */
59 __u32 syscall; /* syscall number */ 59 __u32 syscall; /* syscall number */
60 __u8 used_cp[16]; /* thread used copro */ 60 __u8 used_cp[16]; /* thread used copro */
61 unsigned long tp_value; 61 unsigned long tp_value[2]; /* TLS registers */
62#ifdef CONFIG_CRUNCH 62#ifdef CONFIG_CRUNCH
63 struct crunch_state crunchstate; 63 struct crunch_state crunchstate;
64#endif 64#endif
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index bdf2b8458ec1..46e7cfb3e721 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -204,6 +204,12 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
204#endif 204#endif
205} 205}
206 206
207static inline void
208tlb_remove_pmd_tlb_entry(struct mmu_gather *tlb, pmd_t *pmdp, unsigned long addr)
209{
210 tlb_add_flush(tlb, addr);
211}
212
207#define pte_free_tlb(tlb, ptep, addr) __pte_free_tlb(tlb, ptep, addr) 213#define pte_free_tlb(tlb, ptep, addr) __pte_free_tlb(tlb, ptep, addr)
208#define pmd_free_tlb(tlb, pmdp, addr) __pmd_free_tlb(tlb, pmdp, addr) 214#define pmd_free_tlb(tlb, pmdp, addr) __pmd_free_tlb(tlb, pmdp, addr)
209#define pud_free_tlb(tlb, pudp, addr) pud_free((tlb)->mm, pudp) 215#define pud_free_tlb(tlb, pudp, addr) pud_free((tlb)->mm, pudp)
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index a3625d141c1d..fdbb9e369745 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -535,8 +535,33 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
535} 535}
536#endif 536#endif
537 537
538#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
539
538#endif 540#endif
539 541
540#endif /* CONFIG_MMU */ 542#elif defined(CONFIG_SMP) /* !CONFIG_MMU */
543
544#ifndef __ASSEMBLY__
545
546#include <linux/mm_types.h>
547
548static inline void local_flush_tlb_all(void) { }
549static inline void local_flush_tlb_mm(struct mm_struct *mm) { }
550static inline void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) { }
551static inline void local_flush_tlb_kernel_page(unsigned long kaddr) { }
552static inline void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { }
553static inline void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) { }
554static inline void local_flush_bp_all(void) { }
555
556extern void flush_tlb_all(void);
557extern void flush_tlb_mm(struct mm_struct *mm);
558extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
559extern void flush_tlb_kernel_page(unsigned long kaddr);
560extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
561extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
562extern void flush_bp_all(void);
563#endif /* __ASSEMBLY__ */
564
565#endif
541 566
542#endif 567#endif
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 73409e6c0251..83259b873333 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -2,27 +2,30 @@
2#define __ASMARM_TLS_H 2#define __ASMARM_TLS_H
3 3
4#ifdef __ASSEMBLY__ 4#ifdef __ASSEMBLY__
5 .macro set_tls_none, tp, tmp1, tmp2 5#include <asm/asm-offsets.h>
6 .macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
6 .endm 7 .endm
7 8
8 .macro set_tls_v6k, tp, tmp1, tmp2 9 .macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2
10 mrc p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
9 mcr p15, 0, \tp, c13, c0, 3 @ set TLS register 11 mcr p15, 0, \tp, c13, c0, 3 @ set TLS register
10 mov \tmp1, #0 12 mcr p15, 0, \tpuser, c13, c0, 2 @ and the user r/w register
11 mcr p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register 13 str \tmp2, [\base, #TI_TP_VALUE + 4] @ save it
12 .endm 14 .endm
13 15
14 .macro set_tls_v6, tp, tmp1, tmp2 16 .macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2
15 ldr \tmp1, =elf_hwcap 17 ldr \tmp1, =elf_hwcap
16 ldr \tmp1, [\tmp1, #0] 18 ldr \tmp1, [\tmp1, #0]
17 mov \tmp2, #0xffff0fff 19 mov \tmp2, #0xffff0fff
18 tst \tmp1, #HWCAP_TLS @ hardware TLS available? 20 tst \tmp1, #HWCAP_TLS @ hardware TLS available?
19 mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
20 movne \tmp1, #0
21 mcrne p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register
22 streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0 21 streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0
22 mrcne p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
23 mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
24 mcrne p15, 0, \tpuser, c13, c0, 2 @ set user r/w register
25 strne \tmp2, [\base, #TI_TP_VALUE + 4] @ save it
23 .endm 26 .endm
24 27
25 .macro set_tls_software, tp, tmp1, tmp2 28 .macro switch_tls_software, base, tp, tpuser, tmp1, tmp2
26 mov \tmp1, #0xffff0fff 29 mov \tmp1, #0xffff0fff
27 str \tp, [\tmp1, #-15] @ set TLS value at 0xffff0ff0 30 str \tp, [\tmp1, #-15] @ set TLS value at 0xffff0ff0
28 .endm 31 .endm
@@ -31,19 +34,30 @@
31#ifdef CONFIG_TLS_REG_EMUL 34#ifdef CONFIG_TLS_REG_EMUL
32#define tls_emu 1 35#define tls_emu 1
33#define has_tls_reg 1 36#define has_tls_reg 1
34#define set_tls set_tls_none 37#define switch_tls switch_tls_none
35#elif defined(CONFIG_CPU_V6) 38#elif defined(CONFIG_CPU_V6)
36#define tls_emu 0 39#define tls_emu 0
37#define has_tls_reg (elf_hwcap & HWCAP_TLS) 40#define has_tls_reg (elf_hwcap & HWCAP_TLS)
38#define set_tls set_tls_v6 41#define switch_tls switch_tls_v6
39#elif defined(CONFIG_CPU_32v6K) 42#elif defined(CONFIG_CPU_32v6K)
40#define tls_emu 0 43#define tls_emu 0
41#define has_tls_reg 1 44#define has_tls_reg 1
42#define set_tls set_tls_v6k 45#define switch_tls switch_tls_v6k
43#else 46#else
44#define tls_emu 0 47#define tls_emu 0
45#define has_tls_reg 0 48#define has_tls_reg 0
46#define set_tls set_tls_software 49#define switch_tls switch_tls_software
47#endif 50#endif
48 51
52#ifndef __ASSEMBLY__
53static inline unsigned long get_tpuser(void)
54{
55 unsigned long reg = 0;
56
57 if (has_tls_reg && !tls_emu)
58 __asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (reg));
59
60 return reg;
61}
62#endif
49#endif /* __ASMARM_TLS_H */ 63#endif /* __ASMARM_TLS_H */
diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h
new file mode 100644
index 000000000000..fa88d09fa3d9
--- /dev/null
+++ b/arch/arm/include/asm/v7m.h
@@ -0,0 +1,44 @@
1/*
2 * Common defines for v7m cpus
3 */
4#define V7M_SCS_ICTR IOMEM(0xe000e004)
5#define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
6
7#define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
8
9#define V7M_SCB_CPUID 0x00
10
11#define V7M_SCB_ICSR 0x04
12#define V7M_SCB_ICSR_PENDSVSET (1 << 28)
13#define V7M_SCB_ICSR_PENDSVCLR (1 << 27)
14#define V7M_SCB_ICSR_RETTOBASE (1 << 11)
15
16#define V7M_SCB_VTOR 0x08
17
18#define V7M_SCB_SCR 0x10
19#define V7M_SCB_SCR_SLEEPDEEP (1 << 2)
20
21#define V7M_SCB_CCR 0x14
22#define V7M_SCB_CCR_STKALIGN (1 << 9)
23
24#define V7M_SCB_SHPR2 0x1c
25#define V7M_SCB_SHPR3 0x20
26
27#define V7M_SCB_SHCSR 0x24
28#define V7M_SCB_SHCSR_USGFAULTENA (1 << 18)
29#define V7M_SCB_SHCSR_BUSFAULTENA (1 << 17)
30#define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16)
31
32#define V7M_xPSR_FRAMEPTRALIGN 0x00000200
33#define V7M_xPSR_EXCEPTIONNO 0x000001ff
34
35/*
36 * When branching to an address that has bits [31:28] == 0xf an exception return
37 * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP
38 * extension Bit [4] defines if the exception frame has space allocated for FP
39 * state information, SBOP otherwise. Bit [3] defines the mode that is returned
40 * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
41 * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
42 */
43#define EXC_RET_STACK_MASK 0x00000004
44#define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd
diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h
index 799f42ecca63..7704e28c3483 100644
--- a/arch/arm/include/asm/xen/hypercall.h
+++ b/arch/arm/include/asm/xen/hypercall.h
@@ -47,6 +47,7 @@ unsigned long HYPERVISOR_hvm_op(int op, void *arg);
47int HYPERVISOR_memory_op(unsigned int cmd, void *arg); 47int HYPERVISOR_memory_op(unsigned int cmd, void *arg);
48int HYPERVISOR_physdev_op(int cmd, void *arg); 48int HYPERVISOR_physdev_op(int cmd, void *arg);
49int HYPERVISOR_vcpu_op(int cmd, int vcpuid, void *extra_args); 49int HYPERVISOR_vcpu_op(int cmd, int vcpuid, void *extra_args);
50int HYPERVISOR_tmem_op(void *arg);
50 51
51static inline void 52static inline void
52MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va, 53MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va,
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
index 30cdacb675af..359a7b50b158 100644
--- a/arch/arm/include/asm/xen/page.h
+++ b/arch/arm/include/asm/xen/page.h
@@ -1,7 +1,6 @@
1#ifndef _ASM_ARM_XEN_PAGE_H 1#ifndef _ASM_ARM_XEN_PAGE_H
2#define _ASM_ARM_XEN_PAGE_H 2#define _ASM_ARM_XEN_PAGE_H
3 3
4#include <asm/mach/map.h>
5#include <asm/page.h> 4#include <asm/page.h>
6#include <asm/pgtable.h> 5#include <asm/pgtable.h>
7 6
@@ -88,6 +87,6 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
88 return __set_phys_to_machine(pfn, mfn); 87 return __set_phys_to_machine(pfn, mfn);
89} 88}
90 89
91#define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY); 90#define xen_remap(cookie, size) ioremap_cached((cookie), (size));
92 91
93#endif /* _ASM_ARM_XEN_PAGE_H */ 92#endif /* _ASM_ARM_XEN_PAGE_H */
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 91d38e38a0b4..29da84e183f4 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -65,6 +65,14 @@
65#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR 65#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
66#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) 66#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
67 67
68#define IMX6SL_UART1_BASE_ADDR 0x02020000
69#define IMX6SL_UART2_BASE_ADDR 0x02024000
70#define IMX6SL_UART3_BASE_ADDR 0x02034000
71#define IMX6SL_UART4_BASE_ADDR 0x02038000
72#define IMX6SL_UART5_BASE_ADDR 0x02018000
73#define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR
74#define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n)
75
68#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT) 76#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
69 77
70#ifdef CONFIG_DEBUG_IMX1_UART 78#ifdef CONFIG_DEBUG_IMX1_UART
@@ -83,6 +91,8 @@
83#define UART_PADDR IMX_DEBUG_UART_BASE(IMX53) 91#define UART_PADDR IMX_DEBUG_UART_BASE(IMX53)
84#elif defined(CONFIG_DEBUG_IMX6Q_UART) 92#elif defined(CONFIG_DEBUG_IMX6Q_UART)
85#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q) 93#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q)
94#elif defined(CONFIG_DEBUG_IMX6SL_UART)
95#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL)
86#endif 96#endif
87 97
88#endif /* __DEBUG_IMX_UART_H */ 98#endif /* __DEBUG_IMX_UART_H */
diff --git a/arch/arm/include/debug/keystone.S b/arch/arm/include/debug/keystone.S
new file mode 100644
index 000000000000..9aef9ba3f4f0
--- /dev/null
+++ b/arch/arm/include/debug/keystone.S
@@ -0,0 +1,43 @@
1/*
2 * Early serial debug output macro for Keystone SOCs
3 *
4 * Copyright 2013 Texas Instruments, Inc.
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 *
7 * Based on RMKs low level debug code.
8 * Copyright (C) 1994-1999 Russell King
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/serial_reg.h>
16
17#define UART_SHIFT 2
18#if defined(CONFIG_DEBUG_KEYSTONE_UART0)
19#define UART_PHYS 0x02530c00
20#define UART_VIRT 0xfeb30c00
21#elif defined(CONFIG_DEBUG_KEYSTONE_UART1)
22#define UART_PHYS 0x02531000
23#define UART_VIRT 0xfeb31000
24#endif
25
26 .macro addruart, rp, rv, tmp
27 ldr \rv, =UART_VIRT @ physical base address
28 ldr \rp, =UART_PHYS @ virtual base address
29 .endm
30
31 .macro senduart,rd,rx
32 str \rd, [\rx, #UART_TX << UART_SHIFT]
33 .endm
34
35 .macro busyuart,rd,rx
361002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT]
37 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
38 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
39 bne 1002b
40 .endm
41
42 .macro waituart,rd,rx
43 .endm
diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S
index df191afa3be1..6517311a1c91 100644
--- a/arch/arm/include/debug/mvebu.S
+++ b/arch/arm/include/debug/mvebu.S
@@ -11,7 +11,12 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12*/ 12*/
13 13
14#ifdef CONFIG_DEBUG_MVEBU_UART_ALTERNATE
15#define ARMADA_370_XP_REGS_PHYS_BASE 0xf1000000
16#else
14#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 17#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
18#endif
19
15#define ARMADA_370_XP_REGS_VIRT_BASE 0xfec00000 20#define ARMADA_370_XP_REGS_VIRT_BASE 0xfec00000
16 21
17 .macro addruart, rp, rv, tmp 22 .macro addruart, rp, rv, tmp
diff --git a/arch/arm/include/debug/nspire.S b/arch/arm/include/debug/nspire.S
new file mode 100644
index 000000000000..886fd276fcbc
--- /dev/null
+++ b/arch/arm/include/debug/nspire.S
@@ -0,0 +1,28 @@
1/*
2 * linux/arch/arm/include/debug/nspire.S
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#define NSPIRE_EARLY_UART_PHYS_BASE 0x90020000
13#define NSPIRE_EARLY_UART_VIRT_BASE 0xfee20000
14
15.macro addruart, rp, rv, tmp
16 ldr \rp, =(NSPIRE_EARLY_UART_PHYS_BASE) @ physical base address
17 ldr \rv, =(NSPIRE_EARLY_UART_VIRT_BASE) @ virtual base address
18.endm
19
20
21#ifdef CONFIG_DEBUG_NSPIRE_CX_UART
22#include <asm/hardware/debug-pl01x.S>
23#endif
24
25#ifdef CONFIG_DEBUG_NSPIRE_CLASSIC_UART
26#define UART_SHIFT 2
27#include <asm/hardware/debug-8250.S>
28#endif
diff --git a/arch/arm/include/debug/rockchip.S b/arch/arm/include/debug/rockchip.S
new file mode 100644
index 000000000000..cfd883e69588
--- /dev/null
+++ b/arch/arm/include/debug/rockchip.S
@@ -0,0 +1,42 @@
1/*
2 * Early serial output macro for Rockchip SoCs
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#if defined(CONFIG_DEBUG_RK29_UART0)
14#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20060000
15#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed60000
16#elif defined(CONFIG_DEBUG_RK29_UART1)
17#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000
18#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000
19#elif defined(CONFIG_DEBUG_RK29_UART2)
20#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000
21#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000
22#elif defined(CONFIG_DEBUG_RK3X_UART0)
23#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10124000
24#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb24000
25#elif defined(CONFIG_DEBUG_RK3X_UART1)
26#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10126000
27#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb26000
28#elif defined(CONFIG_DEBUG_RK3X_UART2)
29#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000
30#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000
31#elif defined(CONFIG_DEBUG_RK3X_UART3)
32#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000
33#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000
34#endif
35
36 .macro addruart, rp, rv, tmp
37 ldr \rp, =ROCKCHIP_UART_DEBUG_PHYS_BASE
38 ldr \rv, =ROCKCHIP_UART_DEBUG_VIRT_BASE
39 .endm
40
41#define UART_SHIFT 2
42#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/include/debug/sti.S b/arch/arm/include/debug/sti.S
new file mode 100644
index 000000000000..e3aa58ff1776
--- /dev/null
+++ b/arch/arm/include/debug/sti.S
@@ -0,0 +1,61 @@
1/*
2 * arch/arm/include/debug/sti.S
3 *
4 * Debugging macro include header
5 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#define STIH41X_COMMS_BASE 0xfed00000
13#define STIH41X_ASC2_BASE (STIH41X_COMMS_BASE+0x32000)
14
15#define STIH41X_SBC_LPM_BASE 0xfe400000
16#define STIH41X_SBC_COMMS_BASE (STIH41X_SBC_LPM_BASE + 0x100000)
17#define STIH41X_SBC_ASC1_BASE (STIH41X_SBC_COMMS_BASE + 0x31000)
18
19
20#define VIRT_ADDRESS(x) (x - 0x1000000)
21
22#if IS_ENABLED(CONFIG_STIH41X_DEBUG_ASC2)
23#define DEBUG_LL_UART_BASE STIH41X_ASC2_BASE
24#endif
25
26#if IS_ENABLED(CONFIG_STIH41X_DEBUG_SBC_ASC1)
27#define DEBUG_LL_UART_BASE STIH41X_SBC_ASC1_BASE
28#endif
29
30#ifndef DEBUG_LL_UART_BASE
31#error "DEBUG UART is not Configured"
32#endif
33
34#define ASC_TX_BUF_OFF 0x04
35#define ASC_CTRL_OFF 0x0c
36#define ASC_STA_OFF 0x14
37
38#define ASC_STA_TX_FULL (1<<9)
39#define ASC_STA_TX_EMPTY (1<<1)
40
41
42 .macro addruart, rp, rv, tmp
43 ldr \rp, =DEBUG_LL_UART_BASE @ physical base
44 ldr \rv, =VIRT_ADDRESS(DEBUG_LL_UART_BASE) @ virt base
45 .endm
46
47 .macro senduart,rd,rx
48 strb \rd, [\rx, #ASC_TX_BUF_OFF]
49 .endm
50
51 .macro waituart,rd,rx
521001: ldr \rd, [\rx, #ASC_STA_OFF]
53 tst \rd, #ASC_STA_TX_FULL
54 bne 1001b
55 .endm
56
57 .macro busyuart,rd,rx
581001: ldr \rd, [\rx, #ASC_STA_OFF]
59 tst \rd, #ASC_STA_TX_EMPTY
60 beq 1001b
61 .endm
diff --git a/arch/arm/include/debug/u300.S b/arch/arm/include/debug/u300.S
new file mode 100644
index 000000000000..6f04f08a203c
--- /dev/null
+++ b/arch/arm/include/debug/u300.S
@@ -0,0 +1,18 @@
1/*
2 * Copyright (C) 2006-2013 ST-Ericsson AB
3 * License terms: GNU General Public License (GPL) version 2
4 * Debugging macro include header.
5 * Author: Linus Walleij <linus.walleij@stericsson.com>
6 */
7#define U300_SLOW_PER_PHYS_BASE 0xc0010000
8#define U300_SLOW_PER_VIRT_BASE 0xff000000
9
10 .macro addruart, rp, rv, tmp
11 /* If we move the address using MMU, use this. */
12 ldr \rp, = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address
13 ldr \rv, = U300_SLOW_PER_VIRT_BASE @ MMU on, virtual address
14 orr \rp, \rp, #0x00003000
15 orr \rv, \rv, #0x00003000
16 .endm
17
18#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/include/debug/vexpress.S b/arch/arm/include/debug/vexpress.S
index dc8e882a6257..acafb229e2b6 100644
--- a/arch/arm/include/debug/vexpress.S
+++ b/arch/arm/include/debug/vexpress.S
@@ -16,6 +16,8 @@
16#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000 16#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
17#define DEBUG_LL_UART_OFFSET_RS1 0x00090000 17#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
18 18
19#define DEBUG_LL_UART_PHYS_CRX 0xb0090000
20
19#define DEBUG_LL_VIRT_BASE 0xf8000000 21#define DEBUG_LL_VIRT_BASE 0xf8000000
20 22
21#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT) 23#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
@@ -67,6 +69,14 @@
67 69
68#include <asm/hardware/debug-pl01x.S> 70#include <asm/hardware/debug-pl01x.S>
69 71
72#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CRX)
73
74 .macro addruart,rp,tmp,tmp2
75 ldr \rp, =DEBUG_LL_UART_PHYS_CRX
76 .endm
77
78#include <asm/hardware/debug-pl01x.S>
79
70#else /* CONFIG_DEBUG_LL_UART_NONE */ 80#else /* CONFIG_DEBUG_LL_UART_NONE */
71 81
72 .macro addruart, rp, rv, tmp 82 .macro addruart, rp, rv, tmp
diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index 3688fd15a32d..6d34d080372a 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -25,6 +25,6 @@
25#define HWCAP_IDIVT (1 << 18) 25#define HWCAP_IDIVT (1 << 18)
26#define HWCAP_VFPD32 (1 << 19) /* set if VFP has 32 regs (not 16) */ 26#define HWCAP_VFPD32 (1 << 19) /* set if VFP has 32 regs (not 16) */
27#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT) 27#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT)
28 28#define HWCAP_LPAE (1 << 20)
29 29
30#endif /* _UAPI__ASMARM_HWCAP_H */ 30#endif /* _UAPI__ASMARM_HWCAP_H */
diff --git a/arch/arm/include/uapi/asm/ptrace.h b/arch/arm/include/uapi/asm/ptrace.h
index 96ee0929790f..5af0ed1b825a 100644
--- a/arch/arm/include/uapi/asm/ptrace.h
+++ b/arch/arm/include/uapi/asm/ptrace.h
@@ -34,28 +34,47 @@
34 34
35/* 35/*
36 * PSR bits 36 * PSR bits
37 * Note on V7M there is no mode contained in the PSR
37 */ 38 */
38#define USR26_MODE 0x00000000 39#define USR26_MODE 0x00000000
39#define FIQ26_MODE 0x00000001 40#define FIQ26_MODE 0x00000001
40#define IRQ26_MODE 0x00000002 41#define IRQ26_MODE 0x00000002
41#define SVC26_MODE 0x00000003 42#define SVC26_MODE 0x00000003
43#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
44/*
45 * Use 0 here to get code right that creates a userspace
46 * or kernel space thread.
47 */
48#define USR_MODE 0x00000000
49#define SVC_MODE 0x00000000
50#else
42#define USR_MODE 0x00000010 51#define USR_MODE 0x00000010
52#define SVC_MODE 0x00000013
53#endif
43#define FIQ_MODE 0x00000011 54#define FIQ_MODE 0x00000011
44#define IRQ_MODE 0x00000012 55#define IRQ_MODE 0x00000012
45#define SVC_MODE 0x00000013
46#define ABT_MODE 0x00000017 56#define ABT_MODE 0x00000017
47#define HYP_MODE 0x0000001a 57#define HYP_MODE 0x0000001a
48#define UND_MODE 0x0000001b 58#define UND_MODE 0x0000001b
49#define SYSTEM_MODE 0x0000001f 59#define SYSTEM_MODE 0x0000001f
50#define MODE32_BIT 0x00000010 60#define MODE32_BIT 0x00000010
51#define MODE_MASK 0x0000001f 61#define MODE_MASK 0x0000001f
52#define PSR_T_BIT 0x00000020 62
53#define PSR_F_BIT 0x00000040 63#define V4_PSR_T_BIT 0x00000020 /* >= V4T, but not V7M */
54#define PSR_I_BIT 0x00000080 64#define V7M_PSR_T_BIT 0x01000000
55#define PSR_A_BIT 0x00000100 65#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
56#define PSR_E_BIT 0x00000200 66#define PSR_T_BIT V7M_PSR_T_BIT
57#define PSR_J_BIT 0x01000000 67#else
58#define PSR_Q_BIT 0x08000000 68/* for compatibility */
69#define PSR_T_BIT V4_PSR_T_BIT
70#endif
71
72#define PSR_F_BIT 0x00000040 /* >= V4, but not V7M */
73#define PSR_I_BIT 0x00000080 /* >= V4, but not V7M */
74#define PSR_A_BIT 0x00000100 /* >= V6, but not V7M */
75#define PSR_E_BIT 0x00000200 /* >= V6, but not V7M */
76#define PSR_J_BIT 0x01000000 /* >= V5J, but not V7M */
77#define PSR_Q_BIT 0x08000000 /* >= V5E, including V7M */
59#define PSR_V_BIT 0x10000000 78#define PSR_V_BIT 0x10000000
60#define PSR_C_BIT 0x20000000 79#define PSR_C_BIT 0x20000000
61#define PSR_Z_BIT 0x40000000 80#define PSR_Z_BIT 0x40000000
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 10:40:15 -0500