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-rw-r--r--arch/arm/include/asm/arch_timer.h14
-rw-r--r--arch/arm/include/asm/assembler.h4
-rw-r--r--arch/arm/include/asm/barrier.h32
-rw-r--r--arch/arm/include/asm/cacheflush.h5
-rw-r--r--arch/arm/include/asm/dma-contiguous.h2
-rw-r--r--arch/arm/include/asm/elf.h2
-rw-r--r--arch/arm/include/asm/hardware/debug-8250.S29
-rw-r--r--arch/arm/include/asm/kvm_mmu.h2
-rw-r--r--arch/arm/include/asm/mach/arch.h4
-rw-r--r--arch/arm/include/asm/memblock.h3
-rw-r--r--arch/arm/include/asm/module.h2
-rw-r--r--arch/arm/include/asm/neon.h36
-rw-r--r--arch/arm/include/asm/pgtable.h2
-rw-r--r--arch/arm/include/asm/prom.h4
-rw-r--r--arch/arm/include/asm/smp_plat.h3
-rw-r--r--arch/arm/include/asm/spinlock.h53
-rw-r--r--arch/arm/include/asm/switch_to.h10
-rw-r--r--arch/arm/include/asm/thread_info.h11
-rw-r--r--arch/arm/include/asm/tlb.h7
-rw-r--r--arch/arm/include/asm/tlbflush.h181
-rw-r--r--arch/arm/include/asm/types.h40
-rw-r--r--arch/arm/include/asm/v7m.h12
-rw-r--r--arch/arm/include/asm/xor.h73
-rw-r--r--arch/arm/include/debug/8250.S54
-rw-r--r--arch/arm/include/debug/8250_32.S27
-rw-r--r--arch/arm/include/debug/bcm2835.S22
-rw-r--r--arch/arm/include/debug/cns3xxx.S19
-rw-r--r--arch/arm/include/debug/highbank.S17
-rw-r--r--arch/arm/include/debug/keystone.S43
-rw-r--r--arch/arm/include/debug/mvebu.S30
-rw-r--r--arch/arm/include/debug/mxs.S27
-rw-r--r--arch/arm/include/debug/nomadik.S20
-rw-r--r--arch/arm/include/debug/nspire.S28
-rw-r--r--arch/arm/include/debug/picoxcell.S19
-rw-r--r--arch/arm/include/debug/pl01x.S (renamed from arch/arm/include/asm/hardware/debug-pl01x.S)9
-rw-r--r--arch/arm/include/debug/pxa.S33
-rw-r--r--arch/arm/include/debug/rockchip.S42
-rw-r--r--arch/arm/include/debug/socfpga.S21
-rw-r--r--arch/arm/include/debug/sunxi.S27
-rw-r--r--arch/arm/include/debug/tegra.S29
-rw-r--r--arch/arm/include/debug/u300.S18
-rw-r--r--arch/arm/include/debug/ux500.S2
-rw-r--r--arch/arm/include/debug/vexpress.S48
43 files changed, 500 insertions, 566 deletions
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index e406d575c94f..5665134bfa3e 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -17,7 +17,8 @@ int arch_timer_arch_init(void);
17 * nicely work out which register we want, and chuck away the rest of 17 * nicely work out which register we want, and chuck away the rest of
18 * the code. At least it does so with a recent GCC (4.6.3). 18 * the code. At least it does so with a recent GCC (4.6.3).
19 */ 19 */
20static inline void arch_timer_reg_write(const int access, const int reg, u32 val) 20static __always_inline
21void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
21{ 22{
22 if (access == ARCH_TIMER_PHYS_ACCESS) { 23 if (access == ARCH_TIMER_PHYS_ACCESS) {
23 switch (reg) { 24 switch (reg) {
@@ -28,9 +29,7 @@ static inline void arch_timer_reg_write(const int access, const int reg, u32 val
28 asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val)); 29 asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
29 break; 30 break;
30 } 31 }
31 } 32 } else if (access == ARCH_TIMER_VIRT_ACCESS) {
32
33 if (access == ARCH_TIMER_VIRT_ACCESS) {
34 switch (reg) { 33 switch (reg) {
35 case ARCH_TIMER_REG_CTRL: 34 case ARCH_TIMER_REG_CTRL:
36 asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val)); 35 asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
@@ -44,7 +43,8 @@ static inline void arch_timer_reg_write(const int access, const int reg, u32 val
44 isb(); 43 isb();
45} 44}
46 45
47static inline u32 arch_timer_reg_read(const int access, const int reg) 46static __always_inline
47u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
48{ 48{
49 u32 val = 0; 49 u32 val = 0;
50 50
@@ -57,9 +57,7 @@ static inline u32 arch_timer_reg_read(const int access, const int reg)
57 asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); 57 asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
58 break; 58 break;
59 } 59 }
60 } 60 } else if (access == ARCH_TIMER_VIRT_ACCESS) {
61
62 if (access == ARCH_TIMER_VIRT_ACCESS) {
63 switch (reg) { 61 switch (reg) {
64 case ARCH_TIMER_REG_CTRL: 62 case ARCH_TIMER_REG_CTRL:
65 asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val)); 63 asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index a5fef710af32..fcc1b5bf6979 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -220,9 +220,9 @@
220#ifdef CONFIG_SMP 220#ifdef CONFIG_SMP
221#if __LINUX_ARM_ARCH__ >= 7 221#if __LINUX_ARM_ARCH__ >= 7
222 .ifeqs "\mode","arm" 222 .ifeqs "\mode","arm"
223 ALT_SMP(dmb) 223 ALT_SMP(dmb ish)
224 .else 224 .else
225 ALT_SMP(W(dmb)) 225 ALT_SMP(W(dmb) ish)
226 .endif 226 .endif
227#elif __LINUX_ARM_ARCH__ == 6 227#elif __LINUX_ARM_ARCH__ == 6
228 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 228 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
index 8dcd9c702d90..60f15e274e6d 100644
--- a/arch/arm/include/asm/barrier.h
+++ b/arch/arm/include/asm/barrier.h
@@ -14,27 +14,27 @@
14#endif 14#endif
15 15
16#if __LINUX_ARM_ARCH__ >= 7 16#if __LINUX_ARM_ARCH__ >= 7
17#define isb() __asm__ __volatile__ ("isb" : : : "memory") 17#define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory")
18#define dsb() __asm__ __volatile__ ("dsb" : : : "memory") 18#define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory")
19#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") 19#define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory")
20#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6 20#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
21#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ 21#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
22 : : "r" (0) : "memory") 22 : : "r" (0) : "memory")
23#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ 23#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
24 : : "r" (0) : "memory") 24 : : "r" (0) : "memory")
25#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ 25#define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
26 : : "r" (0) : "memory") 26 : : "r" (0) : "memory")
27#elif defined(CONFIG_CPU_FA526) 27#elif defined(CONFIG_CPU_FA526)
28#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ 28#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
29 : : "r" (0) : "memory") 29 : : "r" (0) : "memory")
30#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ 30#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
31 : : "r" (0) : "memory") 31 : : "r" (0) : "memory")
32#define dmb() __asm__ __volatile__ ("" : : : "memory") 32#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
33#else 33#else
34#define isb() __asm__ __volatile__ ("" : : : "memory") 34#define isb(x) __asm__ __volatile__ ("" : : : "memory")
35#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ 35#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
36 : : "r" (0) : "memory") 36 : : "r" (0) : "memory")
37#define dmb() __asm__ __volatile__ ("" : : : "memory") 37#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
38#endif 38#endif
39 39
40#ifdef CONFIG_ARCH_HAS_BARRIERS 40#ifdef CONFIG_ARCH_HAS_BARRIERS
@@ -42,7 +42,7 @@
42#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP) 42#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
43#define mb() do { dsb(); outer_sync(); } while (0) 43#define mb() do { dsb(); outer_sync(); } while (0)
44#define rmb() dsb() 44#define rmb() dsb()
45#define wmb() mb() 45#define wmb() do { dsb(st); outer_sync(); } while (0)
46#else 46#else
47#define mb() barrier() 47#define mb() barrier()
48#define rmb() barrier() 48#define rmb() barrier()
@@ -54,9 +54,9 @@
54#define smp_rmb() barrier() 54#define smp_rmb() barrier()
55#define smp_wmb() barrier() 55#define smp_wmb() barrier()
56#else 56#else
57#define smp_mb() dmb() 57#define smp_mb() dmb(ish)
58#define smp_rmb() dmb() 58#define smp_rmb() smp_mb()
59#define smp_wmb() dmb() 59#define smp_wmb() dmb(ishst)
60#endif 60#endif
61 61
62#define read_barrier_depends() do { } while(0) 62#define read_barrier_depends() do { } while(0)
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 17d0ae8672fa..15f2d5bf8875 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -268,8 +268,7 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr
268 * Harvard caches are synchronised for the user space address range. 268 * Harvard caches are synchronised for the user space address range.
269 * This is used for the ARM private sys_cacheflush system call. 269 * This is used for the ARM private sys_cacheflush system call.
270 */ 270 */
271#define flush_cache_user_range(start,end) \ 271#define flush_cache_user_range(s,e) __cpuc_coherent_user_range(s,e)
272 __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
273 272
274/* 273/*
275 * Perform necessary cache operations to ensure that data previously 274 * Perform necessary cache operations to ensure that data previously
@@ -352,7 +351,7 @@ static inline void flush_cache_vmap(unsigned long start, unsigned long end)
352 * set_pte_at() called from vmap_pte_range() does not 351 * set_pte_at() called from vmap_pte_range() does not
353 * have a DSB after cleaning the cache line. 352 * have a DSB after cleaning the cache line.
354 */ 353 */
355 dsb(); 354 dsb(ishst);
356} 355}
357 356
358static inline void flush_cache_vunmap(unsigned long start, unsigned long end) 357static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
diff --git a/arch/arm/include/asm/dma-contiguous.h b/arch/arm/include/asm/dma-contiguous.h
index 3ed37b4d93da..e072bb2ba1b1 100644
--- a/arch/arm/include/asm/dma-contiguous.h
+++ b/arch/arm/include/asm/dma-contiguous.h
@@ -2,7 +2,7 @@
2#define ASMARM_DMA_CONTIGUOUS_H 2#define ASMARM_DMA_CONTIGUOUS_H
3 3
4#ifdef __KERNEL__ 4#ifdef __KERNEL__
5#ifdef CONFIG_CMA 5#ifdef CONFIG_DMA_CMA
6 6
7#include <linux/types.h> 7#include <linux/types.h>
8#include <asm-generic/dma-contiguous.h> 8#include <asm-generic/dma-contiguous.h>
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 56211f2084ef..f4b46d39b9cf 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -19,8 +19,6 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG];
19 19
20typedef struct user_fp elf_fpregset_t; 20typedef struct user_fp elf_fpregset_t;
21 21
22#define EM_ARM 40
23
24#define EF_ARM_EABI_MASK 0xff000000 22#define EF_ARM_EABI_MASK 0xff000000
25#define EF_ARM_EABI_UNKNOWN 0x00000000 23#define EF_ARM_EABI_UNKNOWN 0x00000000
26#define EF_ARM_EABI_VER1 0x01000000 24#define EF_ARM_EABI_VER1 0x01000000
diff --git a/arch/arm/include/asm/hardware/debug-8250.S b/arch/arm/include/asm/hardware/debug-8250.S
deleted file mode 100644
index 22c689255e6e..000000000000
--- a/arch/arm/include/asm/hardware/debug-8250.S
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * arch/arm/include/asm/hardware/debug-8250.S
3 *
4 * Copyright (C) 1994-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/serial_reg.h>
11
12 .macro senduart,rd,rx
13 strb \rd, [\rx, #UART_TX << UART_SHIFT]
14 .endm
15
16 .macro busyuart,rd,rx
171002: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
18 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
19 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
20 bne 1002b
21 .endm
22
23 .macro waituart,rd,rx
24#ifdef FLOW_CONTROL
251001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
26 tst \rd, #UART_MSR_CTS
27 beq 1001b
28#endif
29 .endm
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
index 472ac7091003..9b28c41f4ba9 100644
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -64,7 +64,7 @@ void kvm_clear_hyp_idmap(void);
64 64
65static inline void kvm_set_pte(pte_t *pte, pte_t new_pte) 65static inline void kvm_set_pte(pte_t *pte, pte_t new_pte)
66{ 66{
67 pte_val(*pte) = new_pte; 67 *pte = new_pte;
68 /* 68 /*
69 * flush_pmd_entry just takes a void pointer and cleans the necessary 69 * flush_pmd_entry just takes a void pointer and cleans the necessary
70 * cache entries, so we can reuse the function for ptes. 70 * cache entries, so we can reuse the function for ptes.
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 441efc491b50..69b879ac0289 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -65,12 +65,12 @@ struct machine_desc {
65/* 65/*
66 * Current machine - only accessible during boot. 66 * Current machine - only accessible during boot.
67 */ 67 */
68extern struct machine_desc *machine_desc; 68extern const struct machine_desc *machine_desc;
69 69
70/* 70/*
71 * Machine type table - also only accessible during boot 71 * Machine type table - also only accessible during boot
72 */ 72 */
73extern struct machine_desc __arch_info_begin[], __arch_info_end[]; 73extern const struct machine_desc __arch_info_begin[], __arch_info_end[];
74#define for_each_machine_desc(p) \ 74#define for_each_machine_desc(p) \
75 for (p = __arch_info_begin; p < __arch_info_end; p++) 75 for (p = __arch_info_begin; p < __arch_info_end; p++)
76 76
diff --git a/arch/arm/include/asm/memblock.h b/arch/arm/include/asm/memblock.h
index 00ca5f92648e..c2f5102ae659 100644
--- a/arch/arm/include/asm/memblock.h
+++ b/arch/arm/include/asm/memblock.h
@@ -4,8 +4,7 @@
4struct meminfo; 4struct meminfo;
5struct machine_desc; 5struct machine_desc;
6 6
7extern void arm_memblock_init(struct meminfo *, struct machine_desc *); 7void arm_memblock_init(struct meminfo *, const struct machine_desc *);
8
9phys_addr_t arm_memblock_steal(phys_addr_t size, phys_addr_t align); 8phys_addr_t arm_memblock_steal(phys_addr_t size, phys_addr_t align);
10 9
11#endif 10#endif
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
index 0d3a28dbc8e5..ed690c49ef93 100644
--- a/arch/arm/include/asm/module.h
+++ b/arch/arm/include/asm/module.h
@@ -12,6 +12,8 @@ enum {
12 ARM_SEC_CORE, 12 ARM_SEC_CORE,
13 ARM_SEC_EXIT, 13 ARM_SEC_EXIT,
14 ARM_SEC_DEVEXIT, 14 ARM_SEC_DEVEXIT,
15 ARM_SEC_HOT,
16 ARM_SEC_UNLIKELY,
15 ARM_SEC_MAX, 17 ARM_SEC_MAX,
16}; 18};
17 19
diff --git a/arch/arm/include/asm/neon.h b/arch/arm/include/asm/neon.h
new file mode 100644
index 000000000000..8f730fe70093
--- /dev/null
+++ b/arch/arm/include/asm/neon.h
@@ -0,0 +1,36 @@
1/*
2 * linux/arch/arm/include/asm/neon.h
3 *
4 * Copyright (C) 2013 Linaro Ltd <ard.biesheuvel@linaro.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <asm/hwcap.h>
12
13#define cpu_has_neon() (!!(elf_hwcap & HWCAP_NEON))
14
15#ifdef __ARM_NEON__
16
17/*
18 * If you are affected by the BUILD_BUG below, it probably means that you are
19 * using NEON code /and/ calling the kernel_neon_begin() function from the same
20 * compilation unit. To prevent issues that may arise from GCC reordering or
21 * generating(1) NEON instructions outside of these begin/end functions, the
22 * only supported way of using NEON code in the kernel is by isolating it in a
23 * separate compilation unit, and calling it from another unit from inside a
24 * kernel_neon_begin/kernel_neon_end pair.
25 *
26 * (1) Current GCC (4.7) might generate NEON instructions at O3 level if
27 * -mpfu=neon is set.
28 */
29
30#define kernel_neon_begin() \
31 BUILD_BUG_ON_MSG(1, "kernel_neon_begin() called from NEON code")
32
33#else
34void kernel_neon_begin(void);
35#endif
36void kernel_neon_end(void);
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 04aeb02d2e11..be956dbf6bae 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -100,7 +100,7 @@ extern pgprot_t pgprot_s2_device;
100#define PAGE_HYP _MOD_PROT(pgprot_kernel, L_PTE_HYP) 100#define PAGE_HYP _MOD_PROT(pgprot_kernel, L_PTE_HYP)
101#define PAGE_HYP_DEVICE _MOD_PROT(pgprot_hyp_device, L_PTE_HYP) 101#define PAGE_HYP_DEVICE _MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
102#define PAGE_S2 _MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY) 102#define PAGE_S2 _MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
103#define PAGE_S2_DEVICE _MOD_PROT(pgprot_s2_device, L_PTE_USER | L_PTE_S2_RDONLY) 103#define PAGE_S2_DEVICE _MOD_PROT(pgprot_s2_device, L_PTE_S2_RDWR)
104 104
105#define __PAGE_NONE __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE) 105#define __PAGE_NONE __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
106#define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN) 106#define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
diff --git a/arch/arm/include/asm/prom.h b/arch/arm/include/asm/prom.h
index a219227c3e43..4a2985e21969 100644
--- a/arch/arm/include/asm/prom.h
+++ b/arch/arm/include/asm/prom.h
@@ -15,13 +15,13 @@
15 15
16#ifdef CONFIG_OF 16#ifdef CONFIG_OF
17 17
18extern struct machine_desc *setup_machine_fdt(unsigned int dt_phys); 18extern const struct machine_desc *setup_machine_fdt(unsigned int dt_phys);
19extern void arm_dt_memblock_reserve(void); 19extern void arm_dt_memblock_reserve(void);
20extern void __init arm_dt_init_cpu_maps(void); 20extern void __init arm_dt_init_cpu_maps(void);
21 21
22#else /* CONFIG_OF */ 22#else /* CONFIG_OF */
23 23
24static inline struct machine_desc *setup_machine_fdt(unsigned int dt_phys) 24static inline const struct machine_desc *setup_machine_fdt(unsigned int dt_phys)
25{ 25{
26 return NULL; 26 return NULL;
27} 27}
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 6462a721ebd4..a252c0bfacf5 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -88,4 +88,7 @@ static inline u32 mpidr_hash_size(void)
88{ 88{
89 return 1 << mpidr_hash.bits; 89 return 1 << mpidr_hash.bits;
90} 90}
91
92extern int platform_can_cpu_hotplug(void);
93
91#endif 94#endif
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index f8b8965666e9..4f2c28060c9a 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -46,7 +46,7 @@ static inline void dsb_sev(void)
46{ 46{
47#if __LINUX_ARM_ARCH__ >= 7 47#if __LINUX_ARM_ARCH__ >= 7
48 __asm__ __volatile__ ( 48 __asm__ __volatile__ (
49 "dsb\n" 49 "dsb ishst\n"
50 SEV 50 SEV
51 ); 51 );
52#else 52#else
@@ -107,7 +107,7 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
107 " subs %1, %0, %0, ror #16\n" 107 " subs %1, %0, %0, ror #16\n"
108 " addeq %0, %0, %4\n" 108 " addeq %0, %0, %4\n"
109 " strexeq %2, %0, [%3]" 109 " strexeq %2, %0, [%3]"
110 : "=&r" (slock), "=&r" (contended), "=r" (res) 110 : "=&r" (slock), "=&r" (contended), "=&r" (res)
111 : "r" (&lock->slock), "I" (1 << TICKET_SHIFT) 111 : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
112 : "cc"); 112 : "cc");
113 } while (res); 113 } while (res);
@@ -168,17 +168,20 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
168 168
169static inline int arch_write_trylock(arch_rwlock_t *rw) 169static inline int arch_write_trylock(arch_rwlock_t *rw)
170{ 170{
171 unsigned long tmp; 171 unsigned long contended, res;
172 172
173 __asm__ __volatile__( 173 do {
174" ldrex %0, [%1]\n" 174 __asm__ __volatile__(
175" teq %0, #0\n" 175 " ldrex %0, [%2]\n"
176" strexeq %0, %2, [%1]" 176 " mov %1, #0\n"
177 : "=&r" (tmp) 177 " teq %0, #0\n"
178 : "r" (&rw->lock), "r" (0x80000000) 178 " strexeq %1, %3, [%2]"
179 : "cc"); 179 : "=&r" (contended), "=&r" (res)
180 : "r" (&rw->lock), "r" (0x80000000)
181 : "cc");
182 } while (res);
180 183
181 if (tmp == 0) { 184 if (!contended) {
182 smp_mb(); 185 smp_mb();
183 return 1; 186 return 1;
184 } else { 187 } else {
@@ -254,18 +257,26 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
254 257
255static inline int arch_read_trylock(arch_rwlock_t *rw) 258static inline int arch_read_trylock(arch_rwlock_t *rw)
256{ 259{
257 unsigned long tmp, tmp2 = 1; 260 unsigned long contended, res;
258 261
259 __asm__ __volatile__( 262 do {
260" ldrex %0, [%2]\n" 263 __asm__ __volatile__(
261" adds %0, %0, #1\n" 264 " ldrex %0, [%2]\n"
262" strexpl %1, %0, [%2]\n" 265 " mov %1, #0\n"
263 : "=&r" (tmp), "+r" (tmp2) 266 " adds %0, %0, #1\n"
264 : "r" (&rw->lock) 267 " strexpl %1, %0, [%2]"
265 : "cc"); 268 : "=&r" (contended), "=&r" (res)
269 : "r" (&rw->lock)
270 : "cc");
271 } while (res);
266 272
267 smp_mb(); 273 /* If the lock is negative, then it is already held for write. */
268 return tmp2 == 0; 274 if (contended < 0x80000000) {
275 smp_mb();
276 return 1;
277 } else {
278 return 0;
279 }
269} 280}
270 281
271/* read_can_lock - would read_trylock() succeed? */ 282/* read_can_lock - would read_trylock() succeed? */
diff --git a/arch/arm/include/asm/switch_to.h b/arch/arm/include/asm/switch_to.h
index fa09e6b49bf1..c99e259469f7 100644
--- a/arch/arm/include/asm/switch_to.h
+++ b/arch/arm/include/asm/switch_to.h
@@ -4,6 +4,16 @@
4#include <linux/thread_info.h> 4#include <linux/thread_info.h>
5 5
6/* 6/*
7 * For v7 SMP cores running a preemptible kernel we may be pre-empted
8 * during a TLB maintenance operation, so execute an inner-shareable dsb
9 * to ensure that the maintenance completes in case we migrate to another
10 * CPU.
11 */
12#if defined(CONFIG_PREEMPT) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7)
13#define finish_arch_switch(prev) dsb(ish)
14#endif
15
16/*
7 * switch_to(prev, next) should switch from task `prev' to `next' 17 * switch_to(prev, next) should switch from task `prev' to `next'
8 * `prev' will never be the same as `next'. schedule() itself 18 * `prev' will never be the same as `next'. schedule() itself
9 * contains the memory barrier to tell GCC not to cache `current'. 19 * contains the memory barrier to tell GCC not to cache `current'.
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 2b8114fcba09..df5e13d64f2c 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -43,6 +43,16 @@ struct cpu_context_save {
43 __u32 extra[2]; /* Xscale 'acc' register, etc */ 43 __u32 extra[2]; /* Xscale 'acc' register, etc */
44}; 44};
45 45
46struct arm_restart_block {
47 union {
48 /* For user cache flushing */
49 struct {
50 unsigned long start;
51 unsigned long end;
52 } cache;
53 };
54};
55
46/* 56/*
47 * low level task data that entry.S needs immediate access to. 57 * low level task data that entry.S needs immediate access to.
48 * __switch_to() assumes cpu_context follows immediately after cpu_domain. 58 * __switch_to() assumes cpu_context follows immediately after cpu_domain.
@@ -68,6 +78,7 @@ struct thread_info {
68 unsigned long thumbee_state; /* ThumbEE Handler Base register */ 78 unsigned long thumbee_state; /* ThumbEE Handler Base register */
69#endif 79#endif
70 struct restart_block restart_block; 80 struct restart_block restart_block;
81 struct arm_restart_block arm_restart_block;
71}; 82};
72 83
73#define INIT_THREAD_INFO(tsk) \ 84#define INIT_THREAD_INFO(tsk) \
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index 46e7cfb3e721..0baf7f0d9394 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -43,6 +43,7 @@ struct mmu_gather {
43 struct mm_struct *mm; 43 struct mm_struct *mm;
44 unsigned int fullmm; 44 unsigned int fullmm;
45 struct vm_area_struct *vma; 45 struct vm_area_struct *vma;
46 unsigned long start, end;
46 unsigned long range_start; 47 unsigned long range_start;
47 unsigned long range_end; 48 unsigned long range_end;
48 unsigned int nr; 49 unsigned int nr;
@@ -107,10 +108,12 @@ static inline void tlb_flush_mmu(struct mmu_gather *tlb)
107} 108}
108 109
109static inline void 110static inline void
110tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int fullmm) 111tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned long start, unsigned long end)
111{ 112{
112 tlb->mm = mm; 113 tlb->mm = mm;
113 tlb->fullmm = fullmm; 114 tlb->fullmm = !(start | (end+1));
115 tlb->start = start;
116 tlb->end = end;
114 tlb->vma = NULL; 117 tlb->vma = NULL;
115 tlb->max = ARRAY_SIZE(tlb->local); 118 tlb->max = ARRAY_SIZE(tlb->local);
116 tlb->pages = tlb->local; 119 tlb->pages = tlb->local;
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index f467e9b3f8d5..38960264040c 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -319,67 +319,110 @@ extern struct cpu_tlb_fns cpu_tlb;
319#define tlb_op(f, regs, arg) __tlb_op(f, "p15, 0, %0, " regs, arg) 319#define tlb_op(f, regs, arg) __tlb_op(f, "p15, 0, %0, " regs, arg)
320#define tlb_l2_op(f, regs, arg) __tlb_op(f, "p15, 1, %0, " regs, arg) 320#define tlb_l2_op(f, regs, arg) __tlb_op(f, "p15, 1, %0, " regs, arg)
321 321
322static inline void local_flush_tlb_all(void) 322static inline void __local_flush_tlb_all(void)
323{ 323{
324 const int zero = 0; 324 const int zero = 0;
325 const unsigned int __tlb_flag = __cpu_tlb_flags; 325 const unsigned int __tlb_flag = __cpu_tlb_flags;
326 326
327 if (tlb_flag(TLB_WB))
328 dsb();
329
330 tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero); 327 tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero);
331 tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero); 328 tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero);
332 tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero); 329 tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero);
333 tlb_op(TLB_V7_UIS_FULL, "c8, c3, 0", zero); 330}
331
332static inline void local_flush_tlb_all(void)
333{
334 const int zero = 0;
335 const unsigned int __tlb_flag = __cpu_tlb_flags;
336
337 if (tlb_flag(TLB_WB))
338 dsb(nshst);
339
340 __local_flush_tlb_all();
341 tlb_op(TLB_V7_UIS_FULL, "c8, c7, 0", zero);
334 342
335 if (tlb_flag(TLB_BARRIER)) { 343 if (tlb_flag(TLB_BARRIER)) {
336 dsb(); 344 dsb(nsh);
337 isb(); 345 isb();
338 } 346 }
339} 347}
340 348
341static inline void local_flush_tlb_mm(struct mm_struct *mm) 349static inline void __flush_tlb_all(void)
342{ 350{
343 const int zero = 0; 351 const int zero = 0;
344 const int asid = ASID(mm);
345 const unsigned int __tlb_flag = __cpu_tlb_flags; 352 const unsigned int __tlb_flag = __cpu_tlb_flags;
346 353
347 if (tlb_flag(TLB_WB)) 354 if (tlb_flag(TLB_WB))
348 dsb(); 355 dsb(ishst);
356
357 __local_flush_tlb_all();
358 tlb_op(TLB_V7_UIS_FULL, "c8, c3, 0", zero);
359
360 if (tlb_flag(TLB_BARRIER)) {
361 dsb(ish);
362 isb();
363 }
364}
365
366static inline void __local_flush_tlb_mm(struct mm_struct *mm)
367{
368 const int zero = 0;
369 const int asid = ASID(mm);
370 const unsigned int __tlb_flag = __cpu_tlb_flags;
349 371
350 if (possible_tlb_flags & (TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) { 372 if (possible_tlb_flags & (TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) {
351 if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) { 373 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) {
352 tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero); 374 tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);
353 tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero); 375 tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);
354 tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero); 376 tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
355 } 377 }
356 put_cpu();
357 } 378 }
358 379
359 tlb_op(TLB_V6_U_ASID, "c8, c7, 2", asid); 380 tlb_op(TLB_V6_U_ASID, "c8, c7, 2", asid);
360 tlb_op(TLB_V6_D_ASID, "c8, c6, 2", asid); 381 tlb_op(TLB_V6_D_ASID, "c8, c6, 2", asid);
361 tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid); 382 tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid);
383}
384
385static inline void local_flush_tlb_mm(struct mm_struct *mm)
386{
387 const int asid = ASID(mm);
388 const unsigned int __tlb_flag = __cpu_tlb_flags;
389
390 if (tlb_flag(TLB_WB))
391 dsb(nshst);
392
393 __local_flush_tlb_mm(mm);
394 tlb_op(TLB_V7_UIS_ASID, "c8, c7, 2", asid);
395
396 if (tlb_flag(TLB_BARRIER))
397 dsb(nsh);
398}
399
400static inline void __flush_tlb_mm(struct mm_struct *mm)
401{
402 const unsigned int __tlb_flag = __cpu_tlb_flags;
403
404 if (tlb_flag(TLB_WB))
405 dsb(ishst);
406
407 __local_flush_tlb_mm(mm);
362#ifdef CONFIG_ARM_ERRATA_720789 408#ifdef CONFIG_ARM_ERRATA_720789
363 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", zero); 409 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", 0);
364#else 410#else
365 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", asid); 411 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", ASID(mm));
366#endif 412#endif
367 413
368 if (tlb_flag(TLB_BARRIER)) 414 if (tlb_flag(TLB_BARRIER))
369 dsb(); 415 dsb(ish);
370} 416}
371 417
372static inline void 418static inline void
373local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) 419__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
374{ 420{
375 const int zero = 0; 421 const int zero = 0;
376 const unsigned int __tlb_flag = __cpu_tlb_flags; 422 const unsigned int __tlb_flag = __cpu_tlb_flags;
377 423
378 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); 424 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
379 425
380 if (tlb_flag(TLB_WB))
381 dsb();
382
383 if (possible_tlb_flags & (TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) && 426 if (possible_tlb_flags & (TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) &&
384 cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { 427 cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
385 tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr); 428 tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr);
@@ -392,6 +435,36 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
392 tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", uaddr); 435 tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", uaddr);
393 tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", uaddr); 436 tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", uaddr);
394 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr); 437 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr);
438}
439
440static inline void
441local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
442{
443 const unsigned int __tlb_flag = __cpu_tlb_flags;
444
445 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
446
447 if (tlb_flag(TLB_WB))
448 dsb(nshst);
449
450 __local_flush_tlb_page(vma, uaddr);
451 tlb_op(TLB_V7_UIS_PAGE, "c8, c7, 1", uaddr);
452
453 if (tlb_flag(TLB_BARRIER))
454 dsb(nsh);
455}
456
457static inline void
458__flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
459{
460 const unsigned int __tlb_flag = __cpu_tlb_flags;
461
462 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
463
464 if (tlb_flag(TLB_WB))
465 dsb(ishst);
466
467 __local_flush_tlb_page(vma, uaddr);
395#ifdef CONFIG_ARM_ERRATA_720789 468#ifdef CONFIG_ARM_ERRATA_720789
396 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 3", uaddr & PAGE_MASK); 469 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 3", uaddr & PAGE_MASK);
397#else 470#else
@@ -399,19 +472,14 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
399#endif 472#endif
400 473
401 if (tlb_flag(TLB_BARRIER)) 474 if (tlb_flag(TLB_BARRIER))
402 dsb(); 475 dsb(ish);
403} 476}
404 477
405static inline void local_flush_tlb_kernel_page(unsigned long kaddr) 478static inline void __local_flush_tlb_kernel_page(unsigned long kaddr)
406{ 479{
407 const int zero = 0; 480 const int zero = 0;
408 const unsigned int __tlb_flag = __cpu_tlb_flags; 481 const unsigned int __tlb_flag = __cpu_tlb_flags;
409 482
410 kaddr &= PAGE_MASK;
411
412 if (tlb_flag(TLB_WB))
413 dsb();
414
415 tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr); 483 tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr);
416 tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr); 484 tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr);
417 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr); 485 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr);
@@ -421,26 +489,75 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
421 tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", kaddr); 489 tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", kaddr);
422 tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", kaddr); 490 tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", kaddr);
423 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr); 491 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr);
492}
493
494static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
495{
496 const unsigned int __tlb_flag = __cpu_tlb_flags;
497
498 kaddr &= PAGE_MASK;
499
500 if (tlb_flag(TLB_WB))
501 dsb(nshst);
502
503 __local_flush_tlb_kernel_page(kaddr);
504 tlb_op(TLB_V7_UIS_PAGE, "c8, c7, 1", kaddr);
505
506 if (tlb_flag(TLB_BARRIER)) {
507 dsb(nsh);
508 isb();
509 }
510}
511
512static inline void __flush_tlb_kernel_page(unsigned long kaddr)
513{
514 const unsigned int __tlb_flag = __cpu_tlb_flags;
515
516 kaddr &= PAGE_MASK;
517
518 if (tlb_flag(TLB_WB))
519 dsb(ishst);
520
521 __local_flush_tlb_kernel_page(kaddr);
424 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", kaddr); 522 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", kaddr);
425 523
426 if (tlb_flag(TLB_BARRIER)) { 524 if (tlb_flag(TLB_BARRIER)) {
427 dsb(); 525 dsb(ish);
428 isb(); 526 isb();
429 } 527 }
430} 528}
431 529
530/*
531 * Branch predictor maintenance is paired with full TLB invalidation, so
532 * there is no need for any barriers here.
533 */
534static inline void __local_flush_bp_all(void)
535{
536 const int zero = 0;
537 const unsigned int __tlb_flag = __cpu_tlb_flags;
538
539 if (tlb_flag(TLB_V6_BP))
540 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
541}
542
432static inline void local_flush_bp_all(void) 543static inline void local_flush_bp_all(void)
433{ 544{
434 const int zero = 0; 545 const int zero = 0;
435 const unsigned int __tlb_flag = __cpu_tlb_flags; 546 const unsigned int __tlb_flag = __cpu_tlb_flags;
436 547
548 __local_flush_bp_all();
437 if (tlb_flag(TLB_V7_UIS_BP)) 549 if (tlb_flag(TLB_V7_UIS_BP))
438 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));
439 else if (tlb_flag(TLB_V6_BP))
440 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); 550 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
551}
441 552
442 if (tlb_flag(TLB_BARRIER)) 553static inline void __flush_bp_all(void)
443 isb(); 554{
555 const int zero = 0;
556 const unsigned int __tlb_flag = __cpu_tlb_flags;
557
558 __local_flush_bp_all();
559 if (tlb_flag(TLB_V7_UIS_BP))
560 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));
444} 561}
445 562
446#include <asm/cputype.h> 563#include <asm/cputype.h>
@@ -461,7 +578,7 @@ static inline void dummy_flush_tlb_a15_erratum(void)
461 * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0. 578 * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0.
462 */ 579 */
463 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); 580 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
464 dsb(); 581 dsb(ish);
465} 582}
466#else 583#else
467static inline int erratum_a15_798181(void) 584static inline int erratum_a15_798181(void)
@@ -495,7 +612,7 @@ static inline void flush_pmd_entry(void *pmd)
495 tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd); 612 tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd);
496 613
497 if (tlb_flag(TLB_WB)) 614 if (tlb_flag(TLB_WB))
498 dsb(); 615 dsb(ishst);
499} 616}
500 617
501static inline void clean_pmd_entry(void *pmd) 618static inline void clean_pmd_entry(void *pmd)
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
new file mode 100644
index 000000000000..a53cdb8f068c
--- /dev/null
+++ b/arch/arm/include/asm/types.h
@@ -0,0 +1,40 @@
1#ifndef _ASM_TYPES_H
2#define _ASM_TYPES_H
3
4#include <asm-generic/int-ll64.h>
5
6/*
7 * The C99 types uintXX_t that are usually defined in 'stdint.h' are not as
8 * unambiguous on ARM as you would expect. For the types below, there is a
9 * difference on ARM between GCC built for bare metal ARM, GCC built for glibc
10 * and the kernel itself, which results in build errors if you try to build with
11 * -ffreestanding and include 'stdint.h' (such as when you include 'arm_neon.h'
12 * in order to use NEON intrinsics)
13 *
14 * As the typedefs for these types in 'stdint.h' are based on builtin defines
15 * supplied by GCC, we can tweak these to align with the kernel's idea of those
16 * types, so 'linux/types.h' and 'stdint.h' can be safely included from the same
17 * source file (provided that -ffreestanding is used).
18 *
19 * int32_t uint32_t uintptr_t
20 * bare metal GCC long unsigned long unsigned int
21 * glibc GCC int unsigned int unsigned int
22 * kernel int unsigned int unsigned long
23 */
24
25#ifdef __INT32_TYPE__
26#undef __INT32_TYPE__
27#define __INT32_TYPE__ int
28#endif
29
30#ifdef __UINT32_TYPE__
31#undef __UINT32_TYPE__
32#define __UINT32_TYPE__ unsigned int
33#endif
34
35#ifdef __UINTPTR_TYPE__
36#undef __UINTPTR_TYPE__
37#define __UINTPTR_TYPE__ unsigned long
38#endif
39
40#endif /* _ASM_TYPES_H */
diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h
index fa88d09fa3d9..615781c61627 100644
--- a/arch/arm/include/asm/v7m.h
+++ b/arch/arm/include/asm/v7m.h
@@ -15,6 +15,10 @@
15 15
16#define V7M_SCB_VTOR 0x08 16#define V7M_SCB_VTOR 0x08
17 17
18#define V7M_SCB_AIRCR 0x0c
19#define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
20#define V7M_SCB_AIRCR_SYSRESETREQ (1 << 2)
21
18#define V7M_SCB_SCR 0x10 22#define V7M_SCB_SCR 0x10
19#define V7M_SCB_SCR_SLEEPDEEP (1 << 2) 23#define V7M_SCB_SCR_SLEEPDEEP (1 << 2)
20 24
@@ -42,3 +46,11 @@
42 */ 46 */
43#define EXC_RET_STACK_MASK 0x00000004 47#define EXC_RET_STACK_MASK 0x00000004
44#define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd 48#define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd
49
50#ifndef __ASSEMBLY__
51
52enum reboot_mode;
53
54void armv7m_restart(enum reboot_mode mode, const char *cmd);
55
56#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/asm/xor.h
index 7604673dc427..4ffb26d4cad8 100644
--- a/arch/arm/include/asm/xor.h
+++ b/arch/arm/include/asm/xor.h
@@ -7,7 +7,10 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10#include <linux/hardirq.h>
10#include <asm-generic/xor.h> 11#include <asm-generic/xor.h>
12#include <asm/hwcap.h>
13#include <asm/neon.h>
11 14
12#define __XOR(a1, a2) a1 ^= a2 15#define __XOR(a1, a2) a1 ^= a2
13 16
@@ -138,4 +141,74 @@ static struct xor_block_template xor_block_arm4regs = {
138 xor_speed(&xor_block_arm4regs); \ 141 xor_speed(&xor_block_arm4regs); \
139 xor_speed(&xor_block_8regs); \ 142 xor_speed(&xor_block_8regs); \
140 xor_speed(&xor_block_32regs); \ 143 xor_speed(&xor_block_32regs); \
144 NEON_TEMPLATES; \
141 } while (0) 145 } while (0)
146
147#ifdef CONFIG_KERNEL_MODE_NEON
148
149extern struct xor_block_template const xor_block_neon_inner;
150
151static void
152xor_neon_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
153{
154 if (in_interrupt()) {
155 xor_arm4regs_2(bytes, p1, p2);
156 } else {
157 kernel_neon_begin();
158 xor_block_neon_inner.do_2(bytes, p1, p2);
159 kernel_neon_end();
160 }
161}
162
163static void
164xor_neon_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
165 unsigned long *p3)
166{
167 if (in_interrupt()) {
168 xor_arm4regs_3(bytes, p1, p2, p3);
169 } else {
170 kernel_neon_begin();
171 xor_block_neon_inner.do_3(bytes, p1, p2, p3);
172 kernel_neon_end();
173 }
174}
175
176static void
177xor_neon_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
178 unsigned long *p3, unsigned long *p4)
179{
180 if (in_interrupt()) {
181 xor_arm4regs_4(bytes, p1, p2, p3, p4);
182 } else {
183 kernel_neon_begin();
184 xor_block_neon_inner.do_4(bytes, p1, p2, p3, p4);
185 kernel_neon_end();
186 }
187}
188
189static void
190xor_neon_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
191 unsigned long *p3, unsigned long *p4, unsigned long *p5)
192{
193 if (in_interrupt()) {
194 xor_arm4regs_5(bytes, p1, p2, p3, p4, p5);
195 } else {
196 kernel_neon_begin();
197 xor_block_neon_inner.do_5(bytes, p1, p2, p3, p4, p5);
198 kernel_neon_end();
199 }
200}
201
202static struct xor_block_template xor_block_neon = {
203 .name = "neon",
204 .do_2 = xor_neon_2,
205 .do_3 = xor_neon_3,
206 .do_4 = xor_neon_4,
207 .do_5 = xor_neon_5
208};
209
210#define NEON_TEMPLATES \
211 do { if (cpu_has_neon()) xor_speed(&xor_block_neon); } while (0)
212#else
213#define NEON_TEMPLATES
214#endif
diff --git a/arch/arm/include/debug/8250.S b/arch/arm/include/debug/8250.S
new file mode 100644
index 000000000000..7a2baf913aa0
--- /dev/null
+++ b/arch/arm/include/debug/8250.S
@@ -0,0 +1,54 @@
1/*
2 * arch/arm/include/debug/8250.S
3 *
4 * Copyright (C) 1994-2013 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/serial_reg.h>
11
12 .macro addruart, rp, rv, tmp
13 ldr \rp, =CONFIG_DEBUG_UART_PHYS
14 ldr \rv, =CONFIG_DEBUG_UART_VIRT
15 .endm
16
17#ifdef CONFIG_DEBUG_UART_8250_WORD
18 .macro store, rd, rx:vararg
19 str \rd, \rx
20 .endm
21
22 .macro load, rd, rx:vararg
23 ldr \rd, \rx
24 .endm
25#else
26 .macro store, rd, rx:vararg
27 strb \rd, \rx
28 .endm
29
30 .macro load, rd, rx:vararg
31 ldrb \rd, \rx
32 .endm
33#endif
34
35#define UART_SHIFT CONFIG_DEBUG_UART_8250_SHIFT
36
37 .macro senduart,rd,rx
38 store \rd, [\rx, #UART_TX << UART_SHIFT]
39 .endm
40
41 .macro busyuart,rd,rx
421002: load \rd, [\rx, #UART_LSR << UART_SHIFT]
43 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
44 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
45 bne 1002b
46 .endm
47
48 .macro waituart,rd,rx
49#ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL
501001: load \rd, [\rx, #UART_MSR << UART_SHIFT]
51 tst \rd, #UART_MSR_CTS
52 beq 1001b
53#endif
54 .endm
diff --git a/arch/arm/include/debug/8250_32.S b/arch/arm/include/debug/8250_32.S
deleted file mode 100644
index 8db01eeabbb4..000000000000
--- a/arch/arm/include/debug/8250_32.S
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit
9 * accesses to the 8250.
10 */
11
12#include <linux/serial_reg.h>
13
14 .macro senduart,rd,rx
15 str \rd, [\rx, #UART_TX << UART_SHIFT]
16 .endm
17
18 .macro busyuart,rd,rx
191002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT]
20 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
21 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
22 bne 1002b
23 .endm
24
25 /* The UART's don't have any flow control IO's wired up. */
26 .macro waituart,rd,rx
27 .endm
diff --git a/arch/arm/include/debug/bcm2835.S b/arch/arm/include/debug/bcm2835.S
deleted file mode 100644
index aed9199bd847..000000000000
--- a/arch/arm/include/debug/bcm2835.S
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Debugging macro include header
3 *
4 * Copyright (C) 2010 Broadcom
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#define BCM2835_DEBUG_PHYS 0x20201000
15#define BCM2835_DEBUG_VIRT 0xf0201000
16
17 .macro addruart, rp, rv, tmp
18 ldr \rp, =BCM2835_DEBUG_PHYS
19 ldr \rv, =BCM2835_DEBUG_VIRT
20 .endm
21
22#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/include/debug/cns3xxx.S b/arch/arm/include/debug/cns3xxx.S
deleted file mode 100644
index d04c150baa1c..000000000000
--- a/arch/arm/include/debug/cns3xxx.S
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Debugging macro include header
3 *
4 * Copyright 1994-1999 Russell King
5 * Copyright 2008 Cavium Networks
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This file is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License, Version 2, as
10 * published by the Free Software Foundation.
11 */
12
13 .macro addruart,rp,rv,tmp
14 mov \rp, #0x00009000
15 orr \rv, \rp, #0xf0000000 @ virtual base
16 orr \rp, \rp, #0x10000000
17 .endm
18
19#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/include/debug/highbank.S b/arch/arm/include/debug/highbank.S
deleted file mode 100644
index 8cad4322a5a2..000000000000
--- a/arch/arm/include/debug/highbank.S
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * Debugging macro include header
3 *
4 * Copyright (C) 1994-1999 Russell King
5 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 .macro addruart,rp,rv,tmp
13 ldr \rv, =0xfee36000
14 ldr \rp, =0xfff36000
15 .endm
16
17#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/include/debug/keystone.S b/arch/arm/include/debug/keystone.S
deleted file mode 100644
index 9aef9ba3f4f0..000000000000
--- a/arch/arm/include/debug/keystone.S
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * Early serial debug output macro for Keystone SOCs
3 *
4 * Copyright 2013 Texas Instruments, Inc.
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 *
7 * Based on RMKs low level debug code.
8 * Copyright (C) 1994-1999 Russell King
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/serial_reg.h>
16
17#define UART_SHIFT 2
18#if defined(CONFIG_DEBUG_KEYSTONE_UART0)
19#define UART_PHYS 0x02530c00
20#define UART_VIRT 0xfeb30c00
21#elif defined(CONFIG_DEBUG_KEYSTONE_UART1)
22#define UART_PHYS 0x02531000
23#define UART_VIRT 0xfeb31000
24#endif
25
26 .macro addruart, rp, rv, tmp
27 ldr \rv, =UART_VIRT @ physical base address
28 ldr \rp, =UART_PHYS @ virtual base address
29 .endm
30
31 .macro senduart,rd,rx
32 str \rd, [\rx, #UART_TX << UART_SHIFT]
33 .endm
34
35 .macro busyuart,rd,rx
361002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT]
37 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
38 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
39 bne 1002b
40 .endm
41
42 .macro waituart,rd,rx
43 .endm
diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S
deleted file mode 100644
index 6517311a1c91..000000000000
--- a/arch/arm/include/debug/mvebu.S
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Early serial output macro for Marvell SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory Clement <gregory.clement@free-electrons.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifdef CONFIG_DEBUG_MVEBU_UART_ALTERNATE
15#define ARMADA_370_XP_REGS_PHYS_BASE 0xf1000000
16#else
17#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
18#endif
19
20#define ARMADA_370_XP_REGS_VIRT_BASE 0xfec00000
21
22 .macro addruart, rp, rv, tmp
23 ldr \rp, =ARMADA_370_XP_REGS_PHYS_BASE
24 ldr \rv, =ARMADA_370_XP_REGS_VIRT_BASE
25 orr \rp, \rp, #0x00012000
26 orr \rv, \rv, #0x00012000
27 .endm
28
29#define UART_SHIFT 2
30#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/include/debug/mxs.S b/arch/arm/include/debug/mxs.S
deleted file mode 100644
index d86951551ca1..000000000000
--- a/arch/arm/include/debug/mxs.S
+++ /dev/null
@@ -1,27 +0,0 @@
1/* arch/arm/mach-mxs/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#ifdef CONFIG_DEBUG_IMX23_UART
15#define UART_PADDR 0x80070000
16#elif defined (CONFIG_DEBUG_IMX28_UART)
17#define UART_PADDR 0x80074000
18#endif
19
20#define UART_VADDR 0xfe100000
21
22 .macro addruart, rp, rv, tmp
23 ldr \rp, =UART_PADDR @ physical
24 ldr \rv, =UART_VADDR @ virtual
25 .endm
26
27#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/include/debug/nomadik.S b/arch/arm/include/debug/nomadik.S
deleted file mode 100644
index 735417922ce2..000000000000
--- a/arch/arm/include/debug/nomadik.S
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * Debugging macro include header
3 *
4 * Copyright (C) 1994-1999 Russell King
5 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11*/
12
13 .macro addruart, rp, rv, tmp
14 mov \rp, #0x00100000
15 add \rp, \rp, #0x000fb000
16 add \rv, \rp, #0xf0000000 @ virtual base
17 add \rp, \rp, #0x10000000 @ physical base address
18 .endm
19
20#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/include/debug/nspire.S b/arch/arm/include/debug/nspire.S
deleted file mode 100644
index 886fd276fcbc..000000000000
--- a/arch/arm/include/debug/nspire.S
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * linux/arch/arm/include/debug/nspire.S
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#define NSPIRE_EARLY_UART_PHYS_BASE 0x90020000
13#define NSPIRE_EARLY_UART_VIRT_BASE 0xfee20000
14
15.macro addruart, rp, rv, tmp
16 ldr \rp, =(NSPIRE_EARLY_UART_PHYS_BASE) @ physical base address
17 ldr \rv, =(NSPIRE_EARLY_UART_VIRT_BASE) @ virtual base address
18.endm
19
20
21#ifdef CONFIG_DEBUG_NSPIRE_CX_UART
22#include <asm/hardware/debug-pl01x.S>
23#endif
24
25#ifdef CONFIG_DEBUG_NSPIRE_CLASSIC_UART
26#define UART_SHIFT 2
27#include <asm/hardware/debug-8250.S>
28#endif
diff --git a/arch/arm/include/debug/picoxcell.S b/arch/arm/include/debug/picoxcell.S
deleted file mode 100644
index bc1f07c49cd4..000000000000
--- a/arch/arm/include/debug/picoxcell.S
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#define UART_SHIFT 2
11#define PICOXCELL_UART1_BASE 0x80230000
12#define PHYS_TO_IO(x) (((x) & 0x00ffffff) | 0xfe000000)
13
14 .macro addruart, rp, rv, tmp
15 ldr \rv, =PHYS_TO_IO(PICOXCELL_UART1_BASE)
16 ldr \rp, =PICOXCELL_UART1_BASE
17 .endm
18
19#include "8250_32.S"
diff --git a/arch/arm/include/asm/hardware/debug-pl01x.S b/arch/arm/include/debug/pl01x.S
index f9fd083eff63..37c6895b87e6 100644
--- a/arch/arm/include/asm/hardware/debug-pl01x.S
+++ b/arch/arm/include/debug/pl01x.S
@@ -1,4 +1,4 @@
1/* arch/arm/include/asm/hardware/debug-pl01x.S 1/* arch/arm/include/debug/pl01x.S
2 * 2 *
3 * Debugging macro include header 3 * Debugging macro include header
4 * 4 *
@@ -12,6 +12,13 @@
12*/ 12*/
13#include <linux/amba/serial.h> 13#include <linux/amba/serial.h>
14 14
15#ifdef CONFIG_DEBUG_UART_PHYS
16 .macro addruart, rp, rv, tmp
17 ldr \rp, =CONFIG_DEBUG_UART_PHYS
18 ldr \rv, =CONFIG_DEBUG_UART_VIRT
19 .endm
20#endif
21
15 .macro senduart,rd,rx 22 .macro senduart,rd,rx
16 strb \rd, [\rx, #UART01x_DR] 23 strb \rd, [\rx, #UART01x_DR]
17 .endm 24 .endm
diff --git a/arch/arm/include/debug/pxa.S b/arch/arm/include/debug/pxa.S
deleted file mode 100644
index e1e795aa3d7f..000000000000
--- a/arch/arm/include/debug/pxa.S
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * Early serial output macro for Marvell PXA/MMP SoC
3 *
4 * Copyright (C) 1994-1999 Russell King
5 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
6 *
7 * Copyright (C) 2013 Haojian Zhuang
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#if defined(CONFIG_DEBUG_PXA_UART1)
15#define PXA_UART_REG_PHYS_BASE 0x40100000
16#define PXA_UART_REG_VIRT_BASE 0xf2100000
17#elif defined(CONFIG_DEBUG_MMP_UART2)
18#define PXA_UART_REG_PHYS_BASE 0xd4017000
19#define PXA_UART_REG_VIRT_BASE 0xfe017000
20#elif defined(CONFIG_DEBUG_MMP_UART3)
21#define PXA_UART_REG_PHYS_BASE 0xd4018000
22#define PXA_UART_REG_VIRT_BASE 0xfe018000
23#else
24#error "Select uart for DEBUG_LL"
25#endif
26
27 .macro addruart, rp, rv, tmp
28 ldr \rp, =PXA_UART_REG_PHYS_BASE
29 ldr \rv, =PXA_UART_REG_VIRT_BASE
30 .endm
31
32#define UART_SHIFT 2
33#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/include/debug/rockchip.S b/arch/arm/include/debug/rockchip.S
deleted file mode 100644
index cfd883e69588..000000000000
--- a/arch/arm/include/debug/rockchip.S
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * Early serial output macro for Rockchip SoCs
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#if defined(CONFIG_DEBUG_RK29_UART0)
14#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20060000
15#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed60000
16#elif defined(CONFIG_DEBUG_RK29_UART1)
17#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000
18#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000
19#elif defined(CONFIG_DEBUG_RK29_UART2)
20#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000
21#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000
22#elif defined(CONFIG_DEBUG_RK3X_UART0)
23#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10124000
24#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb24000
25#elif defined(CONFIG_DEBUG_RK3X_UART1)
26#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10126000
27#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb26000
28#elif defined(CONFIG_DEBUG_RK3X_UART2)
29#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000
30#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000
31#elif defined(CONFIG_DEBUG_RK3X_UART3)
32#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000
33#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000
34#endif
35
36 .macro addruart, rp, rv, tmp
37 ldr \rp, =ROCKCHIP_UART_DEBUG_PHYS_BASE
38 ldr \rv, =ROCKCHIP_UART_DEBUG_VIRT_BASE
39 .endm
40
41#define UART_SHIFT 2
42#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/include/debug/socfpga.S b/arch/arm/include/debug/socfpga.S
deleted file mode 100644
index 966b2f994946..000000000000
--- a/arch/arm/include/debug/socfpga.S
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * Copyright (C) 1994-1999 Russell King
3 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#define UART_SHIFT 2
11#define DEBUG_LL_UART_OFFSET 0x00002000
12
13 .macro addruart, rp, rv, tmp
14 mov \rp, #DEBUG_LL_UART_OFFSET
15 orr \rp, \rp, #0x00c00000
16 orr \rv, \rp, #0xfe000000 @ virtual base
17 orr \rp, \rp, #0xff000000 @ physical base
18 .endm
19
20#include "8250_32.S"
21
diff --git a/arch/arm/include/debug/sunxi.S b/arch/arm/include/debug/sunxi.S
deleted file mode 100644
index 04eb56d5db2c..000000000000
--- a/arch/arm/include/debug/sunxi.S
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * Early serial output macro for Allwinner A1X SoCs
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#if defined(CONFIG_DEBUG_SUNXI_UART0)
14#define SUNXI_UART_DEBUG_PHYS_BASE 0x01c28000
15#define SUNXI_UART_DEBUG_VIRT_BASE 0xf1c28000
16#elif defined(CONFIG_DEBUG_SUNXI_UART1)
17#define SUNXI_UART_DEBUG_PHYS_BASE 0x01c28400
18#define SUNXI_UART_DEBUG_VIRT_BASE 0xf1c28400
19#endif
20
21 .macro addruart, rp, rv, tmp
22 ldr \rp, =SUNXI_UART_DEBUG_PHYS_BASE
23 ldr \rv, =SUNXI_UART_DEBUG_VIRT_BASE
24 .endm
25
26#define UART_SHIFT 2
27#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S
index 883d7c22fd9d..be6a720dd183 100644
--- a/arch/arm/include/debug/tegra.S
+++ b/arch/arm/include/debug/tegra.S
@@ -221,3 +221,32 @@
2211002: 2211002:
222#endif 222#endif
223 .endm 223 .endm
224
225/*
226 * Storage for the state maintained by the macros above.
227 *
228 * In the kernel proper, this data is located in arch/arm/mach-tegra/common.c.
229 * That's because this header is included from multiple files, and we only
230 * want a single copy of the data. In particular, the UART probing code above
231 * assumes it's running using physical addresses. This is true when this file
232 * is included from head.o, but not when included from debug.o. So we need
233 * to share the probe results between the two copies, rather than having
234 * to re-run the probing again later.
235 *
236 * In the decompressor, we put the symbol/storage right here, since common.c
237 * isn't included in the decompressor build. This symbol gets put in .text
238 * even though it's really data, since .data is discarded from the
239 * decompressor. Luckily, .text is writeable in the decompressor, unless
240 * CONFIG_ZBOOT_ROM. That dependency is handled in arch/arm/Kconfig.debug.
241 */
242#if defined(ZIMAGE)
243tegra_uart_config:
244 /* Debug UART initialization required */
245 .word 1
246 /* Debug UART physical address */
247 .word 0
248 /* Debug UART virtual address */
249 .word 0
250 /* Scratch space for debug macro */
251 .word 0
252#endif
diff --git a/arch/arm/include/debug/u300.S b/arch/arm/include/debug/u300.S
deleted file mode 100644
index 6f04f08a203c..000000000000
--- a/arch/arm/include/debug/u300.S
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * Copyright (C) 2006-2013 ST-Ericsson AB
3 * License terms: GNU General Public License (GPL) version 2
4 * Debugging macro include header.
5 * Author: Linus Walleij <linus.walleij@stericsson.com>
6 */
7#define U300_SLOW_PER_PHYS_BASE 0xc0010000
8#define U300_SLOW_PER_VIRT_BASE 0xff000000
9
10 .macro addruart, rp, rv, tmp
11 /* If we move the address using MMU, use this. */
12 ldr \rp, = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address
13 ldr \rv, = U300_SLOW_PER_VIRT_BASE @ MMU on, virtual address
14 orr \rp, \rp, #0x00003000
15 orr \rv, \rv, #0x00003000
16 .endm
17
18#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/include/debug/ux500.S b/arch/arm/include/debug/ux500.S
index fbd24beeb1fa..aa7f63a8b5e0 100644
--- a/arch/arm/include/debug/ux500.S
+++ b/arch/arm/include/debug/ux500.S
@@ -45,4 +45,4 @@
45 ldr \rv, =UART_VIRT_BASE @ yes, virtual address 45 ldr \rv, =UART_VIRT_BASE @ yes, virtual address
46 .endm 46 .endm
47 47
48#include <asm/hardware/debug-pl01x.S> 48#include <debug/pl01x.S>
diff --git a/arch/arm/include/debug/vexpress.S b/arch/arm/include/debug/vexpress.S
index acafb229e2b6..524acd5a223e 100644
--- a/arch/arm/include/debug/vexpress.S
+++ b/arch/arm/include/debug/vexpress.S
@@ -47,51 +47,5 @@
47 47
48 .endm 48 .endm
49 49
50#include <asm/hardware/debug-pl01x.S> 50#include <debug/pl01x.S>
51
52#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9)
53
54 .macro addruart,rp,rv,tmp
55 mov \rp, #DEBUG_LL_UART_OFFSET
56 orr \rv, \rp, #DEBUG_LL_VIRT_BASE
57 orr \rp, \rp, #DEBUG_LL_PHYS_BASE
58 .endm
59
60#include <asm/hardware/debug-pl01x.S>
61
62#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1)
63
64 .macro addruart,rp,rv,tmp
65 mov \rp, #DEBUG_LL_UART_OFFSET_RS1
66 orr \rv, \rp, #DEBUG_LL_VIRT_BASE
67 orr \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
68 .endm
69
70#include <asm/hardware/debug-pl01x.S>
71
72#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CRX)
73
74 .macro addruart,rp,tmp,tmp2
75 ldr \rp, =DEBUG_LL_UART_PHYS_CRX
76 .endm
77
78#include <asm/hardware/debug-pl01x.S>
79
80#else /* CONFIG_DEBUG_LL_UART_NONE */
81
82 .macro addruart, rp, rv, tmp
83 /* Safe dummy values */
84 mov \rp, #0
85 mov \rv, #DEBUG_LL_VIRT_BASE
86 .endm
87
88 .macro senduart,rd,rx
89 .endm
90
91 .macro waituart,rd,rx
92 .endm
93
94 .macro busyuart,rd,rx
95 .endm
96
97#endif 51#endif
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