26 files changed, 265 insertions, 101 deletions

diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index c38b58c80202..3278afe2c3ab 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -34,3 +34,4 @@ generic-y += timex.h
 generic-y += trace_clock.h
 generic-y += unaligned.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
index 60f15e274e6d..2f59f7443396 100644
--- a/arch/arm/include/asm/barrier.h
+++ b/arch/arm/include/asm/barrier.h
@@ -59,6 +59,21 @@
 #define smp_wmb()       dmb(ishst)
 #endif
 
+#define smp_store_release(p, v)                                         \
+do {                                                                    \
+        compiletime_assert_atomic_type(*p);                             \
+        smp_mb();                                                       \
+        ACCESS_ONCE(*p) = (v);                                          \
+} while (0)
+
+#define smp_load_acquire(p)                                             \
+({                                                                      \
+        typeof(*p) ___p1 = ACCESS_ONCE(*p);                             \
+        compiletime_assert_atomic_type(*p);                             \
+        smp_mb();                                                       \
+        ___p1;                                                          \
+})
+
 #define read_barrier_depends()          do { } while(0)
 #define smp_read_barrier_depends()      do { } while(0)
 
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index e691ec91e4d3..b2e298a90d76 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -254,25 +254,59 @@ static inline int constant_fls(int x)
 }
 
 /*
- * On ARMv5 and above those functions can be implemented around
- * the clz instruction for much better code efficiency.
+ * On ARMv5 and above those functions can be implemented around the
+ * clz instruction for much better code efficiency.  __clz returns
+ * the number of leading zeros, zero input will return 32, and
+ * 0x80000000 will return 0.
  */
+static inline unsigned int __clz(unsigned int x)
+{
+        unsigned int ret;
+
+        asm("clz\t%0, %1" : "=r" (ret) : "r" (x));
 
+        return ret;
+}
+
+/*
+ * fls() returns zero if the input is zero, otherwise returns the bit
+ * position of the last set bit, where the LSB is 1 and MSB is 32.
+ */
 static inline int fls(int x)
 {
-        int ret;
-
         if (__builtin_constant_p(x))
                return constant_fls(x);
 
-        asm("clz\t%0, %1" : "=r" (ret) : "r" (x));
-        ret = 32 - ret;
-        return ret;
+        return 32 - __clz(x);
+}
+
+/*
+ * __fls() returns the bit position of the last bit set, where the
+ * LSB is 0 and MSB is 31.  Zero input is undefined.
+ */
+static inline unsigned long __fls(unsigned long x)
+{
+        return fls(x) - 1;
+}
+
+/*
+ * ffs() returns zero if the input was zero, otherwise returns the bit
+ * position of the first set bit, where the LSB is 1 and MSB is 32.
+ */
+static inline int ffs(int x)
+{
+        return fls(x & -x);
+}
+
+/*
+ * __ffs() returns the bit position of the first bit set, where the
+ * LSB is 0 and MSB is 31.  Zero input is undefined.
+ */
+static inline unsigned long __ffs(unsigned long x)
+{
+        return ffs(x) - 1;
 }
 
-#define __fls(x) (fls(x) - 1)
-#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
-#define __ffs(x) (ffs(x) - 1)
 #define ffz(x) __ffs( ~(x) )
 
 #endif
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index ee753f1749cd..8b8b61685a34 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -212,6 +212,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
 static inline void __flush_icache_all(void)
 {
         __flush_icache_preferred();
+        dsb();
 }
 
 /*
@@ -481,4 +482,9 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size)
         : : : "r0","r1","r2","r3","r4","r5","r6","r7", \
               "r9","r10","lr","memory" )
 
+int set_memory_ro(unsigned long addr, int numpages);
+int set_memory_rw(unsigned long addr, int numpages);
+int set_memory_x(unsigned long addr, int numpages);
+int set_memory_nx(unsigned long addr, int numpages);
+
 #endif
diff --git a/arch/arm/include/asm/checksum.h b/arch/arm/include/asm/checksum.h
index 6dcc16430868..523315115478 100644
--- a/arch/arm/include/asm/checksum.h
+++ b/arch/arm/include/asm/checksum.h
@@ -87,19 +87,33 @@ static inline __wsum
 csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
                    unsigned short proto, __wsum sum)
 {
-        __asm__(
-        "adds   %0, %1, %2              @ csum_tcpudp_nofold    \n\
-        adcs    %0, %0, %3                                      \n"
+        u32 lenprot = len | proto << 16;
+        if (__builtin_constant_p(sum) && sum == 0) {
+                __asm__(
+                "adds   %0, %1, %2      @ csum_tcpudp_nofold0   \n\t"
 #ifdef __ARMEB__
-        "adcs   %0, %0, %4                                      \n"
+                "adcs   %0, %0, %3                              \n\t"
 #else
-        "adcs   %0, %0, %4, lsl #8                              \n"
+                "adcs   %0, %0, %3, ror #8                      \n\t"
 #endif
-        "adcs   %0, %0, %5                                      \n\
-        adc     %0, %0, #0"
-        : "=&r"(sum)
-        : "r" (sum), "r" (daddr), "r" (saddr), "r" (len), "Ir" (htons(proto))
-        : "cc");
+                "adc    %0, %0, #0"
+                : "=&r" (sum)
+                : "r" (daddr), "r" (saddr), "r" (lenprot)
+                : "cc");
+        } else {
+                __asm__(
+                "adds   %0, %1, %2      @ csum_tcpudp_nofold    \n\t"
+                "adcs   %0, %0, %3                              \n\t"
+#ifdef __ARMEB__
+                "adcs   %0, %0, %4                              \n\t"
+#else
+                "adcs   %0, %0, %4, ror #8                      \n\t"
+#endif
+                "adc    %0, %0, #0"
+                : "=&r"(sum)
+                : "r" (sum), "r" (daddr), "r" (saddr), "r" (lenprot)
+                : "cc");
+        }
         return sum;
 }       
 /*
diff --git a/arch/arm/include/asm/clkdev.h b/arch/arm/include/asm/clkdev.h
index 80751c15c300..4e8a4b27d7c7 100644
--- a/arch/arm/include/asm/clkdev.h
+++ b/arch/arm/include/asm/clkdev.h
@@ -14,12 +14,14 @@
 
 #include <linux/slab.h>
 
+#ifndef CONFIG_COMMON_CLK
 #ifdef CONFIG_HAVE_MACH_CLKDEV
 #include <mach/clkdev.h>
 #else
 #define __clk_get(clk)  ({ 1; })
 #define __clk_put(clk)  do { } while (0)
 #endif
+#endif
 
 static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
 {
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 58b8c6a0ab1f..99084431d6ae 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -8,8 +8,8 @@
 #define MAX_DMA_ADDRESS 0xffffffffUL
 #else
 #define MAX_DMA_ADDRESS ({ \
-        extern unsigned long arm_dma_zone_size; \
-        arm_dma_zone_size ? \
+        extern phys_addr_t arm_dma_zone_size; \
+        arm_dma_zone_size && arm_dma_zone_size < (0x10000000 - PAGE_OFFSET) ? \
                 (PAGE_OFFSET + arm_dma_zone_size) : 0xffffffffUL; })
 #endif
 
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 3b2c40b5bfa2..6795ff743b3d 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -131,6 +131,7 @@ struct l2x0_regs {
         unsigned long prefetch_ctrl;
         unsigned long pwr_ctrl;
         unsigned long ctrl;
+        unsigned long aux2_ctrl;
 };
 
 extern struct l2x0_regs l2x0_saved_regs;
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index fbeb39c869e9..8aa4cca74501 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -38,6 +38,12 @@
 #define isa_bus_to_virt phys_to_virt
 
 /*
+ * Atomic MMIO-wide IO modify
+ */
+extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set);
+extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set);
+
+/*
  * Generic IO read/write.  These perform native-endian accesses.  Note
  * that some architectures will want to re-define __raw_{read,write}w.
  */
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 8a6f6db14ee4..098f7dd6d564 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -225,4 +225,7 @@ static inline int kvm_arch_dev_ioctl_check_extension(long ext)
 int kvm_perf_init(void);
 int kvm_perf_teardown(void);
 
+u64 kvm_arm_timer_get_reg(struct kvm_vcpu *, u64 regid);
+int kvm_arm_timer_set_reg(struct kvm_vcpu *, u64 regid, u64 value);
+
 #endif /* __ARM_KVM_HOST_H__ */
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
index 77de4a41cc50..2d122adcdb22 100644
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -140,6 +140,7 @@ static inline void coherent_icache_guest_page(struct kvm *kvm, hva_t hva,
 }
 
 #define kvm_flush_dcache_to_poc(a,l)    __cpuc_flush_dcache_area((a), (l))
+#define kvm_virt_to_phys(x)             virt_to_idmap((unsigned long)(x))
 
 #endif  /* !__ASSEMBLY__ */
 
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index 2fe141fcc8d6..f98c7f32c9c8 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -22,18 +22,21 @@ struct map_desc {
 };
 
 /* types 0-3 are defined in asm/io.h */
-#define MT_UNCACHED             4
-#define MT_CACHECLEAN           5
-#define MT_MINICLEAN            6
-#define MT_LOW_VECTORS          7
-#define MT_HIGH_VECTORS         8
-#define MT_MEMORY               9
-#define MT_ROM                  10
-#define MT_MEMORY_NONCACHED     11
-#define MT_MEMORY_DTCM          12
-#define MT_MEMORY_ITCM          13
-#define MT_MEMORY_SO            14
-#define MT_MEMORY_DMA_READY     15
+enum {
+        MT_UNCACHED = 4,
+        MT_CACHECLEAN,
+        MT_MINICLEAN,
+        MT_LOW_VECTORS,
+        MT_HIGH_VECTORS,
+        MT_MEMORY_RWX,
+        MT_MEMORY_RW,
+        MT_ROM,
+        MT_MEMORY_RWX_NONCACHED,
+        MT_MEMORY_RW_DTCM,
+        MT_MEMORY_RWX_ITCM,
+        MT_MEMORY_RW_SO,
+        MT_MEMORY_DMA_READY,
+};
 
 #ifdef CONFIG_MMU
 extern void iotable_init(struct map_desc *, int);
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 8756e4bcdba0..4afb376d9c7c 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -30,14 +30,15 @@
  */
 #define UL(x) _AC(x, UL)
 
+/* PAGE_OFFSET - the virtual address of the start of the kernel image */
+#define PAGE_OFFSET             UL(CONFIG_PAGE_OFFSET)
+
 #ifdef CONFIG_MMU
 
 /*
- * PAGE_OFFSET - the virtual address of the start of the kernel image
  * TASK_SIZE - the maximum size of a user space task.
  * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
  */
-#define PAGE_OFFSET             UL(CONFIG_PAGE_OFFSET)
 #define TASK_SIZE               (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M))
 #define TASK_UNMAPPED_BASE      ALIGN(TASK_SIZE / 3, SZ_16M)
 
@@ -104,10 +105,6 @@
 #define END_MEM                 (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE)
 #endif
 
-#ifndef PAGE_OFFSET
-#define PAGE_OFFSET             PLAT_PHYS_OFFSET
-#endif
-
 /*
  * The module can be at any place in ram in nommu mode.
  */
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index a98a2e112fae..680a83e94467 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -57,12 +57,9 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                                enum pci_mmap_state mmap_state, int write_combine);
 
-/*
- * Dummy implementation; always return 0.
- */
 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 {
-        return 0;
+        return channel ? 15 : 14;
 }
 
 #endif /* __KERNEL__ */
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index 86a659a19526..dfff709fda3c 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -160,6 +160,7 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
         return (pmd_t *)pud;
 }
 
+#define pmd_large(pmd)          (pmd_val(pmd) & 2)
 #define pmd_bad(pmd)            (pmd_val(pmd) & 2)
 
 #define copy_pmd(pmdpd,pmdps)           \
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 4f9503908dca..85c60adc8b60 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -120,13 +120,16 @@
 /*
  * 2nd stage PTE definitions for LPAE.
  */
-#define L_PTE_S2_MT_UNCACHED     (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
-#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
-#define L_PTE_S2_MT_WRITEBACK    (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
-#define L_PTE_S2_RDONLY          (_AT(pteval_t, 1) << 6)   /* HAP[1]   */
-#define L_PTE_S2_RDWR            (_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
+#define L_PTE_S2_MT_UNCACHED            (_AT(pteval_t, 0x0) << 2) /* strongly ordered */
+#define L_PTE_S2_MT_WRITETHROUGH        (_AT(pteval_t, 0xa) << 2) /* normal inner write-through */
+#define L_PTE_S2_MT_WRITEBACK           (_AT(pteval_t, 0xf) << 2) /* normal inner write-back */
+#define L_PTE_S2_MT_DEV_SHARED          (_AT(pteval_t, 0x1) << 2) /* device */
+#define L_PTE_S2_MT_MASK                (_AT(pteval_t, 0xf) << 2)
 
-#define L_PMD_S2_RDWR            (_AT(pmdval_t, 3) << 6)   /* HAP[2:1] */
+#define L_PTE_S2_RDONLY                 (_AT(pteval_t, 1) << 6)   /* HAP[1]   */
+#define L_PTE_S2_RDWR                   (_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
+
+#define L_PMD_S2_RDWR                   (_AT(pmdval_t, 3) << 6)   /* HAP[2:1] */
 
 /*
  * Hyp-mode PL2 PTE definitions for LPAE.
@@ -142,6 +145,7 @@
                                                  PMD_TYPE_TABLE)
 #define pmd_sect(pmd)           ((pmd_val(pmd) & PMD_TYPE_MASK) == \
                                                  PMD_TYPE_SECT)
+#define pmd_large(pmd)          pmd_sect(pmd)
 
 #define pud_clear(pudp)                 \
         do {                            \
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 1571d126e9dd..7d59b524f2af 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -254,6 +254,8 @@ PTE_BIT_FUNC(mkclean,   &= ~L_PTE_DIRTY);
 PTE_BIT_FUNC(mkdirty,   |= L_PTE_DIRTY);
 PTE_BIT_FUNC(mkold,     &= ~L_PTE_YOUNG);
 PTE_BIT_FUNC(mkyoung,   |= L_PTE_YOUNG);
+PTE_BIT_FUNC(mkexec,   &= ~L_PTE_XN);
+PTE_BIT_FUNC(mknexec,   |= L_PTE_XN);
 
 static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
 
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index ef3c6072aa45..ac4bfae26702 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -37,18 +37,9 @@
 
 static inline void dsb_sev(void)
 {
-#if __LINUX_ARM_ARCH__ >= 7
-        __asm__ __volatile__ (
-                "dsb ishst\n"
-                SEV
-        );
-#else
-        __asm__ __volatile__ (
-                "mcr p15, 0, %0, c7, c10, 4\n"
-                SEV
-                : : "r" (0)
-        );
-#endif
+
+        dsb(ishst);
+        __asm__(SEV);
 }
 
 /*
diff --git a/arch/arm/include/asm/trusted_foundations.h b/arch/arm/include/asm/trusted_foundations.h
new file mode 100644
index 000000000000..3bd36e2c5f2e
--- /dev/null
+++ b/arch/arm/include/asm/trusted_foundations.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2013, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+/*
+ * Support for the Trusted Foundations secure monitor.
+ *
+ * Trusted Foundation comes active on some ARM consumer devices (most
+ * Tegra-based devices sold on the market are concerned). Such devices can only
+ * perform some basic operations, like setting the CPU reset vector, through
+ * SMC calls to the secure monitor. The calls are completely specific to
+ * Trusted Foundations, and do *not* follow the SMC calling convention or the
+ * PSCI standard.
+ */
+
+#ifndef __ASM_ARM_TRUSTED_FOUNDATIONS_H
+#define __ASM_ARM_TRUSTED_FOUNDATIONS_H
+
+#include <linux/kconfig.h>
+#include <linux/printk.h>
+#include <linux/bug.h>
+#include <linux/of.h>
+
+struct trusted_foundations_platform_data {
+        unsigned int version_major;
+        unsigned int version_minor;
+};
+
+#if IS_ENABLED(CONFIG_TRUSTED_FOUNDATIONS)
+
+void register_trusted_foundations(struct trusted_foundations_platform_data *pd);
+void of_register_trusted_foundations(void);
+
+#else /* CONFIG_TRUSTED_FOUNDATIONS */
+
+static inline void register_trusted_foundations(
+                                   struct trusted_foundations_platform_data *pd)
+{
+        /*
+         * If we try to register TF, this means the system needs it to continue.
+         * Its absence if thus a fatal error.
+         */
+        panic("No support for Trusted Foundations, stopping...\n");
+}
+
+static inline void of_register_trusted_foundations(void)
+{
+        /*
+         * If we find the target should enable TF but does not support it,
+         * fail as the system won't be able to do much anyway
+         */
+        if (of_find_compatible_node(NULL, NULL, "tl,trusted-foundations"))
+                register_trusted_foundations(NULL);
+}
+#endif /* CONFIG_TRUSTED_FOUNDATIONS */
+
+#endif
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 141baa3f9a72..acabef1a75df 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -15,7 +15,7 @@
 
 #include <uapi/asm/unistd.h>
 
-#define __NR_syscalls  (380)
+#define __NR_syscalls  (384)
 #define __ARM_NR_cmpxchg                (__ARM_NR_BASE+0x00fff0)
 
 #define __ARCH_WANT_STAT64
diff --git a/arch/arm/include/asm/word-at-a-time.h b/arch/arm/include/asm/word-at-a-time.h
index 4d52f92967a6..a6d0a29861e7 100644
--- a/arch/arm/include/asm/word-at-a-time.h
+++ b/arch/arm/include/asm/word-at-a-time.h
@@ -48,10 +48,14 @@ static inline unsigned long find_zero(unsigned long mask)
         return ret;
 }
 
-#ifdef CONFIG_DCACHE_WORD_ACCESS
-
 #define zero_bytemask(mask) (mask)
 
+#else   /* __ARMEB__ */
+#include <asm-generic/word-at-a-time.h>
+#endif
+
+#ifdef CONFIG_DCACHE_WORD_ACCESS
+
 /*
  * Load an unaligned word from kernel space.
  *
@@ -73,7 +77,11 @@ static inline unsigned long load_unaligned_zeropad(const void *addr)
         "       bic     %2, %2, #0x3\n"
         "       ldr     %0, [%2]\n"
         "       lsl     %1, %1, #0x3\n"
+#ifndef __ARMEB__
         "       lsr     %0, %0, %1\n"
+#else
+        "       lsl     %0, %0, %1\n"
+#endif
         "       b       2b\n"
         "       .popsection\n"
         "       .pushsection __ex_table,\"a\"\n"
@@ -86,11 +94,5 @@ static inline unsigned long load_unaligned_zeropad(const void *addr)
         return ret;
 }
 
-
 #endif  /* DCACHE_WORD_ACCESS */
-
-#else   /* __ARMEB__ */
-#include <asm-generic/word-at-a-time.h>
-#endif
-
 #endif /* __ASM_ARM_WORD_AT_A_TIME_H */
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
index 3759cacdd7f8..e0965abacb7d 100644
--- a/arch/arm/include/asm/xen/page.h
+++ b/arch/arm/include/asm/xen/page.h
@@ -117,6 +117,7 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
         return __set_phys_to_machine(pfn, mfn);
 }
 
-#define xen_remap(cookie, size) ioremap_cache((cookie), (size));
+#define xen_remap(cookie, size) ioremap_cache((cookie), (size))
+#define xen_unmap(cookie) iounmap((cookie))
 
 #endif /* _ASM_ARM_XEN_PAGE_H */
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 29da84e183f4..42b823cd2d22 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -43,6 +43,14 @@
 #define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR
 #define IMX35_UART_BASE(n)      IMX35_UART_BASE_ADDR(n)
 
+#define IMX50_UART1_BASE_ADDR   0x53fbc000
+#define IMX50_UART2_BASE_ADDR   0x53fc0000
+#define IMX50_UART3_BASE_ADDR   0x5000c000
+#define IMX50_UART4_BASE_ADDR   0x53ff0000
+#define IMX50_UART5_BASE_ADDR   0x63f90000
+#define IMX50_UART_BASE_ADDR(n) IMX50_UART##n##_BASE_ADDR
+#define IMX50_UART_BASE(n)      IMX50_UART_BASE_ADDR(n)
+
 #define IMX51_UART1_BASE_ADDR   0x73fbc000
 #define IMX51_UART2_BASE_ADDR   0x73fc0000
 #define IMX51_UART3_BASE_ADDR   0x7000c000
@@ -85,6 +93,8 @@
 #define UART_PADDR      IMX_DEBUG_UART_BASE(IMX31)
 #elif defined(CONFIG_DEBUG_IMX35_UART)
 #define UART_PADDR      IMX_DEBUG_UART_BASE(IMX35)
+#elif defined(CONFIG_DEBUG_IMX50_UART)
+#define UART_PADDR      IMX_DEBUG_UART_BASE(IMX50)
 #elif defined(CONFIG_DEBUG_IMX51_UART)
 #define UART_PADDR      IMX_DEBUG_UART_BASE(IMX51)
 #elif defined(CONFIG_DEBUG_IMX53_UART)
diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S
index be6a720dd183..f98763f0bc17 100644
--- a/arch/arm/include/debug/tegra.S
+++ b/arch/arm/include/debug/tegra.S
@@ -46,10 +46,10 @@
 #define TEGRA_APB_MISC_GP_HIDREV        (TEGRA_APB_MISC_BASE + 0x804)
 
 /*
- * Must be 1MB-aligned since a 1MB mapping is used early on.
+ * Must be section-aligned since a section mapping is used early on.
  * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
  */
-#define UART_VIRTUAL_BASE               0xfe100000
+#define UART_VIRTUAL_BASE               0xfe800000
 
 #define checkuart(rp, rv, lhu, bit, uart) \
                 /* Load address of CLK_RST register */ \
@@ -156,28 +156,6 @@
 92:             and     \rv, \rp, #0xffffff     @ offset within 1MB section
                 add     \rv, \rv, #UART_VIRTUAL_BASE
                 str     \rv, [\tmp, #8]         @ Store in tegra_uart_virt
-                movw    \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff
-                movt    \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16
-                ldr     \rv, [\rv, #0]          @ Load HIDREV
-                ubfx    \rv, \rv, #8, #8        @ 15:8 are SoC version
-                cmp     \rv, #0x20              @ Tegra20?
-                moveq   \rv, #0x75              @ Tegra20 divisor
-                movne   \rv, #0xdd              @ Tegra30 divisor
-                str     \rv, [\tmp, #12]        @ Save divisor to scratch
-                /* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */
-                mov     \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB
-                str     \rv, [\rp, #UART_LCR << UART_SHIFT]
-                /* uart[UART_DLL] = div & 0xff; */
-                ldr     \rv, [\tmp, #12]
-                and     \rv, \rv, #0xff
-                str     \rv, [\rp, #UART_DLL << UART_SHIFT]
-                /* uart[UART_DLM] = div >> 8; */
-                ldr     \rv, [\tmp, #12]
-                lsr     \rv, \rv, #8
-                str     \rv, [\rp, #UART_DLM << UART_SHIFT]
-                /* uart[UART_LCR] = UART_LCR_WLEN8; */
-                mov     \rv, #UART_LCR_WLEN8
-                str     \rv, [\rp, #UART_LCR << UART_SHIFT]
                 b       100f
 
                 .align
@@ -205,8 +183,8 @@
                 cmp     \rx, #0
                 beq     1002f
 1001:           ldrb    \rd, [\rx, #UART_LSR << UART_SHIFT]
-                and     \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
-                teq     \rd, #UART_LSR_TEMT | UART_LSR_THRE
+                and     \rd, \rd, #UART_LSR_THRE
+                teq     \rd, #UART_LSR_THRE
                 bne     1001b
 1002:
                 .endm
@@ -225,7 +203,7 @@
 /*
  * Storage for the state maintained by the macros above.
  *
- * In the kernel proper, this data is located in arch/arm/mach-tegra/common.c.
+ * In the kernel proper, this data is located in arch/arm/mach-tegra/tegra.c.
  * That's because this header is included from multiple files, and we only
  * want a single copy of the data. In particular, the UART probing code above
  * assumes it's running using physical addresses. This is true when this file
@@ -247,6 +225,4 @@ tegra_uart_config:
         .word 0
         /* Debug UART virtual address */
         .word 0
-        /* Scratch space for debug macro */
-        .word 0
 #endif
diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
index c498b60c0505..ef0c8785ba16 100644
--- a/arch/arm/include/uapi/asm/kvm.h
+++ b/arch/arm/include/uapi/asm/kvm.h
@@ -119,6 +119,26 @@ struct kvm_arch_memory_slot {
 #define KVM_REG_ARM_32_CRN_MASK         0x0000000000007800
 #define KVM_REG_ARM_32_CRN_SHIFT        11
 
+#define ARM_CP15_REG_SHIFT_MASK(x,n) \
+        (((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)
+
+#define __ARM_CP15_REG(op1,crn,crm,op2) \
+        (KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \
+        ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \
+        ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \
+        ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
+        ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))
+
+#define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32)
+
+#define __ARM_CP15_REG64(op1,crm) \
+        (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
+#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
+
+#define KVM_REG_ARM_TIMER_CTL           ARM_CP15_REG32(0, 14, 3, 1)
+#define KVM_REG_ARM_TIMER_CNT           ARM_CP15_REG64(1, 14) 
+#define KVM_REG_ARM_TIMER_CVAL          ARM_CP15_REG64(3, 14) 
+
 /* Normal registers are mapped as coprocessor 16. */
 #define KVM_REG_ARM_CORE                (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
 #define KVM_REG_ARM_CORE_REG(name)      (offsetof(struct kvm_regs, name) / 4)
@@ -143,6 +163,14 @@ struct kvm_arch_memory_slot {
 #define KVM_REG_ARM_VFP_FPINST          0x1009
 #define KVM_REG_ARM_VFP_FPINST2         0x100A
 
+/* Device Control API: ARM VGIC */
+#define KVM_DEV_ARM_VGIC_GRP_ADDR       0
+#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS  1
+#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS   2
+#define   KVM_DEV_ARM_VGIC_CPUID_SHIFT  32
+#define   KVM_DEV_ARM_VGIC_CPUID_MASK   (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
+#define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
+#define   KVM_DEV_ARM_VGIC_OFFSET_MASK  (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
 
 /* KVM_IRQ_LINE irq field index values */
 #define KVM_ARM_IRQ_TYPE_SHIFT          24
diff --git a/arch/arm/include/uapi/asm/unistd.h b/arch/arm/include/uapi/asm/unistd.h
index af33b44990ed..fb5584d0cc05 100644
--- a/arch/arm/include/uapi/asm/unistd.h
+++ b/arch/arm/include/uapi/asm/unistd.h
@@ -406,6 +406,8 @@
 #define __NR_process_vm_writev          (__NR_SYSCALL_BASE+377)
 #define __NR_kcmp                       (__NR_SYSCALL_BASE+378)
 #define __NR_finit_module               (__NR_SYSCALL_BASE+379)
+#define __NR_sched_setattr              (__NR_SYSCALL_BASE+380)
+#define __NR_sched_getattr              (__NR_SYSCALL_BASE+381)
 
 /*
  * This may need to be greater than __NR_last_syscall+1 in order to