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-rw-r--r--arch/arm/include/asm/assembler.h2
-rw-r--r--arch/arm/include/asm/atomic.h4
-rw-r--r--arch/arm/include/asm/barrier.h69
-rw-r--r--arch/arm/include/asm/bitops.h2
-rw-r--r--arch/arm/include/asm/bug.h30
-rw-r--r--arch/arm/include/asm/cmpxchg.h295
-rw-r--r--arch/arm/include/asm/compiler.h15
-rw-r--r--arch/arm/include/asm/cp15.h87
-rw-r--r--arch/arm/include/asm/div64.h2
-rw-r--r--arch/arm/include/asm/dma.h1
-rw-r--r--arch/arm/include/asm/domain.h4
-rw-r--r--arch/arm/include/asm/elf.h4
-rw-r--r--arch/arm/include/asm/exec.h6
-rw-r--r--arch/arm/include/asm/hardware/arm_timer.h5
-rw-r--r--arch/arm/include/asm/hardware/cache-l2x0.h6
-rw-r--r--arch/arm/include/asm/hardware/iop3xx.h3
-rw-r--r--arch/arm/include/asm/hardware/iop_adma.h2
-rw-r--r--arch/arm/include/asm/hardware/it8152.h3
-rw-r--r--arch/arm/include/asm/hardware/pl330.h217
-rw-r--r--arch/arm/include/asm/hardware/sa1111.h156
-rw-r--r--arch/arm/include/asm/hardware/timer-sp.h15
-rw-r--r--arch/arm/include/asm/io.h73
-rw-r--r--arch/arm/include/asm/irq.h8
-rw-r--r--arch/arm/include/asm/jump_label.h41
-rw-r--r--arch/arm/include/asm/localtimer.h37
-rw-r--r--arch/arm/include/asm/mc146818rtc.h4
-rw-r--r--arch/arm/include/asm/memory.h2
-rw-r--r--arch/arm/include/asm/mmu.h7
-rw-r--r--arch/arm/include/asm/mmu_context.h29
-rw-r--r--arch/arm/include/asm/opcodes.h59
-rw-r--r--arch/arm/include/asm/page.h2
-rw-r--r--arch/arm/include/asm/perf_event.h1
-rw-r--r--arch/arm/include/asm/posix_types.h55
-rw-r--r--arch/arm/include/asm/processor.h4
-rw-r--r--arch/arm/include/asm/prom.h2
-rw-r--r--arch/arm/include/asm/smp_twd.h25
-rw-r--r--arch/arm/include/asm/switch_to.h18
-rw-r--r--arch/arm/include/asm/system.h552
-rw-r--r--arch/arm/include/asm/system_info.h27
-rw-r--r--arch/arm/include/asm/system_misc.h29
-rw-r--r--arch/arm/include/asm/tlbflush.h136
-rw-r--r--arch/arm/include/asm/traps.h2
-rw-r--r--arch/arm/include/asm/uaccess.h2
43 files changed, 901 insertions, 1142 deletions
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 23371b17b23e..03fb93621d0d 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -23,6 +23,8 @@
23#include <asm/ptrace.h> 23#include <asm/ptrace.h>
24#include <asm/domain.h> 24#include <asm/domain.h>
25 25
26#define IOMEM(x) (x)
27
26/* 28/*
27 * Endian independent macros for shifting bytes within registers. 29 * Endian independent macros for shifting bytes within registers.
28 */ 30 */
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index 86976d034382..68374ba6a943 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -13,7 +13,9 @@
13 13
14#include <linux/compiler.h> 14#include <linux/compiler.h>
15#include <linux/types.h> 15#include <linux/types.h>
16#include <asm/system.h> 16#include <linux/irqflags.h>
17#include <asm/barrier.h>
18#include <asm/cmpxchg.h>
17 19
18#define ATOMIC_INIT(i) { (i) } 20#define ATOMIC_INIT(i) { (i) }
19 21
diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
new file mode 100644
index 000000000000..44f4a09ff37b
--- /dev/null
+++ b/arch/arm/include/asm/barrier.h
@@ -0,0 +1,69 @@
1#ifndef __ASM_BARRIER_H
2#define __ASM_BARRIER_H
3
4#ifndef __ASSEMBLY__
5
6#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
7
8#if __LINUX_ARM_ARCH__ >= 7 || \
9 (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
10#define sev() __asm__ __volatile__ ("sev" : : : "memory")
11#define wfe() __asm__ __volatile__ ("wfe" : : : "memory")
12#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
13#endif
14
15#if __LINUX_ARM_ARCH__ >= 7
16#define isb() __asm__ __volatile__ ("isb" : : : "memory")
17#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
18#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
19#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
20#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
21 : : "r" (0) : "memory")
22#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
23 : : "r" (0) : "memory")
24#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
25 : : "r" (0) : "memory")
26#elif defined(CONFIG_CPU_FA526)
27#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
28 : : "r" (0) : "memory")
29#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
30 : : "r" (0) : "memory")
31#define dmb() __asm__ __volatile__ ("" : : : "memory")
32#else
33#define isb() __asm__ __volatile__ ("" : : : "memory")
34#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
35 : : "r" (0) : "memory")
36#define dmb() __asm__ __volatile__ ("" : : : "memory")
37#endif
38
39#ifdef CONFIG_ARCH_HAS_BARRIERS
40#include <mach/barriers.h>
41#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
42#include <asm/outercache.h>
43#define mb() do { dsb(); outer_sync(); } while (0)
44#define rmb() dsb()
45#define wmb() mb()
46#else
47#include <asm/memory.h>
48#define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
49#define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
50#define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
51#endif
52
53#ifndef CONFIG_SMP
54#define smp_mb() barrier()
55#define smp_rmb() barrier()
56#define smp_wmb() barrier()
57#else
58#define smp_mb() dmb()
59#define smp_rmb() dmb()
60#define smp_wmb() dmb()
61#endif
62
63#define read_barrier_depends() do { } while(0)
64#define smp_read_barrier_depends() do { } while(0)
65
66#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
67
68#endif /* !__ASSEMBLY__ */
69#endif /* __ASM_BARRIER_H */
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index f7419ef9c8f9..e691ec91e4d3 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -24,7 +24,7 @@
24#endif 24#endif
25 25
26#include <linux/compiler.h> 26#include <linux/compiler.h>
27#include <asm/system.h> 27#include <linux/irqflags.h>
28 28
29#define smp_mb__before_clear_bit() smp_mb() 29#define smp_mb__before_clear_bit() smp_mb()
30#define smp_mb__after_clear_bit() smp_mb() 30#define smp_mb__after_clear_bit() smp_mb()
diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h
index fac79dceb736..7af5c6c3653a 100644
--- a/arch/arm/include/asm/bug.h
+++ b/arch/arm/include/asm/bug.h
@@ -1,6 +1,7 @@
1#ifndef _ASMARM_BUG_H 1#ifndef _ASMARM_BUG_H
2#define _ASMARM_BUG_H 2#define _ASMARM_BUG_H
3 3
4#include <linux/linkage.h>
4 5
5#ifdef CONFIG_BUG 6#ifdef CONFIG_BUG
6 7
@@ -57,4 +58,33 @@ do { \
57 58
58#include <asm-generic/bug.h> 59#include <asm-generic/bug.h>
59 60
61struct pt_regs;
62void die(const char *msg, struct pt_regs *regs, int err);
63
64struct siginfo;
65void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
66 unsigned long err, unsigned long trap);
67
68#ifdef CONFIG_ARM_LPAE
69#define FAULT_CODE_ALIGNMENT 33
70#define FAULT_CODE_DEBUG 34
71#else
72#define FAULT_CODE_ALIGNMENT 1
73#define FAULT_CODE_DEBUG 2
74#endif
75
76void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
77 struct pt_regs *),
78 int sig, int code, const char *name);
79
80void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int,
81 struct pt_regs *),
82 int sig, int code, const char *name);
83
84extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
85
86struct mm_struct;
87extern void show_pte(struct mm_struct *mm, unsigned long addr);
88extern void __show_regs(struct pt_regs *);
89
60#endif 90#endif
diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
new file mode 100644
index 000000000000..d41d7cbf0ada
--- /dev/null
+++ b/arch/arm/include/asm/cmpxchg.h
@@ -0,0 +1,295 @@
1#ifndef __ASM_ARM_CMPXCHG_H
2#define __ASM_ARM_CMPXCHG_H
3
4#include <linux/irqflags.h>
5#include <asm/barrier.h>
6
7#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
8/*
9 * On the StrongARM, "swp" is terminally broken since it bypasses the
10 * cache totally. This means that the cache becomes inconsistent, and,
11 * since we use normal loads/stores as well, this is really bad.
12 * Typically, this causes oopsen in filp_close, but could have other,
13 * more disastrous effects. There are two work-arounds:
14 * 1. Disable interrupts and emulate the atomic swap
15 * 2. Clean the cache, perform atomic swap, flush the cache
16 *
17 * We choose (1) since its the "easiest" to achieve here and is not
18 * dependent on the processor type.
19 *
20 * NOTE that this solution won't work on an SMP system, so explcitly
21 * forbid it here.
22 */
23#define swp_is_buggy
24#endif
25
26static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
27{
28 extern void __bad_xchg(volatile void *, int);
29 unsigned long ret;
30#ifdef swp_is_buggy
31 unsigned long flags;
32#endif
33#if __LINUX_ARM_ARCH__ >= 6
34 unsigned int tmp;
35#endif
36
37 smp_mb();
38
39 switch (size) {
40#if __LINUX_ARM_ARCH__ >= 6
41 case 1:
42 asm volatile("@ __xchg1\n"
43 "1: ldrexb %0, [%3]\n"
44 " strexb %1, %2, [%3]\n"
45 " teq %1, #0\n"
46 " bne 1b"
47 : "=&r" (ret), "=&r" (tmp)
48 : "r" (x), "r" (ptr)
49 : "memory", "cc");
50 break;
51 case 4:
52 asm volatile("@ __xchg4\n"
53 "1: ldrex %0, [%3]\n"
54 " strex %1, %2, [%3]\n"
55 " teq %1, #0\n"
56 " bne 1b"
57 : "=&r" (ret), "=&r" (tmp)
58 : "r" (x), "r" (ptr)
59 : "memory", "cc");
60 break;
61#elif defined(swp_is_buggy)
62#ifdef CONFIG_SMP
63#error SMP is not supported on this platform
64#endif
65 case 1:
66 raw_local_irq_save(flags);
67 ret = *(volatile unsigned char *)ptr;
68 *(volatile unsigned char *)ptr = x;
69 raw_local_irq_restore(flags);
70 break;
71
72 case 4:
73 raw_local_irq_save(flags);
74 ret = *(volatile unsigned long *)ptr;
75 *(volatile unsigned long *)ptr = x;
76 raw_local_irq_restore(flags);
77 break;
78#else
79 case 1:
80 asm volatile("@ __xchg1\n"
81 " swpb %0, %1, [%2]"
82 : "=&r" (ret)
83 : "r" (x), "r" (ptr)
84 : "memory", "cc");
85 break;
86 case 4:
87 asm volatile("@ __xchg4\n"
88 " swp %0, %1, [%2]"
89 : "=&r" (ret)
90 : "r" (x), "r" (ptr)
91 : "memory", "cc");
92 break;
93#endif
94 default:
95 __bad_xchg(ptr, size), ret = 0;
96 break;
97 }
98 smp_mb();
99
100 return ret;
101}
102
103#define xchg(ptr,x) \
104 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
105
106#include <asm-generic/cmpxchg-local.h>
107
108#if __LINUX_ARM_ARCH__ < 6
109/* min ARCH < ARMv6 */
110
111#ifdef CONFIG_SMP
112#error "SMP is not supported on this platform"
113#endif
114
115/*
116 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
117 * them available.
118 */
119#define cmpxchg_local(ptr, o, n) \
120 ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
121 (unsigned long)(n), sizeof(*(ptr))))
122#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
123
124#ifndef CONFIG_SMP
125#include <asm-generic/cmpxchg.h>
126#endif
127
128#else /* min ARCH >= ARMv6 */
129
130extern void __bad_cmpxchg(volatile void *ptr, int size);
131
132/*
133 * cmpxchg only support 32-bits operands on ARMv6.
134 */
135
136static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
137 unsigned long new, int size)
138{
139 unsigned long oldval, res;
140
141 switch (size) {
142#ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */
143 case 1:
144 do {
145 asm volatile("@ __cmpxchg1\n"
146 " ldrexb %1, [%2]\n"
147 " mov %0, #0\n"
148 " teq %1, %3\n"
149 " strexbeq %0, %4, [%2]\n"
150 : "=&r" (res), "=&r" (oldval)
151 : "r" (ptr), "Ir" (old), "r" (new)
152 : "memory", "cc");
153 } while (res);
154 break;
155 case 2:
156 do {
157 asm volatile("@ __cmpxchg1\n"
158 " ldrexh %1, [%2]\n"
159 " mov %0, #0\n"
160 " teq %1, %3\n"
161 " strexheq %0, %4, [%2]\n"
162 : "=&r" (res), "=&r" (oldval)
163 : "r" (ptr), "Ir" (old), "r" (new)
164 : "memory", "cc");
165 } while (res);
166 break;
167#endif
168 case 4:
169 do {
170 asm volatile("@ __cmpxchg4\n"
171 " ldrex %1, [%2]\n"
172 " mov %0, #0\n"
173 " teq %1, %3\n"
174 " strexeq %0, %4, [%2]\n"
175 : "=&r" (res), "=&r" (oldval)
176 : "r" (ptr), "Ir" (old), "r" (new)
177 : "memory", "cc");
178 } while (res);
179 break;
180 default:
181 __bad_cmpxchg(ptr, size);
182 oldval = 0;
183 }
184
185 return oldval;
186}
187
188static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
189 unsigned long new, int size)
190{
191 unsigned long ret;
192
193 smp_mb();
194 ret = __cmpxchg(ptr, old, new, size);
195 smp_mb();
196
197 return ret;
198}
199
200#define cmpxchg(ptr,o,n) \
201 ((__typeof__(*(ptr)))__cmpxchg_mb((ptr), \
202 (unsigned long)(o), \
203 (unsigned long)(n), \
204 sizeof(*(ptr))))
205
206static inline unsigned long __cmpxchg_local(volatile void *ptr,
207 unsigned long old,
208 unsigned long new, int size)
209{
210 unsigned long ret;
211
212 switch (size) {
213#ifdef CONFIG_CPU_V6 /* min ARCH == ARMv6 */
214 case 1:
215 case 2:
216 ret = __cmpxchg_local_generic(ptr, old, new, size);
217 break;
218#endif
219 default:
220 ret = __cmpxchg(ptr, old, new, size);
221 }
222
223 return ret;
224}
225
226#define cmpxchg_local(ptr,o,n) \
227 ((__typeof__(*(ptr)))__cmpxchg_local((ptr), \
228 (unsigned long)(o), \
229 (unsigned long)(n), \
230 sizeof(*(ptr))))
231
232#ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */
233
234/*
235 * Note : ARMv7-M (currently unsupported by Linux) does not support
236 * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
237 * not be allowed to use __cmpxchg64.
238 */
239static inline unsigned long long __cmpxchg64(volatile void *ptr,
240 unsigned long long old,
241 unsigned long long new)
242{
243 register unsigned long long oldval asm("r0");
244 register unsigned long long __old asm("r2") = old;
245 register unsigned long long __new asm("r4") = new;
246 unsigned long res;
247
248 do {
249 asm volatile(
250 " @ __cmpxchg8\n"
251 " ldrexd %1, %H1, [%2]\n"
252 " mov %0, #0\n"
253 " teq %1, %3\n"
254 " teqeq %H1, %H3\n"
255 " strexdeq %0, %4, %H4, [%2]\n"
256 : "=&r" (res), "=&r" (oldval)
257 : "r" (ptr), "Ir" (__old), "r" (__new)
258 : "memory", "cc");
259 } while (res);
260
261 return oldval;
262}
263
264static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
265 unsigned long long old,
266 unsigned long long new)
267{
268 unsigned long long ret;
269
270 smp_mb();
271 ret = __cmpxchg64(ptr, old, new);
272 smp_mb();
273
274 return ret;
275}
276
277#define cmpxchg64(ptr,o,n) \
278 ((__typeof__(*(ptr)))__cmpxchg64_mb((ptr), \
279 (unsigned long long)(o), \
280 (unsigned long long)(n)))
281
282#define cmpxchg64_local(ptr,o,n) \
283 ((__typeof__(*(ptr)))__cmpxchg64((ptr), \
284 (unsigned long long)(o), \
285 (unsigned long long)(n)))
286
287#else /* min ARCH = ARMv6 */
288
289#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
290
291#endif
292
293#endif /* __LINUX_ARM_ARCH__ >= 6 */
294
295#endif /* __ASM_ARM_CMPXCHG_H */
diff --git a/arch/arm/include/asm/compiler.h b/arch/arm/include/asm/compiler.h
new file mode 100644
index 000000000000..8155db2f7fa1
--- /dev/null
+++ b/arch/arm/include/asm/compiler.h
@@ -0,0 +1,15 @@
1#ifndef __ASM_ARM_COMPILER_H
2#define __ASM_ARM_COMPILER_H
3
4/*
5 * This is used to ensure the compiler did actually allocate the register we
6 * asked it for some inline assembly sequences. Apparently we can't trust
7 * the compiler from one version to another so a bit of paranoia won't hurt.
8 * This string is meant to be concatenated with the inline asm string and
9 * will cause compilation to stop on mismatch.
10 * (for details, see gcc PR 15089)
11 */
12#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
13
14
15#endif /* __ASM_ARM_COMPILER_H */
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
new file mode 100644
index 000000000000..5ef4d8015a60
--- /dev/null
+++ b/arch/arm/include/asm/cp15.h
@@ -0,0 +1,87 @@
1#ifndef __ASM_ARM_CP15_H
2#define __ASM_ARM_CP15_H
3
4#include <asm/barrier.h>
5
6/*
7 * CR1 bits (CP#15 CR1)
8 */
9#define CR_M (1 << 0) /* MMU enable */
10#define CR_A (1 << 1) /* Alignment abort enable */
11#define CR_C (1 << 2) /* Dcache enable */
12#define CR_W (1 << 3) /* Write buffer enable */
13#define CR_P (1 << 4) /* 32-bit exception handler */
14#define CR_D (1 << 5) /* 32-bit data address range */
15#define CR_L (1 << 6) /* Implementation defined */
16#define CR_B (1 << 7) /* Big endian */
17#define CR_S (1 << 8) /* System MMU protection */
18#define CR_R (1 << 9) /* ROM MMU protection */
19#define CR_F (1 << 10) /* Implementation defined */
20#define CR_Z (1 << 11) /* Implementation defined */
21#define CR_I (1 << 12) /* Icache enable */
22#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
23#define CR_RR (1 << 14) /* Round Robin cache replacement */
24#define CR_L4 (1 << 15) /* LDR pc can set T bit */
25#define CR_DT (1 << 16)
26#define CR_IT (1 << 18)
27#define CR_ST (1 << 19)
28#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
29#define CR_U (1 << 22) /* Unaligned access operation */
30#define CR_XP (1 << 23) /* Extended page tables */
31#define CR_VE (1 << 24) /* Vectored interrupts */
32#define CR_EE (1 << 25) /* Exception (Big) Endian */
33#define CR_TRE (1 << 28) /* TEX remap enable */
34#define CR_AFE (1 << 29) /* Access flag enable */
35#define CR_TE (1 << 30) /* Thumb exception enable */
36
37#ifndef __ASSEMBLY__
38
39#if __LINUX_ARM_ARCH__ >= 4
40#define vectors_high() (cr_alignment & CR_V)
41#else
42#define vectors_high() (0)
43#endif
44
45extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
46extern unsigned long cr_alignment; /* defined in entry-armv.S */
47
48static inline unsigned int get_cr(void)
49{
50 unsigned int val;
51 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
52 return val;
53}
54
55static inline void set_cr(unsigned int val)
56{
57 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
58 : : "r" (val) : "cc");
59 isb();
60}
61
62#ifndef CONFIG_SMP
63extern void adjust_cr(unsigned long mask, unsigned long set);
64#endif
65
66#define CPACC_FULL(n) (3 << (n * 2))
67#define CPACC_SVC(n) (1 << (n * 2))
68#define CPACC_DISABLE(n) (0 << (n * 2))
69
70static inline unsigned int get_copro_access(void)
71{
72 unsigned int val;
73 asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
74 : "=r" (val) : : "cc");
75 return val;
76}
77
78static inline void set_copro_access(unsigned int val)
79{
80 asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
81 : : "r" (val) : "cc");
82 isb();
83}
84
85#endif
86
87#endif
diff --git a/arch/arm/include/asm/div64.h b/arch/arm/include/asm/div64.h
index d3f0a9eee9f6..fe92ccf1d0b0 100644
--- a/arch/arm/include/asm/div64.h
+++ b/arch/arm/include/asm/div64.h
@@ -1,8 +1,8 @@
1#ifndef __ASM_ARM_DIV64 1#ifndef __ASM_ARM_DIV64
2#define __ASM_ARM_DIV64 2#define __ASM_ARM_DIV64
3 3
4#include <asm/system.h>
5#include <linux/types.h> 4#include <linux/types.h>
5#include <asm/compiler.h>
6 6
7/* 7/*
8 * The semantics of do_div() are: 8 * The semantics of do_div() are:
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 69a5b0b6455c..5694a0d6576b 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -19,7 +19,6 @@
19 * It should not be re-used except for that purpose. 19 * It should not be re-used except for that purpose.
20 */ 20 */
21#include <linux/spinlock.h> 21#include <linux/spinlock.h>
22#include <asm/system.h>
23#include <asm/scatterlist.h> 22#include <asm/scatterlist.h>
24 23
25#include <mach/isa-dma.h> 24#include <mach/isa-dma.h>
diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h
index b5dc173d336f..3d2220498abc 100644
--- a/arch/arm/include/asm/domain.h
+++ b/arch/arm/include/asm/domain.h
@@ -10,6 +10,10 @@
10#ifndef __ASM_PROC_DOMAIN_H 10#ifndef __ASM_PROC_DOMAIN_H
11#define __ASM_PROC_DOMAIN_H 11#define __ASM_PROC_DOMAIN_H
12 12
13#ifndef __ASSEMBLY__
14#include <asm/barrier.h>
15#endif
16
13/* 17/*
14 * Domain numbers 18 * Domain numbers
15 * 19 *
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 0e9ce8d9686e..38050b1c4800 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -130,8 +130,4 @@ struct mm_struct;
130extern unsigned long arch_randomize_brk(struct mm_struct *mm); 130extern unsigned long arch_randomize_brk(struct mm_struct *mm);
131#define arch_randomize_brk arch_randomize_brk 131#define arch_randomize_brk arch_randomize_brk
132 132
133extern int vectors_user_mapping(void);
134#define arch_setup_additional_pages(bprm, uses_interp) vectors_user_mapping()
135#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
136
137#endif 133#endif
diff --git a/arch/arm/include/asm/exec.h b/arch/arm/include/asm/exec.h
new file mode 100644
index 000000000000..7c4fbef72b3a
--- /dev/null
+++ b/arch/arm/include/asm/exec.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_ARM_EXEC_H
2#define __ASM_ARM_EXEC_H
3
4#define arch_align_stack(x) (x)
5
6#endif /* __ASM_ARM_EXEC_H */
diff --git a/arch/arm/include/asm/hardware/arm_timer.h b/arch/arm/include/asm/hardware/arm_timer.h
index c0f4e7bf22de..d6030ff599db 100644
--- a/arch/arm/include/asm/hardware/arm_timer.h
+++ b/arch/arm/include/asm/hardware/arm_timer.h
@@ -9,7 +9,12 @@
9 * 9 *
10 * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview 10 * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
11 * can have 16-bit or 32-bit selectable via a bit in the control register. 11 * can have 16-bit or 32-bit selectable via a bit in the control register.
12 *
13 * Every SP804 contains two identical timers.
12 */ 14 */
15#define TIMER_1_BASE 0x00
16#define TIMER_2_BASE 0x20
17
13#define TIMER_LOAD 0x00 /* ACVR rw */ 18#define TIMER_LOAD 0x00 /* ACVR rw */
14#define TIMER_VALUE 0x04 /* ACVR ro */ 19#define TIMER_VALUE 0x04 /* ACVR ro */
15#define TIMER_CTRL 0x08 /* ACVR rw */ 20#define TIMER_CTRL 0x08 /* ACVR rw */
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 7df239bcdf27..c4c87bc12231 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -103,11 +103,11 @@
103#define L2X0_ADDR_FILTER_EN 1 103#define L2X0_ADDR_FILTER_EN 1
104 104
105#ifndef __ASSEMBLY__ 105#ifndef __ASSEMBLY__
106extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); 106extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask);
107#if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF) 107#if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
108extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask); 108extern int l2x0_of_init(u32 aux_val, u32 aux_mask);
109#else 109#else
110static inline int l2x0_of_init(__u32 aux_val, __u32 aux_mask) 110static inline int l2x0_of_init(u32 aux_val, u32 aux_mask)
111{ 111{
112 return -ENODEV; 112 return -ENODEV;
113} 113}
diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index 077c32326c63..2ff2c75a4639 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -231,6 +231,9 @@ extern int iop3xx_get_init_atu(void);
231 231
232 232
233#ifndef __ASSEMBLY__ 233#ifndef __ASSEMBLY__
234
235#include <linux/types.h>
236
234void iop3xx_map_io(void); 237void iop3xx_map_io(void);
235void iop_init_cp6_handler(void); 238void iop_init_cp6_handler(void);
236void iop_init_time(unsigned long tickrate); 239void iop_init_time(unsigned long tickrate);
diff --git a/arch/arm/include/asm/hardware/iop_adma.h b/arch/arm/include/asm/hardware/iop_adma.h
index 59b8c3892f76..122f86d8c991 100644
--- a/arch/arm/include/asm/hardware/iop_adma.h
+++ b/arch/arm/include/asm/hardware/iop_adma.h
@@ -49,7 +49,6 @@ struct iop_adma_device {
49/** 49/**
50 * struct iop_adma_chan - internal representation of an ADMA device 50 * struct iop_adma_chan - internal representation of an ADMA device
51 * @pending: allows batching of hardware operations 51 * @pending: allows batching of hardware operations
52 * @completed_cookie: identifier for the most recently completed operation
53 * @lock: serializes enqueue/dequeue operations to the slot pool 52 * @lock: serializes enqueue/dequeue operations to the slot pool
54 * @mmr_base: memory mapped register base 53 * @mmr_base: memory mapped register base
55 * @chain: device chain view of the descriptors 54 * @chain: device chain view of the descriptors
@@ -62,7 +61,6 @@ struct iop_adma_device {
62 */ 61 */
63struct iop_adma_chan { 62struct iop_adma_chan {
64 int pending; 63 int pending;
65 dma_cookie_t completed_cookie;
66 spinlock_t lock; /* protects the descriptor slot pool */ 64 spinlock_t lock; /* protects the descriptor slot pool */
67 void __iomem *mmr_base; 65 void __iomem *mmr_base;
68 struct list_head chain; 66 struct list_head chain;
diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h
index 43cab498bc27..73f84fa4f366 100644
--- a/arch/arm/include/asm/hardware/it8152.h
+++ b/arch/arm/include/asm/hardware/it8152.h
@@ -9,6 +9,9 @@
9 9
10#ifndef __ASM_HARDWARE_IT8152_H 10#ifndef __ASM_HARDWARE_IT8152_H
11#define __ASM_HARDWARE_IT8152_H 11#define __ASM_HARDWARE_IT8152_H
12
13#include <mach/irqs.h>
14
12extern void __iomem *it8152_base_address; 15extern void __iomem *it8152_base_address;
13 16
14#define IT8152_IO_BASE (it8152_base_address + 0x03e00000) 17#define IT8152_IO_BASE (it8152_base_address + 0x03e00000)
diff --git a/arch/arm/include/asm/hardware/pl330.h b/arch/arm/include/asm/hardware/pl330.h
deleted file mode 100644
index c1821385abfa..000000000000
--- a/arch/arm/include/asm/hardware/pl330.h
+++ /dev/null
@@ -1,217 +0,0 @@
1/* linux/include/asm/hardware/pl330.h
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#ifndef __PL330_CORE_H
22#define __PL330_CORE_H
23
24#define PL330_MAX_CHAN 8
25#define PL330_MAX_IRQS 32
26#define PL330_MAX_PERI 32
27
28enum pl330_srccachectrl {
29 SCCTRL0 = 0, /* Noncacheable and nonbufferable */
30 SCCTRL1, /* Bufferable only */
31 SCCTRL2, /* Cacheable, but do not allocate */
32 SCCTRL3, /* Cacheable and bufferable, but do not allocate */
33 SINVALID1,
34 SINVALID2,
35 SCCTRL6, /* Cacheable write-through, allocate on reads only */
36 SCCTRL7, /* Cacheable write-back, allocate on reads only */
37};
38
39enum pl330_dstcachectrl {
40 DCCTRL0 = 0, /* Noncacheable and nonbufferable */
41 DCCTRL1, /* Bufferable only */
42 DCCTRL2, /* Cacheable, but do not allocate */
43 DCCTRL3, /* Cacheable and bufferable, but do not allocate */
44 DINVALID1, /* AWCACHE = 0x1000 */
45 DINVALID2,
46 DCCTRL6, /* Cacheable write-through, allocate on writes only */
47 DCCTRL7, /* Cacheable write-back, allocate on writes only */
48};
49
50/* Populated by the PL330 core driver for DMA API driver's info */
51struct pl330_config {
52 u32 periph_id;
53 u32 pcell_id;
54#define DMAC_MODE_NS (1 << 0)
55 unsigned int mode;
56 unsigned int data_bus_width:10; /* In number of bits */
57 unsigned int data_buf_dep:10;
58 unsigned int num_chan:4;
59 unsigned int num_peri:6;
60 u32 peri_ns;
61 unsigned int num_events:6;
62 u32 irq_ns;
63};
64
65/* Handle to the DMAC provided to the PL330 core */
66struct pl330_info {
67 /* Owning device */
68 struct device *dev;
69 /* Size of MicroCode buffers for each channel. */
70 unsigned mcbufsz;
71 /* ioremap'ed address of PL330 registers. */
72 void __iomem *base;
73 /* Client can freely use it. */
74 void *client_data;
75 /* PL330 core data, Client must not touch it. */
76 void *pl330_data;
77 /* Populated by the PL330 core driver during pl330_add */
78 struct pl330_config pcfg;
79 /*
80 * If the DMAC has some reset mechanism, then the
81 * client may want to provide pointer to the method.
82 */
83 void (*dmac_reset)(struct pl330_info *pi);
84};
85
86enum pl330_byteswap {
87 SWAP_NO = 0,
88 SWAP_2,
89 SWAP_4,
90 SWAP_8,
91 SWAP_16,
92};
93
94/**
95 * Request Configuration.
96 * The PL330 core does not modify this and uses the last
97 * working configuration if the request doesn't provide any.
98 *
99 * The Client may want to provide this info only for the
100 * first request and a request with new settings.
101 */
102struct pl330_reqcfg {
103 /* Address Incrementing */
104 unsigned dst_inc:1;
105 unsigned src_inc:1;
106
107 /*
108 * For now, the SRC & DST protection levels
109 * and burst size/length are assumed same.
110 */
111 bool nonsecure;
112 bool privileged;
113 bool insnaccess;
114 unsigned brst_len:5;
115 unsigned brst_size:3; /* in power of 2 */
116
117 enum pl330_dstcachectrl dcctl;
118 enum pl330_srccachectrl scctl;
119 enum pl330_byteswap swap;
120};
121
122/*
123 * One cycle of DMAC operation.
124 * There may be more than one xfer in a request.
125 */
126struct pl330_xfer {
127 u32 src_addr;
128 u32 dst_addr;
129 /* Size to xfer */
130 u32 bytes;
131 /*
132 * Pointer to next xfer in the list.
133 * The last xfer in the req must point to NULL.
134 */
135 struct pl330_xfer *next;
136};
137
138/* The xfer callbacks are made with one of these arguments. */
139enum pl330_op_err {
140 /* The all xfers in the request were success. */
141 PL330_ERR_NONE,
142 /* If req aborted due to global error. */
143 PL330_ERR_ABORT,
144 /* If req failed due to problem with Channel. */
145 PL330_ERR_FAIL,
146};
147
148enum pl330_reqtype {
149 MEMTOMEM,
150 MEMTODEV,
151 DEVTOMEM,
152 DEVTODEV,
153};
154
155/* A request defining Scatter-Gather List ending with NULL xfer. */
156struct pl330_req {
157 enum pl330_reqtype rqtype;
158 /* Index of peripheral for the xfer. */
159 unsigned peri:5;
160 /* Unique token for this xfer, set by the client. */
161 void *token;
162 /* Callback to be called after xfer. */
163 void (*xfer_cb)(void *token, enum pl330_op_err err);
164 /* If NULL, req will be done at last set parameters. */
165 struct pl330_reqcfg *cfg;
166 /* Pointer to first xfer in the request. */
167 struct pl330_xfer *x;
168};
169
170/*
171 * To know the status of the channel and DMAC, the client
172 * provides a pointer to this structure. The PL330 core
173 * fills it with current information.
174 */
175struct pl330_chanstatus {
176 /*
177 * If the DMAC engine halted due to some error,
178 * the client should remove-add DMAC.
179 */
180 bool dmac_halted;
181 /*
182 * If channel is halted due to some error,
183 * the client should ABORT/FLUSH and START the channel.
184 */
185 bool faulting;
186 /* Location of last load */
187 u32 src_addr;
188 /* Location of last store */
189 u32 dst_addr;
190 /*
191 * Pointer to the currently active req, NULL if channel is
192 * inactive, even though the requests may be present.
193 */
194 struct pl330_req *top_req;
195 /* Pointer to req waiting second in the queue if any. */
196 struct pl330_req *wait_req;
197};
198
199enum pl330_chan_op {
200 /* Start the channel */
201 PL330_OP_START,
202 /* Abort the active xfer */
203 PL330_OP_ABORT,
204 /* Stop xfer and flush queue */
205 PL330_OP_FLUSH,
206};
207
208extern int pl330_add(struct pl330_info *);
209extern void pl330_del(struct pl330_info *pi);
210extern int pl330_update(const struct pl330_info *pi);
211extern void pl330_release_channel(void *ch_id);
212extern void *pl330_request_channel(const struct pl330_info *pi);
213extern int pl330_chan_status(void *ch_id, struct pl330_chanstatus *pstatus);
214extern int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op);
215extern int pl330_submit_req(void *ch_id, struct pl330_req *r);
216
217#endif /* __PL330_CORE_H */
diff --git a/arch/arm/include/asm/hardware/sa1111.h b/arch/arm/include/asm/hardware/sa1111.h
index 92ed254c175b..7c2bbc7f0be1 100644
--- a/arch/arm/include/asm/hardware/sa1111.h
+++ b/arch/arm/include/asm/hardware/sa1111.h
@@ -132,34 +132,10 @@
132#define SKPCR_DCLKEN (1<<7) 132#define SKPCR_DCLKEN (1<<7)
133#define SKPCR_PWMCLKEN (1<<8) 133#define SKPCR_PWMCLKEN (1<<8)
134 134
135/* 135/* USB Host controller */
136 * USB Host controller
137 */
138#define SA1111_USB 0x0400 136#define SA1111_USB 0x0400
139 137
140/* 138/*
141 * Offsets from SA1111_USB_BASE
142 */
143#define SA1111_USB_STATUS 0x0118
144#define SA1111_USB_RESET 0x011c
145#define SA1111_USB_IRQTEST 0x0120
146
147#define USB_RESET_FORCEIFRESET (1 << 0)
148#define USB_RESET_FORCEHCRESET (1 << 1)
149#define USB_RESET_CLKGENRESET (1 << 2)
150#define USB_RESET_SIMSCALEDOWN (1 << 3)
151#define USB_RESET_USBINTTEST (1 << 4)
152#define USB_RESET_SLEEPSTBYEN (1 << 5)
153#define USB_RESET_PWRSENSELOW (1 << 6)
154#define USB_RESET_PWRCTRLLOW (1 << 7)
155
156#define USB_STATUS_IRQHCIRMTWKUP (1 << 7)
157#define USB_STATUS_IRQHCIBUFFACC (1 << 8)
158#define USB_STATUS_NIRQHCIM (1 << 9)
159#define USB_STATUS_NHCIMFCLR (1 << 10)
160#define USB_STATUS_USBPWRSENSE (1 << 11)
161
162/*
163 * Serial Audio Controller 139 * Serial Audio Controller
164 * 140 *
165 * Registers 141 * Registers
@@ -327,22 +303,6 @@
327 * PC_SSR GPIO Block C Sleep State 303 * PC_SSR GPIO Block C Sleep State
328 */ 304 */
329 305
330#define _PA_DDR _SA1111( 0x1000 )
331#define _PA_DRR _SA1111( 0x1004 )
332#define _PA_DWR _SA1111( 0x1004 )
333#define _PA_SDR _SA1111( 0x1008 )
334#define _PA_SSR _SA1111( 0x100c )
335#define _PB_DDR _SA1111( 0x1010 )
336#define _PB_DRR _SA1111( 0x1014 )
337#define _PB_DWR _SA1111( 0x1014 )
338#define _PB_SDR _SA1111( 0x1018 )
339#define _PB_SSR _SA1111( 0x101c )
340#define _PC_DDR _SA1111( 0x1020 )
341#define _PC_DRR _SA1111( 0x1024 )
342#define _PC_DWR _SA1111( 0x1024 )
343#define _PC_SDR _SA1111( 0x1028 )
344#define _PC_SSR _SA1111( 0x102c )
345
346#define SA1111_GPIO 0x1000 306#define SA1111_GPIO 0x1000
347 307
348#define SA1111_GPIO_PADDR (0x000) 308#define SA1111_GPIO_PADDR (0x000)
@@ -425,106 +385,30 @@
425#define SA1111_WAKEPOL0 0x0034 385#define SA1111_WAKEPOL0 0x0034
426#define SA1111_WAKEPOL1 0x0038 386#define SA1111_WAKEPOL1 0x0038
427 387
428/* 388/* PS/2 Trackpad and Mouse Interfaces */
429 * PS/2 Trackpad and Mouse Interfaces
430 *
431 * Registers
432 * PS2CR Control Register
433 * PS2STAT Status Register
434 * PS2DATA Transmit/Receive Data register
435 * PS2CLKDIV Clock Division Register
436 * PS2PRECNT Clock Precount Register
437 * PS2TEST1 Test register 1
438 * PS2TEST2 Test register 2
439 * PS2TEST3 Test register 3
440 * PS2TEST4 Test register 4
441 */
442
443#define SA1111_KBD 0x0a00 389#define SA1111_KBD 0x0a00
444#define SA1111_MSE 0x0c00 390#define SA1111_MSE 0x0c00
445 391
446/* 392/* PCMCIA Interface */
447 * These are offsets from the above bases. 393#define SA1111_PCMCIA 0x1600
448 */
449#define SA1111_PS2CR 0x0000
450#define SA1111_PS2STAT 0x0004
451#define SA1111_PS2DATA 0x0008
452#define SA1111_PS2CLKDIV 0x000c
453#define SA1111_PS2PRECNT 0x0010
454
455#define PS2CR_ENA 0x08
456#define PS2CR_FKD 0x02
457#define PS2CR_FKC 0x01
458
459#define PS2STAT_STP 0x0100
460#define PS2STAT_TXE 0x0080
461#define PS2STAT_TXB 0x0040
462#define PS2STAT_RXF 0x0020
463#define PS2STAT_RXB 0x0010
464#define PS2STAT_ENA 0x0008
465#define PS2STAT_RXP 0x0004
466#define PS2STAT_KBD 0x0002
467#define PS2STAT_KBC 0x0001
468 394
469/*
470 * PCMCIA Interface
471 *
472 * Registers
473 * PCSR Status Register
474 * PCCR Control Register
475 * PCSSR Sleep State Register
476 */
477
478#define SA1111_PCMCIA 0x1600
479
480/*
481 * These are offsets from the above base.
482 */
483#define SA1111_PCCR 0x0000
484#define SA1111_PCSSR 0x0004
485#define SA1111_PCSR 0x0008
486
487#define PCSR_S0_READY (1<<0)
488#define PCSR_S1_READY (1<<1)
489#define PCSR_S0_DETECT (1<<2)
490#define PCSR_S1_DETECT (1<<3)
491#define PCSR_S0_VS1 (1<<4)
492#define PCSR_S0_VS2 (1<<5)
493#define PCSR_S1_VS1 (1<<6)
494#define PCSR_S1_VS2 (1<<7)
495#define PCSR_S0_WP (1<<8)
496#define PCSR_S1_WP (1<<9)
497#define PCSR_S0_BVD1 (1<<10)
498#define PCSR_S0_BVD2 (1<<11)
499#define PCSR_S1_BVD1 (1<<12)
500#define PCSR_S1_BVD2 (1<<13)
501
502#define PCCR_S0_RST (1<<0)
503#define PCCR_S1_RST (1<<1)
504#define PCCR_S0_FLT (1<<2)
505#define PCCR_S1_FLT (1<<3)
506#define PCCR_S0_PWAITEN (1<<4)
507#define PCCR_S1_PWAITEN (1<<5)
508#define PCCR_S0_PSE (1<<6)
509#define PCCR_S1_PSE (1<<7)
510
511#define PCSSR_S0_SLEEP (1<<0)
512#define PCSSR_S1_SLEEP (1<<1)
513 395
514 396
515 397
516 398
517extern struct bus_type sa1111_bus_type; 399extern struct bus_type sa1111_bus_type;
518 400
519#define SA1111_DEVID_SBI 0 401#define SA1111_DEVID_SBI (1 << 0)
520#define SA1111_DEVID_SK 1 402#define SA1111_DEVID_SK (1 << 1)
521#define SA1111_DEVID_USB 2 403#define SA1111_DEVID_USB (1 << 2)
522#define SA1111_DEVID_SAC 3 404#define SA1111_DEVID_SAC (1 << 3)
523#define SA1111_DEVID_SSP 4 405#define SA1111_DEVID_SSP (1 << 4)
524#define SA1111_DEVID_PS2 5 406#define SA1111_DEVID_PS2 (3 << 5)
525#define SA1111_DEVID_GPIO 6 407#define SA1111_DEVID_PS2_KBD (1 << 5)
526#define SA1111_DEVID_INT 7 408#define SA1111_DEVID_PS2_MSE (1 << 6)
527#define SA1111_DEVID_PCMCIA 8 409#define SA1111_DEVID_GPIO (1 << 7)
410#define SA1111_DEVID_INT (1 << 8)
411#define SA1111_DEVID_PCMCIA (1 << 9)
528 412
529struct sa1111_dev { 413struct sa1111_dev {
530 struct device dev; 414 struct device dev;
@@ -548,6 +432,7 @@ struct sa1111_driver {
548 int (*remove)(struct sa1111_dev *); 432 int (*remove)(struct sa1111_dev *);
549 int (*suspend)(struct sa1111_dev *, pm_message_t); 433 int (*suspend)(struct sa1111_dev *, pm_message_t);
550 int (*resume)(struct sa1111_dev *); 434 int (*resume)(struct sa1111_dev *);
435 void (*shutdown)(struct sa1111_dev *);
551}; 436};
552 437
553#define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv) 438#define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv)
@@ -555,9 +440,10 @@ struct sa1111_driver {
555#define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name) 440#define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name)
556 441
557/* 442/*
558 * These frob the SKPCR register. 443 * These frob the SKPCR register, and call platform specific
444 * enable/disable functions.
559 */ 445 */
560void sa1111_enable_device(struct sa1111_dev *); 446int sa1111_enable_device(struct sa1111_dev *);
561void sa1111_disable_device(struct sa1111_dev *); 447void sa1111_disable_device(struct sa1111_dev *);
562 448
563unsigned int sa1111_pll_clock(struct sa1111_dev *); 449unsigned int sa1111_pll_clock(struct sa1111_dev *);
@@ -580,6 +466,10 @@ void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned i
580 466
581struct sa1111_platform_data { 467struct sa1111_platform_data {
582 int irq_base; /* base for cascaded on-chip IRQs */ 468 int irq_base; /* base for cascaded on-chip IRQs */
469 unsigned disable_devs;
470 void *data;
471 int (*enable)(void *, unsigned);
472 void (*disable)(void *, unsigned);
583}; 473};
584 474
585#endif /* _ASM_ARCH_SA1111 */ 475#endif /* _ASM_ARCH_SA1111 */
diff --git a/arch/arm/include/asm/hardware/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h
index 4384d81eee79..2dd9d3f83f29 100644
--- a/arch/arm/include/asm/hardware/timer-sp.h
+++ b/arch/arm/include/asm/hardware/timer-sp.h
@@ -1,2 +1,15 @@
1void sp804_clocksource_init(void __iomem *, const char *); 1void __sp804_clocksource_and_sched_clock_init(void __iomem *,
2 const char *, int);
3
4static inline void sp804_clocksource_init(void __iomem *base, const char *name)
5{
6 __sp804_clocksource_and_sched_clock_init(base, name, 0);
7}
8
9static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base,
10 const char *name)
11{
12 __sp804_clocksource_and_sched_clock_init(base, name, 1);
13}
14
2void sp804_clockevents_init(void __iomem *, unsigned int, const char *); 15void sp804_clockevents_init(void __iomem *, unsigned int, const char *);
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 9275828feb3d..df0ac0bb39aa 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -26,7 +26,6 @@
26#include <linux/types.h> 26#include <linux/types.h>
27#include <asm/byteorder.h> 27#include <asm/byteorder.h>
28#include <asm/memory.h> 28#include <asm/memory.h>
29#include <asm/system.h>
30#include <asm-generic/pci_iomap.h> 29#include <asm-generic/pci_iomap.h>
31 30
32/* 31/*
@@ -83,6 +82,11 @@ extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, uns
83extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int); 82extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
84extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached); 83extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached);
85extern void __iounmap(volatile void __iomem *addr); 84extern void __iounmap(volatile void __iomem *addr);
85extern void __arm_iounmap(volatile void __iomem *addr);
86
87extern void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
88 unsigned int, void *);
89extern void (*arch_iounmap)(volatile void __iomem *);
86 90
87/* 91/*
88 * Bad read/write accesses... 92 * Bad read/write accesses...
@@ -97,8 +101,11 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
97 return (void __iomem *)addr; 101 return (void __iomem *)addr;
98} 102}
99 103
104#define IOMEM(x) ((void __force __iomem *)(x))
105
100/* IO barriers */ 106/* IO barriers */
101#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 107#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
108#include <asm/barrier.h>
102#define __iormb() rmb() 109#define __iormb() rmb()
103#define __iowmb() wmb() 110#define __iowmb() wmb()
104#else 111#else
@@ -109,7 +116,11 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
109/* 116/*
110 * Now, pick up the machine-defined IO definitions 117 * Now, pick up the machine-defined IO definitions
111 */ 118 */
119#ifdef CONFIG_NEED_MACH_IO_H
112#include <mach/io.h> 120#include <mach/io.h>
121#else
122#define __io(a) ({ (void)(a); __typesafe_io(0); })
123#endif
113 124
114/* 125/*
115 * This is the limit of PC card/PCI/ISA IO space, which is by default 126 * This is the limit of PC card/PCI/ISA IO space, which is by default
@@ -211,18 +222,18 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
211 * Again, this are defined to perform little endian accesses. See the 222 * Again, this are defined to perform little endian accesses. See the
212 * IO port primitives for more information. 223 * IO port primitives for more information.
213 */ 224 */
214#ifdef __mem_pci 225#ifndef readl
215#define readb_relaxed(c) ({ u8 __r = __raw_readb(__mem_pci(c)); __r; }) 226#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
216#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \ 227#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
217 __raw_readw(__mem_pci(c))); __r; }) 228 __raw_readw(c)); __r; })
218#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ 229#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
219 __raw_readl(__mem_pci(c))); __r; }) 230 __raw_readl(c)); __r; })
220 231
221#define writeb_relaxed(v,c) ((void)__raw_writeb(v,__mem_pci(c))) 232#define writeb_relaxed(v,c) ((void)__raw_writeb(v,c))
222#define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \ 233#define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \
223 cpu_to_le16(v),__mem_pci(c))) 234 cpu_to_le16(v),c))
224#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \ 235#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
225 cpu_to_le32(v),__mem_pci(c))) 236 cpu_to_le32(v),c))
226 237
227#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) 238#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
228#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) 239#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
@@ -232,30 +243,19 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
232#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); }) 243#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
233#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); }) 244#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
234 245
235#define readsb(p,d,l) __raw_readsb(__mem_pci(p),d,l) 246#define readsb(p,d,l) __raw_readsb(p,d,l)
236#define readsw(p,d,l) __raw_readsw(__mem_pci(p),d,l) 247#define readsw(p,d,l) __raw_readsw(p,d,l)
237#define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l) 248#define readsl(p,d,l) __raw_readsl(p,d,l)
238
239#define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l)
240#define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l)
241#define writesl(p,d,l) __raw_writesl(__mem_pci(p),d,l)
242 249
243#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) 250#define writesb(p,d,l) __raw_writesb(p,d,l)
244#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) 251#define writesw(p,d,l) __raw_writesw(p,d,l)
245#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) 252#define writesl(p,d,l) __raw_writesl(p,d,l)
246 253
247#elif !defined(readb) 254#define memset_io(c,v,l) _memset_io(c,(v),(l))
255#define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l))
256#define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l))
248 257
249#define readb(c) (__readwrite_bug("readb"),0) 258#endif /* readl */
250#define readw(c) (__readwrite_bug("readw"),0)
251#define readl(c) (__readwrite_bug("readl"),0)
252#define writeb(v,c) __readwrite_bug("writeb")
253#define writew(v,c) __readwrite_bug("writew")
254#define writel(v,c) __readwrite_bug("writel")
255
256#define check_signature(io,sig,len) (0)
257
258#endif /* __mem_pci */
259 259
260/* 260/*
261 * ioremap and friends. 261 * ioremap and friends.
@@ -264,16 +264,11 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
264 * Documentation/io-mapping.txt. 264 * Documentation/io-mapping.txt.
265 * 265 *
266 */ 266 */
267#ifndef __arch_ioremap 267#define ioremap(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
268#define __arch_ioremap __arm_ioremap 268#define ioremap_nocache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
269#define __arch_iounmap __iounmap 269#define ioremap_cached(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_CACHED)
270#endif 270#define ioremap_wc(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_WC)
271 271#define iounmap __arm_iounmap
272#define ioremap(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
273#define ioremap_nocache(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
274#define ioremap_cached(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
275#define ioremap_wc(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_WC)
276#define iounmap __arch_iounmap
277 272
278/* 273/*
279 * io{read,write}{8,16,32} macros 274 * io{read,write}{8,16,32} macros
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 5a526afb5f18..35c21c375d81 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -1,14 +1,18 @@
1#ifndef __ASM_ARM_IRQ_H 1#ifndef __ASM_ARM_IRQ_H
2#define __ASM_ARM_IRQ_H 2#define __ASM_ARM_IRQ_H
3 3
4#define NR_IRQS_LEGACY 16
5
6#ifndef CONFIG_SPARSE_IRQ
4#include <mach/irqs.h> 7#include <mach/irqs.h>
8#else
9#define NR_IRQS NR_IRQS_LEGACY
10#endif
5 11
6#ifndef irq_canonicalize 12#ifndef irq_canonicalize
7#define irq_canonicalize(i) (i) 13#define irq_canonicalize(i) (i)
8#endif 14#endif
9 15
10#define NR_IRQS_LEGACY 16
11
12/* 16/*
13 * Use this value to indicate lack of interrupt 17 * Use this value to indicate lack of interrupt
14 * capability 18 * capability
diff --git a/arch/arm/include/asm/jump_label.h b/arch/arm/include/asm/jump_label.h
new file mode 100644
index 000000000000..5c5ca2ea62b0
--- /dev/null
+++ b/arch/arm/include/asm/jump_label.h
@@ -0,0 +1,41 @@
1#ifndef _ASM_ARM_JUMP_LABEL_H
2#define _ASM_ARM_JUMP_LABEL_H
3
4#ifdef __KERNEL__
5
6#include <linux/types.h>
7#include <asm/system.h>
8
9#define JUMP_LABEL_NOP_SIZE 4
10
11#ifdef CONFIG_THUMB2_KERNEL
12#define JUMP_LABEL_NOP "nop.w"
13#else
14#define JUMP_LABEL_NOP "nop"
15#endif
16
17static __always_inline bool arch_static_branch(struct jump_label_key *key)
18{
19 asm goto("1:\n\t"
20 JUMP_LABEL_NOP "\n\t"
21 ".pushsection __jump_table, \"aw\"\n\t"
22 ".word 1b, %l[l_yes], %c0\n\t"
23 ".popsection\n\t"
24 : : "i" (key) : : l_yes);
25
26 return false;
27l_yes:
28 return true;
29}
30
31#endif /* __KERNEL__ */
32
33typedef u32 jump_label_t;
34
35struct jump_entry {
36 jump_label_t code;
37 jump_label_t target;
38 jump_label_t key;
39};
40
41#endif
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
index c6a18424888e..f77ffc1eb0c2 100644
--- a/arch/arm/include/asm/localtimer.h
+++ b/arch/arm/include/asm/localtimer.h
@@ -11,47 +11,24 @@
11#define __ASM_ARM_LOCALTIMER_H 11#define __ASM_ARM_LOCALTIMER_H
12 12
13#include <linux/errno.h> 13#include <linux/errno.h>
14#include <linux/interrupt.h>
15 14
16struct clock_event_device; 15struct clock_event_device;
17 16
18/* 17struct local_timer_ops {
19 * Setup a per-cpu timer, whether it be a local timer or dummy broadcast 18 int (*setup)(struct clock_event_device *);
20 */ 19 void (*stop)(struct clock_event_device *);
21void percpu_timer_setup(void); 20};
22 21
23#ifdef CONFIG_LOCAL_TIMERS 22#ifdef CONFIG_LOCAL_TIMERS
24
25#ifdef CONFIG_HAVE_ARM_TWD
26
27#include "smp_twd.h"
28
29#define local_timer_stop(c) twd_timer_stop((c))
30
31#else
32
33/*
34 * Stop the local timer
35 */
36void local_timer_stop(struct clock_event_device *);
37
38#endif
39
40/* 23/*
41 * Setup a local timer interrupt for a CPU. 24 * Register a local timer driver
42 */ 25 */
43int local_timer_setup(struct clock_event_device *); 26int local_timer_register(struct local_timer_ops *);
44
45#else 27#else
46 28static inline int local_timer_register(struct local_timer_ops *ops)
47static inline int local_timer_setup(struct clock_event_device *evt)
48{ 29{
49 return -ENXIO; 30 return -ENXIO;
50} 31}
51
52static inline void local_timer_stop(struct clock_event_device *evt)
53{
54}
55#endif 32#endif
56 33
57#endif 34#endif
diff --git a/arch/arm/include/asm/mc146818rtc.h b/arch/arm/include/asm/mc146818rtc.h
index 6b884d2b0b69..e8567bb99dfc 100644
--- a/arch/arm/include/asm/mc146818rtc.h
+++ b/arch/arm/include/asm/mc146818rtc.h
@@ -5,7 +5,9 @@
5#define _ASM_MC146818RTC_H 5#define _ASM_MC146818RTC_H
6 6
7#include <linux/io.h> 7#include <linux/io.h>
8#include <mach/irqs.h> 8#include <linux/kernel.h>
9
10#define RTC_IRQ BUILD_BUG_ON(1)
9 11
10#ifndef RTC_PORT 12#ifndef RTC_PORT
11#define RTC_PORT(x) (0x70 + (x)) 13#define RTC_PORT(x) (0x70 + (x))
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index a8997d71084e..fcb575747e5e 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -116,6 +116,8 @@
116#define MODULES_END (END_MEM) 116#define MODULES_END (END_MEM)
117#define MODULES_VADDR (PHYS_OFFSET) 117#define MODULES_VADDR (PHYS_OFFSET)
118 118
119#define XIP_VIRT_ADDR(physaddr) (physaddr)
120
119#endif /* !CONFIG_MMU */ 121#endif /* !CONFIG_MMU */
120 122
121/* 123/*
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index 14965658a923..b8e580a297e4 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -34,4 +34,11 @@ typedef struct {
34 34
35#endif 35#endif
36 36
37/*
38 * switch_mm() may do a full cache flush over the context switch,
39 * so enable interrupts over the context switch to avoid high
40 * latency.
41 */
42#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
43
37#endif 44#endif
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index 71605d9f8e42..a0b3cac0547c 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -18,6 +18,7 @@
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/cachetype.h> 19#include <asm/cachetype.h>
20#include <asm/proc-fns.h> 20#include <asm/proc-fns.h>
21#include <asm-generic/mm_hooks.h>
21 22
22void __check_kvm_seq(struct mm_struct *mm); 23void __check_kvm_seq(struct mm_struct *mm);
23 24
@@ -133,32 +134,4 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
133#define deactivate_mm(tsk,mm) do { } while (0) 134#define deactivate_mm(tsk,mm) do { } while (0)
134#define activate_mm(prev,next) switch_mm(prev, next, NULL) 135#define activate_mm(prev,next) switch_mm(prev, next, NULL)
135 136
136/*
137 * We are inserting a "fake" vma for the user-accessible vector page so
138 * gdb and friends can get to it through ptrace and /proc/<pid>/mem.
139 * But we also want to remove it before the generic code gets to see it
140 * during process exit or the unmapping of it would cause total havoc.
141 * (the macro is used as remove_vma() is static to mm/mmap.c)
142 */
143#define arch_exit_mmap(mm) \
144do { \
145 struct vm_area_struct *high_vma = find_vma(mm, 0xffff0000); \
146 if (high_vma) { \
147 BUG_ON(high_vma->vm_next); /* it should be last */ \
148 if (high_vma->vm_prev) \
149 high_vma->vm_prev->vm_next = NULL; \
150 else \
151 mm->mmap = NULL; \
152 rb_erase(&high_vma->vm_rb, &mm->mm_rb); \
153 mm->mmap_cache = NULL; \
154 mm->map_count--; \
155 remove_vma(high_vma); \
156 } \
157} while (0)
158
159static inline void arch_dup_mmap(struct mm_struct *oldmm,
160 struct mm_struct *mm)
161{
162}
163
164#endif 137#endif
diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index c0efdd60966f..19c48deda70f 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -17,4 +17,63 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
17#define ARM_OPCODE_CONDTEST_PASS 1 17#define ARM_OPCODE_CONDTEST_PASS 1
18#define ARM_OPCODE_CONDTEST_UNCOND 2 18#define ARM_OPCODE_CONDTEST_UNCOND 2
19 19
20
21/*
22 * Opcode byteswap helpers
23 *
24 * These macros help with converting instructions between a canonical integer
25 * format and in-memory representation, in an endianness-agnostic manner.
26 *
27 * __mem_to_opcode_*() convert from in-memory representation to canonical form.
28 * __opcode_to_mem_*() convert from canonical form to in-memory representation.
29 *
30 *
31 * Canonical instruction representation:
32 *
33 * ARM: 0xKKLLMMNN
34 * Thumb 16-bit: 0x0000KKLL, where KK < 0xE8
35 * Thumb 32-bit: 0xKKLLMMNN, where KK >= 0xE8
36 *
37 * There is no way to distinguish an ARM instruction in canonical representation
38 * from a Thumb instruction (just as these cannot be distinguished in memory).
39 * Where this distinction is important, it needs to be tracked separately.
40 *
41 * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not
42 * represent any valid Thumb-2 instruction. For this range,
43 * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false.
44 */
45
46#ifndef __ASSEMBLY__
47
48#include <linux/types.h>
49#include <linux/swab.h>
50
51#ifdef CONFIG_CPU_ENDIAN_BE8
52#define __opcode_to_mem_arm(x) swab32(x)
53#define __opcode_to_mem_thumb16(x) swab16(x)
54#define __opcode_to_mem_thumb32(x) swahb32(x)
55#else
56#define __opcode_to_mem_arm(x) ((u32)(x))
57#define __opcode_to_mem_thumb16(x) ((u16)(x))
58#define __opcode_to_mem_thumb32(x) swahw32(x)
59#endif
60
61#define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x)
62#define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x)
63#define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x)
64
65/* Operations specific to Thumb opcodes */
66
67/* Instruction size checks: */
68#define __opcode_is_thumb32(x) ((u32)(x) >= 0xE8000000UL)
69#define __opcode_is_thumb16(x) ((u32)(x) < 0xE800UL)
70
71/* Operations to construct or split 32-bit Thumb instructions: */
72#define __opcode_thumb32_first(x) ((u16)((x) >> 16))
73#define __opcode_thumb32_second(x) ((u16)(x))
74#define __opcode_thumb32_compose(first, second) \
75 (((u32)(u16)(first) << 16) | (u32)(u16)(second))
76
77#endif /* __ASSEMBLY__ */
78
20#endif /* __ASM_ARM_OPCODES_H */ 79#endif /* __ASM_ARM_OPCODES_H */
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index 97b440c25c58..5838361c48b3 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -151,6 +151,8 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
151#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) 151#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
152extern void copy_page(void *to, const void *from); 152extern void copy_page(void *to, const void *from);
153 153
154#define __HAVE_ARCH_GATE_AREA 1
155
154#ifdef CONFIG_ARM_LPAE 156#ifdef CONFIG_ARM_LPAE
155#include <asm/pgtable-3level-types.h> 157#include <asm/pgtable-3level-types.h>
156#else 158#else
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index 7523340afb8a..00cbe10a50e3 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -22,6 +22,7 @@ enum arm_perf_pmu_ids {
22 ARM_PERF_PMU_ID_CA9, 22 ARM_PERF_PMU_ID_CA9,
23 ARM_PERF_PMU_ID_CA5, 23 ARM_PERF_PMU_ID_CA5,
24 ARM_PERF_PMU_ID_CA15, 24 ARM_PERF_PMU_ID_CA15,
25 ARM_PERF_PMU_ID_CA7,
25 ARM_NUM_PMU_IDS, 26 ARM_NUM_PMU_IDS,
26}; 27};
27 28
diff --git a/arch/arm/include/asm/posix_types.h b/arch/arm/include/asm/posix_types.h
index 2446d23bfdbf..efdf99045d87 100644
--- a/arch/arm/include/asm/posix_types.h
+++ b/arch/arm/include/asm/posix_types.h
@@ -19,59 +19,22 @@
19 * assume GCC is being used. 19 * assume GCC is being used.
20 */ 20 */
21 21
22typedef unsigned long __kernel_ino_t;
23typedef unsigned short __kernel_mode_t; 22typedef unsigned short __kernel_mode_t;
23#define __kernel_mode_t __kernel_mode_t
24
24typedef unsigned short __kernel_nlink_t; 25typedef unsigned short __kernel_nlink_t;
25typedef long __kernel_off_t; 26#define __kernel_nlink_t __kernel_nlink_t
26typedef int __kernel_pid_t; 27
27typedef unsigned short __kernel_ipc_pid_t; 28typedef unsigned short __kernel_ipc_pid_t;
29#define __kernel_ipc_pid_t __kernel_ipc_pid_t
30
28typedef unsigned short __kernel_uid_t; 31typedef unsigned short __kernel_uid_t;
29typedef unsigned short __kernel_gid_t; 32typedef unsigned short __kernel_gid_t;
30typedef unsigned int __kernel_size_t; 33#define __kernel_uid_t __kernel_uid_t
31typedef int __kernel_ssize_t;
32typedef int __kernel_ptrdiff_t;
33typedef long __kernel_time_t;
34typedef long __kernel_suseconds_t;
35typedef long __kernel_clock_t;
36typedef int __kernel_timer_t;
37typedef int __kernel_clockid_t;
38typedef int __kernel_daddr_t;
39typedef char * __kernel_caddr_t;
40typedef unsigned short __kernel_uid16_t;
41typedef unsigned short __kernel_gid16_t;
42typedef unsigned int __kernel_uid32_t;
43typedef unsigned int __kernel_gid32_t;
44 34
45typedef unsigned short __kernel_old_uid_t;
46typedef unsigned short __kernel_old_gid_t;
47typedef unsigned short __kernel_old_dev_t; 35typedef unsigned short __kernel_old_dev_t;
36#define __kernel_old_dev_t __kernel_old_dev_t
48 37
49#ifdef __GNUC__ 38#include <asm-generic/posix_types.h>
50typedef long long __kernel_loff_t;
51#endif
52
53typedef struct {
54 int val[2];
55} __kernel_fsid_t;
56
57#if defined(__KERNEL__)
58
59#undef __FD_SET
60#define __FD_SET(fd, fdsetp) \
61 (((fd_set *)(fdsetp))->fds_bits[(fd) >> 5] |= (1<<((fd) & 31)))
62
63#undef __FD_CLR
64#define __FD_CLR(fd, fdsetp) \
65 (((fd_set *)(fdsetp))->fds_bits[(fd) >> 5] &= ~(1<<((fd) & 31)))
66
67#undef __FD_ISSET
68#define __FD_ISSET(fd, fdsetp) \
69 ((((fd_set *)(fdsetp))->fds_bits[(fd) >> 5] & (1<<((fd) & 31))) != 0)
70
71#undef __FD_ZERO
72#define __FD_ZERO(fdsetp) \
73 (memset (fdsetp, 0, sizeof (*(fd_set *)(fdsetp))))
74
75#endif
76 39
77#endif 40#endif
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index cb8d638924fd..5ac8d3d3e025 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -22,7 +22,6 @@
22#include <asm/hw_breakpoint.h> 22#include <asm/hw_breakpoint.h>
23#include <asm/ptrace.h> 23#include <asm/ptrace.h>
24#include <asm/types.h> 24#include <asm/types.h>
25#include <asm/system.h>
26 25
27#ifdef __KERNEL__ 26#ifdef __KERNEL__
28#define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \ 27#define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \
@@ -56,7 +55,6 @@ struct thread_struct {
56#define start_thread(regs,pc,sp) \ 55#define start_thread(regs,pc,sp) \
57({ \ 56({ \
58 unsigned long *stack = (unsigned long *)sp; \ 57 unsigned long *stack = (unsigned long *)sp; \
59 set_fs(USER_DS); \
60 memset(regs->uregs, 0, sizeof(regs->uregs)); \ 58 memset(regs->uregs, 0, sizeof(regs->uregs)); \
61 if (current->personality & ADDR_LIMIT_32BIT) \ 59 if (current->personality & ADDR_LIMIT_32BIT) \
62 regs->ARM_cpsr = USR_MODE; \ 60 regs->ARM_cpsr = USR_MODE; \
@@ -90,6 +88,8 @@ unsigned long get_wchan(struct task_struct *p);
90#define cpu_relax() barrier() 88#define cpu_relax() barrier()
91#endif 89#endif
92 90
91void cpu_idle_wait(void);
92
93/* 93/*
94 * Create a new kernel thread 94 * Create a new kernel thread
95 */ 95 */
diff --git a/arch/arm/include/asm/prom.h b/arch/arm/include/asm/prom.h
index ee0363307918..aeae9c609df4 100644
--- a/arch/arm/include/asm/prom.h
+++ b/arch/arm/include/asm/prom.h
@@ -13,8 +13,6 @@
13 13
14#ifdef CONFIG_OF 14#ifdef CONFIG_OF
15 15
16#include <asm/irq.h>
17
18extern struct machine_desc *setup_machine_fdt(unsigned int dt_phys); 16extern struct machine_desc *setup_machine_fdt(unsigned int dt_phys);
19extern void arm_dt_memblock_reserve(void); 17extern void arm_dt_memblock_reserve(void);
20 18
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index ef9ffba97ad8..0f01f4677bd2 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -18,11 +18,28 @@
18#define TWD_TIMER_CONTROL_PERIODIC (1 << 1) 18#define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
19#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2) 19#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
20 20
21struct clock_event_device; 21#include <linux/ioport.h>
22 22
23extern void __iomem *twd_base; 23struct twd_local_timer {
24 struct resource res[2];
25};
24 26
25void twd_timer_setup(struct clock_event_device *); 27#define DEFINE_TWD_LOCAL_TIMER(name,base,irq) \
26void twd_timer_stop(struct clock_event_device *); 28struct twd_local_timer name __initdata = { \
29 .res = { \
30 DEFINE_RES_MEM(base, 0x10), \
31 DEFINE_RES_IRQ(irq), \
32 }, \
33};
34
35int twd_local_timer_register(struct twd_local_timer *);
36
37#ifdef CONFIG_HAVE_ARM_TWD
38void twd_local_timer_of_register(void);
39#else
40static inline void twd_local_timer_of_register(void)
41{
42}
43#endif
27 44
28#endif 45#endif
diff --git a/arch/arm/include/asm/switch_to.h b/arch/arm/include/asm/switch_to.h
new file mode 100644
index 000000000000..fa09e6b49bf1
--- /dev/null
+++ b/arch/arm/include/asm/switch_to.h
@@ -0,0 +1,18 @@
1#ifndef __ASM_ARM_SWITCH_TO_H
2#define __ASM_ARM_SWITCH_TO_H
3
4#include <linux/thread_info.h>
5
6/*
7 * switch_to(prev, next) should switch from task `prev' to `next'
8 * `prev' will never be the same as `next'. schedule() itself
9 * contains the memory barrier to tell GCC not to cache `current'.
10 */
11extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
12
13#define switch_to(prev,next,last) \
14do { \
15 last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \
16} while (0)
17
18#endif /* __ASM_ARM_SWITCH_TO_H */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 424aa458c487..74542c52f9be 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -1,544 +1,8 @@
1#ifndef __ASM_ARM_SYSTEM_H 1/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
2#define __ASM_ARM_SYSTEM_H 2#include <asm/barrier.h>
3 3#include <asm/compiler.h>
4#ifdef __KERNEL__ 4#include <asm/cmpxchg.h>
5 5#include <asm/exec.h>
6#define CPU_ARCH_UNKNOWN 0 6#include <asm/switch_to.h>
7#define CPU_ARCH_ARMv3 1 7#include <asm/system_info.h>
8#define CPU_ARCH_ARMv4 2 8#include <asm/system_misc.h>
9#define CPU_ARCH_ARMv4T 3
10#define CPU_ARCH_ARMv5 4
11#define CPU_ARCH_ARMv5T 5
12#define CPU_ARCH_ARMv5TE 6
13#define CPU_ARCH_ARMv5TEJ 7
14#define CPU_ARCH_ARMv6 8
15#define CPU_ARCH_ARMv7 9
16
17/*
18 * CR1 bits (CP#15 CR1)
19 */
20#define CR_M (1 << 0) /* MMU enable */
21#define CR_A (1 << 1) /* Alignment abort enable */
22#define CR_C (1 << 2) /* Dcache enable */
23#define CR_W (1 << 3) /* Write buffer enable */
24#define CR_P (1 << 4) /* 32-bit exception handler */
25#define CR_D (1 << 5) /* 32-bit data address range */
26#define CR_L (1 << 6) /* Implementation defined */
27#define CR_B (1 << 7) /* Big endian */
28#define CR_S (1 << 8) /* System MMU protection */
29#define CR_R (1 << 9) /* ROM MMU protection */
30#define CR_F (1 << 10) /* Implementation defined */
31#define CR_Z (1 << 11) /* Implementation defined */
32#define CR_I (1 << 12) /* Icache enable */
33#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
34#define CR_RR (1 << 14) /* Round Robin cache replacement */
35#define CR_L4 (1 << 15) /* LDR pc can set T bit */
36#define CR_DT (1 << 16)
37#define CR_IT (1 << 18)
38#define CR_ST (1 << 19)
39#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
40#define CR_U (1 << 22) /* Unaligned access operation */
41#define CR_XP (1 << 23) /* Extended page tables */
42#define CR_VE (1 << 24) /* Vectored interrupts */
43#define CR_EE (1 << 25) /* Exception (Big) Endian */
44#define CR_TRE (1 << 28) /* TEX remap enable */
45#define CR_AFE (1 << 29) /* Access flag enable */
46#define CR_TE (1 << 30) /* Thumb exception enable */
47
48/*
49 * This is used to ensure the compiler did actually allocate the register we
50 * asked it for some inline assembly sequences. Apparently we can't trust
51 * the compiler from one version to another so a bit of paranoia won't hurt.
52 * This string is meant to be concatenated with the inline asm string and
53 * will cause compilation to stop on mismatch.
54 * (for details, see gcc PR 15089)
55 */
56#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
57
58#ifndef __ASSEMBLY__
59
60#include <linux/compiler.h>
61#include <linux/linkage.h>
62#include <linux/irqflags.h>
63
64#include <asm/outercache.h>
65
66struct thread_info;
67struct task_struct;
68
69/* information about the system we're running on */
70extern unsigned int system_rev;
71extern unsigned int system_serial_low;
72extern unsigned int system_serial_high;
73extern unsigned int mem_fclk_21285;
74
75struct pt_regs;
76
77void die(const char *msg, struct pt_regs *regs, int err);
78
79struct siginfo;
80void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
81 unsigned long err, unsigned long trap);
82
83#ifdef CONFIG_ARM_LPAE
84#define FAULT_CODE_ALIGNMENT 33
85#define FAULT_CODE_DEBUG 34
86#else
87#define FAULT_CODE_ALIGNMENT 1
88#define FAULT_CODE_DEBUG 2
89#endif
90
91void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
92 struct pt_regs *),
93 int sig, int code, const char *name);
94
95void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int,
96 struct pt_regs *),
97 int sig, int code, const char *name);
98
99#define xchg(ptr,x) \
100 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
101
102extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
103
104struct mm_struct;
105extern void show_pte(struct mm_struct *mm, unsigned long addr);
106extern void __show_regs(struct pt_regs *);
107
108extern int __pure cpu_architecture(void);
109extern void cpu_init(void);
110
111void soft_restart(unsigned long);
112extern void (*arm_pm_restart)(char str, const char *cmd);
113extern void (*arm_pm_idle)(void);
114
115#define UDBG_UNDEFINED (1 << 0)
116#define UDBG_SYSCALL (1 << 1)
117#define UDBG_BADABORT (1 << 2)
118#define UDBG_SEGV (1 << 3)
119#define UDBG_BUS (1 << 4)
120
121extern unsigned int user_debug;
122
123#if __LINUX_ARM_ARCH__ >= 4
124#define vectors_high() (cr_alignment & CR_V)
125#else
126#define vectors_high() (0)
127#endif
128
129#if __LINUX_ARM_ARCH__ >= 7 || \
130 (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
131#define sev() __asm__ __volatile__ ("sev" : : : "memory")
132#define wfe() __asm__ __volatile__ ("wfe" : : : "memory")
133#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
134#endif
135
136#if __LINUX_ARM_ARCH__ >= 7
137#define isb() __asm__ __volatile__ ("isb" : : : "memory")
138#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
139#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
140#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
141#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
142 : : "r" (0) : "memory")
143#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
144 : : "r" (0) : "memory")
145#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
146 : : "r" (0) : "memory")
147#elif defined(CONFIG_CPU_FA526)
148#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
149 : : "r" (0) : "memory")
150#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
151 : : "r" (0) : "memory")
152#define dmb() __asm__ __volatile__ ("" : : : "memory")
153#else
154#define isb() __asm__ __volatile__ ("" : : : "memory")
155#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
156 : : "r" (0) : "memory")
157#define dmb() __asm__ __volatile__ ("" : : : "memory")
158#endif
159
160#ifdef CONFIG_ARCH_HAS_BARRIERS
161#include <mach/barriers.h>
162#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
163#define mb() do { dsb(); outer_sync(); } while (0)
164#define rmb() dsb()
165#define wmb() mb()
166#else
167#include <asm/memory.h>
168#define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
169#define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
170#define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
171#endif
172
173#ifndef CONFIG_SMP
174#define smp_mb() barrier()
175#define smp_rmb() barrier()
176#define smp_wmb() barrier()
177#else
178#define smp_mb() dmb()
179#define smp_rmb() dmb()
180#define smp_wmb() dmb()
181#endif
182
183#define read_barrier_depends() do { } while(0)
184#define smp_read_barrier_depends() do { } while(0)
185
186#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
187#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
188
189extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
190extern unsigned long cr_alignment; /* defined in entry-armv.S */
191
192static inline unsigned int get_cr(void)
193{
194 unsigned int val;
195 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
196 return val;
197}
198
199static inline void set_cr(unsigned int val)
200{
201 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
202 : : "r" (val) : "cc");
203 isb();
204}
205
206#ifndef CONFIG_SMP
207extern void adjust_cr(unsigned long mask, unsigned long set);
208#endif
209
210#define CPACC_FULL(n) (3 << (n * 2))
211#define CPACC_SVC(n) (1 << (n * 2))
212#define CPACC_DISABLE(n) (0 << (n * 2))
213
214static inline unsigned int get_copro_access(void)
215{
216 unsigned int val;
217 asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
218 : "=r" (val) : : "cc");
219 return val;
220}
221
222static inline void set_copro_access(unsigned int val)
223{
224 asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
225 : : "r" (val) : "cc");
226 isb();
227}
228
229/*
230 * switch_mm() may do a full cache flush over the context switch,
231 * so enable interrupts over the context switch to avoid high
232 * latency.
233 */
234#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
235
236/*
237 * switch_to(prev, next) should switch from task `prev' to `next'
238 * `prev' will never be the same as `next'. schedule() itself
239 * contains the memory barrier to tell GCC not to cache `current'.
240 */
241extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
242
243#define switch_to(prev,next,last) \
244do { \
245 last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \
246} while (0)
247
248#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
249/*
250 * On the StrongARM, "swp" is terminally broken since it bypasses the
251 * cache totally. This means that the cache becomes inconsistent, and,
252 * since we use normal loads/stores as well, this is really bad.
253 * Typically, this causes oopsen in filp_close, but could have other,
254 * more disastrous effects. There are two work-arounds:
255 * 1. Disable interrupts and emulate the atomic swap
256 * 2. Clean the cache, perform atomic swap, flush the cache
257 *
258 * We choose (1) since its the "easiest" to achieve here and is not
259 * dependent on the processor type.
260 *
261 * NOTE that this solution won't work on an SMP system, so explcitly
262 * forbid it here.
263 */
264#define swp_is_buggy
265#endif
266
267static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
268{
269 extern void __bad_xchg(volatile void *, int);
270 unsigned long ret;
271#ifdef swp_is_buggy
272 unsigned long flags;
273#endif
274#if __LINUX_ARM_ARCH__ >= 6
275 unsigned int tmp;
276#endif
277
278 smp_mb();
279
280 switch (size) {
281#if __LINUX_ARM_ARCH__ >= 6
282 case 1:
283 asm volatile("@ __xchg1\n"
284 "1: ldrexb %0, [%3]\n"
285 " strexb %1, %2, [%3]\n"
286 " teq %1, #0\n"
287 " bne 1b"
288 : "=&r" (ret), "=&r" (tmp)
289 : "r" (x), "r" (ptr)
290 : "memory", "cc");
291 break;
292 case 4:
293 asm volatile("@ __xchg4\n"
294 "1: ldrex %0, [%3]\n"
295 " strex %1, %2, [%3]\n"
296 " teq %1, #0\n"
297 " bne 1b"
298 : "=&r" (ret), "=&r" (tmp)
299 : "r" (x), "r" (ptr)
300 : "memory", "cc");
301 break;
302#elif defined(swp_is_buggy)
303#ifdef CONFIG_SMP
304#error SMP is not supported on this platform
305#endif
306 case 1:
307 raw_local_irq_save(flags);
308 ret = *(volatile unsigned char *)ptr;
309 *(volatile unsigned char *)ptr = x;
310 raw_local_irq_restore(flags);
311 break;
312
313 case 4:
314 raw_local_irq_save(flags);
315 ret = *(volatile unsigned long *)ptr;
316 *(volatile unsigned long *)ptr = x;
317 raw_local_irq_restore(flags);
318 break;
319#else
320 case 1:
321 asm volatile("@ __xchg1\n"
322 " swpb %0, %1, [%2]"
323 : "=&r" (ret)
324 : "r" (x), "r" (ptr)
325 : "memory", "cc");
326 break;
327 case 4:
328 asm volatile("@ __xchg4\n"
329 " swp %0, %1, [%2]"
330 : "=&r" (ret)
331 : "r" (x), "r" (ptr)
332 : "memory", "cc");
333 break;
334#endif
335 default:
336 __bad_xchg(ptr, size), ret = 0;
337 break;
338 }
339 smp_mb();
340
341 return ret;
342}
343
344extern void disable_hlt(void);
345extern void enable_hlt(void);
346
347void cpu_idle_wait(void);
348
349#include <asm-generic/cmpxchg-local.h>
350
351#if __LINUX_ARM_ARCH__ < 6
352/* min ARCH < ARMv6 */
353
354#ifdef CONFIG_SMP
355#error "SMP is not supported on this platform"
356#endif
357
358/*
359 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
360 * them available.
361 */
362#define cmpxchg_local(ptr, o, n) \
363 ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
364 (unsigned long)(n), sizeof(*(ptr))))
365#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
366
367#ifndef CONFIG_SMP
368#include <asm-generic/cmpxchg.h>
369#endif
370
371#else /* min ARCH >= ARMv6 */
372
373extern void __bad_cmpxchg(volatile void *ptr, int size);
374
375/*
376 * cmpxchg only support 32-bits operands on ARMv6.
377 */
378
379static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
380 unsigned long new, int size)
381{
382 unsigned long oldval, res;
383
384 switch (size) {
385#ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */
386 case 1:
387 do {
388 asm volatile("@ __cmpxchg1\n"
389 " ldrexb %1, [%2]\n"
390 " mov %0, #0\n"
391 " teq %1, %3\n"
392 " strexbeq %0, %4, [%2]\n"
393 : "=&r" (res), "=&r" (oldval)
394 : "r" (ptr), "Ir" (old), "r" (new)
395 : "memory", "cc");
396 } while (res);
397 break;
398 case 2:
399 do {
400 asm volatile("@ __cmpxchg1\n"
401 " ldrexh %1, [%2]\n"
402 " mov %0, #0\n"
403 " teq %1, %3\n"
404 " strexheq %0, %4, [%2]\n"
405 : "=&r" (res), "=&r" (oldval)
406 : "r" (ptr), "Ir" (old), "r" (new)
407 : "memory", "cc");
408 } while (res);
409 break;
410#endif
411 case 4:
412 do {
413 asm volatile("@ __cmpxchg4\n"
414 " ldrex %1, [%2]\n"
415 " mov %0, #0\n"
416 " teq %1, %3\n"
417 " strexeq %0, %4, [%2]\n"
418 : "=&r" (res), "=&r" (oldval)
419 : "r" (ptr), "Ir" (old), "r" (new)
420 : "memory", "cc");
421 } while (res);
422 break;
423 default:
424 __bad_cmpxchg(ptr, size);
425 oldval = 0;
426 }
427
428 return oldval;
429}
430
431static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
432 unsigned long new, int size)
433{
434 unsigned long ret;
435
436 smp_mb();
437 ret = __cmpxchg(ptr, old, new, size);
438 smp_mb();
439
440 return ret;
441}
442
443#define cmpxchg(ptr,o,n) \
444 ((__typeof__(*(ptr)))__cmpxchg_mb((ptr), \
445 (unsigned long)(o), \
446 (unsigned long)(n), \
447 sizeof(*(ptr))))
448
449static inline unsigned long __cmpxchg_local(volatile void *ptr,
450 unsigned long old,
451 unsigned long new, int size)
452{
453 unsigned long ret;
454
455 switch (size) {
456#ifdef CONFIG_CPU_V6 /* min ARCH == ARMv6 */
457 case 1:
458 case 2:
459 ret = __cmpxchg_local_generic(ptr, old, new, size);
460 break;
461#endif
462 default:
463 ret = __cmpxchg(ptr, old, new, size);
464 }
465
466 return ret;
467}
468
469#define cmpxchg_local(ptr,o,n) \
470 ((__typeof__(*(ptr)))__cmpxchg_local((ptr), \
471 (unsigned long)(o), \
472 (unsigned long)(n), \
473 sizeof(*(ptr))))
474
475#ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */
476
477/*
478 * Note : ARMv7-M (currently unsupported by Linux) does not support
479 * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
480 * not be allowed to use __cmpxchg64.
481 */
482static inline unsigned long long __cmpxchg64(volatile void *ptr,
483 unsigned long long old,
484 unsigned long long new)
485{
486 register unsigned long long oldval asm("r0");
487 register unsigned long long __old asm("r2") = old;
488 register unsigned long long __new asm("r4") = new;
489 unsigned long res;
490
491 do {
492 asm volatile(
493 " @ __cmpxchg8\n"
494 " ldrexd %1, %H1, [%2]\n"
495 " mov %0, #0\n"
496 " teq %1, %3\n"
497 " teqeq %H1, %H3\n"
498 " strexdeq %0, %4, %H4, [%2]\n"
499 : "=&r" (res), "=&r" (oldval)
500 : "r" (ptr), "Ir" (__old), "r" (__new)
501 : "memory", "cc");
502 } while (res);
503
504 return oldval;
505}
506
507static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
508 unsigned long long old,
509 unsigned long long new)
510{
511 unsigned long long ret;
512
513 smp_mb();
514 ret = __cmpxchg64(ptr, old, new);
515 smp_mb();
516
517 return ret;
518}
519
520#define cmpxchg64(ptr,o,n) \
521 ((__typeof__(*(ptr)))__cmpxchg64_mb((ptr), \
522 (unsigned long long)(o), \
523 (unsigned long long)(n)))
524
525#define cmpxchg64_local(ptr,o,n) \
526 ((__typeof__(*(ptr)))__cmpxchg64((ptr), \
527 (unsigned long long)(o), \
528 (unsigned long long)(n)))
529
530#else /* min ARCH = ARMv6 */
531
532#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
533
534#endif
535
536#endif /* __LINUX_ARM_ARCH__ >= 6 */
537
538#endif /* __ASSEMBLY__ */
539
540#define arch_align_stack(x) (x)
541
542#endif /* __KERNEL__ */
543
544#endif
diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
new file mode 100644
index 000000000000..dfd386d0c022
--- /dev/null
+++ b/arch/arm/include/asm/system_info.h
@@ -0,0 +1,27 @@
1#ifndef __ASM_ARM_SYSTEM_INFO_H
2#define __ASM_ARM_SYSTEM_INFO_H
3
4#define CPU_ARCH_UNKNOWN 0
5#define CPU_ARCH_ARMv3 1
6#define CPU_ARCH_ARMv4 2
7#define CPU_ARCH_ARMv4T 3
8#define CPU_ARCH_ARMv5 4
9#define CPU_ARCH_ARMv5T 5
10#define CPU_ARCH_ARMv5TE 6
11#define CPU_ARCH_ARMv5TEJ 7
12#define CPU_ARCH_ARMv6 8
13#define CPU_ARCH_ARMv7 9
14
15#ifndef __ASSEMBLY__
16
17/* information about the system we're running on */
18extern unsigned int system_rev;
19extern unsigned int system_serial_low;
20extern unsigned int system_serial_high;
21extern unsigned int mem_fclk_21285;
22
23extern int __pure cpu_architecture(void);
24
25#endif /* !__ASSEMBLY__ */
26
27#endif /* __ASM_ARM_SYSTEM_INFO_H */
diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
new file mode 100644
index 000000000000..5a85f148b607
--- /dev/null
+++ b/arch/arm/include/asm/system_misc.h
@@ -0,0 +1,29 @@
1#ifndef __ASM_ARM_SYSTEM_MISC_H
2#define __ASM_ARM_SYSTEM_MISC_H
3
4#ifndef __ASSEMBLY__
5
6#include <linux/compiler.h>
7#include <linux/linkage.h>
8#include <linux/irqflags.h>
9
10extern void cpu_init(void);
11
12void soft_restart(unsigned long);
13extern void (*arm_pm_restart)(char str, const char *cmd);
14extern void (*arm_pm_idle)(void);
15
16#define UDBG_UNDEFINED (1 << 0)
17#define UDBG_SYSCALL (1 << 1)
18#define UDBG_BADABORT (1 << 2)
19#define UDBG_SEGV (1 << 3)
20#define UDBG_BUS (1 << 4)
21
22extern unsigned int user_debug;
23
24extern void disable_hlt(void);
25extern void enable_hlt(void);
26
27#endif /* !__ASSEMBLY__ */
28
29#endif /* __ASM_ARM_SYSTEM_MISC_H */
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 02b2f8203982..85fe61e73202 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -318,6 +318,21 @@ extern struct cpu_tlb_fns cpu_tlb;
318 318
319#define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f))) 319#define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
320 320
321#define __tlb_op(f, insnarg, arg) \
322 do { \
323 if (always_tlb_flags & (f)) \
324 asm("mcr " insnarg \
325 : : "r" (arg) : "cc"); \
326 else if (possible_tlb_flags & (f)) \
327 asm("tst %1, %2\n\t" \
328 "mcrne " insnarg \
329 : : "r" (arg), "r" (__tlb_flag), "Ir" (f) \
330 : "cc"); \
331 } while (0)
332
333#define tlb_op(f, regs, arg) __tlb_op(f, "p15, 0, %0, " regs, arg)
334#define tlb_l2_op(f, regs, arg) __tlb_op(f, "p15, 1, %0, " regs, arg)
335
321static inline void local_flush_tlb_all(void) 336static inline void local_flush_tlb_all(void)
322{ 337{
323 const int zero = 0; 338 const int zero = 0;
@@ -326,16 +341,11 @@ static inline void local_flush_tlb_all(void)
326 if (tlb_flag(TLB_WB)) 341 if (tlb_flag(TLB_WB))
327 dsb(); 342 dsb();
328 343
329 if (tlb_flag(TLB_V3_FULL)) 344 tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);
330 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc"); 345 tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero);
331 if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL)) 346 tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero);
332 asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc"); 347 tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero);
333 if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL)) 348 tlb_op(TLB_V7_UIS_FULL, "c8, c3, 0", zero);
334 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
335 if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
336 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
337 if (tlb_flag(TLB_V7_UIS_FULL))
338 asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
339 349
340 if (tlb_flag(TLB_BARRIER)) { 350 if (tlb_flag(TLB_BARRIER)) {
341 dsb(); 351 dsb();
@@ -352,29 +362,23 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
352 if (tlb_flag(TLB_WB)) 362 if (tlb_flag(TLB_WB))
353 dsb(); 363 dsb();
354 364
355 if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) { 365 if (possible_tlb_flags & (TLB_V3_FULL|TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) {
356 if (tlb_flag(TLB_V3_FULL)) 366 if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
357 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc"); 367 tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);
358 if (tlb_flag(TLB_V4_U_FULL)) 368 tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);
359 asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc"); 369 tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);
360 if (tlb_flag(TLB_V4_D_FULL)) 370 tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
361 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc"); 371 }
362 if (tlb_flag(TLB_V4_I_FULL)) 372 put_cpu();
363 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
364 } 373 }
365 put_cpu(); 374
366 375 tlb_op(TLB_V6_U_ASID, "c8, c7, 2", asid);
367 if (tlb_flag(TLB_V6_U_ASID)) 376 tlb_op(TLB_V6_D_ASID, "c8, c6, 2", asid);
368 asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc"); 377 tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid);
369 if (tlb_flag(TLB_V6_D_ASID))
370 asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
371 if (tlb_flag(TLB_V6_I_ASID))
372 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
373 if (tlb_flag(TLB_V7_UIS_ASID))
374#ifdef CONFIG_ARM_ERRATA_720789 378#ifdef CONFIG_ARM_ERRATA_720789
375 asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc"); 379 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", zero);
376#else 380#else
377 asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc"); 381 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", asid);
378#endif 382#endif
379 383
380 if (tlb_flag(TLB_BARRIER)) 384 if (tlb_flag(TLB_BARRIER))
@@ -392,30 +396,23 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
392 if (tlb_flag(TLB_WB)) 396 if (tlb_flag(TLB_WB))
393 dsb(); 397 dsb();
394 398
395 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { 399 if (possible_tlb_flags & (TLB_V3_PAGE|TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) &&
396 if (tlb_flag(TLB_V3_PAGE)) 400 cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
397 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc"); 401 tlb_op(TLB_V3_PAGE, "c6, c0, 0", uaddr);
398 if (tlb_flag(TLB_V4_U_PAGE)) 402 tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr);
399 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc"); 403 tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr);
400 if (tlb_flag(TLB_V4_D_PAGE)) 404 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr);
401 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
402 if (tlb_flag(TLB_V4_I_PAGE))
403 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
404 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL)) 405 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
405 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); 406 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
406 } 407 }
407 408
408 if (tlb_flag(TLB_V6_U_PAGE)) 409 tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", uaddr);
409 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc"); 410 tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", uaddr);
410 if (tlb_flag(TLB_V6_D_PAGE)) 411 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr);
411 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
412 if (tlb_flag(TLB_V6_I_PAGE))
413 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
414 if (tlb_flag(TLB_V7_UIS_PAGE))
415#ifdef CONFIG_ARM_ERRATA_720789 412#ifdef CONFIG_ARM_ERRATA_720789
416 asm("mcr p15, 0, %0, c8, c3, 3" : : "r" (uaddr & PAGE_MASK) : "cc"); 413 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 3", uaddr & PAGE_MASK);
417#else 414#else
418 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc"); 415 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", uaddr);
419#endif 416#endif
420 417
421 if (tlb_flag(TLB_BARRIER)) 418 if (tlb_flag(TLB_BARRIER))
@@ -432,25 +429,17 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
432 if (tlb_flag(TLB_WB)) 429 if (tlb_flag(TLB_WB))
433 dsb(); 430 dsb();
434 431
435 if (tlb_flag(TLB_V3_PAGE)) 432 tlb_op(TLB_V3_PAGE, "c6, c0, 0", kaddr);
436 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc"); 433 tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr);
437 if (tlb_flag(TLB_V4_U_PAGE)) 434 tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr);
438 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc"); 435 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr);
439 if (tlb_flag(TLB_V4_D_PAGE))
440 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
441 if (tlb_flag(TLB_V4_I_PAGE))
442 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
443 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL)) 436 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
444 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); 437 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
445 438
446 if (tlb_flag(TLB_V6_U_PAGE)) 439 tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", kaddr);
447 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc"); 440 tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", kaddr);
448 if (tlb_flag(TLB_V6_D_PAGE)) 441 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr);
449 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc"); 442 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", kaddr);
450 if (tlb_flag(TLB_V6_I_PAGE))
451 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
452 if (tlb_flag(TLB_V7_UIS_PAGE))
453 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc");
454 443
455 if (tlb_flag(TLB_BARRIER)) { 444 if (tlb_flag(TLB_BARRIER)) {
456 dsb(); 445 dsb();
@@ -475,13 +464,8 @@ static inline void flush_pmd_entry(void *pmd)
475{ 464{
476 const unsigned int __tlb_flag = __cpu_tlb_flags; 465 const unsigned int __tlb_flag = __cpu_tlb_flags;
477 466
478 if (tlb_flag(TLB_DCLEAN)) 467 tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd);
479 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" 468 tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd);
480 : : "r" (pmd) : "cc");
481
482 if (tlb_flag(TLB_L2CLEAN_FR))
483 asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd"
484 : : "r" (pmd) : "cc");
485 469
486 if (tlb_flag(TLB_WB)) 470 if (tlb_flag(TLB_WB))
487 dsb(); 471 dsb();
@@ -491,15 +475,11 @@ static inline void clean_pmd_entry(void *pmd)
491{ 475{
492 const unsigned int __tlb_flag = __cpu_tlb_flags; 476 const unsigned int __tlb_flag = __cpu_tlb_flags;
493 477
494 if (tlb_flag(TLB_DCLEAN)) 478 tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd);
495 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" 479 tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd);
496 : : "r" (pmd) : "cc");
497
498 if (tlb_flag(TLB_L2CLEAN_FR))
499 asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd"
500 : : "r" (pmd) : "cc");
501} 480}
502 481
482#undef tlb_op
503#undef tlb_flag 483#undef tlb_flag
504#undef always_tlb_flags 484#undef always_tlb_flags
505#undef possible_tlb_flags 485#undef possible_tlb_flags
diff --git a/arch/arm/include/asm/traps.h b/arch/arm/include/asm/traps.h
index 5b29a6673625..f555bb3664dc 100644
--- a/arch/arm/include/asm/traps.h
+++ b/arch/arm/include/asm/traps.h
@@ -46,7 +46,7 @@ static inline int in_exception_text(unsigned long ptr)
46 return in ? : __in_irqentry_text(ptr); 46 return in ? : __in_irqentry_text(ptr);
47} 47}
48 48
49extern void __init early_trap_init(void); 49extern void __init early_trap_init(void *);
50extern void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame); 50extern void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame);
51extern void ptrace_break(struct task_struct *tsk, struct pt_regs *regs); 51extern void ptrace_break(struct task_struct *tsk, struct pt_regs *regs);
52 52
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 2958976d867b..71f6536d17ac 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -16,8 +16,8 @@
16#include <asm/errno.h> 16#include <asm/errno.h>
17#include <asm/memory.h> 17#include <asm/memory.h>
18#include <asm/domain.h> 18#include <asm/domain.h>
19#include <asm/system.h>
20#include <asm/unified.h> 19#include <asm/unified.h>
20#include <asm/compiler.h>
21 21
22#define VERIFY_READ 0 22#define VERIFY_READ 0
23#define VERIFY_WRITE 1 23#define VERIFY_WRITE 1
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-30 17:57:11 -0500