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-rw-r--r--arch/arm/include/asm/Kbuild17
-rw-r--r--arch/arm/include/asm/auxvec.h4
-rw-r--r--arch/arm/include/asm/bitsperlong.h1
-rw-r--r--arch/arm/include/asm/bug.h55
-rw-r--r--arch/arm/include/asm/cachetype.h5
-rw-r--r--arch/arm/include/asm/cputime.h6
-rw-r--r--arch/arm/include/asm/cputype.h6
-rw-r--r--arch/arm/include/asm/device.h8
-rw-r--r--arch/arm/include/asm/dma-mapping.h9
-rw-r--r--arch/arm/include/asm/dma.h6
-rw-r--r--arch/arm/include/asm/ecard.h1
-rw-r--r--arch/arm/include/asm/emergency-restart.h6
-rw-r--r--arch/arm/include/asm/entry-macro-multi.S7
-rw-r--r--arch/arm/include/asm/errno.h6
-rw-r--r--arch/arm/include/asm/exception.h19
-rw-r--r--arch/arm/include/asm/futex.h34
-rw-r--r--arch/arm/include/asm/gpio.h19
-rw-r--r--arch/arm/include/asm/hardirq.h3
-rw-r--r--arch/arm/include/asm/hardware/cache-l2x0.h51
-rw-r--r--arch/arm/include/asm/hardware/entry-macro-gic.S19
-rw-r--r--arch/arm/include/asm/hardware/gic.h9
-rw-r--r--arch/arm/include/asm/hardware/iop3xx-gpio.h2
-rw-r--r--arch/arm/include/asm/hardware/it8152.h2
-rw-r--r--arch/arm/include/asm/hw_breakpoint.h2
-rw-r--r--arch/arm/include/asm/io.h40
-rw-r--r--arch/arm/include/asm/ioctl.h1
-rw-r--r--arch/arm/include/asm/irq_regs.h1
-rw-r--r--arch/arm/include/asm/kdebug.h1
-rw-r--r--arch/arm/include/asm/local.h1
-rw-r--r--arch/arm/include/asm/local64.h1
-rw-r--r--arch/arm/include/asm/localtimer.h20
-rw-r--r--arch/arm/include/asm/mach/arch.h5
-rw-r--r--arch/arm/include/asm/mach/map.h1
-rw-r--r--arch/arm/include/asm/memory.h25
-rw-r--r--arch/arm/include/asm/mmu.h4
-rw-r--r--arch/arm/include/asm/module.h4
-rw-r--r--arch/arm/include/asm/outercache.h7
-rw-r--r--arch/arm/include/asm/page.h42
-rw-r--r--arch/arm/include/asm/percpu.h6
-rw-r--r--arch/arm/include/asm/pgalloc.h4
-rw-r--r--arch/arm/include/asm/pgtable-2level-hwdef.h93
-rw-r--r--arch/arm/include/asm/pgtable-2level-types.h67
-rw-r--r--arch/arm/include/asm/pgtable-2level.h143
-rw-r--r--arch/arm/include/asm/pgtable-hwdef.h77
-rw-r--r--arch/arm/include/asm/pgtable.h144
-rw-r--r--arch/arm/include/asm/pmu.h93
-rw-r--r--arch/arm/include/asm/poll.h1
-rw-r--r--arch/arm/include/asm/proc-fns.h8
-rw-r--r--arch/arm/include/asm/resource.h6
-rw-r--r--arch/arm/include/asm/sections.h1
-rw-r--r--arch/arm/include/asm/siginfo.h6
-rw-r--r--arch/arm/include/asm/sizes.h21
-rw-r--r--arch/arm/include/asm/smp.h16
-rw-r--r--arch/arm/include/asm/smp_twd.h2
-rw-r--r--arch/arm/include/asm/suspend.h17
-rw-r--r--arch/arm/include/asm/system.h11
-rw-r--r--arch/arm/include/asm/tlbflush.h4
-rw-r--r--arch/arm/include/asm/topology.h33
-rw-r--r--arch/arm/include/asm/unistd.h4
59 files changed, 724 insertions, 483 deletions
diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index 6550db3aa5c7..960abceb8e14 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -1,3 +1,20 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2 2
3header-y += hwcap.h 3header-y += hwcap.h
4
5generic-y += auxvec.h
6generic-y += bitsperlong.h
7generic-y += cputime.h
8generic-y += emergency-restart.h
9generic-y += errno.h
10generic-y += ioctl.h
11generic-y += irq_regs.h
12generic-y += kdebug.h
13generic-y += local.h
14generic-y += local64.h
15generic-y += percpu.h
16generic-y += poll.h
17generic-y += resource.h
18generic-y += sections.h
19generic-y += siginfo.h
20generic-y += sizes.h
diff --git a/arch/arm/include/asm/auxvec.h b/arch/arm/include/asm/auxvec.h
deleted file mode 100644
index c0536f6b29a7..000000000000
--- a/arch/arm/include/asm/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
1#ifndef __ASMARM_AUXVEC_H
2#define __ASMARM_AUXVEC_H
3
4#endif
diff --git a/arch/arm/include/asm/bitsperlong.h b/arch/arm/include/asm/bitsperlong.h
deleted file mode 100644
index 6dc0bb0c13b2..000000000000
--- a/arch/arm/include/asm/bitsperlong.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/bitsperlong.h>
diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h
index 4d88425a4169..9abe7a07d5ac 100644
--- a/arch/arm/include/asm/bug.h
+++ b/arch/arm/include/asm/bug.h
@@ -3,21 +3,58 @@
3 3
4 4
5#ifdef CONFIG_BUG 5#ifdef CONFIG_BUG
6#ifdef CONFIG_DEBUG_BUGVERBOSE
7extern void __bug(const char *file, int line) __attribute__((noreturn));
8
9/* give file/line information */
10#define BUG() __bug(__FILE__, __LINE__)
11 6
7/*
8 * Use a suitable undefined instruction to use for ARM/Thumb2 bug handling.
9 * We need to be careful not to conflict with those used by other modules and
10 * the register_undef_hook() system.
11 */
12#ifdef CONFIG_THUMB2_KERNEL
13#define BUG_INSTR_VALUE 0xde02
14#define BUG_INSTR_TYPE ".hword "
12#else 15#else
16#define BUG_INSTR_VALUE 0xe7f001f2
17#define BUG_INSTR_TYPE ".word "
18#endif
13 19
14/* this just causes an oops */
15#define BUG() do { *(int *)0 = 0; } while (1)
16 20
17#endif 21#define BUG() _BUG(__FILE__, __LINE__, BUG_INSTR_VALUE)
22#define _BUG(file, line, value) __BUG(file, line, value)
23
24#ifdef CONFIG_DEBUG_BUGVERBOSE
25
26/*
27 * The extra indirection is to ensure that the __FILE__ string comes through
28 * OK. Many version of gcc do not support the asm %c parameter which would be
29 * preferable to this unpleasantness. We use mergeable string sections to
30 * avoid multiple copies of the string appearing in the kernel image.
31 */
32
33#define __BUG(__file, __line, __value) \
34do { \
35 BUILD_BUG_ON(sizeof(struct bug_entry) != 12); \
36 asm volatile("1:\t" BUG_INSTR_TYPE #__value "\n" \
37 ".pushsection .rodata.str, \"aMS\", %progbits, 1\n" \
38 "2:\t.asciz " #__file "\n" \
39 ".popsection\n" \
40 ".pushsection __bug_table,\"a\"\n" \
41 "3:\t.word 1b, 2b\n" \
42 "\t.hword " #__line ", 0\n" \
43 ".popsection"); \
44 unreachable(); \
45} while (0)
46
47#else /* not CONFIG_DEBUG_BUGVERBOSE */
48
49#define __BUG(__file, __line, __value) \
50do { \
51 asm volatile(BUG_INSTR_TYPE #__value); \
52 unreachable(); \
53} while (0)
54#endif /* CONFIG_DEBUG_BUGVERBOSE */
18 55
19#define HAVE_ARCH_BUG 56#define HAVE_ARCH_BUG
20#endif 57#endif /* CONFIG_BUG */
21 58
22#include <asm-generic/bug.h> 59#include <asm-generic/bug.h>
23 60
diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h
index c023db09fcc1..7ea78144ae22 100644
--- a/arch/arm/include/asm/cachetype.h
+++ b/arch/arm/include/asm/cachetype.h
@@ -7,6 +7,7 @@
7#define CACHEID_VIPT (CACHEID_VIPT_ALIASING|CACHEID_VIPT_NONALIASING) 7#define CACHEID_VIPT (CACHEID_VIPT_ALIASING|CACHEID_VIPT_NONALIASING)
8#define CACHEID_ASID_TAGGED (1 << 3) 8#define CACHEID_ASID_TAGGED (1 << 3)
9#define CACHEID_VIPT_I_ALIASING (1 << 4) 9#define CACHEID_VIPT_I_ALIASING (1 << 4)
10#define CACHEID_PIPT (1 << 5)
10 11
11extern unsigned int cacheid; 12extern unsigned int cacheid;
12 13
@@ -16,6 +17,7 @@ extern unsigned int cacheid;
16#define cache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_ALIASING) 17#define cache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_ALIASING)
17#define icache_is_vivt_asid_tagged() cacheid_is(CACHEID_ASID_TAGGED) 18#define icache_is_vivt_asid_tagged() cacheid_is(CACHEID_ASID_TAGGED)
18#define icache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_I_ALIASING) 19#define icache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_I_ALIASING)
20#define icache_is_pipt() cacheid_is(CACHEID_PIPT)
19 21
20/* 22/*
21 * __LINUX_ARM_ARCH__ is the minimum supported CPU architecture 23 * __LINUX_ARM_ARCH__ is the minimum supported CPU architecture
@@ -26,7 +28,8 @@ extern unsigned int cacheid;
26#if __LINUX_ARM_ARCH__ >= 7 28#if __LINUX_ARM_ARCH__ >= 7
27#define __CACHEID_ARCH_MIN (CACHEID_VIPT_NONALIASING |\ 29#define __CACHEID_ARCH_MIN (CACHEID_VIPT_NONALIASING |\
28 CACHEID_ASID_TAGGED |\ 30 CACHEID_ASID_TAGGED |\
29 CACHEID_VIPT_I_ALIASING) 31 CACHEID_VIPT_I_ALIASING |\
32 CACHEID_PIPT)
30#elif __LINUX_ARM_ARCH__ >= 6 33#elif __LINUX_ARM_ARCH__ >= 6
31#define __CACHEID_ARCH_MIN (~CACHEID_VIVT) 34#define __CACHEID_ARCH_MIN (~CACHEID_VIVT)
32#else 35#else
diff --git a/arch/arm/include/asm/cputime.h b/arch/arm/include/asm/cputime.h
deleted file mode 100644
index 3a8002a5fec7..000000000000
--- a/arch/arm/include/asm/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ARM_CPUTIME_H
2#define __ARM_CPUTIME_H
3
4#include <asm-generic/cputime.h>
5
6#endif /* __ARM_CPUTIME_H */
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index cd4458f64171..cb47d28cbe1f 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -8,6 +8,7 @@
8#define CPUID_CACHETYPE 1 8#define CPUID_CACHETYPE 1
9#define CPUID_TCM 2 9#define CPUID_TCM 2
10#define CPUID_TLBTYPE 3 10#define CPUID_TLBTYPE 3
11#define CPUID_MPIDR 5
11 12
12#define CPUID_EXT_PFR0 "c1, 0" 13#define CPUID_EXT_PFR0 "c1, 0"
13#define CPUID_EXT_PFR1 "c1, 1" 14#define CPUID_EXT_PFR1 "c1, 1"
@@ -70,6 +71,11 @@ static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
70 return read_cpuid(CPUID_TCM); 71 return read_cpuid(CPUID_TCM);
71} 72}
72 73
74static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
75{
76 return read_cpuid(CPUID_MPIDR);
77}
78
73/* 79/*
74 * Intel's XScale3 core supports some v6 features (supersections, L2) 80 * Intel's XScale3 core supports some v6 features (supersections, L2)
75 * but advertises itself as v5 as it does not support the v6 ISA. For 81 * but advertises itself as v5 as it does not support the v6 ISA. For
diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h
index 9f390ce335cb..7aa368003b05 100644
--- a/arch/arm/include/asm/device.h
+++ b/arch/arm/include/asm/device.h
@@ -10,9 +10,17 @@ struct dev_archdata {
10#ifdef CONFIG_DMABOUNCE 10#ifdef CONFIG_DMABOUNCE
11 struct dmabounce_device_info *dmabounce; 11 struct dmabounce_device_info *dmabounce;
12#endif 12#endif
13#ifdef CONFIG_IOMMU_API
14 void *iommu; /* private IOMMU data */
15#endif
13}; 16};
14 17
18struct omap_device;
19
15struct pdev_archdata { 20struct pdev_archdata {
21#ifdef CONFIG_ARCH_OMAP
22 struct omap_device *od;
23#endif
16}; 24};
17 25
18#endif 26#endif
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 7a21d0bf7134..cb3b7c981c4b 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -32,7 +32,7 @@ static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr)
32 32
33static inline void *dma_to_virt(struct device *dev, dma_addr_t addr) 33static inline void *dma_to_virt(struct device *dev, dma_addr_t addr)
34{ 34{
35 return (void *)__bus_to_virt(addr); 35 return (void *)__bus_to_virt((unsigned long)addr);
36} 36}
37 37
38static inline dma_addr_t virt_to_dma(struct device *dev, void *addr) 38static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
@@ -205,6 +205,13 @@ extern void *dma_alloc_writecombine(struct device *, size_t, dma_addr_t *,
205int dma_mmap_writecombine(struct device *, struct vm_area_struct *, 205int dma_mmap_writecombine(struct device *, struct vm_area_struct *,
206 void *, dma_addr_t, size_t); 206 void *, dma_addr_t, size_t);
207 207
208/*
209 * This can be called during boot to increase the size of the consistent
210 * DMA region above it's default value of 2MB. It must be called before the
211 * memory allocator is initialised, i.e. before any core_initcall.
212 */
213extern void __init init_consistent_dma_size(unsigned long size);
214
208 215
209#ifdef CONFIG_DMABOUNCE 216#ifdef CONFIG_DMABOUNCE
210/* 217/*
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 628670e9d7c9..69a5b0b6455c 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -34,18 +34,18 @@
34#define DMA_MODE_CASCADE 0xc0 34#define DMA_MODE_CASCADE 0xc0
35#define DMA_AUTOINIT 0x10 35#define DMA_AUTOINIT 0x10
36 36
37extern spinlock_t dma_spin_lock; 37extern raw_spinlock_t dma_spin_lock;
38 38
39static inline unsigned long claim_dma_lock(void) 39static inline unsigned long claim_dma_lock(void)
40{ 40{
41 unsigned long flags; 41 unsigned long flags;
42 spin_lock_irqsave(&dma_spin_lock, flags); 42 raw_spin_lock_irqsave(&dma_spin_lock, flags);
43 return flags; 43 return flags;
44} 44}
45 45
46static inline void release_dma_lock(unsigned long flags) 46static inline void release_dma_lock(unsigned long flags)
47{ 47{
48 spin_unlock_irqrestore(&dma_spin_lock, flags); 48 raw_spin_unlock_irqrestore(&dma_spin_lock, flags);
49} 49}
50 50
51/* Clear the 'DMA Pointer Flip Flop'. 51/* Clear the 'DMA Pointer Flip Flop'.
diff --git a/arch/arm/include/asm/ecard.h b/arch/arm/include/asm/ecard.h
index 29f2610efc70..eaea14676d57 100644
--- a/arch/arm/include/asm/ecard.h
+++ b/arch/arm/include/asm/ecard.h
@@ -161,7 +161,6 @@ struct expansion_card {
161 161
162 /* Private internal data */ 162 /* Private internal data */
163 const char *card_desc; /* Card description */ 163 const char *card_desc; /* Card description */
164 CONST unsigned int podaddr; /* Base Linux address for card */
165 CONST loader_t loader; /* loader program */ 164 CONST loader_t loader; /* loader program */
166 u64 dma_mask; 165 u64 dma_mask;
167}; 166};
diff --git a/arch/arm/include/asm/emergency-restart.h b/arch/arm/include/asm/emergency-restart.h
deleted file mode 100644
index 108d8c48e42e..000000000000
--- a/arch/arm/include/asm/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_EMERGENCY_RESTART_H
2#define _ASM_EMERGENCY_RESTART_H
3
4#include <asm-generic/emergency-restart.h>
5
6#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/arm/include/asm/entry-macro-multi.S b/arch/arm/include/asm/entry-macro-multi.S
index 2f1e2098dfe7..88d61815f0c0 100644
--- a/arch/arm/include/asm/entry-macro-multi.S
+++ b/arch/arm/include/asm/entry-macro-multi.S
@@ -25,13 +25,6 @@
25 movne r1, sp 25 movne r1, sp
26 adrne lr, BSYM(1b) 26 adrne lr, BSYM(1b)
27 bne do_IPI 27 bne do_IPI
28
29#ifdef CONFIG_LOCAL_TIMERS
30 test_for_ltirq r0, r2, r6, lr
31 movne r0, sp
32 adrne lr, BSYM(1b)
33 bne do_local_timer
34#endif
35#endif 28#endif
369997: 299997:
37 .endm 30 .endm
diff --git a/arch/arm/include/asm/errno.h b/arch/arm/include/asm/errno.h
deleted file mode 100644
index 6e60f0612bb6..000000000000
--- a/arch/arm/include/asm/errno.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ARM_ERRNO_H
2#define _ARM_ERRNO_H
3
4#include <asm-generic/errno.h>
5
6#endif
diff --git a/arch/arm/include/asm/exception.h b/arch/arm/include/asm/exception.h
new file mode 100644
index 000000000000..5abaf5bbd985
--- /dev/null
+++ b/arch/arm/include/asm/exception.h
@@ -0,0 +1,19 @@
1/*
2 * Annotations for marking C functions as exception handlers.
3 *
4 * These should only be used for C functions that are called from the low
5 * level exception entry code and not any intervening C code.
6 */
7#ifndef __ASM_ARM_EXCEPTION_H
8#define __ASM_ARM_EXCEPTION_H
9
10#include <linux/ftrace.h>
11
12#define __exception __attribute__((section(".exception.text")))
13#ifdef CONFIG_FUNCTION_GRAPH_TRACER
14#define __exception_irq_entry __irq_entry
15#else
16#define __exception_irq_entry __exception
17#endif
18
19#endif /* __ASM_ARM_EXCEPTION_H */
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 8c73900da9ed..253cc86318bf 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -25,17 +25,17 @@
25 25
26#ifdef CONFIG_SMP 26#ifdef CONFIG_SMP
27 27
28#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 28#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
29 smp_mb(); \ 29 smp_mb(); \
30 __asm__ __volatile__( \ 30 __asm__ __volatile__( \
31 "1: ldrex %1, [%2]\n" \ 31 "1: ldrex %1, [%3]\n" \
32 " " insn "\n" \ 32 " " insn "\n" \
33 "2: strex %1, %0, [%2]\n" \ 33 "2: strex %2, %0, [%3]\n" \
34 " teq %1, #0\n" \ 34 " teq %2, #0\n" \
35 " bne 1b\n" \ 35 " bne 1b\n" \
36 " mov %0, #0\n" \ 36 " mov %0, #0\n" \
37 __futex_atomic_ex_table("%4") \ 37 __futex_atomic_ex_table("%5") \
38 : "=&r" (ret), "=&r" (oldval) \ 38 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
39 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ 39 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
40 : "cc", "memory") 40 : "cc", "memory")
41 41
@@ -73,14 +73,14 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
73#include <linux/preempt.h> 73#include <linux/preempt.h>
74#include <asm/domain.h> 74#include <asm/domain.h>
75 75
76#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 76#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
77 __asm__ __volatile__( \ 77 __asm__ __volatile__( \
78 "1: " T(ldr) " %1, [%2]\n" \ 78 "1: " T(ldr) " %1, [%3]\n" \
79 " " insn "\n" \ 79 " " insn "\n" \
80 "2: " T(str) " %0, [%2]\n" \ 80 "2: " T(str) " %0, [%3]\n" \
81 " mov %0, #0\n" \ 81 " mov %0, #0\n" \
82 __futex_atomic_ex_table("%4") \ 82 __futex_atomic_ex_table("%5") \
83 : "=&r" (ret), "=&r" (oldval) \ 83 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
84 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ 84 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
85 : "cc", "memory") 85 : "cc", "memory")
86 86
@@ -117,7 +117,7 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
117 int cmp = (encoded_op >> 24) & 15; 117 int cmp = (encoded_op >> 24) & 15;
118 int oparg = (encoded_op << 8) >> 20; 118 int oparg = (encoded_op << 8) >> 20;
119 int cmparg = (encoded_op << 20) >> 20; 119 int cmparg = (encoded_op << 20) >> 20;
120 int oldval = 0, ret; 120 int oldval = 0, ret, tmp;
121 121
122 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) 122 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
123 oparg = 1 << oparg; 123 oparg = 1 << oparg;
@@ -129,19 +129,19 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
129 129
130 switch (op) { 130 switch (op) {
131 case FUTEX_OP_SET: 131 case FUTEX_OP_SET:
132 __futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg); 132 __futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg);
133 break; 133 break;
134 case FUTEX_OP_ADD: 134 case FUTEX_OP_ADD:
135 __futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg); 135 __futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
136 break; 136 break;
137 case FUTEX_OP_OR: 137 case FUTEX_OP_OR:
138 __futex_atomic_op("orr %0, %1, %3", ret, oldval, uaddr, oparg); 138 __futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
139 break; 139 break;
140 case FUTEX_OP_ANDN: 140 case FUTEX_OP_ANDN:
141 __futex_atomic_op("and %0, %1, %3", ret, oldval, uaddr, ~oparg); 141 __futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
142 break; 142 break;
143 case FUTEX_OP_XOR: 143 case FUTEX_OP_XOR:
144 __futex_atomic_op("eor %0, %1, %3", ret, oldval, uaddr, oparg); 144 __futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
145 break; 145 break;
146 default: 146 default:
147 ret = -ENOSYS; 147 ret = -ENOSYS;
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index 166a7a3e2840..11ad0bfbb0ad 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -4,4 +4,23 @@
4/* not all ARM platforms necessarily support this API ... */ 4/* not all ARM platforms necessarily support this API ... */
5#include <mach/gpio.h> 5#include <mach/gpio.h>
6 6
7#ifndef __ARM_GPIOLIB_COMPLEX
8/* Note: this may rely upon the value of ARCH_NR_GPIOS set in mach/gpio.h */
9#include <asm-generic/gpio.h>
10
11/* The trivial gpiolib dispatchers */
12#define gpio_get_value __gpio_get_value
13#define gpio_set_value __gpio_set_value
14#define gpio_cansleep __gpio_cansleep
15#endif
16
17/*
18 * Provide a default gpio_to_irq() which should satisfy every case.
19 * However, some platforms want to do this differently, so allow them
20 * to override it.
21 */
22#ifndef gpio_to_irq
23#define gpio_to_irq __gpio_to_irq
24#endif
25
7#endif /* _ARCH_ARM_GPIO_H */ 26#endif /* _ARCH_ARM_GPIO_H */
diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h
index 89ad1805e579..ddf07a92a6c8 100644
--- a/arch/arm/include/asm/hardirq.h
+++ b/arch/arm/include/asm/hardirq.h
@@ -9,9 +9,6 @@
9 9
10typedef struct { 10typedef struct {
11 unsigned int __softirq_pending; 11 unsigned int __softirq_pending;
12#ifdef CONFIG_LOCAL_TIMERS
13 unsigned int local_timer_irqs;
14#endif
15#ifdef CONFIG_SMP 12#ifdef CONFIG_SMP
16 unsigned int ipi_irqs[NR_IPI]; 13 unsigned int ipi_irqs[NR_IPI];
17#endif 14#endif
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index bfa706ffd968..434edccdf7f3 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -45,8 +45,15 @@
45#define L2X0_CLEAN_INV_LINE_PA 0x7F0 45#define L2X0_CLEAN_INV_LINE_PA 0x7F0
46#define L2X0_CLEAN_INV_LINE_IDX 0x7F8 46#define L2X0_CLEAN_INV_LINE_IDX 0x7F8
47#define L2X0_CLEAN_INV_WAY 0x7FC 47#define L2X0_CLEAN_INV_WAY 0x7FC
48#define L2X0_LOCKDOWN_WAY_D 0x900 48/*
49#define L2X0_LOCKDOWN_WAY_I 0x904 49 * The lockdown registers repeat 8 times for L310, the L210 has only one
50 * D and one I lockdown register at 0x0900 and 0x0904.
51 */
52#define L2X0_LOCKDOWN_WAY_D_BASE 0x900
53#define L2X0_LOCKDOWN_WAY_I_BASE 0x904
54#define L2X0_LOCKDOWN_STRIDE 0x08
55#define L2X0_ADDR_FILTER_START 0xC00
56#define L2X0_ADDR_FILTER_END 0xC04
50#define L2X0_TEST_OPERATION 0xF00 57#define L2X0_TEST_OPERATION 0xF00
51#define L2X0_LINE_DATA 0xF10 58#define L2X0_LINE_DATA 0xF10
52#define L2X0_LINE_TAG 0xF30 59#define L2X0_LINE_TAG 0xF30
@@ -60,8 +67,23 @@
60#define L2X0_CACHE_ID_PART_MASK (0xf << 6) 67#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
61#define L2X0_CACHE_ID_PART_L210 (1 << 6) 68#define L2X0_CACHE_ID_PART_L210 (1 << 6)
62#define L2X0_CACHE_ID_PART_L310 (3 << 6) 69#define L2X0_CACHE_ID_PART_L310 (3 << 6)
70#define L2X0_CACHE_ID_RTL_MASK 0x3f
71#define L2X0_CACHE_ID_RTL_R0P0 0x0
72#define L2X0_CACHE_ID_RTL_R1P0 0x2
73#define L2X0_CACHE_ID_RTL_R2P0 0x4
74#define L2X0_CACHE_ID_RTL_R3P0 0x5
75#define L2X0_CACHE_ID_RTL_R3P1 0x6
76#define L2X0_CACHE_ID_RTL_R3P2 0x8
63 77
64#define L2X0_AUX_CTRL_MASK 0xc0000fff 78#define L2X0_AUX_CTRL_MASK 0xc0000fff
79#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
80#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7
81#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3
82#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3)
83#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6
84#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6)
85#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9
86#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9)
65#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16 87#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16
66#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 88#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17
67#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17) 89#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
@@ -72,8 +94,33 @@
72#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29 94#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29
73#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30 95#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30
74 96
97#define L2X0_LATENCY_CTRL_SETUP_SHIFT 0
98#define L2X0_LATENCY_CTRL_RD_SHIFT 4
99#define L2X0_LATENCY_CTRL_WR_SHIFT 8
100
101#define L2X0_ADDR_FILTER_EN 1
102
75#ifndef __ASSEMBLY__ 103#ifndef __ASSEMBLY__
76extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); 104extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
105extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask);
106
107struct l2x0_regs {
108 unsigned long phy_base;
109 unsigned long aux_ctrl;
110 /*
111 * Whether the following registers need to be saved/restored
112 * depends on platform
113 */
114 unsigned long tag_latency;
115 unsigned long data_latency;
116 unsigned long filter_start;
117 unsigned long filter_end;
118 unsigned long prefetch_ctrl;
119 unsigned long pwr_ctrl;
120};
121
122extern struct l2x0_regs l2x0_saved_regs;
123
77#endif 124#endif
78 125
79#endif 126#endif
diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S
index c115b82fe80a..74ebc803904d 100644
--- a/arch/arm/include/asm/hardware/entry-macro-gic.S
+++ b/arch/arm/include/asm/hardware/entry-macro-gic.S
@@ -22,15 +22,11 @@
22 * interrupt controller spec. To wit: 22 * interrupt controller spec. To wit:
23 * 23 *
24 * Interrupts 0-15 are IPI 24 * Interrupts 0-15 are IPI
25 * 16-28 are reserved 25 * 16-31 are local. We allow 30 to be used for the watchdog.
26 * 29-31 are local. We allow 30 to be used for the watchdog.
27 * 32-1020 are global 26 * 32-1020 are global
28 * 1021-1022 are reserved 27 * 1021-1022 are reserved
29 * 1023 is "spurious" (no interrupt) 28 * 1023 is "spurious" (no interrupt)
30 * 29 *
31 * For now, we ignore all local interrupts so only return an interrupt if it's
32 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
33 *
34 * A simple read from the controller will tell us the number of the highest 30 * A simple read from the controller will tell us the number of the highest
35 * priority enabled interrupt. We then just need to check whether it is in the 31 * priority enabled interrupt. We then just need to check whether it is in the
36 * valid range for an IRQ (30-1020 inclusive). 32 * valid range for an IRQ (30-1020 inclusive).
@@ -43,7 +39,7 @@
43 39
44 ldr \tmp, =1021 40 ldr \tmp, =1021
45 bic \irqnr, \irqstat, #0x1c00 41 bic \irqnr, \irqstat, #0x1c00
46 cmp \irqnr, #29 42 cmp \irqnr, #15
47 cmpcc \irqnr, \irqnr 43 cmpcc \irqnr, \irqnr
48 cmpne \irqnr, \tmp 44 cmpne \irqnr, \tmp
49 cmpcs \irqnr, \irqnr 45 cmpcs \irqnr, \irqnr
@@ -62,14 +58,3 @@
62 strcc \irqstat, [\base, #GIC_CPU_EOI] 58 strcc \irqstat, [\base, #GIC_CPU_EOI]
63 cmpcs \irqnr, \irqnr 59 cmpcs \irqnr, \irqnr
64 .endm 60 .endm
65
66/* As above, this assumes that irqstat and base are preserved.. */
67
68 .macro test_for_ltirq, irqnr, irqstat, base, tmp
69 bic \irqnr, \irqstat, #0x1c00
70 mov \tmp, #0
71 cmp \irqnr, #29
72 moveq \tmp, #1
73 streq \irqstat, [\base, #GIC_CPU_EOI]
74 cmp \tmp, #0
75 .endm
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 435d3f86c708..14867e12f205 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -40,12 +40,19 @@ void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
40void gic_secondary_init(unsigned int); 40void gic_secondary_init(unsigned int);
41void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); 41void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
42void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); 42void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
43void gic_enable_ppi(unsigned int);
44 43
45struct gic_chip_data { 44struct gic_chip_data {
46 unsigned int irq_offset; 45 unsigned int irq_offset;
47 void __iomem *dist_base; 46 void __iomem *dist_base;
48 void __iomem *cpu_base; 47 void __iomem *cpu_base;
48#ifdef CONFIG_CPU_PM
49 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
50 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
51 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
52 u32 __percpu *saved_ppi_enable;
53 u32 __percpu *saved_ppi_conf;
54#endif
55 unsigned int gic_irqs;
49}; 56};
50#endif 57#endif
51 58
diff --git a/arch/arm/include/asm/hardware/iop3xx-gpio.h b/arch/arm/include/asm/hardware/iop3xx-gpio.h
index b69d972b1f7d..9eda7dc92ad8 100644
--- a/arch/arm/include/asm/hardware/iop3xx-gpio.h
+++ b/arch/arm/include/asm/hardware/iop3xx-gpio.h
@@ -28,6 +28,8 @@
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <asm-generic/gpio.h> 29#include <asm-generic/gpio.h>
30 30
31#define __ARM_GPIOLIB_COMPLEX
32
31#define IOP3XX_N_GPIOS 8 33#define IOP3XX_N_GPIOS 8
32 34
33static inline int gpio_get_value(unsigned gpio) 35static inline int gpio_get_value(unsigned gpio)
diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h
index b3fea38d55c6..43cab498bc27 100644
--- a/arch/arm/include/asm/hardware/it8152.h
+++ b/arch/arm/include/asm/hardware/it8152.h
@@ -9,7 +9,7 @@
9 9
10#ifndef __ASM_HARDWARE_IT8152_H 10#ifndef __ASM_HARDWARE_IT8152_H
11#define __ASM_HARDWARE_IT8152_H 11#define __ASM_HARDWARE_IT8152_H
12extern unsigned long it8152_base_address; 12extern void __iomem *it8152_base_address;
13 13
14#define IT8152_IO_BASE (it8152_base_address + 0x03e00000) 14#define IT8152_IO_BASE (it8152_base_address + 0x03e00000)
15#define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000) 15#define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000)
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
index f389b2704d82..c190bc992f0e 100644
--- a/arch/arm/include/asm/hw_breakpoint.h
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -50,6 +50,7 @@ static inline void decode_ctrl_reg(u32 reg,
50#define ARM_DEBUG_ARCH_V6_1 2 50#define ARM_DEBUG_ARCH_V6_1 2
51#define ARM_DEBUG_ARCH_V7_ECP14 3 51#define ARM_DEBUG_ARCH_V7_ECP14 3
52#define ARM_DEBUG_ARCH_V7_MM 4 52#define ARM_DEBUG_ARCH_V7_MM 4
53#define ARM_DEBUG_ARCH_V7_1 5
53 54
54/* Breakpoint */ 55/* Breakpoint */
55#define ARM_BREAKPOINT_EXECUTE 0 56#define ARM_BREAKPOINT_EXECUTE 0
@@ -57,6 +58,7 @@ static inline void decode_ctrl_reg(u32 reg,
57/* Watchpoints */ 58/* Watchpoints */
58#define ARM_BREAKPOINT_LOAD 1 59#define ARM_BREAKPOINT_LOAD 1
59#define ARM_BREAKPOINT_STORE 2 60#define ARM_BREAKPOINT_STORE 2
61#define ARM_FSR_ACCESS_MASK (1 << 11)
60 62
61/* Privilege Levels */ 63/* Privilege Levels */
62#define ARM_BREAKPOINT_PRIV 1 64#define ARM_BREAKPOINT_PRIV 1
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index d66605dea55a..065d100fa63e 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -80,6 +80,7 @@ extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
80 80
81extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int); 81extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
82extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int); 82extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
83extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached);
83extern void __iounmap(volatile void __iomem *addr); 84extern void __iounmap(volatile void __iomem *addr);
84 85
85/* 86/*
@@ -110,6 +111,27 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
110#include <mach/io.h> 111#include <mach/io.h>
111 112
112/* 113/*
114 * This is the limit of PC card/PCI/ISA IO space, which is by default
115 * 64K if we have PC card, PCI or ISA support. Otherwise, default to
116 * zero to prevent ISA/PCI drivers claiming IO space (and potentially
117 * oopsing.)
118 *
119 * Only set this larger if you really need inb() et.al. to operate over
120 * a larger address space. Note that SOC_COMMON ioremaps each sockets
121 * IO space area, and so inb() et.al. must be defined to operate as per
122 * readb() et.al. on such platforms.
123 */
124#ifndef IO_SPACE_LIMIT
125#if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE)
126#define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
127#elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD)
128#define IO_SPACE_LIMIT ((resource_size_t)0xffff)
129#else
130#define IO_SPACE_LIMIT ((resource_size_t)0)
131#endif
132#endif
133
134/*
113 * IO port access primitives 135 * IO port access primitives
114 * ------------------------- 136 * -------------------------
115 * 137 *
@@ -189,11 +211,11 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
189 * IO port primitives for more information. 211 * IO port primitives for more information.
190 */ 212 */
191#ifdef __mem_pci 213#ifdef __mem_pci
192#define readb_relaxed(c) ({ u8 __v = __raw_readb(__mem_pci(c)); __v; }) 214#define readb_relaxed(c) ({ u8 __r = __raw_readb(__mem_pci(c)); __r; })
193#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16) \ 215#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
194 __raw_readw(__mem_pci(c))); __v; }) 216 __raw_readw(__mem_pci(c))); __r; })
195#define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32) \ 217#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
196 __raw_readl(__mem_pci(c))); __v; }) 218 __raw_readl(__mem_pci(c))); __r; })
197 219
198#define writeb_relaxed(v,c) ((void)__raw_writeb(v,__mem_pci(c))) 220#define writeb_relaxed(v,c) ((void)__raw_writeb(v,__mem_pci(c)))
199#define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \ 221#define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \
@@ -238,7 +260,7 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
238 * ioremap and friends. 260 * ioremap and friends.
239 * 261 *
240 * ioremap takes a PCI memory address, as specified in 262 * ioremap takes a PCI memory address, as specified in
241 * Documentation/IO-mapping.txt. 263 * Documentation/io-mapping.txt.
242 * 264 *
243 */ 265 */
244#ifndef __arch_ioremap 266#ifndef __arch_ioremap
@@ -260,10 +282,16 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
260#define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; }) 282#define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; })
261#define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; }) 283#define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; })
262 284
285#define ioread16be(p) ({ unsigned int __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
286#define ioread32be(p) ({ unsigned int __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
287
263#define iowrite8(v,p) ({ __iowmb(); (void)__raw_writeb(v, p); }) 288#define iowrite8(v,p) ({ __iowmb(); (void)__raw_writeb(v, p); })
264#define iowrite16(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_le16(v), p); }) 289#define iowrite16(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_le16(v), p); })
265#define iowrite32(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_le32(v), p); }) 290#define iowrite32(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_le32(v), p); })
266 291
292#define iowrite16be(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_be16(v), p); })
293#define iowrite32be(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_be32(v), p); })
294
267#define ioread8_rep(p,d,c) __raw_readsb(p,d,c) 295#define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
268#define ioread16_rep(p,d,c) __raw_readsw(p,d,c) 296#define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
269#define ioread32_rep(p,d,c) __raw_readsl(p,d,c) 297#define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
diff --git a/arch/arm/include/asm/ioctl.h b/arch/arm/include/asm/ioctl.h
deleted file mode 100644
index b279fe06dfe5..000000000000
--- a/arch/arm/include/asm/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/ioctl.h>
diff --git a/arch/arm/include/asm/irq_regs.h b/arch/arm/include/asm/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/arch/arm/include/asm/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/irq_regs.h>
diff --git a/arch/arm/include/asm/kdebug.h b/arch/arm/include/asm/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/arch/arm/include/asm/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/kdebug.h>
diff --git a/arch/arm/include/asm/local.h b/arch/arm/include/asm/local.h
deleted file mode 100644
index c11c530f74d0..000000000000
--- a/arch/arm/include/asm/local.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/local.h>
diff --git a/arch/arm/include/asm/local64.h b/arch/arm/include/asm/local64.h
deleted file mode 100644
index 36c93b5cc239..000000000000
--- a/arch/arm/include/asm/local64.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/local64.h>
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
index 080d74f8128d..c6a18424888e 100644
--- a/arch/arm/include/asm/localtimer.h
+++ b/arch/arm/include/asm/localtimer.h
@@ -10,6 +10,9 @@
10#ifndef __ASM_ARM_LOCALTIMER_H 10#ifndef __ASM_ARM_LOCALTIMER_H
11#define __ASM_ARM_LOCALTIMER_H 11#define __ASM_ARM_LOCALTIMER_H
12 12
13#include <linux/errno.h>
14#include <linux/interrupt.h>
15
13struct clock_event_device; 16struct clock_event_device;
14 17
15/* 18/*
@@ -17,27 +20,20 @@ struct clock_event_device;
17 */ 20 */
18void percpu_timer_setup(void); 21void percpu_timer_setup(void);
19 22
20/*
21 * Called from assembly, this is the local timer IRQ handler
22 */
23asmlinkage void do_local_timer(struct pt_regs *);
24
25
26#ifdef CONFIG_LOCAL_TIMERS 23#ifdef CONFIG_LOCAL_TIMERS
27 24
28#ifdef CONFIG_HAVE_ARM_TWD 25#ifdef CONFIG_HAVE_ARM_TWD
29 26
30#include "smp_twd.h" 27#include "smp_twd.h"
31 28
32#define local_timer_ack() twd_timer_ack() 29#define local_timer_stop(c) twd_timer_stop((c))
33 30
34#else 31#else
35 32
36/* 33/*
37 * Platform provides this to acknowledge a local timer IRQ. 34 * Stop the local timer
38 * Returns true if the local timer IRQ is to be processed.
39 */ 35 */
40int local_timer_ack(void); 36void local_timer_stop(struct clock_event_device *);
41 37
42#endif 38#endif
43 39
@@ -52,6 +48,10 @@ static inline int local_timer_setup(struct clock_event_device *evt)
52{ 48{
53 return -ENXIO; 49 return -ENXIO;
54} 50}
51
52static inline void local_timer_stop(struct clock_event_device *evt)
53{
54}
55#endif 55#endif
56 56
57#endif 57#endif
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 217aa1911dd7..7d19425dd496 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -17,7 +17,7 @@ struct sys_timer;
17struct machine_desc { 17struct machine_desc {
18 unsigned int nr; /* architecture number */ 18 unsigned int nr; /* architecture number */
19 const char *name; /* architecture name */ 19 const char *name; /* architecture name */
20 unsigned long boot_params; /* tagged list */ 20 unsigned long atag_offset; /* tagged list (relative) */
21 const char **dt_compat; /* array of device tree 21 const char **dt_compat; /* array of device tree
22 * 'compatible' strings */ 22 * 'compatible' strings */
23 23
@@ -34,8 +34,7 @@ struct machine_desc {
34 unsigned int reserve_lp1 :1; /* never has lp1 */ 34 unsigned int reserve_lp1 :1; /* never has lp1 */
35 unsigned int reserve_lp2 :1; /* never has lp2 */ 35 unsigned int reserve_lp2 :1; /* never has lp2 */
36 unsigned int soft_reboot :1; /* soft reboot */ 36 unsigned int soft_reboot :1; /* soft reboot */
37 void (*fixup)(struct machine_desc *, 37 void (*fixup)(struct tag *, char **,
38 struct tag *, char **,
39 struct meminfo *); 38 struct meminfo *);
40 void (*reserve)(void);/* reserve mem blocks */ 39 void (*reserve)(void);/* reserve mem blocks */
41 void (*map_io)(void);/* IO mapping function */ 40 void (*map_io)(void);/* IO mapping function */
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index d2fedb5aeb1f..b36f3654bf54 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -29,6 +29,7 @@ struct map_desc {
29#define MT_MEMORY_NONCACHED 11 29#define MT_MEMORY_NONCACHED 11
30#define MT_MEMORY_DTCM 12 30#define MT_MEMORY_DTCM 12
31#define MT_MEMORY_ITCM 13 31#define MT_MEMORY_ITCM 13
32#define MT_MEMORY_SO 14
32 33
33#ifdef CONFIG_MMU 34#ifdef CONFIG_MMU
34extern void iotable_init(struct map_desc *, int); 35extern void iotable_init(struct map_desc *, int);
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index b8de516e600e..a8997d71084e 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -16,9 +16,12 @@
16#include <linux/compiler.h> 16#include <linux/compiler.h>
17#include <linux/const.h> 17#include <linux/const.h>
18#include <linux/types.h> 18#include <linux/types.h>
19#include <mach/memory.h>
20#include <asm/sizes.h> 19#include <asm/sizes.h>
21 20
21#ifdef CONFIG_NEED_MACH_MEMORY_H
22#include <mach/memory.h>
23#endif
24
22/* 25/*
23 * Allow for constants defined here to be used from assembly code 26 * Allow for constants defined here to be used from assembly code
24 * by prepending the UL suffix only with actual C code compilation. 27 * by prepending the UL suffix only with actual C code compilation.
@@ -77,16 +80,7 @@
77 */ 80 */
78#define IOREMAP_MAX_ORDER 24 81#define IOREMAP_MAX_ORDER 24
79 82
80/*
81 * Size of DMA-consistent memory region. Must be multiple of 2M,
82 * between 2MB and 14MB inclusive.
83 */
84#ifndef CONSISTENT_DMA_SIZE
85#define CONSISTENT_DMA_SIZE SZ_2M
86#endif
87
88#define CONSISTENT_END (0xffe00000UL) 83#define CONSISTENT_END (0xffe00000UL)
89#define CONSISTENT_BASE (CONSISTENT_END - CONSISTENT_DMA_SIZE)
90 84
91#else /* CONFIG_MMU */ 85#else /* CONFIG_MMU */
92 86
@@ -160,7 +154,6 @@
160 * so that all we need to do is modify the 8-bit constant field. 154 * so that all we need to do is modify the 8-bit constant field.
161 */ 155 */
162#define __PV_BITS_31_24 0x81000000 156#define __PV_BITS_31_24 0x81000000
163#define __PV_BITS_23_16 0x00810000
164 157
165extern unsigned long __pv_phys_offset; 158extern unsigned long __pv_phys_offset;
166#define PHYS_OFFSET __pv_phys_offset 159#define PHYS_OFFSET __pv_phys_offset
@@ -178,9 +171,6 @@ static inline unsigned long __virt_to_phys(unsigned long x)
178{ 171{
179 unsigned long t; 172 unsigned long t;
180 __pv_stub(x, t, "add", __PV_BITS_31_24); 173 __pv_stub(x, t, "add", __PV_BITS_31_24);
181#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
182 __pv_stub(t, t, "add", __PV_BITS_23_16);
183#endif
184 return t; 174 return t;
185} 175}
186 176
@@ -188,9 +178,6 @@ static inline unsigned long __phys_to_virt(unsigned long x)
188{ 178{
189 unsigned long t; 179 unsigned long t;
190 __pv_stub(x, t, "sub", __PV_BITS_31_24); 180 __pv_stub(x, t, "sub", __PV_BITS_31_24);
191#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
192 __pv_stub(t, t, "sub", __PV_BITS_23_16);
193#endif
194 return t; 181 return t;
195} 182}
196#else 183#else
@@ -200,7 +187,11 @@ static inline unsigned long __phys_to_virt(unsigned long x)
200#endif 187#endif
201 188
202#ifndef PHYS_OFFSET 189#ifndef PHYS_OFFSET
190#ifdef PLAT_PHYS_OFFSET
203#define PHYS_OFFSET PLAT_PHYS_OFFSET 191#define PHYS_OFFSET PLAT_PHYS_OFFSET
192#else
193#define PHYS_OFFSET UL(CONFIG_PHYS_OFFSET)
194#endif
204#endif 195#endif
205 196
206/* 197/*
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index b4ffe9d5b526..14965658a923 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -6,7 +6,7 @@
6typedef struct { 6typedef struct {
7#ifdef CONFIG_CPU_HAS_ASID 7#ifdef CONFIG_CPU_HAS_ASID
8 unsigned int id; 8 unsigned int id;
9 spinlock_t id_lock; 9 raw_spinlock_t id_lock;
10#endif 10#endif
11 unsigned int kvm_seq; 11 unsigned int kvm_seq;
12} mm_context_t; 12} mm_context_t;
@@ -16,7 +16,7 @@ typedef struct {
16 16
17/* init_mm.context.id_lock should be initialized. */ 17/* init_mm.context.id_lock should be initialized. */
18#define INIT_MM_CONTEXT(name) \ 18#define INIT_MM_CONTEXT(name) \
19 .context.id_lock = __SPIN_LOCK_UNLOCKED(name.context.id_lock), 19 .context.id_lock = __RAW_SPIN_LOCK_UNLOCKED(name.context.id_lock),
20#else 20#else
21#define ASID(mm) (0) 21#define ASID(mm) (0)
22#endif 22#endif
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
index 543b44916d2c..6c6809f982f1 100644
--- a/arch/arm/include/asm/module.h
+++ b/arch/arm/include/asm/module.h
@@ -31,11 +31,7 @@ struct mod_arch_specific {
31 31
32/* Add __virt_to_phys patching state as well */ 32/* Add __virt_to_phys patching state as well */
33#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 33#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
34#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
35#define MODULE_ARCH_VERMAGIC_P2V "p2v16 "
36#else
37#define MODULE_ARCH_VERMAGIC_P2V "p2v8 " 34#define MODULE_ARCH_VERMAGIC_P2V "p2v8 "
38#endif
39#else 35#else
40#define MODULE_ARCH_VERMAGIC_P2V "" 36#define MODULE_ARCH_VERMAGIC_P2V ""
41#endif 37#endif
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index d8387437ec5a..53426c66352a 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -34,6 +34,7 @@ struct outer_cache_fns {
34 void (*sync)(void); 34 void (*sync)(void);
35#endif 35#endif
36 void (*set_debug)(unsigned long); 36 void (*set_debug)(unsigned long);
37 void (*resume)(void);
37}; 38};
38 39
39#ifdef CONFIG_OUTER_CACHE 40#ifdef CONFIG_OUTER_CACHE
@@ -74,6 +75,12 @@ static inline void outer_disable(void)
74 outer_cache.disable(); 75 outer_cache.disable();
75} 76}
76 77
78static inline void outer_resume(void)
79{
80 if (outer_cache.resume)
81 outer_cache.resume();
82}
83
77#else 84#else
78 85
79static inline void outer_inv_range(phys_addr_t start, phys_addr_t end) 86static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index ac75d0848889..ca94653f1ecb 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -151,47 +151,7 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
151#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) 151#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
152extern void copy_page(void *to, const void *from); 152extern void copy_page(void *to, const void *from);
153 153
154typedef unsigned long pteval_t; 154#include <asm/pgtable-2level-types.h>
155
156#undef STRICT_MM_TYPECHECKS
157
158#ifdef STRICT_MM_TYPECHECKS
159/*
160 * These are used to make use of C type-checking..
161 */
162typedef struct { pteval_t pte; } pte_t;
163typedef struct { unsigned long pmd; } pmd_t;
164typedef struct { unsigned long pgd[2]; } pgd_t;
165typedef struct { unsigned long pgprot; } pgprot_t;
166
167#define pte_val(x) ((x).pte)
168#define pmd_val(x) ((x).pmd)
169#define pgd_val(x) ((x).pgd[0])
170#define pgprot_val(x) ((x).pgprot)
171
172#define __pte(x) ((pte_t) { (x) } )
173#define __pmd(x) ((pmd_t) { (x) } )
174#define __pgprot(x) ((pgprot_t) { (x) } )
175
176#else
177/*
178 * .. while these make it easier on the compiler
179 */
180typedef pteval_t pte_t;
181typedef unsigned long pmd_t;
182typedef unsigned long pgd_t[2];
183typedef unsigned long pgprot_t;
184
185#define pte_val(x) (x)
186#define pmd_val(x) (x)
187#define pgd_val(x) ((x)[0])
188#define pgprot_val(x) (x)
189
190#define __pte(x) (x)
191#define __pmd(x) (x)
192#define __pgprot(x) (x)
193
194#endif /* STRICT_MM_TYPECHECKS */
195 155
196#endif /* CONFIG_MMU */ 156#endif /* CONFIG_MMU */
197 157
diff --git a/arch/arm/include/asm/percpu.h b/arch/arm/include/asm/percpu.h
deleted file mode 100644
index b4e32d8ec072..000000000000
--- a/arch/arm/include/asm/percpu.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ARM_PERCPU
2#define __ARM_PERCPU
3
4#include <asm-generic/percpu.h>
5
6#endif
diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h
index 22de005f159c..3e08fd3fbb6b 100644
--- a/arch/arm/include/asm/pgalloc.h
+++ b/arch/arm/include/asm/pgalloc.h
@@ -105,9 +105,9 @@ static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
105} 105}
106 106
107static inline void __pmd_populate(pmd_t *pmdp, phys_addr_t pte, 107static inline void __pmd_populate(pmd_t *pmdp, phys_addr_t pte,
108 unsigned long prot) 108 pmdval_t prot)
109{ 109{
110 unsigned long pmdval = (pte + PTE_HWTABLE_OFF) | prot; 110 pmdval_t pmdval = (pte + PTE_HWTABLE_OFF) | prot;
111 pmdp[0] = __pmd(pmdval); 111 pmdp[0] = __pmd(pmdval);
112 pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t)); 112 pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
113 flush_pmd_entry(pmdp); 113 flush_pmd_entry(pmdp);
diff --git a/arch/arm/include/asm/pgtable-2level-hwdef.h b/arch/arm/include/asm/pgtable-2level-hwdef.h
new file mode 100644
index 000000000000..5cfba15cb401
--- /dev/null
+++ b/arch/arm/include/asm/pgtable-2level-hwdef.h
@@ -0,0 +1,93 @@
1/*
2 * arch/arm/include/asm/pgtable-2level-hwdef.h
3 *
4 * Copyright (C) 1995-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef _ASM_PGTABLE_2LEVEL_HWDEF_H
11#define _ASM_PGTABLE_2LEVEL_HWDEF_H
12
13/*
14 * Hardware page table definitions.
15 *
16 * + Level 1 descriptor (PMD)
17 * - common
18 */
19#define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0)
20#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0)
21#define PMD_TYPE_TABLE (_AT(pmdval_t, 1) << 0)
22#define PMD_TYPE_SECT (_AT(pmdval_t, 2) << 0)
23#define PMD_BIT4 (_AT(pmdval_t, 1) << 4)
24#define PMD_DOMAIN(x) (_AT(pmdval_t, (x)) << 5)
25#define PMD_PROTECTION (_AT(pmdval_t, 1) << 9) /* v5 */
26/*
27 * - section
28 */
29#define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2)
30#define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3)
31#define PMD_SECT_XN (_AT(pmdval_t, 1) << 4) /* v6 */
32#define PMD_SECT_AP_WRITE (_AT(pmdval_t, 1) << 10)
33#define PMD_SECT_AP_READ (_AT(pmdval_t, 1) << 11)
34#define PMD_SECT_TEX(x) (_AT(pmdval_t, (x)) << 12) /* v5 */
35#define PMD_SECT_APX (_AT(pmdval_t, 1) << 15) /* v6 */
36#define PMD_SECT_S (_AT(pmdval_t, 1) << 16) /* v6 */
37#define PMD_SECT_nG (_AT(pmdval_t, 1) << 17) /* v6 */
38#define PMD_SECT_SUPER (_AT(pmdval_t, 1) << 18) /* v6 */
39#define PMD_SECT_AF (_AT(pmdval_t, 0))
40
41#define PMD_SECT_UNCACHED (_AT(pmdval_t, 0))
42#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
43#define PMD_SECT_WT (PMD_SECT_CACHEABLE)
44#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
45#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
46#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
47#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2))
48
49/*
50 * - coarse table (not used)
51 */
52
53/*
54 * + Level 2 descriptor (PTE)
55 * - common
56 */
57#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0)
58#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0)
59#define PTE_TYPE_LARGE (_AT(pteval_t, 1) << 0)
60#define PTE_TYPE_SMALL (_AT(pteval_t, 2) << 0)
61#define PTE_TYPE_EXT (_AT(pteval_t, 3) << 0) /* v5 */
62#define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2)
63#define PTE_CACHEABLE (_AT(pteval_t, 1) << 3)
64
65/*
66 * - extended small page/tiny page
67 */
68#define PTE_EXT_XN (_AT(pteval_t, 1) << 0) /* v6 */
69#define PTE_EXT_AP_MASK (_AT(pteval_t, 3) << 4)
70#define PTE_EXT_AP0 (_AT(pteval_t, 1) << 4)
71#define PTE_EXT_AP1 (_AT(pteval_t, 2) << 4)
72#define PTE_EXT_AP_UNO_SRO (_AT(pteval_t, 0) << 4)
73#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
74#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
75#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
76#define PTE_EXT_TEX(x) (_AT(pteval_t, (x)) << 6) /* v5 */
77#define PTE_EXT_APX (_AT(pteval_t, 1) << 9) /* v6 */
78#define PTE_EXT_COHERENT (_AT(pteval_t, 1) << 9) /* XScale3 */
79#define PTE_EXT_SHARED (_AT(pteval_t, 1) << 10) /* v6 */
80#define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* v6 */
81
82/*
83 * - small page
84 */
85#define PTE_SMALL_AP_MASK (_AT(pteval_t, 0xff) << 4)
86#define PTE_SMALL_AP_UNO_SRO (_AT(pteval_t, 0x00) << 4)
87#define PTE_SMALL_AP_UNO_SRW (_AT(pteval_t, 0x55) << 4)
88#define PTE_SMALL_AP_URO_SRW (_AT(pteval_t, 0xaa) << 4)
89#define PTE_SMALL_AP_URW_SRW (_AT(pteval_t, 0xff) << 4)
90
91#define PHYS_MASK (~0UL)
92
93#endif
diff --git a/arch/arm/include/asm/pgtable-2level-types.h b/arch/arm/include/asm/pgtable-2level-types.h
new file mode 100644
index 000000000000..66cb5b0e89c5
--- /dev/null
+++ b/arch/arm/include/asm/pgtable-2level-types.h
@@ -0,0 +1,67 @@
1/*
2 * arch/arm/include/asm/pgtable-2level-types.h
3 *
4 * Copyright (C) 1995-2003 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef _ASM_PGTABLE_2LEVEL_TYPES_H
20#define _ASM_PGTABLE_2LEVEL_TYPES_H
21
22#include <asm/types.h>
23
24typedef u32 pteval_t;
25typedef u32 pmdval_t;
26
27#undef STRICT_MM_TYPECHECKS
28
29#ifdef STRICT_MM_TYPECHECKS
30/*
31 * These are used to make use of C type-checking..
32 */
33typedef struct { pteval_t pte; } pte_t;
34typedef struct { pmdval_t pmd; } pmd_t;
35typedef struct { pmdval_t pgd[2]; } pgd_t;
36typedef struct { pteval_t pgprot; } pgprot_t;
37
38#define pte_val(x) ((x).pte)
39#define pmd_val(x) ((x).pmd)
40#define pgd_val(x) ((x).pgd[0])
41#define pgprot_val(x) ((x).pgprot)
42
43#define __pte(x) ((pte_t) { (x) } )
44#define __pmd(x) ((pmd_t) { (x) } )
45#define __pgprot(x) ((pgprot_t) { (x) } )
46
47#else
48/*
49 * .. while these make it easier on the compiler
50 */
51typedef pteval_t pte_t;
52typedef pmdval_t pmd_t;
53typedef pmdval_t pgd_t[2];
54typedef pteval_t pgprot_t;
55
56#define pte_val(x) (x)
57#define pmd_val(x) (x)
58#define pgd_val(x) ((x)[0])
59#define pgprot_val(x) (x)
60
61#define __pte(x) (x)
62#define __pmd(x) (x)
63#define __pgprot(x) (x)
64
65#endif /* STRICT_MM_TYPECHECKS */
66
67#endif /* _ASM_PGTABLE_2LEVEL_TYPES_H */
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
new file mode 100644
index 000000000000..470457e1cfc5
--- /dev/null
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -0,0 +1,143 @@
1/*
2 * arch/arm/include/asm/pgtable-2level.h
3 *
4 * Copyright (C) 1995-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef _ASM_PGTABLE_2LEVEL_H
11#define _ASM_PGTABLE_2LEVEL_H
12
13/*
14 * Hardware-wise, we have a two level page table structure, where the first
15 * level has 4096 entries, and the second level has 256 entries. Each entry
16 * is one 32-bit word. Most of the bits in the second level entry are used
17 * by hardware, and there aren't any "accessed" and "dirty" bits.
18 *
19 * Linux on the other hand has a three level page table structure, which can
20 * be wrapped to fit a two level page table structure easily - using the PGD
21 * and PTE only. However, Linux also expects one "PTE" table per page, and
22 * at least a "dirty" bit.
23 *
24 * Therefore, we tweak the implementation slightly - we tell Linux that we
25 * have 2048 entries in the first level, each of which is 8 bytes (iow, two
26 * hardware pointers to the second level.) The second level contains two
27 * hardware PTE tables arranged contiguously, preceded by Linux versions
28 * which contain the state information Linux needs. We, therefore, end up
29 * with 512 entries in the "PTE" level.
30 *
31 * This leads to the page tables having the following layout:
32 *
33 * pgd pte
34 * | |
35 * +--------+
36 * | | +------------+ +0
37 * +- - - - + | Linux pt 0 |
38 * | | +------------+ +1024
39 * +--------+ +0 | Linux pt 1 |
40 * | |-----> +------------+ +2048
41 * +- - - - + +4 | h/w pt 0 |
42 * | |-----> +------------+ +3072
43 * +--------+ +8 | h/w pt 1 |
44 * | | +------------+ +4096
45 *
46 * See L_PTE_xxx below for definitions of bits in the "Linux pt", and
47 * PTE_xxx for definitions of bits appearing in the "h/w pt".
48 *
49 * PMD_xxx definitions refer to bits in the first level page table.
50 *
51 * The "dirty" bit is emulated by only granting hardware write permission
52 * iff the page is marked "writable" and "dirty" in the Linux PTE. This
53 * means that a write to a clean page will cause a permission fault, and
54 * the Linux MM layer will mark the page dirty via handle_pte_fault().
55 * For the hardware to notice the permission change, the TLB entry must
56 * be flushed, and ptep_set_access_flags() does that for us.
57 *
58 * The "accessed" or "young" bit is emulated by a similar method; we only
59 * allow accesses to the page if the "young" bit is set. Accesses to the
60 * page will cause a fault, and handle_pte_fault() will set the young bit
61 * for us as long as the page is marked present in the corresponding Linux
62 * PTE entry. Again, ptep_set_access_flags() will ensure that the TLB is
63 * up to date.
64 *
65 * However, when the "young" bit is cleared, we deny access to the page
66 * by clearing the hardware PTE. Currently Linux does not flush the TLB
67 * for us in this case, which means the TLB will retain the transation
68 * until either the TLB entry is evicted under pressure, or a context
69 * switch which changes the user space mapping occurs.
70 */
71#define PTRS_PER_PTE 512
72#define PTRS_PER_PMD 1
73#define PTRS_PER_PGD 2048
74
75#define PTE_HWTABLE_PTRS (PTRS_PER_PTE)
76#define PTE_HWTABLE_OFF (PTE_HWTABLE_PTRS * sizeof(pte_t))
77#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32))
78
79/*
80 * PMD_SHIFT determines the size of the area a second-level page table can map
81 * PGDIR_SHIFT determines what a third-level page table entry can map
82 */
83#define PMD_SHIFT 21
84#define PGDIR_SHIFT 21
85
86#define PMD_SIZE (1UL << PMD_SHIFT)
87#define PMD_MASK (~(PMD_SIZE-1))
88#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
89#define PGDIR_MASK (~(PGDIR_SIZE-1))
90
91/*
92 * section address mask and size definitions.
93 */
94#define SECTION_SHIFT 20
95#define SECTION_SIZE (1UL << SECTION_SHIFT)
96#define SECTION_MASK (~(SECTION_SIZE-1))
97
98/*
99 * ARMv6 supersection address mask and size definitions.
100 */
101#define SUPERSECTION_SHIFT 24
102#define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT)
103#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1))
104
105#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
106
107/*
108 * "Linux" PTE definitions.
109 *
110 * We keep two sets of PTEs - the hardware and the linux version.
111 * This allows greater flexibility in the way we map the Linux bits
112 * onto the hardware tables, and allows us to have YOUNG and DIRTY
113 * bits.
114 *
115 * The PTE table pointer refers to the hardware entries; the "Linux"
116 * entries are stored 1024 bytes below.
117 */
118#define L_PTE_PRESENT (_AT(pteval_t, 1) << 0)
119#define L_PTE_YOUNG (_AT(pteval_t, 1) << 1)
120#define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */
121#define L_PTE_DIRTY (_AT(pteval_t, 1) << 6)
122#define L_PTE_RDONLY (_AT(pteval_t, 1) << 7)
123#define L_PTE_USER (_AT(pteval_t, 1) << 8)
124#define L_PTE_XN (_AT(pteval_t, 1) << 9)
125#define L_PTE_SHARED (_AT(pteval_t, 1) << 10) /* shared(v6), coherent(xsc3) */
126
127/*
128 * These are the memory types, defined to be compatible with
129 * pre-ARMv6 CPUs cacheable and bufferable bits: XXCB
130 */
131#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0x00) << 2) /* 0000 */
132#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */
133#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */
134#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */
135#define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */
136#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */
137#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
138#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
139#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */
140#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */
141#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
142
143#endif /* _ASM_PGTABLE_2LEVEL_H */
diff --git a/arch/arm/include/asm/pgtable-hwdef.h b/arch/arm/include/asm/pgtable-hwdef.h
index fd1521d5cb9d..183111164ce9 100644
--- a/arch/arm/include/asm/pgtable-hwdef.h
+++ b/arch/arm/include/asm/pgtable-hwdef.h
@@ -10,81 +10,6 @@
10#ifndef _ASMARM_PGTABLE_HWDEF_H 10#ifndef _ASMARM_PGTABLE_HWDEF_H
11#define _ASMARM_PGTABLE_HWDEF_H 11#define _ASMARM_PGTABLE_HWDEF_H
12 12
13/* 13#include <asm/pgtable-2level-hwdef.h>
14 * Hardware page table definitions.
15 *
16 * + Level 1 descriptor (PMD)
17 * - common
18 */
19#define PMD_TYPE_MASK (3 << 0)
20#define PMD_TYPE_FAULT (0 << 0)
21#define PMD_TYPE_TABLE (1 << 0)
22#define PMD_TYPE_SECT (2 << 0)
23#define PMD_BIT4 (1 << 4)
24#define PMD_DOMAIN(x) ((x) << 5)
25#define PMD_PROTECTION (1 << 9) /* v5 */
26/*
27 * - section
28 */
29#define PMD_SECT_BUFFERABLE (1 << 2)
30#define PMD_SECT_CACHEABLE (1 << 3)
31#define PMD_SECT_XN (1 << 4) /* v6 */
32#define PMD_SECT_AP_WRITE (1 << 10)
33#define PMD_SECT_AP_READ (1 << 11)
34#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */
35#define PMD_SECT_APX (1 << 15) /* v6 */
36#define PMD_SECT_S (1 << 16) /* v6 */
37#define PMD_SECT_nG (1 << 17) /* v6 */
38#define PMD_SECT_SUPER (1 << 18) /* v6 */
39
40#define PMD_SECT_UNCACHED (0)
41#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
42#define PMD_SECT_WT (PMD_SECT_CACHEABLE)
43#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
44#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
45#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
46#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2))
47
48/*
49 * - coarse table (not used)
50 */
51
52/*
53 * + Level 2 descriptor (PTE)
54 * - common
55 */
56#define PTE_TYPE_MASK (3 << 0)
57#define PTE_TYPE_FAULT (0 << 0)
58#define PTE_TYPE_LARGE (1 << 0)
59#define PTE_TYPE_SMALL (2 << 0)
60#define PTE_TYPE_EXT (3 << 0) /* v5 */
61#define PTE_BUFFERABLE (1 << 2)
62#define PTE_CACHEABLE (1 << 3)
63
64/*
65 * - extended small page/tiny page
66 */
67#define PTE_EXT_XN (1 << 0) /* v6 */
68#define PTE_EXT_AP_MASK (3 << 4)
69#define PTE_EXT_AP0 (1 << 4)
70#define PTE_EXT_AP1 (2 << 4)
71#define PTE_EXT_AP_UNO_SRO (0 << 4)
72#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
73#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
74#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
75#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
76#define PTE_EXT_APX (1 << 9) /* v6 */
77#define PTE_EXT_COHERENT (1 << 9) /* XScale3 */
78#define PTE_EXT_SHARED (1 << 10) /* v6 */
79#define PTE_EXT_NG (1 << 11) /* v6 */
80
81/*
82 * - small page
83 */
84#define PTE_SMALL_AP_MASK (0xff << 4)
85#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
86#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
87#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
88#define PTE_SMALL_AP_URW_SRW (0xff << 4)
89 14
90#endif 15#endif
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 5750704e0271..9451dce3a553 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -24,6 +24,8 @@
24#include <mach/vmalloc.h> 24#include <mach/vmalloc.h>
25#include <asm/pgtable-hwdef.h> 25#include <asm/pgtable-hwdef.h>
26 26
27#include <asm/pgtable-2level.h>
28
27/* 29/*
28 * Just any arbitrary offset to the start of the vmalloc VM area: the 30 * Just any arbitrary offset to the start of the vmalloc VM area: the
29 * current 8MB value just means that there will be a 8MB "hole" after the 31 * current 8MB value just means that there will be a 8MB "hole" after the
@@ -41,79 +43,6 @@
41#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) 43#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
42#endif 44#endif
43 45
44/*
45 * Hardware-wise, we have a two level page table structure, where the first
46 * level has 4096 entries, and the second level has 256 entries. Each entry
47 * is one 32-bit word. Most of the bits in the second level entry are used
48 * by hardware, and there aren't any "accessed" and "dirty" bits.
49 *
50 * Linux on the other hand has a three level page table structure, which can
51 * be wrapped to fit a two level page table structure easily - using the PGD
52 * and PTE only. However, Linux also expects one "PTE" table per page, and
53 * at least a "dirty" bit.
54 *
55 * Therefore, we tweak the implementation slightly - we tell Linux that we
56 * have 2048 entries in the first level, each of which is 8 bytes (iow, two
57 * hardware pointers to the second level.) The second level contains two
58 * hardware PTE tables arranged contiguously, preceded by Linux versions
59 * which contain the state information Linux needs. We, therefore, end up
60 * with 512 entries in the "PTE" level.
61 *
62 * This leads to the page tables having the following layout:
63 *
64 * pgd pte
65 * | |
66 * +--------+
67 * | | +------------+ +0
68 * +- - - - + | Linux pt 0 |
69 * | | +------------+ +1024
70 * +--------+ +0 | Linux pt 1 |
71 * | |-----> +------------+ +2048
72 * +- - - - + +4 | h/w pt 0 |
73 * | |-----> +------------+ +3072
74 * +--------+ +8 | h/w pt 1 |
75 * | | +------------+ +4096
76 *
77 * See L_PTE_xxx below for definitions of bits in the "Linux pt", and
78 * PTE_xxx for definitions of bits appearing in the "h/w pt".
79 *
80 * PMD_xxx definitions refer to bits in the first level page table.
81 *
82 * The "dirty" bit is emulated by only granting hardware write permission
83 * iff the page is marked "writable" and "dirty" in the Linux PTE. This
84 * means that a write to a clean page will cause a permission fault, and
85 * the Linux MM layer will mark the page dirty via handle_pte_fault().
86 * For the hardware to notice the permission change, the TLB entry must
87 * be flushed, and ptep_set_access_flags() does that for us.
88 *
89 * The "accessed" or "young" bit is emulated by a similar method; we only
90 * allow accesses to the page if the "young" bit is set. Accesses to the
91 * page will cause a fault, and handle_pte_fault() will set the young bit
92 * for us as long as the page is marked present in the corresponding Linux
93 * PTE entry. Again, ptep_set_access_flags() will ensure that the TLB is
94 * up to date.
95 *
96 * However, when the "young" bit is cleared, we deny access to the page
97 * by clearing the hardware PTE. Currently Linux does not flush the TLB
98 * for us in this case, which means the TLB will retain the transation
99 * until either the TLB entry is evicted under pressure, or a context
100 * switch which changes the user space mapping occurs.
101 */
102#define PTRS_PER_PTE 512
103#define PTRS_PER_PMD 1
104#define PTRS_PER_PGD 2048
105
106#define PTE_HWTABLE_PTRS (PTRS_PER_PTE)
107#define PTE_HWTABLE_OFF (PTE_HWTABLE_PTRS * sizeof(pte_t))
108#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32))
109
110/*
111 * PMD_SHIFT determines the size of the area a second-level page table can map
112 * PGDIR_SHIFT determines what a third-level page table entry can map
113 */
114#define PMD_SHIFT 21
115#define PGDIR_SHIFT 21
116
117#define LIBRARY_TEXT_START 0x0c000000 46#define LIBRARY_TEXT_START 0x0c000000
118 47
119#ifndef __ASSEMBLY__ 48#ifndef __ASSEMBLY__
@@ -124,12 +53,6 @@ extern void __pgd_error(const char *file, int line, pgd_t);
124#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte) 53#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte)
125#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd) 54#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd)
126#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd) 55#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd)
127#endif /* !__ASSEMBLY__ */
128
129#define PMD_SIZE (1UL << PMD_SHIFT)
130#define PMD_MASK (~(PMD_SIZE-1))
131#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
132#define PGDIR_MASK (~(PGDIR_SIZE-1))
133 56
134/* 57/*
135 * This is the lowest virtual address we can permit any user space 58 * This is the lowest virtual address we can permit any user space
@@ -138,60 +61,6 @@ extern void __pgd_error(const char *file, int line, pgd_t);
138 */ 61 */
139#define FIRST_USER_ADDRESS PAGE_SIZE 62#define FIRST_USER_ADDRESS PAGE_SIZE
140 63
141#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
142
143/*
144 * section address mask and size definitions.
145 */
146#define SECTION_SHIFT 20
147#define SECTION_SIZE (1UL << SECTION_SHIFT)
148#define SECTION_MASK (~(SECTION_SIZE-1))
149
150/*
151 * ARMv6 supersection address mask and size definitions.
152 */
153#define SUPERSECTION_SHIFT 24
154#define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT)
155#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1))
156
157/*
158 * "Linux" PTE definitions.
159 *
160 * We keep two sets of PTEs - the hardware and the linux version.
161 * This allows greater flexibility in the way we map the Linux bits
162 * onto the hardware tables, and allows us to have YOUNG and DIRTY
163 * bits.
164 *
165 * The PTE table pointer refers to the hardware entries; the "Linux"
166 * entries are stored 1024 bytes below.
167 */
168#define L_PTE_PRESENT (_AT(pteval_t, 1) << 0)
169#define L_PTE_YOUNG (_AT(pteval_t, 1) << 1)
170#define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */
171#define L_PTE_DIRTY (_AT(pteval_t, 1) << 6)
172#define L_PTE_RDONLY (_AT(pteval_t, 1) << 7)
173#define L_PTE_USER (_AT(pteval_t, 1) << 8)
174#define L_PTE_XN (_AT(pteval_t, 1) << 9)
175#define L_PTE_SHARED (_AT(pteval_t, 1) << 10) /* shared(v6), coherent(xsc3) */
176
177/*
178 * These are the memory types, defined to be compatible with
179 * pre-ARMv6 CPUs cacheable and bufferable bits: XXCB
180 */
181#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0x00) << 2) /* 0000 */
182#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */
183#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */
184#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */
185#define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */
186#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */
187#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
188#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
189#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */
190#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */
191#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
192
193#ifndef __ASSEMBLY__
194
195/* 64/*
196 * The pgprot_* and protection_map entries will be fixed up in runtime 65 * The pgprot_* and protection_map entries will be fixed up in runtime
197 * to include the cachable and bufferable bits based on memory policy, 66 * to include the cachable and bufferable bits based on memory policy,
@@ -232,6 +101,9 @@ extern pgprot_t pgprot_kernel;
232#define pgprot_writecombine(prot) \ 101#define pgprot_writecombine(prot) \
233 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE) 102 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
234 103
104#define pgprot_stronglyordered(prot) \
105 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
106
235#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 107#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
236#define pgprot_dmacoherent(prot) \ 108#define pgprot_dmacoherent(prot) \
237 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN) 109 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
@@ -327,10 +199,10 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
327 199
328static inline pte_t *pmd_page_vaddr(pmd_t pmd) 200static inline pte_t *pmd_page_vaddr(pmd_t pmd)
329{ 201{
330 return __va(pmd_val(pmd) & PAGE_MASK); 202 return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
331} 203}
332 204
333#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd))) 205#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
334 206
335/* we don't need complex calculations here as the pmd is folded into the pgd */ 207/* we don't need complex calculations here as the pmd is folded into the pgd */
336#define pmd_addr_end(addr,end) (end) 208#define pmd_addr_end(addr,end) (end)
@@ -351,7 +223,7 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
351#define pte_offset_map(pmd,addr) (__pte_map(pmd) + pte_index(addr)) 223#define pte_offset_map(pmd,addr) (__pte_map(pmd) + pte_index(addr))
352#define pte_unmap(pte) __pte_unmap(pte) 224#define pte_unmap(pte) __pte_unmap(pte)
353 225
354#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) 226#define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
355#define pfn_pte(pfn,prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot)) 227#define pfn_pte(pfn,prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot))
356 228
357#define pte_page(pte) pfn_to_page(pte_pfn(pte)) 229#define pte_page(pte) pfn_to_page(pte_pfn(pte))
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index b7e82c4aced6..71d99b83cdb9 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -13,7 +13,12 @@
13#define __ARM_PMU_H__ 13#define __ARM_PMU_H__
14 14
15#include <linux/interrupt.h> 15#include <linux/interrupt.h>
16#include <linux/perf_event.h>
16 17
18/*
19 * Types of PMUs that can be accessed directly and require mutual
20 * exclusion between profiling tools.
21 */
17enum arm_pmu_type { 22enum arm_pmu_type {
18 ARM_PMU_DEVICE_CPU = 0, 23 ARM_PMU_DEVICE_CPU = 0,
19 ARM_NUM_PMU_DEVICES, 24 ARM_NUM_PMU_DEVICES,
@@ -37,21 +42,17 @@ struct arm_pmu_platdata {
37 * reserve_pmu() - reserve the hardware performance counters 42 * reserve_pmu() - reserve the hardware performance counters
38 * 43 *
39 * Reserve the hardware performance counters in the system for exclusive use. 44 * Reserve the hardware performance counters in the system for exclusive use.
40 * The platform_device for the system is returned on success, ERR_PTR() 45 * Returns 0 on success or -EBUSY if the lock is already held.
41 * encoded error on failure.
42 */ 46 */
43extern struct platform_device * 47extern int
44reserve_pmu(enum arm_pmu_type type); 48reserve_pmu(enum arm_pmu_type type);
45 49
46/** 50/**
47 * release_pmu() - Relinquish control of the performance counters 51 * release_pmu() - Relinquish control of the performance counters
48 * 52 *
49 * Release the performance counters and allow someone else to use them. 53 * Release the performance counters and allow someone else to use them.
50 * Callers must have disabled the counters and released IRQs before calling
51 * this. The platform_device returned from reserve_pmu() must be passed as
52 * a cookie.
53 */ 54 */
54extern int 55extern void
55release_pmu(enum arm_pmu_type type); 56release_pmu(enum arm_pmu_type type);
56 57
57/** 58/**
@@ -68,24 +69,78 @@ init_pmu(enum arm_pmu_type type);
68 69
69#include <linux/err.h> 70#include <linux/err.h>
70 71
71static inline struct platform_device *
72reserve_pmu(enum arm_pmu_type type)
73{
74 return ERR_PTR(-ENODEV);
75}
76
77static inline int 72static inline int
78release_pmu(enum arm_pmu_type type) 73reserve_pmu(enum arm_pmu_type type)
79{ 74{
80 return -ENODEV; 75 return -ENODEV;
81} 76}
82 77
83static inline int 78static inline void
84init_pmu(enum arm_pmu_type type) 79release_pmu(enum arm_pmu_type type) { }
85{
86 return -ENODEV;
87}
88 80
89#endif /* CONFIG_CPU_HAS_PMU */ 81#endif /* CONFIG_CPU_HAS_PMU */
90 82
83#ifdef CONFIG_HW_PERF_EVENTS
84
85/* The events for a given PMU register set. */
86struct pmu_hw_events {
87 /*
88 * The events that are active on the PMU for the given index.
89 */
90 struct perf_event **events;
91
92 /*
93 * A 1 bit for an index indicates that the counter is being used for
94 * an event. A 0 means that the counter can be used.
95 */
96 unsigned long *used_mask;
97
98 /*
99 * Hardware lock to serialize accesses to PMU registers. Needed for the
100 * read/modify/write sequences.
101 */
102 raw_spinlock_t pmu_lock;
103};
104
105struct arm_pmu {
106 struct pmu pmu;
107 enum arm_perf_pmu_ids id;
108 enum arm_pmu_type type;
109 cpumask_t active_irqs;
110 const char *name;
111 irqreturn_t (*handle_irq)(int irq_num, void *dev);
112 void (*enable)(struct hw_perf_event *evt, int idx);
113 void (*disable)(struct hw_perf_event *evt, int idx);
114 int (*get_event_idx)(struct pmu_hw_events *hw_events,
115 struct hw_perf_event *hwc);
116 int (*set_event_filter)(struct hw_perf_event *evt,
117 struct perf_event_attr *attr);
118 u32 (*read_counter)(int idx);
119 void (*write_counter)(int idx, u32 val);
120 void (*start)(void);
121 void (*stop)(void);
122 void (*reset)(void *);
123 int (*map_event)(struct perf_event *event);
124 int num_events;
125 atomic_t active_events;
126 struct mutex reserve_mutex;
127 u64 max_period;
128 struct platform_device *plat_device;
129 struct pmu_hw_events *(*get_hw_events)(void);
130};
131
132#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
133
134int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
135
136u64 armpmu_event_update(struct perf_event *event,
137 struct hw_perf_event *hwc,
138 int idx, int overflow);
139
140int armpmu_event_set_period(struct perf_event *event,
141 struct hw_perf_event *hwc,
142 int idx);
143
144#endif /* CONFIG_HW_PERF_EVENTS */
145
91#endif /* __ARM_PMU_H__ */ 146#endif /* __ARM_PMU_H__ */
diff --git a/arch/arm/include/asm/poll.h b/arch/arm/include/asm/poll.h
deleted file mode 100644
index c98509d3149e..000000000000
--- a/arch/arm/include/asm/poll.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/poll.h>
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index 633d1cb84d87..9e92cb205e65 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -81,6 +81,10 @@ extern void cpu_dcache_clean_area(void *, int);
81extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm); 81extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
82extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext); 82extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext);
83extern void cpu_reset(unsigned long addr) __attribute__((noreturn)); 83extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
84
85/* These three are private to arch/arm/kernel/suspend.c */
86extern void cpu_do_suspend(void *);
87extern void cpu_do_resume(void *);
84#else 88#else
85#define cpu_proc_init processor._proc_init 89#define cpu_proc_init processor._proc_init
86#define cpu_proc_fin processor._proc_fin 90#define cpu_proc_fin processor._proc_fin
@@ -89,6 +93,10 @@ extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
89#define cpu_dcache_clean_area processor.dcache_clean_area 93#define cpu_dcache_clean_area processor.dcache_clean_area
90#define cpu_set_pte_ext processor.set_pte_ext 94#define cpu_set_pte_ext processor.set_pte_ext
91#define cpu_do_switch_mm processor.switch_mm 95#define cpu_do_switch_mm processor.switch_mm
96
97/* These three are private to arch/arm/kernel/suspend.c */
98#define cpu_do_suspend processor.do_suspend
99#define cpu_do_resume processor.do_resume
92#endif 100#endif
93 101
94extern void cpu_resume(void); 102extern void cpu_resume(void);
diff --git a/arch/arm/include/asm/resource.h b/arch/arm/include/asm/resource.h
deleted file mode 100644
index 734b581b5b6a..000000000000
--- a/arch/arm/include/asm/resource.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ARM_RESOURCE_H
2#define _ARM_RESOURCE_H
3
4#include <asm-generic/resource.h>
5
6#endif
diff --git a/arch/arm/include/asm/sections.h b/arch/arm/include/asm/sections.h
deleted file mode 100644
index 2b8c5160388f..000000000000
--- a/arch/arm/include/asm/sections.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/sections.h>
diff --git a/arch/arm/include/asm/siginfo.h b/arch/arm/include/asm/siginfo.h
deleted file mode 100644
index 5e21852e6039..000000000000
--- a/arch/arm/include/asm/siginfo.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASMARM_SIGINFO_H
2#define _ASMARM_SIGINFO_H
3
4#include <asm-generic/siginfo.h>
5
6#endif
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
deleted file mode 100644
index 154b89b81d3e..000000000000
--- a/arch/arm/include/asm/sizes.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
15 */
16/* Size definitions
17 * Copyright (C) ARM Limited 1998. All rights reserved.
18 */
19#include <asm-generic/sizes.h>
20
21#define SZ_48M (SZ_32M + SZ_16M)
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index e42d96a45d3e..1e5717afc4ac 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -33,6 +33,11 @@ extern void show_ipi_list(struct seq_file *, int);
33asmlinkage void do_IPI(int ipinr, struct pt_regs *regs); 33asmlinkage void do_IPI(int ipinr, struct pt_regs *regs);
34 34
35/* 35/*
36 * Called from C code, this handles an IPI.
37 */
38void handle_IPI(int ipinr, struct pt_regs *regs);
39
40/*
36 * Setup the set of possible CPUs (via set_cpu_possible) 41 * Setup the set of possible CPUs (via set_cpu_possible)
37 */ 42 */
38extern void smp_init_cpus(void); 43extern void smp_init_cpus(void);
@@ -66,6 +71,12 @@ extern void platform_secondary_init(unsigned int cpu);
66extern void platform_smp_prepare_cpus(unsigned int); 71extern void platform_smp_prepare_cpus(unsigned int);
67 72
68/* 73/*
74 * Logical CPU mapping.
75 */
76extern int __cpu_logical_map[NR_CPUS];
77#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
78
79/*
69 * Initial data for bringing up a secondary CPU. 80 * Initial data for bringing up a secondary CPU.
70 */ 81 */
71struct secondary_data { 82struct secondary_data {
@@ -88,9 +99,4 @@ extern void platform_cpu_enable(unsigned int cpu);
88extern void arch_send_call_function_single_ipi(int cpu); 99extern void arch_send_call_function_single_ipi(int cpu);
89extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); 100extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
90 101
91/*
92 * show local interrupt info
93 */
94extern void show_local_irqs(struct seq_file *, int);
95
96#endif /* ifndef __ASM_ARM_SMP_H */ 102#endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index fed9981fba08..ef9ffba97ad8 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -22,7 +22,7 @@ struct clock_event_device;
22 22
23extern void __iomem *twd_base; 23extern void __iomem *twd_base;
24 24
25int twd_timer_ack(void);
26void twd_timer_setup(struct clock_event_device *); 25void twd_timer_setup(struct clock_event_device *);
26void twd_timer_stop(struct clock_event_device *);
27 27
28#endif 28#endif
diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h
index b0e4e1a02318..1c0a551ae375 100644
--- a/arch/arm/include/asm/suspend.h
+++ b/arch/arm/include/asm/suspend.h
@@ -1,22 +1,7 @@
1#ifndef __ASM_ARM_SUSPEND_H 1#ifndef __ASM_ARM_SUSPEND_H
2#define __ASM_ARM_SUSPEND_H 2#define __ASM_ARM_SUSPEND_H
3 3
4#include <asm/memory.h>
5#include <asm/tlbflush.h>
6
7extern void cpu_resume(void); 4extern void cpu_resume(void);
8 5extern int cpu_suspend(unsigned long, int (*)(unsigned long));
9/*
10 * Hide the first two arguments to __cpu_suspend - these are an implementation
11 * detail which platform code shouldn't have to know about.
12 */
13static inline int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
14{
15 extern int __cpu_suspend(int, long, unsigned long,
16 int (*)(unsigned long));
17 int ret = __cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);
18 flush_tlb_all();
19 return ret;
20}
21 6
22#endif 7#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 832888d0c20c..984014b92647 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -57,18 +57,12 @@
57 57
58#ifndef __ASSEMBLY__ 58#ifndef __ASSEMBLY__
59 59
60#include <linux/compiler.h>
60#include <linux/linkage.h> 61#include <linux/linkage.h>
61#include <linux/irqflags.h> 62#include <linux/irqflags.h>
62 63
63#include <asm/outercache.h> 64#include <asm/outercache.h>
64 65
65#define __exception __attribute__((section(".exception.text")))
66#ifdef CONFIG_FUNCTION_GRAPH_TRACER
67#define __exception_irq_entry __irq_entry
68#else
69#define __exception_irq_entry __exception
70#endif
71
72struct thread_info; 66struct thread_info;
73struct task_struct; 67struct task_struct;
74 68
@@ -97,14 +91,13 @@ void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int,
97#define xchg(ptr,x) \ 91#define xchg(ptr,x) \
98 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) 92 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
99 93
100extern asmlinkage void __backtrace(void);
101extern asmlinkage void c_backtrace(unsigned long fp, int pmode); 94extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
102 95
103struct mm_struct; 96struct mm_struct;
104extern void show_pte(struct mm_struct *mm, unsigned long addr); 97extern void show_pte(struct mm_struct *mm, unsigned long addr);
105extern void __show_regs(struct pt_regs *); 98extern void __show_regs(struct pt_regs *);
106 99
107extern int cpu_architecture(void); 100extern int __pure cpu_architecture(void);
108extern void cpu_init(void); 101extern void cpu_init(void);
109 102
110void arm_machine_restart(char mode, const char *cmd); 103void arm_machine_restart(char mode, const char *cmd);
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 8077145698ff..02b2f8203982 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -471,7 +471,7 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
471 * these operations. This is typically used when we are removing 471 * these operations. This is typically used when we are removing
472 * PMD entries. 472 * PMD entries.
473 */ 473 */
474static inline void flush_pmd_entry(pmd_t *pmd) 474static inline void flush_pmd_entry(void *pmd)
475{ 475{
476 const unsigned int __tlb_flag = __cpu_tlb_flags; 476 const unsigned int __tlb_flag = __cpu_tlb_flags;
477 477
@@ -487,7 +487,7 @@ static inline void flush_pmd_entry(pmd_t *pmd)
487 dsb(); 487 dsb();
488} 488}
489 489
490static inline void clean_pmd_entry(pmd_t *pmd) 490static inline void clean_pmd_entry(void *pmd)
491{ 491{
492 const unsigned int __tlb_flag = __cpu_tlb_flags; 492 const unsigned int __tlb_flag = __cpu_tlb_flags;
493 493
diff --git a/arch/arm/include/asm/topology.h b/arch/arm/include/asm/topology.h
index accbd7cad9b5..a7e457ed27c3 100644
--- a/arch/arm/include/asm/topology.h
+++ b/arch/arm/include/asm/topology.h
@@ -1,6 +1,39 @@
1#ifndef _ASM_ARM_TOPOLOGY_H 1#ifndef _ASM_ARM_TOPOLOGY_H
2#define _ASM_ARM_TOPOLOGY_H 2#define _ASM_ARM_TOPOLOGY_H
3 3
4#ifdef CONFIG_ARM_CPU_TOPOLOGY
5
6#include <linux/cpumask.h>
7
8struct cputopo_arm {
9 int thread_id;
10 int core_id;
11 int socket_id;
12 cpumask_t thread_sibling;
13 cpumask_t core_sibling;
14};
15
16extern struct cputopo_arm cpu_topology[NR_CPUS];
17
18#define topology_physical_package_id(cpu) (cpu_topology[cpu].socket_id)
19#define topology_core_id(cpu) (cpu_topology[cpu].core_id)
20#define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling)
21#define topology_thread_cpumask(cpu) (&cpu_topology[cpu].thread_sibling)
22
23#define mc_capable() (cpu_topology[0].socket_id != -1)
24#define smt_capable() (cpu_topology[0].thread_id != -1)
25
26void init_cpu_topology(void);
27void store_cpu_topology(unsigned int cpuid);
28const struct cpumask *cpu_coregroup_mask(unsigned int cpu);
29
30#else
31
32static inline void init_cpu_topology(void) { }
33static inline void store_cpu_topology(unsigned int cpuid) { }
34
35#endif
36
4#include <asm-generic/topology.h> 37#include <asm-generic/topology.h>
5 38
6#endif /* _ASM_ARM_TOPOLOGY_H */ 39#endif /* _ASM_ARM_TOPOLOGY_H */
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 2c04ed5efeb5..c60a2944f95b 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -478,8 +478,8 @@
478/* 478/*
479 * Unimplemented (or alternatively implemented) syscalls 479 * Unimplemented (or alternatively implemented) syscalls
480 */ 480 */
481#define __IGNORE_fadvise64_64 1 481#define __IGNORE_fadvise64_64
482#define __IGNORE_migrate_pages 1 482#define __IGNORE_migrate_pages
483 483
484#endif /* __KERNEL__ */ 484#endif /* __KERNEL__ */
485#endif /* __ASM_ARM_UNISTD_H */ 485#endif /* __ASM_ARM_UNISTD_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-04 03:56:06 -0500