5 files changed, 70 insertions, 31 deletions

diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index 5ef4d8015a60..1f3262e99d81 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -42,6 +42,8 @@
 #define vectors_high()  (0)
 #endif
 
+#ifdef CONFIG_CPU_CP15
+
 extern unsigned long cr_no_alignment;   /* defined in entry-armv.S */
 extern unsigned long cr_alignment;      /* defined in entry-armv.S */
 
@@ -82,6 +84,18 @@ static inline void set_copro_access(unsigned int val)
         isb();
 }
 
-#endif
+#else /* ifdef CONFIG_CPU_CP15 */
+
+/*
+ * cr_alignment and cr_no_alignment are tightly coupled to cp15 (at least in the
+ * minds of the developers). Yielding 0 for machines without a cp15 (and making
+ * it read-only) is fine for most cases and saves quite some #ifdeffery.
+ */
+#define cr_no_alignment UL(0)
+#define cr_alignment    UL(0)
+
+#endif /* ifdef CONFIG_CPU_CP15 / else */
+
+#endif /* ifndef __ASSEMBLY__ */
 
 #endif
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index ad41ec2471e8..7652712d1d14 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -38,6 +38,24 @@
 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
         ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
 
+#define ARM_CPU_IMP_ARM                 0x41
+#define ARM_CPU_IMP_INTEL               0x69
+
+#define ARM_CPU_PART_ARM1136            0xB360
+#define ARM_CPU_PART_ARM1156            0xB560
+#define ARM_CPU_PART_ARM1176            0xB760
+#define ARM_CPU_PART_ARM11MPCORE        0xB020
+#define ARM_CPU_PART_CORTEX_A8          0xC080
+#define ARM_CPU_PART_CORTEX_A9          0xC090
+#define ARM_CPU_PART_CORTEX_A5          0xC050
+#define ARM_CPU_PART_CORTEX_A15         0xC0F0
+#define ARM_CPU_PART_CORTEX_A7          0xC070
+
+#define ARM_CPU_XSCALE_ARCH_MASK        0xe000
+#define ARM_CPU_XSCALE_ARCH_V1          0x2000
+#define ARM_CPU_XSCALE_ARCH_V2          0x4000
+#define ARM_CPU_XSCALE_ARCH_V3          0x6000
+
 extern unsigned int processor_id;
 
 #ifdef CONFIG_CPU_CP15
@@ -50,6 +68,7 @@ extern unsigned int processor_id;
                     : "cc");                                            \
                 __val;                                                  \
         })
+
 #define read_cpuid_ext(ext_reg)                                         \
         ({                                                              \
                 unsigned int __val;                                     \
@@ -59,29 +78,24 @@ extern unsigned int processor_id;
                     : "cc");                                            \
                 __val;                                                  \
         })
-#else
-#define read_cpuid(reg) (processor_id)
-#define read_cpuid_ext(reg) 0
-#endif
 
-#define ARM_CPU_IMP_ARM                 0x41
-#define ARM_CPU_IMP_INTEL               0x69
+#else /* ifdef CONFIG_CPU_CP15 */
 
-#define ARM_CPU_PART_ARM1136            0xB360
-#define ARM_CPU_PART_ARM1156            0xB560
-#define ARM_CPU_PART_ARM1176            0xB760
-#define ARM_CPU_PART_ARM11MPCORE        0xB020
-#define ARM_CPU_PART_CORTEX_A8          0xC080
-#define ARM_CPU_PART_CORTEX_A9          0xC090
-#define ARM_CPU_PART_CORTEX_A5          0xC050
-#define ARM_CPU_PART_CORTEX_A15         0xC0F0
-#define ARM_CPU_PART_CORTEX_A7          0xC070
+/*
+ * read_cpuid and read_cpuid_ext should only ever be called on machines that
+ * have cp15 so warn on other usages.
+ */
+#define read_cpuid(reg)                                                 \
+        ({                                                              \
+                WARN_ON_ONCE(1);                                        \
+                0;                                                      \
+        })
 
-#define ARM_CPU_XSCALE_ARCH_MASK        0xe000
-#define ARM_CPU_XSCALE_ARCH_V1          0x2000
-#define ARM_CPU_XSCALE_ARCH_V2          0x4000
-#define ARM_CPU_XSCALE_ARCH_V3          0x6000
+#define read_cpuid_ext(reg) read_cpuid(reg)
+
+#endif /* ifdef CONFIG_CPU_CP15 / else */
 
+#ifdef CONFIG_CPU_CP15
 /*
  * The CPU ID never changes at run time, so we might as well tell the
  * compiler that it's constant.  Use this function to read the CPU ID
@@ -92,6 +106,15 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
         return read_cpuid(CPUID_ID);
 }
 
+#else /* ifdef CONFIG_CPU_CP15 */
+
+static inline unsigned int __attribute_const__ read_cpuid_id(void)
+{
+        return processor_id;
+}
+
+#endif /* ifdef CONFIG_CPU_CP15 / else */
+
 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 {
         return (read_cpuid_id() & 0xFF000000) >> 24;
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
index ab98fdd083bd..720799fd3a81 100644
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@@ -24,6 +24,7 @@ extern struct arm_delay_ops {
         void (*delay)(unsigned long);
         void (*const_udelay)(unsigned long);
         void (*udelay)(unsigned long);
+        bool const_clock;
 } arm_delay_ops;
 
 #define __delay(n)              arm_delay_ops.delay(n)
diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h
index 8cacbcda76da..b6e9f2c108b5 100644
--- a/arch/arm/include/asm/glue-df.h
+++ b/arch/arm/include/asm/glue-df.h
@@ -18,12 +18,12 @@
  *      ================
  *
  *      We have the following to choose from:
- *        arm6          - ARM6 style
  *        arm7          - ARM7 style
  *        v4_early      - ARMv4 without Thumb early abort handler
  *        v4t_late      - ARMv4 with Thumb late abort handler
  *        v4t_early     - ARMv4 with Thumb early abort handler
- *        v5tej_early   - ARMv5 with Thumb and Java early abort handler
+ *        v5t_early     - ARMv5 with Thumb early abort handler
+ *        v5tj_early    - ARMv5 with Thumb and Java early abort handler
  *        xscale        - ARMv5 with Thumb with Xscale extensions
  *        v6_early      - ARMv6 generic early abort handler
  *        v7_early      - ARMv7 generic early abort handler
@@ -39,19 +39,19 @@
 # endif
 #endif
 
-#ifdef CONFIG_CPU_ABRT_LV4T
+#ifdef CONFIG_CPU_ABRT_EV4
 # ifdef CPU_DABORT_HANDLER
 #  define MULTI_DABORT 1
 # else
-#  define CPU_DABORT_HANDLER v4t_late_abort
+#  define CPU_DABORT_HANDLER v4_early_abort
 # endif
 #endif
 
-#ifdef CONFIG_CPU_ABRT_EV4
+#ifdef CONFIG_CPU_ABRT_LV4T
 # ifdef CPU_DABORT_HANDLER
 #  define MULTI_DABORT 1
 # else
-#  define CPU_DABORT_HANDLER v4_early_abort
+#  define CPU_DABORT_HANDLER v4t_late_abort
 # endif
 #endif
 
@@ -63,19 +63,19 @@
 # endif
 #endif
 
-#ifdef CONFIG_CPU_ABRT_EV5TJ
+#ifdef CONFIG_CPU_ABRT_EV5T
 # ifdef CPU_DABORT_HANDLER
 #  define MULTI_DABORT 1
 # else
-#  define CPU_DABORT_HANDLER v5tj_early_abort
+#  define CPU_DABORT_HANDLER v5t_early_abort
 # endif
 #endif
 
-#ifdef CONFIG_CPU_ABRT_EV5T
+#ifdef CONFIG_CPU_ABRT_EV5TJ
 # ifdef CPU_DABORT_HANDLER
 #  define MULTI_DABORT 1
 # else
-#  define CPU_DABORT_HANDLER v5t_early_abort
+#  define CPU_DABORT_HANDLER v5tj_early_abort
 # endif
 #endif
 
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index f30ac3b55ba9..80d6fc4dbe4a 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -247,7 +247,8 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
 
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
-        const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER | L_PTE_NONE;
+        const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER |
+                L_PTE_NONE | L_PTE_VALID;
         pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
         return pte;
 }