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-rw-r--r--arch/arm/include/asm/hardware/coresight.h165
1 files changed, 165 insertions, 0 deletions
diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h
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1/*
2 * linux/arch/arm/include/asm/hardware/coresight.h
3 *
4 * CoreSight components' registers
5 *
6 * Copyright (C) 2009 Nokia Corporation.
7 * Alexander Shishkin
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_HARDWARE_CORESIGHT_H
15#define __ASM_HARDWARE_CORESIGHT_H
16
17#define TRACER_ACCESSED_BIT 0
18#define TRACER_RUNNING_BIT 1
19#define TRACER_CYCLE_ACC_BIT 2
20#define TRACER_ACCESSED BIT(TRACER_ACCESSED_BIT)
21#define TRACER_RUNNING BIT(TRACER_RUNNING_BIT)
22#define TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT)
23
24struct tracectx {
25 unsigned int etb_bufsz;
26 void __iomem *etb_regs;
27 void __iomem *etm_regs;
28 unsigned long flags;
29 int ncmppairs;
30 int etm_portsz;
31 struct device *dev;
32 struct clk *emu_clk;
33 struct mutex mutex;
34};
35
36#define TRACER_TIMEOUT 10000
37
38#define etm_writel(t, v, x) \
39 (__raw_writel((v), (t)->etm_regs + (x)))
40#define etm_readl(t, x) (__raw_readl((t)->etm_regs + (x)))
41
42/* CoreSight Management Registers */
43#define CSMR_LOCKACCESS 0xfb0
44#define CSMR_LOCKSTATUS 0xfb4
45#define CSMR_AUTHSTATUS 0xfb8
46#define CSMR_DEVID 0xfc8
47#define CSMR_DEVTYPE 0xfcc
48/* CoreSight Component Registers */
49#define CSCR_CLASS 0xff4
50
51#define CSCR_PRSR 0x314
52
53#define UNLOCK_MAGIC 0xc5acce55
54
55/* ETM control register, "ETM Architecture", 3.3.1 */
56#define ETMR_CTRL 0
57#define ETMCTRL_POWERDOWN 1
58#define ETMCTRL_PROGRAM (1 << 10)
59#define ETMCTRL_PORTSEL (1 << 11)
60#define ETMCTRL_DO_CONTEXTID (3 << 14)
61#define ETMCTRL_PORTMASK1 (7 << 4)
62#define ETMCTRL_PORTMASK2 (1 << 21)
63#define ETMCTRL_PORTMASK (ETMCTRL_PORTMASK1 | ETMCTRL_PORTMASK2)
64#define ETMCTRL_PORTSIZE(x) ((((x) & 7) << 4) | (!!((x) & 8)) << 21)
65#define ETMCTRL_DO_CPRT (1 << 1)
66#define ETMCTRL_DATAMASK (3 << 2)
67#define ETMCTRL_DATA_DO_DATA (1 << 2)
68#define ETMCTRL_DATA_DO_ADDR (1 << 3)
69#define ETMCTRL_DATA_DO_BOTH (ETMCTRL_DATA_DO_DATA | ETMCTRL_DATA_DO_ADDR)
70#define ETMCTRL_BRANCH_OUTPUT (1 << 8)
71#define ETMCTRL_CYCLEACCURATE (1 << 12)
72
73/* ETM configuration code register */
74#define ETMR_CONFCODE (0x04)
75
76/* ETM trace start/stop resource control register */
77#define ETMR_TRACESSCTRL (0x18)
78
79/* ETM trigger event register */
80#define ETMR_TRIGEVT (0x08)
81
82/* address access type register bits, "ETM architecture",
83 * table 3-27 */
84/* - access type */
85#define ETMAAT_IFETCH 0
86#define ETMAAT_IEXEC 1
87#define ETMAAT_IEXECPASS 2
88#define ETMAAT_IEXECFAIL 3
89#define ETMAAT_DLOADSTORE 4
90#define ETMAAT_DLOAD 5
91#define ETMAAT_DSTORE 6
92/* - comparison access size */
93#define ETMAAT_JAVA (0 << 3)
94#define ETMAAT_THUMB (1 << 3)
95#define ETMAAT_ARM (3 << 3)
96/* - data value comparison control */
97#define ETMAAT_NOVALCMP (0 << 5)
98#define ETMAAT_VALMATCH (1 << 5)
99#define ETMAAT_VALNOMATCH (3 << 5)
100/* - exact match */
101#define ETMAAT_EXACTMATCH (1 << 7)
102/* - context id comparator control */
103#define ETMAAT_IGNCONTEXTID (0 << 8)
104#define ETMAAT_VALUE1 (1 << 8)
105#define ETMAAT_VALUE2 (2 << 8)
106#define ETMAAT_VALUE3 (3 << 8)
107/* - security level control */
108#define ETMAAT_IGNSECURITY (0 << 10)
109#define ETMAAT_NSONLY (1 << 10)
110#define ETMAAT_SONLY (2 << 10)
111
112#define ETMR_COMP_VAL(x) (0x40 + (x) * 4)
113#define ETMR_COMP_ACC_TYPE(x) (0x80 + (x) * 4)
114
115/* ETM status register, "ETM Architecture", 3.3.2 */
116#define ETMR_STATUS (0x10)
117#define ETMST_OVERFLOW (1 << 0)
118#define ETMST_PROGBIT (1 << 1)
119#define ETMST_STARTSTOP (1 << 2)
120#define ETMST_TRIGGER (1 << 3)
121
122#define etm_progbit(t) (etm_readl((t), ETMR_STATUS) & ETMST_PROGBIT)
123#define etm_started(t) (etm_readl((t), ETMR_STATUS) & ETMST_STARTSTOP)
124#define etm_triggered(t) (etm_readl((t), ETMR_STATUS) & ETMST_TRIGGER)
125
126#define ETMR_TRACEENCTRL2 0x1c
127#define ETMR_TRACEENCTRL 0x24
128#define ETMTE_INCLEXCL (1 << 24)
129#define ETMR_TRACEENEVT 0x20
130#define ETMCTRL_OPTS (ETMCTRL_DO_CPRT | \
131 ETMCTRL_DATA_DO_ADDR | \
132 ETMCTRL_BRANCH_OUTPUT | \
133 ETMCTRL_DO_CONTEXTID)
134
135/* ETB registers, "CoreSight Components TRM", 9.3 */
136#define ETBR_DEPTH 0x04
137#define ETBR_STATUS 0x0c
138#define ETBR_READMEM 0x10
139#define ETBR_READADDR 0x14
140#define ETBR_WRITEADDR 0x18
141#define ETBR_TRIGGERCOUNT 0x1c
142#define ETBR_CTRL 0x20
143#define ETBR_FORMATTERCTRL 0x304
144#define ETBFF_ENFTC 1
145#define ETBFF_ENFCONT (1 << 1)
146#define ETBFF_FONFLIN (1 << 4)
147#define ETBFF_MANUAL_FLUSH (1 << 6)
148#define ETBFF_TRIGIN (1 << 8)
149#define ETBFF_TRIGEVT (1 << 9)
150#define ETBFF_TRIGFL (1 << 10)
151
152#define etb_writel(t, v, x) \
153 (__raw_writel((v), (t)->etb_regs + (x)))
154#define etb_readl(t, x) (__raw_readl((t)->etb_regs + (x)))
155
156#define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0)
157#define etm_unlock(t) \
158 do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
159
160#define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0)
161#define etb_unlock(t) \
162 do { etb_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
163
164#endif /* __ASM_HARDWARE_CORESIGHT_H */
165