1 files changed, 93 insertions, 0 deletions
diff --git a/arch/arm/include/debug/msm.S b/arch/arm/include/debug/msm.S
new file mode 100644
index 000000000000..9166e1bc470e
--- /dev/null
+++ b/arch/arm/include/debug/msm.S
@@ -0,0 +1,93 @@
+/*
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_QSD8X50)
+#define MSM_UART1_PHYS        0xA9A00000
+#define MSM_UART2_PHYS        0xA9B00000
+#define MSM_UART3_PHYS        0xA9C00000
+#elif defined(CONFIG_ARCH_MSM7X30)
+#define MSM_UART1_PHYS        0xACA00000
+#define MSM_UART2_PHYS        0xACB00000
+#define MSM_UART3_PHYS        0xACC00000
+#endif
+#if defined(CONFIG_DEBUG_MSM_UART1)
+#define MSM_DEBUG_UART_BASE     0xE1000000
+#define MSM_DEBUG_UART_PHYS     MSM_UART1_PHYS
+#elif defined(CONFIG_DEBUG_MSM_UART2)
+#define MSM_DEBUG_UART_BASE     0xE1000000
+#define MSM_DEBUG_UART_PHYS     MSM_UART2_PHYS
+#elif defined(CONFIG_DEBUG_MSM_UART3)
+#define MSM_DEBUG_UART_BASE     0xE1000000
+#define MSM_DEBUG_UART_PHYS     MSM_UART3_PHYS
+#endif
+#ifdef CONFIG_DEBUG_MSM8660_UART
+#define MSM_DEBUG_UART_BASE     0xF0040000
+#define MSM_DEBUG_UART_PHYS     0x19C40000
+#endif
+#ifdef CONFIG_DEBUG_MSM8960_UART
+#define MSM_DEBUG_UART_BASE     0xF0040000
+#define MSM_DEBUG_UART_PHYS     0x16440000
+#endif
+        .macro  addruart, rp, rv, tmp
+#ifdef MSM_DEBUG_UART_PHYS
+        ldr     \rp, =MSM_DEBUG_UART_PHYS
+        ldr     \rv, =MSM_DEBUG_UART_BASE
+#endif
+        .endm
+        .macro  senduart, rd, rx
+#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
+        @ Write the 1 character to UARTDM_TF
+        str     \rd, [\rx, #0x70]
+#else
+        str     \rd, [\rx, #0x0C]
+#endif
+        .endm
+        .macro  waituart, rd, rx
+#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
+        @ check for TX_EMT in UARTDM_SR
+        ldr     \rd, [\rx, #0x08]
+        tst     \rd, #0x08
+        bne     1002f
+        @ wait for TXREADY in UARTDM_ISR
+1001:   ldr     \rd, [\rx, #0x14]
+        tst     \rd, #0x80
+        beq     1001b
+1002:
+        @ Clear TX_READY by writing to the UARTDM_CR register
+        mov     \rd, #0x300
+        str     \rd, [\rx, #0x10]
+        @ Write 0x1 to NCF register
+        mov     \rd, #0x1
+        str     \rd, [\rx, #0x40]
+        @ UARTDM reg. Read to induce delay
+        ldr     \rd, [\rx, #0x08]
+#else
+        @ wait for TX_READY
+1001:   ldr     \rd, [\rx, #0x08]
+        tst     \rd, #0x04
+        beq     1001b
+#endif
+        .endm
+        .macro  busyuart, rd, rx
+        .endm

diff --git a/arch/arm/include/debug/msm.S b/arch/arm/include/debug/msm.S new file mode 100644 index 000000000000..9166e1bc470e --- /dev/null +++ b/arch/arm/include/debug/msm.S
@@ -0,0 +1,93 @@
	1	/*
	2	*
	3	* Copyright (C) 2007 Google, Inc.
	4	* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
	5	* Author: Brian Swetland <swetland@google.com>
	6	*
	7	* This software is licensed under the terms of the GNU General Public
	8	* License version 2, as published by the Free Software Foundation, and
	9	* may be copied, distributed, and modified under those terms.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	*/
	17
	18	#if defined(CONFIG_ARCH_MSM7X00A) \|\| defined(CONFIG_ARCH_QSD8X50)
	19	#define MSM_UART1_PHYS 0xA9A00000
	20	#define MSM_UART2_PHYS 0xA9B00000
	21	#define MSM_UART3_PHYS 0xA9C00000
	22	#elif defined(CONFIG_ARCH_MSM7X30)
	23	#define MSM_UART1_PHYS 0xACA00000
	24	#define MSM_UART2_PHYS 0xACB00000
	25	#define MSM_UART3_PHYS 0xACC00000
	26	#endif
	27
	28	#if defined(CONFIG_DEBUG_MSM_UART1)
	29	#define MSM_DEBUG_UART_BASE 0xE1000000
	30	#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
	31	#elif defined(CONFIG_DEBUG_MSM_UART2)
	32	#define MSM_DEBUG_UART_BASE 0xE1000000
	33	#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
	34	#elif defined(CONFIG_DEBUG_MSM_UART3)
	35	#define MSM_DEBUG_UART_BASE 0xE1000000
	36	#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
	37	#endif
	38
	39	#ifdef CONFIG_DEBUG_MSM8660_UART
	40	#define MSM_DEBUG_UART_BASE 0xF0040000
	41	#define MSM_DEBUG_UART_PHYS 0x19C40000
	42	#endif
	43
	44	#ifdef CONFIG_DEBUG_MSM8960_UART
	45	#define MSM_DEBUG_UART_BASE 0xF0040000
	46	#define MSM_DEBUG_UART_PHYS 0x16440000
	47	#endif
	48
	49	.macro addruart, rp, rv, tmp
	50	#ifdef MSM_DEBUG_UART_PHYS
	51	ldr \rp, =MSM_DEBUG_UART_PHYS
	52	ldr \rv, =MSM_DEBUG_UART_BASE
	53	#endif
	54	.endm
	55
	56	.macro senduart, rd, rx
	57	#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
	58	@ Write the 1 character to UARTDM_TF
	59	str \rd, [\rx, #0x70]
	60	#else
	61	str \rd, [\rx, #0x0C]
	62	#endif
	63	.endm
	64
	65	.macro waituart, rd, rx
	66	#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
	67	@ check for TX_EMT in UARTDM_SR
	68	ldr \rd, [\rx, #0x08]
	69	tst \rd, #0x08
	70	bne 1002f
	71	@ wait for TXREADY in UARTDM_ISR
	72	1001: ldr \rd, [\rx, #0x14]
	73	tst \rd, #0x80
	74	beq 1001b
	75	1002:
	76	@ Clear TX_READY by writing to the UARTDM_CR register
	77	mov \rd, #0x300
	78	str \rd, [\rx, #0x10]
	79	@ Write 0x1 to NCF register
	80	mov \rd, #0x1
	81	str \rd, [\rx, #0x40]
	82	@ UARTDM reg. Read to induce delay
	83	ldr \rd, [\rx, #0x08]
	84	#else
	85	@ wait for TX_READY
	86	1001: ldr \rd, [\rx, #0x08]
	87	tst \rd, #0x04
	88	beq 1001b
	89	#endif
	90	.endm
	91
	92	.macro busyuart, rd, rx
	93	.endm