aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/include/asm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/assembler.h17
-rw-r--r--arch/arm/include/asm/cacheflush.h4
-rw-r--r--arch/arm/include/asm/cp15.h14
-rw-r--r--arch/arm/include/asm/cputype.h46
-rw-r--r--arch/arm/include/asm/glue-cache.h27
-rw-r--r--arch/arm/include/asm/glue-df.h8
-rw-r--r--arch/arm/include/asm/glue-proc.h18
-rw-r--r--arch/arm/include/asm/hardware/pci_v3.h186
-rw-r--r--arch/arm/include/asm/irqflags.h22
-rw-r--r--arch/arm/include/asm/mach/arch.h5
-rw-r--r--arch/arm/include/asm/mach/pci.h17
-rw-r--r--arch/arm/include/asm/pgtable-nommu.h2
-rw-r--r--arch/arm/include/asm/pgtable.h7
-rw-r--r--arch/arm/include/asm/psci.h9
-rw-r--r--arch/arm/include/asm/ptrace.h4
-rw-r--r--arch/arm/include/asm/smp_plat.h2
-rw-r--r--arch/arm/include/asm/system_info.h1
-rw-r--r--arch/arm/include/asm/v7m.h44
18 files changed, 219 insertions, 214 deletions
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 05ee9eebad6b..a5fef710af32 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -136,7 +136,11 @@
136 * assumes FIQs are enabled, and that the processor is in SVC mode. 136 * assumes FIQs are enabled, and that the processor is in SVC mode.
137 */ 137 */
138 .macro save_and_disable_irqs, oldcpsr 138 .macro save_and_disable_irqs, oldcpsr
139#ifdef CONFIG_CPU_V7M
140 mrs \oldcpsr, primask
141#else
139 mrs \oldcpsr, cpsr 142 mrs \oldcpsr, cpsr
143#endif
140 disable_irq 144 disable_irq
141 .endm 145 .endm
142 146
@@ -150,7 +154,11 @@
150 * guarantee that this will preserve the flags. 154 * guarantee that this will preserve the flags.
151 */ 155 */
152 .macro restore_irqs_notrace, oldcpsr 156 .macro restore_irqs_notrace, oldcpsr
157#ifdef CONFIG_CPU_V7M
158 msr primask, \oldcpsr
159#else
153 msr cpsr_c, \oldcpsr 160 msr cpsr_c, \oldcpsr
161#endif
154 .endm 162 .endm
155 163
156 .macro restore_irqs, oldcpsr 164 .macro restore_irqs, oldcpsr
@@ -229,7 +237,14 @@
229#endif 237#endif
230 .endm 238 .endm
231 239
232#ifdef CONFIG_THUMB2_KERNEL 240#if defined(CONFIG_CPU_V7M)
241 /*
242 * setmode is used to assert to be in svc mode during boot. For v7-M
243 * this is done in __v7m_setup, so setmode can be empty here.
244 */
245 .macro setmode, mode, reg
246 .endm
247#elif defined(CONFIG_THUMB2_KERNEL)
233 .macro setmode, mode, reg 248 .macro setmode, mode, reg
234 mov \reg, #\mode 249 mov \reg, #\mode
235 msr cpsr_c, \reg 250 msr cpsr_c, \reg
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index bff71388e72a..17d0ae8672fa 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -320,9 +320,7 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
320} 320}
321 321
322#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE 322#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
323static inline void flush_kernel_dcache_page(struct page *page) 323extern void flush_kernel_dcache_page(struct page *);
324{
325}
326 324
327#define flush_dcache_mmap_lock(mapping) \ 325#define flush_dcache_mmap_lock(mapping) \
328 spin_lock_irq(&(mapping)->tree_lock) 326 spin_lock_irq(&(mapping)->tree_lock)
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index 1f3262e99d81..cedd3721318b 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -61,6 +61,20 @@ static inline void set_cr(unsigned int val)
61 isb(); 61 isb();
62} 62}
63 63
64static inline unsigned int get_auxcr(void)
65{
66 unsigned int val;
67 asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val));
68 return val;
69}
70
71static inline void set_auxcr(unsigned int val)
72{
73 asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
74 : : "r" (val));
75 isb();
76}
77
64#ifndef CONFIG_SMP 78#ifndef CONFIG_SMP
65extern void adjust_cr(unsigned long mask, unsigned long set); 79extern void adjust_cr(unsigned long mask, unsigned long set);
66#endif 80#endif
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 7652712d1d14..d7deb62554c9 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -10,6 +10,22 @@
10#define CPUID_TLBTYPE 3 10#define CPUID_TLBTYPE 3
11#define CPUID_MPIDR 5 11#define CPUID_MPIDR 5
12 12
13#ifdef CONFIG_CPU_V7M
14#define CPUID_EXT_PFR0 0x40
15#define CPUID_EXT_PFR1 0x44
16#define CPUID_EXT_DFR0 0x48
17#define CPUID_EXT_AFR0 0x4c
18#define CPUID_EXT_MMFR0 0x50
19#define CPUID_EXT_MMFR1 0x54
20#define CPUID_EXT_MMFR2 0x58
21#define CPUID_EXT_MMFR3 0x5c
22#define CPUID_EXT_ISAR0 0x60
23#define CPUID_EXT_ISAR1 0x64
24#define CPUID_EXT_ISAR2 0x68
25#define CPUID_EXT_ISAR3 0x6c
26#define CPUID_EXT_ISAR4 0x70
27#define CPUID_EXT_ISAR5 0x74
28#else
13#define CPUID_EXT_PFR0 "c1, 0" 29#define CPUID_EXT_PFR0 "c1, 0"
14#define CPUID_EXT_PFR1 "c1, 1" 30#define CPUID_EXT_PFR1 "c1, 1"
15#define CPUID_EXT_DFR0 "c1, 2" 31#define CPUID_EXT_DFR0 "c1, 2"
@@ -24,6 +40,7 @@
24#define CPUID_EXT_ISAR3 "c2, 3" 40#define CPUID_EXT_ISAR3 "c2, 3"
25#define CPUID_EXT_ISAR4 "c2, 4" 41#define CPUID_EXT_ISAR4 "c2, 4"
26#define CPUID_EXT_ISAR5 "c2, 5" 42#define CPUID_EXT_ISAR5 "c2, 5"
43#endif
27 44
28#define MPIDR_SMP_BITMASK (0x3 << 30) 45#define MPIDR_SMP_BITMASK (0x3 << 30)
29#define MPIDR_SMP_VALUE (0x2 << 30) 46#define MPIDR_SMP_VALUE (0x2 << 30)
@@ -32,6 +49,8 @@
32 49
33#define MPIDR_HWID_BITMASK 0xFFFFFF 50#define MPIDR_HWID_BITMASK 0xFFFFFF
34 51
52#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
53
35#define MPIDR_LEVEL_BITS 8 54#define MPIDR_LEVEL_BITS 8
36#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) 55#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
37 56
@@ -79,7 +98,23 @@ extern unsigned int processor_id;
79 __val; \ 98 __val; \
80 }) 99 })
81 100
82#else /* ifdef CONFIG_CPU_CP15 */ 101#elif defined(CONFIG_CPU_V7M)
102
103#include <asm/io.h>
104#include <asm/v7m.h>
105
106#define read_cpuid(reg) \
107 ({ \
108 WARN_ON_ONCE(1); \
109 0; \
110 })
111
112static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
113{
114 return readl(BASEADDR_V7M_SCB + offset);
115}
116
117#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
83 118
84/* 119/*
85 * read_cpuid and read_cpuid_ext should only ever be called on machines that 120 * read_cpuid and read_cpuid_ext should only ever be called on machines that
@@ -106,7 +141,14 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
106 return read_cpuid(CPUID_ID); 141 return read_cpuid(CPUID_ID);
107} 142}
108 143
109#else /* ifdef CONFIG_CPU_CP15 */ 144#elif defined(CONFIG_CPU_V7M)
145
146static inline unsigned int __attribute_const__ read_cpuid_id(void)
147{
148 return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
149}
150
151#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
110 152
111static inline unsigned int __attribute_const__ read_cpuid_id(void) 153static inline unsigned int __attribute_const__ read_cpuid_id(void)
112{ 154{
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index ea289e1435e7..c81adc08b3fb 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -117,10 +117,37 @@
117# endif 117# endif
118#endif 118#endif
119 119
120#if defined(CONFIG_CPU_V7M)
121# ifdef _CACHE
122# define MULTI_CACHE 1
123# else
124# define _CACHE nop
125# endif
126#endif
127
120#if !defined(_CACHE) && !defined(MULTI_CACHE) 128#if !defined(_CACHE) && !defined(MULTI_CACHE)
121#error Unknown cache maintenance model 129#error Unknown cache maintenance model
122#endif 130#endif
123 131
132#ifndef __ASSEMBLER__
133extern inline void nop_flush_icache_all(void) { }
134extern inline void nop_flush_kern_cache_all(void) { }
135extern inline void nop_flush_kern_cache_louis(void) { }
136extern inline void nop_flush_user_cache_all(void) { }
137extern inline void nop_flush_user_cache_range(unsigned long a,
138 unsigned long b, unsigned int c) { }
139
140extern inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
141extern inline int nop_coherent_user_range(unsigned long a,
142 unsigned long b) { return 0; }
143extern inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
144
145extern inline void nop_dma_flush_range(const void *a, const void *b) { }
146
147extern inline void nop_dma_map_area(const void *s, size_t l, int f) { }
148extern inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
149#endif
150
124#ifndef MULTI_CACHE 151#ifndef MULTI_CACHE
125#define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all) 152#define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all)
126#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) 153#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h
index b6e9f2c108b5..6b70f1b46a6e 100644
--- a/arch/arm/include/asm/glue-df.h
+++ b/arch/arm/include/asm/glue-df.h
@@ -95,6 +95,14 @@
95# endif 95# endif
96#endif 96#endif
97 97
98#ifdef CONFIG_CPU_ABRT_NOMMU
99# ifdef CPU_DABORT_HANDLER
100# define MULTI_DABORT 1
101# else
102# define CPU_DABORT_HANDLER nommu_early_abort
103# endif
104#endif
105
98#ifndef CPU_DABORT_HANDLER 106#ifndef CPU_DABORT_HANDLER
99#error Unknown data abort handler type 107#error Unknown data abort handler type
100#endif 108#endif
diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h
index ac1dd54724b6..e6168c0c18e9 100644
--- a/arch/arm/include/asm/glue-proc.h
+++ b/arch/arm/include/asm/glue-proc.h
@@ -230,6 +230,24 @@
230# endif 230# endif
231#endif 231#endif
232 232
233#ifdef CONFIG_CPU_PJ4B
234# ifdef CPU_NAME
235# undef MULTI_CPU
236# define MULTI_CPU
237# else
238# define CPU_NAME cpu_pj4b
239# endif
240#endif
241
242#ifdef CONFIG_CPU_V7M
243# ifdef CPU_NAME
244# undef MULTI_CPU
245# define MULTI_CPU
246# else
247# define CPU_NAME cpu_v7m
248# endif
249#endif
250
233#ifndef MULTI_CPU 251#ifndef MULTI_CPU
234#define cpu_proc_init __glue(CPU_NAME,_proc_init) 252#define cpu_proc_init __glue(CPU_NAME,_proc_init)
235#define cpu_proc_fin __glue(CPU_NAME,_proc_fin) 253#define cpu_proc_fin __glue(CPU_NAME,_proc_fin)
diff --git a/arch/arm/include/asm/hardware/pci_v3.h b/arch/arm/include/asm/hardware/pci_v3.h
deleted file mode 100644
index 2811c7e2cfdf..000000000000
--- a/arch/arm/include/asm/hardware/pci_v3.h
+++ /dev/null
@@ -1,186 +0,0 @@
1/*
2 * arch/arm/include/asm/hardware/pci_v3.h
3 *
4 * Internal header file PCI V3 chip
5 *
6 * Copyright (C) ARM Limited
7 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef ASM_ARM_HARDWARE_PCI_V3_H
24#define ASM_ARM_HARDWARE_PCI_V3_H
25
26/* -------------------------------------------------------------------------------
27 * V3 Local Bus to PCI Bridge definitions
28 * -------------------------------------------------------------------------------
29 * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
30 * All V3 register names are prefaced by V3_ to avoid clashing with any other
31 * PCI definitions. Their names match the user's manual.
32 *
33 * I'm assuming that I20 is disabled.
34 *
35 */
36#define V3_PCI_VENDOR 0x00000000
37#define V3_PCI_DEVICE 0x00000002
38#define V3_PCI_CMD 0x00000004
39#define V3_PCI_STAT 0x00000006
40#define V3_PCI_CC_REV 0x00000008
41#define V3_PCI_HDR_CFG 0x0000000C
42#define V3_PCI_IO_BASE 0x00000010
43#define V3_PCI_BASE0 0x00000014
44#define V3_PCI_BASE1 0x00000018
45#define V3_PCI_SUB_VENDOR 0x0000002C
46#define V3_PCI_SUB_ID 0x0000002E
47#define V3_PCI_ROM 0x00000030
48#define V3_PCI_BPARAM 0x0000003C
49#define V3_PCI_MAP0 0x00000040
50#define V3_PCI_MAP1 0x00000044
51#define V3_PCI_INT_STAT 0x00000048
52#define V3_PCI_INT_CFG 0x0000004C
53#define V3_LB_BASE0 0x00000054
54#define V3_LB_BASE1 0x00000058
55#define V3_LB_MAP0 0x0000005E
56#define V3_LB_MAP1 0x00000062
57#define V3_LB_BASE2 0x00000064
58#define V3_LB_MAP2 0x00000066
59#define V3_LB_SIZE 0x00000068
60#define V3_LB_IO_BASE 0x0000006E
61#define V3_FIFO_CFG 0x00000070
62#define V3_FIFO_PRIORITY 0x00000072
63#define V3_FIFO_STAT 0x00000074
64#define V3_LB_ISTAT 0x00000076
65#define V3_LB_IMASK 0x00000077
66#define V3_SYSTEM 0x00000078
67#define V3_LB_CFG 0x0000007A
68#define V3_PCI_CFG 0x0000007C
69#define V3_DMA_PCI_ADR0 0x00000080
70#define V3_DMA_PCI_ADR1 0x00000090
71#define V3_DMA_LOCAL_ADR0 0x00000084
72#define V3_DMA_LOCAL_ADR1 0x00000094
73#define V3_DMA_LENGTH0 0x00000088
74#define V3_DMA_LENGTH1 0x00000098
75#define V3_DMA_CSR0 0x0000008B
76#define V3_DMA_CSR1 0x0000009B
77#define V3_DMA_CTLB_ADR0 0x0000008C
78#define V3_DMA_CTLB_ADR1 0x0000009C
79#define V3_DMA_DELAY 0x000000E0
80#define V3_MAIL_DATA 0x000000C0
81#define V3_PCI_MAIL_IEWR 0x000000D0
82#define V3_PCI_MAIL_IERD 0x000000D2
83#define V3_LB_MAIL_IEWR 0x000000D4
84#define V3_LB_MAIL_IERD 0x000000D6
85#define V3_MAIL_WR_STAT 0x000000D8
86#define V3_MAIL_RD_STAT 0x000000DA
87#define V3_QBA_MAP 0x000000DC
88
89/* PCI COMMAND REGISTER bits
90 */
91#define V3_COMMAND_M_FBB_EN (1 << 9)
92#define V3_COMMAND_M_SERR_EN (1 << 8)
93#define V3_COMMAND_M_PAR_EN (1 << 6)
94#define V3_COMMAND_M_MASTER_EN (1 << 2)
95#define V3_COMMAND_M_MEM_EN (1 << 1)
96#define V3_COMMAND_M_IO_EN (1 << 0)
97
98/* SYSTEM REGISTER bits
99 */
100#define V3_SYSTEM_M_RST_OUT (1 << 15)
101#define V3_SYSTEM_M_LOCK (1 << 14)
102
103/* PCI_CFG bits
104 */
105#define V3_PCI_CFG_M_I2O_EN (1 << 15)
106#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
107#define V3_PCI_CFG_M_IO_DIS (1 << 13)
108#define V3_PCI_CFG_M_EN3V (1 << 12)
109#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
110#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
111#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
112
113/* PCI_BASE register bits (PCI -> Local Bus)
114 */
115#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
116#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
117#define V3_PCI_BASE_M_PREFETCH (1 << 3)
118#define V3_PCI_BASE_M_TYPE (3 << 1)
119#define V3_PCI_BASE_M_IO (1 << 0)
120
121/* PCI MAP register bits (PCI -> Local bus)
122 */
123#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
124#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
125#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
126#define V3_PCI_MAP_M_SWAP (3 << 8)
127#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
128#define V3_PCI_MAP_M_REG_EN (1 << 1)
129#define V3_PCI_MAP_M_ENABLE (1 << 0)
130
131/*
132 * LB_BASE0,1 register bits (Local bus -> PCI)
133 */
134#define V3_LB_BASE_ADR_BASE 0xfff00000
135#define V3_LB_BASE_SWAP (3 << 8)
136#define V3_LB_BASE_ADR_SIZE (15 << 4)
137#define V3_LB_BASE_PREFETCH (1 << 3)
138#define V3_LB_BASE_ENABLE (1 << 0)
139
140#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
141#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
142#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
143#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
144#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
145#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
146#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
147#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
148#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
149#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
150#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
151#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
152
153#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
154
155/*
156 * LB_MAP0,1 register bits (Local bus -> PCI)
157 */
158#define V3_LB_MAP_MAP_ADR 0xfff0
159#define V3_LB_MAP_TYPE (7 << 1)
160#define V3_LB_MAP_AD_LOW_EN (1 << 0)
161
162#define V3_LB_MAP_TYPE_IACK (0 << 1)
163#define V3_LB_MAP_TYPE_IO (1 << 1)
164#define V3_LB_MAP_TYPE_MEM (3 << 1)
165#define V3_LB_MAP_TYPE_CONFIG (5 << 1)
166#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
167
168#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
169
170/*
171 * LB_BASE2 register bits (Local bus -> PCI IO)
172 */
173#define V3_LB_BASE2_ADR_BASE 0xff00
174#define V3_LB_BASE2_SWAP (3 << 6)
175#define V3_LB_BASE2_ENABLE (1 << 0)
176
177#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
178
179/*
180 * LB_MAP2 register bits (Local bus -> PCI IO)
181 */
182#define V3_LB_MAP2_MAP_ADR 0xff00
183
184#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
185
186#endif
diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h
index 1e6cca55c750..3b763d6652a0 100644
--- a/arch/arm/include/asm/irqflags.h
+++ b/arch/arm/include/asm/irqflags.h
@@ -8,6 +8,16 @@
8/* 8/*
9 * CPU interrupt mask handling. 9 * CPU interrupt mask handling.
10 */ 10 */
11#ifdef CONFIG_CPU_V7M
12#define IRQMASK_REG_NAME_R "primask"
13#define IRQMASK_REG_NAME_W "primask"
14#define IRQMASK_I_BIT 1
15#else
16#define IRQMASK_REG_NAME_R "cpsr"
17#define IRQMASK_REG_NAME_W "cpsr_c"
18#define IRQMASK_I_BIT PSR_I_BIT
19#endif
20
11#if __LINUX_ARM_ARCH__ >= 6 21#if __LINUX_ARM_ARCH__ >= 6
12 22
13static inline unsigned long arch_local_irq_save(void) 23static inline unsigned long arch_local_irq_save(void)
@@ -15,7 +25,7 @@ static inline unsigned long arch_local_irq_save(void)
15 unsigned long flags; 25 unsigned long flags;
16 26
17 asm volatile( 27 asm volatile(
18 " mrs %0, cpsr @ arch_local_irq_save\n" 28 " mrs %0, " IRQMASK_REG_NAME_R " @ arch_local_irq_save\n"
19 " cpsid i" 29 " cpsid i"
20 : "=r" (flags) : : "memory", "cc"); 30 : "=r" (flags) : : "memory", "cc");
21 return flags; 31 return flags;
@@ -129,7 +139,7 @@ static inline unsigned long arch_local_save_flags(void)
129{ 139{
130 unsigned long flags; 140 unsigned long flags;
131 asm volatile( 141 asm volatile(
132 " mrs %0, cpsr @ local_save_flags" 142 " mrs %0, " IRQMASK_REG_NAME_R " @ local_save_flags"
133 : "=r" (flags) : : "memory", "cc"); 143 : "=r" (flags) : : "memory", "cc");
134 return flags; 144 return flags;
135} 145}
@@ -140,7 +150,7 @@ static inline unsigned long arch_local_save_flags(void)
140static inline void arch_local_irq_restore(unsigned long flags) 150static inline void arch_local_irq_restore(unsigned long flags)
141{ 151{
142 asm volatile( 152 asm volatile(
143 " msr cpsr_c, %0 @ local_irq_restore" 153 " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore"
144 : 154 :
145 : "r" (flags) 155 : "r" (flags)
146 : "memory", "cc"); 156 : "memory", "cc");
@@ -148,8 +158,8 @@ static inline void arch_local_irq_restore(unsigned long flags)
148 158
149static inline int arch_irqs_disabled_flags(unsigned long flags) 159static inline int arch_irqs_disabled_flags(unsigned long flags)
150{ 160{
151 return flags & PSR_I_BIT; 161 return flags & IRQMASK_I_BIT;
152} 162}
153 163
154#endif 164#endif /* ifdef __KERNEL__ */
155#endif 165#endif /* ifndef __ASM_ARM_IRQFLAGS_H */
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 308ad7d6f98b..75bf07910b81 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -8,6 +8,8 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#include <linux/types.h>
12
11#ifndef __ASSEMBLY__ 13#ifndef __ASSEMBLY__
12 14
13struct tag; 15struct tag;
@@ -16,8 +18,10 @@ struct pt_regs;
16struct smp_operations; 18struct smp_operations;
17#ifdef CONFIG_SMP 19#ifdef CONFIG_SMP
18#define smp_ops(ops) (&(ops)) 20#define smp_ops(ops) (&(ops))
21#define smp_init_ops(ops) (&(ops))
19#else 22#else
20#define smp_ops(ops) (struct smp_operations *)NULL 23#define smp_ops(ops) (struct smp_operations *)NULL
24#define smp_init_ops(ops) (bool (*)(void))NULL
21#endif 25#endif
22 26
23struct machine_desc { 27struct machine_desc {
@@ -41,6 +45,7 @@ struct machine_desc {
41 unsigned char reserve_lp2 :1; /* never has lp2 */ 45 unsigned char reserve_lp2 :1; /* never has lp2 */
42 char restart_mode; /* default restart mode */ 46 char restart_mode; /* default restart mode */
43 struct smp_operations *smp; /* SMP operations */ 47 struct smp_operations *smp; /* SMP operations */
48 bool (*smp_init)(void);
44 void (*fixup)(struct tag *, char **, 49 void (*fixup)(struct tag *, char **,
45 struct meminfo *); 50 struct meminfo *);
46 void (*reserve)(void);/* reserve mem blocks */ 51 void (*reserve)(void);/* reserve mem blocks */
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 7d2c3c843801..a1c90d7feb0e 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -16,6 +16,7 @@
16struct pci_sys_data; 16struct pci_sys_data;
17struct pci_ops; 17struct pci_ops;
18struct pci_bus; 18struct pci_bus;
19struct device;
19 20
20struct hw_pci { 21struct hw_pci {
21#ifdef CONFIG_PCI_DOMAINS 22#ifdef CONFIG_PCI_DOMAINS
@@ -68,7 +69,16 @@ struct pci_sys_data {
68/* 69/*
69 * Call this with your hw_pci struct to initialise the PCI system. 70 * Call this with your hw_pci struct to initialise the PCI system.
70 */ 71 */
71void pci_common_init(struct hw_pci *); 72void pci_common_init_dev(struct device *, struct hw_pci *);
73
74/*
75 * Compatibility wrapper for older platforms that do not care about
76 * passing the parent device.
77 */
78static inline void pci_common_init(struct hw_pci *hw)
79{
80 pci_common_init_dev(NULL, hw);
81}
72 82
73/* 83/*
74 * Setup early fixed I/O mapping. 84 * Setup early fixed I/O mapping.
@@ -96,9 +106,4 @@ extern struct pci_ops via82c505_ops;
96extern int via82c505_setup(int nr, struct pci_sys_data *); 106extern int via82c505_setup(int nr, struct pci_sys_data *);
97extern void via82c505_init(void *sysdata); 107extern void via82c505_init(void *sysdata);
98 108
99extern struct pci_ops pci_v3_ops;
100extern int pci_v3_setup(int nr, struct pci_sys_data *);
101extern void pci_v3_preinit(void);
102extern void pci_v3_postinit(void);
103
104#endif /* __ASM_MACH_PCI_H */ 109#endif /* __ASM_MACH_PCI_H */
diff --git a/arch/arm/include/asm/pgtable-nommu.h b/arch/arm/include/asm/pgtable-nommu.h
index 7ec60d6075bf..0642228ff785 100644
--- a/arch/arm/include/asm/pgtable-nommu.h
+++ b/arch/arm/include/asm/pgtable-nommu.h
@@ -79,8 +79,6 @@ extern unsigned int kobjsize(const void *objp);
79 * No page table caches to initialise. 79 * No page table caches to initialise.
80 */ 80 */
81#define pgtable_cache_init() do { } while (0) 81#define pgtable_cache_init() do { } while (0)
82#define io_remap_pfn_range remap_pfn_range
83
84 82
85/* 83/*
86 * All 32bit addresses are effectively valid for vmalloc... 84 * All 32bit addresses are effectively valid for vmalloc...
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 9bcd262a9008..229e0dde9c71 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -318,13 +318,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
318#define HAVE_ARCH_UNMAPPED_AREA 318#define HAVE_ARCH_UNMAPPED_AREA
319#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 319#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
320 320
321/*
322 * remap a physical page `pfn' of size `size' with page protection `prot'
323 * into virtual address `from'
324 */
325#define io_remap_pfn_range(vma,from,pfn,size,prot) \
326 remap_pfn_range(vma, from, pfn, size, prot)
327
328#define pgtable_cache_init() do { } while (0) 321#define pgtable_cache_init() do { } while (0)
329 322
330#endif /* !__ASSEMBLY__ */ 323#endif /* !__ASSEMBLY__ */
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index ce0dbe7c1625..c4ae171850f8 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -32,5 +32,14 @@ struct psci_operations {
32}; 32};
33 33
34extern struct psci_operations psci_ops; 34extern struct psci_operations psci_ops;
35extern struct smp_operations psci_smp_ops;
36
37#ifdef CONFIG_ARM_PSCI
38void psci_init(void);
39bool psci_smp_available(void);
40#else
41static inline void psci_init(void) { }
42static inline bool psci_smp_available(void) { return false; }
43#endif
35 44
36#endif /* __ASM_ARM_PSCI_H */ 45#endif /* __ASM_ARM_PSCI_H */
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 3d52ee1bfb31..04c99f36ff7f 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -45,6 +45,7 @@ struct pt_regs {
45 */ 45 */
46static inline int valid_user_regs(struct pt_regs *regs) 46static inline int valid_user_regs(struct pt_regs *regs)
47{ 47{
48#ifndef CONFIG_CPU_V7M
48 unsigned long mode = regs->ARM_cpsr & MODE_MASK; 49 unsigned long mode = regs->ARM_cpsr & MODE_MASK;
49 50
50 /* 51 /*
@@ -67,6 +68,9 @@ static inline int valid_user_regs(struct pt_regs *regs)
67 regs->ARM_cpsr |= USR_MODE; 68 regs->ARM_cpsr |= USR_MODE;
68 69
69 return 0; 70 return 0;
71#else /* ifndef CONFIG_CPU_V7M */
72 return 1;
73#endif
70} 74}
71 75
72static inline long regs_return_value(struct pt_regs *regs) 76static inline long regs_return_value(struct pt_regs *regs)
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index aaa61b6f50ff..e78983202737 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void)
49/* 49/*
50 * Logical CPU mapping. 50 * Logical CPU mapping.
51 */ 51 */
52extern int __cpu_logical_map[]; 52extern u32 __cpu_logical_map[];
53#define cpu_logical_map(cpu) __cpu_logical_map[cpu] 53#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
54/* 54/*
55 * Retrieve logical cpu index corresponding to a given MPIDR[23:0] 55 * Retrieve logical cpu index corresponding to a given MPIDR[23:0]
diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
index dfd386d0c022..720ea0320a6d 100644
--- a/arch/arm/include/asm/system_info.h
+++ b/arch/arm/include/asm/system_info.h
@@ -11,6 +11,7 @@
11#define CPU_ARCH_ARMv5TEJ 7 11#define CPU_ARCH_ARMv5TEJ 7
12#define CPU_ARCH_ARMv6 8 12#define CPU_ARCH_ARMv6 8
13#define CPU_ARCH_ARMv7 9 13#define CPU_ARCH_ARMv7 9
14#define CPU_ARCH_ARMv7M 10
14 15
15#ifndef __ASSEMBLY__ 16#ifndef __ASSEMBLY__
16 17
diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h
new file mode 100644
index 000000000000..fa88d09fa3d9
--- /dev/null
+++ b/arch/arm/include/asm/v7m.h
@@ -0,0 +1,44 @@
1/*
2 * Common defines for v7m cpus
3 */
4#define V7M_SCS_ICTR IOMEM(0xe000e004)
5#define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
6
7#define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
8
9#define V7M_SCB_CPUID 0x00
10
11#define V7M_SCB_ICSR 0x04
12#define V7M_SCB_ICSR_PENDSVSET (1 << 28)
13#define V7M_SCB_ICSR_PENDSVCLR (1 << 27)
14#define V7M_SCB_ICSR_RETTOBASE (1 << 11)
15
16#define V7M_SCB_VTOR 0x08
17
18#define V7M_SCB_SCR 0x10
19#define V7M_SCB_SCR_SLEEPDEEP (1 << 2)
20
21#define V7M_SCB_CCR 0x14
22#define V7M_SCB_CCR_STKALIGN (1 << 9)
23
24#define V7M_SCB_SHPR2 0x1c
25#define V7M_SCB_SHPR3 0x20
26
27#define V7M_SCB_SHCSR 0x24
28#define V7M_SCB_SHCSR_USGFAULTENA (1 << 18)
29#define V7M_SCB_SHCSR_BUSFAULTENA (1 << 17)
30#define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16)
31
32#define V7M_xPSR_FRAMEPTRALIGN 0x00000200
33#define V7M_xPSR_EXCEPTIONNO 0x000001ff
34
35/*
36 * When branching to an address that has bits [31:28] == 0xf an exception return
37 * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP
38 * extension Bit [4] defines if the exception frame has space allocated for FP
39 * state information, SBOP otherwise. Bit [3] defines the mode that is returned
40 * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
41 * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
42 */
43#define EXC_RET_STACK_MASK 0x00000004
44#define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 14:19:01 -0400