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-rw-r--r--arch/arm/include/asm/cputype.h1
-rw-r--r--arch/arm/include/asm/dma.h4
-rw-r--r--arch/arm/include/asm/elf.h1
-rw-r--r--arch/arm/include/asm/fpstate.h2
-rw-r--r--arch/arm/include/asm/futex.h137
-rw-r--r--arch/arm/include/asm/glue-cache.h2
-rw-r--r--arch/arm/include/asm/glue.h4
-rw-r--r--arch/arm/include/asm/hardware/pl080.h2
-rw-r--r--arch/arm/include/asm/hardware/timer-sp.h4
-rw-r--r--arch/arm/include/asm/hw_irq.h8
-rw-r--r--arch/arm/include/asm/i8253.h15
-rw-r--r--arch/arm/include/asm/kprobes.h3
-rw-r--r--arch/arm/include/asm/mach/time.h1
-rw-r--r--arch/arm/include/asm/mach/udc_pxa2xx.h2
-rw-r--r--arch/arm/include/asm/memory.h10
-rw-r--r--arch/arm/include/asm/ptrace.h6
-rw-r--r--arch/arm/include/asm/sizes.h42
-rw-r--r--arch/arm/include/asm/smp.h6
-rw-r--r--arch/arm/include/asm/spinlock.h2
-rw-r--r--arch/arm/include/asm/system.h4
-rw-r--r--arch/arm/include/asm/thread_notify.h1
-rw-r--r--arch/arm/include/asm/ucontext.h2
-rw-r--r--arch/arm/include/asm/unistd.h4
23 files changed, 143 insertions, 120 deletions
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index ed5bc9e05a4e..cd4458f64171 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -2,6 +2,7 @@
2#define __ASM_ARM_CPUTYPE_H 2#define __ASM_ARM_CPUTYPE_H
3 3
4#include <linux/stringify.h> 4#include <linux/stringify.h>
5#include <linux/kernel.h>
5 6
6#define CPUID_ID 0 7#define CPUID_ID 0
7#define CPUID_CACHETYPE 1 8#define CPUID_CACHETYPE 1
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index ca51143f97f1..42005542932b 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -6,8 +6,10 @@
6/* 6/*
7 * This is the maximum virtual address which can be DMA'd from. 7 * This is the maximum virtual address which can be DMA'd from.
8 */ 8 */
9#ifndef MAX_DMA_ADDRESS 9#ifndef ARM_DMA_ZONE_SIZE
10#define MAX_DMA_ADDRESS 0xffffffff 10#define MAX_DMA_ADDRESS 0xffffffff
11#else
12#define MAX_DMA_ADDRESS (PAGE_OFFSET + ARM_DMA_ZONE_SIZE)
11#endif 13#endif
12 14
13#ifdef CONFIG_ISA_DMA_API 15#ifdef CONFIG_ISA_DMA_API
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index c3cd8755e648..0e9ce8d9686e 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -108,6 +108,7 @@ struct task_struct;
108int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); 108int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs);
109#define ELF_CORE_COPY_TASK_REGS dump_task_regs 109#define ELF_CORE_COPY_TASK_REGS dump_task_regs
110 110
111#define CORE_DUMP_USE_REGSET
111#define ELF_EXEC_PAGESIZE 4096 112#define ELF_EXEC_PAGESIZE 4096
112 113
113/* This is the location that an ET_DYN program is loaded if exec'ed. Typical 114/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
diff --git a/arch/arm/include/asm/fpstate.h b/arch/arm/include/asm/fpstate.h
index ee5e03efc1bb..3ad4c10d0d84 100644
--- a/arch/arm/include/asm/fpstate.h
+++ b/arch/arm/include/asm/fpstate.h
@@ -18,7 +18,7 @@
18 * VFP storage area has: 18 * VFP storage area has:
19 * - FPEXC, FPSCR, FPINST and FPINST2. 19 * - FPEXC, FPSCR, FPINST and FPINST2.
20 * - 16 or 32 double precision data registers 20 * - 16 or 32 double precision data registers
21 * - an implementation-dependant word of state for FLDMX/FSTMX (pre-ARMv6) 21 * - an implementation-dependent word of state for FLDMX/FSTMX (pre-ARMv6)
22 * 22 *
23 * FPEXC will always be non-zero once the VFP has been used in this process. 23 * FPEXC will always be non-zero once the VFP has been used in this process.
24 */ 24 */
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 199a6b6de7f4..8c73900da9ed 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -3,16 +3,74 @@
3 3
4#ifdef __KERNEL__ 4#ifdef __KERNEL__
5 5
6#if defined(CONFIG_CPU_USE_DOMAINS) && defined(CONFIG_SMP)
7/* ARM doesn't provide unprivileged exclusive memory accessors */
8#include <asm-generic/futex.h>
9#else
10
11#include <linux/futex.h>
12#include <linux/uaccess.h>
13#include <asm/errno.h>
14
15#define __futex_atomic_ex_table(err_reg) \
16 "3:\n" \
17 " .pushsection __ex_table,\"a\"\n" \
18 " .align 3\n" \
19 " .long 1b, 4f, 2b, 4f\n" \
20 " .popsection\n" \
21 " .pushsection .fixup,\"ax\"\n" \
22 "4: mov %0, " err_reg "\n" \
23 " b 3b\n" \
24 " .popsection"
25
6#ifdef CONFIG_SMP 26#ifdef CONFIG_SMP
7 27
8#include <asm-generic/futex.h> 28#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
29 smp_mb(); \
30 __asm__ __volatile__( \
31 "1: ldrex %1, [%2]\n" \
32 " " insn "\n" \
33 "2: strex %1, %0, [%2]\n" \
34 " teq %1, #0\n" \
35 " bne 1b\n" \
36 " mov %0, #0\n" \
37 __futex_atomic_ex_table("%4") \
38 : "=&r" (ret), "=&r" (oldval) \
39 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
40 : "cc", "memory")
41
42static inline int
43futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
44 u32 oldval, u32 newval)
45{
46 int ret;
47 u32 val;
48
49 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
50 return -EFAULT;
51
52 smp_mb();
53 __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
54 "1: ldrex %1, [%4]\n"
55 " teq %1, %2\n"
56 " ite eq @ explicit IT needed for the 2b label\n"
57 "2: strexeq %0, %3, [%4]\n"
58 " movne %0, #0\n"
59 " teq %0, #0\n"
60 " bne 1b\n"
61 __futex_atomic_ex_table("%5")
62 : "=&r" (ret), "=&r" (val)
63 : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
64 : "cc", "memory");
65 smp_mb();
66
67 *uval = val;
68 return ret;
69}
9 70
10#else /* !SMP, we can work around lack of atomic ops by disabling preemption */ 71#else /* !SMP, we can work around lack of atomic ops by disabling preemption */
11 72
12#include <linux/futex.h>
13#include <linux/preempt.h> 73#include <linux/preempt.h>
14#include <linux/uaccess.h>
15#include <asm/errno.h>
16#include <asm/domain.h> 74#include <asm/domain.h>
17 75
18#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 76#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
@@ -21,20 +79,38 @@
21 " " insn "\n" \ 79 " " insn "\n" \
22 "2: " T(str) " %0, [%2]\n" \ 80 "2: " T(str) " %0, [%2]\n" \
23 " mov %0, #0\n" \ 81 " mov %0, #0\n" \
24 "3:\n" \ 82 __futex_atomic_ex_table("%4") \
25 " .pushsection __ex_table,\"a\"\n" \
26 " .align 3\n" \
27 " .long 1b, 4f, 2b, 4f\n" \
28 " .popsection\n" \
29 " .pushsection .fixup,\"ax\"\n" \
30 "4: mov %0, %4\n" \
31 " b 3b\n" \
32 " .popsection" \
33 : "=&r" (ret), "=&r" (oldval) \ 83 : "=&r" (ret), "=&r" (oldval) \
34 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ 84 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
35 : "cc", "memory") 85 : "cc", "memory")
36 86
37static inline int 87static inline int
88futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
89 u32 oldval, u32 newval)
90{
91 int ret = 0;
92 u32 val;
93
94 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
95 return -EFAULT;
96
97 __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
98 "1: " T(ldr) " %1, [%4]\n"
99 " teq %1, %2\n"
100 " it eq @ explicit IT needed for the 2b label\n"
101 "2: " T(streq) " %3, [%4]\n"
102 __futex_atomic_ex_table("%5")
103 : "+r" (ret), "=&r" (val)
104 : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
105 : "cc", "memory");
106
107 *uval = val;
108 return ret;
109}
110
111#endif /* !SMP */
112
113static inline int
38futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) 114futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
39{ 115{
40 int op = (encoded_op >> 28) & 7; 116 int op = (encoded_op >> 28) & 7;
@@ -87,39 +163,6 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
87 return ret; 163 return ret;
88} 164}
89 165
90static inline int 166#endif /* !(CPU_USE_DOMAINS && SMP) */
91futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
92 u32 oldval, u32 newval)
93{
94 int ret = 0;
95 u32 val;
96
97 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
98 return -EFAULT;
99
100 __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
101 "1: " T(ldr) " %1, [%4]\n"
102 " teq %1, %2\n"
103 " it eq @ explicit IT needed for the 2b label\n"
104 "2: " T(streq) " %3, [%4]\n"
105 "3:\n"
106 " .pushsection __ex_table,\"a\"\n"
107 " .align 3\n"
108 " .long 1b, 4f, 2b, 4f\n"
109 " .popsection\n"
110 " .pushsection .fixup,\"ax\"\n"
111 "4: mov %0, %5\n"
112 " b 3b\n"
113 " .popsection"
114 : "+r" (ret), "=&r" (val)
115 : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
116 : "cc", "memory");
117
118 *uval = val;
119 return ret;
120}
121
122#endif /* !SMP */
123
124#endif /* __KERNEL__ */ 167#endif /* __KERNEL__ */
125#endif /* _ASM_ARM_FUTEX_H */ 168#endif /* _ASM_ARM_FUTEX_H */
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index c7afbc552c7f..7e30874377e6 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -126,7 +126,7 @@
126#endif 126#endif
127 127
128#if !defined(_CACHE) && !defined(MULTI_CACHE) 128#if !defined(_CACHE) && !defined(MULTI_CACHE)
129#error Unknown cache maintainence model 129#error Unknown cache maintenance model
130#endif 130#endif
131 131
132#ifndef MULTI_CACHE 132#ifndef MULTI_CACHE
diff --git a/arch/arm/include/asm/glue.h b/arch/arm/include/asm/glue.h
index 0ec35d1698aa..fbf71d75ec83 100644
--- a/arch/arm/include/asm/glue.h
+++ b/arch/arm/include/asm/glue.h
@@ -10,8 +10,8 @@
10 * 10 *
11 * This file provides the glue to stick the processor-specific bits 11 * This file provides the glue to stick the processor-specific bits
12 * into the kernel in an efficient manner. The idea is to use branches 12 * into the kernel in an efficient manner. The idea is to use branches
13 * when we're only targetting one class of TLB, or indirect calls 13 * when we're only targeting one class of TLB, or indirect calls
14 * when we're targetting multiple classes of TLBs. 14 * when we're targeting multiple classes of TLBs.
15 */ 15 */
16#ifdef __KERNEL__ 16#ifdef __KERNEL__
17 17
diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
index f35b86e68dd5..e4a04e4e5627 100644
--- a/arch/arm/include/asm/hardware/pl080.h
+++ b/arch/arm/include/asm/hardware/pl080.h
@@ -16,7 +16,7 @@
16 * make it not entierly compatible with the PL080 specification from 16 * make it not entierly compatible with the PL080 specification from
17 * ARM. When in doubt, check the Samsung documentation first. 17 * ARM. When in doubt, check the Samsung documentation first.
18 * 18 *
19 * The Samsung defines are PL080S, and add an extra controll register, 19 * The Samsung defines are PL080S, and add an extra control register,
20 * the ability to move more than 2^11 counts of data and some extra 20 * the ability to move more than 2^11 counts of data and some extra
21 * OneNAND features. 21 * OneNAND features.
22*/ 22*/
diff --git a/arch/arm/include/asm/hardware/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h
index 21e75e30d497..4384d81eee79 100644
--- a/arch/arm/include/asm/hardware/timer-sp.h
+++ b/arch/arm/include/asm/hardware/timer-sp.h
@@ -1,2 +1,2 @@
1void sp804_clocksource_init(void __iomem *); 1void sp804_clocksource_init(void __iomem *, const char *);
2void sp804_clockevents_init(void __iomem *, unsigned int); 2void sp804_clockevents_init(void __iomem *, unsigned int, const char *);
diff --git a/arch/arm/include/asm/hw_irq.h b/arch/arm/include/asm/hw_irq.h
index 5586b7c8ef6f..a71b417b1856 100644
--- a/arch/arm/include/asm/hw_irq.h
+++ b/arch/arm/include/asm/hw_irq.h
@@ -10,14 +10,6 @@ static inline void ack_bad_irq(int irq)
10 irq_err_count++; 10 irq_err_count++;
11} 11}
12 12
13/*
14 * Obsolete inline function for calling irq descriptor handlers.
15 */
16static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc)
17{
18 desc->handle_irq(irq, desc);
19}
20
21void set_irq_flags(unsigned int irq, unsigned int flags); 13void set_irq_flags(unsigned int irq, unsigned int flags);
22 14
23#define IRQF_VALID (1 << 0) 15#define IRQF_VALID (1 << 0)
diff --git a/arch/arm/include/asm/i8253.h b/arch/arm/include/asm/i8253.h
new file mode 100644
index 000000000000..70656b69d5ce
--- /dev/null
+++ b/arch/arm/include/asm/i8253.h
@@ -0,0 +1,15 @@
1#ifndef __ASMARM_I8253_H
2#define __ASMARM_I8253_H
3
4/* i8253A PIT registers */
5#define PIT_MODE 0x43
6#define PIT_CH0 0x40
7
8#define PIT_LATCH ((PIT_TICK_RATE + HZ / 2) / HZ)
9
10extern raw_spinlock_t i8253_lock;
11
12#define outb_pit outb_p
13#define inb_pit inb_p
14
15#endif
diff --git a/arch/arm/include/asm/kprobes.h b/arch/arm/include/asm/kprobes.h
index bb8a19bd5822..e46bdd0097eb 100644
--- a/arch/arm/include/asm/kprobes.h
+++ b/arch/arm/include/asm/kprobes.h
@@ -39,10 +39,13 @@ typedef u32 kprobe_opcode_t;
39struct kprobe; 39struct kprobe;
40typedef void (kprobe_insn_handler_t)(struct kprobe *, struct pt_regs *); 40typedef void (kprobe_insn_handler_t)(struct kprobe *, struct pt_regs *);
41 41
42typedef unsigned long (kprobe_check_cc)(unsigned long);
43
42/* Architecture specific copy of original instruction. */ 44/* Architecture specific copy of original instruction. */
43struct arch_specific_insn { 45struct arch_specific_insn {
44 kprobe_opcode_t *insn; 46 kprobe_opcode_t *insn;
45 kprobe_insn_handler_t *insn_handler; 47 kprobe_insn_handler_t *insn_handler;
48 kprobe_check_cc *insn_check_cc;
46}; 49};
47 50
48struct prev_kprobe { 51struct prev_kprobe {
diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h
index 883f6be5117a..d5adaae5ee2c 100644
--- a/arch/arm/include/asm/mach/time.h
+++ b/arch/arm/include/asm/mach/time.h
@@ -34,7 +34,6 @@
34 * timer interrupt which may be pending. 34 * timer interrupt which may be pending.
35 */ 35 */
36struct sys_timer { 36struct sys_timer {
37 struct sys_device dev;
38 void (*init)(void); 37 void (*init)(void);
39 void (*suspend)(void); 38 void (*suspend)(void);
40 void (*resume)(void); 39 void (*resume)(void);
diff --git a/arch/arm/include/asm/mach/udc_pxa2xx.h b/arch/arm/include/asm/mach/udc_pxa2xx.h
index 833306ee9e7f..ea297ac70bc6 100644
--- a/arch/arm/include/asm/mach/udc_pxa2xx.h
+++ b/arch/arm/include/asm/mach/udc_pxa2xx.h
@@ -20,8 +20,6 @@ struct pxa2xx_udc_mach_info {
20 * VBUS IRQ and omit the methods above. Store the GPIO number 20 * VBUS IRQ and omit the methods above. Store the GPIO number
21 * here. Note that sometimes the signals go through inverters... 21 * here. Note that sometimes the signals go through inverters...
22 */ 22 */
23 bool gpio_vbus_inverted;
24 int gpio_vbus; /* high == vbus present */
25 bool gpio_pullup_inverted; 23 bool gpio_pullup_inverted;
26 int gpio_pullup; /* high == pullup activated */ 24 int gpio_pullup; /* high == pullup activated */
27}; 25};
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 431077c5a867..af44a8fb3480 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -209,14 +209,10 @@ static inline unsigned long __phys_to_virt(unsigned long x)
209 * allocations. This must be the smallest DMA mask in the system, 209 * allocations. This must be the smallest DMA mask in the system,
210 * so a successful GFP_DMA allocation will always satisfy this. 210 * so a successful GFP_DMA allocation will always satisfy this.
211 */ 211 */
212#ifndef ISA_DMA_THRESHOLD 212#ifndef ARM_DMA_ZONE_SIZE
213#define ISA_DMA_THRESHOLD (0xffffffffULL) 213#define ISA_DMA_THRESHOLD (0xffffffffULL)
214#endif 214#else
215 215#define ISA_DMA_THRESHOLD (PHYS_OFFSET + ARM_DMA_ZONE_SIZE - 1)
216#ifndef arch_adjust_zones
217#define arch_adjust_zones(size,holes) do { } while (0)
218#elif !defined(CONFIG_ZONE_DMA)
219#error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA"
220#endif 216#endif
221 217
222/* 218/*
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index a8ff22b2a391..312d10877bd7 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -128,6 +128,12 @@ struct pt_regs {
128#define ARM_r0 uregs[0] 128#define ARM_r0 uregs[0]
129#define ARM_ORIG_r0 uregs[17] 129#define ARM_ORIG_r0 uregs[17]
130 130
131/*
132 * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS
133 * and core dumps.
134 */
135#define ARM_VFPREGS_SIZE ( 32 * 8 /*fpregs*/ + 4 /*fpscr*/ )
136
131#ifdef __KERNEL__ 137#ifdef __KERNEL__
132 138
133#define user_mode(regs) \ 139#define user_mode(regs) \
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
index 316bb2b2be3d..154b89b81d3e 100644
--- a/arch/arm/include/asm/sizes.h
+++ b/arch/arm/include/asm/sizes.h
@@ -16,44 +16,6 @@
16/* Size definitions 16/* Size definitions
17 * Copyright (C) ARM Limited 1998. All rights reserved. 17 * Copyright (C) ARM Limited 1998. All rights reserved.
18 */ 18 */
19#include <asm-generic/sizes.h>
19 20
20#ifndef __sizes_h 21#define SZ_48M (SZ_32M + SZ_16M)
21#define __sizes_h 1
22
23/* handy sizes */
24#define SZ_16 0x00000010
25#define SZ_32 0x00000020
26#define SZ_64 0x00000040
27#define SZ_128 0x00000080
28#define SZ_256 0x00000100
29#define SZ_512 0x00000200
30
31#define SZ_1K 0x00000400
32#define SZ_2K 0x00000800
33#define SZ_4K 0x00001000
34#define SZ_8K 0x00002000
35#define SZ_16K 0x00004000
36#define SZ_32K 0x00008000
37#define SZ_64K 0x00010000
38#define SZ_128K 0x00020000
39#define SZ_256K 0x00040000
40#define SZ_512K 0x00080000
41
42#define SZ_1M 0x00100000
43#define SZ_2M 0x00200000
44#define SZ_4M 0x00400000
45#define SZ_8M 0x00800000
46#define SZ_16M 0x01000000
47#define SZ_32M 0x02000000
48#define SZ_48M 0x03000000
49#define SZ_64M 0x04000000
50#define SZ_128M 0x08000000
51#define SZ_256M 0x10000000
52#define SZ_512M 0x20000000
53
54#define SZ_1G 0x40000000
55#define SZ_2G 0x80000000
56
57#endif
58
59/* END */
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 96ed521f2408..a87664f54f93 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -14,8 +14,6 @@
14#include <linux/cpumask.h> 14#include <linux/cpumask.h>
15#include <linux/thread_info.h> 15#include <linux/thread_info.h>
16 16
17#include <mach/smp.h>
18
19#ifndef CONFIG_SMP 17#ifndef CONFIG_SMP
20# error "<asm/smp.h> included in non-SMP build" 18# error "<asm/smp.h> included in non-SMP build"
21#endif 19#endif
@@ -47,9 +45,9 @@ extern void smp_init_cpus(void);
47 45
48 46
49/* 47/*
50 * Raise an IPI cross call on CPUs in callmap. 48 * Provide a function to raise an IPI cross call on CPUs in callmap.
51 */ 49 */
52extern void smp_cross_call(const struct cpumask *mask, int ipi); 50extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
53 51
54/* 52/*
55 * Boot a secondary CPU, and assign it the specified idle task. 53 * Boot a secondary CPU, and assign it the specified idle task.
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index fdd3820edff8..65fa3c88095c 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -5,6 +5,8 @@
5#error SMP not supported on pre-ARMv6 CPUs 5#error SMP not supported on pre-ARMv6 CPUs
6#endif 6#endif
7 7
8#include <asm/processor.h>
9
8/* 10/*
9 * sev and wfe are ARMv6K extensions. Uniprocessor ARMv6 may not have the K 11 * sev and wfe are ARMv6K extensions. Uniprocessor ARMv6 may not have the K
10 * extensions, so when running on UP, we have to patch these instructions away. 12 * extensions, so when running on UP, we have to patch these instructions away.
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 9a87823642d0..832888d0c20c 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -159,7 +159,7 @@ extern unsigned int user_debug;
159#include <mach/barriers.h> 159#include <mach/barriers.h>
160#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP) 160#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
161#define mb() do { dsb(); outer_sync(); } while (0) 161#define mb() do { dsb(); outer_sync(); } while (0)
162#define rmb() dmb() 162#define rmb() dsb()
163#define wmb() mb() 163#define wmb() mb()
164#else 164#else
165#include <asm/memory.h> 165#include <asm/memory.h>
@@ -249,7 +249,7 @@ do { \
249 * cache totally. This means that the cache becomes inconsistent, and, 249 * cache totally. This means that the cache becomes inconsistent, and,
250 * since we use normal loads/stores as well, this is really bad. 250 * since we use normal loads/stores as well, this is really bad.
251 * Typically, this causes oopsen in filp_close, but could have other, 251 * Typically, this causes oopsen in filp_close, but could have other,
252 * more disasterous effects. There are two work-arounds: 252 * more disastrous effects. There are two work-arounds:
253 * 1. Disable interrupts and emulate the atomic swap 253 * 1. Disable interrupts and emulate the atomic swap
254 * 2. Clean the cache, perform atomic swap, flush the cache 254 * 2. Clean the cache, perform atomic swap, flush the cache
255 * 255 *
diff --git a/arch/arm/include/asm/thread_notify.h b/arch/arm/include/asm/thread_notify.h
index c4391ba20350..1dc980675894 100644
--- a/arch/arm/include/asm/thread_notify.h
+++ b/arch/arm/include/asm/thread_notify.h
@@ -43,6 +43,7 @@ static inline void thread_notify(unsigned long rc, struct thread_info *thread)
43#define THREAD_NOTIFY_FLUSH 0 43#define THREAD_NOTIFY_FLUSH 0
44#define THREAD_NOTIFY_EXIT 1 44#define THREAD_NOTIFY_EXIT 1
45#define THREAD_NOTIFY_SWITCH 2 45#define THREAD_NOTIFY_SWITCH 2
46#define THREAD_NOTIFY_COPY 3
46 47
47#endif 48#endif
48#endif 49#endif
diff --git a/arch/arm/include/asm/ucontext.h b/arch/arm/include/asm/ucontext.h
index 47f023aa8495..14749aec94bf 100644
--- a/arch/arm/include/asm/ucontext.h
+++ b/arch/arm/include/asm/ucontext.h
@@ -47,7 +47,7 @@ struct crunch_sigframe {
47#endif 47#endif
48 48
49#ifdef CONFIG_IWMMXT 49#ifdef CONFIG_IWMMXT
50/* iwmmxt_area is 0x98 bytes long, preceeded by 8 bytes of signature */ 50/* iwmmxt_area is 0x98 bytes long, preceded by 8 bytes of signature */
51#define IWMMXT_MAGIC 0x12ef842a 51#define IWMMXT_MAGIC 0x12ef842a
52#define IWMMXT_STORAGE_SIZE (IWMMXT_SIZE + 8) 52#define IWMMXT_STORAGE_SIZE (IWMMXT_SIZE + 8)
53 53
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index c891eb76c0e3..87dbe3e21970 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -396,6 +396,10 @@
396#define __NR_fanotify_init (__NR_SYSCALL_BASE+367) 396#define __NR_fanotify_init (__NR_SYSCALL_BASE+367)
397#define __NR_fanotify_mark (__NR_SYSCALL_BASE+368) 397#define __NR_fanotify_mark (__NR_SYSCALL_BASE+368)
398#define __NR_prlimit64 (__NR_SYSCALL_BASE+369) 398#define __NR_prlimit64 (__NR_SYSCALL_BASE+369)
399#define __NR_name_to_handle_at (__NR_SYSCALL_BASE+370)
400#define __NR_open_by_handle_at (__NR_SYSCALL_BASE+371)
401#define __NR_clock_adjtime (__NR_SYSCALL_BASE+372)
402#define __NR_syncfs (__NR_SYSCALL_BASE+373)
399 403
400/* 404/*
401 * The following SWIs are ARM private. 405 * The following SWIs are ARM private.
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 15:52:37 -0500