aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/include/asm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/cputype.h25
-rw-r--r--arch/arm/include/asm/hardware/arm_twd.h21
-rw-r--r--arch/arm/include/asm/hardware/cache-l2x0.h2
-rw-r--r--arch/arm/include/asm/hardware/pl080.h138
-rw-r--r--arch/arm/include/asm/hardware/sharpsl_pm.h106
-rw-r--r--arch/arm/include/asm/hardware/vic.h2
-rw-r--r--arch/arm/include/asm/localtimer.h63
-rw-r--r--arch/arm/include/asm/mach/map.h8
-rw-r--r--arch/arm/include/asm/pgtable.h2
-rw-r--r--arch/arm/include/asm/processor.h1
-rw-r--r--arch/arm/include/asm/ptrace.h17
-rw-r--r--arch/arm/include/asm/sizes.h1
-rw-r--r--arch/arm/include/asm/smp.h42
-rw-r--r--arch/arm/include/asm/smp_scu.h7
-rw-r--r--arch/arm/include/asm/smp_twd.h12
-rw-r--r--arch/arm/include/asm/tlbflush.h26
-rw-r--r--arch/arm/include/asm/uaccess.h2
17 files changed, 303 insertions, 172 deletions
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 7b9d27e749b8..b3e656c6fb78 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -8,6 +8,21 @@
8#define CPUID_TCM 2 8#define CPUID_TCM 2
9#define CPUID_TLBTYPE 3 9#define CPUID_TLBTYPE 3
10 10
11#define CPUID_EXT_PFR0 "c1, 0"
12#define CPUID_EXT_PFR1 "c1, 1"
13#define CPUID_EXT_DFR0 "c1, 2"
14#define CPUID_EXT_AFR0 "c1, 3"
15#define CPUID_EXT_MMFR0 "c1, 4"
16#define CPUID_EXT_MMFR1 "c1, 5"
17#define CPUID_EXT_MMFR2 "c1, 6"
18#define CPUID_EXT_MMFR3 "c1, 7"
19#define CPUID_EXT_ISAR0 "c2, 0"
20#define CPUID_EXT_ISAR1 "c2, 1"
21#define CPUID_EXT_ISAR2 "c2, 2"
22#define CPUID_EXT_ISAR3 "c2, 3"
23#define CPUID_EXT_ISAR4 "c2, 4"
24#define CPUID_EXT_ISAR5 "c2, 5"
25
11#ifdef CONFIG_CPU_CP15 26#ifdef CONFIG_CPU_CP15
12#define read_cpuid(reg) \ 27#define read_cpuid(reg) \
13 ({ \ 28 ({ \
@@ -18,9 +33,19 @@
18 : "cc"); \ 33 : "cc"); \
19 __val; \ 34 __val; \
20 }) 35 })
36#define read_cpuid_ext(ext_reg) \
37 ({ \
38 unsigned int __val; \
39 asm("mrc p15, 0, %0, c0, " ext_reg \
40 : "=r" (__val) \
41 : \
42 : "cc"); \
43 __val; \
44 })
21#else 45#else
22extern unsigned int processor_id; 46extern unsigned int processor_id;
23#define read_cpuid(reg) (processor_id) 47#define read_cpuid(reg) (processor_id)
48#define read_cpuid_ext(reg) 0
24#endif 49#endif
25 50
26/* 51/*
diff --git a/arch/arm/include/asm/hardware/arm_twd.h b/arch/arm/include/asm/hardware/arm_twd.h
deleted file mode 100644
index e521b70713c8..000000000000
--- a/arch/arm/include/asm/hardware/arm_twd.h
+++ /dev/null
@@ -1,21 +0,0 @@
1#ifndef __ASM_HARDWARE_TWD_H
2#define __ASM_HARDWARE_TWD_H
3
4#define TWD_TIMER_LOAD 0x00
5#define TWD_TIMER_COUNTER 0x04
6#define TWD_TIMER_CONTROL 0x08
7#define TWD_TIMER_INTSTAT 0x0C
8
9#define TWD_WDOG_LOAD 0x20
10#define TWD_WDOG_COUNTER 0x24
11#define TWD_WDOG_CONTROL 0x28
12#define TWD_WDOG_INTSTAT 0x2C
13#define TWD_WDOG_RESETSTAT 0x30
14#define TWD_WDOG_DISABLE 0x34
15
16#define TWD_TIMER_CONTROL_ENABLE (1 << 0)
17#define TWD_TIMER_CONTROL_ONESHOT (0 << 1)
18#define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
19#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
20
21#endif
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 64f2252a25cd..cdb9022716fd 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -24,6 +24,8 @@
24#define L2X0_CACHE_TYPE 0x004 24#define L2X0_CACHE_TYPE 0x004
25#define L2X0_CTRL 0x100 25#define L2X0_CTRL 0x100
26#define L2X0_AUX_CTRL 0x104 26#define L2X0_AUX_CTRL 0x104
27#define L2X0_TAG_LATENCY_CTRL 0x108
28#define L2X0_DATA_LATENCY_CTRL 0x10C
27#define L2X0_EVENT_CNT_CTRL 0x200 29#define L2X0_EVENT_CNT_CTRL 0x200
28#define L2X0_EVENT_CNT1_CFG 0x204 30#define L2X0_EVENT_CNT1_CFG 0x204
29#define L2X0_EVENT_CNT0_CFG 0x208 31#define L2X0_EVENT_CNT0_CFG 0x208
diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
new file mode 100644
index 000000000000..6a6c66be7f65
--- /dev/null
+++ b/arch/arm/include/asm/hardware/pl080.h
@@ -0,0 +1,138 @@
1/* arch/arm/include/asm/hardware/pl080.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * ARM PrimeCell PL080 DMA controller
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Note, there are some Samsung updates to this controller block which
16 * make it not entierly compatible with the PL080 specification from
17 * ARM. When in doubt, check the Samsung documentation first.
18 *
19 * The Samsung defines are PL080S, and add an extra controll register,
20 * the ability to move more than 2^11 counts of data and some extra
21 * OneNAND features.
22*/
23
24#define PL080_INT_STATUS (0x00)
25#define PL080_TC_STATUS (0x04)
26#define PL080_TC_CLEAR (0x08)
27#define PL080_ERR_STATUS (0x0C)
28#define PL080_ERR_CLEAR (0x10)
29#define PL080_RAW_TC_STATUS (0x14)
30#define PL080_RAW_ERR_STATUS (0x18)
31#define PL080_EN_CHAN (0x1c)
32#define PL080_SOFT_BREQ (0x20)
33#define PL080_SOFT_SREQ (0x24)
34#define PL080_SOFT_LBREQ (0x28)
35#define PL080_SOFT_LSREQ (0x2C)
36
37#define PL080_CONFIG (0x30)
38#define PL080_CONFIG_M2_BE (1 << 2)
39#define PL080_CONFIG_M1_BE (1 << 1)
40#define PL080_CONFIG_ENABLE (1 << 0)
41
42#define PL080_SYNC (0x34)
43
44/* Per channel configuration registers */
45
46#define PL008_Cx_STRIDE (0x20)
47#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
48#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20)))
49#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20)))
50#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20)))
51#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20)))
52#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20)))
53#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20)))
54#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20)))
55
56#define PL080_CH_SRC_ADDR (0x00)
57#define PL080_CH_DST_ADDR (0x04)
58#define PL080_CH_LLI (0x08)
59#define PL080_CH_CONTROL (0x0C)
60#define PL080_CH_CONFIG (0x10)
61#define PL080S_CH_CONTROL2 (0x10)
62#define PL080S_CH_CONFIG (0x14)
63
64#define PL080_LLI_ADDR_MASK (0x3fffffff << 2)
65#define PL080_LLI_ADDR_SHIFT (2)
66#define PL080_LLI_LM_AHB2 (1 << 0)
67
68#define PL080_CONTROL_TC_IRQ_EN (1 << 31)
69#define PL080_CONTROL_PROT_MASK (0x7 << 28)
70#define PL080_CONTROL_PROT_SHIFT (28)
71#define PL080_CONTROL_PROT_SYS (1 << 28)
72#define PL080_CONTROL_DST_INCR (1 << 27)
73#define PL080_CONTROL_SRC_INCR (1 << 26)
74#define PL080_CONTROL_DST_AHB2 (1 << 25)
75#define PL080_CONTROL_SRC_AHB2 (1 << 24)
76#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21)
77#define PL080_CONTROL_DWIDTH_SHIFT (21)
78#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18)
79#define PL080_CONTROL_SWIDTH_SHIFT (18)
80#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15)
81#define PL080_CONTROL_DB_SIZE_SHIFT (15)
82#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12)
83#define PL080_CONTROL_SB_SIZE_SHIFT (12)
84#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0)
85#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
86
87#define PL080_BSIZE_1 (0x0)
88#define PL080_BSIZE_4 (0x1)
89#define PL080_BSIZE_8 (0x2)
90#define PL080_BSIZE_16 (0x3)
91#define PL080_BSIZE_32 (0x4)
92#define PL080_BSIZE_64 (0x5)
93#define PL080_BSIZE_128 (0x6)
94#define PL080_BSIZE_256 (0x7)
95
96#define PL080_WIDTH_8BIT (0x0)
97#define PL080_WIDTH_16BIT (0x1)
98#define PL080_WIDTH_32BIT (0x2)
99
100#define PL080_CONFIG_HALT (1 << 18)
101#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */
102#define PL080_CONFIG_LOCK (1 << 16)
103#define PL080_CONFIG_TC_IRQ_MASK (1 << 15)
104#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14)
105#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11)
106#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
107#define PL080_CONFIG_DST_SEL_MASK (0xf << 6)
108#define PL080_CONFIG_DST_SEL_SHIFT (6)
109#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1)
110#define PL080_CONFIG_SRC_SEL_SHIFT (1)
111#define PL080_CONFIG_ENABLE (1 << 0)
112
113#define PL080_FLOW_MEM2MEM (0x0)
114#define PL080_FLOW_MEM2PER (0x1)
115#define PL080_FLOW_PER2MEM (0x2)
116#define PL080_FLOW_SRC2DST (0x3)
117#define PL080_FLOW_SRC2DST_DST (0x4)
118#define PL080_FLOW_MEM2PER_PER (0x5)
119#define PL080_FLOW_PER2MEM_PER (0x6)
120#define PL080_FLOW_SRC2DST_SRC (0x7)
121
122/* DMA linked list chain structure */
123
124struct pl080_lli {
125 u32 src_addr;
126 u32 dst_addr;
127 u32 next_lli;
128 u32 control0;
129};
130
131struct pl080s_lli {
132 u32 src_addr;
133 u32 dst_addr;
134 u32 next_lli;
135 u32 control0;
136 u32 control1;
137};
138
diff --git a/arch/arm/include/asm/hardware/sharpsl_pm.h b/arch/arm/include/asm/hardware/sharpsl_pm.h
deleted file mode 100644
index 2d00db22b981..000000000000
--- a/arch/arm/include/asm/hardware/sharpsl_pm.h
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * SharpSL Battery/PM Driver
3 *
4 * Copyright (c) 2004-2005 Richard Purdie
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/interrupt.h>
13
14struct sharpsl_charger_machinfo {
15 void (*init)(void);
16 void (*exit)(void);
17 int gpio_acin;
18 int gpio_batfull;
19 int batfull_irq;
20 int gpio_batlock;
21 int gpio_fatal;
22 void (*discharge)(int);
23 void (*discharge1)(int);
24 void (*charge)(int);
25 void (*measure_temp)(int);
26 void (*presuspend)(void);
27 void (*postsuspend)(void);
28 void (*earlyresume)(void);
29 unsigned long (*read_devdata)(int);
30#define SHARPSL_BATT_VOLT 1
31#define SHARPSL_BATT_TEMP 2
32#define SHARPSL_ACIN_VOLT 3
33#define SHARPSL_STATUS_ACIN 4
34#define SHARPSL_STATUS_LOCK 5
35#define SHARPSL_STATUS_CHRGFULL 6
36#define SHARPSL_STATUS_FATAL 7
37 unsigned long (*charger_wakeup)(void);
38 int (*should_wakeup)(unsigned int resume_on_alarm);
39 void (*backlight_limit)(int);
40 int (*backlight_get_status) (void);
41 int charge_on_volt;
42 int charge_on_temp;
43 int charge_acin_high;
44 int charge_acin_low;
45 int fatal_acin_volt;
46 int fatal_noacin_volt;
47 int bat_levels;
48 struct battery_thresh *bat_levels_noac;
49 struct battery_thresh *bat_levels_acin;
50 struct battery_thresh *bat_levels_noac_bl;
51 struct battery_thresh *bat_levels_acin_bl;
52 int status_high_acin;
53 int status_low_acin;
54 int status_high_noac;
55 int status_low_noac;
56};
57
58struct battery_thresh {
59 int voltage;
60 int percentage;
61};
62
63struct battery_stat {
64 int ac_status; /* APM AC Present/Not Present */
65 int mainbat_status; /* APM Main Battery Status */
66 int mainbat_percent; /* Main Battery Percentage Charge */
67 int mainbat_voltage; /* Main Battery Voltage */
68};
69
70struct sharpsl_pm_status {
71 struct device *dev;
72 struct timer_list ac_timer;
73 struct timer_list chrg_full_timer;
74
75 int charge_mode;
76#define CHRG_ERROR (-1)
77#define CHRG_OFF (0)
78#define CHRG_ON (1)
79#define CHRG_DONE (2)
80
81 unsigned int flags;
82#define SHARPSL_SUSPENDED (1 << 0) /* Device is Suspended */
83#define SHARPSL_ALARM_ACTIVE (1 << 1) /* Alarm is for charging event (not user) */
84#define SHARPSL_BL_LIMIT (1 << 2) /* Backlight Intensity Limited */
85#define SHARPSL_APM_QUEUED (1 << 3) /* APM Event Queued */
86#define SHARPSL_DO_OFFLINE_CHRG (1 << 4) /* Trigger the offline charger */
87
88 int full_count;
89 unsigned long charge_start_time;
90 struct sharpsl_charger_machinfo *machinfo;
91 struct battery_stat battstat;
92};
93
94extern struct sharpsl_pm_status sharpsl_pm;
95
96
97#define SHARPSL_LED_ERROR 2
98#define SHARPSL_LED_ON 1
99#define SHARPSL_LED_OFF 0
100
101void sharpsl_battery_kick(void);
102void sharpsl_pm_led(int val);
103irqreturn_t sharpsl_ac_isr(int irq, void *dev_id);
104irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id);
105irqreturn_t sharpsl_fatal_isr(int irq, void *dev_id);
106
diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
index f87328d4a180..5d72550a8097 100644
--- a/arch/arm/include/asm/hardware/vic.h
+++ b/arch/arm/include/asm/hardware/vic.h
@@ -41,7 +41,7 @@
41#define VIC_PL192_VECT_ADDR 0xF00 41#define VIC_PL192_VECT_ADDR 0xF00
42 42
43#ifndef __ASSEMBLY__ 43#ifndef __ASSEMBLY__
44void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources); 44void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
45#endif 45#endif
46 46
47#endif 47#endif
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
new file mode 100644
index 000000000000..50c7e7cfd670
--- /dev/null
+++ b/arch/arm/include/asm/localtimer.h
@@ -0,0 +1,63 @@
1/*
2 * arch/arm/include/asm/localtimer.h
3 *
4 * Copyright (C) 2004-2005 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_ARM_LOCALTIMER_H
11#define __ASM_ARM_LOCALTIMER_H
12
13struct clock_event_device;
14
15/*
16 * Setup a per-cpu timer, whether it be a local timer or dummy broadcast
17 */
18void percpu_timer_setup(void);
19
20/*
21 * Called from assembly, this is the local timer IRQ handler
22 */
23asmlinkage void do_local_timer(struct pt_regs *);
24
25
26#ifdef CONFIG_LOCAL_TIMERS
27
28#ifdef CONFIG_HAVE_ARM_TWD
29
30#include "smp_twd.h"
31
32#define local_timer_ack() twd_timer_ack()
33#define local_timer_stop() twd_timer_stop()
34
35#else
36
37/*
38 * Platform provides this to acknowledge a local timer IRQ.
39 * Returns true if the local timer IRQ is to be processed.
40 */
41int local_timer_ack(void);
42
43/*
44 * Stop a local timer interrupt.
45 */
46void local_timer_stop(void);
47
48#endif
49
50/*
51 * Setup a local timer interrupt for a CPU.
52 */
53void local_timer_setup(struct clock_event_device *);
54
55#else
56
57static inline void local_timer_stop(void)
58{
59}
60
61#endif
62
63#endif
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index 58cf91f38e6f..742c2aaeb020 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -30,6 +30,14 @@ struct map_desc {
30 30
31#ifdef CONFIG_MMU 31#ifdef CONFIG_MMU
32extern void iotable_init(struct map_desc *, int); 32extern void iotable_init(struct map_desc *, int);
33
34struct mem_type;
35extern const struct mem_type *get_mem_type(unsigned int type);
36/*
37 * external interface to remap single page with appropriate type
38 */
39extern int ioremap_page(unsigned long virt, unsigned long phys,
40 const struct mem_type *mtype);
33#else 41#else
34#define iotable_init(map,num) do { } while (0) 42#define iotable_init(map,num) do { } while (0)
35#endif 43#endif
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 110295c5461d..1cd2d6416bda 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -342,7 +342,7 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
342 return __va(ptr); 342 return __va(ptr);
343} 343}
344 344
345#define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd))) 345#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd)))
346 346
347/* 347/*
348 * Conversion functions: convert a page and protection to a page entry, 348 * Conversion functions: convert a page and protection to a page entry,
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 1845892260e7..6a89567ffc5b 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -71,6 +71,7 @@ struct thread_struct {
71 regs->ARM_cpsr = USR26_MODE; \ 71 regs->ARM_cpsr = USR26_MODE; \
72 if (elf_hwcap & HWCAP_THUMB && pc & 1) \ 72 if (elf_hwcap & HWCAP_THUMB && pc & 1) \
73 regs->ARM_cpsr |= PSR_T_BIT; \ 73 regs->ARM_cpsr |= PSR_T_BIT; \
74 regs->ARM_cpsr |= PSR_ENDSTATE; \
74 regs->ARM_pc = pc & ~1; /* pc */ \ 75 regs->ARM_pc = pc & ~1; /* pc */ \
75 regs->ARM_sp = sp; /* sp */ \ 76 regs->ARM_sp = sp; /* sp */ \
76 regs->ARM_r2 = stack[2]; /* r2 (envp) */ \ 77 regs->ARM_r2 = stack[2]; /* r2 (envp) */ \
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 236a06b9b7ce..67b833c9b6b9 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -50,6 +50,7 @@
50#define PSR_F_BIT 0x00000040 50#define PSR_F_BIT 0x00000040
51#define PSR_I_BIT 0x00000080 51#define PSR_I_BIT 0x00000080
52#define PSR_A_BIT 0x00000100 52#define PSR_A_BIT 0x00000100
53#define PSR_E_BIT 0x00000200
53#define PSR_J_BIT 0x01000000 54#define PSR_J_BIT 0x01000000
54#define PSR_Q_BIT 0x08000000 55#define PSR_Q_BIT 0x08000000
55#define PSR_V_BIT 0x10000000 56#define PSR_V_BIT 0x10000000
@@ -65,6 +66,22 @@
65#define PSR_x 0x0000ff00 /* Extension */ 66#define PSR_x 0x0000ff00 /* Extension */
66#define PSR_c 0x000000ff /* Control */ 67#define PSR_c 0x000000ff /* Control */
67 68
69/*
70 * ARMv7 groups of APSR bits
71 */
72#define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */
73#define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
74#define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */
75
76/*
77 * Default endianness state
78 */
79#ifdef CONFIG_CPU_ENDIAN_BE8
80#define PSR_ENDSTATE PSR_E_BIT
81#else
82#define PSR_ENDSTATE 0
83#endif
84
68#ifndef __ASSEMBLY__ 85#ifndef __ASSEMBLY__
69 86
70/* 87/*
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
index ada93a8fc2ef..4fc1565e4f93 100644
--- a/arch/arm/include/asm/sizes.h
+++ b/arch/arm/include/asm/sizes.h
@@ -29,6 +29,7 @@
29#define SZ_512 0x00000200 29#define SZ_512 0x00000200
30 30
31#define SZ_1K 0x00000400 31#define SZ_1K 0x00000400
32#define SZ_2K 0x00000800
32#define SZ_4K 0x00001000 33#define SZ_4K 0x00001000
33#define SZ_8K 0x00002000 34#define SZ_8K 0x00002000
34#define SZ_16K 0x00004000 35#define SZ_16K 0x00004000
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 5995935338e1..a06e735b262a 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -41,7 +41,7 @@ extern void show_ipi_list(struct seq_file *p);
41asmlinkage void do_IPI(struct pt_regs *regs); 41asmlinkage void do_IPI(struct pt_regs *regs);
42 42
43/* 43/*
44 * Setup the SMP cpu_possible_map 44 * Setup the set of possible CPUs (via set_cpu_possible)
45 */ 45 */
46extern void smp_init_cpus(void); 46extern void smp_init_cpus(void);
47 47
@@ -56,11 +56,6 @@ extern void smp_store_cpu_info(unsigned int cpuid);
56extern void smp_cross_call(const struct cpumask *mask); 56extern void smp_cross_call(const struct cpumask *mask);
57 57
58/* 58/*
59 * Broadcast a clock event to other CPUs.
60 */
61extern void smp_timer_broadcast(const struct cpumask *mask);
62
63/*
64 * Boot a secondary CPU, and assign it the specified idle task. 59 * Boot a secondary CPU, and assign it the specified idle task.
65 * This also gives us the initial stack to use for this CPU. 60 * This also gives us the initial stack to use for this CPU.
66 */ 61 */
@@ -101,43 +96,8 @@ extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
101#define arch_send_call_function_ipi_mask arch_send_call_function_ipi_mask 96#define arch_send_call_function_ipi_mask arch_send_call_function_ipi_mask
102 97
103/* 98/*
104 * Local timer interrupt handling function (can be IPI'ed).
105 */
106extern void local_timer_interrupt(void);
107
108#ifdef CONFIG_LOCAL_TIMERS
109
110/*
111 * Stop a local timer interrupt.
112 */
113extern void local_timer_stop(void);
114
115/*
116 * Platform provides this to acknowledge a local timer IRQ
117 */
118extern int local_timer_ack(void);
119
120#else
121
122static inline void local_timer_stop(void)
123{
124}
125
126#endif
127
128/*
129 * Setup a local timer interrupt for a CPU.
130 */
131extern void local_timer_setup(void);
132
133/*
134 * show local interrupt info 99 * show local interrupt info
135 */ 100 */
136extern void show_local_irqs(struct seq_file *); 101extern void show_local_irqs(struct seq_file *);
137 102
138/*
139 * Called from assembly, this is the local timer IRQ handler
140 */
141asmlinkage void do_local_timer(struct pt_regs *);
142
143#endif /* ifndef __ASM_ARM_SMP_H */ 103#endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
new file mode 100644
index 000000000000..2376835015d6
--- /dev/null
+++ b/arch/arm/include/asm/smp_scu.h
@@ -0,0 +1,7 @@
1#ifndef __ASMARM_ARCH_SCU_H
2#define __ASMARM_ARCH_SCU_H
3
4unsigned int scu_get_core_count(void __iomem *);
5void scu_enable(void __iomem *);
6
7#endif
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
new file mode 100644
index 000000000000..7be0978b2625
--- /dev/null
+++ b/arch/arm/include/asm/smp_twd.h
@@ -0,0 +1,12 @@
1#ifndef __ASMARM_SMP_TWD_H
2#define __ASMARM_SMP_TWD_H
3
4struct clock_event_device;
5
6extern void __iomem *twd_base;
7
8void twd_timer_stop(void);
9int twd_timer_ack(void);
10void twd_timer_setup(struct clock_event_device *);
11
12#endif
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index a62218013c78..c964f3fc3bc5 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -40,6 +40,12 @@
40#define TLB_V6_I_ASID (1 << 18) 40#define TLB_V6_I_ASID (1 << 18)
41 41
42#define TLB_BTB (1 << 28) 42#define TLB_BTB (1 << 28)
43
44/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
45#define TLB_V7_UIS_PAGE (1 << 19)
46#define TLB_V7_UIS_FULL (1 << 20)
47#define TLB_V7_UIS_ASID (1 << 21)
48
43#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ 49#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
44#define TLB_DCLEAN (1 << 30) 50#define TLB_DCLEAN (1 << 30)
45#define TLB_WB (1 << 31) 51#define TLB_WB (1 << 31)
@@ -176,9 +182,17 @@
176# define v6wbi_always_flags (-1UL) 182# define v6wbi_always_flags (-1UL)
177#endif 183#endif
178 184
185#ifdef CONFIG_SMP
186#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
187 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
188#else
189#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
190 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
191#endif
192
179#ifdef CONFIG_CPU_TLB_V7 193#ifdef CONFIG_CPU_TLB_V7
180# define v7wbi_possible_flags v6wbi_tlb_flags 194# define v7wbi_possible_flags v7wbi_tlb_flags
181# define v7wbi_always_flags v6wbi_tlb_flags 195# define v7wbi_always_flags v7wbi_tlb_flags
182# ifdef _TLB 196# ifdef _TLB
183# define MULTI_TLB 1 197# define MULTI_TLB 1
184# else 198# else
@@ -316,6 +330,8 @@ static inline void local_flush_tlb_all(void)
316 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc"); 330 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
317 if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL)) 331 if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
318 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); 332 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
333 if (tlb_flag(TLB_V7_UIS_FULL))
334 asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
319 335
320 if (tlb_flag(TLB_BTB)) { 336 if (tlb_flag(TLB_BTB)) {
321 /* flush the branch target cache */ 337 /* flush the branch target cache */
@@ -351,6 +367,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
351 asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc"); 367 asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
352 if (tlb_flag(TLB_V6_I_ASID)) 368 if (tlb_flag(TLB_V6_I_ASID))
353 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); 369 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
370 if (tlb_flag(TLB_V7_UIS_ASID))
371 asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc");
354 372
355 if (tlb_flag(TLB_BTB)) { 373 if (tlb_flag(TLB_BTB)) {
356 /* flush the branch target cache */ 374 /* flush the branch target cache */
@@ -389,6 +407,8 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
389 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc"); 407 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
390 if (tlb_flag(TLB_V6_I_PAGE)) 408 if (tlb_flag(TLB_V6_I_PAGE))
391 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); 409 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
410 if (tlb_flag(TLB_V7_UIS_PAGE))
411 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc");
392 412
393 if (tlb_flag(TLB_BTB)) { 413 if (tlb_flag(TLB_BTB)) {
394 /* flush the branch target cache */ 414 /* flush the branch target cache */
@@ -424,6 +444,8 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
424 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc"); 444 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
425 if (tlb_flag(TLB_V6_I_PAGE)) 445 if (tlb_flag(TLB_V6_I_PAGE))
426 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); 446 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
447 if (tlb_flag(TLB_V7_UIS_PAGE))
448 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc");
427 449
428 if (tlb_flag(TLB_BTB)) { 450 if (tlb_flag(TLB_BTB)) {
429 /* flush the branch target cache */ 451 /* flush the branch target cache */
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 7897464e0c24..0da9bc9b3b1d 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -386,7 +386,9 @@ do { \
386#ifdef CONFIG_MMU 386#ifdef CONFIG_MMU
387extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n); 387extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n);
388extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n); 388extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n);
389extern unsigned long __must_check __copy_to_user_std(void __user *to, const void *from, unsigned long n);
389extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n); 390extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n);
391extern unsigned long __must_check __clear_user_std(void __user *addr, unsigned long n);
390#else 392#else
391#define __copy_from_user(to,from,n) (memcpy(to, (void __force *)from, n), 0) 393#define __copy_from_user(to,from,n) (memcpy(to, (void __force *)from, n), 0)
392#define __copy_to_user(to,from,n) (memcpy((void __force *)to, from, n), 0) 394#define __copy_to_user(to,from,n) (memcpy((void __force *)to, from, n), 0)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 19:04:31 -0500