1 files changed, 25 insertions, 13 deletions

diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index b543a054a17e..a62218013c78 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -39,6 +39,7 @@
 #define TLB_V6_D_ASID   (1 << 17)
 #define TLB_V6_I_ASID   (1 << 18)
 
+#define TLB_BTB         (1 << 28)
 #define TLB_L2CLEAN_FR  (1 << 29)               /* Feroceon */
 #define TLB_DCLEAN      (1 << 30)
 #define TLB_WB          (1 << 31)
@@ -53,6 +54,7 @@
  *        v4wb  - ARMv4 with write buffer without I TLB flush entry instruction
  *        v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
  *        fr    - Feroceon (v4wbi with non-outer-cacheable page table walks)
+ *        fa    - Faraday (v4 with write buffer with UTLB and branch target buffer (BTB))
  *        v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
  *        v7wbi - identical to v6wbi
  */
@@ -89,6 +91,22 @@
 # define v4_always_flags        (-1UL)
 #endif
 
+#define fa_tlb_flags    (TLB_WB | TLB_BTB | TLB_DCLEAN | \
+                         TLB_V4_U_FULL | TLB_V4_U_PAGE)
+
+#ifdef CONFIG_CPU_TLB_FA
+# define fa_possible_flags      fa_tlb_flags
+# define fa_always_flags        fa_tlb_flags
+# ifdef _TLB
+#  define MULTI_TLB 1
+# else
+#  define _TLB fa
+# endif
+#else
+# define fa_possible_flags      0
+# define fa_always_flags        (-1UL)
+#endif
+
 #define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
                          TLB_V4_I_FULL | TLB_V4_D_FULL | \
                          TLB_V4_I_PAGE | TLB_V4_D_PAGE)
@@ -140,7 +158,7 @@
 # define v4wb_always_flags      (-1UL)
 #endif
 
-#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
+#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
                          TLB_V6_I_FULL | TLB_V6_D_FULL | \
                          TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
                          TLB_V6_I_ASID | TLB_V6_D_ASID)
@@ -267,6 +285,7 @@ extern struct cpu_tlb_fns cpu_tlb;
                                  v4wbi_possible_flags | \
                                  fr_possible_flags | \
                                  v4wb_possible_flags | \
+                                 fa_possible_flags | \
                                  v6wbi_possible_flags | \
                                  v7wbi_possible_flags)
 
@@ -275,6 +294,7 @@ extern struct cpu_tlb_fns cpu_tlb;
                                  v4wbi_always_flags & \
                                  fr_always_flags & \
                                  v4wb_always_flags & \
+                                 fa_always_flags & \
                                  v6wbi_always_flags & \
                                  v7wbi_always_flags)
 
@@ -297,9 +317,7 @@ static inline void local_flush_tlb_all(void)
         if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
                 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
 
-        if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
-                     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
-                     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
+        if (tlb_flag(TLB_BTB)) {
                 /* flush the branch target cache */
                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
                 dsb();
@@ -334,9 +352,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
         if (tlb_flag(TLB_V6_I_ASID))
                 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
 
-        if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
-                     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
-                     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
+        if (tlb_flag(TLB_BTB)) {
                 /* flush the branch target cache */
                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
                 dsb();
@@ -374,9 +390,7 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
         if (tlb_flag(TLB_V6_I_PAGE))
                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
 
-        if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
-                     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
-                     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
+        if (tlb_flag(TLB_BTB)) {
                 /* flush the branch target cache */
                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
                 dsb();
@@ -411,9 +425,7 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
         if (tlb_flag(TLB_V6_I_PAGE))
                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
 
-        if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
-                     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
-                     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
+        if (tlb_flag(TLB_BTB)) {
                 /* flush the branch target cache */
                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
                 dsb();