1 files changed, 64 insertions, 0 deletions
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index a06ba8773cd7..71d99b83cdb9 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -13,6 +13,7 @@
 #define __ARM_PMU_H__
 #include <linux/interrupt.h>
+#include <linux/perf_event.h>
 /*
 * Types of PMUs that can be accessed directly and require mutual
@@ -79,4 +80,67 @@ release_pmu(enum arm_pmu_type type)	{ }
 #endif /* CONFIG_CPU_HAS_PMU */
+#ifdef CONFIG_HW_PERF_EVENTS
+/* The events for a given PMU register set. */
+struct pmu_hw_events {
+        /*
+         * The events that are active on the PMU for the given index.
+         */
+        struct perf_event       **events;
+        /*
+         * A 1 bit for an index indicates that the counter is being used for
+         * an event. A 0 means that the counter can be used.
+         */
+        unsigned long           *used_mask;
+        /*
+         * Hardware lock to serialize accesses to PMU registers. Needed for the
+         * read/modify/write sequences.
+         */
+        raw_spinlock_t          pmu_lock;
+};
+struct arm_pmu {
+        struct pmu      pmu;
+        enum arm_perf_pmu_ids id;
+        enum arm_pmu_type type;
+        cpumask_t       active_irqs;
+        const char      *name;
+        irqreturn_t     (*handle_irq)(int irq_num, void *dev);
+        void            (*enable)(struct hw_perf_event *evt, int idx);
+        void            (*disable)(struct hw_perf_event *evt, int idx);
+        int             (*get_event_idx)(struct pmu_hw_events *hw_events,
+                                         struct hw_perf_event *hwc);
+        int             (*set_event_filter)(struct hw_perf_event *evt,
+                                            struct perf_event_attr *attr);
+        u32             (*read_counter)(int idx);
+        void            (*write_counter)(int idx, u32 val);
+        void            (*start)(void);
+        void            (*stop)(void);
+        void            (*reset)(void *);
+        int             (*map_event)(struct perf_event *event);
+        int             num_events;
+        atomic_t        active_events;
+        struct mutex    reserve_mutex;
+        u64             max_period;
+        struct platform_device  *plat_device;
+        struct pmu_hw_events    *(*get_hw_events)(void);
+};
+#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
+int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
+u64 armpmu_event_update(struct perf_event *event,
+                        struct hw_perf_event *hwc,
+                        int idx, int overflow);
+int armpmu_event_set_period(struct perf_event *event,
+                            struct hw_perf_event *hwc,
+                            int idx);
+#endif /* CONFIG_HW_PERF_EVENTS */
 #endif /* __ARM_PMU_H__ */

diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h index a06ba8773cd7..71d99b83cdb9 100644 --- a/arch/arm/include/asm/pmu.h +++ b/arch/arm/include/asm/pmu.h
@@ -13,6 +13,7 @@
13	#define __ARM_PMU_H__	13	#define __ARM_PMU_H__
14		14
15	#include <linux/interrupt.h>	15	#include <linux/interrupt.h>
		16	#include <linux/perf_event.h>
16		17
17	/*	18	/*
18	* Types of PMUs that can be accessed directly and require mutual	19	* Types of PMUs that can be accessed directly and require mutual
@@ -79,4 +80,67 @@ release_pmu(enum arm_pmu_type type) { }
79		80
80	#endif /* CONFIG_CPU_HAS_PMU */	81	#endif /* CONFIG_CPU_HAS_PMU */
81		82
		83	#ifdef CONFIG_HW_PERF_EVENTS
		84
		85	/* The events for a given PMU register set. */
		86	struct pmu_hw_events {
		87	/*
		88	* The events that are active on the PMU for the given index.
		89	*/
		90	struct perf_event **events;
		91
		92	/*
		93	* A 1 bit for an index indicates that the counter is being used for
		94	* an event. A 0 means that the counter can be used.
		95	*/
		96	unsigned long *used_mask;
		97
		98	/*
		99	* Hardware lock to serialize accesses to PMU registers. Needed for the
		100	* read/modify/write sequences.
		101	*/
		102	raw_spinlock_t pmu_lock;
		103	};
		104
		105	struct arm_pmu {
		106	struct pmu pmu;
		107	enum arm_perf_pmu_ids id;
		108	enum arm_pmu_type type;
		109	cpumask_t active_irqs;
		110	const char *name;
		111	irqreturn_t (handle_irq)(int irq_num, void dev);
		112	void (enable)(struct hw_perf_event evt, int idx);
		113	void (disable)(struct hw_perf_event evt, int idx);
		114	int (get_event_idx)(struct pmu_hw_events hw_events,
		115	struct hw_perf_event *hwc);
		116	int (set_event_filter)(struct hw_perf_event evt,
		117	struct perf_event_attr *attr);
		118	u32 (*read_counter)(int idx);
		119	void (*write_counter)(int idx, u32 val);
		120	void (*start)(void);
		121	void (*stop)(void);
		122	void (reset)(void );
		123	int (map_event)(struct perf_event event);
		124	int num_events;
		125	atomic_t active_events;
		126	struct mutex reserve_mutex;
		127	u64 max_period;
		128	struct platform_device *plat_device;
		129	struct pmu_hw_events (get_hw_events)(void);
		130	};
		131
		132	#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
		133
		134	int __init armpmu_register(struct arm_pmu armpmu, char name, int type);
		135
		136	u64 armpmu_event_update(struct perf_event *event,
		137	struct hw_perf_event *hwc,
		138	int idx, int overflow);
		139
		140	int armpmu_event_set_period(struct perf_event *event,
		141	struct hw_perf_event *hwc,
		142	int idx);
		143
		144	#endif /* CONFIG_HW_PERF_EVENTS */
		145
82	#endif /* __ARM_PMU_H__ */	146	#endif /* __ARM_PMU_H__ */