diff options
Diffstat (limited to 'arch/arm/include/asm/hardware')
-rw-r--r-- | arch/arm/include/asm/hardware/arm_timer.h | 5 | ||||
-rw-r--r-- | arch/arm/include/asm/hardware/cache-l2x0.h | 6 | ||||
-rw-r--r-- | arch/arm/include/asm/hardware/iop3xx.h | 3 | ||||
-rw-r--r-- | arch/arm/include/asm/hardware/iop_adma.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/hardware/it8152.h | 3 | ||||
-rw-r--r-- | arch/arm/include/asm/hardware/pl330.h | 217 | ||||
-rw-r--r-- | arch/arm/include/asm/hardware/sa1111.h | 156 | ||||
-rw-r--r-- | arch/arm/include/asm/hardware/timer-sp.h | 15 |
8 files changed, 51 insertions, 356 deletions
diff --git a/arch/arm/include/asm/hardware/arm_timer.h b/arch/arm/include/asm/hardware/arm_timer.h index c0f4e7bf22de..d6030ff599db 100644 --- a/arch/arm/include/asm/hardware/arm_timer.h +++ b/arch/arm/include/asm/hardware/arm_timer.h | |||
@@ -9,7 +9,12 @@ | |||
9 | * | 9 | * |
10 | * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview | 10 | * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview |
11 | * can have 16-bit or 32-bit selectable via a bit in the control register. | 11 | * can have 16-bit or 32-bit selectable via a bit in the control register. |
12 | * | ||
13 | * Every SP804 contains two identical timers. | ||
12 | */ | 14 | */ |
15 | #define TIMER_1_BASE 0x00 | ||
16 | #define TIMER_2_BASE 0x20 | ||
17 | |||
13 | #define TIMER_LOAD 0x00 /* ACVR rw */ | 18 | #define TIMER_LOAD 0x00 /* ACVR rw */ |
14 | #define TIMER_VALUE 0x04 /* ACVR ro */ | 19 | #define TIMER_VALUE 0x04 /* ACVR ro */ |
15 | #define TIMER_CTRL 0x08 /* ACVR rw */ | 20 | #define TIMER_CTRL 0x08 /* ACVR rw */ |
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 7df239bcdf27..c4c87bc12231 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h | |||
@@ -103,11 +103,11 @@ | |||
103 | #define L2X0_ADDR_FILTER_EN 1 | 103 | #define L2X0_ADDR_FILTER_EN 1 |
104 | 104 | ||
105 | #ifndef __ASSEMBLY__ | 105 | #ifndef __ASSEMBLY__ |
106 | extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); | 106 | extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask); |
107 | #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF) | 107 | #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF) |
108 | extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask); | 108 | extern int l2x0_of_init(u32 aux_val, u32 aux_mask); |
109 | #else | 109 | #else |
110 | static inline int l2x0_of_init(__u32 aux_val, __u32 aux_mask) | 110 | static inline int l2x0_of_init(u32 aux_val, u32 aux_mask) |
111 | { | 111 | { |
112 | return -ENODEV; | 112 | return -ENODEV; |
113 | } | 113 | } |
diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h index 077c32326c63..2ff2c75a4639 100644 --- a/arch/arm/include/asm/hardware/iop3xx.h +++ b/arch/arm/include/asm/hardware/iop3xx.h | |||
@@ -231,6 +231,9 @@ extern int iop3xx_get_init_atu(void); | |||
231 | 231 | ||
232 | 232 | ||
233 | #ifndef __ASSEMBLY__ | 233 | #ifndef __ASSEMBLY__ |
234 | |||
235 | #include <linux/types.h> | ||
236 | |||
234 | void iop3xx_map_io(void); | 237 | void iop3xx_map_io(void); |
235 | void iop_init_cp6_handler(void); | 238 | void iop_init_cp6_handler(void); |
236 | void iop_init_time(unsigned long tickrate); | 239 | void iop_init_time(unsigned long tickrate); |
diff --git a/arch/arm/include/asm/hardware/iop_adma.h b/arch/arm/include/asm/hardware/iop_adma.h index 59b8c3892f76..122f86d8c991 100644 --- a/arch/arm/include/asm/hardware/iop_adma.h +++ b/arch/arm/include/asm/hardware/iop_adma.h | |||
@@ -49,7 +49,6 @@ struct iop_adma_device { | |||
49 | /** | 49 | /** |
50 | * struct iop_adma_chan - internal representation of an ADMA device | 50 | * struct iop_adma_chan - internal representation of an ADMA device |
51 | * @pending: allows batching of hardware operations | 51 | * @pending: allows batching of hardware operations |
52 | * @completed_cookie: identifier for the most recently completed operation | ||
53 | * @lock: serializes enqueue/dequeue operations to the slot pool | 52 | * @lock: serializes enqueue/dequeue operations to the slot pool |
54 | * @mmr_base: memory mapped register base | 53 | * @mmr_base: memory mapped register base |
55 | * @chain: device chain view of the descriptors | 54 | * @chain: device chain view of the descriptors |
@@ -62,7 +61,6 @@ struct iop_adma_device { | |||
62 | */ | 61 | */ |
63 | struct iop_adma_chan { | 62 | struct iop_adma_chan { |
64 | int pending; | 63 | int pending; |
65 | dma_cookie_t completed_cookie; | ||
66 | spinlock_t lock; /* protects the descriptor slot pool */ | 64 | spinlock_t lock; /* protects the descriptor slot pool */ |
67 | void __iomem *mmr_base; | 65 | void __iomem *mmr_base; |
68 | struct list_head chain; | 66 | struct list_head chain; |
diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h index 43cab498bc27..73f84fa4f366 100644 --- a/arch/arm/include/asm/hardware/it8152.h +++ b/arch/arm/include/asm/hardware/it8152.h | |||
@@ -9,6 +9,9 @@ | |||
9 | 9 | ||
10 | #ifndef __ASM_HARDWARE_IT8152_H | 10 | #ifndef __ASM_HARDWARE_IT8152_H |
11 | #define __ASM_HARDWARE_IT8152_H | 11 | #define __ASM_HARDWARE_IT8152_H |
12 | |||
13 | #include <mach/irqs.h> | ||
14 | |||
12 | extern void __iomem *it8152_base_address; | 15 | extern void __iomem *it8152_base_address; |
13 | 16 | ||
14 | #define IT8152_IO_BASE (it8152_base_address + 0x03e00000) | 17 | #define IT8152_IO_BASE (it8152_base_address + 0x03e00000) |
diff --git a/arch/arm/include/asm/hardware/pl330.h b/arch/arm/include/asm/hardware/pl330.h deleted file mode 100644 index c1821385abfa..000000000000 --- a/arch/arm/include/asm/hardware/pl330.h +++ /dev/null | |||
@@ -1,217 +0,0 @@ | |||
1 | /* linux/include/asm/hardware/pl330.h | ||
2 | * | ||
3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
19 | */ | ||
20 | |||
21 | #ifndef __PL330_CORE_H | ||
22 | #define __PL330_CORE_H | ||
23 | |||
24 | #define PL330_MAX_CHAN 8 | ||
25 | #define PL330_MAX_IRQS 32 | ||
26 | #define PL330_MAX_PERI 32 | ||
27 | |||
28 | enum pl330_srccachectrl { | ||
29 | SCCTRL0 = 0, /* Noncacheable and nonbufferable */ | ||
30 | SCCTRL1, /* Bufferable only */ | ||
31 | SCCTRL2, /* Cacheable, but do not allocate */ | ||
32 | SCCTRL3, /* Cacheable and bufferable, but do not allocate */ | ||
33 | SINVALID1, | ||
34 | SINVALID2, | ||
35 | SCCTRL6, /* Cacheable write-through, allocate on reads only */ | ||
36 | SCCTRL7, /* Cacheable write-back, allocate on reads only */ | ||
37 | }; | ||
38 | |||
39 | enum pl330_dstcachectrl { | ||
40 | DCCTRL0 = 0, /* Noncacheable and nonbufferable */ | ||
41 | DCCTRL1, /* Bufferable only */ | ||
42 | DCCTRL2, /* Cacheable, but do not allocate */ | ||
43 | DCCTRL3, /* Cacheable and bufferable, but do not allocate */ | ||
44 | DINVALID1, /* AWCACHE = 0x1000 */ | ||
45 | DINVALID2, | ||
46 | DCCTRL6, /* Cacheable write-through, allocate on writes only */ | ||
47 | DCCTRL7, /* Cacheable write-back, allocate on writes only */ | ||
48 | }; | ||
49 | |||
50 | /* Populated by the PL330 core driver for DMA API driver's info */ | ||
51 | struct pl330_config { | ||
52 | u32 periph_id; | ||
53 | u32 pcell_id; | ||
54 | #define DMAC_MODE_NS (1 << 0) | ||
55 | unsigned int mode; | ||
56 | unsigned int data_bus_width:10; /* In number of bits */ | ||
57 | unsigned int data_buf_dep:10; | ||
58 | unsigned int num_chan:4; | ||
59 | unsigned int num_peri:6; | ||
60 | u32 peri_ns; | ||
61 | unsigned int num_events:6; | ||
62 | u32 irq_ns; | ||
63 | }; | ||
64 | |||
65 | /* Handle to the DMAC provided to the PL330 core */ | ||
66 | struct pl330_info { | ||
67 | /* Owning device */ | ||
68 | struct device *dev; | ||
69 | /* Size of MicroCode buffers for each channel. */ | ||
70 | unsigned mcbufsz; | ||
71 | /* ioremap'ed address of PL330 registers. */ | ||
72 | void __iomem *base; | ||
73 | /* Client can freely use it. */ | ||
74 | void *client_data; | ||
75 | /* PL330 core data, Client must not touch it. */ | ||
76 | void *pl330_data; | ||
77 | /* Populated by the PL330 core driver during pl330_add */ | ||
78 | struct pl330_config pcfg; | ||
79 | /* | ||
80 | * If the DMAC has some reset mechanism, then the | ||
81 | * client may want to provide pointer to the method. | ||
82 | */ | ||
83 | void (*dmac_reset)(struct pl330_info *pi); | ||
84 | }; | ||
85 | |||
86 | enum pl330_byteswap { | ||
87 | SWAP_NO = 0, | ||
88 | SWAP_2, | ||
89 | SWAP_4, | ||
90 | SWAP_8, | ||
91 | SWAP_16, | ||
92 | }; | ||
93 | |||
94 | /** | ||
95 | * Request Configuration. | ||
96 | * The PL330 core does not modify this and uses the last | ||
97 | * working configuration if the request doesn't provide any. | ||
98 | * | ||
99 | * The Client may want to provide this info only for the | ||
100 | * first request and a request with new settings. | ||
101 | */ | ||
102 | struct pl330_reqcfg { | ||
103 | /* Address Incrementing */ | ||
104 | unsigned dst_inc:1; | ||
105 | unsigned src_inc:1; | ||
106 | |||
107 | /* | ||
108 | * For now, the SRC & DST protection levels | ||
109 | * and burst size/length are assumed same. | ||
110 | */ | ||
111 | bool nonsecure; | ||
112 | bool privileged; | ||
113 | bool insnaccess; | ||
114 | unsigned brst_len:5; | ||
115 | unsigned brst_size:3; /* in power of 2 */ | ||
116 | |||
117 | enum pl330_dstcachectrl dcctl; | ||
118 | enum pl330_srccachectrl scctl; | ||
119 | enum pl330_byteswap swap; | ||
120 | }; | ||
121 | |||
122 | /* | ||
123 | * One cycle of DMAC operation. | ||
124 | * There may be more than one xfer in a request. | ||
125 | */ | ||
126 | struct pl330_xfer { | ||
127 | u32 src_addr; | ||
128 | u32 dst_addr; | ||
129 | /* Size to xfer */ | ||
130 | u32 bytes; | ||
131 | /* | ||
132 | * Pointer to next xfer in the list. | ||
133 | * The last xfer in the req must point to NULL. | ||
134 | */ | ||
135 | struct pl330_xfer *next; | ||
136 | }; | ||
137 | |||
138 | /* The xfer callbacks are made with one of these arguments. */ | ||
139 | enum pl330_op_err { | ||
140 | /* The all xfers in the request were success. */ | ||
141 | PL330_ERR_NONE, | ||
142 | /* If req aborted due to global error. */ | ||
143 | PL330_ERR_ABORT, | ||
144 | /* If req failed due to problem with Channel. */ | ||
145 | PL330_ERR_FAIL, | ||
146 | }; | ||
147 | |||
148 | enum pl330_reqtype { | ||
149 | MEMTOMEM, | ||
150 | MEMTODEV, | ||
151 | DEVTOMEM, | ||
152 | DEVTODEV, | ||
153 | }; | ||
154 | |||
155 | /* A request defining Scatter-Gather List ending with NULL xfer. */ | ||
156 | struct pl330_req { | ||
157 | enum pl330_reqtype rqtype; | ||
158 | /* Index of peripheral for the xfer. */ | ||
159 | unsigned peri:5; | ||
160 | /* Unique token for this xfer, set by the client. */ | ||
161 | void *token; | ||
162 | /* Callback to be called after xfer. */ | ||
163 | void (*xfer_cb)(void *token, enum pl330_op_err err); | ||
164 | /* If NULL, req will be done at last set parameters. */ | ||
165 | struct pl330_reqcfg *cfg; | ||
166 | /* Pointer to first xfer in the request. */ | ||
167 | struct pl330_xfer *x; | ||
168 | }; | ||
169 | |||
170 | /* | ||
171 | * To know the status of the channel and DMAC, the client | ||
172 | * provides a pointer to this structure. The PL330 core | ||
173 | * fills it with current information. | ||
174 | */ | ||
175 | struct pl330_chanstatus { | ||
176 | /* | ||
177 | * If the DMAC engine halted due to some error, | ||
178 | * the client should remove-add DMAC. | ||
179 | */ | ||
180 | bool dmac_halted; | ||
181 | /* | ||
182 | * If channel is halted due to some error, | ||
183 | * the client should ABORT/FLUSH and START the channel. | ||
184 | */ | ||
185 | bool faulting; | ||
186 | /* Location of last load */ | ||
187 | u32 src_addr; | ||
188 | /* Location of last store */ | ||
189 | u32 dst_addr; | ||
190 | /* | ||
191 | * Pointer to the currently active req, NULL if channel is | ||
192 | * inactive, even though the requests may be present. | ||
193 | */ | ||
194 | struct pl330_req *top_req; | ||
195 | /* Pointer to req waiting second in the queue if any. */ | ||
196 | struct pl330_req *wait_req; | ||
197 | }; | ||
198 | |||
199 | enum pl330_chan_op { | ||
200 | /* Start the channel */ | ||
201 | PL330_OP_START, | ||
202 | /* Abort the active xfer */ | ||
203 | PL330_OP_ABORT, | ||
204 | /* Stop xfer and flush queue */ | ||
205 | PL330_OP_FLUSH, | ||
206 | }; | ||
207 | |||
208 | extern int pl330_add(struct pl330_info *); | ||
209 | extern void pl330_del(struct pl330_info *pi); | ||
210 | extern int pl330_update(const struct pl330_info *pi); | ||
211 | extern void pl330_release_channel(void *ch_id); | ||
212 | extern void *pl330_request_channel(const struct pl330_info *pi); | ||
213 | extern int pl330_chan_status(void *ch_id, struct pl330_chanstatus *pstatus); | ||
214 | extern int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op); | ||
215 | extern int pl330_submit_req(void *ch_id, struct pl330_req *r); | ||
216 | |||
217 | #endif /* __PL330_CORE_H */ | ||
diff --git a/arch/arm/include/asm/hardware/sa1111.h b/arch/arm/include/asm/hardware/sa1111.h index 92ed254c175b..7c2bbc7f0be1 100644 --- a/arch/arm/include/asm/hardware/sa1111.h +++ b/arch/arm/include/asm/hardware/sa1111.h | |||
@@ -132,34 +132,10 @@ | |||
132 | #define SKPCR_DCLKEN (1<<7) | 132 | #define SKPCR_DCLKEN (1<<7) |
133 | #define SKPCR_PWMCLKEN (1<<8) | 133 | #define SKPCR_PWMCLKEN (1<<8) |
134 | 134 | ||
135 | /* | 135 | /* USB Host controller */ |
136 | * USB Host controller | ||
137 | */ | ||
138 | #define SA1111_USB 0x0400 | 136 | #define SA1111_USB 0x0400 |
139 | 137 | ||
140 | /* | 138 | /* |
141 | * Offsets from SA1111_USB_BASE | ||
142 | */ | ||
143 | #define SA1111_USB_STATUS 0x0118 | ||
144 | #define SA1111_USB_RESET 0x011c | ||
145 | #define SA1111_USB_IRQTEST 0x0120 | ||
146 | |||
147 | #define USB_RESET_FORCEIFRESET (1 << 0) | ||
148 | #define USB_RESET_FORCEHCRESET (1 << 1) | ||
149 | #define USB_RESET_CLKGENRESET (1 << 2) | ||
150 | #define USB_RESET_SIMSCALEDOWN (1 << 3) | ||
151 | #define USB_RESET_USBINTTEST (1 << 4) | ||
152 | #define USB_RESET_SLEEPSTBYEN (1 << 5) | ||
153 | #define USB_RESET_PWRSENSELOW (1 << 6) | ||
154 | #define USB_RESET_PWRCTRLLOW (1 << 7) | ||
155 | |||
156 | #define USB_STATUS_IRQHCIRMTWKUP (1 << 7) | ||
157 | #define USB_STATUS_IRQHCIBUFFACC (1 << 8) | ||
158 | #define USB_STATUS_NIRQHCIM (1 << 9) | ||
159 | #define USB_STATUS_NHCIMFCLR (1 << 10) | ||
160 | #define USB_STATUS_USBPWRSENSE (1 << 11) | ||
161 | |||
162 | /* | ||
163 | * Serial Audio Controller | 139 | * Serial Audio Controller |
164 | * | 140 | * |
165 | * Registers | 141 | * Registers |
@@ -327,22 +303,6 @@ | |||
327 | * PC_SSR GPIO Block C Sleep State | 303 | * PC_SSR GPIO Block C Sleep State |
328 | */ | 304 | */ |
329 | 305 | ||
330 | #define _PA_DDR _SA1111( 0x1000 ) | ||
331 | #define _PA_DRR _SA1111( 0x1004 ) | ||
332 | #define _PA_DWR _SA1111( 0x1004 ) | ||
333 | #define _PA_SDR _SA1111( 0x1008 ) | ||
334 | #define _PA_SSR _SA1111( 0x100c ) | ||
335 | #define _PB_DDR _SA1111( 0x1010 ) | ||
336 | #define _PB_DRR _SA1111( 0x1014 ) | ||
337 | #define _PB_DWR _SA1111( 0x1014 ) | ||
338 | #define _PB_SDR _SA1111( 0x1018 ) | ||
339 | #define _PB_SSR _SA1111( 0x101c ) | ||
340 | #define _PC_DDR _SA1111( 0x1020 ) | ||
341 | #define _PC_DRR _SA1111( 0x1024 ) | ||
342 | #define _PC_DWR _SA1111( 0x1024 ) | ||
343 | #define _PC_SDR _SA1111( 0x1028 ) | ||
344 | #define _PC_SSR _SA1111( 0x102c ) | ||
345 | |||
346 | #define SA1111_GPIO 0x1000 | 306 | #define SA1111_GPIO 0x1000 |
347 | 307 | ||
348 | #define SA1111_GPIO_PADDR (0x000) | 308 | #define SA1111_GPIO_PADDR (0x000) |
@@ -425,106 +385,30 @@ | |||
425 | #define SA1111_WAKEPOL0 0x0034 | 385 | #define SA1111_WAKEPOL0 0x0034 |
426 | #define SA1111_WAKEPOL1 0x0038 | 386 | #define SA1111_WAKEPOL1 0x0038 |
427 | 387 | ||
428 | /* | 388 | /* PS/2 Trackpad and Mouse Interfaces */ |
429 | * PS/2 Trackpad and Mouse Interfaces | ||
430 | * | ||
431 | * Registers | ||
432 | * PS2CR Control Register | ||
433 | * PS2STAT Status Register | ||
434 | * PS2DATA Transmit/Receive Data register | ||
435 | * PS2CLKDIV Clock Division Register | ||
436 | * PS2PRECNT Clock Precount Register | ||
437 | * PS2TEST1 Test register 1 | ||
438 | * PS2TEST2 Test register 2 | ||
439 | * PS2TEST3 Test register 3 | ||
440 | * PS2TEST4 Test register 4 | ||
441 | */ | ||
442 | |||
443 | #define SA1111_KBD 0x0a00 | 389 | #define SA1111_KBD 0x0a00 |
444 | #define SA1111_MSE 0x0c00 | 390 | #define SA1111_MSE 0x0c00 |
445 | 391 | ||
446 | /* | 392 | /* PCMCIA Interface */ |
447 | * These are offsets from the above bases. | 393 | #define SA1111_PCMCIA 0x1600 |
448 | */ | ||
449 | #define SA1111_PS2CR 0x0000 | ||
450 | #define SA1111_PS2STAT 0x0004 | ||
451 | #define SA1111_PS2DATA 0x0008 | ||
452 | #define SA1111_PS2CLKDIV 0x000c | ||
453 | #define SA1111_PS2PRECNT 0x0010 | ||
454 | |||
455 | #define PS2CR_ENA 0x08 | ||
456 | #define PS2CR_FKD 0x02 | ||
457 | #define PS2CR_FKC 0x01 | ||
458 | |||
459 | #define PS2STAT_STP 0x0100 | ||
460 | #define PS2STAT_TXE 0x0080 | ||
461 | #define PS2STAT_TXB 0x0040 | ||
462 | #define PS2STAT_RXF 0x0020 | ||
463 | #define PS2STAT_RXB 0x0010 | ||
464 | #define PS2STAT_ENA 0x0008 | ||
465 | #define PS2STAT_RXP 0x0004 | ||
466 | #define PS2STAT_KBD 0x0002 | ||
467 | #define PS2STAT_KBC 0x0001 | ||
468 | 394 | ||
469 | /* | ||
470 | * PCMCIA Interface | ||
471 | * | ||
472 | * Registers | ||
473 | * PCSR Status Register | ||
474 | * PCCR Control Register | ||
475 | * PCSSR Sleep State Register | ||
476 | */ | ||
477 | |||
478 | #define SA1111_PCMCIA 0x1600 | ||
479 | |||
480 | /* | ||
481 | * These are offsets from the above base. | ||
482 | */ | ||
483 | #define SA1111_PCCR 0x0000 | ||
484 | #define SA1111_PCSSR 0x0004 | ||
485 | #define SA1111_PCSR 0x0008 | ||
486 | |||
487 | #define PCSR_S0_READY (1<<0) | ||
488 | #define PCSR_S1_READY (1<<1) | ||
489 | #define PCSR_S0_DETECT (1<<2) | ||
490 | #define PCSR_S1_DETECT (1<<3) | ||
491 | #define PCSR_S0_VS1 (1<<4) | ||
492 | #define PCSR_S0_VS2 (1<<5) | ||
493 | #define PCSR_S1_VS1 (1<<6) | ||
494 | #define PCSR_S1_VS2 (1<<7) | ||
495 | #define PCSR_S0_WP (1<<8) | ||
496 | #define PCSR_S1_WP (1<<9) | ||
497 | #define PCSR_S0_BVD1 (1<<10) | ||
498 | #define PCSR_S0_BVD2 (1<<11) | ||
499 | #define PCSR_S1_BVD1 (1<<12) | ||
500 | #define PCSR_S1_BVD2 (1<<13) | ||
501 | |||
502 | #define PCCR_S0_RST (1<<0) | ||
503 | #define PCCR_S1_RST (1<<1) | ||
504 | #define PCCR_S0_FLT (1<<2) | ||
505 | #define PCCR_S1_FLT (1<<3) | ||
506 | #define PCCR_S0_PWAITEN (1<<4) | ||
507 | #define PCCR_S1_PWAITEN (1<<5) | ||
508 | #define PCCR_S0_PSE (1<<6) | ||
509 | #define PCCR_S1_PSE (1<<7) | ||
510 | |||
511 | #define PCSSR_S0_SLEEP (1<<0) | ||
512 | #define PCSSR_S1_SLEEP (1<<1) | ||
513 | 395 | ||
514 | 396 | ||
515 | 397 | ||
516 | 398 | ||
517 | extern struct bus_type sa1111_bus_type; | 399 | extern struct bus_type sa1111_bus_type; |
518 | 400 | ||
519 | #define SA1111_DEVID_SBI 0 | 401 | #define SA1111_DEVID_SBI (1 << 0) |
520 | #define SA1111_DEVID_SK 1 | 402 | #define SA1111_DEVID_SK (1 << 1) |
521 | #define SA1111_DEVID_USB 2 | 403 | #define SA1111_DEVID_USB (1 << 2) |
522 | #define SA1111_DEVID_SAC 3 | 404 | #define SA1111_DEVID_SAC (1 << 3) |
523 | #define SA1111_DEVID_SSP 4 | 405 | #define SA1111_DEVID_SSP (1 << 4) |
524 | #define SA1111_DEVID_PS2 5 | 406 | #define SA1111_DEVID_PS2 (3 << 5) |
525 | #define SA1111_DEVID_GPIO 6 | 407 | #define SA1111_DEVID_PS2_KBD (1 << 5) |
526 | #define SA1111_DEVID_INT 7 | 408 | #define SA1111_DEVID_PS2_MSE (1 << 6) |
527 | #define SA1111_DEVID_PCMCIA 8 | 409 | #define SA1111_DEVID_GPIO (1 << 7) |
410 | #define SA1111_DEVID_INT (1 << 8) | ||
411 | #define SA1111_DEVID_PCMCIA (1 << 9) | ||
528 | 412 | ||
529 | struct sa1111_dev { | 413 | struct sa1111_dev { |
530 | struct device dev; | 414 | struct device dev; |
@@ -548,6 +432,7 @@ struct sa1111_driver { | |||
548 | int (*remove)(struct sa1111_dev *); | 432 | int (*remove)(struct sa1111_dev *); |
549 | int (*suspend)(struct sa1111_dev *, pm_message_t); | 433 | int (*suspend)(struct sa1111_dev *, pm_message_t); |
550 | int (*resume)(struct sa1111_dev *); | 434 | int (*resume)(struct sa1111_dev *); |
435 | void (*shutdown)(struct sa1111_dev *); | ||
551 | }; | 436 | }; |
552 | 437 | ||
553 | #define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv) | 438 | #define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv) |
@@ -555,9 +440,10 @@ struct sa1111_driver { | |||
555 | #define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name) | 440 | #define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name) |
556 | 441 | ||
557 | /* | 442 | /* |
558 | * These frob the SKPCR register. | 443 | * These frob the SKPCR register, and call platform specific |
444 | * enable/disable functions. | ||
559 | */ | 445 | */ |
560 | void sa1111_enable_device(struct sa1111_dev *); | 446 | int sa1111_enable_device(struct sa1111_dev *); |
561 | void sa1111_disable_device(struct sa1111_dev *); | 447 | void sa1111_disable_device(struct sa1111_dev *); |
562 | 448 | ||
563 | unsigned int sa1111_pll_clock(struct sa1111_dev *); | 449 | unsigned int sa1111_pll_clock(struct sa1111_dev *); |
@@ -580,6 +466,10 @@ void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned i | |||
580 | 466 | ||
581 | struct sa1111_platform_data { | 467 | struct sa1111_platform_data { |
582 | int irq_base; /* base for cascaded on-chip IRQs */ | 468 | int irq_base; /* base for cascaded on-chip IRQs */ |
469 | unsigned disable_devs; | ||
470 | void *data; | ||
471 | int (*enable)(void *, unsigned); | ||
472 | void (*disable)(void *, unsigned); | ||
583 | }; | 473 | }; |
584 | 474 | ||
585 | #endif /* _ASM_ARCH_SA1111 */ | 475 | #endif /* _ASM_ARCH_SA1111 */ |
diff --git a/arch/arm/include/asm/hardware/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h index 4384d81eee79..2dd9d3f83f29 100644 --- a/arch/arm/include/asm/hardware/timer-sp.h +++ b/arch/arm/include/asm/hardware/timer-sp.h | |||
@@ -1,2 +1,15 @@ | |||
1 | void sp804_clocksource_init(void __iomem *, const char *); | 1 | void __sp804_clocksource_and_sched_clock_init(void __iomem *, |
2 | const char *, int); | ||
3 | |||
4 | static inline void sp804_clocksource_init(void __iomem *base, const char *name) | ||
5 | { | ||
6 | __sp804_clocksource_and_sched_clock_init(base, name, 0); | ||
7 | } | ||
8 | |||
9 | static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base, | ||
10 | const char *name) | ||
11 | { | ||
12 | __sp804_clocksource_and_sched_clock_init(base, name, 1); | ||
13 | } | ||
14 | |||
2 | void sp804_clockevents_init(void __iomem *, unsigned int, const char *); | 15 | void sp804_clockevents_init(void __iomem *, unsigned int, const char *); |