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-rw-r--r--arch/arm/include/asm/hardware/arm_timer.h39
-rw-r--r--arch/arm/include/asm/hardware/cache-l2x0.h3
-rw-r--r--arch/arm/include/asm/hardware/icst.h59
-rw-r--r--arch/arm/include/asm/hardware/icst307.h38
-rw-r--r--arch/arm/include/asm/hardware/icst525.h36
-rw-r--r--arch/arm/include/asm/hardware/pl330.h217
-rw-r--r--arch/arm/include/asm/hardware/sp810.h59
7 files changed, 362 insertions, 89 deletions
diff --git a/arch/arm/include/asm/hardware/arm_timer.h b/arch/arm/include/asm/hardware/arm_timer.h
index 04be3bdf46b8..c0f4e7bf22de 100644
--- a/arch/arm/include/asm/hardware/arm_timer.h
+++ b/arch/arm/include/asm/hardware/arm_timer.h
@@ -1,21 +1,30 @@
1#ifndef __ASM_ARM_HARDWARE_ARM_TIMER_H 1#ifndef __ASM_ARM_HARDWARE_ARM_TIMER_H
2#define __ASM_ARM_HARDWARE_ARM_TIMER_H 2#define __ASM_ARM_HARDWARE_ARM_TIMER_H
3 3
4#define TIMER_LOAD 0x00 4/*
5#define TIMER_VALUE 0x04 5 * ARM timer implementation, found in Integrator, Versatile and Realview
6#define TIMER_CTRL 0x08 6 * platforms. Not all platforms support all registers and bits in these
7#define TIMER_CTRL_ONESHOT (1 << 0) 7 * registers, so we mark them with A for Integrator AP, C for Integrator
8#define TIMER_CTRL_32BIT (1 << 1) 8 * CP, V for Versatile and R for Realview.
9#define TIMER_CTRL_DIV1 (0 << 2) 9 *
10#define TIMER_CTRL_DIV16 (1 << 2) 10 * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
11#define TIMER_CTRL_DIV256 (2 << 2) 11 * can have 16-bit or 32-bit selectable via a bit in the control register.
12#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */ 12 */
13#define TIMER_CTRL_PERIODIC (1 << 6) 13#define TIMER_LOAD 0x00 /* ACVR rw */
14#define TIMER_CTRL_ENABLE (1 << 7) 14#define TIMER_VALUE 0x04 /* ACVR ro */
15#define TIMER_CTRL 0x08 /* ACVR rw */
16#define TIMER_CTRL_ONESHOT (1 << 0) /* CVR */
17#define TIMER_CTRL_32BIT (1 << 1) /* CVR */
18#define TIMER_CTRL_DIV1 (0 << 2) /* ACVR */
19#define TIMER_CTRL_DIV16 (1 << 2) /* ACVR */
20#define TIMER_CTRL_DIV256 (2 << 2) /* ACVR */
21#define TIMER_CTRL_IE (1 << 5) /* VR */
22#define TIMER_CTRL_PERIODIC (1 << 6) /* ACVR */
23#define TIMER_CTRL_ENABLE (1 << 7) /* ACVR */
15 24
16#define TIMER_INTCLR 0x0c 25#define TIMER_INTCLR 0x0c /* ACVR wo */
17#define TIMER_RIS 0x10 26#define TIMER_RIS 0x10 /* CVR ro */
18#define TIMER_MIS 0x14 27#define TIMER_MIS 0x14 /* CVR ro */
19#define TIMER_BGLOAD 0x18 28#define TIMER_BGLOAD 0x18 /* CVR rw */
20 29
21#endif 30#endif
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index cdb9022716fd..6bcba48800fe 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -21,6 +21,9 @@
21#define __ASM_ARM_HARDWARE_L2X0_H 21#define __ASM_ARM_HARDWARE_L2X0_H
22 22
23#define L2X0_CACHE_ID 0x000 23#define L2X0_CACHE_ID 0x000
24#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
25#define L2X0_CACHE_ID_PART_L210 (1 << 6)
26#define L2X0_CACHE_ID_PART_L310 (3 << 6)
24#define L2X0_CACHE_TYPE 0x004 27#define L2X0_CACHE_TYPE 0x004
25#define L2X0_CTRL 0x100 28#define L2X0_CTRL 0x100
26#define L2X0_AUX_CTRL 0x104 29#define L2X0_AUX_CTRL 0x104
diff --git a/arch/arm/include/asm/hardware/icst.h b/arch/arm/include/asm/hardware/icst.h
new file mode 100644
index 000000000000..10382a3dcec9
--- /dev/null
+++ b/arch/arm/include/asm/hardware/icst.h
@@ -0,0 +1,59 @@
1/*
2 * arch/arm/include/asm/hardware/icst.h
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Support functions for calculating clocks/divisors for the ICST
11 * clock generators. See http://www.icst.com/ for more information
12 * on these devices.
13 */
14#ifndef ASMARM_HARDWARE_ICST_H
15#define ASMARM_HARDWARE_ICST_H
16
17struct icst_params {
18 unsigned long ref;
19 unsigned long vco_max; /* inclusive */
20 unsigned long vco_min; /* exclusive */
21 unsigned short vd_min; /* inclusive */
22 unsigned short vd_max; /* inclusive */
23 unsigned char rd_min; /* inclusive */
24 unsigned char rd_max; /* inclusive */
25 const unsigned char *s2div; /* chip specific s2div array */
26 const unsigned char *idx2s; /* chip specific idx2s array */
27};
28
29struct icst_vco {
30 unsigned short v;
31 unsigned char r;
32 unsigned char s;
33};
34
35unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco);
36struct icst_vco icst_hz_to_vco(const struct icst_params *p, unsigned long freq);
37
38/*
39 * ICST307 VCO frequency must be between 6MHz and 200MHz (3.3 or 5V).
40 * This frequency is pre-output divider.
41 */
42#define ICST307_VCO_MIN 6000000
43#define ICST307_VCO_MAX 200000000
44
45extern const unsigned char icst307_s2div[];
46extern const unsigned char icst307_idx2s[];
47
48/*
49 * ICST525 VCO frequency must be between 10MHz and 200MHz (3V) or 320MHz (5V).
50 * This frequency is pre-output divider.
51 */
52#define ICST525_VCO_MIN 10000000
53#define ICST525_VCO_MAX_3V 200000000
54#define ICST525_VCO_MAX_5V 320000000
55
56extern const unsigned char icst525_s2div[];
57extern const unsigned char icst525_idx2s[];
58
59#endif
diff --git a/arch/arm/include/asm/hardware/icst307.h b/arch/arm/include/asm/hardware/icst307.h
deleted file mode 100644
index 554f128a1046..000000000000
--- a/arch/arm/include/asm/hardware/icst307.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * arch/arm/include/asm/hardware/icst307.h
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Support functions for calculating clocks/divisors for the ICS307
11 * clock generators. See http://www.icst.com/ for more information
12 * on these devices.
13 *
14 * This file is similar to the icst525.h file
15 */
16#ifndef ASMARM_HARDWARE_ICST307_H
17#define ASMARM_HARDWARE_ICST307_H
18
19struct icst307_params {
20 unsigned long ref;
21 unsigned long vco_max; /* inclusive */
22 unsigned short vd_min; /* inclusive */
23 unsigned short vd_max; /* inclusive */
24 unsigned char rd_min; /* inclusive */
25 unsigned char rd_max; /* inclusive */
26};
27
28struct icst307_vco {
29 unsigned short v;
30 unsigned char r;
31 unsigned char s;
32};
33
34unsigned long icst307_khz(const struct icst307_params *p, struct icst307_vco vco);
35struct icst307_vco icst307_khz_to_vco(const struct icst307_params *p, unsigned long freq);
36struct icst307_vco icst307_ps_to_vco(const struct icst307_params *p, unsigned long period);
37
38#endif
diff --git a/arch/arm/include/asm/hardware/icst525.h b/arch/arm/include/asm/hardware/icst525.h
deleted file mode 100644
index 58f0dc43e2ed..000000000000
--- a/arch/arm/include/asm/hardware/icst525.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * arch/arm/include/asm/hardware/icst525.h
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Support functions for calculating clocks/divisors for the ICST525
11 * clock generators. See http://www.icst.com/ for more information
12 * on these devices.
13 */
14#ifndef ASMARM_HARDWARE_ICST525_H
15#define ASMARM_HARDWARE_ICST525_H
16
17struct icst525_params {
18 unsigned long ref;
19 unsigned long vco_max; /* inclusive */
20 unsigned short vd_min; /* inclusive */
21 unsigned short vd_max; /* inclusive */
22 unsigned char rd_min; /* inclusive */
23 unsigned char rd_max; /* inclusive */
24};
25
26struct icst525_vco {
27 unsigned short v;
28 unsigned char r;
29 unsigned char s;
30};
31
32unsigned long icst525_khz(const struct icst525_params *p, struct icst525_vco vco);
33struct icst525_vco icst525_khz_to_vco(const struct icst525_params *p, unsigned long freq);
34struct icst525_vco icst525_ps_to_vco(const struct icst525_params *p, unsigned long period);
35
36#endif
diff --git a/arch/arm/include/asm/hardware/pl330.h b/arch/arm/include/asm/hardware/pl330.h
new file mode 100644
index 000000000000..575fa8186ca0
--- /dev/null
+++ b/arch/arm/include/asm/hardware/pl330.h
@@ -0,0 +1,217 @@
1/* linux/include/asm/hardware/pl330.h
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#ifndef __PL330_CORE_H
22#define __PL330_CORE_H
23
24#define PL330_MAX_CHAN 8
25#define PL330_MAX_IRQS 32
26#define PL330_MAX_PERI 32
27
28enum pl330_srccachectrl {
29 SCCTRL0 = 0, /* Noncacheable and nonbufferable */
30 SCCTRL1, /* Bufferable only */
31 SCCTRL2, /* Cacheable, but do not allocate */
32 SCCTRL3, /* Cacheable and bufferable, but do not allocate */
33 SINVALID1,
34 SINVALID2,
35 SCCTRL6, /* Cacheable write-through, allocate on reads only */
36 SCCTRL7, /* Cacheable write-back, allocate on reads only */
37};
38
39enum pl330_dstcachectrl {
40 DCCTRL0 = 0, /* Noncacheable and nonbufferable */
41 DCCTRL1, /* Bufferable only */
42 DCCTRL2, /* Cacheable, but do not allocate */
43 DCCTRL3, /* Cacheable and bufferable, but do not allocate */
44 DINVALID1 = 8,
45 DINVALID2,
46 DCCTRL6, /* Cacheable write-through, allocate on writes only */
47 DCCTRL7, /* Cacheable write-back, allocate on writes only */
48};
49
50/* Populated by the PL330 core driver for DMA API driver's info */
51struct pl330_config {
52 u32 periph_id;
53 u32 pcell_id;
54#define DMAC_MODE_NS (1 << 0)
55 unsigned int mode;
56 unsigned int data_bus_width:10; /* In number of bits */
57 unsigned int data_buf_dep:10;
58 unsigned int num_chan:4;
59 unsigned int num_peri:6;
60 u32 peri_ns;
61 unsigned int num_events:6;
62 u32 irq_ns;
63};
64
65/* Handle to the DMAC provided to the PL330 core */
66struct pl330_info {
67 /* Owning device */
68 struct device *dev;
69 /* Size of MicroCode buffers for each channel. */
70 unsigned mcbufsz;
71 /* ioremap'ed address of PL330 registers. */
72 void __iomem *base;
73 /* Client can freely use it. */
74 void *client_data;
75 /* PL330 core data, Client must not touch it. */
76 void *pl330_data;
77 /* Populated by the PL330 core driver during pl330_add */
78 struct pl330_config pcfg;
79 /*
80 * If the DMAC has some reset mechanism, then the
81 * client may want to provide pointer to the method.
82 */
83 void (*dmac_reset)(struct pl330_info *pi);
84};
85
86enum pl330_byteswap {
87 SWAP_NO = 0,
88 SWAP_2,
89 SWAP_4,
90 SWAP_8,
91 SWAP_16,
92};
93
94/**
95 * Request Configuration.
96 * The PL330 core does not modify this and uses the last
97 * working configuration if the request doesn't provide any.
98 *
99 * The Client may want to provide this info only for the
100 * first request and a request with new settings.
101 */
102struct pl330_reqcfg {
103 /* Address Incrementing */
104 unsigned dst_inc:1;
105 unsigned src_inc:1;
106
107 /*
108 * For now, the SRC & DST protection levels
109 * and burst size/length are assumed same.
110 */
111 bool nonsecure;
112 bool privileged;
113 bool insnaccess;
114 unsigned brst_len:5;
115 unsigned brst_size:3; /* in power of 2 */
116
117 enum pl330_dstcachectrl dcctl;
118 enum pl330_srccachectrl scctl;
119 enum pl330_byteswap swap;
120};
121
122/*
123 * One cycle of DMAC operation.
124 * There may be more than one xfer in a request.
125 */
126struct pl330_xfer {
127 u32 src_addr;
128 u32 dst_addr;
129 /* Size to xfer */
130 u32 bytes;
131 /*
132 * Pointer to next xfer in the list.
133 * The last xfer in the req must point to NULL.
134 */
135 struct pl330_xfer *next;
136};
137
138/* The xfer callbacks are made with one of these arguments. */
139enum pl330_op_err {
140 /* The all xfers in the request were success. */
141 PL330_ERR_NONE,
142 /* If req aborted due to global error. */
143 PL330_ERR_ABORT,
144 /* If req failed due to problem with Channel. */
145 PL330_ERR_FAIL,
146};
147
148enum pl330_reqtype {
149 MEMTOMEM,
150 MEMTODEV,
151 DEVTOMEM,
152 DEVTODEV,
153};
154
155/* A request defining Scatter-Gather List ending with NULL xfer. */
156struct pl330_req {
157 enum pl330_reqtype rqtype;
158 /* Index of peripheral for the xfer. */
159 unsigned peri:5;
160 /* Unique token for this xfer, set by the client. */
161 void *token;
162 /* Callback to be called after xfer. */
163 void (*xfer_cb)(void *token, enum pl330_op_err err);
164 /* If NULL, req will be done at last set parameters. */
165 struct pl330_reqcfg *cfg;
166 /* Pointer to first xfer in the request. */
167 struct pl330_xfer *x;
168};
169
170/*
171 * To know the status of the channel and DMAC, the client
172 * provides a pointer to this structure. The PL330 core
173 * fills it with current information.
174 */
175struct pl330_chanstatus {
176 /*
177 * If the DMAC engine halted due to some error,
178 * the client should remove-add DMAC.
179 */
180 bool dmac_halted;
181 /*
182 * If channel is halted due to some error,
183 * the client should ABORT/FLUSH and START the channel.
184 */
185 bool faulting;
186 /* Location of last load */
187 u32 src_addr;
188 /* Location of last store */
189 u32 dst_addr;
190 /*
191 * Pointer to the currently active req, NULL if channel is
192 * inactive, even though the requests may be present.
193 */
194 struct pl330_req *top_req;
195 /* Pointer to req waiting second in the queue if any. */
196 struct pl330_req *wait_req;
197};
198
199enum pl330_chan_op {
200 /* Start the channel */
201 PL330_OP_START,
202 /* Abort the active xfer */
203 PL330_OP_ABORT,
204 /* Stop xfer and flush queue */
205 PL330_OP_FLUSH,
206};
207
208extern int pl330_add(struct pl330_info *);
209extern void pl330_del(struct pl330_info *pi);
210extern int pl330_update(const struct pl330_info *pi);
211extern void pl330_release_channel(void *ch_id);
212extern void *pl330_request_channel(const struct pl330_info *pi);
213extern int pl330_chan_status(void *ch_id, struct pl330_chanstatus *pstatus);
214extern int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op);
215extern int pl330_submit_req(void *ch_id, struct pl330_req *r);
216
217#endif /* __PL330_CORE_H */
diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h
new file mode 100644
index 000000000000..a101f10bb5b1
--- /dev/null
+++ b/arch/arm/include/asm/hardware/sp810.h
@@ -0,0 +1,59 @@
1/*
2 * arch/arm/include/asm/hardware/sp810.h
3 *
4 * ARM PrimeXsys System Controller SP810 header file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __ASM_ARM_SP810_H
15#define __ASM_ARM_SP810_H
16
17#include <linux/io.h>
18
19/* sysctl registers offset */
20#define SCCTRL 0x000
21#define SCSYSSTAT 0x004
22#define SCIMCTRL 0x008
23#define SCIMSTAT 0x00C
24#define SCXTALCTRL 0x010
25#define SCPLLCTRL 0x014
26#define SCPLLFCTRL 0x018
27#define SCPERCTRL0 0x01C
28#define SCPERCTRL1 0x020
29#define SCPEREN 0x024
30#define SCPERDIS 0x028
31#define SCPERCLKEN 0x02C
32#define SCPERSTAT 0x030
33#define SCSYSID0 0xEE0
34#define SCSYSID1 0xEE4
35#define SCSYSID2 0xEE8
36#define SCSYSID3 0xEEC
37#define SCITCR 0xF00
38#define SCITIR0 0xF04
39#define SCITIR1 0xF08
40#define SCITOR 0xF0C
41#define SCCNTCTRL 0xF10
42#define SCCNTDATA 0xF14
43#define SCCNTSTEP 0xF18
44#define SCPERIPHID0 0xFE0
45#define SCPERIPHID1 0xFE4
46#define SCPERIPHID2 0xFE8
47#define SCPERIPHID3 0xFEC
48#define SCPCELLID0 0xFF0
49#define SCPCELLID1 0xFF4
50#define SCPCELLID2 0xFF8
51#define SCPCELLID3 0xFFC
52
53static inline void sysctl_soft_reset(void __iomem *base)
54{
55 /* writing any value to SCSYSSTAT reg will reset system */
56 writel(0, base + SCSYSSTAT);
57}
58
59#endif /* __ASM_ARM_SP810_H */
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