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-rw-r--r--arch/arm/include/asm/hardware/arm_timer.h21
-rw-r--r--arch/arm/include/asm/hardware/arm_twd.h21
-rw-r--r--arch/arm/include/asm/hardware/cache-l2x0.h56
-rw-r--r--arch/arm/include/asm/hardware/clps7111.h184
-rw-r--r--arch/arm/include/asm/hardware/cs89712.h49
-rw-r--r--arch/arm/include/asm/hardware/debug-8250.S29
-rw-r--r--arch/arm/include/asm/hardware/debug-pl01x.S29
-rw-r--r--arch/arm/include/asm/hardware/dec21285.h147
-rw-r--r--arch/arm/include/asm/hardware/entry-macro-iomd.S139
-rw-r--r--arch/arm/include/asm/hardware/ep7211.h40
-rw-r--r--arch/arm/include/asm/hardware/ep7212.h83
-rw-r--r--arch/arm/include/asm/hardware/gic.h42
-rw-r--r--arch/arm/include/asm/hardware/icst307.h38
-rw-r--r--arch/arm/include/asm/hardware/icst525.h36
-rw-r--r--arch/arm/include/asm/hardware/ioc.h72
-rw-r--r--arch/arm/include/asm/hardware/iomd.h226
-rw-r--r--arch/arm/include/asm/hardware/iop3xx-adma.h888
-rw-r--r--arch/arm/include/asm/hardware/iop3xx-gpio.h73
-rw-r--r--arch/arm/include/asm/hardware/iop3xx.h312
-rw-r--r--arch/arm/include/asm/hardware/iop_adma.h116
-rw-r--r--arch/arm/include/asm/hardware/it8152.h99
-rw-r--r--arch/arm/include/asm/hardware/linkup-l1110.h48
-rw-r--r--arch/arm/include/asm/hardware/locomo.h217
-rw-r--r--arch/arm/include/asm/hardware/memc.h26
-rw-r--r--arch/arm/include/asm/hardware/pci_v3.h186
-rw-r--r--arch/arm/include/asm/hardware/sa1111.h581
-rw-r--r--arch/arm/include/asm/hardware/scoop.h69
-rw-r--r--arch/arm/include/asm/hardware/sharpsl_pm.h106
-rw-r--r--arch/arm/include/asm/hardware/ssp.h28
-rw-r--r--arch/arm/include/asm/hardware/uengine.h62
-rw-r--r--arch/arm/include/asm/hardware/vic.h45
31 files changed, 4068 insertions, 0 deletions
diff --git a/arch/arm/include/asm/hardware/arm_timer.h b/arch/arm/include/asm/hardware/arm_timer.h
new file mode 100644
index 000000000000..04be3bdf46b8
--- /dev/null
+++ b/arch/arm/include/asm/hardware/arm_timer.h
@@ -0,0 +1,21 @@
1#ifndef __ASM_ARM_HARDWARE_ARM_TIMER_H
2#define __ASM_ARM_HARDWARE_ARM_TIMER_H
3
4#define TIMER_LOAD 0x00
5#define TIMER_VALUE 0x04
6#define TIMER_CTRL 0x08
7#define TIMER_CTRL_ONESHOT (1 << 0)
8#define TIMER_CTRL_32BIT (1 << 1)
9#define TIMER_CTRL_DIV1 (0 << 2)
10#define TIMER_CTRL_DIV16 (1 << 2)
11#define TIMER_CTRL_DIV256 (2 << 2)
12#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */
13#define TIMER_CTRL_PERIODIC (1 << 6)
14#define TIMER_CTRL_ENABLE (1 << 7)
15
16#define TIMER_INTCLR 0x0c
17#define TIMER_RIS 0x10
18#define TIMER_MIS 0x14
19#define TIMER_BGLOAD 0x18
20
21#endif
diff --git a/arch/arm/include/asm/hardware/arm_twd.h b/arch/arm/include/asm/hardware/arm_twd.h
new file mode 100644
index 000000000000..e521b70713c8
--- /dev/null
+++ b/arch/arm/include/asm/hardware/arm_twd.h
@@ -0,0 +1,21 @@
1#ifndef __ASM_HARDWARE_TWD_H
2#define __ASM_HARDWARE_TWD_H
3
4#define TWD_TIMER_LOAD 0x00
5#define TWD_TIMER_COUNTER 0x04
6#define TWD_TIMER_CONTROL 0x08
7#define TWD_TIMER_INTSTAT 0x0C
8
9#define TWD_WDOG_LOAD 0x20
10#define TWD_WDOG_COUNTER 0x24
11#define TWD_WDOG_CONTROL 0x28
12#define TWD_WDOG_INTSTAT 0x2C
13#define TWD_WDOG_RESETSTAT 0x30
14#define TWD_WDOG_DISABLE 0x34
15
16#define TWD_TIMER_CONTROL_ENABLE (1 << 0)
17#define TWD_TIMER_CONTROL_ONESHOT (0 << 1)
18#define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
19#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
20
21#endif
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
new file mode 100644
index 000000000000..64f2252a25cd
--- /dev/null
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -0,0 +1,56 @@
1/*
2 * arch/arm/include/asm/hardware/cache-l2x0.h
3 *
4 * Copyright (C) 2007 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef __ASM_ARM_HARDWARE_L2X0_H
21#define __ASM_ARM_HARDWARE_L2X0_H
22
23#define L2X0_CACHE_ID 0x000
24#define L2X0_CACHE_TYPE 0x004
25#define L2X0_CTRL 0x100
26#define L2X0_AUX_CTRL 0x104
27#define L2X0_EVENT_CNT_CTRL 0x200
28#define L2X0_EVENT_CNT1_CFG 0x204
29#define L2X0_EVENT_CNT0_CFG 0x208
30#define L2X0_EVENT_CNT1_VAL 0x20C
31#define L2X0_EVENT_CNT0_VAL 0x210
32#define L2X0_INTR_MASK 0x214
33#define L2X0_MASKED_INTR_STAT 0x218
34#define L2X0_RAW_INTR_STAT 0x21C
35#define L2X0_INTR_CLEAR 0x220
36#define L2X0_CACHE_SYNC 0x730
37#define L2X0_INV_LINE_PA 0x770
38#define L2X0_INV_WAY 0x77C
39#define L2X0_CLEAN_LINE_PA 0x7B0
40#define L2X0_CLEAN_LINE_IDX 0x7B8
41#define L2X0_CLEAN_WAY 0x7BC
42#define L2X0_CLEAN_INV_LINE_PA 0x7F0
43#define L2X0_CLEAN_INV_LINE_IDX 0x7F8
44#define L2X0_CLEAN_INV_WAY 0x7FC
45#define L2X0_LOCKDOWN_WAY_D 0x900
46#define L2X0_LOCKDOWN_WAY_I 0x904
47#define L2X0_TEST_OPERATION 0xF00
48#define L2X0_LINE_DATA 0xF10
49#define L2X0_LINE_TAG 0xF30
50#define L2X0_DEBUG_CTRL 0xF40
51
52#ifndef __ASSEMBLY__
53extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
54#endif
55
56#endif
diff --git a/arch/arm/include/asm/hardware/clps7111.h b/arch/arm/include/asm/hardware/clps7111.h
new file mode 100644
index 000000000000..44477225aed6
--- /dev/null
+++ b/arch/arm/include/asm/hardware/clps7111.h
@@ -0,0 +1,184 @@
1/*
2 * arch/arm/include/asm/hardware/clps7111.h
3 *
4 * This file contains the hardware definitions of the CLPS7111 internal
5 * registers.
6 *
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef __ASM_HARDWARE_CLPS7111_H
24#define __ASM_HARDWARE_CLPS7111_H
25
26#define CLPS7111_PHYS_BASE (0x80000000)
27
28#ifndef __ASSEMBLY__
29#define clps_readb(off) __raw_readb(CLPS7111_BASE + (off))
30#define clps_readw(off) __raw_readw(CLPS7111_BASE + (off))
31#define clps_readl(off) __raw_readl(CLPS7111_BASE + (off))
32#define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off))
33#define clps_writew(val,off) __raw_writew(val, CLPS7111_BASE + (off))
34#define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off))
35#endif
36
37#define PADR (0x0000)
38#define PBDR (0x0001)
39#define PDDR (0x0003)
40#define PADDR (0x0040)
41#define PBDDR (0x0041)
42#define PDDDR (0x0043)
43#define PEDR (0x0080)
44#define PEDDR (0x00c0)
45#define SYSCON1 (0x0100)
46#define SYSFLG1 (0x0140)
47#define MEMCFG1 (0x0180)
48#define MEMCFG2 (0x01c0)
49#define DRFPR (0x0200)
50#define INTSR1 (0x0240)
51#define INTMR1 (0x0280)
52#define LCDCON (0x02c0)
53#define TC1D (0x0300)
54#define TC2D (0x0340)
55#define RTCDR (0x0380)
56#define RTCMR (0x03c0)
57#define PMPCON (0x0400)
58#define CODR (0x0440)
59#define UARTDR1 (0x0480)
60#define UBRLCR1 (0x04c0)
61#define SYNCIO (0x0500)
62#define PALLSW (0x0540)
63#define PALMSW (0x0580)
64#define STFCLR (0x05c0)
65#define BLEOI (0x0600)
66#define MCEOI (0x0640)
67#define TEOI (0x0680)
68#define TC1EOI (0x06c0)
69#define TC2EOI (0x0700)
70#define RTCEOI (0x0740)
71#define UMSEOI (0x0780)
72#define COEOI (0x07c0)
73#define HALT (0x0800)
74#define STDBY (0x0840)
75
76#define FBADDR (0x1000)
77#define SYSCON2 (0x1100)
78#define SYSFLG2 (0x1140)
79#define INTSR2 (0x1240)
80#define INTMR2 (0x1280)
81#define UARTDR2 (0x1480)
82#define UBRLCR2 (0x14c0)
83#define SS2DR (0x1500)
84#define SRXEOF (0x1600)
85#define SS2POP (0x16c0)
86#define KBDEOI (0x1700)
87
88/* common bits: SYSCON1 / SYSCON2 */
89#define SYSCON_UARTEN (1 << 8)
90
91#define SYSCON1_KBDSCAN(x) ((x) & 15)
92#define SYSCON1_KBDSCANMASK (15)
93#define SYSCON1_TC1M (1 << 4)
94#define SYSCON1_TC1S (1 << 5)
95#define SYSCON1_TC2M (1 << 6)
96#define SYSCON1_TC2S (1 << 7)
97#define SYSCON1_UART1EN SYSCON_UARTEN
98#define SYSCON1_BZTOG (1 << 9)
99#define SYSCON1_BZMOD (1 << 10)
100#define SYSCON1_DBGEN (1 << 11)
101#define SYSCON1_LCDEN (1 << 12)
102#define SYSCON1_CDENTX (1 << 13)
103#define SYSCON1_CDENRX (1 << 14)
104#define SYSCON1_SIREN (1 << 15)
105#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
106#define SYSCON1_ADCKSEL_MASK (3 << 16)
107#define SYSCON1_EXCKEN (1 << 18)
108#define SYSCON1_WAKEDIS (1 << 19)
109#define SYSCON1_IRTXM (1 << 20)
110
111/* common bits: SYSFLG1 / SYSFLG2 */
112#define SYSFLG_UBUSY (1 << 11)
113#define SYSFLG_URXFE (1 << 22)
114#define SYSFLG_UTXFF (1 << 23)
115
116#define SYSFLG1_MCDR (1 << 0)
117#define SYSFLG1_DCDET (1 << 1)
118#define SYSFLG1_WUDR (1 << 2)
119#define SYSFLG1_WUON (1 << 3)
120#define SYSFLG1_CTS (1 << 8)
121#define SYSFLG1_DSR (1 << 9)
122#define SYSFLG1_DCD (1 << 10)
123#define SYSFLG1_UBUSY SYSFLG_UBUSY
124#define SYSFLG1_NBFLG (1 << 12)
125#define SYSFLG1_RSTFLG (1 << 13)
126#define SYSFLG1_PFFLG (1 << 14)
127#define SYSFLG1_CLDFLG (1 << 15)
128#define SYSFLG1_URXFE SYSFLG_URXFE
129#define SYSFLG1_UTXFF SYSFLG_UTXFF
130#define SYSFLG1_CRXFE (1 << 24)
131#define SYSFLG1_CTXFF (1 << 25)
132#define SYSFLG1_SSIBUSY (1 << 26)
133#define SYSFLG1_ID (1 << 29)
134
135#define SYSFLG2_SSRXOF (1 << 0)
136#define SYSFLG2_RESVAL (1 << 1)
137#define SYSFLG2_RESFRM (1 << 2)
138#define SYSFLG2_SS2RXFE (1 << 3)
139#define SYSFLG2_SS2TXFF (1 << 4)
140#define SYSFLG2_SS2TXUF (1 << 5)
141#define SYSFLG2_CKMODE (1 << 6)
142#define SYSFLG2_UBUSY SYSFLG_UBUSY
143#define SYSFLG2_URXFE SYSFLG_URXFE
144#define SYSFLG2_UTXFF SYSFLG_UTXFF
145
146#define LCDCON_GSEN (1 << 30)
147#define LCDCON_GSMD (1 << 31)
148
149#define SYSCON2_SERSEL (1 << 0)
150#define SYSCON2_KBD6 (1 << 1)
151#define SYSCON2_DRAMZ (1 << 2)
152#define SYSCON2_KBWEN (1 << 3)
153#define SYSCON2_SS2TXEN (1 << 4)
154#define SYSCON2_PCCARD1 (1 << 5)
155#define SYSCON2_PCCARD2 (1 << 6)
156#define SYSCON2_SS2RXEN (1 << 7)
157#define SYSCON2_UART2EN SYSCON_UARTEN
158#define SYSCON2_SS2MAEN (1 << 9)
159#define SYSCON2_OSTB (1 << 12)
160#define SYSCON2_CLKENSL (1 << 13)
161#define SYSCON2_BUZFREQ (1 << 14)
162
163/* common bits: UARTDR1 / UARTDR2 */
164#define UARTDR_FRMERR (1 << 8)
165#define UARTDR_PARERR (1 << 9)
166#define UARTDR_OVERR (1 << 10)
167
168/* common bits: UBRLCR1 / UBRLCR2 */
169#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
170#define UBRLCR_BREAK (1 << 12)
171#define UBRLCR_PRTEN (1 << 13)
172#define UBRLCR_EVENPRT (1 << 14)
173#define UBRLCR_XSTOP (1 << 15)
174#define UBRLCR_FIFOEN (1 << 16)
175#define UBRLCR_WRDLEN5 (0 << 17)
176#define UBRLCR_WRDLEN6 (1 << 17)
177#define UBRLCR_WRDLEN7 (2 << 17)
178#define UBRLCR_WRDLEN8 (3 << 17)
179#define UBRLCR_WRDLEN_MASK (3 << 17)
180
181#define SYNCIO_SMCKEN (1 << 13)
182#define SYNCIO_TXFRMEN (1 << 14)
183
184#endif /* __ASM_HARDWARE_CLPS7111_H */
diff --git a/arch/arm/include/asm/hardware/cs89712.h b/arch/arm/include/asm/hardware/cs89712.h
new file mode 100644
index 000000000000..f75626933e94
--- /dev/null
+++ b/arch/arm/include/asm/hardware/cs89712.h
@@ -0,0 +1,49 @@
1/*
2 * arch/arm/include/asm/hardware/cs89712.h
3 *
4 * This file contains the hardware definitions of the CS89712
5 * additional internal registers.
6 *
7 * Copyright (C) 2001 Thomas Gleixner autronix automation <gleixner@autronix.de>
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24#ifndef __ASM_HARDWARE_CS89712_H
25#define __ASM_HARDWARE_CS89712_H
26
27/*
28* CS89712 additional registers
29*/
30
31#define PCDR 0x0002 /* Port C Data register ---------------------------- */
32#define PCDDR 0x0042 /* Port C Data Direction register ------------------ */
33#define SDCONF 0x2300 /* SDRAM Configuration register ---------------------*/
34#define SDRFPR 0x2340 /* SDRAM Refresh period register --------------------*/
35
36#define SDCONF_ACTIVE (1 << 10)
37#define SDCONF_CLKCTL (1 << 9)
38#define SDCONF_WIDTH_4 (0 << 7)
39#define SDCONF_WIDTH_8 (1 << 7)
40#define SDCONF_WIDTH_16 (2 << 7)
41#define SDCONF_WIDTH_32 (3 << 7)
42#define SDCONF_SIZE_16 (0 << 5)
43#define SDCONF_SIZE_64 (1 << 5)
44#define SDCONF_SIZE_128 (2 << 5)
45#define SDCONF_SIZE_256 (3 << 5)
46#define SDCONF_CASLAT_2 (2)
47#define SDCONF_CASLAT_3 (3)
48
49#endif /* __ASM_HARDWARE_CS89712_H */
diff --git a/arch/arm/include/asm/hardware/debug-8250.S b/arch/arm/include/asm/hardware/debug-8250.S
new file mode 100644
index 000000000000..22c689255e6e
--- /dev/null
+++ b/arch/arm/include/asm/hardware/debug-8250.S
@@ -0,0 +1,29 @@
1/*
2 * arch/arm/include/asm/hardware/debug-8250.S
3 *
4 * Copyright (C) 1994-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/serial_reg.h>
11
12 .macro senduart,rd,rx
13 strb \rd, [\rx, #UART_TX << UART_SHIFT]
14 .endm
15
16 .macro busyuart,rd,rx
171002: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
18 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
19 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
20 bne 1002b
21 .endm
22
23 .macro waituart,rd,rx
24#ifdef FLOW_CONTROL
251001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
26 tst \rd, #UART_MSR_CTS
27 beq 1001b
28#endif
29 .endm
diff --git a/arch/arm/include/asm/hardware/debug-pl01x.S b/arch/arm/include/asm/hardware/debug-pl01x.S
new file mode 100644
index 000000000000..f9fd083eff63
--- /dev/null
+++ b/arch/arm/include/asm/hardware/debug-pl01x.S
@@ -0,0 +1,29 @@
1/* arch/arm/include/asm/hardware/debug-pl01x.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13#include <linux/amba/serial.h>
14
15 .macro senduart,rd,rx
16 strb \rd, [\rx, #UART01x_DR]
17 .endm
18
19 .macro waituart,rd,rx
201001: ldr \rd, [\rx, #UART01x_FR]
21 tst \rd, #UART01x_FR_TXFF
22 bne 1001b
23 .endm
24
25 .macro busyuart,rd,rx
261001: ldr \rd, [\rx, #UART01x_FR]
27 tst \rd, #UART01x_FR_BUSY
28 bne 1001b
29 .endm
diff --git a/arch/arm/include/asm/hardware/dec21285.h b/arch/arm/include/asm/hardware/dec21285.h
new file mode 100644
index 000000000000..7068a1c1e4e4
--- /dev/null
+++ b/arch/arm/include/asm/hardware/dec21285.h
@@ -0,0 +1,147 @@
1/*
2 * arch/arm/include/asm/hardware/dec21285.h
3 *
4 * Copyright (C) 1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * DC21285 registers
11 */
12#define DC21285_PCI_IACK 0x79000000
13#define DC21285_ARMCSR_BASE 0x42000000
14#define DC21285_PCI_TYPE_0_CONFIG 0x7b000000
15#define DC21285_PCI_TYPE_1_CONFIG 0x7a000000
16#define DC21285_OUTBOUND_WRITE_FLUSH 0x78000000
17#define DC21285_FLASH 0x41000000
18#define DC21285_PCI_IO 0x7c000000
19#define DC21285_PCI_MEM 0x80000000
20
21#ifndef __ASSEMBLY__
22#include <asm/hardware.h>
23#define DC21285_IO(x) ((volatile unsigned long *)(ARMCSR_BASE+(x)))
24#else
25#define DC21285_IO(x) (x)
26#endif
27
28#define CSR_PCICMD DC21285_IO(0x0004)
29#define CSR_CLASSREV DC21285_IO(0x0008)
30#define CSR_PCICACHELINESIZE DC21285_IO(0x000c)
31#define CSR_PCICSRBASE DC21285_IO(0x0010)
32#define CSR_PCICSRIOBASE DC21285_IO(0x0014)
33#define CSR_PCISDRAMBASE DC21285_IO(0x0018)
34#define CSR_PCIROMBASE DC21285_IO(0x0030)
35#define CSR_MBOX0 DC21285_IO(0x0050)
36#define CSR_MBOX1 DC21285_IO(0x0054)
37#define CSR_MBOX2 DC21285_IO(0x0058)
38#define CSR_MBOX3 DC21285_IO(0x005c)
39#define CSR_DOORBELL DC21285_IO(0x0060)
40#define CSR_DOORBELL_SETUP DC21285_IO(0x0064)
41#define CSR_ROMWRITEREG DC21285_IO(0x0068)
42#define CSR_CSRBASEMASK DC21285_IO(0x00f8)
43#define CSR_CSRBASEOFFSET DC21285_IO(0x00fc)
44#define CSR_SDRAMBASEMASK DC21285_IO(0x0100)
45#define CSR_SDRAMBASEOFFSET DC21285_IO(0x0104)
46#define CSR_ROMBASEMASK DC21285_IO(0x0108)
47#define CSR_SDRAMTIMING DC21285_IO(0x010c)
48#define CSR_SDRAMADDRSIZE0 DC21285_IO(0x0110)
49#define CSR_SDRAMADDRSIZE1 DC21285_IO(0x0114)
50#define CSR_SDRAMADDRSIZE2 DC21285_IO(0x0118)
51#define CSR_SDRAMADDRSIZE3 DC21285_IO(0x011c)
52#define CSR_I2O_INFREEHEAD DC21285_IO(0x0120)
53#define CSR_I2O_INPOSTTAIL DC21285_IO(0x0124)
54#define CSR_I2O_OUTPOSTHEAD DC21285_IO(0x0128)
55#define CSR_I2O_OUTFREETAIL DC21285_IO(0x012c)
56#define CSR_I2O_INFREECOUNT DC21285_IO(0x0130)
57#define CSR_I2O_OUTPOSTCOUNT DC21285_IO(0x0134)
58#define CSR_I2O_INPOSTCOUNT DC21285_IO(0x0138)
59#define CSR_SA110_CNTL DC21285_IO(0x013c)
60#define SA110_CNTL_INITCMPLETE (1 << 0)
61#define SA110_CNTL_ASSERTSERR (1 << 1)
62#define SA110_CNTL_RXSERR (1 << 3)
63#define SA110_CNTL_SA110DRAMPARITY (1 << 4)
64#define SA110_CNTL_PCISDRAMPARITY (1 << 5)
65#define SA110_CNTL_DMASDRAMPARITY (1 << 6)
66#define SA110_CNTL_DISCARDTIMER (1 << 8)
67#define SA110_CNTL_PCINRESET (1 << 9)
68#define SA110_CNTL_I2O_256 (0 << 10)
69#define SA110_CNTL_I20_512 (1 << 10)
70#define SA110_CNTL_I2O_1024 (2 << 10)
71#define SA110_CNTL_I2O_2048 (3 << 10)
72#define SA110_CNTL_I2O_4096 (4 << 10)
73#define SA110_CNTL_I2O_8192 (5 << 10)
74#define SA110_CNTL_I2O_16384 (6 << 10)
75#define SA110_CNTL_I2O_32768 (7 << 10)
76#define SA110_CNTL_WATCHDOG (1 << 13)
77#define SA110_CNTL_ROMWIDTH_UNDEF (0 << 14)
78#define SA110_CNTL_ROMWIDTH_16 (1 << 14)
79#define SA110_CNTL_ROMWIDTH_32 (2 << 14)
80#define SA110_CNTL_ROMWIDTH_8 (3 << 14)
81#define SA110_CNTL_ROMACCESSTIME(x) ((x)<<16)
82#define SA110_CNTL_ROMBURSTTIME(x) ((x)<<20)
83#define SA110_CNTL_ROMTRISTATETIME(x) ((x)<<24)
84#define SA110_CNTL_XCSDIR(x) ((x)<<28)
85#define SA110_CNTL_PCICFN (1 << 31)
86
87/*
88 * footbridge_cfn_mode() is used when we want
89 * to check whether we are the central function
90 */
91#define __footbridge_cfn_mode() (*CSR_SA110_CNTL & SA110_CNTL_PCICFN)
92#if defined(CONFIG_FOOTBRIDGE_HOST) && defined(CONFIG_FOOTBRIDGE_ADDIN)
93#define footbridge_cfn_mode() __footbridge_cfn_mode()
94#elif defined(CONFIG_FOOTBRIDGE_HOST)
95#define footbridge_cfn_mode() (1)
96#else
97#define footbridge_cfn_mode() (0)
98#endif
99
100#define CSR_PCIADDR_EXTN DC21285_IO(0x0140)
101#define CSR_PREFETCHMEMRANGE DC21285_IO(0x0144)
102#define CSR_XBUS_CYCLE DC21285_IO(0x0148)
103#define CSR_XBUS_IOSTROBE DC21285_IO(0x014c)
104#define CSR_DOORBELL_PCI DC21285_IO(0x0150)
105#define CSR_DOORBELL_SA110 DC21285_IO(0x0154)
106#define CSR_UARTDR DC21285_IO(0x0160)
107#define CSR_RXSTAT DC21285_IO(0x0164)
108#define CSR_H_UBRLCR DC21285_IO(0x0168)
109#define CSR_M_UBRLCR DC21285_IO(0x016c)
110#define CSR_L_UBRLCR DC21285_IO(0x0170)
111#define CSR_UARTCON DC21285_IO(0x0174)
112#define CSR_UARTFLG DC21285_IO(0x0178)
113#define CSR_IRQ_STATUS DC21285_IO(0x0180)
114#define CSR_IRQ_RAWSTATUS DC21285_IO(0x0184)
115#define CSR_IRQ_ENABLE DC21285_IO(0x0188)
116#define CSR_IRQ_DISABLE DC21285_IO(0x018c)
117#define CSR_IRQ_SOFT DC21285_IO(0x0190)
118#define CSR_FIQ_STATUS DC21285_IO(0x0280)
119#define CSR_FIQ_RAWSTATUS DC21285_IO(0x0284)
120#define CSR_FIQ_ENABLE DC21285_IO(0x0288)
121#define CSR_FIQ_DISABLE DC21285_IO(0x028c)
122#define CSR_FIQ_SOFT DC21285_IO(0x0290)
123#define CSR_TIMER1_LOAD DC21285_IO(0x0300)
124#define CSR_TIMER1_VALUE DC21285_IO(0x0304)
125#define CSR_TIMER1_CNTL DC21285_IO(0x0308)
126#define CSR_TIMER1_CLR DC21285_IO(0x030c)
127#define CSR_TIMER2_LOAD DC21285_IO(0x0320)
128#define CSR_TIMER2_VALUE DC21285_IO(0x0324)
129#define CSR_TIMER2_CNTL DC21285_IO(0x0328)
130#define CSR_TIMER2_CLR DC21285_IO(0x032c)
131#define CSR_TIMER3_LOAD DC21285_IO(0x0340)
132#define CSR_TIMER3_VALUE DC21285_IO(0x0344)
133#define CSR_TIMER3_CNTL DC21285_IO(0x0348)
134#define CSR_TIMER3_CLR DC21285_IO(0x034c)
135#define CSR_TIMER4_LOAD DC21285_IO(0x0360)
136#define CSR_TIMER4_VALUE DC21285_IO(0x0364)
137#define CSR_TIMER4_CNTL DC21285_IO(0x0368)
138#define CSR_TIMER4_CLR DC21285_IO(0x036c)
139
140#define TIMER_CNTL_ENABLE (1 << 7)
141#define TIMER_CNTL_AUTORELOAD (1 << 6)
142#define TIMER_CNTL_DIV1 (0)
143#define TIMER_CNTL_DIV16 (1 << 2)
144#define TIMER_CNTL_DIV256 (2 << 2)
145#define TIMER_CNTL_CNTEXT (3 << 2)
146
147
diff --git a/arch/arm/include/asm/hardware/entry-macro-iomd.S b/arch/arm/include/asm/hardware/entry-macro-iomd.S
new file mode 100644
index 000000000000..e0af4983723f
--- /dev/null
+++ b/arch/arm/include/asm/hardware/entry-macro-iomd.S
@@ -0,0 +1,139 @@
1/*
2 * arch/arm/include/asm/hardware/entry-macro-iomd.S
3 *
4 * Low-level IRQ helper macros for IOC/IOMD based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11/* IOC / IOMD based hardware */
12#include <asm/hardware/iomd.h>
13
14 .macro disable_fiq
15 mov r12, #ioc_base_high
16 .if ioc_base_low
17 orr r12, r12, #ioc_base_low
18 .endif
19 strb r12, [r12, #0x38] @ Disable FIQ register
20 .endm
21
22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
23 ldrb \irqstat, [\base, #IOMD_IRQREQB] @ get high priority first
24 ldr \tmp, =irq_prio_h
25 teq \irqstat, #0
26#ifdef IOMD_BASE
27 ldreqb \irqstat, [\base, #IOMD_DMAREQ] @ get dma
28 addeq \tmp, \tmp, #256 @ irq_prio_h table size
29 teqeq \irqstat, #0
30 bne 2406f
31#endif
32 ldreqb \irqstat, [\base, #IOMD_IRQREQA] @ get low priority
33 addeq \tmp, \tmp, #256 @ irq_prio_d table size
34 teqeq \irqstat, #0
35#ifdef IOMD_IRQREQC
36 ldreqb \irqstat, [\base, #IOMD_IRQREQC]
37 addeq \tmp, \tmp, #256 @ irq_prio_l table size
38 teqeq \irqstat, #0
39#endif
40#ifdef IOMD_IRQREQD
41 ldreqb \irqstat, [\base, #IOMD_IRQREQD]
42 addeq \tmp, \tmp, #256 @ irq_prio_lc table size
43 teqeq \irqstat, #0
44#endif
452406: ldrneb \irqnr, [\tmp, \irqstat] @ get IRQ number
46 .endm
47
48/*
49 * Interrupt table (incorporates priority). Please note that we
50 * rely on the order of these tables (see above code).
51 */
52 .align 5
53irq_prio_h: .byte 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10
54 .byte 12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10
55 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
56 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
57 .byte 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10
58 .byte 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10
59 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
60 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
61 .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
62 .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
63 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
64 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
65 .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
66 .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
67 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
68 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
69#ifdef IOMD_BASE
70irq_prio_d: .byte 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
71 .byte 20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
72 .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
73 .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
74 .byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
75 .byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
76 .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
77 .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
78 .byte 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
79 .byte 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
80 .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
81 .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
82 .byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
83 .byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
84 .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
85 .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
86#endif
87irq_prio_l: .byte 0, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3
88 .byte 4, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3
89 .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
90 .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
91 .byte 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3
92 .byte 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3
93 .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
94 .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
95 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
96 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
97 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
98 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
99 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
100 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
101 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
102 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
103#ifdef IOMD_IRQREQC
104irq_prio_lc: .byte 24,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27
105 .byte 28,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27
106 .byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
107 .byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
108 .byte 30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27
109 .byte 30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27
110 .byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
111 .byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
112 .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
113 .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
114 .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
115 .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
116 .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
117 .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
118 .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
119 .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
120#endif
121#ifdef IOMD_IRQREQD
122irq_prio_ld: .byte 40,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43
123 .byte 44,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43
124 .byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
125 .byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
126 .byte 46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43
127 .byte 46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43
128 .byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
129 .byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
130 .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
131 .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
132 .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
133 .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
134 .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
135 .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
136 .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
137 .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
138#endif
139
diff --git a/arch/arm/include/asm/hardware/ep7211.h b/arch/arm/include/asm/hardware/ep7211.h
new file mode 100644
index 000000000000..654d5f625c49
--- /dev/null
+++ b/arch/arm/include/asm/hardware/ep7211.h
@@ -0,0 +1,40 @@
1/*
2 * arch/arm/include/asm/hardware/ep7211.h
3 *
4 * This file contains the hardware definitions of the EP7211 internal
5 * registers.
6 *
7 * Copyright (C) 2001 Blue Mug, Inc. All Rights Reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef __ASM_HARDWARE_EP7211_H
24#define __ASM_HARDWARE_EP7211_H
25
26#include <asm/hardware/clps7111.h>
27
28/*
29 * define EP7211_BASE to be the base address of the region
30 * you want to access.
31 */
32
33#define EP7211_PHYS_BASE (0x80000000)
34
35/*
36 * XXX miket@bluemug.com: need to introduce EP7211 registers (those not
37 * present in 7212) here.
38 */
39
40#endif /* __ASM_HARDWARE_EP7211_H */
diff --git a/arch/arm/include/asm/hardware/ep7212.h b/arch/arm/include/asm/hardware/ep7212.h
new file mode 100644
index 000000000000..3b43bbeaf1db
--- /dev/null
+++ b/arch/arm/include/asm/hardware/ep7212.h
@@ -0,0 +1,83 @@
1/*
2 * arch/arm/include/asm/hardware/ep7212.h
3 *
4 * This file contains the hardware definitions of the EP7212 internal
5 * registers.
6 *
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef __ASM_HARDWARE_EP7212_H
24#define __ASM_HARDWARE_EP7212_H
25
26/*
27 * define EP7212_BASE to be the base address of the region
28 * you want to access.
29 */
30
31#define EP7212_PHYS_BASE (0x80000000)
32
33#ifndef __ASSEMBLY__
34#define ep_readl(off) __raw_readl(EP7212_BASE + (off))
35#define ep_writel(val,off) __raw_writel(val, EP7212_BASE + (off))
36#endif
37
38/*
39 * These registers are specific to the EP7212 only
40 */
41#define DAIR 0x2000
42#define DAIR0 0x2040
43#define DAIDR1 0x2080
44#define DAIDR2 0x20c0
45#define DAISR 0x2100
46#define SYSCON3 0x2200
47#define INTSR3 0x2240
48#define INTMR3 0x2280
49#define LEDFLSH 0x22c0
50
51#define DAIR_DAIEN (1 << 16)
52#define DAIR_ECS (1 << 17)
53#define DAIR_LCTM (1 << 19)
54#define DAIR_LCRM (1 << 20)
55#define DAIR_RCTM (1 << 21)
56#define DAIR_RCRM (1 << 22)
57#define DAIR_LBM (1 << 23)
58
59#define DAIDR2_FIFOEN (1 << 15)
60#define DAIDR2_FIFOLEFT (0x0d << 16)
61#define DAIDR2_FIFORIGHT (0x11 << 16)
62
63#define DAISR_RCTS (1 << 0)
64#define DAISR_RCRS (1 << 1)
65#define DAISR_LCTS (1 << 2)
66#define DAISR_LCRS (1 << 3)
67#define DAISR_RCTU (1 << 4)
68#define DAISR_RCRO (1 << 5)
69#define DAISR_LCTU (1 << 6)
70#define DAISR_LCRO (1 << 7)
71#define DAISR_RCNF (1 << 8)
72#define DAISR_RCNE (1 << 9)
73#define DAISR_LCNF (1 << 10)
74#define DAISR_LCNE (1 << 11)
75#define DAISR_FIFO (1 << 12)
76
77#define SYSCON3_ADCCON (1 << 0)
78#define SYSCON3_DAISEL (1 << 3)
79#define SYSCON3_ADCCKNSEN (1 << 4)
80#define SYSCON3_FASTWAKE (1 << 8)
81#define SYSCON3_DAIEN (1 << 9)
82
83#endif /* __ASM_HARDWARE_EP7212_H */
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
new file mode 100644
index 000000000000..4924914af188
--- /dev/null
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -0,0 +1,42 @@
1/*
2 * arch/arm/include/asm/hardware/gic.h
3 *
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_ARM_HARDWARE_GIC_H
11#define __ASM_ARM_HARDWARE_GIC_H
12
13#include <linux/compiler.h>
14
15#define GIC_CPU_CTRL 0x00
16#define GIC_CPU_PRIMASK 0x04
17#define GIC_CPU_BINPOINT 0x08
18#define GIC_CPU_INTACK 0x0c
19#define GIC_CPU_EOI 0x10
20#define GIC_CPU_RUNNINGPRI 0x14
21#define GIC_CPU_HIGHPRI 0x18
22
23#define GIC_DIST_CTRL 0x000
24#define GIC_DIST_CTR 0x004
25#define GIC_DIST_ENABLE_SET 0x100
26#define GIC_DIST_ENABLE_CLEAR 0x180
27#define GIC_DIST_PENDING_SET 0x200
28#define GIC_DIST_PENDING_CLEAR 0x280
29#define GIC_DIST_ACTIVE_BIT 0x300
30#define GIC_DIST_PRI 0x400
31#define GIC_DIST_TARGET 0x800
32#define GIC_DIST_CONFIG 0xc00
33#define GIC_DIST_SOFTINT 0xf00
34
35#ifndef __ASSEMBLY__
36void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start);
37void gic_cpu_init(unsigned int gic_nr, void __iomem *base);
38void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
39void gic_raise_softirq(cpumask_t cpumask, unsigned int irq);
40#endif
41
42#endif
diff --git a/arch/arm/include/asm/hardware/icst307.h b/arch/arm/include/asm/hardware/icst307.h
new file mode 100644
index 000000000000..554f128a1046
--- /dev/null
+++ b/arch/arm/include/asm/hardware/icst307.h
@@ -0,0 +1,38 @@
1/*
2 * arch/arm/include/asm/hardware/icst307.h
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Support functions for calculating clocks/divisors for the ICS307
11 * clock generators. See http://www.icst.com/ for more information
12 * on these devices.
13 *
14 * This file is similar to the icst525.h file
15 */
16#ifndef ASMARM_HARDWARE_ICST307_H
17#define ASMARM_HARDWARE_ICST307_H
18
19struct icst307_params {
20 unsigned long ref;
21 unsigned long vco_max; /* inclusive */
22 unsigned short vd_min; /* inclusive */
23 unsigned short vd_max; /* inclusive */
24 unsigned char rd_min; /* inclusive */
25 unsigned char rd_max; /* inclusive */
26};
27
28struct icst307_vco {
29 unsigned short v;
30 unsigned char r;
31 unsigned char s;
32};
33
34unsigned long icst307_khz(const struct icst307_params *p, struct icst307_vco vco);
35struct icst307_vco icst307_khz_to_vco(const struct icst307_params *p, unsigned long freq);
36struct icst307_vco icst307_ps_to_vco(const struct icst307_params *p, unsigned long period);
37
38#endif
diff --git a/arch/arm/include/asm/hardware/icst525.h b/arch/arm/include/asm/hardware/icst525.h
new file mode 100644
index 000000000000..58f0dc43e2ed
--- /dev/null
+++ b/arch/arm/include/asm/hardware/icst525.h
@@ -0,0 +1,36 @@
1/*
2 * arch/arm/include/asm/hardware/icst525.h
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Support functions for calculating clocks/divisors for the ICST525
11 * clock generators. See http://www.icst.com/ for more information
12 * on these devices.
13 */
14#ifndef ASMARM_HARDWARE_ICST525_H
15#define ASMARM_HARDWARE_ICST525_H
16
17struct icst525_params {
18 unsigned long ref;
19 unsigned long vco_max; /* inclusive */
20 unsigned short vd_min; /* inclusive */
21 unsigned short vd_max; /* inclusive */
22 unsigned char rd_min; /* inclusive */
23 unsigned char rd_max; /* inclusive */
24};
25
26struct icst525_vco {
27 unsigned short v;
28 unsigned char r;
29 unsigned char s;
30};
31
32unsigned long icst525_khz(const struct icst525_params *p, struct icst525_vco vco);
33struct icst525_vco icst525_khz_to_vco(const struct icst525_params *p, unsigned long freq);
34struct icst525_vco icst525_ps_to_vco(const struct icst525_params *p, unsigned long period);
35
36#endif
diff --git a/arch/arm/include/asm/hardware/ioc.h b/arch/arm/include/asm/hardware/ioc.h
new file mode 100644
index 000000000000..1f6b8013becb
--- /dev/null
+++ b/arch/arm/include/asm/hardware/ioc.h
@@ -0,0 +1,72 @@
1/*
2 * arch/arm/include/asm/hardware/ioc.h
3 *
4 * Copyright (C) Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Use these macros to read/write the IOC. All it does is perform the actual
11 * read/write.
12 */
13#ifndef __ASMARM_HARDWARE_IOC_H
14#define __ASMARM_HARDWARE_IOC_H
15
16#ifndef __ASSEMBLY__
17
18/*
19 * We use __raw_base variants here so that we give the compiler the
20 * chance to keep IOC_BASE in a register.
21 */
22#define ioc_readb(off) __raw_readb(IOC_BASE + (off))
23#define ioc_writeb(val,off) __raw_writeb(val, IOC_BASE + (off))
24
25#endif
26
27#define IOC_CONTROL (0x00)
28#define IOC_KARTTX (0x04)
29#define IOC_KARTRX (0x04)
30
31#define IOC_IRQSTATA (0x10)
32#define IOC_IRQREQA (0x14)
33#define IOC_IRQCLRA (0x14)
34#define IOC_IRQMASKA (0x18)
35
36#define IOC_IRQSTATB (0x20)
37#define IOC_IRQREQB (0x24)
38#define IOC_IRQMASKB (0x28)
39
40#define IOC_FIQSTAT (0x30)
41#define IOC_FIQREQ (0x34)
42#define IOC_FIQMASK (0x38)
43
44#define IOC_T0CNTL (0x40)
45#define IOC_T0LTCHL (0x40)
46#define IOC_T0CNTH (0x44)
47#define IOC_T0LTCHH (0x44)
48#define IOC_T0GO (0x48)
49#define IOC_T0LATCH (0x4c)
50
51#define IOC_T1CNTL (0x50)
52#define IOC_T1LTCHL (0x50)
53#define IOC_T1CNTH (0x54)
54#define IOC_T1LTCHH (0x54)
55#define IOC_T1GO (0x58)
56#define IOC_T1LATCH (0x5c)
57
58#define IOC_T2CNTL (0x60)
59#define IOC_T2LTCHL (0x60)
60#define IOC_T2CNTH (0x64)
61#define IOC_T2LTCHH (0x64)
62#define IOC_T2GO (0x68)
63#define IOC_T2LATCH (0x6c)
64
65#define IOC_T3CNTL (0x70)
66#define IOC_T3LTCHL (0x70)
67#define IOC_T3CNTH (0x74)
68#define IOC_T3LTCHH (0x74)
69#define IOC_T3GO (0x78)
70#define IOC_T3LATCH (0x7c)
71
72#endif
diff --git a/arch/arm/include/asm/hardware/iomd.h b/arch/arm/include/asm/hardware/iomd.h
new file mode 100644
index 000000000000..9c5afbd71a69
--- /dev/null
+++ b/arch/arm/include/asm/hardware/iomd.h
@@ -0,0 +1,226 @@
1/*
2 * arch/arm/include/asm/hardware/iomd.h
3 *
4 * Copyright (C) 1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This file contains information out the IOMD ASIC used in the
11 * Acorn RiscPC and subsequently integrated into the CLPS7500 chips.
12 */
13#ifndef __ASMARM_HARDWARE_IOMD_H
14#define __ASMARM_HARDWARE_IOMD_H
15
16
17#ifndef __ASSEMBLY__
18
19/*
20 * We use __raw_base variants here so that we give the compiler the
21 * chance to keep IOC_BASE in a register.
22 */
23#define iomd_readb(off) __raw_readb(IOMD_BASE + (off))
24#define iomd_readl(off) __raw_readl(IOMD_BASE + (off))
25#define iomd_writeb(val,off) __raw_writeb(val, IOMD_BASE + (off))
26#define iomd_writel(val,off) __raw_writel(val, IOMD_BASE + (off))
27
28#endif
29
30#define IOMD_CONTROL (0x000)
31#define IOMD_KARTTX (0x004)
32#define IOMD_KARTRX (0x004)
33#define IOMD_KCTRL (0x008)
34
35#ifdef CONFIG_ARCH_CLPS7500
36#define IOMD_IOLINES (0x00C)
37#endif
38
39#define IOMD_IRQSTATA (0x010)
40#define IOMD_IRQREQA (0x014)
41#define IOMD_IRQCLRA (0x014)
42#define IOMD_IRQMASKA (0x018)
43
44#ifdef CONFIG_ARCH_CLPS7500
45#define IOMD_SUSMODE (0x01C)
46#endif
47
48#define IOMD_IRQSTATB (0x020)
49#define IOMD_IRQREQB (0x024)
50#define IOMD_IRQMASKB (0x028)
51
52#define IOMD_FIQSTAT (0x030)
53#define IOMD_FIQREQ (0x034)
54#define IOMD_FIQMASK (0x038)
55
56#ifdef CONFIG_ARCH_CLPS7500
57#define IOMD_CLKCTL (0x03C)
58#endif
59
60#define IOMD_T0CNTL (0x040)
61#define IOMD_T0LTCHL (0x040)
62#define IOMD_T0CNTH (0x044)
63#define IOMD_T0LTCHH (0x044)
64#define IOMD_T0GO (0x048)
65#define IOMD_T0LATCH (0x04c)
66
67#define IOMD_T1CNTL (0x050)
68#define IOMD_T1LTCHL (0x050)
69#define IOMD_T1CNTH (0x054)
70#define IOMD_T1LTCHH (0x054)
71#define IOMD_T1GO (0x058)
72#define IOMD_T1LATCH (0x05c)
73
74#ifdef CONFIG_ARCH_CLPS7500
75#define IOMD_IRQSTATC (0x060)
76#define IOMD_IRQREQC (0x064)
77#define IOMD_IRQMASKC (0x068)
78
79#define IOMD_VIDMUX (0x06c)
80
81#define IOMD_IRQSTATD (0x070)
82#define IOMD_IRQREQD (0x074)
83#define IOMD_IRQMASKD (0x078)
84#endif
85
86#define IOMD_ROMCR0 (0x080)
87#define IOMD_ROMCR1 (0x084)
88#ifdef CONFIG_ARCH_RPC
89#define IOMD_DRAMCR (0x088)
90#endif
91#define IOMD_REFCR (0x08C)
92
93#define IOMD_FSIZE (0x090)
94#define IOMD_ID0 (0x094)
95#define IOMD_ID1 (0x098)
96#define IOMD_VERSION (0x09C)
97
98#ifdef CONFIG_ARCH_RPC
99#define IOMD_MOUSEX (0x0A0)
100#define IOMD_MOUSEY (0x0A4)
101#endif
102
103#ifdef CONFIG_ARCH_CLPS7500
104#define IOMD_MSEDAT (0x0A8)
105#define IOMD_MSECTL (0x0Ac)
106#endif
107
108#ifdef CONFIG_ARCH_RPC
109#define IOMD_DMATCR (0x0C0)
110#endif
111#define IOMD_IOTCR (0x0C4)
112#define IOMD_ECTCR (0x0C8)
113#ifdef CONFIG_ARCH_RPC
114#define IOMD_DMAEXT (0x0CC)
115#endif
116#ifdef CONFIG_ARCH_CLPS7500
117#define IOMD_ASTCR (0x0CC)
118#define IOMD_DRAMCR (0x0D0)
119#define IOMD_SELFREF (0x0D4)
120#define IOMD_ATODICR (0x0E0)
121#define IOMD_ATODSR (0x0E4)
122#define IOMD_ATODCC (0x0E8)
123#define IOMD_ATODCNT1 (0x0EC)
124#define IOMD_ATODCNT2 (0x0F0)
125#define IOMD_ATODCNT3 (0x0F4)
126#define IOMD_ATODCNT4 (0x0F8)
127#endif
128
129#ifdef CONFIG_ARCH_RPC
130#define DMA_EXT_IO0 1
131#define DMA_EXT_IO1 2
132#define DMA_EXT_IO2 4
133#define DMA_EXT_IO3 8
134
135#define IOMD_IO0CURA (0x100)
136#define IOMD_IO0ENDA (0x104)
137#define IOMD_IO0CURB (0x108)
138#define IOMD_IO0ENDB (0x10C)
139#define IOMD_IO0CR (0x110)
140#define IOMD_IO0ST (0x114)
141
142#define IOMD_IO1CURA (0x120)
143#define IOMD_IO1ENDA (0x124)
144#define IOMD_IO1CURB (0x128)
145#define IOMD_IO1ENDB (0x12C)
146#define IOMD_IO1CR (0x130)
147#define IOMD_IO1ST (0x134)
148
149#define IOMD_IO2CURA (0x140)
150#define IOMD_IO2ENDA (0x144)
151#define IOMD_IO2CURB (0x148)
152#define IOMD_IO2ENDB (0x14C)
153#define IOMD_IO2CR (0x150)
154#define IOMD_IO2ST (0x154)
155
156#define IOMD_IO3CURA (0x160)
157#define IOMD_IO3ENDA (0x164)
158#define IOMD_IO3CURB (0x168)
159#define IOMD_IO3ENDB (0x16C)
160#define IOMD_IO3CR (0x170)
161#define IOMD_IO3ST (0x174)
162#endif
163
164#define IOMD_SD0CURA (0x180)
165#define IOMD_SD0ENDA (0x184)
166#define IOMD_SD0CURB (0x188)
167#define IOMD_SD0ENDB (0x18C)
168#define IOMD_SD0CR (0x190)
169#define IOMD_SD0ST (0x194)
170
171#ifdef CONFIG_ARCH_RPC
172#define IOMD_SD1CURA (0x1A0)
173#define IOMD_SD1ENDA (0x1A4)
174#define IOMD_SD1CURB (0x1A8)
175#define IOMD_SD1ENDB (0x1AC)
176#define IOMD_SD1CR (0x1B0)
177#define IOMD_SD1ST (0x1B4)
178#endif
179
180#define IOMD_CURSCUR (0x1C0)
181#define IOMD_CURSINIT (0x1C4)
182
183#define IOMD_VIDCUR (0x1D0)
184#define IOMD_VIDEND (0x1D4)
185#define IOMD_VIDSTART (0x1D8)
186#define IOMD_VIDINIT (0x1DC)
187#define IOMD_VIDCR (0x1E0)
188
189#define IOMD_DMASTAT (0x1F0)
190#define IOMD_DMAREQ (0x1F4)
191#define IOMD_DMAMASK (0x1F8)
192
193#define DMA_END_S (1 << 31)
194#define DMA_END_L (1 << 30)
195
196#define DMA_CR_C 0x80
197#define DMA_CR_D 0x40
198#define DMA_CR_E 0x20
199
200#define DMA_ST_OFL 4
201#define DMA_ST_INT 2
202#define DMA_ST_AB 1
203
204/*
205 * DMA (MEMC) compatibility
206 */
207#define HALF_SAM vram_half_sam
208#define VDMA_ALIGNMENT (HALF_SAM * 2)
209#define VDMA_XFERSIZE (HALF_SAM)
210#define VDMA_INIT IOMD_VIDINIT
211#define VDMA_START IOMD_VIDSTART
212#define VDMA_END IOMD_VIDEND
213
214#ifndef __ASSEMBLY__
215extern unsigned int vram_half_sam;
216#define video_set_dma(start,end,offset) \
217do { \
218 outl (SCREEN_START + start, VDMA_START); \
219 outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END); \
220 if (offset >= end - VDMA_XFERSIZE) \
221 offset |= 0x40000000; \
222 outl (SCREEN_START + offset, VDMA_INIT); \
223} while (0)
224#endif
225
226#endif
diff --git a/arch/arm/include/asm/hardware/iop3xx-adma.h b/arch/arm/include/asm/hardware/iop3xx-adma.h
new file mode 100644
index 000000000000..af64676650a2
--- /dev/null
+++ b/arch/arm/include/asm/hardware/iop3xx-adma.h
@@ -0,0 +1,888 @@
1/*
2 * Copyright © 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 */
18#ifndef _ADMA_H
19#define _ADMA_H
20#include <linux/types.h>
21#include <linux/io.h>
22#include <asm/hardware.h>
23#include <asm/hardware/iop_adma.h>
24
25/* Memory copy units */
26#define DMA_CCR(chan) (chan->mmr_base + 0x0)
27#define DMA_CSR(chan) (chan->mmr_base + 0x4)
28#define DMA_DAR(chan) (chan->mmr_base + 0xc)
29#define DMA_NDAR(chan) (chan->mmr_base + 0x10)
30#define DMA_PADR(chan) (chan->mmr_base + 0x14)
31#define DMA_PUADR(chan) (chan->mmr_base + 0x18)
32#define DMA_LADR(chan) (chan->mmr_base + 0x1c)
33#define DMA_BCR(chan) (chan->mmr_base + 0x20)
34#define DMA_DCR(chan) (chan->mmr_base + 0x24)
35
36/* Application accelerator unit */
37#define AAU_ACR(chan) (chan->mmr_base + 0x0)
38#define AAU_ASR(chan) (chan->mmr_base + 0x4)
39#define AAU_ADAR(chan) (chan->mmr_base + 0x8)
40#define AAU_ANDAR(chan) (chan->mmr_base + 0xc)
41#define AAU_SAR(src, chan) (chan->mmr_base + (0x10 + ((src) << 2)))
42#define AAU_DAR(chan) (chan->mmr_base + 0x20)
43#define AAU_ABCR(chan) (chan->mmr_base + 0x24)
44#define AAU_ADCR(chan) (chan->mmr_base + 0x28)
45#define AAU_SAR_EDCR(src_edc) (chan->mmr_base + (0x02c + ((src_edc-4) << 2)))
46#define AAU_EDCR0_IDX 8
47#define AAU_EDCR1_IDX 17
48#define AAU_EDCR2_IDX 26
49
50#define DMA0_ID 0
51#define DMA1_ID 1
52#define AAU_ID 2
53
54struct iop3xx_aau_desc_ctrl {
55 unsigned int int_en:1;
56 unsigned int blk1_cmd_ctrl:3;
57 unsigned int blk2_cmd_ctrl:3;
58 unsigned int blk3_cmd_ctrl:3;
59 unsigned int blk4_cmd_ctrl:3;
60 unsigned int blk5_cmd_ctrl:3;
61 unsigned int blk6_cmd_ctrl:3;
62 unsigned int blk7_cmd_ctrl:3;
63 unsigned int blk8_cmd_ctrl:3;
64 unsigned int blk_ctrl:2;
65 unsigned int dual_xor_en:1;
66 unsigned int tx_complete:1;
67 unsigned int zero_result_err:1;
68 unsigned int zero_result_en:1;
69 unsigned int dest_write_en:1;
70};
71
72struct iop3xx_aau_e_desc_ctrl {
73 unsigned int reserved:1;
74 unsigned int blk1_cmd_ctrl:3;
75 unsigned int blk2_cmd_ctrl:3;
76 unsigned int blk3_cmd_ctrl:3;
77 unsigned int blk4_cmd_ctrl:3;
78 unsigned int blk5_cmd_ctrl:3;
79 unsigned int blk6_cmd_ctrl:3;
80 unsigned int blk7_cmd_ctrl:3;
81 unsigned int blk8_cmd_ctrl:3;
82 unsigned int reserved2:7;
83};
84
85struct iop3xx_dma_desc_ctrl {
86 unsigned int pci_transaction:4;
87 unsigned int int_en:1;
88 unsigned int dac_cycle_en:1;
89 unsigned int mem_to_mem_en:1;
90 unsigned int crc_data_tx_en:1;
91 unsigned int crc_gen_en:1;
92 unsigned int crc_seed_dis:1;
93 unsigned int reserved:21;
94 unsigned int crc_tx_complete:1;
95};
96
97struct iop3xx_desc_dma {
98 u32 next_desc;
99 union {
100 u32 pci_src_addr;
101 u32 pci_dest_addr;
102 u32 src_addr;
103 };
104 union {
105 u32 upper_pci_src_addr;
106 u32 upper_pci_dest_addr;
107 };
108 union {
109 u32 local_pci_src_addr;
110 u32 local_pci_dest_addr;
111 u32 dest_addr;
112 };
113 u32 byte_count;
114 union {
115 u32 desc_ctrl;
116 struct iop3xx_dma_desc_ctrl desc_ctrl_field;
117 };
118 u32 crc_addr;
119};
120
121struct iop3xx_desc_aau {
122 u32 next_desc;
123 u32 src[4];
124 u32 dest_addr;
125 u32 byte_count;
126 union {
127 u32 desc_ctrl;
128 struct iop3xx_aau_desc_ctrl desc_ctrl_field;
129 };
130 union {
131 u32 src_addr;
132 u32 e_desc_ctrl;
133 struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field;
134 } src_edc[31];
135};
136
137struct iop3xx_aau_gfmr {
138 unsigned int gfmr1:8;
139 unsigned int gfmr2:8;
140 unsigned int gfmr3:8;
141 unsigned int gfmr4:8;
142};
143
144struct iop3xx_desc_pq_xor {
145 u32 next_desc;
146 u32 src[3];
147 union {
148 u32 data_mult1;
149 struct iop3xx_aau_gfmr data_mult1_field;
150 };
151 u32 dest_addr;
152 u32 byte_count;
153 union {
154 u32 desc_ctrl;
155 struct iop3xx_aau_desc_ctrl desc_ctrl_field;
156 };
157 union {
158 u32 src_addr;
159 u32 e_desc_ctrl;
160 struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field;
161 u32 data_multiplier;
162 struct iop3xx_aau_gfmr data_mult_field;
163 u32 reserved;
164 } src_edc_gfmr[19];
165};
166
167struct iop3xx_desc_dual_xor {
168 u32 next_desc;
169 u32 src0_addr;
170 u32 src1_addr;
171 u32 h_src_addr;
172 u32 d_src_addr;
173 u32 h_dest_addr;
174 u32 byte_count;
175 union {
176 u32 desc_ctrl;
177 struct iop3xx_aau_desc_ctrl desc_ctrl_field;
178 };
179 u32 d_dest_addr;
180};
181
182union iop3xx_desc {
183 struct iop3xx_desc_aau *aau;
184 struct iop3xx_desc_dma *dma;
185 struct iop3xx_desc_pq_xor *pq_xor;
186 struct iop3xx_desc_dual_xor *dual_xor;
187 void *ptr;
188};
189
190static inline int iop_adma_get_max_xor(void)
191{
192 return 32;
193}
194
195static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
196{
197 int id = chan->device->id;
198
199 switch (id) {
200 case DMA0_ID:
201 case DMA1_ID:
202 return __raw_readl(DMA_DAR(chan));
203 case AAU_ID:
204 return __raw_readl(AAU_ADAR(chan));
205 default:
206 BUG();
207 }
208 return 0;
209}
210
211static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,
212 u32 next_desc_addr)
213{
214 int id = chan->device->id;
215
216 switch (id) {
217 case DMA0_ID:
218 case DMA1_ID:
219 __raw_writel(next_desc_addr, DMA_NDAR(chan));
220 break;
221 case AAU_ID:
222 __raw_writel(next_desc_addr, AAU_ANDAR(chan));
223 break;
224 }
225
226}
227
228#define IOP_ADMA_STATUS_BUSY (1 << 10)
229#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT (1024)
230#define IOP_ADMA_XOR_MAX_BYTE_COUNT (16 * 1024 * 1024)
231#define IOP_ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024)
232
233static inline int iop_chan_is_busy(struct iop_adma_chan *chan)
234{
235 u32 status = __raw_readl(DMA_CSR(chan));
236 return (status & IOP_ADMA_STATUS_BUSY) ? 1 : 0;
237}
238
239static inline int iop_desc_is_aligned(struct iop_adma_desc_slot *desc,
240 int num_slots)
241{
242 /* num_slots will only ever be 1, 2, 4, or 8 */
243 return (desc->idx & (num_slots - 1)) ? 0 : 1;
244}
245
246/* to do: support large (i.e. > hw max) buffer sizes */
247static inline int iop_chan_memcpy_slot_count(size_t len, int *slots_per_op)
248{
249 *slots_per_op = 1;
250 return 1;
251}
252
253/* to do: support large (i.e. > hw max) buffer sizes */
254static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op)
255{
256 *slots_per_op = 1;
257 return 1;
258}
259
260static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt,
261 int *slots_per_op)
262{
263 static const char slot_count_table[] = {
264 1, 1, 1, 1, /* 01 - 04 */
265 2, 2, 2, 2, /* 05 - 08 */
266 4, 4, 4, 4, /* 09 - 12 */
267 4, 4, 4, 4, /* 13 - 16 */
268 8, 8, 8, 8, /* 17 - 20 */
269 8, 8, 8, 8, /* 21 - 24 */
270 8, 8, 8, 8, /* 25 - 28 */
271 8, 8, 8, 8, /* 29 - 32 */
272 };
273 *slots_per_op = slot_count_table[src_cnt - 1];
274 return *slots_per_op;
275}
276
277static inline int
278iop_chan_interrupt_slot_count(int *slots_per_op, struct iop_adma_chan *chan)
279{
280 switch (chan->device->id) {
281 case DMA0_ID:
282 case DMA1_ID:
283 return iop_chan_memcpy_slot_count(0, slots_per_op);
284 case AAU_ID:
285 return iop3xx_aau_xor_slot_count(0, 2, slots_per_op);
286 default:
287 BUG();
288 }
289 return 0;
290}
291
292static inline int iop_chan_xor_slot_count(size_t len, int src_cnt,
293 int *slots_per_op)
294{
295 int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op);
296
297 if (len <= IOP_ADMA_XOR_MAX_BYTE_COUNT)
298 return slot_cnt;
299
300 len -= IOP_ADMA_XOR_MAX_BYTE_COUNT;
301 while (len > IOP_ADMA_XOR_MAX_BYTE_COUNT) {
302 len -= IOP_ADMA_XOR_MAX_BYTE_COUNT;
303 slot_cnt += *slots_per_op;
304 }
305
306 if (len)
307 slot_cnt += *slots_per_op;
308
309 return slot_cnt;
310}
311
312/* zero sum on iop3xx is limited to 1k at a time so it requires multiple
313 * descriptors
314 */
315static inline int iop_chan_zero_sum_slot_count(size_t len, int src_cnt,
316 int *slots_per_op)
317{
318 int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op);
319
320 if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT)
321 return slot_cnt;
322
323 len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
324 while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
325 len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
326 slot_cnt += *slots_per_op;
327 }
328
329 if (len)
330 slot_cnt += *slots_per_op;
331
332 return slot_cnt;
333}
334
335static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,
336 struct iop_adma_chan *chan)
337{
338 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
339
340 switch (chan->device->id) {
341 case DMA0_ID:
342 case DMA1_ID:
343 return hw_desc.dma->dest_addr;
344 case AAU_ID:
345 return hw_desc.aau->dest_addr;
346 default:
347 BUG();
348 }
349 return 0;
350}
351
352static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
353 struct iop_adma_chan *chan)
354{
355 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
356
357 switch (chan->device->id) {
358 case DMA0_ID:
359 case DMA1_ID:
360 return hw_desc.dma->byte_count;
361 case AAU_ID:
362 return hw_desc.aau->byte_count;
363 default:
364 BUG();
365 }
366 return 0;
367}
368
369/* translate the src_idx to a descriptor word index */
370static inline int __desc_idx(int src_idx)
371{
372 static const int desc_idx_table[] = { 0, 0, 0, 0,
373 0, 1, 2, 3,
374 5, 6, 7, 8,
375 9, 10, 11, 12,
376 14, 15, 16, 17,
377 18, 19, 20, 21,
378 23, 24, 25, 26,
379 27, 28, 29, 30,
380 };
381
382 return desc_idx_table[src_idx];
383}
384
385static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
386 struct iop_adma_chan *chan,
387 int src_idx)
388{
389 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
390
391 switch (chan->device->id) {
392 case DMA0_ID:
393 case DMA1_ID:
394 return hw_desc.dma->src_addr;
395 case AAU_ID:
396 break;
397 default:
398 BUG();
399 }
400
401 if (src_idx < 4)
402 return hw_desc.aau->src[src_idx];
403 else
404 return hw_desc.aau->src_edc[__desc_idx(src_idx)].src_addr;
405}
406
407static inline void iop3xx_aau_desc_set_src_addr(struct iop3xx_desc_aau *hw_desc,
408 int src_idx, dma_addr_t addr)
409{
410 if (src_idx < 4)
411 hw_desc->src[src_idx] = addr;
412 else
413 hw_desc->src_edc[__desc_idx(src_idx)].src_addr = addr;
414}
415
416static inline void
417iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags)
418{
419 struct iop3xx_desc_dma *hw_desc = desc->hw_desc;
420 union {
421 u32 value;
422 struct iop3xx_dma_desc_ctrl field;
423 } u_desc_ctrl;
424
425 u_desc_ctrl.value = 0;
426 u_desc_ctrl.field.mem_to_mem_en = 1;
427 u_desc_ctrl.field.pci_transaction = 0xe; /* memory read block */
428 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
429 hw_desc->desc_ctrl = u_desc_ctrl.value;
430 hw_desc->upper_pci_src_addr = 0;
431 hw_desc->crc_addr = 0;
432}
433
434static inline void
435iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags)
436{
437 struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
438 union {
439 u32 value;
440 struct iop3xx_aau_desc_ctrl field;
441 } u_desc_ctrl;
442
443 u_desc_ctrl.value = 0;
444 u_desc_ctrl.field.blk1_cmd_ctrl = 0x2; /* memory block fill */
445 u_desc_ctrl.field.dest_write_en = 1;
446 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
447 hw_desc->desc_ctrl = u_desc_ctrl.value;
448}
449
450static inline u32
451iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt,
452 unsigned long flags)
453{
454 int i, shift;
455 u32 edcr;
456 union {
457 u32 value;
458 struct iop3xx_aau_desc_ctrl field;
459 } u_desc_ctrl;
460
461 u_desc_ctrl.value = 0;
462 switch (src_cnt) {
463 case 25 ... 32:
464 u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
465 edcr = 0;
466 shift = 1;
467 for (i = 24; i < src_cnt; i++) {
468 edcr |= (1 << shift);
469 shift += 3;
470 }
471 hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = edcr;
472 src_cnt = 24;
473 /* fall through */
474 case 17 ... 24:
475 if (!u_desc_ctrl.field.blk_ctrl) {
476 hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
477 u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
478 }
479 edcr = 0;
480 shift = 1;
481 for (i = 16; i < src_cnt; i++) {
482 edcr |= (1 << shift);
483 shift += 3;
484 }
485 hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = edcr;
486 src_cnt = 16;
487 /* fall through */
488 case 9 ... 16:
489 if (!u_desc_ctrl.field.blk_ctrl)
490 u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */
491 edcr = 0;
492 shift = 1;
493 for (i = 8; i < src_cnt; i++) {
494 edcr |= (1 << shift);
495 shift += 3;
496 }
497 hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = edcr;
498 src_cnt = 8;
499 /* fall through */
500 case 2 ... 8:
501 shift = 1;
502 for (i = 0; i < src_cnt; i++) {
503 u_desc_ctrl.value |= (1 << shift);
504 shift += 3;
505 }
506
507 if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4)
508 u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */
509 }
510
511 u_desc_ctrl.field.dest_write_en = 1;
512 u_desc_ctrl.field.blk1_cmd_ctrl = 0x7; /* direct fill */
513 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
514 hw_desc->desc_ctrl = u_desc_ctrl.value;
515
516 return u_desc_ctrl.value;
517}
518
519static inline void
520iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt,
521 unsigned long flags)
522{
523 iop3xx_desc_init_xor(desc->hw_desc, src_cnt, flags);
524}
525
526/* return the number of operations */
527static inline int
528iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
529 unsigned long flags)
530{
531 int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
532 struct iop3xx_desc_aau *hw_desc, *prev_hw_desc, *iter;
533 union {
534 u32 value;
535 struct iop3xx_aau_desc_ctrl field;
536 } u_desc_ctrl;
537 int i, j;
538
539 hw_desc = desc->hw_desc;
540
541 for (i = 0, j = 0; (slot_cnt -= slots_per_op) >= 0;
542 i += slots_per_op, j++) {
543 iter = iop_hw_desc_slot_idx(hw_desc, i);
544 u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, flags);
545 u_desc_ctrl.field.dest_write_en = 0;
546 u_desc_ctrl.field.zero_result_en = 1;
547 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
548 iter->desc_ctrl = u_desc_ctrl.value;
549
550 /* for the subsequent descriptors preserve the store queue
551 * and chain them together
552 */
553 if (i) {
554 prev_hw_desc =
555 iop_hw_desc_slot_idx(hw_desc, i - slots_per_op);
556 prev_hw_desc->next_desc =
557 (u32) (desc->async_tx.phys + (i << 5));
558 }
559 }
560
561 return j;
562}
563
564static inline void
565iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt,
566 unsigned long flags)
567{
568 struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
569 union {
570 u32 value;
571 struct iop3xx_aau_desc_ctrl field;
572 } u_desc_ctrl;
573
574 u_desc_ctrl.value = 0;
575 switch (src_cnt) {
576 case 25 ... 32:
577 u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
578 hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
579 /* fall through */
580 case 17 ... 24:
581 if (!u_desc_ctrl.field.blk_ctrl) {
582 hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
583 u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
584 }
585 hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = 0;
586 /* fall through */
587 case 9 ... 16:
588 if (!u_desc_ctrl.field.blk_ctrl)
589 u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */
590 hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = 0;
591 /* fall through */
592 case 1 ... 8:
593 if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4)
594 u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */
595 }
596
597 u_desc_ctrl.field.dest_write_en = 0;
598 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
599 hw_desc->desc_ctrl = u_desc_ctrl.value;
600}
601
602static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
603 struct iop_adma_chan *chan,
604 u32 byte_count)
605{
606 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
607
608 switch (chan->device->id) {
609 case DMA0_ID:
610 case DMA1_ID:
611 hw_desc.dma->byte_count = byte_count;
612 break;
613 case AAU_ID:
614 hw_desc.aau->byte_count = byte_count;
615 break;
616 default:
617 BUG();
618 }
619}
620
621static inline void
622iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
623 struct iop_adma_chan *chan)
624{
625 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
626
627 switch (chan->device->id) {
628 case DMA0_ID:
629 case DMA1_ID:
630 iop_desc_init_memcpy(desc, 1);
631 hw_desc.dma->byte_count = 0;
632 hw_desc.dma->dest_addr = 0;
633 hw_desc.dma->src_addr = 0;
634 break;
635 case AAU_ID:
636 iop_desc_init_null_xor(desc, 2, 1);
637 hw_desc.aau->byte_count = 0;
638 hw_desc.aau->dest_addr = 0;
639 hw_desc.aau->src[0] = 0;
640 hw_desc.aau->src[1] = 0;
641 break;
642 default:
643 BUG();
644 }
645}
646
647static inline void
648iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
649{
650 int slots_per_op = desc->slots_per_op;
651 struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;
652 int i = 0;
653
654 if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
655 hw_desc->byte_count = len;
656 } else {
657 do {
658 iter = iop_hw_desc_slot_idx(hw_desc, i);
659 iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
660 len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
661 i += slots_per_op;
662 } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT);
663
664 if (len) {
665 iter = iop_hw_desc_slot_idx(hw_desc, i);
666 iter->byte_count = len;
667 }
668 }
669}
670
671static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
672 struct iop_adma_chan *chan,
673 dma_addr_t addr)
674{
675 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
676
677 switch (chan->device->id) {
678 case DMA0_ID:
679 case DMA1_ID:
680 hw_desc.dma->dest_addr = addr;
681 break;
682 case AAU_ID:
683 hw_desc.aau->dest_addr = addr;
684 break;
685 default:
686 BUG();
687 }
688}
689
690static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
691 dma_addr_t addr)
692{
693 struct iop3xx_desc_dma *hw_desc = desc->hw_desc;
694 hw_desc->src_addr = addr;
695}
696
697static inline void
698iop_desc_set_zero_sum_src_addr(struct iop_adma_desc_slot *desc, int src_idx,
699 dma_addr_t addr)
700{
701
702 struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;
703 int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
704 int i;
705
706 for (i = 0; (slot_cnt -= slots_per_op) >= 0;
707 i += slots_per_op, addr += IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
708 iter = iop_hw_desc_slot_idx(hw_desc, i);
709 iop3xx_aau_desc_set_src_addr(iter, src_idx, addr);
710 }
711}
712
713static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
714 int src_idx, dma_addr_t addr)
715{
716
717 struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;
718 int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
719 int i;
720
721 for (i = 0; (slot_cnt -= slots_per_op) >= 0;
722 i += slots_per_op, addr += IOP_ADMA_XOR_MAX_BYTE_COUNT) {
723 iter = iop_hw_desc_slot_idx(hw_desc, i);
724 iop3xx_aau_desc_set_src_addr(iter, src_idx, addr);
725 }
726}
727
728static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
729 u32 next_desc_addr)
730{
731 /* hw_desc->next_desc is the same location for all channels */
732 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
733 BUG_ON(hw_desc.dma->next_desc);
734 hw_desc.dma->next_desc = next_desc_addr;
735}
736
737static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc)
738{
739 /* hw_desc->next_desc is the same location for all channels */
740 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
741 return hw_desc.dma->next_desc;
742}
743
744static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc)
745{
746 /* hw_desc->next_desc is the same location for all channels */
747 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
748 hw_desc.dma->next_desc = 0;
749}
750
751static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc,
752 u32 val)
753{
754 struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
755 hw_desc->src[0] = val;
756}
757
758static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
759{
760 struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
761 struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
762
763 BUG_ON(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en));
764 return desc_ctrl.zero_result_err;
765}
766
767static inline void iop_chan_append(struct iop_adma_chan *chan)
768{
769 u32 dma_chan_ctrl;
770
771 dma_chan_ctrl = __raw_readl(DMA_CCR(chan));
772 dma_chan_ctrl |= 0x2;
773 __raw_writel(dma_chan_ctrl, DMA_CCR(chan));
774}
775
776static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)
777{
778 return __raw_readl(DMA_CSR(chan));
779}
780
781static inline void iop_chan_disable(struct iop_adma_chan *chan)
782{
783 u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan));
784 dma_chan_ctrl &= ~1;
785 __raw_writel(dma_chan_ctrl, DMA_CCR(chan));
786}
787
788static inline void iop_chan_enable(struct iop_adma_chan *chan)
789{
790 u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan));
791
792 dma_chan_ctrl |= 1;
793 __raw_writel(dma_chan_ctrl, DMA_CCR(chan));
794}
795
796static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)
797{
798 u32 status = __raw_readl(DMA_CSR(chan));
799 status &= (1 << 9);
800 __raw_writel(status, DMA_CSR(chan));
801}
802
803static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)
804{
805 u32 status = __raw_readl(DMA_CSR(chan));
806 status &= (1 << 8);
807 __raw_writel(status, DMA_CSR(chan));
808}
809
810static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)
811{
812 u32 status = __raw_readl(DMA_CSR(chan));
813
814 switch (chan->device->id) {
815 case DMA0_ID:
816 case DMA1_ID:
817 status &= (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1);
818 break;
819 case AAU_ID:
820 status &= (1 << 5);
821 break;
822 default:
823 BUG();
824 }
825
826 __raw_writel(status, DMA_CSR(chan));
827}
828
829static inline int
830iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)
831{
832 return 0;
833}
834
835static inline int
836iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)
837{
838 return 0;
839}
840
841static inline int
842iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)
843{
844 return 0;
845}
846
847static inline int
848iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)
849{
850 return test_bit(5, &status);
851}
852
853static inline int
854iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)
855{
856 switch (chan->device->id) {
857 case DMA0_ID:
858 case DMA1_ID:
859 return test_bit(2, &status);
860 default:
861 return 0;
862 }
863}
864
865static inline int
866iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)
867{
868 switch (chan->device->id) {
869 case DMA0_ID:
870 case DMA1_ID:
871 return test_bit(3, &status);
872 default:
873 return 0;
874 }
875}
876
877static inline int
878iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)
879{
880 switch (chan->device->id) {
881 case DMA0_ID:
882 case DMA1_ID:
883 return test_bit(1, &status);
884 default:
885 return 0;
886 }
887}
888#endif /* _ADMA_H */
diff --git a/arch/arm/include/asm/hardware/iop3xx-gpio.h b/arch/arm/include/asm/hardware/iop3xx-gpio.h
new file mode 100644
index 000000000000..222e74b7c463
--- /dev/null
+++ b/arch/arm/include/asm/hardware/iop3xx-gpio.h
@@ -0,0 +1,73 @@
1/*
2 * arch/arm/include/asm/hardware/iop3xx-gpio.h
3 *
4 * IOP3xx GPIO wrappers
5 *
6 * Copyright (c) 2008 Arnaud Patard <arnaud.patard@rtp-net.org>
7 * Based on IXP4XX gpio.h file
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#ifndef __ASM_ARM_HARDWARE_IOP3XX_GPIO_H
26#define __ASM_ARM_HARDWARE_IOP3XX_GPIO_H
27
28#include <asm/hardware.h>
29#include <asm-generic/gpio.h>
30
31#define IOP3XX_N_GPIOS 8
32
33static inline int gpio_get_value(unsigned gpio)
34{
35 if (gpio > IOP3XX_N_GPIOS)
36 return __gpio_get_value(gpio);
37
38 return gpio_line_get(gpio);
39}
40
41static inline void gpio_set_value(unsigned gpio, int value)
42{
43 if (gpio > IOP3XX_N_GPIOS) {
44 __gpio_set_value(gpio, value);
45 return;
46 }
47 gpio_line_set(gpio, value);
48}
49
50static inline int gpio_cansleep(unsigned gpio)
51{
52 if (gpio < IOP3XX_N_GPIOS)
53 return 0;
54 else
55 return __gpio_cansleep(gpio);
56}
57
58/*
59 * The GPIOs are not generating any interrupt
60 * Note : manuals are not clear about this
61 */
62static inline int gpio_to_irq(int gpio)
63{
64 return -EINVAL;
65}
66
67static inline int irq_to_gpio(int gpio)
68{
69 return -EINVAL;
70}
71
72#endif
73
diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
new file mode 100644
index 000000000000..4b8e7f559929
--- /dev/null
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -0,0 +1,312 @@
1/*
2 * arch/arm/include/asm/hardware/iop3xx.h
3 *
4 * Intel IOP32X and IOP33X register definitions
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __IOP3XX_H
16#define __IOP3XX_H
17
18/*
19 * IOP3XX GPIO handling
20 */
21#define GPIO_IN 0
22#define GPIO_OUT 1
23#define GPIO_LOW 0
24#define GPIO_HIGH 1
25#define IOP3XX_GPIO_LINE(x) (x)
26
27#ifndef __ASSEMBLY__
28extern void gpio_line_config(int line, int direction);
29extern int gpio_line_get(int line);
30extern void gpio_line_set(int line, int value);
31extern int init_atu;
32extern int iop3xx_get_init_atu(void);
33#endif
34
35
36/*
37 * IOP3XX processor registers
38 */
39#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
40#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000
41#define IOP3XX_PERIPHERAL_SIZE 0x00002000
42#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
43 IOP3XX_PERIPHERAL_SIZE - 1)
44#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
45 IOP3XX_PERIPHERAL_SIZE - 1)
46#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
47 (IOP3XX_PERIPHERAL_PHYS_BASE\
48 - IOP3XX_PERIPHERAL_VIRT_BASE))
49#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
50
51/* Address Translation Unit */
52#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
53#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
54#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
55#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
56#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
57#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
58#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
59#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
60#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
61#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
62#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
63#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
64#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
65#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
66#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
67#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
68#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
69#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
70#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
71#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
72#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
73#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
74#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
75#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
76#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
77#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
78#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
79#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
80#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
81#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
82#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
83#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
84#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
85#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
86#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
87#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
88#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
89#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
90#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
91#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
92#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
93#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
94#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
95#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
96#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
97#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
98#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
99#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
100#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
101#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
102#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
103#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
104#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
105#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
106#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
107#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
108#define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
109#define IOP3XX_PCSR_IN_Q_BUSY (1 << 14)
110#define IOP3XX_ATUCR_OUT_EN (1 << 1)
111
112#define IOP3XX_INIT_ATU_DEFAULT 0
113#define IOP3XX_INIT_ATU_DISABLE -1
114#define IOP3XX_INIT_ATU_ENABLE 1
115
116/* Messaging Unit */
117#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
118#define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
119#define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
120#define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
121#define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
122#define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
123#define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
124#define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
125#define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
126#define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
127#define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
128#define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
129#define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
130#define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
131#define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
132#define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
133#define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
134#define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
135#define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
136#define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
137#define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
138
139/* DMA Controller */
140#define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \
141 (0x400 + (chan << 6)))
142#define IOP3XX_DMA_UPPER_PA(chan) (IOP3XX_DMA_PHYS_BASE(chan) + 0x27)
143
144/* Peripheral bus interface */
145#define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
146#define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
147#define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
148#define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
149#define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
150#define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
151#define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
152#define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
153#define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
154#define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
155#define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
156#define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
157#define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
158#define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
159#define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
160#define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
161#define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
162
163/* Peripheral performance monitoring unit */
164#define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
165#define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
166#define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
167#define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
168/* PERCR0 DOESN'T EXIST - index from 1! */
169#define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
170
171/* General Purpose I/O */
172#define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0000)
173#define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0004)
174#define IOP3XX_GPOD (volatile u32 *)IOP3XX_GPIO_REG(0x0008)
175
176/* Timers */
177#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
178#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
179#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
180#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
181#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
182#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
183#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
184#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
185#define IOP_TMR_EN 0x02
186#define IOP_TMR_RELOAD 0x04
187#define IOP_TMR_PRIVILEGED 0x08
188#define IOP_TMR_RATIO_1_1 0x00
189
190/* Watchdog timer definitions */
191#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
192#define IOP_WDTCR_EN 0xe1e1e1e1
193/* iop3xx does not support stopping the watchdog, so we just re-arm */
194#define IOP_WDTCR_DIS_ARM (IOP_WDTCR_EN_ARM)
195#define IOP_WDTCR_DIS (IOP_WDTCR_EN)
196
197/* Application accelerator unit */
198#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
199#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)
200
201/* I2C bus interface unit */
202#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
203#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
204#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
205#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
206#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
207#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
208#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
209#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
210#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
211#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
212
213
214/*
215 * IOP3XX I/O and Mem space regions for PCI autoconfiguration
216 */
217#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
218
219#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000
220#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
221#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000
222#define IOP3XX_PCI_LOWER_IO_BA 0x90000000
223#define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\
224 IOP3XX_PCI_IO_WINDOW_SIZE - 1)
225#define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\
226 IOP3XX_PCI_IO_WINDOW_SIZE - 1)
227#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) (addr) -\
228 IOP3XX_PCI_LOWER_IO_PA) +\
229 IOP3XX_PCI_LOWER_IO_VA)
230
231
232#ifndef __ASSEMBLY__
233void iop3xx_map_io(void);
234void iop_init_cp6_handler(void);
235void iop_init_time(unsigned long tickrate);
236unsigned long iop_gettimeoffset(void);
237
238static inline void write_tmr0(u32 val)
239{
240 asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
241}
242
243static inline void write_tmr1(u32 val)
244{
245 asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
246}
247
248static inline u32 read_tcr0(void)
249{
250 u32 val;
251 asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
252 return val;
253}
254
255static inline u32 read_tcr1(void)
256{
257 u32 val;
258 asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
259 return val;
260}
261
262static inline void write_trr0(u32 val)
263{
264 asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
265}
266
267static inline void write_trr1(u32 val)
268{
269 asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
270}
271
272static inline void write_tisr(u32 val)
273{
274 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
275}
276
277static inline u32 read_wdtcr(void)
278{
279 u32 val;
280 asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val));
281 return val;
282}
283static inline void write_wdtcr(u32 val)
284{
285 asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val));
286}
287
288extern unsigned long get_iop_tick_rate(void);
289
290/* only iop13xx has these registers, we define these to present a
291 * common register interface for the iop_wdt driver.
292 */
293#define IOP_RCSR_WDT (0)
294static inline u32 read_rcsr(void)
295{
296 return 0;
297}
298static inline void write_wdtsr(u32 val)
299{
300 do { } while (0);
301}
302
303extern struct platform_device iop3xx_dma_0_channel;
304extern struct platform_device iop3xx_dma_1_channel;
305extern struct platform_device iop3xx_aau_channel;
306extern struct platform_device iop3xx_i2c0_device;
307extern struct platform_device iop3xx_i2c1_device;
308
309#endif
310
311
312#endif
diff --git a/arch/arm/include/asm/hardware/iop_adma.h b/arch/arm/include/asm/hardware/iop_adma.h
new file mode 100644
index 000000000000..cb7e3611bcba
--- /dev/null
+++ b/arch/arm/include/asm/hardware/iop_adma.h
@@ -0,0 +1,116 @@
1/*
2 * Copyright © 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 */
18#ifndef IOP_ADMA_H
19#define IOP_ADMA_H
20#include <linux/types.h>
21#include <linux/dmaengine.h>
22#include <linux/interrupt.h>
23
24#define IOP_ADMA_SLOT_SIZE 32
25#define IOP_ADMA_THRESHOLD 4
26
27/**
28 * struct iop_adma_device - internal representation of an ADMA device
29 * @pdev: Platform device
30 * @id: HW ADMA Device selector
31 * @dma_desc_pool: base of DMA descriptor region (DMA address)
32 * @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
33 * @common: embedded struct dma_device
34 */
35struct iop_adma_device {
36 struct platform_device *pdev;
37 int id;
38 dma_addr_t dma_desc_pool;
39 void *dma_desc_pool_virt;
40 struct dma_device common;
41};
42
43/**
44 * struct iop_adma_chan - internal representation of an ADMA device
45 * @pending: allows batching of hardware operations
46 * @completed_cookie: identifier for the most recently completed operation
47 * @lock: serializes enqueue/dequeue operations to the slot pool
48 * @mmr_base: memory mapped register base
49 * @chain: device chain view of the descriptors
50 * @device: parent device
51 * @common: common dmaengine channel object members
52 * @last_used: place holder for allocation to continue from where it left off
53 * @all_slots: complete domain of slots usable by the channel
54 * @slots_allocated: records the actual size of the descriptor slot pool
55 * @irq_tasklet: bottom half where iop_adma_slot_cleanup runs
56 */
57struct iop_adma_chan {
58 int pending;
59 dma_cookie_t completed_cookie;
60 spinlock_t lock; /* protects the descriptor slot pool */
61 void __iomem *mmr_base;
62 struct list_head chain;
63 struct iop_adma_device *device;
64 struct dma_chan common;
65 struct iop_adma_desc_slot *last_used;
66 struct list_head all_slots;
67 int slots_allocated;
68 struct tasklet_struct irq_tasklet;
69};
70
71/**
72 * struct iop_adma_desc_slot - IOP-ADMA software descriptor
73 * @slot_node: node on the iop_adma_chan.all_slots list
74 * @chain_node: node on the op_adma_chan.chain list
75 * @hw_desc: virtual address of the hardware descriptor chain
76 * @phys: hardware address of the hardware descriptor chain
77 * @group_head: first operation in a transaction
78 * @slot_cnt: total slots used in an transaction (group of operations)
79 * @slots_per_op: number of slots per operation
80 * @idx: pool index
81 * @unmap_src_cnt: number of xor sources
82 * @unmap_len: transaction bytecount
83 * @async_tx: support for the async_tx api
84 * @group_list: list of slots that make up a multi-descriptor transaction
85 * for example transfer lengths larger than the supported hw max
86 * @xor_check_result: result of zero sum
87 * @crc32_result: result crc calculation
88 */
89struct iop_adma_desc_slot {
90 struct list_head slot_node;
91 struct list_head chain_node;
92 void *hw_desc;
93 struct iop_adma_desc_slot *group_head;
94 u16 slot_cnt;
95 u16 slots_per_op;
96 u16 idx;
97 u16 unmap_src_cnt;
98 size_t unmap_len;
99 struct dma_async_tx_descriptor async_tx;
100 union {
101 u32 *xor_check_result;
102 u32 *crc32_result;
103 };
104};
105
106struct iop_adma_platform_data {
107 int hw_id;
108 dma_cap_mask_t cap_mask;
109 size_t pool_size;
110};
111
112#define to_iop_sw_desc(addr_hw_desc) \
113 container_of(addr_hw_desc, struct iop_adma_desc_slot, hw_desc)
114#define iop_hw_desc_slot_idx(hw_desc, idx) \
115 ( (void *) (((unsigned long) hw_desc) + ((idx) << 5)) )
116#endif
diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h
new file mode 100644
index 000000000000..74b5fff7f575
--- /dev/null
+++ b/arch/arm/include/asm/hardware/it8152.h
@@ -0,0 +1,99 @@
1/*
2 * linux/include/arm/hardware/it8152.h
3 *
4 * Copyright Compulab Ltd., 2006,2007
5 * Mike Rapoport <mike@compulab.co.il>
6 *
7 * ITE 8152 companion chip register definitions
8 */
9
10#ifndef __ASM_HARDWARE_IT8152_H
11#define __ASM_HARDWARE_IT8152_H
12extern unsigned long it8152_base_address;
13
14#define IT8152_IO_BASE (it8152_base_address + 0x03e00000)
15#define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000)
16
17#define __REG_IT8152(x) (it8152_base_address + (x))
18
19#define IT8152_PCI_CFG_ADDR __REG_IT8152(0x3f00800)
20#define IT8152_PCI_CFG_DATA __REG_IT8152(0x3f00804)
21
22#define IT8152_INTC_LDCNIRR __REG_IT8152(0x3f00300)
23#define IT8152_INTC_LDPNIRR __REG_IT8152(0x3f00304)
24#define IT8152_INTC_LDCNIMR __REG_IT8152(0x3f00308)
25#define IT8152_INTC_LDPNIMR __REG_IT8152(0x3f0030C)
26#define IT8152_INTC_LDNITR __REG_IT8152(0x3f00310)
27#define IT8152_INTC_LDNIAR __REG_IT8152(0x3f00314)
28#define IT8152_INTC_LPCNIRR __REG_IT8152(0x3f00320)
29#define IT8152_INTC_LPPNIRR __REG_IT8152(0x3f00324)
30#define IT8152_INTC_LPCNIMR __REG_IT8152(0x3f00328)
31#define IT8152_INTC_LPPNIMR __REG_IT8152(0x3f0032C)
32#define IT8152_INTC_LPNITR __REG_IT8152(0x3f00330)
33#define IT8152_INTC_LPNIAR __REG_IT8152(0x3f00334)
34#define IT8152_INTC_PDCNIRR __REG_IT8152(0x3f00340)
35#define IT8152_INTC_PDPNIRR __REG_IT8152(0x3f00344)
36#define IT8152_INTC_PDCNIMR __REG_IT8152(0x3f00348)
37#define IT8152_INTC_PDPNIMR __REG_IT8152(0x3f0034C)
38#define IT8152_INTC_PDNITR __REG_IT8152(0x3f00350)
39#define IT8152_INTC_PDNIAR __REG_IT8152(0x3f00354)
40#define IT8152_INTC_INTC_TYPER __REG_IT8152(0x3f003FC)
41
42#define IT8152_GPIO_GPDR __REG_IT8152(0x3f00500)
43
44/*
45 Interrupt controller per register summary:
46 ---------------------------------------
47 LCDNIRR:
48 IT8152_LD_IRQ(8) PCICLK stop
49 IT8152_LD_IRQ(7) MCLK ready
50 IT8152_LD_IRQ(6) s/w
51 IT8152_LD_IRQ(5) UART
52 IT8152_LD_IRQ(4) GPIO
53 IT8152_LD_IRQ(3) TIMER 4
54 IT8152_LD_IRQ(2) TIMER 3
55 IT8152_LD_IRQ(1) TIMER 2
56 IT8152_LD_IRQ(0) TIMER 1
57
58 LPCNIRR:
59 IT8152_LP_IRQ(x) serial IRQ x
60
61 PCIDNIRR:
62 IT8152_PD_IRQ(14) PCISERR
63 IT8152_PD_IRQ(13) CPU/PCI bridge target abort (h2pTADR)
64 IT8152_PD_IRQ(12) CPU/PCI bridge master abort (h2pMADR)
65 IT8152_PD_IRQ(11) PCI INTD
66 IT8152_PD_IRQ(10) PCI INTC
67 IT8152_PD_IRQ(9) PCI INTB
68 IT8152_PD_IRQ(8) PCI INTA
69 IT8152_PD_IRQ(7) serial INTD
70 IT8152_PD_IRQ(6) serial INTC
71 IT8152_PD_IRQ(5) serial INTB
72 IT8152_PD_IRQ(4) serial INTA
73 IT8152_PD_IRQ(3) serial IRQ IOCHK (IOCHKR)
74 IT8152_PD_IRQ(2) chaining DMA (CDMAR)
75 IT8152_PD_IRQ(1) USB (USBR)
76 IT8152_PD_IRQ(0) Audio controller (ACR)
77 */
78/* frequently used interrupts */
79#define IT8152_PCISERR IT8152_PD_IRQ(14)
80#define IT8152_H2PTADR IT8152_PD_IRQ(13)
81#define IT8152_H2PMAR IT8152_PD_IRQ(12)
82#define IT8152_PCI_INTD IT8152_PD_IRQ(11)
83#define IT8152_PCI_INTC IT8152_PD_IRQ(10)
84#define IT8152_PCI_INTB IT8152_PD_IRQ(9)
85#define IT8152_PCI_INTA IT8152_PD_IRQ(8)
86#define IT8152_CDMA_INT IT8152_PD_IRQ(2)
87#define IT8152_USB_INT IT8152_PD_IRQ(1)
88#define IT8152_AUDIO_INT IT8152_PD_IRQ(0)
89
90struct pci_dev;
91struct pci_sys_data;
92
93extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc);
94extern void it8152_init_irq(void);
95extern int it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
96extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
97extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys);
98
99#endif /* __ASM_HARDWARE_IT8152_H */
diff --git a/arch/arm/include/asm/hardware/linkup-l1110.h b/arch/arm/include/asm/hardware/linkup-l1110.h
new file mode 100644
index 000000000000..7ec91168a576
--- /dev/null
+++ b/arch/arm/include/asm/hardware/linkup-l1110.h
@@ -0,0 +1,48 @@
1/*
2*
3* Definitions for H3600 Handheld Computer
4*
5* Copyright 2001 Compaq Computer Corporation.
6*
7* Use consistent with the GNU GPL is permitted,
8* provided that this copyright notice is
9* preserved in its entirety in all copies and derived works.
10*
11* COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
12* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
13* FITNESS FOR ANY PARTICULAR PURPOSE.
14*
15* Author: Jamey Hicks.
16*
17*/
18
19/* LinkUp Systems PCCard/CompactFlash Interface for SA-1100 */
20
21/* PC Card Status Register */
22#define LINKUP_PRS_S1 (1 << 0) /* voltage control bits S1-S4 */
23#define LINKUP_PRS_S2 (1 << 1)
24#define LINKUP_PRS_S3 (1 << 2)
25#define LINKUP_PRS_S4 (1 << 3)
26#define LINKUP_PRS_BVD1 (1 << 4)
27#define LINKUP_PRS_BVD2 (1 << 5)
28#define LINKUP_PRS_VS1 (1 << 6)
29#define LINKUP_PRS_VS2 (1 << 7)
30#define LINKUP_PRS_RDY (1 << 8)
31#define LINKUP_PRS_CD1 (1 << 9)
32#define LINKUP_PRS_CD2 (1 << 10)
33
34/* PC Card Command Register */
35#define LINKUP_PRC_S1 (1 << 0)
36#define LINKUP_PRC_S2 (1 << 1)
37#define LINKUP_PRC_S3 (1 << 2)
38#define LINKUP_PRC_S4 (1 << 3)
39#define LINKUP_PRC_RESET (1 << 4)
40#define LINKUP_PRC_APOE (1 << 5) /* Auto Power Off Enable: clears S1-S4 when either nCD goes high */
41#define LINKUP_PRC_CFE (1 << 6) /* CompactFlash mode Enable: addresses A[10:0] only, A[25:11] high */
42#define LINKUP_PRC_SOE (1 << 7) /* signal output driver enable */
43#define LINKUP_PRC_SSP (1 << 8) /* sock select polarity: 0 for socket 0, 1 for socket 1 */
44#define LINKUP_PRC_MBZ (1 << 15) /* must be zero */
45
46struct linkup_l1110 {
47 volatile short prc;
48};
diff --git a/arch/arm/include/asm/hardware/locomo.h b/arch/arm/include/asm/hardware/locomo.h
new file mode 100644
index 000000000000..954b1be991b4
--- /dev/null
+++ b/arch/arm/include/asm/hardware/locomo.h
@@ -0,0 +1,217 @@
1/*
2 * arch/arm/include/asm/hardware/locomo.h
3 *
4 * This file contains the definitions for the LoCoMo G/A Chip
5 *
6 * (C) Copyright 2004 John Lenz
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 *
11 * Based on sa1111.h
12 */
13#ifndef _ASM_ARCH_LOCOMO
14#define _ASM_ARCH_LOCOMO
15
16#define locomo_writel(val,addr) ({ *(volatile u16 *)(addr) = (val); })
17#define locomo_readl(addr) (*(volatile u16 *)(addr))
18
19/* LOCOMO version */
20#define LOCOMO_VER 0x00
21
22/* Pin status */
23#define LOCOMO_ST 0x04
24
25/* Pin status */
26#define LOCOMO_C32K 0x08
27
28/* Interrupt controller */
29#define LOCOMO_ICR 0x0C
30
31/* MCS decoder for boot selecting */
32#define LOCOMO_MCSX0 0x10
33#define LOCOMO_MCSX1 0x14
34#define LOCOMO_MCSX2 0x18
35#define LOCOMO_MCSX3 0x1c
36
37/* Touch panel controller */
38#define LOCOMO_ASD 0x20 /* AD start delay */
39#define LOCOMO_HSD 0x28 /* HSYS delay */
40#define LOCOMO_HSC 0x2c /* HSYS period */
41#define LOCOMO_TADC 0x30 /* tablet ADC clock */
42
43
44/* Long time timer */
45#define LOCOMO_LTC 0xd8 /* LTC interrupt setting */
46#define LOCOMO_LTINT 0xdc /* LTC interrupt */
47
48/* DAC control signal for LCD (COMADJ ) */
49#define LOCOMO_DAC 0xe0
50/* DAC control */
51#define LOCOMO_DAC_SCLOEB 0x08 /* SCL pin output data */
52#define LOCOMO_DAC_TEST 0x04 /* Test bit */
53#define LOCOMO_DAC_SDA 0x02 /* SDA pin level (read-only) */
54#define LOCOMO_DAC_SDAOEB 0x01 /* SDA pin output data */
55
56/* SPI interface */
57#define LOCOMO_SPI 0x60
58#define LOCOMO_SPIMD 0x00 /* SPI mode setting */
59#define LOCOMO_SPICT 0x04 /* SPI mode control */
60#define LOCOMO_SPIST 0x08 /* SPI status */
61#define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */
62#define LOCOMO_SPI_REND (1 << 2) /* Receive end bit */
63#define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */
64#define LOCOMO_SPI_RFR (1) /* read buffer bit */
65
66#define LOCOMO_SPIIS 0x10 /* SPI interrupt status */
67#define LOCOMO_SPIWE 0x14 /* SPI interrupt status write enable */
68#define LOCOMO_SPIIE 0x18 /* SPI interrupt enable */
69#define LOCOMO_SPIIR 0x1c /* SPI interrupt request */
70#define LOCOMO_SPITD 0x20 /* SPI transfer data write */
71#define LOCOMO_SPIRD 0x24 /* SPI receive data read */
72#define LOCOMO_SPITS 0x28 /* SPI transfer data shift */
73#define LOCOMO_SPIRS 0x2C /* SPI receive data shift */
74
75/* GPIO */
76#define LOCOMO_GPD 0x90 /* GPIO direction */
77#define LOCOMO_GPE 0x94 /* GPIO input enable */
78#define LOCOMO_GPL 0x98 /* GPIO level */
79#define LOCOMO_GPO 0x9c /* GPIO out data setting */
80#define LOCOMO_GRIE 0xa0 /* GPIO rise detection */
81#define LOCOMO_GFIE 0xa4 /* GPIO fall detection */
82#define LOCOMO_GIS 0xa8 /* GPIO edge detection status */
83#define LOCOMO_GWE 0xac /* GPIO status write enable */
84#define LOCOMO_GIE 0xb0 /* GPIO interrupt enable */
85#define LOCOMO_GIR 0xb4 /* GPIO interrupt request */
86#define LOCOMO_GPIO(Nb) (0x01 << (Nb))
87#define LOCOMO_GPIO_RTS LOCOMO_GPIO(0)
88#define LOCOMO_GPIO_CTS LOCOMO_GPIO(1)
89#define LOCOMO_GPIO_DSR LOCOMO_GPIO(2)
90#define LOCOMO_GPIO_DTR LOCOMO_GPIO(3)
91#define LOCOMO_GPIO_LCD_VSHA_ON LOCOMO_GPIO(4)
92#define LOCOMO_GPIO_LCD_VSHD_ON LOCOMO_GPIO(5)
93#define LOCOMO_GPIO_LCD_VEE_ON LOCOMO_GPIO(6)
94#define LOCOMO_GPIO_LCD_MOD LOCOMO_GPIO(7)
95#define LOCOMO_GPIO_DAC_ON LOCOMO_GPIO(8)
96#define LOCOMO_GPIO_FL_VR LOCOMO_GPIO(9)
97#define LOCOMO_GPIO_DAC_SDATA LOCOMO_GPIO(10)
98#define LOCOMO_GPIO_DAC_SCK LOCOMO_GPIO(11)
99#define LOCOMO_GPIO_DAC_SLOAD LOCOMO_GPIO(12)
100#define LOCOMO_GPIO_CARD_DETECT LOCOMO_GPIO(13)
101#define LOCOMO_GPIO_WRITE_PROT LOCOMO_GPIO(14)
102#define LOCOMO_GPIO_CARD_POWER LOCOMO_GPIO(15)
103
104/* Start the definitions of the devices. Each device has an initial
105 * base address and a series of offsets from that base address. */
106
107/* Keyboard controller */
108#define LOCOMO_KEYBOARD 0x40
109#define LOCOMO_KIB 0x00 /* KIB level */
110#define LOCOMO_KSC 0x04 /* KSTRB control */
111#define LOCOMO_KCMD 0x08 /* KSTRB command */
112#define LOCOMO_KIC 0x0c /* Key interrupt */
113
114/* Front light adjustment controller */
115#define LOCOMO_FRONTLIGHT 0xc8
116#define LOCOMO_ALS 0x00 /* Adjust light cycle */
117#define LOCOMO_ALD 0x04 /* Adjust light duty */
118
119#define LOCOMO_ALC_EN 0x8000
120
121/* Backlight controller: TFT signal */
122#define LOCOMO_BACKLIGHT 0x38
123#define LOCOMO_TC 0x00 /* TFT control signal */
124#define LOCOMO_CPSD 0x04 /* CPS delay */
125
126/* Audio controller */
127#define LOCOMO_AUDIO 0x54
128#define LOCOMO_ACC 0x00 /* Audio clock */
129#define LOCOMO_PAIF 0xD0 /* PCM audio interface */
130/* Audio clock */
131#define LOCOMO_ACC_XON 0x80
132#define LOCOMO_ACC_XEN 0x40
133#define LOCOMO_ACC_XSEL0 0x00
134#define LOCOMO_ACC_XSEL1 0x20
135#define LOCOMO_ACC_MCLKEN 0x10
136#define LOCOMO_ACC_64FSEN 0x08
137#define LOCOMO_ACC_CLKSEL000 0x00 /* mclk 2 */
138#define LOCOMO_ACC_CLKSEL001 0x01 /* mclk 3 */
139#define LOCOMO_ACC_CLKSEL010 0x02 /* mclk 4 */
140#define LOCOMO_ACC_CLKSEL011 0x03 /* mclk 6 */
141#define LOCOMO_ACC_CLKSEL100 0x04 /* mclk 8 */
142#define LOCOMO_ACC_CLKSEL101 0x05 /* mclk 12 */
143/* PCM audio interface */
144#define LOCOMO_PAIF_SCINV 0x20
145#define LOCOMO_PAIF_SCEN 0x10
146#define LOCOMO_PAIF_LRCRST 0x08
147#define LOCOMO_PAIF_LRCEVE 0x04
148#define LOCOMO_PAIF_LRCINV 0x02
149#define LOCOMO_PAIF_LRCEN 0x01
150
151/* LED controller */
152#define LOCOMO_LED 0xe8
153#define LOCOMO_LPT0 0x00
154#define LOCOMO_LPT1 0x04
155/* LED control */
156#define LOCOMO_LPT_TOFH 0x80
157#define LOCOMO_LPT_TOFL 0x08
158#define LOCOMO_LPT_TOH(TOH) ((TOH & 0x7) << 4)
159#define LOCOMO_LPT_TOL(TOL) ((TOL & 0x7))
160
161extern struct bus_type locomo_bus_type;
162
163#define LOCOMO_DEVID_KEYBOARD 0
164#define LOCOMO_DEVID_FRONTLIGHT 1
165#define LOCOMO_DEVID_BACKLIGHT 2
166#define LOCOMO_DEVID_AUDIO 3
167#define LOCOMO_DEVID_LED 4
168#define LOCOMO_DEVID_UART 5
169#define LOCOMO_DEVID_SPI 6
170
171struct locomo_dev {
172 struct device dev;
173 unsigned int devid;
174 unsigned int irq[1];
175
176 void *mapbase;
177 unsigned long length;
178
179 u64 dma_mask;
180};
181
182#define LOCOMO_DEV(_d) container_of((_d), struct locomo_dev, dev)
183
184#define locomo_get_drvdata(d) dev_get_drvdata(&(d)->dev)
185#define locomo_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
186
187struct locomo_driver {
188 struct device_driver drv;
189 unsigned int devid;
190 int (*probe)(struct locomo_dev *);
191 int (*remove)(struct locomo_dev *);
192 int (*suspend)(struct locomo_dev *, pm_message_t);
193 int (*resume)(struct locomo_dev *);
194};
195
196#define LOCOMO_DRV(_d) container_of((_d), struct locomo_driver, drv)
197
198#define LOCOMO_DRIVER_NAME(_ldev) ((_ldev)->dev.driver->name)
199
200void locomo_lcd_power(struct locomo_dev *, int, unsigned int);
201
202int locomo_driver_register(struct locomo_driver *);
203void locomo_driver_unregister(struct locomo_driver *);
204
205/* GPIO control functions */
206void locomo_gpio_set_dir(struct device *dev, unsigned int bits, unsigned int dir);
207int locomo_gpio_read_level(struct device *dev, unsigned int bits);
208int locomo_gpio_read_output(struct device *dev, unsigned int bits);
209void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set);
210
211/* M62332 control function */
212void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel);
213
214/* Frontlight control */
215void locomo_frontlight_set(struct locomo_dev *dev, int duty, int vr, int bpwf);
216
217#endif
diff --git a/arch/arm/include/asm/hardware/memc.h b/arch/arm/include/asm/hardware/memc.h
new file mode 100644
index 000000000000..42ba7c167d1f
--- /dev/null
+++ b/arch/arm/include/asm/hardware/memc.h
@@ -0,0 +1,26 @@
1/*
2 * arch/arm/include/asm/hardware/memc.h
3 *
4 * Copyright (C) Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#define VDMA_ALIGNMENT PAGE_SIZE
11#define VDMA_XFERSIZE 16
12#define VDMA_INIT 0
13#define VDMA_START 1
14#define VDMA_END 2
15
16#ifndef __ASSEMBLY__
17extern void memc_write(unsigned int reg, unsigned long val);
18
19#define video_set_dma(start,end,offset) \
20do { \
21 memc_write (VDMA_START, (start >> 2)); \
22 memc_write (VDMA_END, (end - VDMA_XFERSIZE) >> 2); \
23 memc_write (VDMA_INIT, (offset >> 2)); \
24} while (0)
25
26#endif
diff --git a/arch/arm/include/asm/hardware/pci_v3.h b/arch/arm/include/asm/hardware/pci_v3.h
new file mode 100644
index 000000000000..2811c7e2cfdf
--- /dev/null
+++ b/arch/arm/include/asm/hardware/pci_v3.h
@@ -0,0 +1,186 @@
1/*
2 * arch/arm/include/asm/hardware/pci_v3.h
3 *
4 * Internal header file PCI V3 chip
5 *
6 * Copyright (C) ARM Limited
7 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef ASM_ARM_HARDWARE_PCI_V3_H
24#define ASM_ARM_HARDWARE_PCI_V3_H
25
26/* -------------------------------------------------------------------------------
27 * V3 Local Bus to PCI Bridge definitions
28 * -------------------------------------------------------------------------------
29 * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
30 * All V3 register names are prefaced by V3_ to avoid clashing with any other
31 * PCI definitions. Their names match the user's manual.
32 *
33 * I'm assuming that I20 is disabled.
34 *
35 */
36#define V3_PCI_VENDOR 0x00000000
37#define V3_PCI_DEVICE 0x00000002
38#define V3_PCI_CMD 0x00000004
39#define V3_PCI_STAT 0x00000006
40#define V3_PCI_CC_REV 0x00000008
41#define V3_PCI_HDR_CFG 0x0000000C
42#define V3_PCI_IO_BASE 0x00000010
43#define V3_PCI_BASE0 0x00000014
44#define V3_PCI_BASE1 0x00000018
45#define V3_PCI_SUB_VENDOR 0x0000002C
46#define V3_PCI_SUB_ID 0x0000002E
47#define V3_PCI_ROM 0x00000030
48#define V3_PCI_BPARAM 0x0000003C
49#define V3_PCI_MAP0 0x00000040
50#define V3_PCI_MAP1 0x00000044
51#define V3_PCI_INT_STAT 0x00000048
52#define V3_PCI_INT_CFG 0x0000004C
53#define V3_LB_BASE0 0x00000054
54#define V3_LB_BASE1 0x00000058
55#define V3_LB_MAP0 0x0000005E
56#define V3_LB_MAP1 0x00000062
57#define V3_LB_BASE2 0x00000064
58#define V3_LB_MAP2 0x00000066
59#define V3_LB_SIZE 0x00000068
60#define V3_LB_IO_BASE 0x0000006E
61#define V3_FIFO_CFG 0x00000070
62#define V3_FIFO_PRIORITY 0x00000072
63#define V3_FIFO_STAT 0x00000074
64#define V3_LB_ISTAT 0x00000076
65#define V3_LB_IMASK 0x00000077
66#define V3_SYSTEM 0x00000078
67#define V3_LB_CFG 0x0000007A
68#define V3_PCI_CFG 0x0000007C
69#define V3_DMA_PCI_ADR0 0x00000080
70#define V3_DMA_PCI_ADR1 0x00000090
71#define V3_DMA_LOCAL_ADR0 0x00000084
72#define V3_DMA_LOCAL_ADR1 0x00000094
73#define V3_DMA_LENGTH0 0x00000088
74#define V3_DMA_LENGTH1 0x00000098
75#define V3_DMA_CSR0 0x0000008B
76#define V3_DMA_CSR1 0x0000009B
77#define V3_DMA_CTLB_ADR0 0x0000008C
78#define V3_DMA_CTLB_ADR1 0x0000009C
79#define V3_DMA_DELAY 0x000000E0
80#define V3_MAIL_DATA 0x000000C0
81#define V3_PCI_MAIL_IEWR 0x000000D0
82#define V3_PCI_MAIL_IERD 0x000000D2
83#define V3_LB_MAIL_IEWR 0x000000D4
84#define V3_LB_MAIL_IERD 0x000000D6
85#define V3_MAIL_WR_STAT 0x000000D8
86#define V3_MAIL_RD_STAT 0x000000DA
87#define V3_QBA_MAP 0x000000DC
88
89/* PCI COMMAND REGISTER bits
90 */
91#define V3_COMMAND_M_FBB_EN (1 << 9)
92#define V3_COMMAND_M_SERR_EN (1 << 8)
93#define V3_COMMAND_M_PAR_EN (1 << 6)
94#define V3_COMMAND_M_MASTER_EN (1 << 2)
95#define V3_COMMAND_M_MEM_EN (1 << 1)
96#define V3_COMMAND_M_IO_EN (1 << 0)
97
98/* SYSTEM REGISTER bits
99 */
100#define V3_SYSTEM_M_RST_OUT (1 << 15)
101#define V3_SYSTEM_M_LOCK (1 << 14)
102
103/* PCI_CFG bits
104 */
105#define V3_PCI_CFG_M_I2O_EN (1 << 15)
106#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
107#define V3_PCI_CFG_M_IO_DIS (1 << 13)
108#define V3_PCI_CFG_M_EN3V (1 << 12)
109#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
110#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
111#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
112
113/* PCI_BASE register bits (PCI -> Local Bus)
114 */
115#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
116#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
117#define V3_PCI_BASE_M_PREFETCH (1 << 3)
118#define V3_PCI_BASE_M_TYPE (3 << 1)
119#define V3_PCI_BASE_M_IO (1 << 0)
120
121/* PCI MAP register bits (PCI -> Local bus)
122 */
123#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
124#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
125#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
126#define V3_PCI_MAP_M_SWAP (3 << 8)
127#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
128#define V3_PCI_MAP_M_REG_EN (1 << 1)
129#define V3_PCI_MAP_M_ENABLE (1 << 0)
130
131/*
132 * LB_BASE0,1 register bits (Local bus -> PCI)
133 */
134#define V3_LB_BASE_ADR_BASE 0xfff00000
135#define V3_LB_BASE_SWAP (3 << 8)
136#define V3_LB_BASE_ADR_SIZE (15 << 4)
137#define V3_LB_BASE_PREFETCH (1 << 3)
138#define V3_LB_BASE_ENABLE (1 << 0)
139
140#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
141#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
142#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
143#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
144#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
145#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
146#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
147#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
148#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
149#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
150#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
151#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
152
153#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
154
155/*
156 * LB_MAP0,1 register bits (Local bus -> PCI)
157 */
158#define V3_LB_MAP_MAP_ADR 0xfff0
159#define V3_LB_MAP_TYPE (7 << 1)
160#define V3_LB_MAP_AD_LOW_EN (1 << 0)
161
162#define V3_LB_MAP_TYPE_IACK (0 << 1)
163#define V3_LB_MAP_TYPE_IO (1 << 1)
164#define V3_LB_MAP_TYPE_MEM (3 << 1)
165#define V3_LB_MAP_TYPE_CONFIG (5 << 1)
166#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
167
168#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
169
170/*
171 * LB_BASE2 register bits (Local bus -> PCI IO)
172 */
173#define V3_LB_BASE2_ADR_BASE 0xff00
174#define V3_LB_BASE2_SWAP (3 << 6)
175#define V3_LB_BASE2_ENABLE (1 << 0)
176
177#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
178
179/*
180 * LB_MAP2 register bits (Local bus -> PCI IO)
181 */
182#define V3_LB_MAP2_MAP_ADR 0xff00
183
184#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
185
186#endif
diff --git a/arch/arm/include/asm/hardware/sa1111.h b/arch/arm/include/asm/hardware/sa1111.h
new file mode 100644
index 000000000000..6cf98d4f7dc3
--- /dev/null
+++ b/arch/arm/include/asm/hardware/sa1111.h
@@ -0,0 +1,581 @@
1/*
2 * arch/arm/include/asm/hardware/sa1111.h
3 *
4 * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
5 *
6 * This file contains definitions for the SA-1111 Companion Chip.
7 * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.)
8 *
9 * Macro that calculates real address for registers in the SA-1111
10 */
11
12#ifndef _ASM_ARCH_SA1111
13#define _ASM_ARCH_SA1111
14
15#include <asm/arch/bitfield.h>
16
17/*
18 * The SA1111 is always located at virtual 0xf4000000, and is always
19 * "native" endian.
20 */
21
22#define SA1111_VBASE 0xf4000000
23
24/* Don't use these! */
25#define SA1111_p2v( x ) ((x) - SA1111_BASE + SA1111_VBASE)
26#define SA1111_v2p( x ) ((x) - SA1111_VBASE + SA1111_BASE)
27
28#ifndef __ASSEMBLY__
29#define _SA1111(x) ((x) + sa1111->resource.start)
30#endif
31
32#define sa1111_writel(val,addr) __raw_writel(val, addr)
33#define sa1111_readl(addr) __raw_readl(addr)
34
35/*
36 * 26 bits of the SA-1110 address bus are available to the SA-1111.
37 * Use these when feeding target addresses to the DMA engines.
38 */
39
40#define SA1111_ADDR_WIDTH (26)
41#define SA1111_ADDR_MASK ((1<<SA1111_ADDR_WIDTH)-1)
42#define SA1111_DMA_ADDR(x) ((x)&SA1111_ADDR_MASK)
43
44/*
45 * Don't ask the (SAC) DMA engines to move less than this amount.
46 */
47
48#define SA1111_SAC_DMA_MIN_XFER (0x800)
49
50/*
51 * System Bus Interface (SBI)
52 *
53 * Registers
54 * SKCR Control Register
55 * SMCR Shared Memory Controller Register
56 * SKID ID Register
57 */
58#define SA1111_SKCR 0x0000
59#define SA1111_SMCR 0x0004
60#define SA1111_SKID 0x0008
61
62#define SKCR_PLL_BYPASS (1<<0)
63#define SKCR_RCLKEN (1<<1)
64#define SKCR_SLEEP (1<<2)
65#define SKCR_DOZE (1<<3)
66#define SKCR_VCO_OFF (1<<4)
67#define SKCR_SCANTSTEN (1<<5)
68#define SKCR_CLKTSTEN (1<<6)
69#define SKCR_RDYEN (1<<7)
70#define SKCR_SELAC (1<<8)
71#define SKCR_OPPC (1<<9)
72#define SKCR_PLLTSTEN (1<<10)
73#define SKCR_USBIOTSTEN (1<<11)
74/*
75 * Don't believe the specs! Take them, throw them outside. Leave them
76 * there for a week. Spit on them. Walk on them. Stamp on them.
77 * Pour gasoline over them and finally burn them. Now think about coding.
78 * - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
79 * - The Feb 2001 errata (278260-010) says that the previous errata
80 * (278260-009) is wrong, and its bit actually 12, fixed in spec
81 * 278242-003.
82 * - The SA1111 manual (278242) says bit 12, but 0 to enable.
83 * - Reality is bit 13, 1 to enable.
84 * -- rmk
85 */
86#define SKCR_OE_EN (1<<13)
87
88#define SMCR_DTIM (1<<0)
89#define SMCR_MBGE (1<<1)
90#define SMCR_DRAC_0 (1<<2)
91#define SMCR_DRAC_1 (1<<3)
92#define SMCR_DRAC_2 (1<<4)
93#define SMCR_DRAC Fld(3, 2)
94#define SMCR_CLAT (1<<5)
95
96#define SKID_SIREV_MASK (0x000000f0)
97#define SKID_MTREV_MASK (0x0000000f)
98#define SKID_ID_MASK (0xffffff00)
99#define SKID_SA1111_ID (0x690cc200)
100
101/*
102 * System Controller
103 *
104 * Registers
105 * SKPCR Power Control Register
106 * SKCDR Clock Divider Register
107 * SKAUD Audio Clock Divider Register
108 * SKPMC PS/2 Mouse Clock Divider Register
109 * SKPTC PS/2 Track Pad Clock Divider Register
110 * SKPEN0 PWM0 Enable Register
111 * SKPWM0 PWM0 Clock Register
112 * SKPEN1 PWM1 Enable Register
113 * SKPWM1 PWM1 Clock Register
114 */
115#define SA1111_SKPCR 0x0200
116#define SA1111_SKCDR 0x0204
117#define SA1111_SKAUD 0x0208
118#define SA1111_SKPMC 0x020c
119#define SA1111_SKPTC 0x0210
120#define SA1111_SKPEN0 0x0214
121#define SA1111_SKPWM0 0x0218
122#define SA1111_SKPEN1 0x021c
123#define SA1111_SKPWM1 0x0220
124
125#define SKPCR_UCLKEN (1<<0)
126#define SKPCR_ACCLKEN (1<<1)
127#define SKPCR_I2SCLKEN (1<<2)
128#define SKPCR_L3CLKEN (1<<3)
129#define SKPCR_SCLKEN (1<<4)
130#define SKPCR_PMCLKEN (1<<5)
131#define SKPCR_PTCLKEN (1<<6)
132#define SKPCR_DCLKEN (1<<7)
133#define SKPCR_PWMCLKEN (1<<8)
134
135/*
136 * USB Host controller
137 */
138#define SA1111_USB 0x0400
139
140/*
141 * Offsets from SA1111_USB_BASE
142 */
143#define SA1111_USB_STATUS 0x0118
144#define SA1111_USB_RESET 0x011c
145#define SA1111_USB_IRQTEST 0x0120
146
147#define USB_RESET_FORCEIFRESET (1 << 0)
148#define USB_RESET_FORCEHCRESET (1 << 1)
149#define USB_RESET_CLKGENRESET (1 << 2)
150#define USB_RESET_SIMSCALEDOWN (1 << 3)
151#define USB_RESET_USBINTTEST (1 << 4)
152#define USB_RESET_SLEEPSTBYEN (1 << 5)
153#define USB_RESET_PWRSENSELOW (1 << 6)
154#define USB_RESET_PWRCTRLLOW (1 << 7)
155
156#define USB_STATUS_IRQHCIRMTWKUP (1 << 7)
157#define USB_STATUS_IRQHCIBUFFACC (1 << 8)
158#define USB_STATUS_NIRQHCIM (1 << 9)
159#define USB_STATUS_NHCIMFCLR (1 << 10)
160#define USB_STATUS_USBPWRSENSE (1 << 11)
161
162/*
163 * Serial Audio Controller
164 *
165 * Registers
166 * SACR0 Serial Audio Common Control Register
167 * SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register
168 * SACR2 Serial Audio AC-link Control Register
169 * SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register
170 * SASR1 Serial Audio AC-link Interface & FIFO Status Register
171 * SASCR Serial Audio Status Clear Register
172 * L3_CAR L3 Control Bus Address Register
173 * L3_CDR L3 Control Bus Data Register
174 * ACCAR AC-link Command Address Register
175 * ACCDR AC-link Command Data Register
176 * ACSAR AC-link Status Address Register
177 * ACSDR AC-link Status Data Register
178 * SADTCS Serial Audio DMA Transmit Control/Status Register
179 * SADTSA Serial Audio DMA Transmit Buffer Start Address A
180 * SADTCA Serial Audio DMA Transmit Buffer Count Register A
181 * SADTSB Serial Audio DMA Transmit Buffer Start Address B
182 * SADTCB Serial Audio DMA Transmit Buffer Count Register B
183 * SADRCS Serial Audio DMA Receive Control/Status Register
184 * SADRSA Serial Audio DMA Receive Buffer Start Address A
185 * SADRCA Serial Audio DMA Receive Buffer Count Register A
186 * SADRSB Serial Audio DMA Receive Buffer Start Address B
187 * SADRCB Serial Audio DMA Receive Buffer Count Register B
188 * SAITR Serial Audio Interrupt Test Register
189 * SADR Serial Audio Data Register (16 x 32-bit)
190 */
191
192#define SA1111_SERAUDIO 0x0600
193
194/*
195 * These are offsets from the above base.
196 */
197#define SA1111_SACR0 0x00
198#define SA1111_SACR1 0x04
199#define SA1111_SACR2 0x08
200#define SA1111_SASR0 0x0c
201#define SA1111_SASR1 0x10
202#define SA1111_SASCR 0x18
203#define SA1111_L3_CAR 0x1c
204#define SA1111_L3_CDR 0x20
205#define SA1111_ACCAR 0x24
206#define SA1111_ACCDR 0x28
207#define SA1111_ACSAR 0x2c
208#define SA1111_ACSDR 0x30
209#define SA1111_SADTCS 0x34
210#define SA1111_SADTSA 0x38
211#define SA1111_SADTCA 0x3c
212#define SA1111_SADTSB 0x40
213#define SA1111_SADTCB 0x44
214#define SA1111_SADRCS 0x48
215#define SA1111_SADRSA 0x4c
216#define SA1111_SADRCA 0x50
217#define SA1111_SADRSB 0x54
218#define SA1111_SADRCB 0x58
219#define SA1111_SAITR 0x5c
220#define SA1111_SADR 0x80
221
222#ifndef CONFIG_ARCH_PXA
223
224#define SACR0_ENB (1<<0)
225#define SACR0_BCKD (1<<2)
226#define SACR0_RST (1<<3)
227
228#define SACR1_AMSL (1<<0)
229#define SACR1_L3EN (1<<1)
230#define SACR1_L3MB (1<<2)
231#define SACR1_DREC (1<<3)
232#define SACR1_DRPL (1<<4)
233#define SACR1_ENLBF (1<<5)
234
235#define SACR2_TS3V (1<<0)
236#define SACR2_TS4V (1<<1)
237#define SACR2_WKUP (1<<2)
238#define SACR2_DREC (1<<3)
239#define SACR2_DRPL (1<<4)
240#define SACR2_ENLBF (1<<5)
241#define SACR2_RESET (1<<6)
242
243#define SASR0_TNF (1<<0)
244#define SASR0_RNE (1<<1)
245#define SASR0_BSY (1<<2)
246#define SASR0_TFS (1<<3)
247#define SASR0_RFS (1<<4)
248#define SASR0_TUR (1<<5)
249#define SASR0_ROR (1<<6)
250#define SASR0_L3WD (1<<16)
251#define SASR0_L3RD (1<<17)
252
253#define SASR1_TNF (1<<0)
254#define SASR1_RNE (1<<1)
255#define SASR1_BSY (1<<2)
256#define SASR1_TFS (1<<3)
257#define SASR1_RFS (1<<4)
258#define SASR1_TUR (1<<5)
259#define SASR1_ROR (1<<6)
260#define SASR1_CADT (1<<16)
261#define SASR1_SADR (1<<17)
262#define SASR1_RSTO (1<<18)
263#define SASR1_CLPM (1<<19)
264#define SASR1_CRDY (1<<20)
265#define SASR1_RS3V (1<<21)
266#define SASR1_RS4V (1<<22)
267
268#define SASCR_TUR (1<<5)
269#define SASCR_ROR (1<<6)
270#define SASCR_DTS (1<<16)
271#define SASCR_RDD (1<<17)
272#define SASCR_STO (1<<18)
273
274#define SADTCS_TDEN (1<<0)
275#define SADTCS_TDIE (1<<1)
276#define SADTCS_TDBDA (1<<3)
277#define SADTCS_TDSTA (1<<4)
278#define SADTCS_TDBDB (1<<5)
279#define SADTCS_TDSTB (1<<6)
280#define SADTCS_TBIU (1<<7)
281
282#define SADRCS_RDEN (1<<0)
283#define SADRCS_RDIE (1<<1)
284#define SADRCS_RDBDA (1<<3)
285#define SADRCS_RDSTA (1<<4)
286#define SADRCS_RDBDB (1<<5)
287#define SADRCS_RDSTB (1<<6)
288#define SADRCS_RBIU (1<<7)
289
290#define SAD_CS_DEN (1<<0)
291#define SAD_CS_DIE (1<<1) /* Not functional on metal 1 */
292#define SAD_CS_DBDA (1<<3) /* Not functional on metal 1 */
293#define SAD_CS_DSTA (1<<4)
294#define SAD_CS_DBDB (1<<5) /* Not functional on metal 1 */
295#define SAD_CS_DSTB (1<<6)
296#define SAD_CS_BIU (1<<7) /* Not functional on metal 1 */
297
298#define SAITR_TFS (1<<0)
299#define SAITR_RFS (1<<1)
300#define SAITR_TUR (1<<2)
301#define SAITR_ROR (1<<3)
302#define SAITR_CADT (1<<4)
303#define SAITR_SADR (1<<5)
304#define SAITR_RSTO (1<<6)
305#define SAITR_TDBDA (1<<8)
306#define SAITR_TDBDB (1<<9)
307#define SAITR_RDBDA (1<<10)
308#define SAITR_RDBDB (1<<11)
309
310#endif /* !CONFIG_ARCH_PXA */
311
312/*
313 * General-Purpose I/O Interface
314 *
315 * Registers
316 * PA_DDR GPIO Block A Data Direction
317 * PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write)
318 * PA_SDR GPIO Block A Sleep Direction
319 * PA_SSR GPIO Block A Sleep State
320 * PB_DDR GPIO Block B Data Direction
321 * PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write)
322 * PB_SDR GPIO Block B Sleep Direction
323 * PB_SSR GPIO Block B Sleep State
324 * PC_DDR GPIO Block C Data Direction
325 * PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write)
326 * PC_SDR GPIO Block C Sleep Direction
327 * PC_SSR GPIO Block C Sleep State
328 */
329
330#define _PA_DDR _SA1111( 0x1000 )
331#define _PA_DRR _SA1111( 0x1004 )
332#define _PA_DWR _SA1111( 0x1004 )
333#define _PA_SDR _SA1111( 0x1008 )
334#define _PA_SSR _SA1111( 0x100c )
335#define _PB_DDR _SA1111( 0x1010 )
336#define _PB_DRR _SA1111( 0x1014 )
337#define _PB_DWR _SA1111( 0x1014 )
338#define _PB_SDR _SA1111( 0x1018 )
339#define _PB_SSR _SA1111( 0x101c )
340#define _PC_DDR _SA1111( 0x1020 )
341#define _PC_DRR _SA1111( 0x1024 )
342#define _PC_DWR _SA1111( 0x1024 )
343#define _PC_SDR _SA1111( 0x1028 )
344#define _PC_SSR _SA1111( 0x102c )
345
346#define SA1111_GPIO 0x1000
347
348#define SA1111_GPIO_PADDR (0x000)
349#define SA1111_GPIO_PADRR (0x004)
350#define SA1111_GPIO_PADWR (0x004)
351#define SA1111_GPIO_PASDR (0x008)
352#define SA1111_GPIO_PASSR (0x00c)
353#define SA1111_GPIO_PBDDR (0x010)
354#define SA1111_GPIO_PBDRR (0x014)
355#define SA1111_GPIO_PBDWR (0x014)
356#define SA1111_GPIO_PBSDR (0x018)
357#define SA1111_GPIO_PBSSR (0x01c)
358#define SA1111_GPIO_PCDDR (0x020)
359#define SA1111_GPIO_PCDRR (0x024)
360#define SA1111_GPIO_PCDWR (0x024)
361#define SA1111_GPIO_PCSDR (0x028)
362#define SA1111_GPIO_PCSSR (0x02c)
363
364#define GPIO_A0 (1 << 0)
365#define GPIO_A1 (1 << 1)
366#define GPIO_A2 (1 << 2)
367#define GPIO_A3 (1 << 3)
368
369#define GPIO_B0 (1 << 8)
370#define GPIO_B1 (1 << 9)
371#define GPIO_B2 (1 << 10)
372#define GPIO_B3 (1 << 11)
373#define GPIO_B4 (1 << 12)
374#define GPIO_B5 (1 << 13)
375#define GPIO_B6 (1 << 14)
376#define GPIO_B7 (1 << 15)
377
378#define GPIO_C0 (1 << 16)
379#define GPIO_C1 (1 << 17)
380#define GPIO_C2 (1 << 18)
381#define GPIO_C3 (1 << 19)
382#define GPIO_C4 (1 << 20)
383#define GPIO_C5 (1 << 21)
384#define GPIO_C6 (1 << 22)
385#define GPIO_C7 (1 << 23)
386
387/*
388 * Interrupt Controller
389 *
390 * Registers
391 * INTTEST0 Test register 0
392 * INTTEST1 Test register 1
393 * INTEN0 Interrupt Enable register 0
394 * INTEN1 Interrupt Enable register 1
395 * INTPOL0 Interrupt Polarity selection 0
396 * INTPOL1 Interrupt Polarity selection 1
397 * INTTSTSEL Interrupt source selection
398 * INTSTATCLR0 Interrupt Status/Clear 0
399 * INTSTATCLR1 Interrupt Status/Clear 1
400 * INTSET0 Interrupt source set 0
401 * INTSET1 Interrupt source set 1
402 * WAKE_EN0 Wake-up source enable 0
403 * WAKE_EN1 Wake-up source enable 1
404 * WAKE_POL0 Wake-up polarity selection 0
405 * WAKE_POL1 Wake-up polarity selection 1
406 */
407#define SA1111_INTC 0x1600
408
409/*
410 * These are offsets from the above base.
411 */
412#define SA1111_INTTEST0 0x0000
413#define SA1111_INTTEST1 0x0004
414#define SA1111_INTEN0 0x0008
415#define SA1111_INTEN1 0x000c
416#define SA1111_INTPOL0 0x0010
417#define SA1111_INTPOL1 0x0014
418#define SA1111_INTTSTSEL 0x0018
419#define SA1111_INTSTATCLR0 0x001c
420#define SA1111_INTSTATCLR1 0x0020
421#define SA1111_INTSET0 0x0024
422#define SA1111_INTSET1 0x0028
423#define SA1111_WAKEEN0 0x002c
424#define SA1111_WAKEEN1 0x0030
425#define SA1111_WAKEPOL0 0x0034
426#define SA1111_WAKEPOL1 0x0038
427
428/*
429 * PS/2 Trackpad and Mouse Interfaces
430 *
431 * Registers
432 * PS2CR Control Register
433 * PS2STAT Status Register
434 * PS2DATA Transmit/Receive Data register
435 * PS2CLKDIV Clock Division Register
436 * PS2PRECNT Clock Precount Register
437 * PS2TEST1 Test register 1
438 * PS2TEST2 Test register 2
439 * PS2TEST3 Test register 3
440 * PS2TEST4 Test register 4
441 */
442
443#define SA1111_KBD 0x0a00
444#define SA1111_MSE 0x0c00
445
446/*
447 * These are offsets from the above bases.
448 */
449#define SA1111_PS2CR 0x0000
450#define SA1111_PS2STAT 0x0004
451#define SA1111_PS2DATA 0x0008
452#define SA1111_PS2CLKDIV 0x000c
453#define SA1111_PS2PRECNT 0x0010
454
455#define PS2CR_ENA 0x08
456#define PS2CR_FKD 0x02
457#define PS2CR_FKC 0x01
458
459#define PS2STAT_STP 0x0100
460#define PS2STAT_TXE 0x0080
461#define PS2STAT_TXB 0x0040
462#define PS2STAT_RXF 0x0020
463#define PS2STAT_RXB 0x0010
464#define PS2STAT_ENA 0x0008
465#define PS2STAT_RXP 0x0004
466#define PS2STAT_KBD 0x0002
467#define PS2STAT_KBC 0x0001
468
469/*
470 * PCMCIA Interface
471 *
472 * Registers
473 * PCSR Status Register
474 * PCCR Control Register
475 * PCSSR Sleep State Register
476 */
477
478#define SA1111_PCMCIA 0x1600
479
480/*
481 * These are offsets from the above base.
482 */
483#define SA1111_PCCR 0x0000
484#define SA1111_PCSSR 0x0004
485#define SA1111_PCSR 0x0008
486
487#define PCSR_S0_READY (1<<0)
488#define PCSR_S1_READY (1<<1)
489#define PCSR_S0_DETECT (1<<2)
490#define PCSR_S1_DETECT (1<<3)
491#define PCSR_S0_VS1 (1<<4)
492#define PCSR_S0_VS2 (1<<5)
493#define PCSR_S1_VS1 (1<<6)
494#define PCSR_S1_VS2 (1<<7)
495#define PCSR_S0_WP (1<<8)
496#define PCSR_S1_WP (1<<9)
497#define PCSR_S0_BVD1 (1<<10)
498#define PCSR_S0_BVD2 (1<<11)
499#define PCSR_S1_BVD1 (1<<12)
500#define PCSR_S1_BVD2 (1<<13)
501
502#define PCCR_S0_RST (1<<0)
503#define PCCR_S1_RST (1<<1)
504#define PCCR_S0_FLT (1<<2)
505#define PCCR_S1_FLT (1<<3)
506#define PCCR_S0_PWAITEN (1<<4)
507#define PCCR_S1_PWAITEN (1<<5)
508#define PCCR_S0_PSE (1<<6)
509#define PCCR_S1_PSE (1<<7)
510
511#define PCSSR_S0_SLEEP (1<<0)
512#define PCSSR_S1_SLEEP (1<<1)
513
514
515
516
517extern struct bus_type sa1111_bus_type;
518
519#define SA1111_DEVID_SBI 0
520#define SA1111_DEVID_SK 1
521#define SA1111_DEVID_USB 2
522#define SA1111_DEVID_SAC 3
523#define SA1111_DEVID_SSP 4
524#define SA1111_DEVID_PS2 5
525#define SA1111_DEVID_GPIO 6
526#define SA1111_DEVID_INT 7
527#define SA1111_DEVID_PCMCIA 8
528
529struct sa1111_dev {
530 struct device dev;
531 unsigned int devid;
532 struct resource res;
533 void __iomem *mapbase;
534 unsigned int skpcr_mask;
535 unsigned int irq[6];
536 u64 dma_mask;
537};
538
539#define SA1111_DEV(_d) container_of((_d), struct sa1111_dev, dev)
540
541#define sa1111_get_drvdata(d) dev_get_drvdata(&(d)->dev)
542#define sa1111_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
543
544struct sa1111_driver {
545 struct device_driver drv;
546 unsigned int devid;
547 int (*probe)(struct sa1111_dev *);
548 int (*remove)(struct sa1111_dev *);
549 int (*suspend)(struct sa1111_dev *, pm_message_t);
550 int (*resume)(struct sa1111_dev *);
551};
552
553#define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv)
554
555#define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name)
556
557/*
558 * These frob the SKPCR register.
559 */
560void sa1111_enable_device(struct sa1111_dev *);
561void sa1111_disable_device(struct sa1111_dev *);
562
563unsigned int sa1111_pll_clock(struct sa1111_dev *);
564
565#define SA1111_AUDIO_ACLINK 0
566#define SA1111_AUDIO_I2S 1
567
568void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode);
569int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate);
570int sa1111_get_audio_rate(struct sa1111_dev *sadev);
571
572int sa1111_check_dma_bug(dma_addr_t addr);
573
574int sa1111_driver_register(struct sa1111_driver *);
575void sa1111_driver_unregister(struct sa1111_driver *);
576
577void sa1111_set_io_dir(struct sa1111_dev *sadev, unsigned int bits, unsigned int dir, unsigned int sleep_dir);
578void sa1111_set_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v);
579void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v);
580
581#endif /* _ASM_ARCH_SA1111 */
diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h
new file mode 100644
index 000000000000..dfb8330599f9
--- /dev/null
+++ b/arch/arm/include/asm/hardware/scoop.h
@@ -0,0 +1,69 @@
1/*
2 * Definitions for the SCOOP interface found on various Sharp PDAs
3 *
4 * Copyright (c) 2004 Richard Purdie
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#define SCOOP_MCR 0x00
13#define SCOOP_CDR 0x04
14#define SCOOP_CSR 0x08
15#define SCOOP_CPR 0x0C
16#define SCOOP_CCR 0x10
17#define SCOOP_IRR 0x14
18#define SCOOP_IRM 0x14
19#define SCOOP_IMR 0x18
20#define SCOOP_ISR 0x1C
21#define SCOOP_GPCR 0x20
22#define SCOOP_GPWR 0x24
23#define SCOOP_GPRR 0x28
24
25#define SCOOP_GPCR_PA22 ( 1 << 12 )
26#define SCOOP_GPCR_PA21 ( 1 << 11 )
27#define SCOOP_GPCR_PA20 ( 1 << 10 )
28#define SCOOP_GPCR_PA19 ( 1 << 9 )
29#define SCOOP_GPCR_PA18 ( 1 << 8 )
30#define SCOOP_GPCR_PA17 ( 1 << 7 )
31#define SCOOP_GPCR_PA16 ( 1 << 6 )
32#define SCOOP_GPCR_PA15 ( 1 << 5 )
33#define SCOOP_GPCR_PA14 ( 1 << 4 )
34#define SCOOP_GPCR_PA13 ( 1 << 3 )
35#define SCOOP_GPCR_PA12 ( 1 << 2 )
36#define SCOOP_GPCR_PA11 ( 1 << 1 )
37
38struct scoop_config {
39 unsigned short io_out;
40 unsigned short io_dir;
41 unsigned short suspend_clr;
42 unsigned short suspend_set;
43 int gpio_base;
44};
45
46/* Structure for linking scoop devices to PCMCIA sockets */
47struct scoop_pcmcia_dev {
48 struct device *dev; /* Pointer to this socket's scoop device */
49 int irq; /* irq for socket */
50 int cd_irq;
51 const char *cd_irq_str;
52 unsigned char keep_vs;
53 unsigned char keep_rd;
54};
55
56struct scoop_pcmcia_config {
57 struct scoop_pcmcia_dev *devs;
58 int num_devs;
59 void (*pcmcia_init)(void);
60 void (*power_ctrl)(struct device *scoop, unsigned short cpr, int nr);
61};
62
63extern struct scoop_pcmcia_config *platform_scoop_config;
64
65void reset_scoop(struct device *dev);
66unsigned short __deprecated set_scoop_gpio(struct device *dev, unsigned short bit);
67unsigned short __deprecated reset_scoop_gpio(struct device *dev, unsigned short bit);
68unsigned short read_scoop_reg(struct device *dev, unsigned short reg);
69void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data);
diff --git a/arch/arm/include/asm/hardware/sharpsl_pm.h b/arch/arm/include/asm/hardware/sharpsl_pm.h
new file mode 100644
index 000000000000..2d00db22b981
--- /dev/null
+++ b/arch/arm/include/asm/hardware/sharpsl_pm.h
@@ -0,0 +1,106 @@
1/*
2 * SharpSL Battery/PM Driver
3 *
4 * Copyright (c) 2004-2005 Richard Purdie
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/interrupt.h>
13
14struct sharpsl_charger_machinfo {
15 void (*init)(void);
16 void (*exit)(void);
17 int gpio_acin;
18 int gpio_batfull;
19 int batfull_irq;
20 int gpio_batlock;
21 int gpio_fatal;
22 void (*discharge)(int);
23 void (*discharge1)(int);
24 void (*charge)(int);
25 void (*measure_temp)(int);
26 void (*presuspend)(void);
27 void (*postsuspend)(void);
28 void (*earlyresume)(void);
29 unsigned long (*read_devdata)(int);
30#define SHARPSL_BATT_VOLT 1
31#define SHARPSL_BATT_TEMP 2
32#define SHARPSL_ACIN_VOLT 3
33#define SHARPSL_STATUS_ACIN 4
34#define SHARPSL_STATUS_LOCK 5
35#define SHARPSL_STATUS_CHRGFULL 6
36#define SHARPSL_STATUS_FATAL 7
37 unsigned long (*charger_wakeup)(void);
38 int (*should_wakeup)(unsigned int resume_on_alarm);
39 void (*backlight_limit)(int);
40 int (*backlight_get_status) (void);
41 int charge_on_volt;
42 int charge_on_temp;
43 int charge_acin_high;
44 int charge_acin_low;
45 int fatal_acin_volt;
46 int fatal_noacin_volt;
47 int bat_levels;
48 struct battery_thresh *bat_levels_noac;
49 struct battery_thresh *bat_levels_acin;
50 struct battery_thresh *bat_levels_noac_bl;
51 struct battery_thresh *bat_levels_acin_bl;
52 int status_high_acin;
53 int status_low_acin;
54 int status_high_noac;
55 int status_low_noac;
56};
57
58struct battery_thresh {
59 int voltage;
60 int percentage;
61};
62
63struct battery_stat {
64 int ac_status; /* APM AC Present/Not Present */
65 int mainbat_status; /* APM Main Battery Status */
66 int mainbat_percent; /* Main Battery Percentage Charge */
67 int mainbat_voltage; /* Main Battery Voltage */
68};
69
70struct sharpsl_pm_status {
71 struct device *dev;
72 struct timer_list ac_timer;
73 struct timer_list chrg_full_timer;
74
75 int charge_mode;
76#define CHRG_ERROR (-1)
77#define CHRG_OFF (0)
78#define CHRG_ON (1)
79#define CHRG_DONE (2)
80
81 unsigned int flags;
82#define SHARPSL_SUSPENDED (1 << 0) /* Device is Suspended */
83#define SHARPSL_ALARM_ACTIVE (1 << 1) /* Alarm is for charging event (not user) */
84#define SHARPSL_BL_LIMIT (1 << 2) /* Backlight Intensity Limited */
85#define SHARPSL_APM_QUEUED (1 << 3) /* APM Event Queued */
86#define SHARPSL_DO_OFFLINE_CHRG (1 << 4) /* Trigger the offline charger */
87
88 int full_count;
89 unsigned long charge_start_time;
90 struct sharpsl_charger_machinfo *machinfo;
91 struct battery_stat battstat;
92};
93
94extern struct sharpsl_pm_status sharpsl_pm;
95
96
97#define SHARPSL_LED_ERROR 2
98#define SHARPSL_LED_ON 1
99#define SHARPSL_LED_OFF 0
100
101void sharpsl_battery_kick(void);
102void sharpsl_pm_led(int val);
103irqreturn_t sharpsl_ac_isr(int irq, void *dev_id);
104irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id);
105irqreturn_t sharpsl_fatal_isr(int irq, void *dev_id);
106
diff --git a/arch/arm/include/asm/hardware/ssp.h b/arch/arm/include/asm/hardware/ssp.h
new file mode 100644
index 000000000000..3b42e181997c
--- /dev/null
+++ b/arch/arm/include/asm/hardware/ssp.h
@@ -0,0 +1,28 @@
1/*
2 * ssp.h
3 *
4 * Copyright (C) 2003 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef SSP_H
11#define SSP_H
12
13struct ssp_state {
14 unsigned int cr0;
15 unsigned int cr1;
16};
17
18int ssp_write_word(u16 data);
19int ssp_read_word(u16 *data);
20int ssp_flush(void);
21void ssp_enable(void);
22void ssp_disable(void);
23void ssp_save_state(struct ssp_state *ssp);
24void ssp_restore_state(struct ssp_state *ssp);
25int ssp_init(void);
26void ssp_exit(void);
27
28#endif
diff --git a/arch/arm/include/asm/hardware/uengine.h b/arch/arm/include/asm/hardware/uengine.h
new file mode 100644
index 000000000000..b442d65c6593
--- /dev/null
+++ b/arch/arm/include/asm/hardware/uengine.h
@@ -0,0 +1,62 @@
1/*
2 * Generic library functions for the microengines found on the Intel
3 * IXP2000 series of network processors.
4 *
5 * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
6 * Dedicated to Marija Kulikova.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU Lesser General Public License as
10 * published by the Free Software Foundation; either version 2.1 of the
11 * License, or (at your option) any later version.
12 */
13
14#ifndef __IXP2000_UENGINE_H
15#define __IXP2000_UENGINE_H
16
17extern u32 ixp2000_uengine_mask;
18
19struct ixp2000_uengine_code
20{
21 u32 cpu_model_bitmask;
22 u8 cpu_min_revision;
23 u8 cpu_max_revision;
24
25 u32 uengine_parameters;
26
27 struct ixp2000_reg_value {
28 int reg;
29 u32 value;
30 } *initial_reg_values;
31
32 int num_insns;
33 u8 *insns;
34};
35
36u32 ixp2000_uengine_csr_read(int uengine, int offset);
37void ixp2000_uengine_csr_write(int uengine, int offset, u32 value);
38void ixp2000_uengine_reset(u32 uengine_mask);
39void ixp2000_uengine_set_mode(int uengine, u32 mode);
40void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns);
41void ixp2000_uengine_init_context(int uengine, int context, int pc);
42void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask);
43void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask);
44int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c);
45
46#define IXP2000_UENGINE_8_CONTEXTS 0x00000000
47#define IXP2000_UENGINE_4_CONTEXTS 0x80000000
48#define IXP2000_UENGINE_PRN_UPDATE_EVERY 0x40000000
49#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS 0x00000000
50#define IXP2000_UENGINE_NN_FROM_SELF 0x00100000
51#define IXP2000_UENGINE_NN_FROM_PREVIOUS 0x00000000
52#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3 0x000c0000
53#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2 0x00080000
54#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1 0x00040000
55#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0 0x00000000
56#define IXP2000_UENGINE_LM_ADDR1_GLOBAL 0x00020000
57#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT 0x00000000
58#define IXP2000_UENGINE_LM_ADDR0_GLOBAL 0x00010000
59#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT 0x00000000
60
61
62#endif
diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
new file mode 100644
index 000000000000..263f2c362a30
--- /dev/null
+++ b/arch/arm/include/asm/hardware/vic.h
@@ -0,0 +1,45 @@
1/*
2 * arch/arm/include/asm/hardware/vic.h
3 *
4 * Copyright (c) ARM Limited 2003. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARM_HARDWARE_VIC_H
21#define __ASM_ARM_HARDWARE_VIC_H
22
23#define VIC_IRQ_STATUS 0x00
24#define VIC_FIQ_STATUS 0x04
25#define VIC_RAW_STATUS 0x08
26#define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
27#define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */
28#define VIC_INT_ENABLE_CLEAR 0x14
29#define VIC_INT_SOFT 0x18
30#define VIC_INT_SOFT_CLEAR 0x1c
31#define VIC_PROTECT 0x20
32#define VIC_VECT_ADDR 0x30
33#define VIC_DEF_VECT_ADDR 0x34
34
35#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */
36#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */
37#define VIC_ITCR 0x300 /* VIC test control register */
38
39#define VIC_VECT_CNTL_ENABLE (1 << 5)
40
41#ifndef __ASSEMBLY__
42void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources);
43#endif
44
45#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 08:40:43 -0500