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-rw-r--r--arch/arm/include/asm/cache.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 66c160b8547f..9d6122096fbe 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -14,7 +14,7 @@
14 * cache before the transfer is done, causing old data to be seen by 14 * cache before the transfer is done, causing old data to be seen by
15 * the CPU. 15 * the CPU.
16 */ 16 */
17#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES 17#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
18 18
19/* 19/*
20 * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. 20 * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers.