diff options
Diffstat (limited to 'arch/arm/common')
-rw-r--r-- | arch/arm/common/gic.c | 26 | ||||
-rw-r--r-- | arch/arm/common/pl330.c | 2 | ||||
-rw-r--r-- | arch/arm/common/sa1111.c | 9 | ||||
-rw-r--r-- | arch/arm/common/scoop.c | 2 | ||||
-rw-r--r-- | arch/arm/common/timer-sp.c | 9 | ||||
-rw-r--r-- | arch/arm/common/vic.c | 4 |
6 files changed, 34 insertions, 18 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 016c1aeb847c..a8fc6b237592 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c | |||
@@ -37,7 +37,7 @@ | |||
37 | #include <asm/mach/irq.h> | 37 | #include <asm/mach/irq.h> |
38 | #include <asm/hardware/gic.h> | 38 | #include <asm/hardware/gic.h> |
39 | 39 | ||
40 | static DEFINE_SPINLOCK(irq_controller_lock); | 40 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
41 | 41 | ||
42 | /* Address of GIC 0 CPU interface */ | 42 | /* Address of GIC 0 CPU interface */ |
43 | void __iomem *gic_cpu_base_addr __read_mostly; | 43 | void __iomem *gic_cpu_base_addr __read_mostly; |
@@ -86,30 +86,30 @@ static void gic_mask_irq(struct irq_data *d) | |||
86 | { | 86 | { |
87 | u32 mask = 1 << (d->irq % 32); | 87 | u32 mask = 1 << (d->irq % 32); |
88 | 88 | ||
89 | spin_lock(&irq_controller_lock); | 89 | raw_spin_lock(&irq_controller_lock); |
90 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); | 90 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); |
91 | if (gic_arch_extn.irq_mask) | 91 | if (gic_arch_extn.irq_mask) |
92 | gic_arch_extn.irq_mask(d); | 92 | gic_arch_extn.irq_mask(d); |
93 | spin_unlock(&irq_controller_lock); | 93 | raw_spin_unlock(&irq_controller_lock); |
94 | } | 94 | } |
95 | 95 | ||
96 | static void gic_unmask_irq(struct irq_data *d) | 96 | static void gic_unmask_irq(struct irq_data *d) |
97 | { | 97 | { |
98 | u32 mask = 1 << (d->irq % 32); | 98 | u32 mask = 1 << (d->irq % 32); |
99 | 99 | ||
100 | spin_lock(&irq_controller_lock); | 100 | raw_spin_lock(&irq_controller_lock); |
101 | if (gic_arch_extn.irq_unmask) | 101 | if (gic_arch_extn.irq_unmask) |
102 | gic_arch_extn.irq_unmask(d); | 102 | gic_arch_extn.irq_unmask(d); |
103 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); | 103 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); |
104 | spin_unlock(&irq_controller_lock); | 104 | raw_spin_unlock(&irq_controller_lock); |
105 | } | 105 | } |
106 | 106 | ||
107 | static void gic_eoi_irq(struct irq_data *d) | 107 | static void gic_eoi_irq(struct irq_data *d) |
108 | { | 108 | { |
109 | if (gic_arch_extn.irq_eoi) { | 109 | if (gic_arch_extn.irq_eoi) { |
110 | spin_lock(&irq_controller_lock); | 110 | raw_spin_lock(&irq_controller_lock); |
111 | gic_arch_extn.irq_eoi(d); | 111 | gic_arch_extn.irq_eoi(d); |
112 | spin_unlock(&irq_controller_lock); | 112 | raw_spin_unlock(&irq_controller_lock); |
113 | } | 113 | } |
114 | 114 | ||
115 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); | 115 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
@@ -133,7 +133,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) | |||
133 | if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) | 133 | if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) |
134 | return -EINVAL; | 134 | return -EINVAL; |
135 | 135 | ||
136 | spin_lock(&irq_controller_lock); | 136 | raw_spin_lock(&irq_controller_lock); |
137 | 137 | ||
138 | if (gic_arch_extn.irq_set_type) | 138 | if (gic_arch_extn.irq_set_type) |
139 | gic_arch_extn.irq_set_type(d, type); | 139 | gic_arch_extn.irq_set_type(d, type); |
@@ -158,7 +158,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) | |||
158 | if (enabled) | 158 | if (enabled) |
159 | writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); | 159 | writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); |
160 | 160 | ||
161 | spin_unlock(&irq_controller_lock); | 161 | raw_spin_unlock(&irq_controller_lock); |
162 | 162 | ||
163 | return 0; | 163 | return 0; |
164 | } | 164 | } |
@@ -186,10 +186,10 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |||
186 | mask = 0xff << shift; | 186 | mask = 0xff << shift; |
187 | bit = 1 << (cpu_logical_map(cpu) + shift); | 187 | bit = 1 << (cpu_logical_map(cpu) + shift); |
188 | 188 | ||
189 | spin_lock(&irq_controller_lock); | 189 | raw_spin_lock(&irq_controller_lock); |
190 | val = readl_relaxed(reg) & ~mask; | 190 | val = readl_relaxed(reg) & ~mask; |
191 | writel_relaxed(val | bit, reg); | 191 | writel_relaxed(val | bit, reg); |
192 | spin_unlock(&irq_controller_lock); | 192 | raw_spin_unlock(&irq_controller_lock); |
193 | 193 | ||
194 | return IRQ_SET_MASK_OK; | 194 | return IRQ_SET_MASK_OK; |
195 | } | 195 | } |
@@ -219,9 +219,9 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) | |||
219 | 219 | ||
220 | chained_irq_enter(chip, desc); | 220 | chained_irq_enter(chip, desc); |
221 | 221 | ||
222 | spin_lock(&irq_controller_lock); | 222 | raw_spin_lock(&irq_controller_lock); |
223 | status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK); | 223 | status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK); |
224 | spin_unlock(&irq_controller_lock); | 224 | raw_spin_unlock(&irq_controller_lock); |
225 | 225 | ||
226 | gic_irq = (status & 0x3ff); | 226 | gic_irq = (status & 0x3ff); |
227 | if (gic_irq == 1023) | 227 | if (gic_irq == 1023) |
diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c index 97912fa48782..7129cfbdacd6 100644 --- a/arch/arm/common/pl330.c +++ b/arch/arm/common/pl330.c | |||
@@ -1546,7 +1546,7 @@ int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op) | |||
1546 | 1546 | ||
1547 | /* Start the next */ | 1547 | /* Start the next */ |
1548 | case PL330_OP_START: | 1548 | case PL330_OP_START: |
1549 | if (!_start(thrd)) | 1549 | if (!_thrd_active(thrd) && !_start(thrd)) |
1550 | ret = -EIO; | 1550 | ret = -EIO; |
1551 | break; | 1551 | break; |
1552 | 1552 | ||
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 0569de6acfba..61691cdbdcf2 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c | |||
@@ -718,6 +718,10 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) | |||
718 | goto err_free; | 718 | goto err_free; |
719 | } | 719 | } |
720 | 720 | ||
721 | ret = clk_prepare(sachip->clk); | ||
722 | if (ret) | ||
723 | goto err_clkput; | ||
724 | |||
721 | spin_lock_init(&sachip->lock); | 725 | spin_lock_init(&sachip->lock); |
722 | 726 | ||
723 | sachip->dev = me; | 727 | sachip->dev = me; |
@@ -733,7 +737,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) | |||
733 | sachip->base = ioremap(mem->start, PAGE_SIZE * 2); | 737 | sachip->base = ioremap(mem->start, PAGE_SIZE * 2); |
734 | if (!sachip->base) { | 738 | if (!sachip->base) { |
735 | ret = -ENOMEM; | 739 | ret = -ENOMEM; |
736 | goto err_clkput; | 740 | goto err_clk_unprep; |
737 | } | 741 | } |
738 | 742 | ||
739 | /* | 743 | /* |
@@ -809,6 +813,8 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) | |||
809 | 813 | ||
810 | err_unmap: | 814 | err_unmap: |
811 | iounmap(sachip->base); | 815 | iounmap(sachip->base); |
816 | err_clk_unprep: | ||
817 | clk_unprepare(sachip->clk); | ||
812 | err_clkput: | 818 | err_clkput: |
813 | clk_put(sachip->clk); | 819 | clk_put(sachip->clk); |
814 | err_free: | 820 | err_free: |
@@ -835,6 +841,7 @@ static void __sa1111_remove(struct sa1111 *sachip) | |||
835 | sa1111_writel(0, irqbase + SA1111_WAKEEN1); | 841 | sa1111_writel(0, irqbase + SA1111_WAKEEN1); |
836 | 842 | ||
837 | clk_disable(sachip->clk); | 843 | clk_disable(sachip->clk); |
844 | clk_unprepare(sachip->clk); | ||
838 | 845 | ||
839 | if (sachip->irq != NO_IRQ) { | 846 | if (sachip->irq != NO_IRQ) { |
840 | irq_set_chained_handler(sachip->irq, NULL); | 847 | irq_set_chained_handler(sachip->irq, NULL); |
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c index a07b0e763a80..1cde34a080d7 100644 --- a/arch/arm/common/scoop.c +++ b/arch/arm/common/scoop.c | |||
@@ -12,11 +12,11 @@ | |||
12 | */ | 12 | */ |
13 | 13 | ||
14 | #include <linux/device.h> | 14 | #include <linux/device.h> |
15 | #include <linux/gpio.h> | ||
15 | #include <linux/string.h> | 16 | #include <linux/string.h> |
16 | #include <linux/slab.h> | 17 | #include <linux/slab.h> |
17 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
18 | #include <linux/io.h> | 19 | #include <linux/io.h> |
19 | #include <asm/gpio.h> | ||
20 | #include <asm/hardware/scoop.h> | 20 | #include <asm/hardware/scoop.h> |
21 | 21 | ||
22 | /* PCMCIA to Scoop linkage | 22 | /* PCMCIA to Scoop linkage |
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c index 41df47875122..2393b5bc96fa 100644 --- a/arch/arm/common/timer-sp.c +++ b/arch/arm/common/timer-sp.c | |||
@@ -41,9 +41,17 @@ static long __init sp804_get_clock_rate(const char *name) | |||
41 | return PTR_ERR(clk); | 41 | return PTR_ERR(clk); |
42 | } | 42 | } |
43 | 43 | ||
44 | err = clk_prepare(clk); | ||
45 | if (err) { | ||
46 | pr_err("sp804: %s clock failed to prepare: %d\n", name, err); | ||
47 | clk_put(clk); | ||
48 | return err; | ||
49 | } | ||
50 | |||
44 | err = clk_enable(clk); | 51 | err = clk_enable(clk); |
45 | if (err) { | 52 | if (err) { |
46 | pr_err("sp804: %s clock failed to enable: %d\n", name, err); | 53 | pr_err("sp804: %s clock failed to enable: %d\n", name, err); |
54 | clk_unprepare(clk); | ||
47 | clk_put(clk); | 55 | clk_put(clk); |
48 | return err; | 56 | return err; |
49 | } | 57 | } |
@@ -52,6 +60,7 @@ static long __init sp804_get_clock_rate(const char *name) | |||
52 | if (rate < 0) { | 60 | if (rate < 0) { |
53 | pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate); | 61 | pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate); |
54 | clk_disable(clk); | 62 | clk_disable(clk); |
63 | clk_unprepare(clk); | ||
55 | clk_put(clk); | 64 | clk_put(clk); |
56 | } | 65 | } |
57 | 66 | ||
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index 7aa4262ada7a..01f18a421b17 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c | |||
@@ -259,7 +259,6 @@ static void __init vic_disable(void __iomem *base) | |||
259 | writel(0, base + VIC_INT_SELECT); | 259 | writel(0, base + VIC_INT_SELECT); |
260 | writel(0, base + VIC_INT_ENABLE); | 260 | writel(0, base + VIC_INT_ENABLE); |
261 | writel(~0, base + VIC_INT_ENABLE_CLEAR); | 261 | writel(~0, base + VIC_INT_ENABLE_CLEAR); |
262 | writel(0, base + VIC_IRQ_STATUS); | ||
263 | writel(0, base + VIC_ITCR); | 262 | writel(0, base + VIC_ITCR); |
264 | writel(~0, base + VIC_INT_SOFT_CLEAR); | 263 | writel(~0, base + VIC_INT_SOFT_CLEAR); |
265 | } | 264 | } |
@@ -347,7 +346,8 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, | |||
347 | 346 | ||
348 | /* Identify which VIC cell this one is, by reading the ID */ | 347 | /* Identify which VIC cell this one is, by reading the ID */ |
349 | for (i = 0; i < 4; i++) { | 348 | for (i = 0; i < 4; i++) { |
350 | u32 addr = ((u32)base & PAGE_MASK) + 0xfe0 + (i * 4); | 349 | void __iomem *addr; |
350 | addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4); | ||
351 | cellid |= (readl(addr) & 0xff) << (8 * i); | 351 | cellid |= (readl(addr) & 0xff) << (8 * i); |
352 | } | 352 | } |
353 | vendor = (cellid >> 12) & 0xff; | 353 | vendor = (cellid >> 12) & 0xff; |