7 files changed, 552 insertions, 78 deletions

diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index c81a2ff6b5be..847e3e6356c6 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_SHARP_LOCOMO)	+= locomo.o
 obj-$(CONFIG_SHARP_PARAM)       += sharpsl_param.o
 obj-$(CONFIG_SHARPSL_PM)        += sharpsl_pm.o
 obj-$(CONFIG_SHARP_SCOOP)       += scoop.o
+obj-$(CONFIG_ARCH_IXP2000)      += uengine.o
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index ad6c89a555bb..7971d0dc6892 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -5,7 +5,7 @@
  *  limited DMA windows. These functions utilize bounce buffers to
  *  copy data to/from buffers located outside the DMA region. This
  *  only works for systems in which DMA memory is at the bottom of
- *  RAM and the remainder of memory is at the top an the DMA memory
+ *  RAM, the remainder of memory is at the top and the DMA memory
  *  can be marked as ZONE_DMA. Anything beyond that such as discontigous
  *  DMA windows will require custom implementations that reserve memory
  *  areas at early bootup.
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index d31b1cb7eea0..a7dc1370695b 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -60,7 +60,7 @@ struct locomo {
         unsigned long phys;
         unsigned int irq;
         spinlock_t lock;
-        void *base;
+        void __iomem *base;
 };
 
 struct locomo_dev_info {
@@ -162,7 +162,7 @@ static void locomo_handler(unsigned int irq, struct irqdesc *desc,
 {
         int req, i;
         struct irqdesc *d;
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
 
         /* Acknowledge the parent IRQ */
         desc->chip->ack(irq);
@@ -189,7 +189,7 @@ static void locomo_ack_irq(unsigned int irq)
 
 static void locomo_mask_irq(unsigned int irq)
 {
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
         unsigned int r;
         r = locomo_readl(mapbase + LOCOMO_ICR);
         r &= ~(0x0010 << (irq - LOCOMO_IRQ_START));
@@ -198,7 +198,7 @@ static void locomo_mask_irq(unsigned int irq)
 
 static void locomo_unmask_irq(unsigned int irq)
 {
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
         unsigned int r;
         r = locomo_readl(mapbase + LOCOMO_ICR);
         r |= (0x0010 << (irq - LOCOMO_IRQ_START));
@@ -215,7 +215,7 @@ static void locomo_key_handler(unsigned int irq, struct irqdesc *desc,
                             struct pt_regs *regs)
 {
         struct irqdesc *d;
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
 
         if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) {
                 d = irq_desc + LOCOMO_IRQ_KEY_START;
@@ -225,7 +225,7 @@ static void locomo_key_handler(unsigned int irq, struct irqdesc *desc,
 
 static void locomo_key_ack_irq(unsigned int irq)
 {
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
         unsigned int r;
         r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
         r &= ~(0x0100 << (irq - LOCOMO_IRQ_KEY_START));
@@ -234,7 +234,7 @@ static void locomo_key_ack_irq(unsigned int irq)
 
 static void locomo_key_mask_irq(unsigned int irq)
 {
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
         unsigned int r;
         r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
         r &= ~(0x0010 << (irq - LOCOMO_IRQ_KEY_START));
@@ -243,7 +243,7 @@ static void locomo_key_mask_irq(unsigned int irq)
 
 static void locomo_key_unmask_irq(unsigned int irq)
 {
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
         unsigned int r;
         r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
         r |= (0x0010 << (irq - LOCOMO_IRQ_KEY_START));
@@ -261,7 +261,7 @@ static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc,
 {
         int req, i;
         struct irqdesc *d;
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
 
         req =   locomo_readl(mapbase + LOCOMO_GIR) &
                 locomo_readl(mapbase + LOCOMO_GPD) &
@@ -280,7 +280,7 @@ static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc,
 
 static void locomo_gpio_ack_irq(unsigned int irq)
 {
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
         unsigned int r;
         r = locomo_readl(mapbase + LOCOMO_GWE);
         r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@@ -297,7 +297,7 @@ static void locomo_gpio_ack_irq(unsigned int irq)
 
 static void locomo_gpio_mask_irq(unsigned int irq)
 {
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
         unsigned int r;
         r = locomo_readl(mapbase + LOCOMO_GIE);
         r &= ~(0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@@ -306,7 +306,7 @@ static void locomo_gpio_mask_irq(unsigned int irq)
 
 static void locomo_gpio_unmask_irq(unsigned int irq)
 {
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
         unsigned int r;
         r = locomo_readl(mapbase + LOCOMO_GIE);
         r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@@ -323,7 +323,7 @@ static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc,
                            struct pt_regs *regs)
 {
         struct irqdesc *d;
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
 
         if (locomo_readl(mapbase + LOCOMO_LTINT) & 0x0001) {
                 d = irq_desc + LOCOMO_IRQ_LT_START;
@@ -333,7 +333,7 @@ static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc,
 
 static void locomo_lt_ack_irq(unsigned int irq)
 {
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
         unsigned int r;
         r = locomo_readl(mapbase + LOCOMO_LTINT);
         r &= ~(0x0100 << (irq - LOCOMO_IRQ_LT_START));
@@ -342,7 +342,7 @@ static void locomo_lt_ack_irq(unsigned int irq)
 
 static void locomo_lt_mask_irq(unsigned int irq)
 {
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
         unsigned int r;
         r = locomo_readl(mapbase + LOCOMO_LTINT);
         r &= ~(0x0010 << (irq - LOCOMO_IRQ_LT_START));
@@ -351,7 +351,7 @@ static void locomo_lt_mask_irq(unsigned int irq)
 
 static void locomo_lt_unmask_irq(unsigned int irq)
 {
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
         unsigned int r;
         r = locomo_readl(mapbase + LOCOMO_LTINT);
         r |= (0x0010 << (irq - LOCOMO_IRQ_LT_START));
@@ -369,7 +369,7 @@ static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc,
 {
         int req, i;
         struct irqdesc *d;
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
 
         req = locomo_readl(mapbase + LOCOMO_SPIIR) & 0x000F;
         if (req) {
@@ -386,7 +386,7 @@ static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc,
 
 static void locomo_spi_ack_irq(unsigned int irq)
 {
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
         unsigned int r;
         r = locomo_readl(mapbase + LOCOMO_SPIWE);
         r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@@ -403,7 +403,7 @@ static void locomo_spi_ack_irq(unsigned int irq)
 
 static void locomo_spi_mask_irq(unsigned int irq)
 {
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
         unsigned int r;
         r = locomo_readl(mapbase + LOCOMO_SPIIE);
         r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@@ -412,7 +412,7 @@ static void locomo_spi_mask_irq(unsigned int irq)
 
 static void locomo_spi_unmask_irq(unsigned int irq)
 {
-        void *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chipdata(irq);
         unsigned int r;
         r = locomo_readl(mapbase + LOCOMO_SPIIE);
         r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@@ -428,7 +428,7 @@ static struct irqchip locomo_spi_chip = {
 static void locomo_setup_irq(struct locomo *lchip)
 {
         int irq;
-        void *irqbase = lchip->base;
+        void __iomem *irqbase = lchip->base;
 
         /*
          * Install handler for IRQ_LOCOMO_HW.
@@ -501,12 +501,11 @@ locomo_init_one_child(struct locomo *lchip, struct locomo_dev_info *info)
         struct locomo_dev *dev;
         int ret;
 
-        dev = kmalloc(sizeof(struct locomo_dev), GFP_KERNEL);
+        dev = kzalloc(sizeof(struct locomo_dev), GFP_KERNEL);
         if (!dev) {
                 ret = -ENOMEM;
                 goto out;
         }
-        memset(dev, 0, sizeof(struct locomo_dev));
 
         strncpy(dev->dev.bus_id,info->name,sizeof(dev->dev.bus_id));
         /*
@@ -664,12 +663,10 @@ __locomo_probe(struct device *me, struct resource *mem, int irq)
         unsigned long r;
         int i, ret = -ENODEV;
 
-        lchip = kmalloc(sizeof(struct locomo), GFP_KERNEL);
+        lchip = kzalloc(sizeof(struct locomo), GFP_KERNEL);
         if (!lchip)
                 return -ENOMEM;
 
-        memset(lchip, 0, sizeof(struct locomo));
-
         spin_lock_init(&lchip->lock);
 
         lchip->dev = me;
@@ -788,6 +785,8 @@ static int locomo_probe(struct platform_device *dev)
         if (!mem)
                 return -EINVAL;
         irq = platform_get_irq(dev, 0);
+        if (irq < 0)
+                return -ENXIO;
 
         return __locomo_probe(&dev->dev, mem, irq);
 }
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index 1475089f9b42..3f68db84e5e6 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -26,6 +26,7 @@
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/dma-mapping.h>
+#include <linux/clk.h>
 
 #include <asm/hardware.h>
 #include <asm/mach-types.h>
@@ -36,10 +37,6 @@
 
 #include <asm/hardware/sa1111.h>
 
-#ifdef CONFIG_ARCH_PXA
-#include <asm/arch/pxa-regs.h>
-#endif
-
 extern void __init sa1110_mb_enable(void);
 
 /*
@@ -51,6 +48,7 @@ extern void __init sa1110_mb_enable(void);
  */
 struct sa1111 {
         struct device   *dev;
+        struct clk      *clk;
         unsigned long   phys;
         int             irq;
         spinlock_t      lock;
@@ -451,19 +449,7 @@ static void sa1111_wake(struct sa1111 *sachip)
 
         spin_lock_irqsave(&sachip->lock, flags);
 
-#ifdef CONFIG_ARCH_SA1100
-        /*
-         * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
-         * (SA-1110 Developer's Manual, section 9.1.2.1)
-         */
-        GAFR |= GPIO_32_768kHz;
-        GPDR |= GPIO_32_768kHz;
-        TUCR = TUCR_3_6864MHz;
-#elif CONFIG_ARCH_PXA
-        pxa_gpio_mode(GPIO11_3_6MHz_MD);
-#else
-#error missing clock setup
-#endif
+        clk_enable(sachip->clk);
 
         /*
          * Turn VCO on, and disable PLL Bypass.
@@ -555,12 +541,11 @@ sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent,
         struct sa1111_dev *dev;
         int ret;
 
-        dev = kmalloc(sizeof(struct sa1111_dev), GFP_KERNEL);
+        dev = kzalloc(sizeof(struct sa1111_dev), GFP_KERNEL);
         if (!dev) {
                 ret = -ENOMEM;
                 goto out;
         }
-        memset(dev, 0, sizeof(struct sa1111_dev));
 
         snprintf(dev->dev.bus_id, sizeof(dev->dev.bus_id),
                  "%4.4lx", info->offset);
@@ -635,11 +620,15 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
         unsigned int has_devs, val;
         int i, ret = -ENODEV;
 
-        sachip = kmalloc(sizeof(struct sa1111), GFP_KERNEL);
+        sachip = kzalloc(sizeof(struct sa1111), GFP_KERNEL);
         if (!sachip)
                 return -ENOMEM;
 
-        memset(sachip, 0, sizeof(struct sa1111));
+        sachip->clk = clk_get(me, "GPIO27_CLK");
+        if (!sachip->clk) {
+                ret = PTR_ERR(sachip->clk);
+                goto err_free;
+        }
 
         spin_lock_init(&sachip->lock);
 
@@ -656,7 +645,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
         sachip->base = ioremap(mem->start, PAGE_SIZE * 2);
         if (!sachip->base) {
                 ret = -ENOMEM;
-                goto out;
+                goto err_clkput;
         }
 
         /*
@@ -666,7 +655,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
         if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
                 printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id);
                 ret = -ENODEV;
-                goto unmap;
+                goto err_unmap;
         }
 
         printk(KERN_INFO "SA1111 Microprocessor Companion Chip: "
@@ -726,9 +715,11 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
 
         return 0;
 
- unmap:
+ err_unmap:
         iounmap(sachip->base);
- out:
+ err_clkput:
+        clk_put(sachip->clk);
+ err_free:
         kfree(sachip);
         return ret;
 }
@@ -751,6 +742,8 @@ static void __sa1111_remove(struct sa1111 *sachip)
         sa1111_writel(0, irqbase + SA1111_WAKEEN0);
         sa1111_writel(0, irqbase + SA1111_WAKEEN1);
 
+        clk_disable(sachip->clk);
+
         if (sachip->irq != NO_IRQ) {
                 set_irq_chained_handler(sachip->irq, NULL);
                 set_irq_data(sachip->irq, NULL);
@@ -759,6 +752,7 @@ static void __sa1111_remove(struct sa1111 *sachip)
         }
 
         iounmap(sachip->base);
+        clk_put(sachip->clk);
         kfree(sachip);
 }
 
@@ -857,6 +851,8 @@ static int sa1111_suspend(struct platform_device *dev, pm_message_t state)
         sa1111_writel(0, sachip->base + SA1111_SKPWM0);
         sa1111_writel(0, sachip->base + SA1111_SKPWM1);
 
+        clk_disable(sachip->clk);
+
         spin_unlock_irqrestore(&sachip->lock, flags);
 
         return 0;
@@ -943,6 +939,8 @@ static int sa1111_probe(struct platform_device *pdev)
         if (!mem)
                 return -EINVAL;
         irq = platform_get_irq(pdev, 0);
+        if (irq < 0)
+                return -ENXIO;
 
         return __sa1111_probe(&pdev->dev, mem, irq);
 }
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c
index a2dfe0b0f1ec..5e830f444c6c 100644
--- a/arch/arm/common/scoop.c
+++ b/arch/arm/common/scoop.c
@@ -132,12 +132,10 @@ int __init scoop_probe(struct platform_device *pdev)
         if (!mem)
                 return -EINVAL;
 
-        devptr = kmalloc(sizeof(struct scoop_dev), GFP_KERNEL);
-
+        devptr = kzalloc(sizeof(struct scoop_dev), GFP_KERNEL);
         if (!devptr)
-                return  -ENOMEM;
+                return -ENOMEM;
 
-        memset(devptr, 0, sizeof(struct scoop_dev));
         spin_lock_init(&devptr->scoop_lock);
 
         inf = pdev->dev.platform_data;
diff --git a/arch/arm/common/uengine.c b/arch/arm/common/uengine.c
new file mode 100644
index 000000000000..a1310b71004e
--- /dev/null
+++ b/arch/arm/common/uengine.c
@@ -0,0 +1,473 @@
+/*
+ * Generic library functions for the microengines found on the Intel
+ * IXP2000 series of network processors.
+ *
+ * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
+ * Dedicated to Marija Kulikova.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as
+ * published by the Free Software Foundation; either version 2.1 of the
+ * License, or (at your option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <asm/hardware.h>
+#include <asm/arch/ixp2000-regs.h>
+#include <asm/hardware/uengine.h>
+#include <asm/io.h>
+
+#define USTORE_ADDRESS                  0x000
+#define USTORE_DATA_LOWER               0x004
+#define USTORE_DATA_UPPER               0x008
+#define CTX_ENABLES                     0x018
+#define CC_ENABLE                       0x01c
+#define CSR_CTX_POINTER                 0x020
+#define INDIRECT_CTX_STS                0x040
+#define ACTIVE_CTX_STS                  0x044
+#define INDIRECT_CTX_SIG_EVENTS         0x048
+#define INDIRECT_CTX_WAKEUP_EVENTS      0x050
+#define NN_PUT                          0x080
+#define NN_GET                          0x084
+#define TIMESTAMP_LOW                   0x0c0
+#define TIMESTAMP_HIGH                  0x0c4
+#define T_INDEX_BYTE_INDEX              0x0f4
+#define LOCAL_CSR_STATUS                0x180
+
+u32 ixp2000_uengine_mask;
+
+static void *ixp2000_uengine_csr_area(int uengine)
+{
+        return ((void *)IXP2000_UENGINE_CSR_VIRT_BASE) + (uengine << 10);
+}
+
+/*
+ * LOCAL_CSR_STATUS=1 after a read or write to a microengine's CSR
+ * space means that the microengine we tried to access was also trying
+ * to access its own CSR space on the same clock cycle as we did.  When
+ * this happens, we lose the arbitration process by default, and the
+ * read or write we tried to do was not actually performed, so we try
+ * again until it succeeds.
+ */
+u32 ixp2000_uengine_csr_read(int uengine, int offset)
+{
+        void *uebase;
+        u32 *local_csr_status;
+        u32 *reg;
+        u32 value;
+
+        uebase = ixp2000_uengine_csr_area(uengine);
+
+        local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
+        reg = (u32 *)(uebase + offset);
+        do {
+                value = ixp2000_reg_read(reg);
+        } while (ixp2000_reg_read(local_csr_status) & 1);
+
+        return value;
+}
+EXPORT_SYMBOL(ixp2000_uengine_csr_read);
+
+void ixp2000_uengine_csr_write(int uengine, int offset, u32 value)
+{
+        void *uebase;
+        u32 *local_csr_status;
+        u32 *reg;
+
+        uebase = ixp2000_uengine_csr_area(uengine);
+
+        local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
+        reg = (u32 *)(uebase + offset);
+        do {
+                ixp2000_reg_write(reg, value);
+        } while (ixp2000_reg_read(local_csr_status) & 1);
+}
+EXPORT_SYMBOL(ixp2000_uengine_csr_write);
+
+void ixp2000_uengine_reset(u32 uengine_mask)
+{
+        ixp2000_reg_wrb(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask);
+        ixp2000_reg_wrb(IXP2000_RESET1, 0);
+}
+EXPORT_SYMBOL(ixp2000_uengine_reset);
+
+void ixp2000_uengine_set_mode(int uengine, u32 mode)
+{
+        /*
+         * CTL_STR_PAR_EN: unconditionally enable parity checking on
+         * control store.
+         */
+        mode |= 0x10000000;
+        ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode);
+
+        /*
+         * Enable updating of condition codes.
+         */
+        ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000);
+
+        /*
+         * Initialise other per-microengine registers.
+         */
+        ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00);
+        ixp2000_uengine_csr_write(uengine, NN_GET, 0x00);
+        ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0);
+}
+EXPORT_SYMBOL(ixp2000_uengine_set_mode);
+
+static int make_even_parity(u32 x)
+{
+        return hweight32(x) & 1;
+}
+
+static void ustore_write(int uengine, u64 insn)
+{
+        /*
+         * Generate even parity for top and bottom 20 bits.
+         */
+        insn |= (u64)make_even_parity((insn >> 20) & 0x000fffff) << 41;
+        insn |= (u64)make_even_parity(insn & 0x000fffff) << 40;
+
+        /*
+         * Write to microstore.  The second write auto-increments
+         * the USTORE_ADDRESS index register.
+         */
+        ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn);
+        ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32));
+}
+
+void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns)
+{
+        int i;
+
+        /*
+         * Start writing to microstore at address 0.
+         */
+        ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000);
+        for (i = 0; i < insns; i++) {
+                u64 insn;
+
+                insn = (((u64)ucode[0]) << 32) |
+                        (((u64)ucode[1]) << 24) |
+                        (((u64)ucode[2]) << 16) |
+                        (((u64)ucode[3]) << 8) |
+                        ((u64)ucode[4]);
+                ucode += 5;
+
+                ustore_write(uengine, insn);
+        }
+
+        /*
+         * Pad with a few NOPs at the end (to avoid the microengine
+         * aborting as it prefetches beyond the last instruction), unless
+         * we run off the end of the instruction store first, at which
+         * point the address register will wrap back to zero.
+         */
+        for (i = 0; i < 4; i++) {
+                u32 addr;
+
+                addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS);
+                if (addr == 0x80000000)
+                        break;
+                ustore_write(uengine, 0xf0000c0300ULL);
+        }
+
+        /*
+         * End programming.
+         */
+        ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000);
+}
+EXPORT_SYMBOL(ixp2000_uengine_load_microcode);
+
+void ixp2000_uengine_init_context(int uengine, int context, int pc)
+{
+        /*
+         * Select the right context for indirect access.
+         */
+        ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context);
+
+        /*
+         * Initialise signal masks to immediately go to Ready state.
+         */
+        ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1);
+        ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1);
+
+        /*
+         * Set program counter.
+         */
+        ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc);
+}
+EXPORT_SYMBOL(ixp2000_uengine_init_context);
+
+void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask)
+{
+        u32 mask;
+
+        /*
+         * Enable the specified context to go to Executing state.
+         */
+        mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
+        mask |= ctx_mask << 8;
+        ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
+}
+EXPORT_SYMBOL(ixp2000_uengine_start_contexts);
+
+void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask)
+{
+        u32 mask;
+
+        /*
+         * Disable the Ready->Executing transition.  Note that this
+         * does not stop the context until it voluntarily yields.
+         */
+        mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
+        mask &= ~(ctx_mask << 8);
+        ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
+}
+EXPORT_SYMBOL(ixp2000_uengine_stop_contexts);
+
+static int check_ixp_type(struct ixp2000_uengine_code *c)
+{
+        u32 product_id;
+        u32 rev;
+
+        product_id = ixp2000_reg_read(IXP2000_PRODUCT_ID);
+        if (((product_id >> 16) & 0x1f) != 0)
+                return 0;
+
+        switch ((product_id >> 8) & 0xff) {
+        case 0:         /* IXP2800 */
+                if (!(c->cpu_model_bitmask & 4))
+                        return 0;
+                break;
+
+        case 1:         /* IXP2850 */
+                if (!(c->cpu_model_bitmask & 8))
+                        return 0;
+                break;
+
+        case 2:         /* IXP2400 */
+                if (!(c->cpu_model_bitmask & 2))
+                        return 0;
+                break;
+
+        default:
+                return 0;
+        }
+
+        rev = product_id & 0xff;
+        if (rev < c->cpu_min_revision || rev > c->cpu_max_revision)
+                return 0;
+
+        return 1;
+}
+
+static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b)
+{
+        int offset;
+        int i;
+
+        offset = 0;
+
+        for (i = 0; i < 128; i++) {
+                u8 b3;
+                u8 b2;
+                u8 b1;
+                u8 b0;
+
+                b3 = (gpr_a[i] >> 24) & 0xff;
+                b2 = (gpr_a[i] >> 16) & 0xff;
+                b1 = (gpr_a[i] >> 8) & 0xff;
+                b0 = gpr_a[i] & 0xff;
+
+                // immed[@ai, (b1 << 8) | b0]
+                // 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII
+                ucode[offset++] = 0xf0;
+                ucode[offset++] = (b1 >> 4);
+                ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6);
+                ucode[offset++] = (b0 << 2);
+                ucode[offset++] = 0x80 | i;
+
+                // immed_w1[@ai, (b3 << 8) | b2]
+                // 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII
+                ucode[offset++] = 0xf4;
+                ucode[offset++] = 0x40 | (b3 >> 4);
+                ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6);
+                ucode[offset++] = (b2 << 2);
+                ucode[offset++] = 0x80 | i;
+        }
+
+        for (i = 0; i < 128; i++) {
+                u8 b3;
+                u8 b2;
+                u8 b1;
+                u8 b0;
+
+                b3 = (gpr_b[i] >> 24) & 0xff;
+                b2 = (gpr_b[i] >> 16) & 0xff;
+                b1 = (gpr_b[i] >> 8) & 0xff;
+                b0 = gpr_b[i] & 0xff;
+
+                // immed[@bi, (b1 << 8) | b0]
+                // 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV
+                ucode[offset++] = 0xf0;
+                ucode[offset++] = (b1 >> 4);
+                ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6);
+                ucode[offset++] = (i << 2) | 0x03;
+                ucode[offset++] = b0;
+
+                // immed_w1[@bi, (b3 << 8) | b2]
+                // 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV
+                ucode[offset++] = 0xf4;
+                ucode[offset++] = 0x40 | (b3 >> 4);
+                ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6);
+                ucode[offset++] = (i << 2) | 0x03;
+                ucode[offset++] = b2;
+        }
+
+        // ctx_arb[kill]
+        ucode[offset++] = 0xe0;
+        ucode[offset++] = 0x00;
+        ucode[offset++] = 0x01;
+        ucode[offset++] = 0x00;
+        ucode[offset++] = 0x00;
+}
+
+static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c)
+{
+        int per_ctx_regs;
+        u32 *gpr_a;
+        u32 *gpr_b;
+        u8 *ucode;
+        int i;
+
+        gpr_a = kmalloc(128 * sizeof(u32), GFP_KERNEL);
+        gpr_b = kmalloc(128 * sizeof(u32), GFP_KERNEL);
+        ucode = kmalloc(513 * 5, GFP_KERNEL);
+        if (gpr_a == NULL || gpr_b == NULL || ucode == NULL) {
+                kfree(ucode);
+                kfree(gpr_b);
+                kfree(gpr_a);
+                return 1;
+        }
+
+        per_ctx_regs = 16;
+        if (c->uengine_parameters & IXP2000_UENGINE_4_CONTEXTS)
+                per_ctx_regs = 32;
+
+        memset(gpr_a, 0, sizeof(gpr_a));
+        memset(gpr_b, 0, sizeof(gpr_b));
+        for (i = 0; i < 256; i++) {
+                struct ixp2000_reg_value *r = c->initial_reg_values + i;
+                u32 *bank;
+                int inc;
+                int j;
+
+                if (r->reg == -1)
+                        break;
+
+                bank = (r->reg & 0x400) ? gpr_b : gpr_a;
+                inc = (r->reg & 0x80) ? 128 : per_ctx_regs;
+
+                j = r->reg & 0x7f;
+                while (j < 128) {
+                        bank[j] = r->value;
+                        j += inc;
+                }
+        }
+
+        generate_ucode(ucode, gpr_a, gpr_b);
+        ixp2000_uengine_load_microcode(uengine, ucode, 513);
+        ixp2000_uengine_init_context(uengine, 0, 0);
+        ixp2000_uengine_start_contexts(uengine, 0x01);
+        for (i = 0; i < 100; i++) {
+                u32 status;
+
+                status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS);
+                if (!(status & 0x80000000))
+                        break;
+        }
+        ixp2000_uengine_stop_contexts(uengine, 0x01);
+
+        kfree(ucode);
+        kfree(gpr_b);
+        kfree(gpr_a);
+
+        return !!(i == 100);
+}
+
+int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c)
+{
+        int ctx;
+
+        if (!check_ixp_type(c))
+                return 1;
+
+        if (!(ixp2000_uengine_mask & (1 << uengine)))
+                return 1;
+
+        ixp2000_uengine_reset(1 << uengine);
+        ixp2000_uengine_set_mode(uengine, c->uengine_parameters);
+        if (set_initial_registers(uengine, c))
+                return 1;
+        ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns);
+
+        for (ctx = 0; ctx < 8; ctx++)
+                ixp2000_uengine_init_context(uengine, ctx, 0);
+
+        return 0;
+}
+EXPORT_SYMBOL(ixp2000_uengine_load);
+
+
+static int __init ixp2000_uengine_init(void)
+{
+        int uengine;
+        u32 value;
+
+        /*
+         * Determine number of microengines present.
+         */
+        switch ((ixp2000_reg_read(IXP2000_PRODUCT_ID) >> 8) & 0x1fff) {
+        case 0:         /* IXP2800 */
+        case 1:         /* IXP2850 */
+                ixp2000_uengine_mask = 0x00ff00ff;
+                break;
+
+        case 2:         /* IXP2400 */
+                ixp2000_uengine_mask = 0x000f000f;
+                break;
+
+        default:
+                printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n",
+                        (unsigned int)ixp2000_reg_read(IXP2000_PRODUCT_ID));
+                ixp2000_uengine_mask = 0x00000000;
+                break;
+        }
+
+        /*
+         * Reset microengines.
+         */
+        ixp2000_uengine_reset(ixp2000_uengine_mask);
+
+        /*
+         * Synchronise timestamp counters across all microengines.
+         */
+        value = ixp2000_reg_read(IXP2000_MISC_CONTROL);
+        ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value & ~0x80);
+        for (uengine = 0; uengine < 32; uengine++) {
+                if (ixp2000_uengine_mask & (1 << uengine)) {
+                        ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
+                        ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
+                }
+        }
+        ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value | 0x80);
+
+        return 0;
+}
+
+subsys_initcall(ixp2000_uengine_init);
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index a45ed1687a59..a19bc4a6196d 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -22,22 +22,21 @@
 #include <linux/list.h>
 
 #include <asm/io.h>
-#include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/vic.h>
 
-static void __iomem *vic_base;
-
 static void vic_mask_irq(unsigned int irq)
 {
-        irq -= IRQ_VIC_START;
-        writel(1 << irq, vic_base + VIC_INT_ENABLE_CLEAR);
+        void __iomem *base = get_irq_chipdata(irq);
+        irq &= 31;
+        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
 }
 
 static void vic_unmask_irq(unsigned int irq)
 {
-        irq -= IRQ_VIC_START;
-        writel(1 << irq, vic_base + VIC_INT_ENABLE);
+        void __iomem *base = get_irq_chipdata(irq);
+        irq &= 31;
+        writel(1 << irq, base + VIC_INT_ENABLE);
 }
 
 static struct irqchip vic_chip = {
@@ -46,43 +45,49 @@ static struct irqchip vic_chip = {
         .unmask = vic_unmask_irq,
 };
 
-void __init vic_init(void __iomem *base, u32 vic_sources)
+/**
+ * vic_init - initialise a vectored interrupt controller
+ * @base: iomem base address
+ * @irq_start: starting interrupt number, must be muliple of 32
+ * @vic_sources: bitmask of interrupt sources to allow
+ */
+void __init vic_init(void __iomem *base, unsigned int irq_start,
+                     u32 vic_sources)
 {
         unsigned int i;
 
-        vic_base = base;
-
         /* Disable all interrupts initially. */
 
-        writel(0, vic_base + VIC_INT_SELECT);
-        writel(0, vic_base + VIC_INT_ENABLE);
-        writel(~0, vic_base + VIC_INT_ENABLE_CLEAR);
-        writel(0, vic_base + VIC_IRQ_STATUS);
-        writel(0, vic_base + VIC_ITCR);
-        writel(~0, vic_base + VIC_INT_SOFT_CLEAR);
+        writel(0, base + VIC_INT_SELECT);
+        writel(0, base + VIC_INT_ENABLE);
+        writel(~0, base + VIC_INT_ENABLE_CLEAR);
+        writel(0, base + VIC_IRQ_STATUS);
+        writel(0, base + VIC_ITCR);
+        writel(~0, base + VIC_INT_SOFT_CLEAR);
 
         /*
          * Make sure we clear all existing interrupts
          */
-        writel(0, vic_base + VIC_VECT_ADDR);
+        writel(0, base + VIC_VECT_ADDR);
         for (i = 0; i < 19; i++) {
                 unsigned int value;
 
-                value = readl(vic_base + VIC_VECT_ADDR);
-                writel(value, vic_base + VIC_VECT_ADDR);
+                value = readl(base + VIC_VECT_ADDR);
+                writel(value, base + VIC_VECT_ADDR);
         }
 
         for (i = 0; i < 16; i++) {
-                void __iomem *reg = vic_base + VIC_VECT_CNTL0 + (i * 4);
+                void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
                 writel(VIC_VECT_CNTL_ENABLE | i, reg);
         }
 
-        writel(32, vic_base + VIC_DEF_VECT_ADDR);
+        writel(32, base + VIC_DEF_VECT_ADDR);
 
         for (i = 0; i < 32; i++) {
-                unsigned int irq = IRQ_VIC_START + i;
+                unsigned int irq = irq_start + i;
 
                 set_irq_chip(irq, &vic_chip);
+                set_irq_chipdata(irq, base);
 
                 if (vic_sources & (1 << i)) {
                         set_irq_handler(irq, do_level_IRQ);