4 files changed, 51 insertions, 77 deletions

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index b2dc2dd7f1df..f0783be17352 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -41,6 +41,7 @@
 
 #include <asm/irq.h>
 #include <asm/exception.h>
+#include <asm/smp_plat.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/gic.h>
 
@@ -50,7 +51,6 @@ union gic_base {
 };
 
 struct gic_chip_data {
-        unsigned int irq_offset;
         union gic_base dist_base;
         union gic_base cpu_base;
 #ifdef CONFIG_CPU_PM
@@ -60,9 +60,7 @@ struct gic_chip_data {
         u32 __percpu *saved_ppi_enable;
         u32 __percpu *saved_ppi_conf;
 #endif
-#ifdef CONFIG_IRQ_DOMAIN
-        struct irq_domain domain;
-#endif
+        struct irq_domain *domain;
         unsigned int gic_irqs;
 #ifdef CONFIG_GIC_NON_BANKED
         void __iomem *(*get_base)(union gic_base *);
@@ -281,7 +279,7 @@ asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
                 irqnr = irqstat & ~0x1c00;
 
                 if (likely(irqnr > 15 && irqnr < 1021)) {
-                        irqnr = irq_domain_to_irq(&gic->domain, irqnr);
+                        irqnr = irq_find_mapping(gic->domain, irqnr);
                         handle_IRQ(irqnr, regs);
                         continue;
                 }
@@ -313,8 +311,8 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
         if (gic_irq == 1023)
                 goto out;
 
-        cascade_irq = irq_domain_to_irq(&chip_data->domain, gic_irq);
-        if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
+        cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
+        if (unlikely(gic_irq < 32 || gic_irq > 1020))
                 do_bad_IRQ(cascade_irq, desc);
         else
                 generic_handle_irq(cascade_irq);
@@ -347,16 +345,11 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
 
 static void __init gic_dist_init(struct gic_chip_data *gic)
 {
-        unsigned int i, irq;
+        unsigned int i;
         u32 cpumask;
         unsigned int gic_irqs = gic->gic_irqs;
-        struct irq_domain *domain = &gic->domain;
         void __iomem *base = gic_data_dist_base(gic);
-        u32 cpu = 0;
-
-#ifdef CONFIG_SMP
-        cpu = cpu_logical_map(smp_processor_id());
-#endif
+        u32 cpu = cpu_logical_map(smp_processor_id());
 
         cpumask = 1 << cpu;
         cpumask |= cpumask << 8;
@@ -389,23 +382,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
         for (i = 32; i < gic_irqs; i += 32)
                 writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
 
-        /*
-         * Setup the Linux IRQ subsystem.
-         */
-        irq_domain_for_each_irq(domain, i, irq) {
-                if (i < 32) {
-                        irq_set_percpu_devid(irq);
-                        irq_set_chip_and_handler(irq, &gic_chip,
-                                                 handle_percpu_devid_irq);
-                        set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
-                } else {
-                        irq_set_chip_and_handler(irq, &gic_chip,
-                                                 handle_fasteoi_irq);
-                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-                }
-                irq_set_chip_data(irq, gic);
-        }
-
         writel_relaxed(1, base + GIC_DIST_CTRL);
 }
 
@@ -621,11 +597,27 @@ static void __init gic_pm_init(struct gic_chip_data *gic)
 }
 #endif
 
-#ifdef CONFIG_OF
-static int gic_irq_domain_dt_translate(struct irq_domain *d,
-                                       struct device_node *controller,
-                                       const u32 *intspec, unsigned int intsize,
-                                       unsigned long *out_hwirq, unsigned int *out_type)
+static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
+                                irq_hw_number_t hw)
+{
+        if (hw < 32) {
+                irq_set_percpu_devid(irq);
+                irq_set_chip_and_handler(irq, &gic_chip,
+                                         handle_percpu_devid_irq);
+                set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
+        } else {
+                irq_set_chip_and_handler(irq, &gic_chip,
+                                         handle_fasteoi_irq);
+                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+        }
+        irq_set_chip_data(irq, d->host_data);
+        return 0;
+}
+
+static int gic_irq_domain_xlate(struct irq_domain *d,
+                                struct device_node *controller,
+                                const u32 *intspec, unsigned int intsize,
+                                unsigned long *out_hwirq, unsigned int *out_type)
 {
         if (d->of_node != controller)
                 return -EINVAL;
@@ -642,26 +634,23 @@ static int gic_irq_domain_dt_translate(struct irq_domain *d,
         *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
         return 0;
 }
-#endif
 
 const struct irq_domain_ops gic_irq_domain_ops = {
-#ifdef CONFIG_OF
-        .dt_translate = gic_irq_domain_dt_translate,
-#endif
+        .map = gic_irq_domain_map,
+        .xlate = gic_irq_domain_xlate,
 };
 
 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
                            void __iomem *dist_base, void __iomem *cpu_base,
-                           u32 percpu_offset)
+                           u32 percpu_offset, struct device_node *node)
 {
+        irq_hw_number_t hwirq_base;
         struct gic_chip_data *gic;
-        struct irq_domain *domain;
-        int gic_irqs;
+        int gic_irqs, irq_base;
 
         BUG_ON(gic_nr >= MAX_GIC_NR);
 
         gic = &gic_data[gic_nr];
-        domain = &gic->domain;
 #ifdef CONFIG_GIC_NON_BANKED
         if (percpu_offset) { /* Frankein-GIC without banked registers... */
                 unsigned int cpu;
@@ -697,10 +686,10 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
          * For primary GICs, skip over SGIs.
          * For secondary GICs, skip over PPIs, too.
          */
-        domain->hwirq_base = 32;
+        hwirq_base = 32;
         if (gic_nr == 0) {
                 if ((irq_start & 31) > 0) {
-                        domain->hwirq_base = 16;
+                        hwirq_base = 16;
                         if (irq_start != -1)
                                 irq_start = (irq_start & ~31) + 16;
                 }
@@ -716,17 +705,17 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
                 gic_irqs = 1020;
         gic->gic_irqs = gic_irqs;
 
-        domain->nr_irq = gic_irqs - domain->hwirq_base;
-        domain->irq_base = irq_alloc_descs(irq_start, 16, domain->nr_irq,
-                                           numa_node_id());
-        if (IS_ERR_VALUE(domain->irq_base)) {
+        gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
+        irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
+        if (IS_ERR_VALUE(irq_base)) {
                 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
                      irq_start);
-                domain->irq_base = irq_start;
+                irq_base = irq_start;
         }
-        domain->priv = gic;
-        domain->ops = &gic_irq_domain_ops;
-        irq_domain_add(domain);
+        gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
+                                    hwirq_base, &gic_irq_domain_ops, gic);
+        if (WARN_ON(!gic->domain))
+                return;
 
         gic_chip.flags |= gic_arch_extn.flags;
         gic_dist_init(gic);
@@ -771,7 +760,6 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
         void __iomem *dist_base;
         u32 percpu_offset;
         int irq;
-        struct irq_domain *domain = &gic_data[gic_cnt].domain;
 
         if (WARN_ON(!node))
                 return -ENODEV;
@@ -785,9 +773,7 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
         if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
                 percpu_offset = 0;
 
-        domain->of_node = of_node_get(node);
-
-        gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset);
+        gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
 
         if (parent) {
                 irq = irq_of_parse_and_map(node, 0);
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index 9384c2d02baa..dcb13494ca0d 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -320,13 +320,6 @@ err0:
         return -EBUSY;
 }
 
-/*
- * If we set up a device for bus mastering, we need to check the latency
- * timer as we don't have even crappy BIOSes to set it properly.
- * The implementation is from arch/i386/pci/i386.c
- */
-unsigned int pcibios_max_latency = 255;
-
 /* ITE bridge requires setting latency timer to avoid early bus access
    termination by PCI bus master devices
 */
diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c
index d8e44a43047c..ff3ad2244824 100644
--- a/arch/arm/common/pl330.c
+++ b/arch/arm/common/pl330.c
@@ -1502,12 +1502,13 @@ int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
         struct pl330_thread *thrd = ch_id;
         struct pl330_dmac *pl330;
         unsigned long flags;
-        int ret = 0, active = thrd->req_running;
+        int ret = 0, active;
 
         if (!thrd || thrd->free || thrd->dmac->state == DYING)
                 return -EINVAL;
 
         pl330 = thrd->dmac;
+        active = thrd->req_running;
 
         spin_lock_irqsave(&pl330->lock, flags);
 
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index dcb004a804c7..7a66311f3066 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -56,7 +56,7 @@ struct vic_device {
         u32             int_enable;
         u32             soft_int;
         u32             protect;
-        struct irq_domain domain;
+        struct irq_domain *domain;
 };
 
 /* we cannot allocate memory when VICs are initially registered */
@@ -192,14 +192,8 @@ static void __init vic_register(void __iomem *base, unsigned int irq,
         v->resume_sources = resume_sources;
         v->irq = irq;
         vic_id++;
-
-        v->domain.irq_base = irq;
-        v->domain.nr_irq = 32;
-#ifdef CONFIG_OF_IRQ
-        v->domain.of_node = of_node_get(node);
-#endif /* CONFIG_OF */
-        v->domain.ops = &irq_domain_simple_ops;
-        irq_domain_add(&v->domain);
+        v->domain = irq_domain_add_legacy(node, 32, irq, 0,
+                                          &irq_domain_simple_ops, v);
 }
 
 static void vic_ack_irq(struct irq_data *d)
@@ -348,7 +342,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
         vic_register(base, irq_start, 0, node);
 }
 
-static void __init __vic_init(void __iomem *base, unsigned int irq_start,
+void __init __vic_init(void __iomem *base, unsigned int irq_start,
                               u32 vic_sources, u32 resume_sources,
                               struct device_node *node)
 {
@@ -444,7 +438,7 @@ static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
         stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
         while (stat) {
                 irq = ffs(stat) - 1;
-                handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs);
+                handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
                 stat &= ~(1 << irq);
                 handled = 1;
         }