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-rw-r--r--arch/arm/boot/dts/Makefile4
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts25
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts56
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi63
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi57
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts44
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi12
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi19
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi34
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts125
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi91
-rw-r--r--arch/arm/boot/dts/dove.dtsi62
-rw-r--r--arch/arm/boot/dts/kirkwood.dtsi62
13 files changed, 649 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d0ae1d3a90d9..0f441740c22a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -77,7 +77,9 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
77dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \ 77dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
78 msm8960-cdp.dtb 78 msm8960-cdp.dtb
79dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ 79dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
80 armada-xp-db.dtb 80 armada-370-mirabox.dtb \
81 armada-xp-db.dtb \
82 armada-xp-openblocks-ax3-4.dtb
81dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \ 83dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \
82 imx53-ard.dtb \ 84 imx53-ard.dtb \
83 imx53-evk.dtb \ 85 imx53-evk.dtb \
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index fffd5c2a3041..00044026ef1f 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -34,9 +34,30 @@
34 clock-frequency = <200000000>; 34 clock-frequency = <200000000>;
35 status = "okay"; 35 status = "okay";
36 }; 36 };
37 timer@d0020300 { 37 sata@d00a0000 {
38 clock-frequency = <600000000>; 38 nr-ports = <2>;
39 status = "okay"; 39 status = "okay";
40 }; 40 };
41
42 mdio {
43 phy0: ethernet-phy@0 {
44 reg = <0>;
45 };
46
47 phy1: ethernet-phy@1 {
48 reg = <1>;
49 };
50 };
51
52 ethernet@d0070000 {
53 status = "okay";
54 phy = <&phy0>;
55 phy-mode = "rgmii-id";
56 };
57 ethernet@d0074000 {
58 status = "okay";
59 phy = <&phy1>;
60 phy-mode = "rgmii-id";
61 };
41 }; 62 };
42}; 63};
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
new file mode 100644
index 000000000000..3b4071336599
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -0,0 +1,56 @@
1/*
2 * Device Tree file for Globalscale Mirabox
3 *
4 * Gregory CLEMENT <gregory.clement@free-electrons.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12/include/ "armada-370.dtsi"
13
14/ {
15 model = "Globalscale Mirabox";
16 compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";
17
18 chosen {
19 bootargs = "console=ttyS0,115200 earlyprintk";
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x00000000 0x20000000>; /* 512 MB */
25 };
26
27 soc {
28 serial@d0012000 {
29 clock-frequency = <200000000>;
30 status = "okay";
31 };
32 timer@d0020300 {
33 clock-frequency = <600000000>;
34 status = "okay";
35 };
36 mdio {
37 phy0: ethernet-phy@0 {
38 reg = <0>;
39 };
40
41 phy1: ethernet-phy@1 {
42 reg = <1>;
43 };
44 };
45 ethernet@d0070000 {
46 status = "okay";
47 phy = <&phy0>;
48 phy-mode = "rgmii-id";
49 };
50 ethernet@d0074000 {
51 status = "okay";
52 phy = <&phy1>;
53 phy-mode = "rgmii-id";
54 };
55 };
56};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 16cc82cdaa81..cf6c48a09eac 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -20,7 +20,7 @@
20 20
21/ { 21/ {
22 model = "Marvell Armada 370 and XP SoC"; 22 model = "Marvell Armada 370 and XP SoC";
23 compatible = "marvell,armada_370_xp"; 23 compatible = "marvell,armada-370-xp";
24 24
25 cpus { 25 cpus {
26 cpu@0 { 26 cpu@0 {
@@ -36,6 +36,12 @@
36 interrupt-controller; 36 interrupt-controller;
37 }; 37 };
38 38
39 coherency-fabric@d0020200 {
40 compatible = "marvell,coherency-fabric";
41 reg = <0xd0020200 0xb0>,
42 <0xd0021810 0x1c>;
43 };
44
39 soc { 45 soc {
40 #address-cells = <1>; 46 #address-cells = <1>;
41 #size-cells = <1>; 47 #size-cells = <1>;
@@ -62,12 +68,67 @@
62 compatible = "marvell,armada-370-xp-timer"; 68 compatible = "marvell,armada-370-xp-timer";
63 reg = <0xd0020300 0x30>; 69 reg = <0xd0020300 0x30>;
64 interrupts = <37>, <38>, <39>, <40>; 70 interrupts = <37>, <38>, <39>, <40>;
71 clocks = <&coreclk 2>;
65 }; 72 };
66 73
67 addr-decoding@d0020000 { 74 addr-decoding@d0020000 {
68 compatible = "marvell,armada-addr-decoding-controller"; 75 compatible = "marvell,armada-addr-decoding-controller";
69 reg = <0xd0020000 0x258>; 76 reg = <0xd0020000 0x258>;
70 }; 77 };
78
79 sata@d00a0000 {
80 compatible = "marvell,orion-sata";
81 reg = <0xd00a0000 0x2400>;
82 interrupts = <55>;
83 clocks = <&gateclk 15>, <&gateclk 30>;
84 clock-names = "0", "1";
85 status = "disabled";
86 };
87
88 mdio {
89 #address-cells = <1>;
90 #size-cells = <0>;
91 compatible = "marvell,orion-mdio";
92 reg = <0xd0072004 0x4>;
93 };
94
95 ethernet@d0070000 {
96 compatible = "marvell,armada-370-neta";
97 reg = <0xd0070000 0x2500>;
98 interrupts = <8>;
99 clocks = <&gateclk 4>;
100 status = "disabled";
101 };
102
103 ethernet@d0074000 {
104 compatible = "marvell,armada-370-neta";
105 reg = <0xd0074000 0x2500>;
106 interrupts = <10>;
107 clocks = <&gateclk 3>;
108 status = "disabled";
109 };
110
111 i2c0: i2c@d0011000 {
112 compatible = "marvell,mv64xxx-i2c";
113 reg = <0xd0011000 0x20>;
114 #address-cells = <1>;
115 #size-cells = <0>;
116 interrupts = <31>;
117 timeout-ms = <1000>;
118 clocks = <&coreclk 0>;
119 status = "disabled";
120 };
121
122 i2c1: i2c@d0011100 {
123 compatible = "marvell,mv64xxx-i2c";
124 reg = <0xd0011100 0x20>;
125 #address-cells = <1>;
126 #size-cells = <0>;
127 interrupts = <32>;
128 timeout-ms = <1000>;
129 clocks = <&coreclk 0>;
130 status = "disabled";
131 };
71 }; 132 };
72}; 133};
73 134
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 2069151afe01..636cf7d4009e 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -20,6 +20,12 @@
20/ { 20/ {
21 model = "Marvell Armada 370 family SoC"; 21 model = "Marvell Armada 370 family SoC";
22 compatible = "marvell,armada370", "marvell,armada-370-xp"; 22 compatible = "marvell,armada370", "marvell,armada-370-xp";
23 L2: l2-cache {
24 compatible = "marvell,aurora-outer-cache";
25 reg = <0xd0008000 0x1000>;
26 cache-id-part = <0x100>;
27 wt-override;
28 };
23 29
24 aliases { 30 aliases {
25 gpio0 = &gpio0; 31 gpio0 = &gpio0;
@@ -75,5 +81,56 @@
75 #interrupts-cells = <2>; 81 #interrupts-cells = <2>;
76 interrupts = <91>; 82 interrupts = <91>;
77 }; 83 };
84
85 coreclk: mvebu-sar@d0018230 {
86 compatible = "marvell,armada-370-core-clock";
87 reg = <0xd0018230 0x08>;
88 #clock-cells = <1>;
89 };
90
91 gateclk: clock-gating-control@d0018220 {
92 compatible = "marvell,armada-370-gating-clock";
93 reg = <0xd0018220 0x4>;
94 clocks = <&coreclk 0>;
95 #clock-cells = <1>;
96 };
97
98 xor@d0060800 {
99 compatible = "marvell,orion-xor";
100 reg = <0xd0060800 0x100
101 0xd0060A00 0x100>;
102 status = "okay";
103
104 xor00 {
105 interrupts = <51>;
106 dmacap,memcpy;
107 dmacap,xor;
108 };
109 xor01 {
110 interrupts = <52>;
111 dmacap,memcpy;
112 dmacap,xor;
113 dmacap,memset;
114 };
115 };
116
117 xor@d0060900 {
118 compatible = "marvell,orion-xor";
119 reg = <0xd0060900 0x100
120 0xd0060b00 0x100>;
121 status = "okay";
122
123 xor10 {
124 interrupts = <94>;
125 dmacap,memcpy;
126 dmacap,xor;
127 };
128 xor11 {
129 interrupts = <95>;
130 dmacap,memcpy;
131 dmacap,xor;
132 dmacap,memset;
133 };
134 };
78 }; 135 };
79}; 136};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index b1fc728515e9..8e53b25b5508 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -46,5 +46,49 @@
46 clock-frequency = <250000000>; 46 clock-frequency = <250000000>;
47 status = "okay"; 47 status = "okay";
48 }; 48 };
49
50 sata@d00a0000 {
51 nr-ports = <2>;
52 status = "okay";
53 };
54
55 mdio {
56 phy0: ethernet-phy@0 {
57 reg = <0>;
58 };
59
60 phy1: ethernet-phy@1 {
61 reg = <1>;
62 };
63
64 phy2: ethernet-phy@2 {
65 reg = <25>;
66 };
67
68 phy3: ethernet-phy@3 {
69 reg = <27>;
70 };
71 };
72
73 ethernet@d0070000 {
74 status = "okay";
75 phy = <&phy0>;
76 phy-mode = "rgmii-id";
77 };
78 ethernet@d0074000 {
79 status = "okay";
80 phy = <&phy1>;
81 phy-mode = "rgmii-id";
82 };
83 ethernet@d0030000 {
84 status = "okay";
85 phy = <&phy2>;
86 phy-mode = "sgmii";
87 };
88 ethernet@d0034000 {
89 status = "okay";
90 phy = <&phy3>;
91 phy-mode = "sgmii";
92 };
49 }; 93 };
50}; 94};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index ea355192be6f..c45c7b4dc352 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -24,6 +24,18 @@
24 gpio1 = &gpio1; 24 gpio1 = &gpio1;
25 }; 25 };
26 26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 compatible = "marvell,sheeva-v7";
34 reg = <0>;
35 clocks = <&cpuclk 0>;
36 };
37 }
38
27 soc { 39 soc {
28 pinctrl { 40 pinctrl {
29 compatible = "marvell,mv78230-pinctrl"; 41 compatible = "marvell,mv78230-pinctrl";
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 2057863f3dfa..a2aee5707377 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -25,6 +25,25 @@
25 gpio2 = &gpio2; 25 gpio2 = &gpio2;
26 }; 26 };
27 27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu@0 {
33 device_type = "cpu";
34 compatible = "marvell,sheeva-v7";
35 reg = <0>;
36 clocks = <&cpuclk 0>;
37 };
38
39 cpu@1 {
40 device_type = "cpu";
41 compatible = "marvell,sheeva-v7";
42 reg = <1>;
43 clocks = <&cpuclk 1>;
44 };
45 };
46
28 soc { 47 soc {
29 pinctrl { 48 pinctrl {
30 compatible = "marvell,mv78260-pinctrl"; 49 compatible = "marvell,mv78260-pinctrl";
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index ffac98373792..da03a129243a 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -25,6 +25,40 @@
25 gpio2 = &gpio2; 25 gpio2 = &gpio2;
26 }; 26 };
27 27
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 compatible = "marvell,sheeva-v7";
36 reg = <0>;
37 clocks = <&cpuclk 0>;
38 };
39
40 cpu@1 {
41 device_type = "cpu";
42 compatible = "marvell,sheeva-v7";
43 reg = <1>;
44 clocks = <&cpuclk 1>;
45 };
46
47 cpu@2 {
48 device_type = "cpu";
49 compatible = "marvell,sheeva-v7";
50 reg = <2>;
51 clocks = <&cpuclk 2>;
52 };
53
54 cpu@3 {
55 device_type = "cpu";
56 compatible = "marvell,sheeva-v7";
57 reg = <3>;
58 clocks = <&cpuclk 3>;
59 };
60 };
61
28 soc { 62 soc {
29 pinctrl { 63 pinctrl {
30 compatible = "marvell,mv78460-pinctrl"; 64 compatible = "marvell,mv78460-pinctrl";
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
new file mode 100644
index 000000000000..b42652fd3d8c
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -0,0 +1,125 @@
1/*
2 * Device Tree file for OpenBlocks AX3-4 board
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13/dts-v1/;
14/include/ "armada-xp-mv78260.dtsi"
15
16/ {
17 model = "PlatHome OpenBlocks AX3-4 board";
18 compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
19
20 chosen {
21 bootargs = "console=ttyS0,115200 earlyprintk";
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x00000000 0xC0000000>; /* 3 GB */
27 };
28
29 soc {
30 serial@d0012000 {
31 clock-frequency = <250000000>;
32 status = "okay";
33 };
34 serial@d0012100 {
35 clock-frequency = <250000000>;
36 status = "okay";
37 };
38 pinctrl {
39 led_pins: led-pins-0 {
40 marvell,pins = "mpp49", "mpp51", "mpp53";
41 marvell,function = "gpio";
42 };
43 };
44 leds {
45 compatible = "gpio-leds";
46 pinctrl-names = "default";
47 pinctrl-0 = <&led_pins>;
48
49 red_led {
50 label = "red_led";
51 gpios = <&gpio1 17 1>;
52 default-state = "off";
53 };
54
55 yellow_led {
56 label = "yellow_led";
57 gpios = <&gpio1 19 1>;
58 default-state = "off";
59 };
60
61 green_led {
62 label = "green_led";
63 gpios = <&gpio1 21 1>;
64 default-state = "off";
65 linux,default-trigger = "heartbeat";
66 };
67 };
68
69 mdio {
70 phy0: ethernet-phy@0 {
71 reg = <0>;
72 };
73
74 phy1: ethernet-phy@1 {
75 reg = <1>;
76 };
77
78 phy2: ethernet-phy@2 {
79 reg = <2>;
80 };
81
82 phy3: ethernet-phy@3 {
83 reg = <3>;
84 };
85 };
86
87 ethernet@d0070000 {
88 status = "okay";
89 phy = <&phy0>;
90 phy-mode = "sgmii";
91 };
92 ethernet@d0074000 {
93 status = "okay";
94 phy = <&phy1>;
95 phy-mode = "sgmii";
96 };
97 ethernet@d0030000 {
98 status = "okay";
99 phy = <&phy2>;
100 phy-mode = "sgmii";
101 };
102 ethernet@d0034000 {
103 status = "okay";
104 phy = <&phy3>;
105 phy-mode = "sgmii";
106 };
107 i2c@d0011000 {
108 status = "okay";
109 clock-frequency = <400000>;
110 };
111 i2c@d0011100 {
112 status = "okay";
113 clock-frequency = <400000>;
114
115 s35390a: s35390a@30 {
116 compatible = "s35390a";
117 reg = <0x30>;
118 };
119 };
120 sata@d00a0000 {
121 nr-ports = <2>;
122 status = "okay";
123 };
124 };
125};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 71d6b5d0daf1..367aa3f94912 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,9 +22,22 @@
22 model = "Marvell Armada XP family SoC"; 22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp"; 23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24 24
25 L2: l2-cache {
26 compatible = "marvell,aurora-system-cache";
27 reg = <0xd0008000 0x1000>;
28 cache-id-part = <0x100>;
29 wt-override;
30 };
31
25 mpic: interrupt-controller@d0020000 { 32 mpic: interrupt-controller@d0020000 {
26 reg = <0xd0020a00 0x1d0>, 33 reg = <0xd0020a00 0x1d0>,
27 <0xd0021870 0x58>; 34 <0xd0021070 0x58>;
35 };
36
37 armada-370-xp-pmsu@d0022000 {
38 compatible = "marvell,armada-370-xp-pmsu";
39 reg = <0xd0022100 0x430>,
40 <0xd0020800 0x20>;
28 }; 41 };
29 42
30 soc { 43 soc {
@@ -47,9 +60,85 @@
47 marvell,timer-25Mhz; 60 marvell,timer-25Mhz;
48 }; 61 };
49 62
63 coreclk: mvebu-sar@d0018230 {
64 compatible = "marvell,armada-xp-core-clock";
65 reg = <0xd0018230 0x08>;
66 #clock-cells = <1>;
67 };
68
69 cpuclk: clock-complex@d0018700 {
70 #clock-cells = <1>;
71 compatible = "marvell,armada-xp-cpu-clock";
72 reg = <0xd0018700 0xA0>;
73 clocks = <&coreclk 1>;
74 };
75
76 gateclk: clock-gating-control@d0018220 {
77 compatible = "marvell,armada-xp-gating-clock";
78 reg = <0xd0018220 0x4>;
79 clocks = <&coreclk 0>;
80 #clock-cells = <1>;
81 };
82
50 system-controller@d0018200 { 83 system-controller@d0018200 {
51 compatible = "marvell,armada-370-xp-system-controller"; 84 compatible = "marvell,armada-370-xp-system-controller";
52 reg = <0xd0018200 0x500>; 85 reg = <0xd0018200 0x500>;
53 }; 86 };
87
88 ethernet@d0030000 {
89 compatible = "marvell,armada-370-neta";
90 reg = <0xd0030000 0x2500>;
91 interrupts = <12>;
92 clocks = <&gateclk 2>;
93 status = "disabled";
94 };
95
96 ethernet@d0034000 {
97 compatible = "marvell,armada-370-neta";
98 reg = <0xd0034000 0x2500>;
99 interrupts = <14>;
100 clocks = <&gateclk 1>;
101 status = "disabled";
102 };
103
104 xor@d0060900 {
105 compatible = "marvell,orion-xor";
106 reg = <0xd0060900 0x100
107 0xd0060b00 0x100>;
108 clocks = <&gateclk 22>;
109 status = "okay";
110
111 xor10 {
112 interrupts = <51>;
113 dmacap,memcpy;
114 dmacap,xor;
115 };
116 xor11 {
117 interrupts = <52>;
118 dmacap,memcpy;
119 dmacap,xor;
120 dmacap,memset;
121 };
122 };
123
124 xor@d00f0900 {
125 compatible = "marvell,orion-xor";
126 reg = <0xd00F0900 0x100
127 0xd00F0B00 0x100>;
128 clocks = <&gateclk 28>;
129 status = "okay";
130
131 xor00 {
132 interrupts = <94>;
133 dmacap,memcpy;
134 dmacap,xor;
135 };
136 xor01 {
137 interrupts = <95>;
138 dmacap,memcpy;
139 dmacap,xor;
140 dmacap,memset;
141 };
142 };
54 }; 143 };
55}; 144};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 61f391412a5a..f3f7e9d8adca 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -37,6 +37,19 @@
37 reg = <0x20204 0x04>, <0x20214 0x04>; 37 reg = <0x20204 0x04>, <0x20214 0x04>;
38 }; 38 };
39 39
40 core_clk: core-clocks@d0214 {
41 compatible = "marvell,dove-core-clock";
42 reg = <0xd0214 0x4>;
43 #clock-cells = <1>;
44 };
45
46 gate_clk: clock-gating-control@d0038 {
47 compatible = "marvell,dove-gating-clock";
48 reg = <0xd0038 0x4>;
49 clocks = <&core_clk 0>;
50 #clock-cells = <1>;
51 };
52
40 uart0: serial@12000 { 53 uart0: serial@12000 {
41 compatible = "ns16550a"; 54 compatible = "ns16550a";
42 reg = <0x12000 0x100>; 55 reg = <0x12000 0x100>;
@@ -113,6 +126,7 @@
113 cell-index = <0>; 126 cell-index = <0>;
114 interrupts = <6>; 127 interrupts = <6>;
115 reg = <0x10600 0x28>; 128 reg = <0x10600 0x28>;
129 clocks = <&core_clk 0>;
116 status = "disabled"; 130 status = "disabled";
117 }; 131 };
118 132
@@ -123,6 +137,7 @@
123 cell-index = <1>; 137 cell-index = <1>;
124 interrupts = <5>; 138 interrupts = <5>;
125 reg = <0x14600 0x28>; 139 reg = <0x14600 0x28>;
140 clocks = <&core_clk 0>;
126 status = "disabled"; 141 status = "disabled";
127 }; 142 };
128 143
@@ -134,6 +149,7 @@
134 interrupts = <11>; 149 interrupts = <11>;
135 clock-frequency = <400000>; 150 clock-frequency = <400000>;
136 timeout-ms = <1000>; 151 timeout-ms = <1000>;
152 clocks = <&core_clk 0>;
137 status = "disabled"; 153 status = "disabled";
138 }; 154 };
139 155
@@ -141,6 +157,7 @@
141 compatible = "marvell,dove-sdhci"; 157 compatible = "marvell,dove-sdhci";
142 reg = <0x92000 0x100>; 158 reg = <0x92000 0x100>;
143 interrupts = <35>, <37>; 159 interrupts = <35>, <37>;
160 clocks = <&gate_clk 8>;
144 status = "disabled"; 161 status = "disabled";
145 }; 162 };
146 163
@@ -148,6 +165,7 @@
148 compatible = "marvell,dove-sdhci"; 165 compatible = "marvell,dove-sdhci";
149 reg = <0x90000 0x100>; 166 reg = <0x90000 0x100>;
150 interrupts = <36>, <38>; 167 interrupts = <36>, <38>;
168 clocks = <&gate_clk 9>;
151 status = "disabled"; 169 status = "disabled";
152 }; 170 };
153 171
@@ -155,6 +173,7 @@
155 compatible = "marvell,orion-sata"; 173 compatible = "marvell,orion-sata";
156 reg = <0xa0000 0x2400>; 174 reg = <0xa0000 0x2400>;
157 interrupts = <62>; 175 interrupts = <62>;
176 clocks = <&gate_clk 3>;
158 nr-ports = <1>; 177 nr-ports = <1>;
159 status = "disabled"; 178 status = "disabled";
160 }; 179 };
@@ -165,7 +184,50 @@
165 <0xc8000000 0x800>; 184 <0xc8000000 0x800>;
166 reg-names = "regs", "sram"; 185 reg-names = "regs", "sram";
167 interrupts = <31>; 186 interrupts = <31>;
187 clocks = <&gate_clk 15>;
188 status = "okay";
189 };
190
191 xor0: dma-engine@60800 {
192 compatible = "marvell,orion-xor";
193 reg = <0x60800 0x100
194 0x60a00 0x100>;
195 clocks = <&gate_clk 23>;
168 status = "okay"; 196 status = "okay";
197
198 channel0 {
199 interrupts = <39>;
200 dmacap,memcpy;
201 dmacap,xor;
202 };
203
204 channel1 {
205 interrupts = <40>;
206 dmacap,memset;
207 dmacap,memcpy;
208 dmacap,xor;
209 };
210 };
211
212 xor1: dma-engine@60900 {
213 compatible = "marvell,orion-xor";
214 reg = <0x60900 0x100
215 0x60b00 0x100>;
216 clocks = <&gate_clk 24>;
217 status = "okay";
218
219 channel0 {
220 interrupts = <42>;
221 dmacap,memcpy;
222 dmacap,xor;
223 };
224
225 channel1 {
226 interrupts = <43>;
227 dmacap,memset;
228 dmacap,memcpy;
229 dmacap,xor;
230 };
169 }; 231 };
170 }; 232 };
171}; 233};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index a990c30f0a26..7735cee4a9c6 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -23,6 +23,12 @@
23 #address-cells = <1>; 23 #address-cells = <1>;
24 #size-cells = <1>; 24 #size-cells = <1>;
25 25
26 core_clk: core-clocks@10030 {
27 compatible = "marvell,kirkwood-core-clock";
28 reg = <0x10030 0x4>;
29 #clock-cells = <1>;
30 };
31
26 gpio0: gpio@10100 { 32 gpio0: gpio@10100 {
27 compatible = "marvell,orion-gpio"; 33 compatible = "marvell,orion-gpio";
28 #gpio-cells = <2>; 34 #gpio-cells = <2>;
@@ -48,6 +54,7 @@
48 reg = <0x12000 0x100>; 54 reg = <0x12000 0x100>;
49 reg-shift = <2>; 55 reg-shift = <2>;
50 interrupts = <33>; 56 interrupts = <33>;
57 clocks = <&gate_clk 7>;
51 /* set clock-frequency in board dts */ 58 /* set clock-frequency in board dts */
52 status = "disabled"; 59 status = "disabled";
53 }; 60 };
@@ -57,6 +64,7 @@
57 reg = <0x12100 0x100>; 64 reg = <0x12100 0x100>;
58 reg-shift = <2>; 65 reg-shift = <2>;
59 interrupts = <34>; 66 interrupts = <34>;
67 clocks = <&gate_clk 7>;
60 /* set clock-frequency in board dts */ 68 /* set clock-frequency in board dts */
61 status = "disabled"; 69 status = "disabled";
62 }; 70 };
@@ -74,13 +82,62 @@
74 cell-index = <0>; 82 cell-index = <0>;
75 interrupts = <23>; 83 interrupts = <23>;
76 reg = <0x10600 0x28>; 84 reg = <0x10600 0x28>;
85 clocks = <&gate_clk 7>;
77 status = "disabled"; 86 status = "disabled";
78 }; 87 };
79 88
89 gate_clk: clock-gating-control@2011c {
90 compatible = "marvell,kirkwood-gating-clock";
91 reg = <0x2011c 0x4>;
92 clocks = <&core_clk 0>;
93 #clock-cells = <1>;
94 };
95
80 wdt@20300 { 96 wdt@20300 {
81 compatible = "marvell,orion-wdt"; 97 compatible = "marvell,orion-wdt";
82 reg = <0x20300 0x28>; 98 reg = <0x20300 0x28>;
99 clocks = <&gate_clk 7>;
100 status = "okay";
101 };
102
103 xor@60800 {
104 compatible = "marvell,orion-xor";
105 reg = <0x60800 0x100
106 0x60A00 0x100>;
107 status = "okay";
108 clocks = <&gate_clk 8>;
109
110 xor00 {
111 interrupts = <5>;
112 dmacap,memcpy;
113 dmacap,xor;
114 };
115 xor01 {
116 interrupts = <6>;
117 dmacap,memcpy;
118 dmacap,xor;
119 dmacap,memset;
120 };
121 };
122
123 xor@60900 {
124 compatible = "marvell,orion-xor";
125 reg = <0x60900 0x100
126 0xd0B00 0x100>;
83 status = "okay"; 127 status = "okay";
128 clocks = <&gate_clk 16>;
129
130 xor00 {
131 interrupts = <7>;
132 dmacap,memcpy;
133 dmacap,xor;
134 };
135 xor01 {
136 interrupts = <8>;
137 dmacap,memcpy;
138 dmacap,xor;
139 dmacap,memset;
140 };
84 }; 141 };
85 142
86 ehci@50000 { 143 ehci@50000 {
@@ -94,6 +151,8 @@
94 compatible = "marvell,orion-sata"; 151 compatible = "marvell,orion-sata";
95 reg = <0x80000 0x5000>; 152 reg = <0x80000 0x5000>;
96 interrupts = <21>; 153 interrupts = <21>;
154 clocks = <&gate_clk 14>, <&gate_clk 15>;
155 clock-names = "0", "1";
97 status = "disabled"; 156 status = "disabled";
98 }; 157 };
99 158
@@ -107,6 +166,7 @@
107 reg = <0x3000000 0x400>; 166 reg = <0x3000000 0x400>;
108 chip-delay = <25>; 167 chip-delay = <25>;
109 /* set partition map and/or chip-delay in board dts */ 168 /* set partition map and/or chip-delay in board dts */
169 clocks = <&gate_clk 7>;
110 status = "disabled"; 170 status = "disabled";
111 }; 171 };
112 172
@@ -117,6 +177,7 @@
117 #size-cells = <0>; 177 #size-cells = <0>;
118 interrupts = <29>; 178 interrupts = <29>;
119 clock-frequency = <100000>; 179 clock-frequency = <100000>;
180 clocks = <&gate_clk 7>;
120 status = "disabled"; 181 status = "disabled";
121 }; 182 };
122 183
@@ -126,6 +187,7 @@
126 <0xf5000000 0x800>; 187 <0xf5000000 0x800>;
127 reg-names = "regs", "sram"; 188 reg-names = "regs", "sram";
128 interrupts = <22>; 189 interrupts = <22>;
190 clocks = <&gate_clk 17>;
129 status = "okay"; 191 status = "okay";
130 }; 192 };
131 }; 193 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 19:52:33 -0500