diff options
Diffstat (limited to 'arch/arm/boot')
372 files changed, 26759 insertions, 2396 deletions
diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c index d1153c8a765a..9448aa0c6686 100644 --- a/arch/arm/boot/compressed/atags_to_fdt.c +++ b/arch/arm/boot/compressed/atags_to_fdt.c | |||
| @@ -7,6 +7,8 @@ | |||
| 7 | #define do_extend_cmdline 0 | 7 | #define do_extend_cmdline 0 |
| 8 | #endif | 8 | #endif |
| 9 | 9 | ||
| 10 | #define NR_BANKS 16 | ||
| 11 | |||
| 10 | static int node_offset(void *fdt, const char *node_path) | 12 | static int node_offset(void *fdt, const char *node_path) |
| 11 | { | 13 | { |
| 12 | int offset = fdt_path_offset(fdt, node_path); | 14 | int offset = fdt_path_offset(fdt, node_path); |
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 066b03480b63..3a8b32df6b31 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S | |||
| @@ -60,11 +60,6 @@ | |||
| 60 | add \rb, \rb, #0x00010000 @ Ser1 | 60 | add \rb, \rb, #0x00010000 @ Ser1 |
| 61 | #endif | 61 | #endif |
| 62 | .endm | 62 | .endm |
| 63 | #elif defined(CONFIG_ARCH_S3C24XX) | ||
| 64 | .macro loadsp, rb, tmp | ||
| 65 | mov \rb, #0x50000000 | ||
| 66 | add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT | ||
| 67 | .endm | ||
| 68 | #else | 63 | #else |
| 69 | .macro loadsp, rb, tmp | 64 | .macro loadsp, rb, tmp |
| 70 | addruart \rb, \tmp | 65 | addruart \rb, \tmp |
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 377b7c364033..5986ff63b901 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile | |||
| @@ -50,13 +50,15 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb | |||
| 50 | dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb | 50 | dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb |
| 51 | 51 | ||
| 52 | dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb | 52 | dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb |
| 53 | dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb | ||
| 53 | dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb | 54 | dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb |
| 54 | dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb | 55 | dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb |
| 55 | dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ | 56 | dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ |
| 56 | bcm21664-garnet.dtb | 57 | bcm21664-garnet.dtb |
| 57 | dtb-$(CONFIG_ARCH_BERLIN) += \ | 58 | dtb-$(CONFIG_ARCH_BERLIN) += \ |
| 58 | berlin2-sony-nsz-gs7.dtb \ | 59 | berlin2-sony-nsz-gs7.dtb \ |
| 59 | berlin2cd-google-chromecast.dtb | 60 | berlin2cd-google-chromecast.dtb \ |
| 61 | berlin2q-marvell-dmp.dtb | ||
| 60 | dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ | 62 | dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ |
| 61 | da850-evm.dtb | 63 | da850-evm.dtb |
| 62 | dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb | 64 | dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb |
| @@ -72,10 +74,14 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ | |||
| 72 | exynos5250-arndale.dtb \ | 74 | exynos5250-arndale.dtb \ |
| 73 | exynos5250-smdk5250.dtb \ | 75 | exynos5250-smdk5250.dtb \ |
| 74 | exynos5250-snow.dtb \ | 76 | exynos5250-snow.dtb \ |
| 77 | exynos5260-xyref5260.dtb \ | ||
| 78 | exynos5410-smdk5410.dtb \ | ||
| 75 | exynos5420-arndale-octa.dtb \ | 79 | exynos5420-arndale-octa.dtb \ |
| 80 | exynos5420-peach-pit.dtb \ | ||
| 76 | exynos5420-smdk5420.dtb \ | 81 | exynos5420-smdk5420.dtb \ |
| 77 | exynos5440-sd5v1.dtb \ | 82 | exynos5440-sd5v1.dtb \ |
| 78 | exynos5440-ssdk5440.dtb | 83 | exynos5440-ssdk5440.dtb \ |
| 84 | exynos5800-peach-pi.dtb | ||
| 79 | dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb | 85 | dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb |
| 80 | dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ | 86 | dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ |
| 81 | ecx-2000.dtb | 87 | ecx-2000.dtb |
| @@ -127,6 +133,9 @@ kirkwood := \ | |||
| 127 | kirkwood-nsa310a.dtb \ | 133 | kirkwood-nsa310a.dtb \ |
| 128 | kirkwood-openblocks_a6.dtb \ | 134 | kirkwood-openblocks_a6.dtb \ |
| 129 | kirkwood-openblocks_a7.dtb \ | 135 | kirkwood-openblocks_a7.dtb \ |
| 136 | kirkwood-openrd-base.dtb \ | ||
| 137 | kirkwood-openrd-client.dtb \ | ||
| 138 | kirkwood-openrd-ultimate.dtb \ | ||
| 130 | kirkwood-rd88f6192.dtb \ | 139 | kirkwood-rd88f6192.dtb \ |
| 131 | kirkwood-rd88f6281-a0.dtb \ | 140 | kirkwood-rd88f6281-a0.dtb \ |
| 132 | kirkwood-rd88f6281-a1.dtb \ | 141 | kirkwood-rd88f6281-a1.dtb \ |
| @@ -157,10 +166,12 @@ dtb-$(CONFIG_ARCH_MXC) += \ | |||
| 157 | imx27-phytec-phycard-s-rdk.dtb \ | 166 | imx27-phytec-phycard-s-rdk.dtb \ |
| 158 | imx31-bug.dtb \ | 167 | imx31-bug.dtb \ |
| 159 | imx35-eukrea-mbimxsd35-baseboard.dtb \ | 168 | imx35-eukrea-mbimxsd35-baseboard.dtb \ |
| 169 | imx35-pdk.dtb \ | ||
| 160 | imx50-evk.dtb \ | 170 | imx50-evk.dtb \ |
| 161 | imx51-apf51.dtb \ | 171 | imx51-apf51.dtb \ |
| 162 | imx51-apf51dev.dtb \ | 172 | imx51-apf51dev.dtb \ |
| 163 | imx51-babbage.dtb \ | 173 | imx51-babbage.dtb \ |
| 174 | imx51-digi-connectcore-jsk.dtb \ | ||
| 164 | imx51-eukrea-mbimxsd51-baseboard.dtb \ | 175 | imx51-eukrea-mbimxsd51-baseboard.dtb \ |
| 165 | imx53-ard.dtb \ | 176 | imx53-ard.dtb \ |
| 166 | imx53-m53evk.dtb \ | 177 | imx53-m53evk.dtb \ |
| @@ -179,6 +190,8 @@ dtb-$(CONFIG_ARCH_MXC) += \ | |||
| 179 | imx6dl-gw54xx.dtb \ | 190 | imx6dl-gw54xx.dtb \ |
| 180 | imx6dl-hummingboard.dtb \ | 191 | imx6dl-hummingboard.dtb \ |
| 181 | imx6dl-nitrogen6x.dtb \ | 192 | imx6dl-nitrogen6x.dtb \ |
| 193 | imx6dl-phytec-pbab01.dtb \ | ||
| 194 | imx6dl-riotboard.dtb \ | ||
| 182 | imx6dl-sabreauto.dtb \ | 195 | imx6dl-sabreauto.dtb \ |
| 183 | imx6dl-sabrelite.dtb \ | 196 | imx6dl-sabrelite.dtb \ |
| 184 | imx6dl-sabresd.dtb \ | 197 | imx6dl-sabresd.dtb \ |
| @@ -203,6 +216,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ | |||
| 203 | imx6q-udoo.dtb \ | 216 | imx6q-udoo.dtb \ |
| 204 | imx6q-wandboard.dtb \ | 217 | imx6q-wandboard.dtb \ |
| 205 | imx6sl-evk.dtb \ | 218 | imx6sl-evk.dtb \ |
| 219 | vf610-colibri.dtb \ | ||
| 206 | vf610-cosmic.dtb \ | 220 | vf610-cosmic.dtb \ |
| 207 | vf610-twr.dtb | 221 | vf610-twr.dtb |
| 208 | dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ | 222 | dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ |
| @@ -230,76 +244,84 @@ dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb | |||
| 230 | dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \ | 244 | dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \ |
| 231 | nspire-tp.dtb \ | 245 | nspire-tp.dtb \ |
| 232 | nspire-clp.dtb | 246 | nspire-clp.dtb |
| 233 | dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ | 247 | dtb-$(CONFIG_ARCH_OMAP2) += omap2420-h4.dtb \ |
| 234 | omap2430-sdp.dtb \ | ||
| 235 | omap2420-n800.dtb \ | 248 | omap2420-n800.dtb \ |
| 236 | omap2420-n810.dtb \ | 249 | omap2420-n810.dtb \ |
| 237 | omap2420-n810-wimax.dtb \ | 250 | omap2420-n810-wimax.dtb \ |
| 251 | omap2430-sdp.dtb | ||
| 252 | dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \ | ||
| 253 | am3517-evm.dtb \ | ||
| 254 | am3517_mt_ventoux.dtb \ | ||
| 238 | omap3430-sdp.dtb \ | 255 | omap3430-sdp.dtb \ |
| 239 | omap3-beagle.dtb \ | 256 | omap3-beagle.dtb \ |
| 257 | omap3-beagle-xm.dtb \ | ||
| 258 | omap3-beagle-xm-ab.dtb \ | ||
| 240 | omap3-cm-t3517.dtb \ | 259 | omap3-cm-t3517.dtb \ |
| 241 | omap3-sbc-t3517.dtb \ | ||
| 242 | omap3-cm-t3530.dtb \ | 260 | omap3-cm-t3530.dtb \ |
| 243 | omap3-sbc-t3530.dtb \ | ||
| 244 | omap3-cm-t3730.dtb \ | 261 | omap3-cm-t3730.dtb \ |
| 245 | omap3-sbc-t3730.dtb \ | ||
| 246 | omap3-devkit8000.dtb \ | 262 | omap3-devkit8000.dtb \ |
| 247 | omap3-beagle-xm.dtb \ | ||
| 248 | omap3-beagle-xm-ab.dtb \ | ||
| 249 | omap3-evm.dtb \ | 263 | omap3-evm.dtb \ |
| 250 | omap3-evm-37xx.dtb \ | 264 | omap3-evm-37xx.dtb \ |
| 265 | omap3-gta04.dtb \ | ||
| 266 | omap3-igep0020.dtb \ | ||
| 267 | omap3-igep0030.dtb \ | ||
| 251 | omap3-ldp.dtb \ | 268 | omap3-ldp.dtb \ |
| 269 | omap3-lilly-dbb056.dtb \ | ||
| 252 | omap3-n900.dtb \ | 270 | omap3-n900.dtb \ |
| 253 | omap3-n9.dtb \ | 271 | omap3-n9.dtb \ |
| 254 | omap3-n950.dtb \ | 272 | omap3-n950.dtb \ |
| 255 | omap3-overo-alto35.dtb \ | 273 | omap3-overo-alto35.dtb \ |
| 256 | omap3-overo-storm-alto35.dtb \ | ||
| 257 | omap3-overo-chestnut43.dtb \ | 274 | omap3-overo-chestnut43.dtb \ |
| 258 | omap3-overo-storm-chestnut43.dtb \ | ||
| 259 | omap3-overo-gallop43.dtb \ | 275 | omap3-overo-gallop43.dtb \ |
| 260 | omap3-overo-storm-gallop43.dtb \ | ||
| 261 | omap3-overo-palo43.dtb \ | 276 | omap3-overo-palo43.dtb \ |
| 277 | omap3-overo-storm-alto35.dtb \ | ||
| 278 | omap3-overo-storm-chestnut43.dtb \ | ||
| 279 | omap3-overo-storm-gallop43.dtb \ | ||
| 262 | omap3-overo-storm-palo43.dtb \ | 280 | omap3-overo-storm-palo43.dtb \ |
| 263 | omap3-overo-summit.dtb \ | ||
| 264 | omap3-overo-storm-summit.dtb \ | 281 | omap3-overo-storm-summit.dtb \ |
| 265 | omap3-overo-tobi.dtb \ | ||
| 266 | omap3-overo-storm-tobi.dtb \ | 282 | omap3-overo-storm-tobi.dtb \ |
| 267 | omap3-gta04.dtb \ | 283 | omap3-overo-summit.dtb \ |
| 268 | omap3-igep0020.dtb \ | 284 | omap3-overo-tobi.dtb \ |
| 269 | omap3-igep0030.dtb \ | 285 | omap3-sbc-t3517.dtb \ |
| 270 | omap3-lilly-dbb056.dtb \ | 286 | omap3-sbc-t3530.dtb \ |
| 271 | omap3-zoom3.dtb \ | 287 | omap3-sbc-t3730.dtb \ |
| 272 | omap4-duovero-parlor.dtb \ | 288 | omap3-zoom3.dtb |
| 289 | dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \ | ||
| 290 | am335x-bone.dtb \ | ||
| 291 | am335x-boneblack.dtb \ | ||
| 292 | am335x-evm.dtb \ | ||
| 293 | am335x-evmsk.dtb \ | ||
| 294 | am335x-nano.dtb | ||
| 295 | dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ | ||
| 273 | omap4-panda.dtb \ | 296 | omap4-panda.dtb \ |
| 274 | omap4-panda-a4.dtb \ | 297 | omap4-panda-a4.dtb \ |
| 275 | omap4-panda-es.dtb \ | 298 | omap4-panda-es.dtb \ |
| 276 | omap4-var-som.dtb \ | ||
| 277 | omap4-sdp.dtb \ | 299 | omap4-sdp.dtb \ |
| 278 | omap4-sdp-es23plus.dtb \ | 300 | omap4-sdp-es23plus.dtb \ |
| 279 | omap5-uevm.dtb \ | 301 | omap4-var-dvk-om44.dtb \ |
| 280 | am335x-evm.dtb \ | 302 | omap4-var-stk-om44.dtb |
| 281 | am335x-evmsk.dtb \ | 303 | dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \ |
| 282 | am335x-bone.dtb \ | 304 | am437x-gp-evm.dtb |
| 283 | am335x-boneblack.dtb \ | 305 | dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \ |
| 284 | am335x-nano.dtb \ | 306 | omap5-sbc-t54.dtb \ |
| 285 | am335x-base0033.dtb \ | 307 | omap5-uevm.dtb |
| 286 | am3517-craneboard.dtb \ | 308 | dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \ |
| 287 | am3517-evm.dtb \ | 309 | dra72-evm.dtb |
| 288 | am3517_mt_ventoux.dtb \ | 310 | dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \ |
| 289 | am43x-epos-evm.dtb \ | 311 | orion5x-lacie-ethernet-disk-mini-v2.dtb \ |
| 290 | am437x-gp-evm.dtb \ | 312 | orion5x-maxtor-shared-storage-2.dtb \ |
| 291 | dra7-evm.dtb | 313 | orion5x-rd88f5182-nas.dtb |
| 292 | dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb | ||
| 293 | dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb | 314 | dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb |
| 294 | dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \ | 315 | dtb-$(CONFIG_ARCH_QCOM) += \ |
| 295 | qcom-msm8960-cdp.dtb \ | 316 | qcom-apq8064-ifc6410.dtb \ |
| 296 | qcom-apq8074-dragonboard.dtb | 317 | qcom-apq8074-dragonboard.dtb \ |
| 318 | qcom-apq8084-mtp.dtb \ | ||
| 319 | qcom-msm8660-surf.dtb \ | ||
| 320 | qcom-msm8960-cdp.dtb | ||
| 297 | dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb | 321 | dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb |
| 298 | dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ | 322 | dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ |
| 299 | s3c6410-smdk6410.dtb | 323 | s3c6410-smdk6410.dtb |
| 300 | dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \ | 324 | dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \ |
| 301 | r7s72100-genmai.dtb \ | ||
| 302 | r7s72100-genmai-reference.dtb \ | ||
| 303 | r8a7740-armadillo800eva.dtb \ | 325 | r8a7740-armadillo800eva.dtb \ |
| 304 | r8a7778-bockw.dtb \ | 326 | r8a7778-bockw.dtb \ |
| 305 | r8a7778-bockw-reference.dtb \ | 327 | r8a7778-bockw-reference.dtb \ |
| @@ -314,12 +336,14 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \ | |||
| 314 | r8a73a4-ape6evm-reference.dtb \ | 336 | r8a73a4-ape6evm-reference.dtb \ |
| 315 | sh7372-mackerel.dtb | 337 | sh7372-mackerel.dtb |
| 316 | dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ | 338 | dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ |
| 317 | r7s72100-genmai-reference.dtb \ | 339 | r7s72100-genmai.dtb \ |
| 340 | r8a7791-henninger.dtb \ | ||
| 318 | r8a7791-koelsch.dtb \ | 341 | r8a7791-koelsch.dtb \ |
| 319 | r8a7790-lager.dtb | 342 | r8a7790-lager.dtb |
| 320 | dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ | 343 | dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ |
| 321 | socfpga_cyclone5_socdk.dtb \ | 344 | socfpga_cyclone5_socdk.dtb \ |
| 322 | socfpga_cyclone5_sockit.dtb \ | 345 | socfpga_cyclone5_sockit.dtb \ |
| 346 | socfpga_cyclone5_socrates.dtb \ | ||
| 323 | socfpga_vt.dtb | 347 | socfpga_vt.dtb |
| 324 | dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ | 348 | dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ |
| 325 | spear1340-evb.dtb | 349 | spear1340-evb.dtb |
| @@ -328,24 +352,33 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ | |||
| 328 | spear320-evb.dtb \ | 352 | spear320-evb.dtb \ |
| 329 | spear320-hmi.dtb | 353 | spear320-hmi.dtb |
| 330 | dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb | 354 | dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb |
| 331 | dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \ | 355 | dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \ |
| 332 | stih416-b2000.dtb \ | 356 | stih415-b2000.dtb \ |
| 333 | stih415-b2020.dtb \ | 357 | stih415-b2020.dtb \ |
| 334 | stih416-b2020.dtb | 358 | stih416-b2000.dtb \ |
| 335 | dtb-$(CONFIG_ARCH_SUNXI) += \ | 359 | stih416-b2020.dtb \ |
| 360 | stih416-b2020-revE.dtb | ||
| 361 | dtb-$(CONFIG_MACH_SUN4I) += \ | ||
| 336 | sun4i-a10-a1000.dtb \ | 362 | sun4i-a10-a1000.dtb \ |
| 337 | sun4i-a10-cubieboard.dtb \ | 363 | sun4i-a10-cubieboard.dtb \ |
| 338 | sun4i-a10-mini-xplus.dtb \ | 364 | sun4i-a10-mini-xplus.dtb \ |
| 339 | sun4i-a10-hackberry.dtb \ | 365 | sun4i-a10-hackberry.dtb \ |
| 340 | sun4i-a10-inet97fv2.dtb \ | 366 | sun4i-a10-inet97fv2.dtb \ |
| 341 | sun4i-a10-olinuxino-lime.dtb \ | 367 | sun4i-a10-olinuxino-lime.dtb \ |
| 342 | sun4i-a10-pcduino.dtb \ | 368 | sun4i-a10-pcduino.dtb |
| 369 | dtb-$(CONFIG_MACH_SUN5I) += \ | ||
| 343 | sun5i-a10s-olinuxino-micro.dtb \ | 370 | sun5i-a10s-olinuxino-micro.dtb \ |
| 371 | sun5i-a10s-r7-tv-dongle.dtb \ | ||
| 344 | sun5i-a13-olinuxino.dtb \ | 372 | sun5i-a13-olinuxino.dtb \ |
| 345 | sun5i-a13-olinuxino-micro.dtb \ | 373 | sun5i-a13-olinuxino-micro.dtb |
| 374 | dtb-$(CONFIG_MACH_SUN6I) += \ | ||
| 375 | sun6i-a31-app4-evb1.dtb \ | ||
| 346 | sun6i-a31-colombus.dtb \ | 376 | sun6i-a31-colombus.dtb \ |
| 377 | sun6i-a31-m9.dtb | ||
| 378 | dtb-$(CONFIG_MACH_SUN7I) += \ | ||
| 347 | sun7i-a20-cubieboard2.dtb \ | 379 | sun7i-a20-cubieboard2.dtb \ |
| 348 | sun7i-a20-cubietruck.dtb \ | 380 | sun7i-a20-cubietruck.dtb \ |
| 381 | sun7i-a20-i12-tvbox.dtb \ | ||
| 349 | sun7i-a20-olinuxino-micro.dtb | 382 | sun7i-a20-olinuxino-micro.dtb |
| 350 | dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ | 383 | dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ |
| 351 | tegra20-iris-512.dtb \ | 384 | tegra20-iris-512.dtb \ |
| @@ -360,7 +393,11 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ | |||
| 360 | tegra30-beaver.dtb \ | 393 | tegra30-beaver.dtb \ |
| 361 | tegra30-cardhu-a02.dtb \ | 394 | tegra30-cardhu-a02.dtb \ |
| 362 | tegra30-cardhu-a04.dtb \ | 395 | tegra30-cardhu-a04.dtb \ |
| 396 | tegra30-colibri-eval-v3.dtb \ | ||
| 363 | tegra114-dalmore.dtb \ | 397 | tegra114-dalmore.dtb \ |
| 398 | tegra114-roth.dtb \ | ||
| 399 | tegra114-tn7.dtb \ | ||
| 400 | tegra124-jetson-tk1.dtb \ | ||
| 364 | tegra124-venice2.dtb | 401 | tegra124-venice2.dtb |
| 365 | dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb | 402 | dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb |
| 366 | dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ | 403 | dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ |
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 2e7d932887b5..bde1777b62be 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi | |||
| @@ -182,31 +182,31 @@ | |||
| 182 | 182 | ||
| 183 | &usb { | 183 | &usb { |
| 184 | status = "okay"; | 184 | status = "okay"; |
| 185 | }; | ||
| 185 | 186 | ||
| 186 | control@44e10620 { | 187 | &usb_ctrl_mod { |
| 187 | status = "okay"; | 188 | status = "okay"; |
| 188 | }; | 189 | }; |
| 189 | 190 | ||
| 190 | usb-phy@47401300 { | 191 | &usb0_phy { |
| 191 | status = "okay"; | 192 | status = "okay"; |
| 192 | }; | 193 | }; |
| 193 | 194 | ||
| 194 | usb-phy@47401b00 { | 195 | &usb1_phy { |
| 195 | status = "okay"; | 196 | status = "okay"; |
| 196 | }; | 197 | }; |
| 197 | 198 | ||
| 198 | usb@47401000 { | 199 | &usb0 { |
| 199 | status = "okay"; | 200 | status = "okay"; |
| 200 | }; | 201 | }; |
| 201 | 202 | ||
| 202 | usb@47401800 { | 203 | &usb1 { |
| 203 | status = "okay"; | 204 | status = "okay"; |
| 204 | dr_mode = "host"; | 205 | dr_mode = "host"; |
| 205 | }; | 206 | }; |
| 206 | 207 | ||
| 207 | dma-controller@47402000 { | 208 | &cppi41dma { |
| 208 | status = "okay"; | 209 | status = "okay"; |
| 209 | }; | ||
| 210 | }; | 210 | }; |
| 211 | 211 | ||
| 212 | &i2c0 { | 212 | &i2c0 { |
| @@ -280,13 +280,14 @@ | |||
| 280 | pinctrl-names = "default", "sleep"; | 280 | pinctrl-names = "default", "sleep"; |
| 281 | pinctrl-0 = <&cpsw_default>; | 281 | pinctrl-0 = <&cpsw_default>; |
| 282 | pinctrl-1 = <&cpsw_sleep>; | 282 | pinctrl-1 = <&cpsw_sleep>; |
| 283 | 283 | status = "okay"; | |
| 284 | }; | 284 | }; |
| 285 | 285 | ||
| 286 | &davinci_mdio { | 286 | &davinci_mdio { |
| 287 | pinctrl-names = "default", "sleep"; | 287 | pinctrl-names = "default", "sleep"; |
| 288 | pinctrl-0 = <&davinci_mdio_default>; | 288 | pinctrl-0 = <&davinci_mdio_default>; |
| 289 | pinctrl-1 = <&davinci_mdio_sleep>; | 289 | pinctrl-1 = <&davinci_mdio_sleep>; |
| 290 | status = "okay"; | ||
| 290 | }; | 291 | }; |
| 291 | 292 | ||
| 292 | &mmc1 { | 293 | &mmc1 { |
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index 6b71ad95a5cf..305975d3f531 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts | |||
| @@ -26,7 +26,6 @@ | |||
| 26 | pinctrl-0 = <&emmc_pins>; | 26 | pinctrl-0 = <&emmc_pins>; |
| 27 | bus-width = <8>; | 27 | bus-width = <8>; |
| 28 | status = "okay"; | 28 | status = "okay"; |
| 29 | ti,vcc-aux-disable-is-sleep; | ||
| 30 | }; | 29 | }; |
| 31 | 30 | ||
| 32 | &am33xx_pinmux { | 31 | &am33xx_pinmux { |
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 6028217ace0f..ecb267767cf5 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts | |||
| @@ -268,34 +268,34 @@ | |||
| 268 | 268 | ||
| 269 | lcd_pins_s0: lcd_pins_s0 { | 269 | lcd_pins_s0: lcd_pins_s0 { |
| 270 | pinctrl-single,pins = < | 270 | pinctrl-single,pins = < |
| 271 | 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */ | 271 | 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ |
| 272 | 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */ | 272 | 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ |
| 273 | 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */ | 273 | 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ |
| 274 | 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */ | 274 | 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ |
| 275 | 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */ | 275 | 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ |
| 276 | 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */ | 276 | 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ |
| 277 | 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */ | 277 | 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ |
| 278 | 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */ | 278 | 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ |
| 279 | 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */ | 279 | 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ |
| 280 | 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */ | 280 | 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ |
| 281 | 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */ | 281 | 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ |
| 282 | 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */ | 282 | 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ |
| 283 | 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */ | 283 | 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ |
| 284 | 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */ | 284 | 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ |
| 285 | 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */ | 285 | 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ |
| 286 | 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */ | 286 | 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ |
| 287 | 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */ | 287 | 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ |
| 288 | 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */ | 288 | 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ |
| 289 | 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */ | 289 | 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ |
| 290 | 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */ | 290 | 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ |
| 291 | 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */ | 291 | 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ |
| 292 | 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */ | 292 | 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ |
| 293 | 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */ | 293 | 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ |
| 294 | 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */ | 294 | 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ |
| 295 | 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */ | 295 | 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ |
| 296 | 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */ | 296 | 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ |
| 297 | 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */ | 297 | 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ |
| 298 | 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */ | 298 | 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ |
| 299 | >; | 299 | >; |
| 300 | }; | 300 | }; |
| 301 | 301 | ||
| @@ -330,31 +330,31 @@ | |||
| 330 | 330 | ||
| 331 | &usb { | 331 | &usb { |
| 332 | status = "okay"; | 332 | status = "okay"; |
| 333 | }; | ||
| 333 | 334 | ||
| 334 | control@44e10620 { | 335 | &usb_ctrl_mod { |
| 335 | status = "okay"; | 336 | status = "okay"; |
| 336 | }; | 337 | }; |
| 337 | 338 | ||
| 338 | usb-phy@47401300 { | 339 | &usb0_phy { |
| 339 | status = "okay"; | 340 | status = "okay"; |
| 340 | }; | 341 | }; |
| 341 | 342 | ||
| 342 | usb-phy@47401b00 { | 343 | &usb1_phy { |
| 343 | status = "okay"; | 344 | status = "okay"; |
| 344 | }; | 345 | }; |
| 345 | 346 | ||
| 346 | usb@47401000 { | 347 | &usb0 { |
| 347 | status = "okay"; | 348 | status = "okay"; |
| 348 | }; | 349 | }; |
| 349 | 350 | ||
| 350 | usb@47401800 { | 351 | &usb1 { |
| 351 | status = "okay"; | 352 | status = "okay"; |
| 352 | dr_mode = "host"; | 353 | dr_mode = "host"; |
| 353 | }; | 354 | }; |
| 354 | 355 | ||
| 355 | dma-controller@47402000 { | 356 | &cppi41dma { |
| 356 | status = "okay"; | 357 | status = "okay"; |
| 357 | }; | ||
| 358 | }; | 358 | }; |
| 359 | 359 | ||
| 360 | &i2c1 { | 360 | &i2c1 { |
| @@ -614,12 +614,14 @@ | |||
| 614 | pinctrl-names = "default", "sleep"; | 614 | pinctrl-names = "default", "sleep"; |
| 615 | pinctrl-0 = <&cpsw_default>; | 615 | pinctrl-0 = <&cpsw_default>; |
| 616 | pinctrl-1 = <&cpsw_sleep>; | 616 | pinctrl-1 = <&cpsw_sleep>; |
| 617 | status = "okay"; | ||
| 617 | }; | 618 | }; |
| 618 | 619 | ||
| 619 | &davinci_mdio { | 620 | &davinci_mdio { |
| 620 | pinctrl-names = "default", "sleep"; | 621 | pinctrl-names = "default", "sleep"; |
| 621 | pinctrl-0 = <&davinci_mdio_default>; | 622 | pinctrl-0 = <&davinci_mdio_default>; |
| 622 | pinctrl-1 = <&davinci_mdio_sleep>; | 623 | pinctrl-1 = <&davinci_mdio_sleep>; |
| 624 | status = "okay"; | ||
| 623 | }; | 625 | }; |
| 624 | 626 | ||
| 625 | &cpsw_emac0 { | 627 | &cpsw_emac0 { |
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index ab238850a7b2..ab9a34ce524c 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts | |||
| @@ -57,6 +57,17 @@ | |||
| 57 | enable-active-high; | 57 | enable-active-high; |
| 58 | }; | 58 | }; |
| 59 | 59 | ||
| 60 | vtt_fixed: fixedregulator@3 { | ||
| 61 | compatible = "regulator-fixed"; | ||
| 62 | regulator-name = "vtt"; | ||
| 63 | regulator-min-microvolt = <1500000>; | ||
| 64 | regulator-max-microvolt = <1500000>; | ||
| 65 | gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>; | ||
| 66 | regulator-always-on; | ||
| 67 | regulator-boot-on; | ||
| 68 | enable-active-high; | ||
| 69 | }; | ||
| 70 | |||
| 60 | leds { | 71 | leds { |
| 61 | pinctrl-names = "default"; | 72 | pinctrl-names = "default"; |
| 62 | pinctrl-0 = <&user_leds_s0>; | 73 | pinctrl-0 = <&user_leds_s0>; |
| @@ -363,31 +374,31 @@ | |||
| 363 | 374 | ||
| 364 | &usb { | 375 | &usb { |
| 365 | status = "okay"; | 376 | status = "okay"; |
| 377 | }; | ||
| 366 | 378 | ||
| 367 | control@44e10620 { | 379 | &usb_ctrl_mod { |
| 368 | status = "okay"; | 380 | status = "okay"; |
| 369 | }; | 381 | }; |
| 370 | 382 | ||
| 371 | usb-phy@47401300 { | 383 | &usb0_phy { |
| 372 | status = "okay"; | 384 | status = "okay"; |
| 373 | }; | 385 | }; |
| 374 | 386 | ||
| 375 | usb-phy@47401b00 { | 387 | &usb1_phy { |
| 376 | status = "okay"; | 388 | status = "okay"; |
| 377 | }; | 389 | }; |
| 378 | 390 | ||
| 379 | usb@47401000 { | 391 | &usb0 { |
| 380 | status = "okay"; | 392 | status = "okay"; |
| 381 | }; | 393 | }; |
| 382 | 394 | ||
| 383 | usb@47401800 { | 395 | &usb1 { |
| 384 | status = "okay"; | 396 | status = "okay"; |
| 385 | dr_mode = "host"; | 397 | dr_mode = "host"; |
| 386 | }; | 398 | }; |
| 387 | 399 | ||
| 388 | dma-controller@47402000 { | 400 | &cppi41dma { |
| 389 | status = "okay"; | 401 | status = "okay"; |
| 390 | }; | ||
| 391 | }; | 402 | }; |
| 392 | 403 | ||
| 393 | &epwmss2 { | 404 | &epwmss2 { |
| @@ -484,12 +495,14 @@ | |||
| 484 | pinctrl-0 = <&cpsw_default>; | 495 | pinctrl-0 = <&cpsw_default>; |
| 485 | pinctrl-1 = <&cpsw_sleep>; | 496 | pinctrl-1 = <&cpsw_sleep>; |
| 486 | dual_emac = <1>; | 497 | dual_emac = <1>; |
| 498 | status = "okay"; | ||
| 487 | }; | 499 | }; |
| 488 | 500 | ||
| 489 | &davinci_mdio { | 501 | &davinci_mdio { |
| 490 | pinctrl-names = "default", "sleep"; | 502 | pinctrl-names = "default", "sleep"; |
| 491 | pinctrl-0 = <&davinci_mdio_default>; | 503 | pinctrl-0 = <&davinci_mdio_default>; |
| 492 | pinctrl-1 = <&davinci_mdio_sleep>; | 504 | pinctrl-1 = <&davinci_mdio_sleep>; |
| 505 | status = "okay"; | ||
| 493 | }; | 506 | }; |
| 494 | 507 | ||
| 495 | &cpsw_emac0 { | 508 | &cpsw_emac0 { |
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index 9f22c189f636..8a0a72dc7dd7 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi | |||
| @@ -95,6 +95,14 @@ | |||
| 95 | }; | 95 | }; |
| 96 | }; | 96 | }; |
| 97 | 97 | ||
| 98 | &mac { | ||
| 99 | status = "okay"; | ||
| 100 | }; | ||
| 101 | |||
| 102 | &davinci_mdio { | ||
| 103 | status = "okay"; | ||
| 104 | }; | ||
| 105 | |||
| 98 | &cpsw_emac0 { | 106 | &cpsw_emac0 { |
| 99 | phy_id = <&davinci_mdio>, <0>; | 107 | phy_id = <&davinci_mdio>, <0>; |
| 100 | }; | 108 | }; |
| @@ -200,31 +208,31 @@ | |||
| 200 | 208 | ||
| 201 | &usb { | 209 | &usb { |
| 202 | status = "okay"; | 210 | status = "okay"; |
| 211 | }; | ||
| 203 | 212 | ||
| 204 | control@44e10620 { | 213 | &usb_ctrl_mod { |
| 205 | status = "okay"; | 214 | status = "okay"; |
| 206 | }; | 215 | }; |
| 207 | 216 | ||
| 208 | usb-phy@47401300 { | 217 | &usb0_phy { |
| 209 | status = "okay"; | 218 | status = "okay"; |
| 210 | }; | 219 | }; |
| 211 | 220 | ||
| 212 | usb-phy@47401b00 { | 221 | &usb1_phy { |
| 213 | status = "okay"; | 222 | status = "okay"; |
| 214 | }; | 223 | }; |
| 215 | 224 | ||
| 216 | usb@47401000 { | 225 | &usb0 { |
| 217 | status = "okay"; | 226 | status = "okay"; |
| 218 | }; | 227 | }; |
| 219 | 228 | ||
| 220 | usb@47401800 { | 229 | &usb1 { |
| 221 | status = "okay"; | 230 | status = "okay"; |
| 222 | dr_mode = "host"; | 231 | dr_mode = "host"; |
| 223 | }; | 232 | }; |
| 224 | 233 | ||
| 225 | dma-controller@47402000 { | 234 | &cppi41dma { |
| 226 | status = "okay"; | 235 | status = "okay"; |
| 227 | }; | ||
| 228 | }; | 236 | }; |
| 229 | 237 | ||
| 230 | #include "tps65910.dtsi" | 238 | #include "tps65910.dtsi" |
diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts index 9907b494b99c..a3466455b171 100644 --- a/arch/arm/boot/dts/am335x-nano.dts +++ b/arch/arm/boot/dts/am335x-nano.dts | |||
| @@ -344,6 +344,11 @@ | |||
| 344 | 344 | ||
| 345 | &mac { | 345 | &mac { |
| 346 | dual_emac = <1>; | 346 | dual_emac = <1>; |
| 347 | status = "okay"; | ||
| 348 | }; | ||
| 349 | |||
| 350 | &davinci_mdio { | ||
| 351 | status = "okay"; | ||
| 347 | }; | 352 | }; |
| 348 | 353 | ||
| 349 | &cpsw_emac0 { | 354 | &cpsw_emac0 { |
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index 9ccfe508dea2..712edce7d6fb 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi | |||
| @@ -96,47 +96,29 @@ | |||
| 96 | clock-div = <1>; | 96 | clock-div = <1>; |
| 97 | }; | 97 | }; |
| 98 | 98 | ||
| 99 | ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk { | 99 | ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { |
| 100 | #clock-cells = <0>; | 100 | #clock-cells = <0>; |
| 101 | compatible = "ti,composite-no-wait-gate-clock"; | 101 | compatible = "ti,gate-clock"; |
| 102 | clocks = <&dpll_per_m2_ck>; | 102 | clocks = <&dpll_per_m2_ck>; |
| 103 | ti,bit-shift = <0>; | 103 | ti,bit-shift = <0>; |
| 104 | reg = <0x0664>; | 104 | reg = <0x0664>; |
| 105 | }; | 105 | }; |
| 106 | 106 | ||
| 107 | ehrpwm0_tbclk: ehrpwm0_tbclk { | 107 | ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { |
| 108 | #clock-cells = <0>; | ||
| 109 | compatible = "ti,composite-clock"; | ||
| 110 | clocks = <&ehrpwm0_gate_tbclk>; | ||
| 111 | }; | ||
| 112 | |||
| 113 | ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk { | ||
| 114 | #clock-cells = <0>; | 108 | #clock-cells = <0>; |
| 115 | compatible = "ti,composite-no-wait-gate-clock"; | 109 | compatible = "ti,gate-clock"; |
| 116 | clocks = <&dpll_per_m2_ck>; | 110 | clocks = <&dpll_per_m2_ck>; |
| 117 | ti,bit-shift = <1>; | 111 | ti,bit-shift = <1>; |
| 118 | reg = <0x0664>; | 112 | reg = <0x0664>; |
| 119 | }; | 113 | }; |
| 120 | 114 | ||
| 121 | ehrpwm1_tbclk: ehrpwm1_tbclk { | 115 | ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { |
| 122 | #clock-cells = <0>; | ||
| 123 | compatible = "ti,composite-clock"; | ||
| 124 | clocks = <&ehrpwm1_gate_tbclk>; | ||
| 125 | }; | ||
| 126 | |||
| 127 | ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk { | ||
| 128 | #clock-cells = <0>; | 116 | #clock-cells = <0>; |
| 129 | compatible = "ti,composite-no-wait-gate-clock"; | 117 | compatible = "ti,gate-clock"; |
| 130 | clocks = <&dpll_per_m2_ck>; | 118 | clocks = <&dpll_per_m2_ck>; |
| 131 | ti,bit-shift = <2>; | 119 | ti,bit-shift = <2>; |
| 132 | reg = <0x0664>; | 120 | reg = <0x0664>; |
| 133 | }; | 121 | }; |
| 134 | |||
| 135 | ehrpwm2_tbclk: ehrpwm2_tbclk { | ||
| 136 | #clock-cells = <0>; | ||
| 137 | compatible = "ti,composite-clock"; | ||
| 138 | clocks = <&ehrpwm2_gate_tbclk>; | ||
| 139 | }; | ||
| 140 | }; | 122 | }; |
| 141 | &prcm_clocks { | 123 | &prcm_clocks { |
| 142 | clk_32768_ck: clk_32768_ck { | 124 | clk_32768_ck: clk_32768_ck { |
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 7ad75b4e0663..9f53e824b037 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi | |||
| @@ -147,9 +147,6 @@ | |||
| 147 | <0x44e10f90 0x40>; | 147 | <0x44e10f90 0x40>; |
| 148 | interrupts = <12 13 14>; | 148 | interrupts = <12 13 14>; |
| 149 | #dma-cells = <1>; | 149 | #dma-cells = <1>; |
| 150 | dma-channels = <64>; | ||
| 151 | ti,edma-regions = <4>; | ||
| 152 | ti,edma-slots = <256>; | ||
| 153 | }; | 150 | }; |
| 154 | 151 | ||
| 155 | gpio0: gpio@44e07000 { | 152 | gpio0: gpio@44e07000 { |
| @@ -688,6 +685,7 @@ | |||
| 688 | */ | 685 | */ |
| 689 | interrupts = <40 41 42 43>; | 686 | interrupts = <40 41 42 43>; |
| 690 | ranges; | 687 | ranges; |
| 688 | status = "disabled"; | ||
| 691 | 689 | ||
| 692 | davinci_mdio: mdio@4a101000 { | 690 | davinci_mdio: mdio@4a101000 { |
| 693 | compatible = "ti,davinci_mdio"; | 691 | compatible = "ti,davinci_mdio"; |
| @@ -696,6 +694,7 @@ | |||
| 696 | ti,hwmods = "davinci_mdio"; | 694 | ti,hwmods = "davinci_mdio"; |
| 697 | bus_freq = <1000000>; | 695 | bus_freq = <1000000>; |
| 698 | reg = <0x4a101000 0x100>; | 696 | reg = <0x4a101000 0x100>; |
| 697 | status = "disabled"; | ||
| 699 | }; | 698 | }; |
| 700 | 699 | ||
| 701 | cpsw_emac0: slave@4a100200 { | 700 | cpsw_emac0: slave@4a100200 { |
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index d1f8707ff1df..794c73e5c4e4 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi | |||
| @@ -67,11 +67,15 @@ | |||
| 67 | }; | 67 | }; |
| 68 | 68 | ||
| 69 | ocp { | 69 | ocp { |
| 70 | compatible = "simple-bus"; | 70 | compatible = "ti,am4372-l3-noc", "simple-bus"; |
| 71 | #address-cells = <1>; | 71 | #address-cells = <1>; |
| 72 | #size-cells = <1>; | 72 | #size-cells = <1>; |
| 73 | ranges; | 73 | ranges; |
| 74 | ti,hwmods = "l3_main"; | 74 | ti,hwmods = "l3_main"; |
| 75 | reg = <0x44000000 0x400000 | ||
| 76 | 0x44800000 0x400000>; | ||
| 77 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | ||
| 78 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | ||
| 75 | 79 | ||
| 76 | prcm: prcm@44df0000 { | 80 | prcm: prcm@44df0000 { |
| 77 | compatible = "ti,am4-prcm"; | 81 | compatible = "ti,am4-prcm"; |
| @@ -108,9 +112,6 @@ | |||
| 108 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | 112 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 109 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | 113 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 110 | #dma-cells = <1>; | 114 | #dma-cells = <1>; |
| 111 | dma-channels = <64>; | ||
| 112 | ti,edma-regions = <4>; | ||
| 113 | ti,edma-slots = <256>; | ||
| 114 | }; | 115 | }; |
| 115 | 116 | ||
| 116 | uart0: serial@44e09000 { | 117 | uart0: serial@44e09000 { |
| @@ -521,6 +522,12 @@ | |||
| 521 | /* Filled in by U-Boot */ | 522 | /* Filled in by U-Boot */ |
| 522 | mac-address = [ 00 00 00 00 00 00 ]; | 523 | mac-address = [ 00 00 00 00 00 00 ]; |
| 523 | }; | 524 | }; |
| 525 | |||
| 526 | phy_sel: cpsw-phy-sel@44e10650 { | ||
| 527 | compatible = "ti,am43xx-cpsw-phy-sel"; | ||
| 528 | reg= <0x44e10650 0x4>; | ||
| 529 | reg-names = "gmii-sel"; | ||
| 530 | }; | ||
| 524 | }; | 531 | }; |
| 525 | 532 | ||
| 526 | epwmss0: epwmss@48300000 { | 533 | epwmss0: epwmss@48300000 { |
| @@ -735,6 +742,121 @@ | |||
| 735 | #size-cells = <1>; | 742 | #size-cells = <1>; |
| 736 | status = "disabled"; | 743 | status = "disabled"; |
| 737 | }; | 744 | }; |
| 745 | |||
| 746 | am43xx_control_usb2phy1: control-phy@44e10620 { | ||
| 747 | compatible = "ti,control-phy-usb2-am437"; | ||
| 748 | reg = <0x44e10620 0x4>; | ||
| 749 | reg-names = "power"; | ||
| 750 | }; | ||
| 751 | |||
| 752 | am43xx_control_usb2phy2: control-phy@0x44e10628 { | ||
| 753 | compatible = "ti,control-phy-usb2-am437"; | ||
| 754 | reg = <0x44e10628 0x4>; | ||
| 755 | reg-names = "power"; | ||
| 756 | }; | ||
| 757 | |||
| 758 | ocp2scp0: ocp2scp@483a8000 { | ||
| 759 | compatible = "ti,omap-ocp2scp"; | ||
| 760 | #address-cells = <1>; | ||
| 761 | #size-cells = <1>; | ||
| 762 | ranges; | ||
| 763 | ti,hwmods = "ocp2scp0"; | ||
| 764 | |||
| 765 | usb2_phy1: phy@483a8000 { | ||
| 766 | compatible = "ti,am437x-usb2"; | ||
| 767 | reg = <0x483a8000 0x8000>; | ||
| 768 | ctrl-module = <&am43xx_control_usb2phy1>; | ||
| 769 | clocks = <&usb_phy0_always_on_clk32k>, | ||
| 770 | <&usb_otg_ss0_refclk960m>; | ||
| 771 | clock-names = "wkupclk", "refclk"; | ||
| 772 | #phy-cells = <0>; | ||
| 773 | status = "disabled"; | ||
| 774 | }; | ||
| 775 | }; | ||
| 776 | |||
| 777 | ocp2scp1: ocp2scp@483e8000 { | ||
| 778 | compatible = "ti,omap-ocp2scp"; | ||
| 779 | #address-cells = <1>; | ||
| 780 | #size-cells = <1>; | ||
| 781 | ranges; | ||
| 782 | ti,hwmods = "ocp2scp1"; | ||
| 783 | |||
| 784 | usb2_phy2: phy@483e8000 { | ||
| 785 | compatible = "ti,am437x-usb2"; | ||
| 786 | reg = <0x483e8000 0x8000>; | ||
| 787 | ctrl-module = <&am43xx_control_usb2phy2>; | ||
| 788 | clocks = <&usb_phy1_always_on_clk32k>, | ||
| 789 | <&usb_otg_ss1_refclk960m>; | ||
| 790 | clock-names = "wkupclk", "refclk"; | ||
| 791 | #phy-cells = <0>; | ||
| 792 | status = "disabled"; | ||
| 793 | }; | ||
| 794 | }; | ||
| 795 | |||
| 796 | dwc3_1: omap_dwc3@48380000 { | ||
| 797 | compatible = "ti,am437x-dwc3"; | ||
| 798 | ti,hwmods = "usb_otg_ss0"; | ||
| 799 | reg = <0x48380000 0x10000>; | ||
| 800 | interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; | ||
| 801 | #address-cells = <1>; | ||
| 802 | #size-cells = <1>; | ||
| 803 | utmi-mode = <1>; | ||
| 804 | ranges; | ||
| 805 | |||
| 806 | usb1: usb@48390000 { | ||
| 807 | compatible = "synopsys,dwc3"; | ||
| 808 | reg = <0x48390000 0x17000>; | ||
| 809 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; | ||
| 810 | phys = <&usb2_phy1>; | ||
| 811 | phy-names = "usb2-phy"; | ||
| 812 | maximum-speed = "high-speed"; | ||
| 813 | dr_mode = "otg"; | ||
| 814 | status = "disabled"; | ||
| 815 | }; | ||
| 816 | }; | ||
| 817 | |||
| 818 | dwc3_2: omap_dwc3@483c0000 { | ||
| 819 | compatible = "ti,am437x-dwc3"; | ||
| 820 | ti,hwmods = "usb_otg_ss1"; | ||
| 821 | reg = <0x483c0000 0x10000>; | ||
| 822 | interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; | ||
| 823 | #address-cells = <1>; | ||
| 824 | #size-cells = <1>; | ||
| 825 | utmi-mode = <1>; | ||
| 826 | ranges; | ||
| 827 | |||
| 828 | usb2: usb@483d0000 { | ||
| 829 | compatible = "synopsys,dwc3"; | ||
| 830 | reg = <0x483d0000 0x17000>; | ||
| 831 | interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; | ||
| 832 | phys = <&usb2_phy2>; | ||
| 833 | phy-names = "usb2-phy"; | ||
| 834 | maximum-speed = "high-speed"; | ||
| 835 | dr_mode = "otg"; | ||
| 836 | status = "disabled"; | ||
| 837 | }; | ||
| 838 | }; | ||
| 839 | |||
| 840 | qspi: qspi@47900000 { | ||
| 841 | compatible = "ti,am4372-qspi"; | ||
| 842 | reg = <0x47900000 0x100>; | ||
| 843 | #address-cells = <1>; | ||
| 844 | #size-cells = <0>; | ||
| 845 | ti,hwmods = "qspi"; | ||
| 846 | interrupts = <0 138 0x4>; | ||
| 847 | num-cs = <4>; | ||
| 848 | status = "disabled"; | ||
| 849 | }; | ||
| 850 | |||
| 851 | hdq: hdq@48347000 { | ||
| 852 | compatible = "ti,am43xx-hdq"; | ||
| 853 | reg = <0x48347000 0x1000>; | ||
| 854 | interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; | ||
| 855 | clocks = <&func_12m_clk>; | ||
| 856 | clock-names = "fck"; | ||
| 857 | ti,hwmods = "hdq1w"; | ||
| 858 | status = "disabled"; | ||
| 859 | }; | ||
| 738 | }; | 860 | }; |
| 739 | }; | 861 | }; |
| 740 | 862 | ||
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index a055f7f0f14a..c25d15837ce9 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts | |||
| @@ -27,6 +27,17 @@ | |||
| 27 | enable-active-high; | 27 | enable-active-high; |
| 28 | }; | 28 | }; |
| 29 | 29 | ||
| 30 | vtt_fixed: fixedregulator-vtt { | ||
| 31 | compatible = "regulator-fixed"; | ||
| 32 | regulator-name = "vtt_fixed"; | ||
| 33 | regulator-min-microvolt = <1500000>; | ||
| 34 | regulator-max-microvolt = <1500000>; | ||
| 35 | regulator-always-on; | ||
| 36 | regulator-boot-on; | ||
| 37 | enable-active-high; | ||
| 38 | gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; | ||
| 39 | }; | ||
| 40 | |||
| 30 | backlight { | 41 | backlight { |
| 31 | compatible = "pwm-backlight"; | 42 | compatible = "pwm-backlight"; |
| 32 | pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; | 43 | pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; |
| @@ -81,6 +92,85 @@ | |||
| 81 | 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ | 92 | 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ |
| 82 | >; | 93 | >; |
| 83 | }; | 94 | }; |
| 95 | |||
| 96 | pixcir_ts_pins: pixcir_ts_pins { | ||
| 97 | pinctrl-single,pins = < | ||
| 98 | 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ | ||
| 99 | >; | ||
| 100 | }; | ||
| 101 | |||
| 102 | cpsw_default: cpsw_default { | ||
| 103 | pinctrl-single,pins = < | ||
| 104 | /* Slave 1 */ | ||
| 105 | 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ | ||
| 106 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ | ||
| 107 | 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ | ||
| 108 | 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ | ||
| 109 | 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ | ||
| 110 | 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ | ||
| 111 | 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ | ||
| 112 | 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ | ||
| 113 | 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ | ||
| 114 | 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ | ||
| 115 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ | ||
| 116 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ | ||
| 117 | >; | ||
| 118 | }; | ||
| 119 | |||
| 120 | cpsw_sleep: cpsw_sleep { | ||
| 121 | pinctrl-single,pins = < | ||
| 122 | /* Slave 1 reset value */ | ||
| 123 | 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 124 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 125 | 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 126 | 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 127 | 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 128 | 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 129 | 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 130 | 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 131 | 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 132 | 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 133 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 134 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 135 | >; | ||
| 136 | }; | ||
| 137 | |||
| 138 | davinci_mdio_default: davinci_mdio_default { | ||
| 139 | pinctrl-single,pins = < | ||
| 140 | /* MDIO */ | ||
| 141 | 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ | ||
| 142 | 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | ||
| 143 | >; | ||
| 144 | }; | ||
| 145 | |||
| 146 | davinci_mdio_sleep: davinci_mdio_sleep { | ||
| 147 | pinctrl-single,pins = < | ||
| 148 | /* MDIO reset value */ | ||
| 149 | 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 150 | 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 151 | >; | ||
| 152 | }; | ||
| 153 | |||
| 154 | nand_flash_x8: nand_flash_x8 { | ||
| 155 | pinctrl-single,pins = < | ||
| 156 | 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */ | ||
| 157 | 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ | ||
| 158 | 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ | ||
| 159 | 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ | ||
| 160 | 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ | ||
| 161 | 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ | ||
| 162 | 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ | ||
| 163 | 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ | ||
| 164 | 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ | ||
| 165 | 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ | ||
| 166 | 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ | ||
| 167 | 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ | ||
| 168 | 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ | ||
| 169 | 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ | ||
| 170 | 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ | ||
| 171 | 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ | ||
| 172 | >; | ||
| 173 | }; | ||
| 84 | }; | 174 | }; |
| 85 | 175 | ||
| 86 | &i2c0 { | 176 | &i2c0 { |
| @@ -93,6 +183,20 @@ | |||
| 93 | status = "okay"; | 183 | status = "okay"; |
| 94 | pinctrl-names = "default"; | 184 | pinctrl-names = "default"; |
| 95 | pinctrl-0 = <&i2c1_pins>; | 185 | pinctrl-0 = <&i2c1_pins>; |
| 186 | |||
| 187 | pixcir_ts@5c { | ||
| 188 | compatible = "pixcir,pixcir_tangoc"; | ||
| 189 | pinctrl-names = "default"; | ||
| 190 | pinctrl-0 = <&pixcir_ts_pins>; | ||
| 191 | reg = <0x5c>; | ||
| 192 | interrupt-parent = <&gpio3>; | ||
| 193 | interrupts = <22 0>; | ||
| 194 | |||
| 195 | attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; | ||
| 196 | |||
| 197 | x-size = <1024>; | ||
| 198 | y-size = <600>; | ||
| 199 | }; | ||
| 96 | }; | 200 | }; |
| 97 | 201 | ||
| 98 | &epwmss0 { | 202 | &epwmss0 { |
| @@ -130,3 +234,128 @@ | |||
| 130 | pinctrl-0 = <&mmc1_pins>; | 234 | pinctrl-0 = <&mmc1_pins>; |
| 131 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; | 235 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; |
| 132 | }; | 236 | }; |
| 237 | |||
| 238 | &usb2_phy1 { | ||
| 239 | status = "okay"; | ||
| 240 | }; | ||
| 241 | |||
| 242 | &usb1 { | ||
| 243 | dr_mode = "peripheral"; | ||
| 244 | status = "okay"; | ||
| 245 | }; | ||
| 246 | |||
| 247 | &usb2_phy2 { | ||
| 248 | status = "okay"; | ||
| 249 | }; | ||
| 250 | |||
| 251 | &usb2 { | ||
| 252 | dr_mode = "host"; | ||
| 253 | status = "okay"; | ||
| 254 | }; | ||
| 255 | |||
| 256 | &mac { | ||
| 257 | slaves = <1>; | ||
| 258 | pinctrl-names = "default", "sleep"; | ||
| 259 | pinctrl-0 = <&cpsw_default>; | ||
| 260 | pinctrl-1 = <&cpsw_sleep>; | ||
| 261 | status = "okay"; | ||
| 262 | }; | ||
| 263 | |||
| 264 | &davinci_mdio { | ||
| 265 | pinctrl-names = "default", "sleep"; | ||
| 266 | pinctrl-0 = <&davinci_mdio_default>; | ||
| 267 | pinctrl-1 = <&davinci_mdio_sleep>; | ||
| 268 | status = "okay"; | ||
| 269 | }; | ||
| 270 | |||
| 271 | &cpsw_emac0 { | ||
| 272 | phy_id = <&davinci_mdio>, <0>; | ||
| 273 | phy-mode = "rgmii"; | ||
| 274 | }; | ||
| 275 | |||
| 276 | &elm { | ||
| 277 | status = "okay"; | ||
| 278 | }; | ||
| 279 | |||
| 280 | &gpmc { | ||
| 281 | status = "okay"; | ||
| 282 | pinctrl-names = "default"; | ||
| 283 | pinctrl-0 = <&nand_flash_x8>; | ||
| 284 | ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ | ||
| 285 | nand@0,0 { | ||
| 286 | reg = <0 0 4>; /* device IO registers */ | ||
| 287 | ti,nand-ecc-opt = "bch8"; | ||
| 288 | ti,elm-id = <&elm>; | ||
| 289 | nand-bus-width = <8>; | ||
| 290 | gpmc,device-width = <1>; | ||
| 291 | gpmc,sync-clk-ps = <0>; | ||
| 292 | gpmc,cs-on-ns = <0>; | ||
| 293 | gpmc,cs-rd-off-ns = <40>; | ||
| 294 | gpmc,cs-wr-off-ns = <40>; | ||
| 295 | gpmc,adv-on-ns = <0>; | ||
| 296 | gpmc,adv-rd-off-ns = <25>; | ||
| 297 | gpmc,adv-wr-off-ns = <25>; | ||
| 298 | gpmc,we-on-ns = <0>; | ||
| 299 | gpmc,we-off-ns = <20>; | ||
| 300 | gpmc,oe-on-ns = <3>; | ||
| 301 | gpmc,oe-off-ns = <30>; | ||
| 302 | gpmc,access-ns = <30>; | ||
| 303 | gpmc,rd-cycle-ns = <40>; | ||
| 304 | gpmc,wr-cycle-ns = <40>; | ||
| 305 | gpmc,wait-pin = <0>; | ||
| 306 | gpmc,wait-on-read; | ||
| 307 | gpmc,wait-on-write; | ||
| 308 | gpmc,bus-turnaround-ns = <0>; | ||
| 309 | gpmc,cycle2cycle-delay-ns = <0>; | ||
| 310 | gpmc,clk-activation-ns = <0>; | ||
| 311 | gpmc,wait-monitoring-ns = <0>; | ||
| 312 | gpmc,wr-access-ns = <40>; | ||
| 313 | gpmc,wr-data-mux-bus-ns = <0>; | ||
| 314 | /* MTD partition table */ | ||
| 315 | /* All SPL-* partitions are sized to minimal length | ||
| 316 | * which can be independently programmable. For | ||
| 317 | * NAND flash this is equal to size of erase-block */ | ||
| 318 | #address-cells = <1>; | ||
| 319 | #size-cells = <1>; | ||
| 320 | partition@0 { | ||
| 321 | label = "NAND.SPL"; | ||
| 322 | reg = <0x00000000 0x00040000>; | ||
| 323 | }; | ||
| 324 | partition@1 { | ||
| 325 | label = "NAND.SPL.backup1"; | ||
| 326 | reg = <0x00040000 0x00040000>; | ||
| 327 | }; | ||
| 328 | partition@2 { | ||
| 329 | label = "NAND.SPL.backup2"; | ||
| 330 | reg = <0x00080000 0x00040000>; | ||
| 331 | }; | ||
| 332 | partition@3 { | ||
| 333 | label = "NAND.SPL.backup3"; | ||
| 334 | reg = <0x000c0000 0x00040000>; | ||
| 335 | }; | ||
| 336 | partition@4 { | ||
| 337 | label = "NAND.u-boot-spl-os"; | ||
| 338 | reg = <0x00100000 0x00080000>; | ||
| 339 | }; | ||
| 340 | partition@5 { | ||
| 341 | label = "NAND.u-boot"; | ||
| 342 | reg = <0x00180000 0x00100000>; | ||
| 343 | }; | ||
| 344 | partition@6 { | ||
| 345 | label = "NAND.u-boot-env"; | ||
| 346 | reg = <0x00280000 0x00040000>; | ||
| 347 | }; | ||
| 348 | partition@7 { | ||
| 349 | label = "NAND.u-boot-env.backup1"; | ||
| 350 | reg = <0x002c0000 0x00040000>; | ||
| 351 | }; | ||
| 352 | partition@8 { | ||
| 353 | label = "NAND.kernel"; | ||
| 354 | reg = <0x00300000 0x00700000>; | ||
| 355 | }; | ||
| 356 | partition@9 { | ||
| 357 | label = "NAND.file-system"; | ||
| 358 | reg = <0x00a00000 0x1f600000>; | ||
| 359 | }; | ||
| 360 | }; | ||
| 361 | }; | ||
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 167dbc8494de..ad362c50e32e 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts | |||
| @@ -138,6 +138,29 @@ | |||
| 138 | 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ | 138 | 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ |
| 139 | >; | 139 | >; |
| 140 | }; | 140 | }; |
| 141 | |||
| 142 | qspi1_default: qspi1_default { | ||
| 143 | pinctrl-single,pins = < | ||
| 144 | 0x7c (PIN_INPUT_PULLUP | MUX_MODE3) | ||
| 145 | 0x88 (PIN_INPUT_PULLUP | MUX_MODE2) | ||
| 146 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE3) | ||
| 147 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE3) | ||
| 148 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE3) | ||
| 149 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) | ||
| 150 | >; | ||
| 151 | }; | ||
| 152 | |||
| 153 | pixcir_ts_pins: pixcir_ts_pins { | ||
| 154 | pinctrl-single,pins = < | ||
| 155 | 0x44 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ | ||
| 156 | >; | ||
| 157 | }; | ||
| 158 | |||
| 159 | hdq_pins: pinmux_hdq_pins { | ||
| 160 | pinctrl-single,pins = < | ||
| 161 | 0x234 (PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ | ||
| 162 | >; | ||
| 163 | }; | ||
| 141 | }; | 164 | }; |
| 142 | 165 | ||
| 143 | matrix_keypad: matrix_keypad@0 { | 166 | matrix_keypad: matrix_keypad@0 { |
| @@ -226,7 +249,9 @@ | |||
| 226 | }; | 249 | }; |
| 227 | 250 | ||
| 228 | pixcir_ts@5c { | 251 | pixcir_ts@5c { |
| 229 | compatible = "pixcir,pixcir_ts"; | 252 | compatible = "pixcir,pixcir_tangoc"; |
| 253 | pinctrl-names = "default"; | ||
| 254 | pinctrl-0 = <&pixcir_ts_pins>; | ||
| 230 | reg = <0x5c>; | 255 | reg = <0x5c>; |
| 231 | interrupt-parent = <&gpio1>; | 256 | interrupt-parent = <&gpio1>; |
| 232 | interrupts = <17 0>; | 257 | interrupts = <17 0>; |
| @@ -234,7 +259,7 @@ | |||
| 234 | attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; | 259 | attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; |
| 235 | 260 | ||
| 236 | x-size = <1024>; | 261 | x-size = <1024>; |
| 237 | y-size = <768>; | 262 | y-size = <600>; |
| 238 | }; | 263 | }; |
| 239 | }; | 264 | }; |
| 240 | 265 | ||
| @@ -341,7 +366,7 @@ | |||
| 341 | }; | 366 | }; |
| 342 | partition@9 { | 367 | partition@9 { |
| 343 | label = "NAND.file-system"; | 368 | label = "NAND.file-system"; |
| 344 | reg = <0x00800000 0x1F600000>; | 369 | reg = <0x00a00000 0x1f600000>; |
| 345 | }; | 370 | }; |
| 346 | }; | 371 | }; |
| 347 | }; | 372 | }; |
| @@ -367,3 +392,79 @@ | |||
| 367 | pinctrl-0 = <&spi1_pins>; | 392 | pinctrl-0 = <&spi1_pins>; |
| 368 | status = "okay"; | 393 | status = "okay"; |
| 369 | }; | 394 | }; |
| 395 | |||
| 396 | &usb2_phy1 { | ||
| 397 | status = "okay"; | ||
| 398 | }; | ||
| 399 | |||
| 400 | &usb1 { | ||
| 401 | dr_mode = "peripheral"; | ||
| 402 | status = "okay"; | ||
| 403 | }; | ||
| 404 | |||
| 405 | &usb2_phy2 { | ||
| 406 | status = "okay"; | ||
| 407 | }; | ||
| 408 | |||
| 409 | &usb2 { | ||
| 410 | dr_mode = "host"; | ||
| 411 | status = "okay"; | ||
| 412 | }; | ||
| 413 | |||
| 414 | &qspi { | ||
| 415 | status = "okay"; | ||
| 416 | pinctrl-names = "default"; | ||
| 417 | pinctrl-0 = <&qspi1_default>; | ||
| 418 | |||
| 419 | spi-max-frequency = <48000000>; | ||
| 420 | m25p80@0 { | ||
| 421 | compatible = "mx66l51235l"; | ||
| 422 | spi-max-frequency = <48000000>; | ||
| 423 | reg = <0>; | ||
| 424 | spi-cpol; | ||
| 425 | spi-cpha; | ||
| 426 | spi-tx-bus-width = <1>; | ||
| 427 | spi-rx-bus-width = <4>; | ||
| 428 | #address-cells = <1>; | ||
| 429 | #size-cells = <1>; | ||
| 430 | |||
| 431 | /* MTD partition table. | ||
| 432 | * The ROM checks the first 512KiB | ||
| 433 | * for a valid file to boot(XIP). | ||
| 434 | */ | ||
| 435 | partition@0 { | ||
| 436 | label = "QSPI.U_BOOT"; | ||
| 437 | reg = <0x00000000 0x000080000>; | ||
| 438 | }; | ||
| 439 | partition@1 { | ||
| 440 | label = "QSPI.U_BOOT.backup"; | ||
| 441 | reg = <0x00080000 0x00080000>; | ||
| 442 | }; | ||
| 443 | partition@2 { | ||
| 444 | label = "QSPI.U-BOOT-SPL_OS"; | ||
| 445 | reg = <0x00100000 0x00010000>; | ||
| 446 | }; | ||
| 447 | partition@3 { | ||
| 448 | label = "QSPI.U_BOOT_ENV"; | ||
| 449 | reg = <0x00110000 0x00010000>; | ||
| 450 | }; | ||
| 451 | partition@4 { | ||
| 452 | label = "QSPI.U-BOOT-ENV.backup"; | ||
| 453 | reg = <0x00120000 0x00010000>; | ||
| 454 | }; | ||
| 455 | partition@5 { | ||
| 456 | label = "QSPI.KERNEL"; | ||
| 457 | reg = <0x00130000 0x0800000>; | ||
| 458 | }; | ||
| 459 | partition@6 { | ||
| 460 | label = "QSPI.FILESYSTEM"; | ||
| 461 | reg = <0x00930000 0x36D0000>; | ||
| 462 | }; | ||
| 463 | }; | ||
| 464 | }; | ||
| 465 | |||
| 466 | &hdq { | ||
| 467 | status = "okay"; | ||
| 468 | pinctrl-names = "default"; | ||
| 469 | pinctrl-0 = <&hdq_pins>; | ||
| 470 | }; | ||
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index 142009cc9332..c7dc9dab93a4 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi | |||
| @@ -11,6 +11,22 @@ | |||
| 11 | sys_clkin_ck: sys_clkin_ck { | 11 | sys_clkin_ck: sys_clkin_ck { |
| 12 | #clock-cells = <0>; | 12 | #clock-cells = <0>; |
| 13 | compatible = "ti,mux-clock"; | 13 | compatible = "ti,mux-clock"; |
| 14 | clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; | ||
| 15 | ti,bit-shift = <31>; | ||
| 16 | reg = <0x0040>; | ||
| 17 | }; | ||
| 18 | |||
| 19 | crystal_freq_sel_ck: crystal_freq_sel_ck { | ||
| 20 | #clock-cells = <0>; | ||
| 21 | compatible = "ti,mux-clock"; | ||
| 22 | clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; | ||
| 23 | ti,bit-shift = <29>; | ||
| 24 | reg = <0x0040>; | ||
| 25 | }; | ||
| 26 | |||
| 27 | sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { | ||
| 28 | #clock-cells = <0>; | ||
| 29 | compatible = "ti,mux-clock"; | ||
| 14 | clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; | 30 | clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; |
| 15 | ti,bit-shift = <22>; | 31 | ti,bit-shift = <22>; |
| 16 | reg = <0x0040>; | 32 | reg = <0x0040>; |
| @@ -87,6 +103,54 @@ | |||
| 87 | clock-mult = <1>; | 103 | clock-mult = <1>; |
| 88 | clock-div = <1>; | 104 | clock-div = <1>; |
| 89 | }; | 105 | }; |
| 106 | |||
| 107 | ehrpwm0_tbclk: ehrpwm0_tbclk { | ||
| 108 | #clock-cells = <0>; | ||
| 109 | compatible = "ti,gate-clock"; | ||
| 110 | clocks = <&dpll_per_m2_ck>; | ||
| 111 | ti,bit-shift = <0>; | ||
| 112 | reg = <0x0664>; | ||
| 113 | }; | ||
| 114 | |||
| 115 | ehrpwm1_tbclk: ehrpwm1_tbclk { | ||
| 116 | #clock-cells = <0>; | ||
| 117 | compatible = "ti,gate-clock"; | ||
| 118 | clocks = <&dpll_per_m2_ck>; | ||
| 119 | ti,bit-shift = <1>; | ||
| 120 | reg = <0x0664>; | ||
| 121 | }; | ||
| 122 | |||
| 123 | ehrpwm2_tbclk: ehrpwm2_tbclk { | ||
| 124 | #clock-cells = <0>; | ||
| 125 | compatible = "ti,gate-clock"; | ||
| 126 | clocks = <&dpll_per_m2_ck>; | ||
| 127 | ti,bit-shift = <2>; | ||
| 128 | reg = <0x0664>; | ||
| 129 | }; | ||
| 130 | |||
| 131 | ehrpwm3_tbclk: ehrpwm3_tbclk { | ||
| 132 | #clock-cells = <0>; | ||
| 133 | compatible = "ti,gate-clock"; | ||
| 134 | clocks = <&dpll_per_m2_ck>; | ||
| 135 | ti,bit-shift = <4>; | ||
| 136 | reg = <0x0664>; | ||
| 137 | }; | ||
| 138 | |||
| 139 | ehrpwm4_tbclk: ehrpwm4_tbclk { | ||
| 140 | #clock-cells = <0>; | ||
| 141 | compatible = "ti,gate-clock"; | ||
| 142 | clocks = <&dpll_per_m2_ck>; | ||
| 143 | ti,bit-shift = <5>; | ||
| 144 | reg = <0x0664>; | ||
| 145 | }; | ||
| 146 | |||
| 147 | ehrpwm5_tbclk: ehrpwm5_tbclk { | ||
| 148 | #clock-cells = <0>; | ||
| 149 | compatible = "ti,gate-clock"; | ||
| 150 | clocks = <&dpll_per_m2_ck>; | ||
| 151 | ti,bit-shift = <6>; | ||
| 152 | reg = <0x0664>; | ||
| 153 | }; | ||
| 90 | }; | 154 | }; |
| 91 | &prcm_clocks { | 155 | &prcm_clocks { |
| 92 | clk_32768_ck: clk_32768_ck { | 156 | clk_32768_ck: clk_32768_ck { |
| @@ -229,6 +293,7 @@ | |||
| 229 | reg = <0x2e30>; | 293 | reg = <0x2e30>; |
| 230 | ti,index-starts-at-one; | 294 | ti,index-starts-at-one; |
| 231 | ti,invert-autoidle-bit; | 295 | ti,invert-autoidle-bit; |
| 296 | ti,set-rate-parent; | ||
| 232 | }; | 297 | }; |
| 233 | 298 | ||
| 234 | dpll_per_ck: dpll_per_ck { | 299 | dpll_per_ck: dpll_per_ck { |
| @@ -511,6 +576,7 @@ | |||
| 511 | compatible = "ti,mux-clock"; | 576 | compatible = "ti,mux-clock"; |
| 512 | clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; | 577 | clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; |
| 513 | reg = <0x4244>; | 578 | reg = <0x4244>; |
| 579 | ti,set-rate-parent; | ||
| 514 | }; | 580 | }; |
| 515 | 581 | ||
| 516 | dpll_extdev_ck: dpll_extdev_ck { | 582 | dpll_extdev_ck: dpll_extdev_ck { |
| @@ -609,10 +675,13 @@ | |||
| 609 | 675 | ||
| 610 | dpll_per_clkdcoldo: dpll_per_clkdcoldo { | 676 | dpll_per_clkdcoldo: dpll_per_clkdcoldo { |
| 611 | #clock-cells = <0>; | 677 | #clock-cells = <0>; |
| 612 | compatible = "fixed-factor-clock"; | 678 | compatible = "ti,fixed-factor-clock"; |
| 613 | clocks = <&dpll_per_ck>; | 679 | clocks = <&dpll_per_ck>; |
| 614 | clock-mult = <1>; | 680 | ti,clock-mult = <1>; |
| 615 | clock-div = <1>; | 681 | ti,clock-div = <1>; |
| 682 | ti,autoidle-shift = <8>; | ||
| 683 | reg = <0x2e14>; | ||
| 684 | ti,invert-autoidle-bit; | ||
| 616 | }; | 685 | }; |
| 617 | 686 | ||
| 618 | dll_aging_clk_div: dll_aging_clk_div { | 687 | dll_aging_clk_div: dll_aging_clk_div { |
| @@ -653,4 +722,36 @@ | |||
| 653 | clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; | 722 | clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; |
| 654 | reg = <0x4260>; | 723 | reg = <0x4260>; |
| 655 | }; | 724 | }; |
| 725 | |||
| 726 | usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k { | ||
| 727 | #clock-cells = <0>; | ||
| 728 | compatible = "ti,gate-clock"; | ||
| 729 | clocks = <&usbphy_32khz_clkmux>; | ||
| 730 | ti,bit-shift = <8>; | ||
| 731 | reg = <0x2a40>; | ||
| 732 | }; | ||
| 733 | |||
| 734 | usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k { | ||
| 735 | #clock-cells = <0>; | ||
| 736 | compatible = "ti,gate-clock"; | ||
| 737 | clocks = <&usbphy_32khz_clkmux>; | ||
| 738 | ti,bit-shift = <8>; | ||
| 739 | reg = <0x2a48>; | ||
| 740 | }; | ||
| 741 | |||
| 742 | usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m { | ||
| 743 | #clock-cells = <0>; | ||
| 744 | compatible = "ti,gate-clock"; | ||
| 745 | clocks = <&dpll_per_clkdcoldo>; | ||
| 746 | ti,bit-shift = <8>; | ||
| 747 | reg = <0x8a60>; | ||
| 748 | }; | ||
| 749 | |||
| 750 | usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { | ||
| 751 | #clock-cells = <0>; | ||
| 752 | compatible = "ti,gate-clock"; | ||
| 753 | clocks = <&dpll_per_clkdcoldo>; | ||
| 754 | ti,bit-shift = <8>; | ||
| 755 | reg = <0x8a68>; | ||
| 756 | }; | ||
| 656 | }; | 757 | }; |
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 3383c4b66803..416f4e5a69c1 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts | |||
| @@ -35,7 +35,6 @@ | |||
| 35 | 35 | ||
| 36 | internal-regs { | 36 | internal-regs { |
| 37 | serial@12000 { | 37 | serial@12000 { |
| 38 | clock-frequency = <200000000>; | ||
| 39 | status = "okay"; | 38 | status = "okay"; |
| 40 | }; | 39 | }; |
| 41 | sata@a0000 { | 40 | sata@a0000 { |
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 2354fe023ee0..097df7d8f0f6 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts | |||
| @@ -47,7 +47,6 @@ | |||
| 47 | 47 | ||
| 48 | internal-regs { | 48 | internal-regs { |
| 49 | serial@12000 { | 49 | serial@12000 { |
| 50 | clock-frequency = <200000000>; | ||
| 51 | status = "okay"; | 50 | status = "okay"; |
| 52 | }; | 51 | }; |
| 53 | timer@20300 { | 52 | timer@20300 { |
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index 651aeb5ef439..d6d572e5af32 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts | |||
| @@ -50,7 +50,6 @@ | |||
| 50 | 50 | ||
| 51 | internal-regs { | 51 | internal-regs { |
| 52 | serial@12000 { | 52 | serial@12000 { |
| 53 | clock-frequency = <200000000>; | ||
| 54 | status = "okay"; | 53 | status = "okay"; |
| 55 | }; | 54 | }; |
| 56 | 55 | ||
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index 4e27587667bf..c5fe8b5dcdc7 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts | |||
| @@ -50,7 +50,6 @@ | |||
| 50 | 50 | ||
| 51 | internal-regs { | 51 | internal-regs { |
| 52 | serial@12000 { | 52 | serial@12000 { |
| 53 | clock-frequency = <200000000>; | ||
| 54 | status = "okay"; | 53 | status = "okay"; |
| 55 | }; | 54 | }; |
| 56 | 55 | ||
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 3e2c857d6000..4169f4096ea3 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts | |||
| @@ -51,7 +51,6 @@ | |||
| 51 | 51 | ||
| 52 | internal-regs { | 52 | internal-regs { |
| 53 | serial@12000 { | 53 | serial@12000 { |
| 54 | clock-frequency = <200000000>; | ||
| 55 | status = "okay"; | 54 | status = "okay"; |
| 56 | }; | 55 | }; |
| 57 | sata@a0000 { | 56 | sata@a0000 { |
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index bb77970c0b12..23227e0027ec 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi | |||
| @@ -157,6 +157,7 @@ | |||
| 157 | reg-shift = <2>; | 157 | reg-shift = <2>; |
| 158 | interrupts = <41>; | 158 | interrupts = <41>; |
| 159 | reg-io-width = <1>; | 159 | reg-io-width = <1>; |
| 160 | clocks = <&coreclk 0>; | ||
| 160 | status = "disabled"; | 161 | status = "disabled"; |
| 161 | }; | 162 | }; |
| 162 | serial@12100 { | 163 | serial@12100 { |
| @@ -165,6 +166,7 @@ | |||
| 165 | reg-shift = <2>; | 166 | reg-shift = <2>; |
| 166 | interrupts = <42>; | 167 | interrupts = <42>; |
| 167 | reg-io-width = <1>; | 168 | reg-io-width = <1>; |
| 169 | clocks = <&coreclk 0>; | ||
| 168 | status = "disabled"; | 170 | status = "disabled"; |
| 169 | }; | 171 | }; |
| 170 | 172 | ||
| @@ -203,6 +205,11 @@ | |||
| 203 | reg = <0x20300 0x34>, <0x20704 0x4>; | 205 | reg = <0x20300 0x34>, <0x20704 0x4>; |
| 204 | }; | 206 | }; |
| 205 | 207 | ||
| 208 | pmsu@22000 { | ||
| 209 | compatible = "marvell,armada-370-pmsu"; | ||
| 210 | reg = <0x22000 0x1000>; | ||
| 211 | }; | ||
| 212 | |||
| 206 | usb@50000 { | 213 | usb@50000 { |
| 207 | compatible = "marvell,orion-ehci"; | 214 | compatible = "marvell,orion-ehci"; |
| 208 | reg = <0x50000 0x500>; | 215 | reg = <0x50000 0x500>; |
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index af1f11e9e5a0..21b588b6f6bd 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi | |||
| @@ -220,6 +220,11 @@ | |||
| 220 | clocks = <&coreclk 2>; | 220 | clocks = <&coreclk 2>; |
| 221 | }; | 221 | }; |
| 222 | 222 | ||
| 223 | cpurst@20800 { | ||
| 224 | compatible = "marvell,armada-370-cpu-reset"; | ||
| 225 | reg = <0x20800 0x8>; | ||
| 226 | }; | ||
| 227 | |||
| 223 | audio_controller: audio-controller@30000 { | 228 | audio_controller: audio-controller@30000 { |
| 224 | compatible = "marvell,armada370-audio"; | 229 | compatible = "marvell,armada370-audio"; |
| 225 | reg = <0x30000 0x4000>; | 230 | reg = <0x30000 0x4000>; |
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts index 0451124e8ebf..772fec2d26ce 100644 --- a/arch/arm/boot/dts/armada-375-db.dts +++ b/arch/arm/boot/dts/armada-375-db.dts | |||
| @@ -68,7 +68,6 @@ | |||
| 68 | }; | 68 | }; |
| 69 | 69 | ||
| 70 | serial@12000 { | 70 | serial@12000 { |
| 71 | clock-frequency = <200000000>; | ||
| 72 | status = "okay"; | 71 | status = "okay"; |
| 73 | }; | 72 | }; |
| 74 | 73 | ||
| @@ -107,6 +106,14 @@ | |||
| 107 | }; | 106 | }; |
| 108 | }; | 107 | }; |
| 109 | 108 | ||
| 109 | usb@54000 { | ||
| 110 | status = "okay"; | ||
| 111 | }; | ||
| 112 | |||
| 113 | usb3@58000 { | ||
| 114 | status = "okay"; | ||
| 115 | }; | ||
| 116 | |||
| 110 | mvsdio@d4000 { | 117 | mvsdio@d4000 { |
| 111 | pinctrl-0 = <&sdio_pins &sdio_st_pins>; | 118 | pinctrl-0 = <&sdio_pins &sdio_st_pins>; |
| 112 | pinctrl-names = "default"; | 119 | pinctrl-names = "default"; |
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 3877693fb2d8..fb92551a1e71 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi | |||
| @@ -39,6 +39,8 @@ | |||
| 39 | cpus { | 39 | cpus { |
| 40 | #address-cells = <1>; | 40 | #address-cells = <1>; |
| 41 | #size-cells = <0>; | 41 | #size-cells = <0>; |
| 42 | enable-method = "marvell,armada-375-smp"; | ||
| 43 | |||
| 42 | cpu@0 { | 44 | cpu@0 { |
| 43 | device_type = "cpu"; | 45 | device_type = "cpu"; |
| 44 | compatible = "arm,cortex-a9"; | 46 | compatible = "arm,cortex-a9"; |
| @@ -128,6 +130,11 @@ | |||
| 128 | cache-level = <2>; | 130 | cache-level = <2>; |
| 129 | }; | 131 | }; |
| 130 | 132 | ||
| 133 | scu@c000 { | ||
| 134 | compatible = "arm,cortex-a9-scu"; | ||
| 135 | reg = <0xc000 0x58>; | ||
| 136 | }; | ||
| 137 | |||
| 131 | timer@c600 { | 138 | timer@c600 { |
| 132 | compatible = "arm,cortex-a9-twd-timer"; | 139 | compatible = "arm,cortex-a9-twd-timer"; |
| 133 | reg = <0xc600 0x20>; | 140 | reg = <0xc600 0x20>; |
| @@ -194,6 +201,7 @@ | |||
| 194 | reg-shift = <2>; | 201 | reg-shift = <2>; |
| 195 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | 202 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| 196 | reg-io-width = <1>; | 203 | reg-io-width = <1>; |
| 204 | clocks = <&coreclk 0>; | ||
| 197 | status = "disabled"; | 205 | status = "disabled"; |
| 198 | }; | 206 | }; |
| 199 | 207 | ||
| @@ -203,6 +211,7 @@ | |||
| 203 | reg-shift = <2>; | 211 | reg-shift = <2>; |
| 204 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | 212 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| 205 | reg-io-width = <1>; | 213 | reg-io-width = <1>; |
| 214 | clocks = <&coreclk 0>; | ||
| 206 | status = "disabled"; | 215 | status = "disabled"; |
| 207 | }; | 216 | }; |
| 208 | 217 | ||
| @@ -320,6 +329,46 @@ | |||
| 320 | clocks = <&coreclk 0>; | 329 | clocks = <&coreclk 0>; |
| 321 | }; | 330 | }; |
| 322 | 331 | ||
| 332 | watchdog@20300 { | ||
| 333 | compatible = "marvell,armada-375-wdt"; | ||
| 334 | reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; | ||
| 335 | clocks = <&coreclk 0>; | ||
| 336 | }; | ||
| 337 | |||
| 338 | cpurst@20800 { | ||
| 339 | compatible = "marvell,armada-370-cpu-reset"; | ||
| 340 | reg = <0x20800 0x10>; | ||
| 341 | }; | ||
| 342 | |||
| 343 | coherency-fabric@21010 { | ||
| 344 | compatible = "marvell,armada-375-coherency-fabric"; | ||
| 345 | reg = <0x21010 0x1c>; | ||
| 346 | }; | ||
| 347 | |||
| 348 | usb@50000 { | ||
| 349 | compatible = "marvell,orion-ehci"; | ||
| 350 | reg = <0x50000 0x500>; | ||
| 351 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | ||
| 352 | clocks = <&gateclk 18>; | ||
| 353 | status = "disabled"; | ||
| 354 | }; | ||
| 355 | |||
| 356 | usb@54000 { | ||
| 357 | compatible = "marvell,orion-ehci"; | ||
| 358 | reg = <0x54000 0x500>; | ||
| 359 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; | ||
| 360 | clocks = <&gateclk 26>; | ||
| 361 | status = "disabled"; | ||
| 362 | }; | ||
| 363 | |||
| 364 | usb3@58000 { | ||
| 365 | compatible = "marvell,armada-375-xhci"; | ||
| 366 | reg = <0x58000 0x20000>,<0x5b880 0x80>; | ||
| 367 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | ||
| 368 | clocks = <&gateclk 16>; | ||
| 369 | status = "disabled"; | ||
| 370 | }; | ||
| 371 | |||
| 323 | xor@60800 { | 372 | xor@60800 { |
| 324 | compatible = "marvell,orion-xor"; | 373 | compatible = "marvell,orion-xor"; |
| 325 | reg = <0x60800 0x100 | 374 | reg = <0x60800 0x100 |
| @@ -391,6 +440,12 @@ | |||
| 391 | status = "disabled"; | 440 | status = "disabled"; |
| 392 | }; | 441 | }; |
| 393 | 442 | ||
| 443 | thermal@e8078 { | ||
| 444 | compatible = "marvell,armada375-thermal"; | ||
| 445 | reg = <0xe8078 0x4>, <0xe807c 0x8>; | ||
| 446 | status = "okay"; | ||
| 447 | }; | ||
| 448 | |||
| 394 | coreclk: mvebu-sar@e8204 { | 449 | coreclk: mvebu-sar@e8204 { |
| 395 | compatible = "marvell,armada-375-core-clock"; | 450 | compatible = "marvell,armada-375-core-clock"; |
| 396 | reg = <0xe8204 0x04>; | 451 | reg = <0xe8204 0x04>; |
diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi index 6d0f03c98ee9..e69bc6759c39 100644 --- a/arch/arm/boot/dts/armada-380.dtsi +++ b/arch/arm/boot/dts/armada-380.dtsi | |||
| @@ -21,6 +21,8 @@ | |||
| 21 | cpus { | 21 | cpus { |
| 22 | #address-cells = <1>; | 22 | #address-cells = <1>; |
| 23 | #size-cells = <0>; | 23 | #size-cells = <0>; |
| 24 | enable-method = "marvell,armada-380-smp"; | ||
| 25 | |||
| 24 | cpu@0 { | 26 | cpu@0 { |
| 25 | device_type = "cpu"; | 27 | device_type = "cpu"; |
| 26 | compatible = "arm,cortex-a9"; | 28 | compatible = "arm,cortex-a9"; |
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts index 6828d77696a6..ff9637dd8d0f 100644 --- a/arch/arm/boot/dts/armada-385-db.dts +++ b/arch/arm/boot/dts/armada-385-db.dts | |||
| @@ -55,7 +55,6 @@ | |||
| 55 | }; | 55 | }; |
| 56 | 56 | ||
| 57 | serial@12000 { | 57 | serial@12000 { |
| 58 | clock-frequency = <200000000>; | ||
| 59 | status = "okay"; | 58 | status = "okay"; |
| 60 | }; | 59 | }; |
| 61 | 60 | ||
| @@ -65,6 +64,10 @@ | |||
| 65 | phy-mode = "rgmii-id"; | 64 | phy-mode = "rgmii-id"; |
| 66 | }; | 65 | }; |
| 67 | 66 | ||
| 67 | usb@50000 { | ||
| 68 | status = "ok"; | ||
| 69 | }; | ||
| 70 | |||
| 68 | ethernet@70000 { | 71 | ethernet@70000 { |
| 69 | status = "okay"; | 72 | status = "okay"; |
| 70 | phy = <&phy0>; | 73 | phy = <&phy0>; |
| @@ -81,6 +84,14 @@ | |||
| 81 | }; | 84 | }; |
| 82 | }; | 85 | }; |
| 83 | 86 | ||
| 87 | sata@a8000 { | ||
| 88 | status = "okay"; | ||
| 89 | }; | ||
| 90 | |||
| 91 | sata@e0000 { | ||
| 92 | status = "okay"; | ||
| 93 | }; | ||
| 94 | |||
| 84 | flash@d0000 { | 95 | flash@d0000 { |
| 85 | status = "okay"; | 96 | status = "okay"; |
| 86 | num-cs = <1>; | 97 | num-cs = <1>; |
| @@ -101,6 +112,22 @@ | |||
| 101 | reg = <0x1000000 0x3f000000>; | 112 | reg = <0x1000000 0x3f000000>; |
| 102 | }; | 113 | }; |
| 103 | }; | 114 | }; |
| 115 | |||
| 116 | sdhci@d8000 { | ||
| 117 | clock-frequency = <200000000>; | ||
| 118 | broken-cd; | ||
| 119 | wp-inverted; | ||
| 120 | bus-width = <8>; | ||
| 121 | status = "okay"; | ||
| 122 | }; | ||
| 123 | |||
| 124 | usb3@f0000 { | ||
| 125 | status = "okay"; | ||
| 126 | }; | ||
| 127 | |||
| 128 | usb3@f8000 { | ||
| 129 | status = "okay"; | ||
| 130 | }; | ||
| 104 | }; | 131 | }; |
| 105 | 132 | ||
| 106 | pcie-controller { | 133 | pcie-controller { |
diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-385-rd.dts index 45250c88814b..40893255a3f0 100644 --- a/arch/arm/boot/dts/armada-385-rd.dts +++ b/arch/arm/boot/dts/armada-385-rd.dts | |||
| @@ -51,7 +51,6 @@ | |||
| 51 | }; | 51 | }; |
| 52 | 52 | ||
| 53 | serial@12000 { | 53 | serial@12000 { |
| 54 | clock-frequency = <200000000>; | ||
| 55 | status = "okay"; | 54 | status = "okay"; |
| 56 | }; | 55 | }; |
| 57 | 56 | ||
| @@ -77,6 +76,10 @@ | |||
| 77 | reg = <1>; | 76 | reg = <1>; |
| 78 | }; | 77 | }; |
| 79 | }; | 78 | }; |
| 79 | |||
| 80 | usb3@f0000 { | ||
| 81 | status = "okay"; | ||
| 82 | }; | ||
| 80 | }; | 83 | }; |
| 81 | 84 | ||
| 82 | pcie-controller { | 85 | pcie-controller { |
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi index da801964a257..f011009bf4cf 100644 --- a/arch/arm/boot/dts/armada-385.dtsi +++ b/arch/arm/boot/dts/armada-385.dtsi | |||
| @@ -21,6 +21,8 @@ | |||
| 21 | cpus { | 21 | cpus { |
| 22 | #address-cells = <1>; | 22 | #address-cells = <1>; |
| 23 | #size-cells = <0>; | 23 | #size-cells = <0>; |
| 24 | enable-method = "marvell,armada-380-smp"; | ||
| 25 | |||
| 24 | cpu@0 { | 26 | cpu@0 { |
| 25 | device_type = "cpu"; | 27 | device_type = "cpu"; |
| 26 | compatible = "arm,cortex-a9"; | 28 | compatible = "arm,cortex-a9"; |
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index ca8813bb99ba..3de364e81b52 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi | |||
| @@ -108,6 +108,11 @@ | |||
| 108 | cache-level = <2>; | 108 | cache-level = <2>; |
| 109 | }; | 109 | }; |
| 110 | 110 | ||
| 111 | scu@c000 { | ||
| 112 | compatible = "arm,cortex-a9-scu"; | ||
| 113 | reg = <0xc000 0x58>; | ||
| 114 | }; | ||
| 115 | |||
| 111 | timer@c600 { | 116 | timer@c600 { |
| 112 | compatible = "arm,cortex-a9-twd-timer"; | 117 | compatible = "arm,cortex-a9-twd-timer"; |
| 113 | reg = <0xc600 0x20>; | 118 | reg = <0xc600 0x20>; |
| @@ -174,6 +179,7 @@ | |||
| 174 | reg-shift = <2>; | 179 | reg-shift = <2>; |
| 175 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | 180 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| 176 | reg-io-width = <1>; | 181 | reg-io-width = <1>; |
| 182 | clocks = <&coreclk 0>; | ||
| 177 | status = "disabled"; | 183 | status = "disabled"; |
| 178 | }; | 184 | }; |
| 179 | 185 | ||
| @@ -183,6 +189,7 @@ | |||
| 183 | reg-shift = <2>; | 189 | reg-shift = <2>; |
| 184 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | 190 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| 185 | reg-io-width = <1>; | 191 | reg-io-width = <1>; |
| 192 | clocks = <&coreclk 0>; | ||
| 186 | status = "disabled"; | 193 | status = "disabled"; |
| 187 | }; | 194 | }; |
| 188 | 195 | ||
| @@ -267,6 +274,28 @@ | |||
| 267 | clock-names = "nbclk", "fixed"; | 274 | clock-names = "nbclk", "fixed"; |
| 268 | }; | 275 | }; |
| 269 | 276 | ||
| 277 | watchdog@20300 { | ||
| 278 | compatible = "marvell,armada-380-wdt"; | ||
| 279 | reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; | ||
| 280 | clocks = <&coreclk 2>, <&refclk>; | ||
| 281 | clock-names = "nbclk", "fixed"; | ||
| 282 | }; | ||
| 283 | |||
| 284 | cpurst@20800 { | ||
| 285 | compatible = "marvell,armada-370-cpu-reset"; | ||
| 286 | reg = <0x20800 0x10>; | ||
| 287 | }; | ||
| 288 | |||
| 289 | coherency-fabric@21010 { | ||
| 290 | compatible = "marvell,armada-380-coherency-fabric"; | ||
| 291 | reg = <0x21010 0x1c>; | ||
| 292 | }; | ||
| 293 | |||
| 294 | pmsu@22000 { | ||
| 295 | compatible = "marvell,armada-380-pmsu"; | ||
| 296 | reg = <0x22000 0x1000>; | ||
| 297 | }; | ||
| 298 | |||
| 270 | eth1: ethernet@30000 { | 299 | eth1: ethernet@30000 { |
| 271 | compatible = "marvell,armada-370-neta"; | 300 | compatible = "marvell,armada-370-neta"; |
| 272 | reg = <0x30000 0x4000>; | 301 | reg = <0x30000 0x4000>; |
| @@ -283,6 +312,14 @@ | |||
| 283 | status = "disabled"; | 312 | status = "disabled"; |
| 284 | }; | 313 | }; |
| 285 | 314 | ||
| 315 | usb@50000 { | ||
| 316 | compatible = "marvell,orion-ehci"; | ||
| 317 | reg = <0x58000 0x500>; | ||
| 318 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; | ||
| 319 | clocks = <&gateclk 18>; | ||
| 320 | status = "disabled"; | ||
| 321 | }; | ||
| 322 | |||
| 286 | xor@60800 { | 323 | xor@60800 { |
| 287 | compatible = "marvell,orion-xor"; | 324 | compatible = "marvell,orion-xor"; |
| 288 | reg = <0x60800 0x100 | 325 | reg = <0x60800 0x100 |
| @@ -339,6 +376,22 @@ | |||
| 339 | clocks = <&gateclk 4>; | 376 | clocks = <&gateclk 4>; |
| 340 | }; | 377 | }; |
| 341 | 378 | ||
| 379 | sata@a8000 { | ||
| 380 | compatible = "marvell,armada-380-ahci"; | ||
| 381 | reg = <0xa8000 0x2000>; | ||
| 382 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | ||
| 383 | clocks = <&gateclk 15>; | ||
| 384 | status = "disabled"; | ||
| 385 | }; | ||
| 386 | |||
| 387 | sata@e0000 { | ||
| 388 | compatible = "marvell,armada-380-ahci"; | ||
| 389 | reg = <0xe0000 0x2000>; | ||
| 390 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | ||
| 391 | clocks = <&gateclk 30>; | ||
| 392 | status = "disabled"; | ||
| 393 | }; | ||
| 394 | |||
| 342 | coredivclk: clock@e4250 { | 395 | coredivclk: clock@e4250 { |
| 343 | compatible = "marvell,armada-380-corediv-clock"; | 396 | compatible = "marvell,armada-380-corediv-clock"; |
| 344 | reg = <0xe4250 0xc>; | 397 | reg = <0xe4250 0xc>; |
| @@ -347,6 +400,12 @@ | |||
| 347 | clock-output-names = "nand"; | 400 | clock-output-names = "nand"; |
| 348 | }; | 401 | }; |
| 349 | 402 | ||
| 403 | thermal@e8078 { | ||
| 404 | compatible = "marvell,armada380-thermal"; | ||
| 405 | reg = <0xe4078 0x4>, <0xe4074 0x4>; | ||
| 406 | status = "okay"; | ||
| 407 | }; | ||
| 408 | |||
| 350 | flash@d0000 { | 409 | flash@d0000 { |
| 351 | compatible = "marvell,armada370-nand"; | 410 | compatible = "marvell,armada370-nand"; |
| 352 | reg = <0xd0000 0x54>; | 411 | reg = <0xd0000 0x54>; |
| @@ -356,6 +415,31 @@ | |||
| 356 | clocks = <&coredivclk 0>; | 415 | clocks = <&coredivclk 0>; |
| 357 | status = "disabled"; | 416 | status = "disabled"; |
| 358 | }; | 417 | }; |
| 418 | |||
| 419 | sdhci@d8000 { | ||
| 420 | compatible = "marvell,armada-380-sdhci"; | ||
| 421 | reg = <0xd8000 0x1000>, <0xdc000 0x100>; | ||
| 422 | interrupts = <0 25 0x4>; | ||
| 423 | clocks = <&gateclk 17>; | ||
| 424 | mrvl,clk-delay-cycles = <0x1F>; | ||
| 425 | status = "disabled"; | ||
| 426 | }; | ||
| 427 | |||
| 428 | usb3@f0000 { | ||
| 429 | compatible = "marvell,armada-380-xhci"; | ||
| 430 | reg = <0xf0000 0x4000>,<0xf4000 0x4000>; | ||
| 431 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | ||
| 432 | clocks = <&gateclk 9>; | ||
| 433 | status = "disabled"; | ||
| 434 | }; | ||
| 435 | |||
| 436 | usb3@f8000 { | ||
| 437 | compatible = "marvell,armada-380-xhci"; | ||
| 438 | reg = <0xf8000 0x4000>,<0xfc000 0x4000>; | ||
| 439 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | ||
| 440 | clocks = <&gateclk 10>; | ||
| 441 | status = "disabled"; | ||
| 442 | }; | ||
| 359 | }; | 443 | }; |
| 360 | }; | 444 | }; |
| 361 | 445 | ||
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts index d83d7d69ac01..a55a97a70505 100644 --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts | |||
| @@ -95,12 +95,10 @@ | |||
| 95 | }; | 95 | }; |
| 96 | 96 | ||
| 97 | serial@12000 { | 97 | serial@12000 { |
| 98 | clock-frequency = <250000000>; | ||
| 99 | status = "okay"; | 98 | status = "okay"; |
| 100 | }; | 99 | }; |
| 101 | 100 | ||
| 102 | serial@12100 { | 101 | serial@12100 { |
| 103 | clock-frequency = <250000000>; | ||
| 104 | status = "okay"; | 102 | status = "okay"; |
| 105 | }; | 103 | }; |
| 106 | 104 | ||
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index 90f0bf6f9271..42ddb2864365 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts | |||
| @@ -106,19 +106,15 @@ | |||
| 106 | 106 | ||
| 107 | internal-regs { | 107 | internal-regs { |
| 108 | serial@12000 { | 108 | serial@12000 { |
| 109 | clock-frequency = <250000000>; | ||
| 110 | status = "okay"; | 109 | status = "okay"; |
| 111 | }; | 110 | }; |
| 112 | serial@12100 { | 111 | serial@12100 { |
| 113 | clock-frequency = <250000000>; | ||
| 114 | status = "okay"; | 112 | status = "okay"; |
| 115 | }; | 113 | }; |
| 116 | serial@12200 { | 114 | serial@12200 { |
| 117 | clock-frequency = <250000000>; | ||
| 118 | status = "okay"; | 115 | status = "okay"; |
| 119 | }; | 116 | }; |
| 120 | serial@12300 { | 117 | serial@12300 { |
| 121 | clock-frequency = <250000000>; | ||
| 122 | status = "okay"; | 118 | status = "okay"; |
| 123 | }; | 119 | }; |
| 124 | 120 | ||
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 0c756421ae6a..0478c55ca656 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts | |||
| @@ -104,19 +104,15 @@ | |||
| 104 | 104 | ||
| 105 | internal-regs { | 105 | internal-regs { |
| 106 | serial@12000 { | 106 | serial@12000 { |
| 107 | clock-frequency = <250000000>; | ||
| 108 | status = "okay"; | 107 | status = "okay"; |
| 109 | }; | 108 | }; |
| 110 | serial@12100 { | 109 | serial@12100 { |
| 111 | clock-frequency = <250000000>; | ||
| 112 | status = "okay"; | 110 | status = "okay"; |
| 113 | }; | 111 | }; |
| 114 | serial@12200 { | 112 | serial@12200 { |
| 115 | clock-frequency = <250000000>; | ||
| 116 | status = "okay"; | 113 | status = "okay"; |
| 117 | }; | 114 | }; |
| 118 | serial@12300 { | 115 | serial@12300 { |
| 119 | clock-frequency = <250000000>; | ||
| 120 | status = "okay"; | 116 | status = "okay"; |
| 121 | }; | 117 | }; |
| 122 | 118 | ||
diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts index c2242745b9b8..25674fe81f70 100644 --- a/arch/arm/boot/dts/armada-xp-matrix.dts +++ b/arch/arm/boot/dts/armada-xp-matrix.dts | |||
| @@ -37,19 +37,15 @@ | |||
| 37 | 37 | ||
| 38 | internal-regs { | 38 | internal-regs { |
| 39 | serial@12000 { | 39 | serial@12000 { |
| 40 | clock-frequency = <250000000>; | ||
| 41 | status = "okay"; | 40 | status = "okay"; |
| 42 | }; | 41 | }; |
| 43 | serial@12100 { | 42 | serial@12100 { |
| 44 | clock-frequency = <250000000>; | ||
| 45 | status = "okay"; | 43 | status = "okay"; |
| 46 | }; | 44 | }; |
| 47 | serial@12200 { | 45 | serial@12200 { |
| 48 | clock-frequency = <250000000>; | ||
| 49 | status = "okay"; | 46 | status = "okay"; |
| 50 | }; | 47 | }; |
| 51 | serial@12300 { | 48 | serial@12300 { |
| 52 | clock-frequency = <250000000>; | ||
| 53 | status = "okay"; | 49 | status = "okay"; |
| 54 | }; | 50 | }; |
| 55 | 51 | ||
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index 98335fb34b7a..1257ff1ed278 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | cpus { | 27 | cpus { |
| 28 | #address-cells = <1>; | 28 | #address-cells = <1>; |
| 29 | #size-cells = <0>; | 29 | #size-cells = <0>; |
| 30 | enable-method = "marvell,armada-xp-smp"; | ||
| 30 | 31 | ||
| 31 | cpu@0 { | 32 | cpu@0 { |
| 32 | device_type = "cpu"; | 33 | device_type = "cpu"; |
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 9480cf891f8c..3396b25b39e1 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | cpus { | 29 | cpus { |
| 30 | #address-cells = <1>; | 30 | #address-cells = <1>; |
| 31 | #size-cells = <0>; | 31 | #size-cells = <0>; |
| 32 | enable-method = "marvell,armada-xp-smp"; | ||
| 32 | 33 | ||
| 33 | cpu@0 { | 34 | cpu@0 { |
| 34 | device_type = "cpu"; | 35 | device_type = "cpu"; |
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 31ba6d8fbadf..6da84bf40aaf 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | cpus { | 30 | cpus { |
| 31 | #address-cells = <1>; | 31 | #address-cells = <1>; |
| 32 | #size-cells = <0>; | 32 | #size-cells = <0>; |
| 33 | enable-method = "marvell,armada-xp-smp"; | ||
| 33 | 34 | ||
| 34 | cpu@0 { | 35 | cpu@0 { |
| 35 | device_type = "cpu"; | 36 | device_type = "cpu"; |
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts index ff049ee862eb..0cf999abc4ed 100644 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | |||
| @@ -138,7 +138,6 @@ | |||
| 138 | }; | 138 | }; |
| 139 | 139 | ||
| 140 | serial@12000 { | 140 | serial@12000 { |
| 141 | clocks = <&coreclk 0>; | ||
| 142 | status = "okay"; | 141 | status = "okay"; |
| 143 | }; | 142 | }; |
| 144 | 143 | ||
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 5d42feb31049..e5c6a0492ca0 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | |||
| @@ -72,11 +72,9 @@ | |||
| 72 | 72 | ||
| 73 | internal-regs { | 73 | internal-regs { |
| 74 | serial@12000 { | 74 | serial@12000 { |
| 75 | clock-frequency = <250000000>; | ||
| 76 | status = "okay"; | 75 | status = "okay"; |
| 77 | }; | 76 | }; |
| 78 | serial@12100 { | 77 | serial@12100 { |
| 79 | clock-frequency = <250000000>; | ||
| 80 | status = "okay"; | 78 | status = "okay"; |
| 81 | }; | 79 | }; |
| 82 | pinctrl { | 80 | pinctrl { |
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index abb9f9dcc525..5902e8359c91 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi | |||
| @@ -58,6 +58,7 @@ | |||
| 58 | reg-shift = <2>; | 58 | reg-shift = <2>; |
| 59 | interrupts = <43>; | 59 | interrupts = <43>; |
| 60 | reg-io-width = <1>; | 60 | reg-io-width = <1>; |
| 61 | clocks = <&coreclk 0>; | ||
| 61 | status = "disabled"; | 62 | status = "disabled"; |
| 62 | }; | 63 | }; |
| 63 | serial@12300 { | 64 | serial@12300 { |
| @@ -66,6 +67,7 @@ | |||
| 66 | reg-shift = <2>; | 67 | reg-shift = <2>; |
| 67 | interrupts = <44>; | 68 | interrupts = <44>; |
| 68 | reg-io-width = <1>; | 69 | reg-io-width = <1>; |
| 70 | clocks = <&coreclk 0>; | ||
| 69 | status = "disabled"; | 71 | status = "disabled"; |
| 70 | }; | 72 | }; |
| 71 | 73 | ||
| @@ -117,9 +119,9 @@ | |||
| 117 | clock-names = "nbclk", "fixed"; | 119 | clock-names = "nbclk", "fixed"; |
| 118 | }; | 120 | }; |
| 119 | 121 | ||
| 120 | armada-370-xp-pmsu@22000 { | 122 | cpurst@20800 { |
| 121 | compatible = "marvell,armada-370-xp-pmsu"; | 123 | compatible = "marvell,armada-370-cpu-reset"; |
| 122 | reg = <0x22100 0x400>, <0x20800 0x20>; | 124 | reg = <0x20800 0x20>; |
| 123 | }; | 125 | }; |
| 124 | 126 | ||
| 125 | eth2: ethernet@30000 { | 127 | eth2: ethernet@30000 { |
diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts index a542d5837a17..27ebb0f722fd 100644 --- a/arch/arm/boot/dts/at91-cosino_mega2560.dts +++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts | |||
| @@ -32,11 +32,6 @@ | |||
| 32 | status = "okay"; | 32 | status = "okay"; |
| 33 | }; | 33 | }; |
| 34 | 34 | ||
| 35 | |||
| 36 | tsadcc: tsadcc@f804c000 { | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | |||
| 40 | rtc@fffffeb0 { | 35 | rtc@fffffeb0 { |
| 41 | status = "okay"; | 36 | status = "okay"; |
| 42 | }; | 37 | }; |
diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index 4537259ce529..5b8e40400bec 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts | |||
| @@ -21,6 +21,14 @@ | |||
| 21 | reg = <0x20000000 0x10000000>; | 21 | reg = <0x20000000 0x10000000>; |
| 22 | }; | 22 | }; |
| 23 | 23 | ||
| 24 | slow_xtal { | ||
| 25 | clock-frequency = <32768>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | main_xtal { | ||
| 29 | clock-frequency = <12000000>; | ||
| 30 | }; | ||
| 31 | |||
| 24 | ahb { | 32 | ahb { |
| 25 | apb { | 33 | apb { |
| 26 | mmc0: mmc@f0000000 { | 34 | mmc0: mmc@f0000000 { |
| @@ -43,11 +51,54 @@ | |||
| 43 | }; | 51 | }; |
| 44 | 52 | ||
| 45 | i2c0: i2c@f0014000 { | 53 | i2c0: i2c@f0014000 { |
| 54 | pinctrl-0 = <&pinctrl_i2c0_pu>; | ||
| 46 | status = "okay"; | 55 | status = "okay"; |
| 47 | }; | 56 | }; |
| 48 | 57 | ||
| 49 | i2c1: i2c@f0018000 { | 58 | i2c1: i2c@f0018000 { |
| 50 | status = "okay"; | 59 | status = "okay"; |
| 60 | |||
| 61 | pmic: act8865@5b { | ||
| 62 | compatible = "active-semi,act8865"; | ||
| 63 | reg = <0x5b>; | ||
| 64 | status = "okay"; | ||
| 65 | |||
| 66 | regulators { | ||
| 67 | vcc_1v8_reg: DCDC_REG1 { | ||
| 68 | regulator-name = "VCC_1V8"; | ||
| 69 | regulator-min-microvolt = <1800000>; | ||
| 70 | regulator-max-microvolt = <1800000>; | ||
| 71 | regulator-always-on; | ||
| 72 | }; | ||
| 73 | |||
| 74 | vcc_1v2_reg: DCDC_REG2 { | ||
| 75 | regulator-name = "VCC_1V2"; | ||
| 76 | regulator-min-microvolt = <1200000>; | ||
| 77 | regulator-max-microvolt = <1200000>; | ||
| 78 | regulator-always-on; | ||
| 79 | }; | ||
| 80 | |||
| 81 | vcc_3v3_reg: DCDC_REG3 { | ||
| 82 | regulator-name = "VCC_3V3"; | ||
| 83 | regulator-min-microvolt = <3300000>; | ||
| 84 | regulator-max-microvolt = <3300000>; | ||
| 85 | regulator-always-on; | ||
| 86 | }; | ||
| 87 | |||
| 88 | vddfuse_reg: LDO_REG1 { | ||
| 89 | regulator-name = "FUSE_2V5"; | ||
| 90 | regulator-min-microvolt = <2500000>; | ||
| 91 | regulator-max-microvolt = <2500000>; | ||
| 92 | }; | ||
| 93 | |||
| 94 | vddana_reg: LDO_REG2 { | ||
| 95 | regulator-name = "VDDANA"; | ||
| 96 | regulator-min-microvolt = <3300000>; | ||
| 97 | regulator-max-microvolt = <3300000>; | ||
| 98 | regulator-always-on; | ||
| 99 | }; | ||
| 100 | }; | ||
| 101 | }; | ||
| 51 | }; | 102 | }; |
| 52 | 103 | ||
| 53 | macb0: ethernet@f0028000 { | 104 | macb0: ethernet@f0028000 { |
| @@ -55,6 +106,12 @@ | |||
| 55 | status = "okay"; | 106 | status = "okay"; |
| 56 | }; | 107 | }; |
| 57 | 108 | ||
| 109 | pwm0: pwm@f002c000 { | ||
| 110 | pinctrl-names = "default"; | ||
| 111 | pinctrl-0 = <&pinctrl_pwm0_pwmh0_0 &pinctrl_pwm0_pwmh1_0>; | ||
| 112 | status = "okay"; | ||
| 113 | }; | ||
| 114 | |||
| 58 | usart0: serial@f001c000 { | 115 | usart0: serial@f001c000 { |
| 59 | status = "okay"; | 116 | status = "okay"; |
| 60 | }; | 117 | }; |
| @@ -102,6 +159,7 @@ | |||
| 102 | 159 | ||
| 103 | i2c2: i2c@f801c000 { | 160 | i2c2: i2c@f801c000 { |
| 104 | dmas = <0>, <0>; /* Do not use DMA for i2c2 */ | 161 | dmas = <0>, <0>; /* Do not use DMA for i2c2 */ |
| 162 | pinctrl-0 = <&pinctrl_i2c2_pu>; | ||
| 105 | status = "okay"; | 163 | status = "okay"; |
| 106 | }; | 164 | }; |
| 107 | 165 | ||
| @@ -116,6 +174,18 @@ | |||
| 116 | 174 | ||
| 117 | pinctrl@fffff200 { | 175 | pinctrl@fffff200 { |
| 118 | board { | 176 | board { |
| 177 | pinctrl_i2c0_pu: i2c0_pu { | ||
| 178 | atmel,pins = | ||
| 179 | <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, | ||
| 180 | <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; | ||
| 181 | }; | ||
| 182 | |||
| 183 | pinctrl_i2c2_pu: i2c2_pu { | ||
| 184 | atmel,pins = | ||
| 185 | <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>, | ||
| 186 | <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; | ||
| 187 | }; | ||
| 188 | |||
| 119 | pinctrl_mmc0_cd: mmc0_cd { | 189 | pinctrl_mmc0_cd: mmc0_cd { |
| 120 | atmel,pins = | 190 | atmel,pins = |
| 121 | <AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; | 191 | <AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; |
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 3be973e9889a..b309c1c6e848 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | i2c0 = &i2c0; | 29 | i2c0 = &i2c0; |
| 30 | ssc0 = &ssc0; | 30 | ssc0 = &ssc0; |
| 31 | ssc1 = &ssc1; | 31 | ssc1 = &ssc1; |
| 32 | ssc2 = &ssc2; | ||
| 32 | }; | 33 | }; |
| 33 | 34 | ||
| 34 | cpus { | 35 | cpus { |
| @@ -45,6 +46,18 @@ | |||
| 45 | reg = <0x20000000 0x08000000>; | 46 | reg = <0x20000000 0x08000000>; |
| 46 | }; | 47 | }; |
| 47 | 48 | ||
| 49 | main_xtal: main_xtal { | ||
| 50 | compatible = "fixed-clock"; | ||
| 51 | #clock-cells = <0>; | ||
| 52 | clock-frequency = <0>; | ||
| 53 | }; | ||
| 54 | |||
| 55 | slow_xtal: slow_xtal { | ||
| 56 | compatible = "fixed-clock"; | ||
| 57 | #clock-cells = <0>; | ||
| 58 | clock-frequency = <0>; | ||
| 59 | }; | ||
| 60 | |||
| 48 | ahb { | 61 | ahb { |
| 49 | compatible = "simple-bus"; | 62 | compatible = "simple-bus"; |
| 50 | #address-cells = <1>; | 63 | #address-cells = <1>; |
| @@ -182,6 +195,8 @@ | |||
| 182 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; | 195 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; |
| 183 | pinctrl-names = "default"; | 196 | pinctrl-names = "default"; |
| 184 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | 197 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 198 | clocks = <&ssc0_clk>; | ||
| 199 | clock-names = "pclk"; | ||
| 185 | status = "disabled"; | 200 | status = "disabled"; |
| 186 | }; | 201 | }; |
| 187 | 202 | ||
| @@ -191,6 +206,19 @@ | |||
| 191 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; | 206 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; |
| 192 | pinctrl-names = "default"; | 207 | pinctrl-names = "default"; |
| 193 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | 208 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; |
| 209 | clocks = <&ssc1_clk>; | ||
| 210 | clock-names = "pclk"; | ||
| 211 | status = "disabled"; | ||
| 212 | }; | ||
| 213 | |||
| 214 | ssc2: ssc@fffc4000 { | ||
| 215 | compatible = "atmel,at91rm9200-ssc"; | ||
| 216 | reg = <0xfffc4000 0x4000>; | ||
| 217 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; | ||
| 218 | pinctrl-names = "default"; | ||
| 219 | pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; | ||
| 220 | clocks = <&ssc2_clk>; | ||
| 221 | clock-names = "pclk"; | ||
| 194 | status = "disabled"; | 222 | status = "disabled"; |
| 195 | }; | 223 | }; |
| 196 | 224 | ||
| @@ -385,6 +413,22 @@ | |||
| 385 | }; | 413 | }; |
| 386 | }; | 414 | }; |
| 387 | 415 | ||
| 416 | ssc2 { | ||
| 417 | pinctrl_ssc2_tx: ssc2_tx-0 { | ||
| 418 | atmel,pins = | ||
| 419 | <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 420 | <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 421 | <AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 422 | }; | ||
| 423 | |||
| 424 | pinctrl_ssc2_rx: ssc2_rx-0 { | ||
| 425 | atmel,pins = | ||
| 426 | <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 427 | <AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 428 | <AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 429 | }; | ||
| 430 | }; | ||
| 431 | |||
| 388 | spi0 { | 432 | spi0 { |
| 389 | pinctrl_spi0: spi0-0 { | 433 | pinctrl_spi0: spi0-0 { |
| 390 | atmel,pins = | 434 | atmel,pins = |
| @@ -524,17 +568,24 @@ | |||
| 524 | #size-cells = <0>; | 568 | #size-cells = <0>; |
| 525 | #interrupt-cells = <1>; | 569 | #interrupt-cells = <1>; |
| 526 | 570 | ||
| 527 | clk32k: slck { | 571 | slow_rc_osc: slow_rc_osc { |
| 528 | compatible = "fixed-clock"; | 572 | compatible = "fixed-clock"; |
| 529 | #clock-cells = <0>; | 573 | #clock-cells = <0>; |
| 530 | clock-frequency = <32768>; | 574 | clock-frequency = <32768>; |
| 575 | clock-accuracy = <50000000>; | ||
| 576 | }; | ||
| 577 | |||
| 578 | clk32k: slck { | ||
| 579 | compatible = "atmel,at91sam9260-clk-slow"; | ||
| 580 | #clock-cells = <0>; | ||
| 581 | clocks = <&slow_rc_osc &slow_xtal>; | ||
| 531 | }; | 582 | }; |
| 532 | 583 | ||
| 533 | main: mainck { | 584 | main: mainck { |
| 534 | compatible = "atmel,at91rm9200-clk-main"; | 585 | compatible = "atmel,at91rm9200-clk-main"; |
| 535 | #clock-cells = <0>; | 586 | #clock-cells = <0>; |
| 536 | interrupts-extended = <&pmc AT91_PMC_MOSCS>; | 587 | interrupts-extended = <&pmc AT91_PMC_MOSCS>; |
| 537 | clocks = <&clk32k>; | 588 | clocks = <&main_xtal>; |
| 538 | }; | 589 | }; |
| 539 | 590 | ||
| 540 | plla: pllack { | 591 | plla: pllack { |
| @@ -545,7 +596,8 @@ | |||
| 545 | reg = <0>; | 596 | reg = <0>; |
| 546 | atmel,clk-input-range = <1000000 32000000>; | 597 | atmel,clk-input-range = <1000000 32000000>; |
| 547 | #atmel,pll-clk-output-range-cells = <4>; | 598 | #atmel,pll-clk-output-range-cells = <4>; |
| 548 | atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>; | 599 | atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, |
| 600 | <190000000 240000000 2 1>; | ||
| 549 | }; | 601 | }; |
| 550 | 602 | ||
| 551 | pllb: pllbck { | 603 | pllb: pllbck { |
| @@ -554,9 +606,9 @@ | |||
| 554 | interrupts-extended = <&pmc AT91_PMC_LOCKB>; | 606 | interrupts-extended = <&pmc AT91_PMC_LOCKB>; |
| 555 | clocks = <&main>; | 607 | clocks = <&main>; |
| 556 | reg = <1>; | 608 | reg = <1>; |
| 557 | atmel,clk-input-range = <1000000 32000000>; | 609 | atmel,clk-input-range = <1000000 5000000>; |
| 558 | #atmel,pll-clk-output-range-cells = <4>; | 610 | #atmel,pll-clk-output-range-cells = <4>; |
| 559 | atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>; | 611 | atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; |
| 560 | }; | 612 | }; |
| 561 | 613 | ||
| 562 | mck: masterck { | 614 | mck: masterck { |
| @@ -565,16 +617,48 @@ | |||
| 565 | interrupts-extended = <&pmc AT91_PMC_MCKRDY>; | 617 | interrupts-extended = <&pmc AT91_PMC_MCKRDY>; |
| 566 | clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; | 618 | clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; |
| 567 | atmel,clk-output-range = <0 94000000>; | 619 | atmel,clk-output-range = <0 94000000>; |
| 568 | atmel,clk-divisors = <1 2 4 3>; | 620 | atmel,clk-divisors = <1 2 4 0>; |
| 569 | }; | 621 | }; |
| 570 | 622 | ||
| 571 | usb: usbck { | 623 | usb: usbck { |
| 572 | compatible = "atmel,at91rm9200-clk-usb"; | 624 | compatible = "atmel,at91rm9200-clk-usb"; |
| 573 | #clock-cells = <0>; | 625 | #clock-cells = <0>; |
| 574 | atmel,clk-divisors = <1 2 4 3>; | 626 | atmel,clk-divisors = <1 2 4 0>; |
| 575 | clocks = <&pllb>; | 627 | clocks = <&pllb>; |
| 576 | }; | 628 | }; |
| 577 | 629 | ||
| 630 | prog: progck { | ||
| 631 | compatible = "atmel,at91rm9200-clk-programmable"; | ||
| 632 | #address-cells = <1>; | ||
| 633 | #size-cells = <0>; | ||
| 634 | interrupt-parent = <&pmc>; | ||
| 635 | clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; | ||
| 636 | |||
| 637 | prog0: prog0 { | ||
| 638 | #clock-cells = <0>; | ||
| 639 | reg = <0>; | ||
| 640 | interrupts = <AT91_PMC_PCKRDY(0)>; | ||
| 641 | }; | ||
| 642 | |||
| 643 | prog1: prog1 { | ||
| 644 | #clock-cells = <0>; | ||
| 645 | reg = <1>; | ||
| 646 | interrupts = <AT91_PMC_PCKRDY(1)>; | ||
| 647 | }; | ||
| 648 | |||
| 649 | prog2: prog2 { | ||
| 650 | #clock-cells = <0>; | ||
| 651 | reg = <2>; | ||
| 652 | interrupts = <AT91_PMC_PCKRDY(2)>; | ||
| 653 | }; | ||
| 654 | |||
| 655 | prog3: prog3 { | ||
| 656 | #clock-cells = <0>; | ||
| 657 | reg = <3>; | ||
| 658 | interrupts = <AT91_PMC_PCKRDY(3)>; | ||
| 659 | }; | ||
| 660 | }; | ||
| 661 | |||
| 578 | systemck { | 662 | systemck { |
| 579 | compatible = "atmel,at91rm9200-clk-system"; | 663 | compatible = "atmel,at91rm9200-clk-system"; |
| 580 | #address-cells = <1>; | 664 | #address-cells = <1>; |
| @@ -592,6 +676,30 @@ | |||
| 592 | clocks = <&usb>; | 676 | clocks = <&usb>; |
| 593 | }; | 677 | }; |
| 594 | 678 | ||
| 679 | pck0: pck0 { | ||
| 680 | #clock-cells = <0>; | ||
| 681 | reg = <8>; | ||
| 682 | clocks = <&prog0>; | ||
| 683 | }; | ||
| 684 | |||
| 685 | pck1: pck1 { | ||
| 686 | #clock-cells = <0>; | ||
| 687 | reg = <9>; | ||
| 688 | clocks = <&prog1>; | ||
| 689 | }; | ||
| 690 | |||
| 691 | pck2: pck2 { | ||
| 692 | #clock-cells = <0>; | ||
| 693 | reg = <10>; | ||
| 694 | clocks = <&prog2>; | ||
| 695 | }; | ||
| 696 | |||
| 697 | pck3: pck3 { | ||
| 698 | #clock-cells = <0>; | ||
| 699 | reg = <11>; | ||
| 700 | clocks = <&prog3>; | ||
| 701 | }; | ||
| 702 | |||
| 595 | hclk0: hclk0 { | 703 | hclk0: hclk0 { |
| 596 | #clock-cells = <0>; | 704 | #clock-cells = <0>; |
| 597 | reg = <16>; | 705 | reg = <16>; |
| @@ -666,6 +774,21 @@ | |||
| 666 | reg = <13>; | 774 | reg = <13>; |
| 667 | }; | 775 | }; |
| 668 | 776 | ||
| 777 | ssc0_clk: ssc0_clk { | ||
| 778 | #clock-cells = <0>; | ||
| 779 | reg = <14>; | ||
| 780 | }; | ||
| 781 | |||
| 782 | ssc1_clk: ssc1_clk { | ||
| 783 | #clock-cells = <0>; | ||
| 784 | reg = <15>; | ||
| 785 | }; | ||
| 786 | |||
| 787 | ssc2_clk: ssc2_clk { | ||
| 788 | #clock-cells = <0>; | ||
| 789 | reg = <16>; | ||
| 790 | }; | ||
| 791 | |||
| 669 | tc0_clk: tc0_clk { | 792 | tc0_clk: tc0_clk { |
| 670 | #clock-cells = <0>; | 793 | #clock-cells = <0>; |
| 671 | reg = <17>; | 794 | reg = <17>; |
diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts index 2ce527e70c7a..c6683ea8b743 100644 --- a/arch/arm/boot/dts/at91sam9261ek.dts +++ b/arch/arm/boot/dts/at91sam9261ek.dts | |||
| @@ -20,6 +20,10 @@ | |||
| 20 | reg = <0x20000000 0x4000000>; | 20 | reg = <0x20000000 0x4000000>; |
| 21 | }; | 21 | }; |
| 22 | 22 | ||
| 23 | main_xtal { | ||
| 24 | clock-frequency = <18432000>; | ||
| 25 | }; | ||
| 26 | |||
| 23 | clocks { | 27 | clocks { |
| 24 | #address-cells = <1>; | 28 | #address-cells = <1>; |
| 25 | #size-cells = <1>; | 29 | #size-cells = <1>; |
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 9cdaecff13b3..ace6bf197b70 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi | |||
| @@ -136,6 +136,36 @@ | |||
| 136 | >; | 136 | >; |
| 137 | 137 | ||
| 138 | /* shared pinctrl settings */ | 138 | /* shared pinctrl settings */ |
| 139 | adc0 { | ||
| 140 | pinctrl_adc0_adtrg: adc0_adtrg { | ||
| 141 | atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 142 | }; | ||
| 143 | pinctrl_adc0_ad0: adc0_ad0 { | ||
| 144 | atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; | ||
| 145 | }; | ||
| 146 | pinctrl_adc0_ad1: adc0_ad1 { | ||
| 147 | atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; | ||
| 148 | }; | ||
| 149 | pinctrl_adc0_ad2: adc0_ad2 { | ||
| 150 | atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; | ||
| 151 | }; | ||
| 152 | pinctrl_adc0_ad3: adc0_ad3 { | ||
| 153 | atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; | ||
| 154 | }; | ||
| 155 | pinctrl_adc0_ad4: adc0_ad4 { | ||
| 156 | atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; | ||
| 157 | }; | ||
| 158 | pinctrl_adc0_ad5: adc0_ad5 { | ||
| 159 | atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; | ||
| 160 | }; | ||
| 161 | pinctrl_adc0_ad6: adc0_ad6 { | ||
| 162 | atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; | ||
| 163 | }; | ||
| 164 | pinctrl_adc0_ad7: adc0_ad7 { | ||
| 165 | atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; | ||
| 166 | }; | ||
| 167 | }; | ||
| 168 | |||
| 139 | dbgu { | 169 | dbgu { |
| 140 | pinctrl_dbgu: dbgu-0 { | 170 | pinctrl_dbgu: dbgu-0 { |
| 141 | atmel,pins = | 171 | atmel,pins = |
| @@ -634,10 +664,9 @@ | |||
| 634 | adc0: adc@fffb0000 { | 664 | adc0: adc@fffb0000 { |
| 635 | #address-cells = <1>; | 665 | #address-cells = <1>; |
| 636 | #size-cells = <0>; | 666 | #size-cells = <0>; |
| 637 | compatible = "atmel,at91sam9260-adc"; | 667 | compatible = "atmel,at91sam9g45-adc"; |
| 638 | reg = <0xfffb0000 0x100>; | 668 | reg = <0xfffb0000 0x100>; |
| 639 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; | 669 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; |
| 640 | atmel,adc-use-external-triggers; | ||
| 641 | atmel,adc-channels-used = <0xff>; | 670 | atmel,adc-channels-used = <0xff>; |
| 642 | atmel,adc-vref = <3300>; | 671 | atmel,adc-vref = <3300>; |
| 643 | atmel,adc-startup-time = <40>; | 672 | atmel,adc-startup-time = <40>; |
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 7ff665a8c708..9f5b0a674995 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts | |||
| @@ -8,6 +8,7 @@ | |||
| 8 | */ | 8 | */ |
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | #include "at91sam9g45.dtsi" | 10 | #include "at91sam9g45.dtsi" |
| 11 | #include <dt-bindings/pwm/pwm.h> | ||
| 11 | 12 | ||
| 12 | / { | 13 | / { |
| 13 | model = "Atmel AT91SAM9M10G45-EK"; | 14 | model = "Atmel AT91SAM9M10G45-EK"; |
| @@ -130,6 +131,21 @@ | |||
| 130 | status = "okay"; | 131 | status = "okay"; |
| 131 | }; | 132 | }; |
| 132 | 133 | ||
| 134 | adc0: adc@fffb0000 { | ||
| 135 | pinctrl-names = "default"; | ||
| 136 | pinctrl-0 = < | ||
| 137 | &pinctrl_adc0_ad0 | ||
| 138 | &pinctrl_adc0_ad1 | ||
| 139 | &pinctrl_adc0_ad2 | ||
| 140 | &pinctrl_adc0_ad3 | ||
| 141 | &pinctrl_adc0_ad4 | ||
| 142 | &pinctrl_adc0_ad5 | ||
| 143 | &pinctrl_adc0_ad6 | ||
| 144 | &pinctrl_adc0_ad7>; | ||
| 145 | atmel,adc-ts-wires = <4>; | ||
| 146 | status = "okay"; | ||
| 147 | }; | ||
| 148 | |||
| 133 | pwm0: pwm@fffb8000 { | 149 | pwm0: pwm@fffb8000 { |
| 134 | status = "okay"; | 150 | status = "okay"; |
| 135 | 151 | ||
| @@ -216,14 +232,14 @@ | |||
| 216 | 232 | ||
| 217 | d6 { | 233 | d6 { |
| 218 | label = "d6"; | 234 | label = "d6"; |
| 219 | pwms = <&pwm0 3 5000 0>; | 235 | pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>; |
| 220 | max-brightness = <255>; | 236 | max-brightness = <255>; |
| 221 | linux,default-trigger = "nand-disk"; | 237 | linux,default-trigger = "nand-disk"; |
| 222 | }; | 238 | }; |
| 223 | 239 | ||
| 224 | d7 { | 240 | d7 { |
| 225 | label = "d7"; | 241 | label = "d7"; |
| 226 | pwms = <&pwm0 1 5000 0>; | 242 | pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; |
| 227 | max-brightness = <255>; | 243 | max-brightness = <255>; |
| 228 | linux,default-trigger = "mmc0"; | 244 | linux,default-trigger = "mmc0"; |
| 229 | }; | 245 | }; |
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 9f04808fc697..d1b82e6635d5 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | #include <dt-bindings/pinctrl/at91.h> | 12 | #include <dt-bindings/pinctrl/at91.h> |
| 13 | #include <dt-bindings/interrupt-controller/irq.h> | 13 | #include <dt-bindings/interrupt-controller/irq.h> |
| 14 | #include <dt-bindings/gpio/gpio.h> | 14 | #include <dt-bindings/gpio/gpio.h> |
| 15 | #include <dt-bindings/clock/at91.h> | ||
| 15 | 16 | ||
| 16 | / { | 17 | / { |
| 17 | model = "Atmel AT91SAM9N12 SoC"; | 18 | model = "Atmel AT91SAM9N12 SoC"; |
| @@ -49,6 +50,18 @@ | |||
| 49 | reg = <0x20000000 0x10000000>; | 50 | reg = <0x20000000 0x10000000>; |
| 50 | }; | 51 | }; |
| 51 | 52 | ||
| 53 | slow_xtal: slow_xtal { | ||
| 54 | compatible = "fixed-clock"; | ||
| 55 | #clock-cells = <0>; | ||
| 56 | clock-frequency = <0>; | ||
| 57 | }; | ||
| 58 | |||
| 59 | main_xtal: main_xtal { | ||
| 60 | compatible = "fixed-clock"; | ||
| 61 | #clock-cells = <0>; | ||
| 62 | clock-frequency = <0>; | ||
| 63 | }; | ||
| 64 | |||
| 52 | ahb { | 65 | ahb { |
| 53 | compatible = "simple-bus"; | 66 | compatible = "simple-bus"; |
| 54 | #address-cells = <1>; | 67 | #address-cells = <1>; |
| @@ -75,8 +88,280 @@ | |||
| 75 | }; | 88 | }; |
| 76 | 89 | ||
| 77 | pmc: pmc@fffffc00 { | 90 | pmc: pmc@fffffc00 { |
| 78 | compatible = "atmel,at91rm9200-pmc"; | 91 | compatible = "atmel,at91sam9n12-pmc"; |
| 79 | reg = <0xfffffc00 0x100>; | 92 | reg = <0xfffffc00 0x200>; |
| 93 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | ||
| 94 | interrupt-controller; | ||
| 95 | #address-cells = <1>; | ||
| 96 | #size-cells = <0>; | ||
| 97 | #interrupt-cells = <1>; | ||
| 98 | |||
| 99 | main_rc_osc: main_rc_osc { | ||
| 100 | compatible = "atmel,at91sam9x5-clk-main-rc-osc"; | ||
| 101 | #clock-cells = <0>; | ||
| 102 | interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; | ||
| 103 | clock-frequency = <12000000>; | ||
| 104 | clock-accuracy = <50000000>; | ||
| 105 | }; | ||
| 106 | |||
| 107 | main_osc: main_osc { | ||
| 108 | compatible = "atmel,at91rm9200-clk-main-osc"; | ||
| 109 | #clock-cells = <0>; | ||
| 110 | interrupts-extended = <&pmc AT91_PMC_MOSCS>; | ||
| 111 | clocks = <&main_xtal>; | ||
| 112 | }; | ||
| 113 | |||
| 114 | main: mainck { | ||
| 115 | compatible = "atmel,at91sam9x5-clk-main"; | ||
| 116 | #clock-cells = <0>; | ||
| 117 | interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; | ||
| 118 | clocks = <&main_rc_osc>, <&main_osc>; | ||
| 119 | }; | ||
| 120 | |||
| 121 | plla: pllack { | ||
| 122 | compatible = "atmel,at91rm9200-clk-pll"; | ||
| 123 | #clock-cells = <0>; | ||
| 124 | interrupts-extended = <&pmc AT91_PMC_LOCKA>; | ||
| 125 | clocks = <&main>; | ||
| 126 | reg = <0>; | ||
| 127 | atmel,clk-input-range = <2000000 32000000>; | ||
| 128 | #atmel,pll-clk-output-range-cells = <4>; | ||
| 129 | atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, | ||
| 130 | <695000000 750000000 1 0>, | ||
| 131 | <645000000 700000000 2 0>, | ||
| 132 | <595000000 650000000 3 0>, | ||
| 133 | <545000000 600000000 0 1>, | ||
| 134 | <495000000 555000000 1 1>, | ||
| 135 | <445000000 500000000 1 2>, | ||
| 136 | <400000000 450000000 1 3>; | ||
| 137 | }; | ||
| 138 | |||
| 139 | plladiv: plladivck { | ||
| 140 | compatible = "atmel,at91sam9x5-clk-plldiv"; | ||
| 141 | #clock-cells = <0>; | ||
| 142 | clocks = <&plla>; | ||
| 143 | }; | ||
| 144 | |||
| 145 | pllb: pllbck { | ||
| 146 | compatible = "atmel,at91rm9200-clk-pll"; | ||
| 147 | #clock-cells = <0>; | ||
| 148 | interrupts-extended = <&pmc AT91_PMC_LOCKB>; | ||
| 149 | clocks = <&main>; | ||
| 150 | reg = <1>; | ||
| 151 | atmel,clk-input-range = <2000000 32000000>; | ||
| 152 | #atmel,pll-clk-output-range-cells = <3>; | ||
| 153 | atmel,pll-clk-output-ranges = <30000000 100000000 0>; | ||
| 154 | }; | ||
| 155 | |||
| 156 | mck: masterck { | ||
| 157 | compatible = "atmel,at91sam9x5-clk-master"; | ||
| 158 | #clock-cells = <0>; | ||
| 159 | interrupts-extended = <&pmc AT91_PMC_MCKRDY>; | ||
| 160 | clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>; | ||
| 161 | atmel,clk-output-range = <0 133333333>; | ||
| 162 | atmel,clk-divisors = <1 2 4 3>; | ||
| 163 | atmel,master-clk-have-div3-pres; | ||
| 164 | }; | ||
| 165 | |||
| 166 | usb: usbck { | ||
| 167 | compatible = "atmel,at91sam9n12-clk-usb"; | ||
| 168 | #clock-cells = <0>; | ||
| 169 | clocks = <&pllb>; | ||
| 170 | }; | ||
| 171 | |||
| 172 | prog: progck { | ||
| 173 | compatible = "atmel,at91sam9x5-clk-programmable"; | ||
| 174 | #address-cells = <1>; | ||
| 175 | #size-cells = <0>; | ||
| 176 | interrupt-parent = <&pmc>; | ||
| 177 | clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>; | ||
| 178 | |||
| 179 | prog0: prog0 { | ||
| 180 | #clock-cells = <0>; | ||
| 181 | reg = <0>; | ||
| 182 | interrupts = <AT91_PMC_PCKRDY(0)>; | ||
| 183 | }; | ||
| 184 | |||
| 185 | prog1: prog1 { | ||
| 186 | #clock-cells = <0>; | ||
| 187 | reg = <1>; | ||
| 188 | interrupts = <AT91_PMC_PCKRDY(1)>; | ||
| 189 | }; | ||
| 190 | }; | ||
| 191 | |||
| 192 | systemck { | ||
| 193 | compatible = "atmel,at91rm9200-clk-system"; | ||
| 194 | #address-cells = <1>; | ||
| 195 | #size-cells = <0>; | ||
| 196 | |||
| 197 | ddrck: ddrck { | ||
| 198 | #clock-cells = <0>; | ||
| 199 | reg = <2>; | ||
| 200 | clocks = <&mck>; | ||
| 201 | }; | ||
| 202 | |||
| 203 | lcdck: lcdck { | ||
| 204 | #clock-cells = <0>; | ||
| 205 | reg = <3>; | ||
| 206 | clocks = <&mck>; | ||
| 207 | }; | ||
| 208 | |||
| 209 | uhpck: uhpck { | ||
| 210 | #clock-cells = <0>; | ||
| 211 | reg = <6>; | ||
| 212 | clocks = <&usb>; | ||
| 213 | }; | ||
| 214 | |||
| 215 | udpck: udpck { | ||
| 216 | #clock-cells = <0>; | ||
| 217 | reg = <7>; | ||
| 218 | clocks = <&usb>; | ||
| 219 | }; | ||
| 220 | |||
| 221 | pck0: pck0 { | ||
| 222 | #clock-cells = <0>; | ||
| 223 | reg = <8>; | ||
| 224 | clocks = <&prog0>; | ||
| 225 | }; | ||
| 226 | |||
| 227 | pck1: pck1 { | ||
| 228 | #clock-cells = <0>; | ||
| 229 | reg = <9>; | ||
| 230 | clocks = <&prog1>; | ||
| 231 | }; | ||
| 232 | }; | ||
| 233 | |||
| 234 | periphck { | ||
| 235 | compatible = "atmel,at91sam9x5-clk-peripheral"; | ||
| 236 | #address-cells = <1>; | ||
| 237 | #size-cells = <0>; | ||
| 238 | clocks = <&mck>; | ||
| 239 | |||
| 240 | pioAB_clk: pioAB_clk { | ||
| 241 | #clock-cells = <0>; | ||
| 242 | reg = <2>; | ||
| 243 | }; | ||
| 244 | |||
| 245 | pioCD_clk: pioCD_clk { | ||
| 246 | #clock-cells = <0>; | ||
| 247 | reg = <3>; | ||
| 248 | }; | ||
| 249 | |||
| 250 | fuse_clk: fuse_clk { | ||
| 251 | #clock-cells = <0>; | ||
| 252 | reg = <4>; | ||
| 253 | }; | ||
| 254 | |||
| 255 | usart0_clk: usart0_clk { | ||
| 256 | #clock-cells = <0>; | ||
| 257 | reg = <5>; | ||
| 258 | }; | ||
| 259 | |||
| 260 | usart1_clk: usart1_clk { | ||
| 261 | #clock-cells = <0>; | ||
| 262 | reg = <6>; | ||
| 263 | }; | ||
| 264 | |||
| 265 | usart2_clk: usart2_clk { | ||
| 266 | #clock-cells = <0>; | ||
| 267 | reg = <7>; | ||
| 268 | }; | ||
| 269 | |||
| 270 | usart3_clk: usart3_clk { | ||
| 271 | #clock-cells = <0>; | ||
| 272 | reg = <8>; | ||
| 273 | }; | ||
| 274 | |||
| 275 | twi0_clk: twi0_clk { | ||
| 276 | reg = <9>; | ||
| 277 | #clock-cells = <0>; | ||
| 278 | }; | ||
| 279 | |||
| 280 | twi1_clk: twi1_clk { | ||
| 281 | #clock-cells = <0>; | ||
| 282 | reg = <10>; | ||
| 283 | }; | ||
| 284 | |||
| 285 | mci0_clk: mci0_clk { | ||
| 286 | #clock-cells = <0>; | ||
| 287 | reg = <12>; | ||
| 288 | }; | ||
| 289 | |||
| 290 | spi0_clk: spi0_clk { | ||
| 291 | #clock-cells = <0>; | ||
| 292 | reg = <13>; | ||
| 293 | }; | ||
| 294 | |||
| 295 | spi1_clk: spi1_clk { | ||
| 296 | #clock-cells = <0>; | ||
| 297 | reg = <14>; | ||
| 298 | }; | ||
| 299 | |||
| 300 | uart0_clk: uart0_clk { | ||
| 301 | #clock-cells = <0>; | ||
| 302 | reg = <15>; | ||
| 303 | }; | ||
| 304 | |||
| 305 | uart1_clk: uart1_clk { | ||
| 306 | #clock-cells = <0>; | ||
| 307 | reg = <16>; | ||
| 308 | }; | ||
| 309 | |||
| 310 | tcb_clk: tcb_clk { | ||
| 311 | #clock-cells = <0>; | ||
| 312 | reg = <17>; | ||
| 313 | }; | ||
| 314 | |||
| 315 | pwm_clk: pwm_clk { | ||
| 316 | #clock-cells = <0>; | ||
| 317 | reg = <18>; | ||
| 318 | }; | ||
| 319 | |||
| 320 | adc_clk: adc_clk { | ||
| 321 | #clock-cells = <0>; | ||
| 322 | reg = <19>; | ||
| 323 | }; | ||
| 324 | |||
| 325 | dma0_clk: dma0_clk { | ||
| 326 | #clock-cells = <0>; | ||
| 327 | reg = <20>; | ||
| 328 | }; | ||
| 329 | |||
| 330 | uhphs_clk: uhphs_clk { | ||
| 331 | #clock-cells = <0>; | ||
| 332 | reg = <22>; | ||
| 333 | }; | ||
| 334 | |||
| 335 | udphs_clk: udphs_clk { | ||
| 336 | #clock-cells = <0>; | ||
| 337 | reg = <23>; | ||
| 338 | }; | ||
| 339 | |||
| 340 | lcdc_clk: lcdc_clk { | ||
| 341 | #clock-cells = <0>; | ||
| 342 | reg = <25>; | ||
| 343 | }; | ||
| 344 | |||
| 345 | sha_clk: sha_clk { | ||
| 346 | #clock-cells = <0>; | ||
| 347 | reg = <27>; | ||
| 348 | }; | ||
| 349 | |||
| 350 | ssc0_clk: ssc0_clk { | ||
| 351 | #clock-cells = <0>; | ||
| 352 | reg = <28>; | ||
| 353 | }; | ||
| 354 | |||
| 355 | aes_clk: aes_clk { | ||
| 356 | #clock-cells = <0>; | ||
| 357 | reg = <29>; | ||
| 358 | }; | ||
| 359 | |||
| 360 | trng_clk: trng_clk { | ||
| 361 | #clock-cells = <0>; | ||
| 362 | reg = <30>; | ||
| 363 | }; | ||
| 364 | }; | ||
| 80 | }; | 365 | }; |
| 81 | 366 | ||
| 82 | rstc@fffffe00 { | 367 | rstc@fffffe00 { |
| @@ -88,6 +373,7 @@ | |||
| 88 | compatible = "atmel,at91sam9260-pit"; | 373 | compatible = "atmel,at91sam9260-pit"; |
| 89 | reg = <0xfffffe30 0xf>; | 374 | reg = <0xfffffe30 0xf>; |
| 90 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | 375 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 376 | clocks = <&mck>; | ||
| 91 | }; | 377 | }; |
| 92 | 378 | ||
| 93 | shdwc@fffffe10 { | 379 | shdwc@fffffe10 { |
| @@ -95,12 +381,38 @@ | |||
| 95 | reg = <0xfffffe10 0x10>; | 381 | reg = <0xfffffe10 0x10>; |
| 96 | }; | 382 | }; |
| 97 | 383 | ||
| 384 | sckc@fffffe50 { | ||
| 385 | compatible = "atmel,at91sam9x5-sckc"; | ||
| 386 | reg = <0xfffffe50 0x4>; | ||
| 387 | |||
| 388 | slow_osc: slow_osc { | ||
| 389 | compatible = "atmel,at91sam9x5-clk-slow-osc"; | ||
| 390 | #clock-cells = <0>; | ||
| 391 | clocks = <&slow_xtal>; | ||
| 392 | }; | ||
| 393 | |||
| 394 | slow_rc_osc: slow_rc_osc { | ||
| 395 | compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; | ||
| 396 | #clock-cells = <0>; | ||
| 397 | clock-frequency = <32768>; | ||
| 398 | clock-accuracy = <50000000>; | ||
| 399 | }; | ||
| 400 | |||
| 401 | clk32k: slck { | ||
| 402 | compatible = "atmel,at91sam9x5-clk-slow"; | ||
| 403 | #clock-cells = <0>; | ||
| 404 | clocks = <&slow_rc_osc>, <&slow_osc>; | ||
| 405 | }; | ||
| 406 | }; | ||
| 407 | |||
| 98 | mmc0: mmc@f0008000 { | 408 | mmc0: mmc@f0008000 { |
| 99 | compatible = "atmel,hsmci"; | 409 | compatible = "atmel,hsmci"; |
| 100 | reg = <0xf0008000 0x600>; | 410 | reg = <0xf0008000 0x600>; |
| 101 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; | 411 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; |
| 102 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; | 412 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; |
| 103 | dma-names = "rxtx"; | 413 | dma-names = "rxtx"; |
| 414 | clocks = <&mci0_clk>; | ||
| 415 | clock-names = "mci_clk"; | ||
| 104 | #address-cells = <1>; | 416 | #address-cells = <1>; |
| 105 | #size-cells = <0>; | 417 | #size-cells = <0>; |
| 106 | status = "disabled"; | 418 | status = "disabled"; |
| @@ -110,12 +422,16 @@ | |||
| 110 | compatible = "atmel,at91sam9x5-tcb"; | 422 | compatible = "atmel,at91sam9x5-tcb"; |
| 111 | reg = <0xf8008000 0x100>; | 423 | reg = <0xf8008000 0x100>; |
| 112 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; | 424 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; |
| 425 | clocks = <&tcb_clk>; | ||
| 426 | clock-names = "t0_clk"; | ||
| 113 | }; | 427 | }; |
| 114 | 428 | ||
| 115 | tcb1: timer@f800c000 { | 429 | tcb1: timer@f800c000 { |
| 116 | compatible = "atmel,at91sam9x5-tcb"; | 430 | compatible = "atmel,at91sam9x5-tcb"; |
| 117 | reg = <0xf800c000 0x100>; | 431 | reg = <0xf800c000 0x100>; |
| 118 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; | 432 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; |
| 433 | clocks = <&tcb_clk>; | ||
| 434 | clock-names = "t0_clk"; | ||
| 119 | }; | 435 | }; |
| 120 | 436 | ||
| 121 | dma: dma-controller@ffffec00 { | 437 | dma: dma-controller@ffffec00 { |
| @@ -123,6 +439,8 @@ | |||
| 123 | reg = <0xffffec00 0x200>; | 439 | reg = <0xffffec00 0x200>; |
| 124 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; | 440 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; |
| 125 | #dma-cells = <2>; | 441 | #dma-cells = <2>; |
| 442 | clocks = <&dma0_clk>; | ||
| 443 | clock-names = "dma_clk"; | ||
| 126 | }; | 444 | }; |
| 127 | 445 | ||
| 128 | pinctrl@fffff400 { | 446 | pinctrl@fffff400 { |
| @@ -392,6 +710,7 @@ | |||
| 392 | gpio-controller; | 710 | gpio-controller; |
| 393 | interrupt-controller; | 711 | interrupt-controller; |
| 394 | #interrupt-cells = <2>; | 712 | #interrupt-cells = <2>; |
| 713 | clocks = <&pioAB_clk>; | ||
| 395 | }; | 714 | }; |
| 396 | 715 | ||
| 397 | pioB: gpio@fffff600 { | 716 | pioB: gpio@fffff600 { |
| @@ -402,6 +721,7 @@ | |||
| 402 | gpio-controller; | 721 | gpio-controller; |
| 403 | interrupt-controller; | 722 | interrupt-controller; |
| 404 | #interrupt-cells = <2>; | 723 | #interrupt-cells = <2>; |
| 724 | clocks = <&pioAB_clk>; | ||
| 405 | }; | 725 | }; |
| 406 | 726 | ||
| 407 | pioC: gpio@fffff800 { | 727 | pioC: gpio@fffff800 { |
| @@ -412,6 +732,7 @@ | |||
| 412 | gpio-controller; | 732 | gpio-controller; |
| 413 | interrupt-controller; | 733 | interrupt-controller; |
| 414 | #interrupt-cells = <2>; | 734 | #interrupt-cells = <2>; |
| 735 | clocks = <&pioCD_clk>; | ||
| 415 | }; | 736 | }; |
| 416 | 737 | ||
| 417 | pioD: gpio@fffffa00 { | 738 | pioD: gpio@fffffa00 { |
| @@ -422,6 +743,7 @@ | |||
| 422 | gpio-controller; | 743 | gpio-controller; |
| 423 | interrupt-controller; | 744 | interrupt-controller; |
| 424 | #interrupt-cells = <2>; | 745 | #interrupt-cells = <2>; |
| 746 | clocks = <&pioCD_clk>; | ||
| 425 | }; | 747 | }; |
| 426 | }; | 748 | }; |
| 427 | 749 | ||
| @@ -431,6 +753,8 @@ | |||
| 431 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | 753 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 432 | pinctrl-names = "default"; | 754 | pinctrl-names = "default"; |
| 433 | pinctrl-0 = <&pinctrl_dbgu>; | 755 | pinctrl-0 = <&pinctrl_dbgu>; |
| 756 | clocks = <&mck>; | ||
| 757 | clock-names = "usart"; | ||
| 434 | status = "disabled"; | 758 | status = "disabled"; |
| 435 | }; | 759 | }; |
| 436 | 760 | ||
| @@ -443,6 +767,8 @@ | |||
| 443 | dma-names = "tx", "rx"; | 767 | dma-names = "tx", "rx"; |
| 444 | pinctrl-names = "default"; | 768 | pinctrl-names = "default"; |
| 445 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | 769 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 770 | clocks = <&ssc0_clk>; | ||
| 771 | clock-names = "pclk"; | ||
| 446 | status = "disabled"; | 772 | status = "disabled"; |
| 447 | }; | 773 | }; |
| 448 | 774 | ||
| @@ -452,6 +778,8 @@ | |||
| 452 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; | 778 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; |
| 453 | pinctrl-names = "default"; | 779 | pinctrl-names = "default"; |
| 454 | pinctrl-0 = <&pinctrl_usart0>; | 780 | pinctrl-0 = <&pinctrl_usart0>; |
| 781 | clocks = <&usart0_clk>; | ||
| 782 | clock-names = "usart"; | ||
| 455 | status = "disabled"; | 783 | status = "disabled"; |
| 456 | }; | 784 | }; |
| 457 | 785 | ||
| @@ -461,6 +789,8 @@ | |||
| 461 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; | 789 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; |
| 462 | pinctrl-names = "default"; | 790 | pinctrl-names = "default"; |
| 463 | pinctrl-0 = <&pinctrl_usart1>; | 791 | pinctrl-0 = <&pinctrl_usart1>; |
| 792 | clocks = <&usart1_clk>; | ||
| 793 | clock-names = "usart"; | ||
| 464 | status = "disabled"; | 794 | status = "disabled"; |
| 465 | }; | 795 | }; |
| 466 | 796 | ||
| @@ -470,6 +800,8 @@ | |||
| 470 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; | 800 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
| 471 | pinctrl-names = "default"; | 801 | pinctrl-names = "default"; |
| 472 | pinctrl-0 = <&pinctrl_usart2>; | 802 | pinctrl-0 = <&pinctrl_usart2>; |
| 803 | clocks = <&usart2_clk>; | ||
| 804 | clock-names = "usart"; | ||
| 473 | status = "disabled"; | 805 | status = "disabled"; |
| 474 | }; | 806 | }; |
| 475 | 807 | ||
| @@ -479,6 +811,8 @@ | |||
| 479 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; | 811 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; |
| 480 | pinctrl-names = "default"; | 812 | pinctrl-names = "default"; |
| 481 | pinctrl-0 = <&pinctrl_usart3>; | 813 | pinctrl-0 = <&pinctrl_usart3>; |
| 814 | clocks = <&usart3_clk>; | ||
| 815 | clock-names = "usart"; | ||
| 482 | status = "disabled"; | 816 | status = "disabled"; |
| 483 | }; | 817 | }; |
| 484 | 818 | ||
| @@ -493,6 +827,7 @@ | |||
| 493 | #size-cells = <0>; | 827 | #size-cells = <0>; |
| 494 | pinctrl-names = "default"; | 828 | pinctrl-names = "default"; |
| 495 | pinctrl-0 = <&pinctrl_i2c0>; | 829 | pinctrl-0 = <&pinctrl_i2c0>; |
| 830 | clocks = <&twi0_clk>; | ||
| 496 | status = "disabled"; | 831 | status = "disabled"; |
| 497 | }; | 832 | }; |
| 498 | 833 | ||
| @@ -507,6 +842,7 @@ | |||
| 507 | #size-cells = <0>; | 842 | #size-cells = <0>; |
| 508 | pinctrl-names = "default"; | 843 | pinctrl-names = "default"; |
| 509 | pinctrl-0 = <&pinctrl_i2c1>; | 844 | pinctrl-0 = <&pinctrl_i2c1>; |
| 845 | clocks = <&twi1_clk>; | ||
| 510 | status = "disabled"; | 846 | status = "disabled"; |
| 511 | }; | 847 | }; |
| 512 | 848 | ||
| @@ -521,6 +857,8 @@ | |||
| 521 | dma-names = "tx", "rx"; | 857 | dma-names = "tx", "rx"; |
| 522 | pinctrl-names = "default"; | 858 | pinctrl-names = "default"; |
| 523 | pinctrl-0 = <&pinctrl_spi0>; | 859 | pinctrl-0 = <&pinctrl_spi0>; |
| 860 | clocks = <&spi0_clk>; | ||
| 861 | clock-names = "spi_clk"; | ||
| 524 | status = "disabled"; | 862 | status = "disabled"; |
| 525 | }; | 863 | }; |
| 526 | 864 | ||
| @@ -535,6 +873,8 @@ | |||
| 535 | dma-names = "tx", "rx"; | 873 | dma-names = "tx", "rx"; |
| 536 | pinctrl-names = "default"; | 874 | pinctrl-names = "default"; |
| 537 | pinctrl-0 = <&pinctrl_spi1>; | 875 | pinctrl-0 = <&pinctrl_spi1>; |
| 876 | clocks = <&spi1_clk>; | ||
| 877 | clock-names = "spi_clk"; | ||
| 538 | status = "disabled"; | 878 | status = "disabled"; |
| 539 | }; | 879 | }; |
| 540 | 880 | ||
| @@ -554,6 +894,7 @@ | |||
| 554 | reg = <0xf8034000 0x300>; | 894 | reg = <0xf8034000 0x300>; |
| 555 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; | 895 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; |
| 556 | #pwm-cells = <3>; | 896 | #pwm-cells = <3>; |
| 897 | clocks = <&pwm_clk>; | ||
| 557 | status = "disabled"; | 898 | status = "disabled"; |
| 558 | }; | 899 | }; |
| 559 | }; | 900 | }; |
| @@ -584,6 +925,9 @@ | |||
| 584 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 925 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 585 | reg = <0x00500000 0x00100000>; | 926 | reg = <0x00500000 0x00100000>; |
| 586 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; | 927 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
| 928 | clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>, | ||
| 929 | <&uhpck>; | ||
| 930 | clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; | ||
| 587 | status = "disabled"; | 931 | status = "disabled"; |
| 588 | }; | 932 | }; |
| 589 | }; | 933 | }; |
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 924a6a6ffd0f..64bbe46e4f90 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts | |||
| @@ -21,6 +21,14 @@ | |||
| 21 | reg = <0x20000000 0x8000000>; | 21 | reg = <0x20000000 0x8000000>; |
| 22 | }; | 22 | }; |
| 23 | 23 | ||
| 24 | slow_xtal { | ||
| 25 | clock-frequency = <32768>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | main_xtal { | ||
| 29 | clock-frequency = <16000000>; | ||
| 30 | }; | ||
| 31 | |||
| 24 | clocks { | 32 | clocks { |
| 25 | #address-cells = <1>; | 33 | #address-cells = <1>; |
| 26 | #size-cells = <1>; | 34 | #size-cells = <1>; |
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 92a52faebef7..1da183155eee 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | #include <dt-bindings/clock/at91.h> | 11 | #include <dt-bindings/clock/at91.h> |
| 12 | #include <dt-bindings/interrupt-controller/irq.h> | 12 | #include <dt-bindings/interrupt-controller/irq.h> |
| 13 | #include <dt-bindings/gpio/gpio.h> | 13 | #include <dt-bindings/gpio/gpio.h> |
| 14 | #include <dt-bindings/pwm/pwm.h> | ||
| 14 | 15 | ||
| 15 | / { | 16 | / { |
| 16 | model = "Atmel AT91SAM9RL family SoC"; | 17 | model = "Atmel AT91SAM9RL family SoC"; |
| @@ -32,6 +33,7 @@ | |||
| 32 | i2c1 = &i2c1; | 33 | i2c1 = &i2c1; |
| 33 | ssc0 = &ssc0; | 34 | ssc0 = &ssc0; |
| 34 | ssc1 = &ssc1; | 35 | ssc1 = &ssc1; |
| 36 | pwm0 = &pwm0; | ||
| 35 | }; | 37 | }; |
| 36 | 38 | ||
| 37 | cpus { | 39 | cpus { |
| @@ -48,12 +50,43 @@ | |||
| 48 | reg = <0x20000000 0x04000000>; | 50 | reg = <0x20000000 0x04000000>; |
| 49 | }; | 51 | }; |
| 50 | 52 | ||
| 53 | slow_xtal: slow_xtal { | ||
| 54 | compatible = "fixed-clock"; | ||
| 55 | #clock-cells = <0>; | ||
| 56 | clock-frequency = <0>; | ||
| 57 | }; | ||
| 58 | |||
| 59 | main_xtal: main_xtal { | ||
| 60 | compatible = "fixed-clock"; | ||
| 61 | #clock-cells = <0>; | ||
| 62 | clock-frequency = <0>; | ||
| 63 | }; | ||
| 64 | |||
| 65 | clocks { | ||
| 66 | adc_op_clk: adc_op_clk{ | ||
| 67 | compatible = "fixed-clock"; | ||
| 68 | #clock-cells = <0>; | ||
| 69 | clock-frequency = <1000000>; | ||
| 70 | }; | ||
| 71 | }; | ||
| 72 | |||
| 51 | ahb { | 73 | ahb { |
| 52 | compatible = "simple-bus"; | 74 | compatible = "simple-bus"; |
| 53 | #address-cells = <1>; | 75 | #address-cells = <1>; |
| 54 | #size-cells = <1>; | 76 | #size-cells = <1>; |
| 55 | ranges; | 77 | ranges; |
| 56 | 78 | ||
| 79 | fb0: fb@00500000 { | ||
| 80 | compatible = "atmel,at91sam9rl-lcdc"; | ||
| 81 | reg = <0x00500000 0x1000>; | ||
| 82 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; | ||
| 83 | pinctrl-names = "default"; | ||
| 84 | pinctrl-0 = <&pinctrl_fb>; | ||
| 85 | clocks = <&lcd_clk>, <&lcd_clk>; | ||
| 86 | clock-names = "hclk", "lcdc_clk"; | ||
| 87 | status = "disabled"; | ||
| 88 | }; | ||
| 89 | |||
| 57 | nand0: nand@40000000 { | 90 | nand0: nand@40000000 { |
| 58 | compatible = "atmel,at91rm9200-nand"; | 91 | compatible = "atmel,at91rm9200-nand"; |
| 59 | #address-cells = <1>; | 92 | #address-cells = <1>; |
| @@ -187,6 +220,16 @@ | |||
| 187 | status = "disabled"; | 220 | status = "disabled"; |
| 188 | }; | 221 | }; |
| 189 | 222 | ||
| 223 | pwm0: pwm@fffc8000 { | ||
| 224 | compatible = "atmel,at91sam9rl-pwm"; | ||
| 225 | reg = <0xfffc8000 0x300>; | ||
| 226 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; | ||
| 227 | #pwm-cells = <3>; | ||
| 228 | clocks = <&pwm_clk>; | ||
| 229 | clock-names = "pwm_clk"; | ||
| 230 | status = "disabled"; | ||
| 231 | }; | ||
| 232 | |||
| 190 | spi0: spi@fffcc000 { | 233 | spi0: spi@fffcc000 { |
| 191 | #address-cells = <1>; | 234 | #address-cells = <1>; |
| 192 | #size-cells = <0>; | 235 | #size-cells = <0>; |
| @@ -200,6 +243,111 @@ | |||
| 200 | status = "disabled"; | 243 | status = "disabled"; |
| 201 | }; | 244 | }; |
| 202 | 245 | ||
| 246 | adc0: adc@fffd0000 { | ||
| 247 | #address-cells = <1>; | ||
| 248 | #size-cells = <0>; | ||
| 249 | compatible = "atmel,at91sam9rl-adc"; | ||
| 250 | reg = <0xfffd0000 0x100>; | ||
| 251 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; | ||
| 252 | clocks = <&adc_clk>, <&adc_op_clk>; | ||
| 253 | clock-names = "adc_clk", "adc_op_clk"; | ||
| 254 | atmel,adc-use-external-triggers; | ||
| 255 | atmel,adc-channels-used = <0x3f>; | ||
| 256 | atmel,adc-vref = <3300>; | ||
| 257 | atmel,adc-startup-time = <40>; | ||
| 258 | atmel,adc-res = <8 10>; | ||
| 259 | atmel,adc-res-names = "lowres", "highres"; | ||
| 260 | atmel,adc-use-res = "highres"; | ||
| 261 | |||
| 262 | trigger@0 { | ||
| 263 | reg = <0>; | ||
| 264 | trigger-name = "timer-counter-0"; | ||
| 265 | trigger-value = <0x1>; | ||
| 266 | }; | ||
| 267 | trigger@1 { | ||
| 268 | reg = <1>; | ||
| 269 | trigger-name = "timer-counter-1"; | ||
| 270 | trigger-value = <0x3>; | ||
| 271 | }; | ||
| 272 | |||
| 273 | trigger@2 { | ||
| 274 | reg = <2>; | ||
| 275 | trigger-name = "timer-counter-2"; | ||
| 276 | trigger-value = <0x5>; | ||
| 277 | }; | ||
| 278 | |||
| 279 | trigger@3 { | ||
| 280 | reg = <3>; | ||
| 281 | trigger-name = "external"; | ||
| 282 | trigger-value = <0x13>; | ||
| 283 | trigger-external; | ||
| 284 | }; | ||
| 285 | }; | ||
| 286 | |||
| 287 | usb0: gadget@fffd4000 { | ||
| 288 | #address-cells = <1>; | ||
| 289 | #size-cells = <0>; | ||
| 290 | compatible = "atmel,at91sam9rl-udc"; | ||
| 291 | reg = <0x00600000 0x100000>, | ||
| 292 | <0xfffd4000 0x4000>; | ||
| 293 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; | ||
| 294 | clocks = <&udphs_clk>, <&utmi>; | ||
| 295 | clock-names = "pclk", "hclk"; | ||
| 296 | status = "disabled"; | ||
| 297 | |||
| 298 | ep0 { | ||
| 299 | reg = <0>; | ||
| 300 | atmel,fifo-size = <64>; | ||
| 301 | atmel,nb-banks = <1>; | ||
| 302 | }; | ||
| 303 | |||
| 304 | ep1 { | ||
| 305 | reg = <1>; | ||
| 306 | atmel,fifo-size = <1024>; | ||
| 307 | atmel,nb-banks = <2>; | ||
| 308 | atmel,can-dma; | ||
| 309 | atmel,can-isoc; | ||
| 310 | }; | ||
| 311 | |||
| 312 | ep2 { | ||
| 313 | reg = <2>; | ||
| 314 | atmel,fifo-size = <1024>; | ||
| 315 | atmel,nb-banks = <2>; | ||
| 316 | atmel,can-dma; | ||
| 317 | atmel,can-isoc; | ||
| 318 | }; | ||
| 319 | |||
| 320 | ep3 { | ||
| 321 | reg = <3>; | ||
| 322 | atmel,fifo-size = <1024>; | ||
| 323 | atmel,nb-banks = <3>; | ||
| 324 | atmel,can-dma; | ||
| 325 | }; | ||
| 326 | |||
| 327 | ep4 { | ||
| 328 | reg = <4>; | ||
| 329 | atmel,fifo-size = <1024>; | ||
| 330 | atmel,nb-banks = <3>; | ||
| 331 | atmel,can-dma; | ||
| 332 | }; | ||
| 333 | |||
| 334 | ep5 { | ||
| 335 | reg = <5>; | ||
| 336 | atmel,fifo-size = <1024>; | ||
| 337 | atmel,nb-banks = <3>; | ||
| 338 | atmel,can-dma; | ||
| 339 | atmel,can-isoc; | ||
| 340 | }; | ||
| 341 | |||
| 342 | ep6 { | ||
| 343 | reg = <6>; | ||
| 344 | atmel,fifo-size = <1024>; | ||
| 345 | atmel,nb-banks = <3>; | ||
| 346 | atmel,can-dma; | ||
| 347 | atmel,can-isoc; | ||
| 348 | }; | ||
| 349 | }; | ||
| 350 | |||
| 203 | ramc0: ramc@ffffea00 { | 351 | ramc0: ramc@ffffea00 { |
| 204 | compatible = "atmel,at91sam9260-sdramc"; | 352 | compatible = "atmel,at91sam9260-sdramc"; |
| 205 | reg = <0xffffea00 0x200>; | 353 | reg = <0xffffea00 0x200>; |
| @@ -238,6 +386,44 @@ | |||
| 238 | <0x003fffff 0x0001ff3c>; /* pioD */ | 386 | <0x003fffff 0x0001ff3c>; /* pioD */ |
| 239 | 387 | ||
| 240 | /* shared pinctrl settings */ | 388 | /* shared pinctrl settings */ |
| 389 | adc0 { | ||
| 390 | pinctrl_adc0_ts: adc0_ts-0 { | ||
| 391 | atmel,pins = | ||
| 392 | <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>, | ||
| 393 | <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>, | ||
| 394 | <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>, | ||
| 395 | <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 396 | }; | ||
| 397 | |||
| 398 | pinctrl_adc0_ad0: adc0_ad0-0 { | ||
| 399 | atmel,pins = <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 400 | }; | ||
| 401 | |||
| 402 | pinctrl_adc0_ad1: adc0_ad1-0 { | ||
| 403 | atmel,pins = <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 404 | }; | ||
| 405 | |||
| 406 | pinctrl_adc0_ad2: adc0_ad2-0 { | ||
| 407 | atmel,pins = <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 408 | }; | ||
| 409 | |||
| 410 | pinctrl_adc0_ad3: adc0_ad3-0 { | ||
| 411 | atmel,pins = <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 412 | }; | ||
| 413 | |||
| 414 | pinctrl_adc0_ad4: adc0_ad4-0 { | ||
| 415 | atmel,pins = <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 416 | }; | ||
| 417 | |||
| 418 | pinctrl_adc0_ad5: adc0_ad5-0 { | ||
| 419 | atmel,pins = <AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 420 | }; | ||
| 421 | |||
| 422 | pinctrl_adc0_adtrg: adc0_adtrg-0 { | ||
| 423 | atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 424 | }; | ||
| 425 | }; | ||
| 426 | |||
| 241 | dbgu { | 427 | dbgu { |
| 242 | pinctrl_dbgu: dbgu-0 { | 428 | pinctrl_dbgu: dbgu-0 { |
| 243 | atmel,pins = | 429 | atmel,pins = |
| @@ -246,6 +432,33 @@ | |||
| 246 | }; | 432 | }; |
| 247 | }; | 433 | }; |
| 248 | 434 | ||
| 435 | fb { | ||
| 436 | pinctrl_fb: fb-0 { | ||
| 437 | atmel,pins = | ||
| 438 | <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 439 | <AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE>, | ||
| 440 | <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE>, | ||
| 441 | <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>, | ||
| 442 | <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>, | ||
| 443 | <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 444 | <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 445 | <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 446 | <AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 447 | <AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 448 | <AT91_PIOC 15 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 449 | <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 450 | <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 451 | <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 452 | <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 453 | <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 454 | <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 455 | <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 456 | <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 457 | <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>, | ||
| 458 | <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 459 | }; | ||
| 460 | }; | ||
| 461 | |||
| 249 | i2c_gpio0 { | 462 | i2c_gpio0 { |
| 250 | pinctrl_i2c_gpio0: i2c_gpio0-0 { | 463 | pinctrl_i2c_gpio0: i2c_gpio0-0 { |
| 251 | atmel,pins = | 464 | atmel,pins = |
| @@ -307,6 +520,61 @@ | |||
| 307 | }; | 520 | }; |
| 308 | }; | 521 | }; |
| 309 | 522 | ||
| 523 | pwm0 { | ||
| 524 | pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { | ||
| 525 | atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 526 | }; | ||
| 527 | |||
| 528 | pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { | ||
| 529 | atmel,pins = <AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 530 | }; | ||
| 531 | |||
| 532 | pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { | ||
| 533 | atmel,pins = <AT91_PIOD 14 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 534 | }; | ||
| 535 | |||
| 536 | pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { | ||
| 537 | atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 538 | }; | ||
| 539 | |||
| 540 | pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { | ||
| 541 | atmel,pins = <AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 542 | }; | ||
| 543 | |||
| 544 | pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { | ||
| 545 | atmel,pins = <AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 546 | }; | ||
| 547 | |||
| 548 | pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { | ||
| 549 | atmel,pins = <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 550 | }; | ||
| 551 | |||
| 552 | pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { | ||
| 553 | atmel,pins = <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 554 | }; | ||
| 555 | |||
| 556 | pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 { | ||
| 557 | atmel,pins = <AT91_PIOD 16 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 558 | }; | ||
| 559 | |||
| 560 | pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { | ||
| 561 | atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 562 | }; | ||
| 563 | |||
| 564 | pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { | ||
| 565 | atmel,pins = <AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 566 | }; | ||
| 567 | }; | ||
| 568 | |||
| 569 | spi0 { | ||
| 570 | pinctrl_spi0: spi0-0 { | ||
| 571 | atmel,pins = | ||
| 572 | <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>, | ||
| 573 | <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>, | ||
| 574 | <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 575 | }; | ||
| 576 | }; | ||
| 577 | |||
| 310 | ssc0 { | 578 | ssc0 { |
| 311 | pinctrl_ssc0_tx: ssc0_tx-0 { | 579 | pinctrl_ssc0_tx: ssc0_tx-0 { |
| 312 | atmel,pins = | 580 | atmel,pins = |
| @@ -339,15 +607,6 @@ | |||
| 339 | }; | 607 | }; |
| 340 | }; | 608 | }; |
| 341 | 609 | ||
| 342 | spi0 { | ||
| 343 | pinctrl_spi0: spi0-0 { | ||
| 344 | atmel,pins = | ||
| 345 | <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>, | ||
| 346 | <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>, | ||
| 347 | <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 348 | }; | ||
| 349 | }; | ||
| 350 | |||
| 351 | tcb0 { | 610 | tcb0 { |
| 352 | pinctrl_tcb0_tclk0: tcb0_tclk0-0 { | 611 | pinctrl_tcb0_tclk0: tcb0_tclk0-0 { |
| 353 | atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; | 612 | atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| @@ -548,17 +807,11 @@ | |||
| 548 | #size-cells = <0>; | 807 | #size-cells = <0>; |
| 549 | #interrupt-cells = <1>; | 808 | #interrupt-cells = <1>; |
| 550 | 809 | ||
| 551 | clk32k: slck { | ||
| 552 | compatible = "fixed-clock"; | ||
| 553 | #clock-cells = <0>; | ||
| 554 | clock-frequency = <32768>; | ||
| 555 | }; | ||
| 556 | |||
| 557 | main: mainck { | 810 | main: mainck { |
| 558 | compatible = "atmel,at91rm9200-clk-main"; | 811 | compatible = "atmel,at91rm9200-clk-main"; |
| 559 | #clock-cells = <0>; | 812 | #clock-cells = <0>; |
| 560 | interrupts-extended = <&pmc AT91_PMC_MOSCS>; | 813 | interrupts-extended = <&pmc AT91_PMC_MOSCS>; |
| 561 | clocks = <&clk32k>; | 814 | clocks = <&main_xtal>; |
| 562 | }; | 815 | }; |
| 563 | 816 | ||
| 564 | plla: pllack { | 817 | plla: pllack { |
| @@ -568,8 +821,9 @@ | |||
| 568 | clocks = <&main>; | 821 | clocks = <&main>; |
| 569 | reg = <0>; | 822 | reg = <0>; |
| 570 | atmel,clk-input-range = <1000000 32000000>; | 823 | atmel,clk-input-range = <1000000 32000000>; |
| 571 | #atmel,pll-clk-output-range-cells = <4>; | 824 | #atmel,pll-clk-output-range-cells = <3>; |
| 572 | atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>; | 825 | atmel,pll-clk-output-ranges = <80000000 200000000 0>, |
| 826 | <190000000 240000000 2>; | ||
| 573 | }; | 827 | }; |
| 574 | 828 | ||
| 575 | utmi: utmick { | 829 | utmi: utmick { |
| @@ -586,7 +840,7 @@ | |||
| 586 | interrupts-extended = <&pmc AT91_PMC_MCKRDY>; | 840 | interrupts-extended = <&pmc AT91_PMC_MCKRDY>; |
| 587 | clocks = <&clk32k>, <&main>, <&plla>, <&utmi>; | 841 | clocks = <&clk32k>, <&main>, <&plla>, <&utmi>; |
| 588 | atmel,clk-output-range = <0 94000000>; | 842 | atmel,clk-output-range = <0 94000000>; |
| 589 | atmel,clk-divisors = <1 2 4 3>; | 843 | atmel,clk-divisors = <1 2 4 0>; |
| 590 | }; | 844 | }; |
| 591 | 845 | ||
| 592 | prog: progck { | 846 | prog: progck { |
| @@ -769,6 +1023,32 @@ | |||
| 769 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | 1023 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 770 | status = "disabled"; | 1024 | status = "disabled"; |
| 771 | }; | 1025 | }; |
| 1026 | |||
| 1027 | sckc@fffffd50 { | ||
| 1028 | compatible = "atmel,at91sam9x5-sckc"; | ||
| 1029 | reg = <0xfffffd50 0x4>; | ||
| 1030 | |||
| 1031 | slow_osc: slow_osc { | ||
| 1032 | compatible = "atmel,at91sam9x5-clk-slow-osc"; | ||
| 1033 | #clock-cells = <0>; | ||
| 1034 | atmel,startup-time-usec = <1200000>; | ||
| 1035 | clocks = <&slow_xtal>; | ||
| 1036 | }; | ||
| 1037 | |||
| 1038 | slow_rc_osc: slow_rc_osc { | ||
| 1039 | compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; | ||
| 1040 | #clock-cells = <0>; | ||
| 1041 | atmel,startup-time-usec = <75>; | ||
| 1042 | clock-frequency = <32768>; | ||
| 1043 | clock-accuracy = <50000000>; | ||
| 1044 | }; | ||
| 1045 | |||
| 1046 | clk32k: slck { | ||
| 1047 | compatible = "atmel,at91sam9x5-clk-slow"; | ||
| 1048 | #clock-cells = <0>; | ||
| 1049 | clocks = <&slow_rc_osc &slow_osc>; | ||
| 1050 | }; | ||
| 1051 | }; | ||
| 772 | }; | 1052 | }; |
| 773 | }; | 1053 | }; |
| 774 | 1054 | ||
diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts index cddb37825fad..d4a010e40fe3 100644 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ b/arch/arm/boot/dts/at91sam9rlek.dts | |||
| @@ -20,6 +20,15 @@ | |||
| 20 | reg = <0x20000000 0x4000000>; | 20 | reg = <0x20000000 0x4000000>; |
| 21 | }; | 21 | }; |
| 22 | 22 | ||
| 23 | |||
| 24 | slow_xtal { | ||
| 25 | clock-frequency = <32768>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | main_xtal { | ||
| 29 | clock-frequency = <12000000>; | ||
| 30 | }; | ||
| 31 | |||
| 23 | clocks { | 32 | clocks { |
| 24 | #address-cells = <1>; | 33 | #address-cells = <1>; |
| 25 | #size-cells = <1>; | 34 | #size-cells = <1>; |
| @@ -32,6 +41,37 @@ | |||
| 32 | }; | 41 | }; |
| 33 | 42 | ||
| 34 | ahb { | 43 | ahb { |
| 44 | fb0: fb@00500000 { | ||
| 45 | display = <&display0>; | ||
| 46 | status = "okay"; | ||
| 47 | |||
| 48 | display0: display { | ||
| 49 | bits-per-pixel = <16>; | ||
| 50 | atmel,lcdcon-backlight; | ||
| 51 | atmel,dmacon = <0x1>; | ||
| 52 | atmel,lcdcon2 = <0x80008002>; | ||
| 53 | atmel,guard-time = <1>; | ||
| 54 | atmel,lcd-wiring-mode = "RGB"; | ||
| 55 | |||
| 56 | display-timings { | ||
| 57 | native-mode = <&timing0>; | ||
| 58 | timing0: timing0 { | ||
| 59 | clock-frequency = <4965000>; | ||
| 60 | hactive = <240>; | ||
| 61 | vactive = <320>; | ||
| 62 | hback-porch = <1>; | ||
| 63 | hfront-porch = <33>; | ||
| 64 | vback-porch = <1>; | ||
| 65 | vfront-porch = <0>; | ||
| 66 | hsync-len = <5>; | ||
| 67 | vsync-len = <1>; | ||
| 68 | hsync-active = <1>; | ||
| 69 | vsync-active = <1>; | ||
| 70 | }; | ||
| 71 | }; | ||
| 72 | }; | ||
| 73 | }; | ||
| 74 | |||
| 35 | nand0: nand@40000000 { | 75 | nand0: nand@40000000 { |
| 36 | nand-bus-width = <8>; | 76 | nand-bus-width = <8>; |
| 37 | nand-ecc-mode = "soft"; | 77 | nand-ecc-mode = "soft"; |
| @@ -92,6 +132,43 @@ | |||
| 92 | status = "okay"; | 132 | status = "okay"; |
| 93 | }; | 133 | }; |
| 94 | 134 | ||
| 135 | adc0: adc@fffd0000 { | ||
| 136 | pinctrl-names = "default"; | ||
| 137 | pinctrl-0 = < | ||
| 138 | &pinctrl_adc0_ad0 | ||
| 139 | &pinctrl_adc0_ad1 | ||
| 140 | &pinctrl_adc0_ad2 | ||
| 141 | &pinctrl_adc0_ad3 | ||
| 142 | &pinctrl_adc0_ad4 | ||
| 143 | &pinctrl_adc0_ad5 | ||
| 144 | &pinctrl_adc0_adtrg>; | ||
| 145 | atmel,adc-ts-wires = <4>; | ||
| 146 | status = "okay"; | ||
| 147 | }; | ||
| 148 | |||
| 149 | usb0: gadget@fffd4000 { | ||
| 150 | atmel,vbus-gpio = <&pioA 8 GPIO_ACTIVE_HIGH>; | ||
| 151 | status = "okay"; | ||
| 152 | }; | ||
| 153 | |||
| 154 | spi0: spi@fffcc000 { | ||
| 155 | status = "okay"; | ||
| 156 | cs-gpios = <&pioA 28 0>, <0>, <0>, <0>; | ||
| 157 | mtd_dataflash@0 { | ||
| 158 | compatible = "atmel,at45", "atmel,dataflash"; | ||
| 159 | spi-max-frequency = <15000000>; | ||
| 160 | reg = <0>; | ||
| 161 | }; | ||
| 162 | }; | ||
| 163 | |||
| 164 | pwm0: pwm@fffc8000 { | ||
| 165 | status = "okay"; | ||
| 166 | |||
| 167 | pinctrl-names = "default"; | ||
| 168 | pinctrl-0 = <&pinctrl_pwm0_pwm1_2>, | ||
| 169 | <&pinctrl_pwm0_pwm2_2>; | ||
| 170 | }; | ||
| 171 | |||
| 95 | dbgu: serial@fffff200 { | 172 | dbgu: serial@fffff200 { |
| 96 | status = "okay"; | 173 | status = "okay"; |
| 97 | }; | 174 | }; |
| @@ -117,18 +194,24 @@ | |||
| 117 | }; | 194 | }; |
| 118 | }; | 195 | }; |
| 119 | 196 | ||
| 120 | leds { | 197 | pwmleds { |
| 121 | compatible = "gpio-leds"; | 198 | compatible = "pwm-leds"; |
| 122 | 199 | ||
| 123 | ds1 { | 200 | ds1 { |
| 124 | label = "ds1"; | 201 | label = "ds1"; |
| 125 | gpios = <&pioD 15 GPIO_ACTIVE_LOW>; | 202 | pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; |
| 203 | max-brightness = <255>; | ||
| 126 | }; | 204 | }; |
| 127 | 205 | ||
| 128 | ds2 { | 206 | ds2 { |
| 129 | label = "ds2"; | 207 | label = "ds2"; |
| 130 | gpios = <&pioD 16 GPIO_ACTIVE_LOW>; | 208 | pwms = <&pwm0 2 5000 PWM_POLARITY_INVERTED>; |
| 209 | max-brightness = <255>; | ||
| 131 | }; | 210 | }; |
| 211 | }; | ||
| 212 | |||
| 213 | leds { | ||
| 214 | compatible = "gpio-leds"; | ||
| 132 | 215 | ||
| 133 | ds3 { | 216 | ds3 { |
| 134 | label = "ds3"; | 217 | label = "ds3"; |
| @@ -154,4 +237,12 @@ | |||
| 154 | gpio-key,wakeup; | 237 | gpio-key,wakeup; |
| 155 | }; | 238 | }; |
| 156 | }; | 239 | }; |
| 240 | |||
| 241 | i2c@0 { | ||
| 242 | status = "okay"; | ||
| 243 | }; | ||
| 244 | |||
| 245 | i2c@1 { | ||
| 246 | status = "okay"; | ||
| 247 | }; | ||
| 157 | }; | 248 | }; |
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index fc13c9240da8..1a57298636a5 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <dt-bindings/pinctrl/at91.h> | 14 | #include <dt-bindings/pinctrl/at91.h> |
| 15 | #include <dt-bindings/interrupt-controller/irq.h> | 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 16 | #include <dt-bindings/gpio/gpio.h> | 16 | #include <dt-bindings/gpio/gpio.h> |
| 17 | #include <dt-bindings/clock/at91.h> | ||
| 17 | 18 | ||
| 18 | / { | 19 | / { |
| 19 | model = "Atmel AT91SAM9x5 family SoC"; | 20 | model = "Atmel AT91SAM9x5 family SoC"; |
| @@ -51,6 +52,24 @@ | |||
| 51 | reg = <0x20000000 0x10000000>; | 52 | reg = <0x20000000 0x10000000>; |
| 52 | }; | 53 | }; |
| 53 | 54 | ||
| 55 | slow_xtal: slow_xtal { | ||
| 56 | compatible = "fixed-clock"; | ||
| 57 | #clock-cells = <0>; | ||
| 58 | clock-frequency = <0>; | ||
| 59 | }; | ||
| 60 | |||
| 61 | main_xtal: main_xtal { | ||
| 62 | compatible = "fixed-clock"; | ||
| 63 | #clock-cells = <0>; | ||
| 64 | clock-frequency = <0>; | ||
| 65 | }; | ||
| 66 | |||
| 67 | adc_op_clk: adc_op_clk{ | ||
| 68 | compatible = "fixed-clock"; | ||
| 69 | #clock-cells = <0>; | ||
| 70 | clock-frequency = <5000000>; | ||
| 71 | }; | ||
| 72 | |||
| 54 | ahb { | 73 | ahb { |
| 55 | compatible = "simple-bus"; | 74 | compatible = "simple-bus"; |
| 56 | #address-cells = <1>; | 75 | #address-cells = <1>; |
| @@ -77,8 +96,272 @@ | |||
| 77 | }; | 96 | }; |
| 78 | 97 | ||
| 79 | pmc: pmc@fffffc00 { | 98 | pmc: pmc@fffffc00 { |
| 80 | compatible = "atmel,at91rm9200-pmc"; | 99 | compatible = "atmel,at91sam9x5-pmc"; |
| 81 | reg = <0xfffffc00 0x100>; | 100 | reg = <0xfffffc00 0x100>; |
| 101 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | ||
| 102 | interrupt-controller; | ||
| 103 | #address-cells = <1>; | ||
| 104 | #size-cells = <0>; | ||
| 105 | #interrupt-cells = <1>; | ||
| 106 | |||
| 107 | main_rc_osc: main_rc_osc { | ||
| 108 | compatible = "atmel,at91sam9x5-clk-main-rc-osc"; | ||
| 109 | #clock-cells = <0>; | ||
| 110 | interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; | ||
| 111 | clock-frequency = <12000000>; | ||
| 112 | clock-accuracy = <50000000>; | ||
| 113 | }; | ||
| 114 | |||
| 115 | main_osc: main_osc { | ||
| 116 | compatible = "atmel,at91rm9200-clk-main-osc"; | ||
| 117 | #clock-cells = <0>; | ||
| 118 | interrupts-extended = <&pmc AT91_PMC_MOSCS>; | ||
| 119 | clocks = <&main_xtal>; | ||
| 120 | }; | ||
| 121 | |||
| 122 | main: mainck { | ||
| 123 | compatible = "atmel,at91sam9x5-clk-main"; | ||
| 124 | #clock-cells = <0>; | ||
| 125 | interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; | ||
| 126 | clocks = <&main_rc_osc>, <&main_osc>; | ||
| 127 | }; | ||
| 128 | |||
| 129 | plla: pllack { | ||
| 130 | compatible = "atmel,at91rm9200-clk-pll"; | ||
| 131 | #clock-cells = <0>; | ||
| 132 | interrupts-extended = <&pmc AT91_PMC_LOCKA>; | ||
| 133 | clocks = <&main>; | ||
| 134 | reg = <0>; | ||
| 135 | atmel,clk-input-range = <2000000 32000000>; | ||
| 136 | #atmel,pll-clk-output-range-cells = <4>; | ||
| 137 | atmel,pll-clk-output-ranges = <745000000 800000000 0 0 | ||
| 138 | 695000000 750000000 1 0 | ||
| 139 | 645000000 700000000 2 0 | ||
| 140 | 595000000 650000000 3 0 | ||
| 141 | 545000000 600000000 0 1 | ||
| 142 | 495000000 555000000 1 1 | ||
| 143 | 445000000 500000000 1 2 | ||
| 144 | 400000000 450000000 1 3>; | ||
| 145 | }; | ||
| 146 | |||
| 147 | plladiv: plladivck { | ||
| 148 | compatible = "atmel,at91sam9x5-clk-plldiv"; | ||
| 149 | #clock-cells = <0>; | ||
| 150 | clocks = <&plla>; | ||
| 151 | }; | ||
| 152 | |||
| 153 | utmi: utmick { | ||
| 154 | compatible = "atmel,at91sam9x5-clk-utmi"; | ||
| 155 | #clock-cells = <0>; | ||
| 156 | interrupts-extended = <&pmc AT91_PMC_LOCKU>; | ||
| 157 | clocks = <&main>; | ||
| 158 | }; | ||
| 159 | |||
| 160 | mck: masterck { | ||
| 161 | compatible = "atmel,at91sam9x5-clk-master"; | ||
| 162 | #clock-cells = <0>; | ||
| 163 | interrupts-extended = <&pmc AT91_PMC_MCKRDY>; | ||
| 164 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; | ||
| 165 | atmel,clk-output-range = <0 133333333>; | ||
| 166 | atmel,clk-divisors = <1 2 4 3>; | ||
| 167 | atmel,master-clk-have-div3-pres; | ||
| 168 | }; | ||
| 169 | |||
| 170 | usb: usbck { | ||
| 171 | compatible = "atmel,at91sam9x5-clk-usb"; | ||
| 172 | #clock-cells = <0>; | ||
| 173 | clocks = <&plladiv>, <&utmi>; | ||
| 174 | }; | ||
| 175 | |||
| 176 | prog: progck { | ||
| 177 | compatible = "atmel,at91sam9x5-clk-programmable"; | ||
| 178 | #address-cells = <1>; | ||
| 179 | #size-cells = <0>; | ||
| 180 | interrupt-parent = <&pmc>; | ||
| 181 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; | ||
| 182 | |||
| 183 | prog0: prog0 { | ||
| 184 | #clock-cells = <0>; | ||
| 185 | reg = <0>; | ||
| 186 | interrupts = <AT91_PMC_PCKRDY(0)>; | ||
| 187 | }; | ||
| 188 | |||
| 189 | prog1: prog1 { | ||
| 190 | #clock-cells = <0>; | ||
| 191 | reg = <1>; | ||
| 192 | interrupts = <AT91_PMC_PCKRDY(1)>; | ||
| 193 | }; | ||
| 194 | }; | ||
| 195 | |||
| 196 | smd: smdclk { | ||
| 197 | compatible = "atmel,at91sam9x5-clk-smd"; | ||
| 198 | #clock-cells = <0>; | ||
| 199 | clocks = <&plladiv>, <&utmi>; | ||
| 200 | }; | ||
| 201 | |||
| 202 | systemck { | ||
| 203 | compatible = "atmel,at91rm9200-clk-system"; | ||
| 204 | #address-cells = <1>; | ||
| 205 | #size-cells = <0>; | ||
| 206 | |||
| 207 | ddrck: ddrck { | ||
| 208 | #clock-cells = <0>; | ||
| 209 | reg = <2>; | ||
| 210 | clocks = <&mck>; | ||
| 211 | }; | ||
| 212 | |||
| 213 | smdck: smdck { | ||
| 214 | #clock-cells = <0>; | ||
| 215 | reg = <4>; | ||
| 216 | clocks = <&smd>; | ||
| 217 | }; | ||
| 218 | |||
| 219 | uhpck: uhpck { | ||
| 220 | #clock-cells = <0>; | ||
| 221 | reg = <6>; | ||
| 222 | clocks = <&usb>; | ||
| 223 | }; | ||
| 224 | |||
| 225 | udpck: udpck { | ||
| 226 | #clock-cells = <0>; | ||
| 227 | reg = <7>; | ||
| 228 | clocks = <&usb>; | ||
| 229 | }; | ||
| 230 | |||
| 231 | pck0: pck0 { | ||
| 232 | #clock-cells = <0>; | ||
| 233 | reg = <8>; | ||
| 234 | clocks = <&prog0>; | ||
| 235 | }; | ||
| 236 | |||
| 237 | pck1: pck1 { | ||
| 238 | #clock-cells = <0>; | ||
| 239 | reg = <9>; | ||
| 240 | clocks = <&prog1>; | ||
| 241 | }; | ||
| 242 | }; | ||
| 243 | |||
| 244 | periphck { | ||
| 245 | compatible = "atmel,at91sam9x5-clk-peripheral"; | ||
| 246 | #address-cells = <1>; | ||
| 247 | #size-cells = <0>; | ||
| 248 | clocks = <&mck>; | ||
| 249 | |||
| 250 | pioAB_clk: pioAB_clk { | ||
| 251 | #clock-cells = <0>; | ||
| 252 | reg = <2>; | ||
| 253 | }; | ||
| 254 | |||
| 255 | pioCD_clk: pioCD_clk { | ||
| 256 | #clock-cells = <0>; | ||
| 257 | reg = <3>; | ||
| 258 | }; | ||
| 259 | |||
| 260 | smd_clk: smd_clk { | ||
| 261 | #clock-cells = <0>; | ||
| 262 | reg = <4>; | ||
| 263 | }; | ||
| 264 | |||
| 265 | usart0_clk: usart0_clk { | ||
| 266 | #clock-cells = <0>; | ||
| 267 | reg = <5>; | ||
| 268 | }; | ||
| 269 | |||
| 270 | usart1_clk: usart1_clk { | ||
| 271 | #clock-cells = <0>; | ||
| 272 | reg = <6>; | ||
| 273 | }; | ||
| 274 | |||
| 275 | usart2_clk: usart2_clk { | ||
| 276 | #clock-cells = <0>; | ||
| 277 | reg = <7>; | ||
| 278 | }; | ||
| 279 | |||
| 280 | twi0_clk: twi0_clk { | ||
| 281 | reg = <9>; | ||
| 282 | #clock-cells = <0>; | ||
| 283 | }; | ||
| 284 | |||
| 285 | twi1_clk: twi1_clk { | ||
| 286 | #clock-cells = <0>; | ||
| 287 | reg = <10>; | ||
| 288 | }; | ||
| 289 | |||
| 290 | twi2_clk: twi2_clk { | ||
| 291 | #clock-cells = <0>; | ||
| 292 | reg = <11>; | ||
| 293 | }; | ||
| 294 | |||
| 295 | mci0_clk: mci0_clk { | ||
| 296 | #clock-cells = <0>; | ||
| 297 | reg = <12>; | ||
| 298 | }; | ||
| 299 | |||
| 300 | spi0_clk: spi0_clk { | ||
| 301 | #clock-cells = <0>; | ||
| 302 | reg = <13>; | ||
| 303 | }; | ||
| 304 | |||
| 305 | spi1_clk: spi1_clk { | ||
| 306 | #clock-cells = <0>; | ||
| 307 | reg = <14>; | ||
| 308 | }; | ||
| 309 | |||
| 310 | uart0_clk: uart0_clk { | ||
| 311 | #clock-cells = <0>; | ||
| 312 | reg = <15>; | ||
| 313 | }; | ||
| 314 | |||
| 315 | uart1_clk: uart1_clk { | ||
| 316 | #clock-cells = <0>; | ||
| 317 | reg = <16>; | ||
| 318 | }; | ||
| 319 | |||
| 320 | tcb0_clk: tcb0_clk { | ||
| 321 | #clock-cells = <0>; | ||
| 322 | reg = <17>; | ||
| 323 | }; | ||
| 324 | |||
| 325 | pwm_clk: pwm_clk { | ||
| 326 | #clock-cells = <0>; | ||
| 327 | reg = <18>; | ||
| 328 | }; | ||
| 329 | |||
| 330 | adc_clk: adc_clk { | ||
| 331 | #clock-cells = <0>; | ||
| 332 | reg = <19>; | ||
| 333 | }; | ||
| 334 | |||
| 335 | dma0_clk: dma0_clk { | ||
| 336 | #clock-cells = <0>; | ||
| 337 | reg = <20>; | ||
| 338 | }; | ||
| 339 | |||
| 340 | dma1_clk: dma1_clk { | ||
| 341 | #clock-cells = <0>; | ||
| 342 | reg = <21>; | ||
| 343 | }; | ||
| 344 | |||
| 345 | uhphs_clk: uhphs_clk { | ||
| 346 | #clock-cells = <0>; | ||
| 347 | reg = <22>; | ||
| 348 | }; | ||
| 349 | |||
| 350 | udphs_clk: udphs_clk { | ||
| 351 | #clock-cells = <0>; | ||
| 352 | reg = <23>; | ||
| 353 | }; | ||
| 354 | |||
| 355 | mci1_clk: mci1_clk { | ||
| 356 | #clock-cells = <0>; | ||
| 357 | reg = <26>; | ||
| 358 | }; | ||
| 359 | |||
| 360 | ssc0_clk: ssc0_clk { | ||
| 361 | #clock-cells = <0>; | ||
| 362 | reg = <28>; | ||
| 363 | }; | ||
| 364 | }; | ||
| 82 | }; | 365 | }; |
| 83 | 366 | ||
| 84 | rstc@fffffe00 { | 367 | rstc@fffffe00 { |
| @@ -95,18 +378,47 @@ | |||
| 95 | compatible = "atmel,at91sam9260-pit"; | 378 | compatible = "atmel,at91sam9260-pit"; |
| 96 | reg = <0xfffffe30 0xf>; | 379 | reg = <0xfffffe30 0xf>; |
| 97 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | 380 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 381 | clocks = <&mck>; | ||
| 382 | }; | ||
| 383 | |||
| 384 | sckc@fffffe50 { | ||
| 385 | compatible = "atmel,at91sam9x5-sckc"; | ||
| 386 | reg = <0xfffffe50 0x4>; | ||
| 387 | |||
| 388 | slow_osc: slow_osc { | ||
| 389 | compatible = "atmel,at91sam9x5-clk-slow-osc"; | ||
| 390 | #clock-cells = <0>; | ||
| 391 | clocks = <&slow_xtal>; | ||
| 392 | }; | ||
| 393 | |||
| 394 | slow_rc_osc: slow_rc_osc { | ||
| 395 | compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; | ||
| 396 | #clock-cells = <0>; | ||
| 397 | clock-frequency = <32768>; | ||
| 398 | clock-accuracy = <50000000>; | ||
| 399 | }; | ||
| 400 | |||
| 401 | clk32k: slck { | ||
| 402 | compatible = "atmel,at91sam9x5-clk-slow"; | ||
| 403 | #clock-cells = <0>; | ||
| 404 | clocks = <&slow_rc_osc>, <&slow_osc>; | ||
| 405 | }; | ||
| 98 | }; | 406 | }; |
| 99 | 407 | ||
| 100 | tcb0: timer@f8008000 { | 408 | tcb0: timer@f8008000 { |
| 101 | compatible = "atmel,at91sam9x5-tcb"; | 409 | compatible = "atmel,at91sam9x5-tcb"; |
| 102 | reg = <0xf8008000 0x100>; | 410 | reg = <0xf8008000 0x100>; |
| 103 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; | 411 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; |
| 412 | clocks = <&tcb0_clk>; | ||
| 413 | clock-names = "t0_clk"; | ||
| 104 | }; | 414 | }; |
| 105 | 415 | ||
| 106 | tcb1: timer@f800c000 { | 416 | tcb1: timer@f800c000 { |
| 107 | compatible = "atmel,at91sam9x5-tcb"; | 417 | compatible = "atmel,at91sam9x5-tcb"; |
| 108 | reg = <0xf800c000 0x100>; | 418 | reg = <0xf800c000 0x100>; |
| 109 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; | 419 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; |
| 420 | clocks = <&tcb0_clk>; | ||
| 421 | clock-names = "t0_clk"; | ||
| 110 | }; | 422 | }; |
| 111 | 423 | ||
| 112 | dma0: dma-controller@ffffec00 { | 424 | dma0: dma-controller@ffffec00 { |
| @@ -114,6 +426,8 @@ | |||
| 114 | reg = <0xffffec00 0x200>; | 426 | reg = <0xffffec00 0x200>; |
| 115 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; | 427 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; |
| 116 | #dma-cells = <2>; | 428 | #dma-cells = <2>; |
| 429 | clocks = <&dma0_clk>; | ||
| 430 | clock-names = "dma_clk"; | ||
| 117 | }; | 431 | }; |
| 118 | 432 | ||
| 119 | dma1: dma-controller@ffffee00 { | 433 | dma1: dma-controller@ffffee00 { |
| @@ -121,6 +435,8 @@ | |||
| 121 | reg = <0xffffee00 0x200>; | 435 | reg = <0xffffee00 0x200>; |
| 122 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; | 436 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; |
| 123 | #dma-cells = <2>; | 437 | #dma-cells = <2>; |
| 438 | clocks = <&dma1_clk>; | ||
| 439 | clock-names = "dma_clk"; | ||
| 124 | }; | 440 | }; |
| 125 | 441 | ||
| 126 | pinctrl@fffff400 { | 442 | pinctrl@fffff400 { |
| @@ -453,6 +769,7 @@ | |||
| 453 | gpio-controller; | 769 | gpio-controller; |
| 454 | interrupt-controller; | 770 | interrupt-controller; |
| 455 | #interrupt-cells = <2>; | 771 | #interrupt-cells = <2>; |
| 772 | clocks = <&pioAB_clk>; | ||
| 456 | }; | 773 | }; |
| 457 | 774 | ||
| 458 | pioB: gpio@fffff600 { | 775 | pioB: gpio@fffff600 { |
| @@ -464,6 +781,7 @@ | |||
| 464 | #gpio-lines = <19>; | 781 | #gpio-lines = <19>; |
| 465 | interrupt-controller; | 782 | interrupt-controller; |
| 466 | #interrupt-cells = <2>; | 783 | #interrupt-cells = <2>; |
| 784 | clocks = <&pioAB_clk>; | ||
| 467 | }; | 785 | }; |
| 468 | 786 | ||
| 469 | pioC: gpio@fffff800 { | 787 | pioC: gpio@fffff800 { |
| @@ -474,6 +792,7 @@ | |||
| 474 | gpio-controller; | 792 | gpio-controller; |
| 475 | interrupt-controller; | 793 | interrupt-controller; |
| 476 | #interrupt-cells = <2>; | 794 | #interrupt-cells = <2>; |
| 795 | clocks = <&pioCD_clk>; | ||
| 477 | }; | 796 | }; |
| 478 | 797 | ||
| 479 | pioD: gpio@fffffa00 { | 798 | pioD: gpio@fffffa00 { |
| @@ -485,6 +804,7 @@ | |||
| 485 | #gpio-lines = <22>; | 804 | #gpio-lines = <22>; |
| 486 | interrupt-controller; | 805 | interrupt-controller; |
| 487 | #interrupt-cells = <2>; | 806 | #interrupt-cells = <2>; |
| 807 | clocks = <&pioCD_clk>; | ||
| 488 | }; | 808 | }; |
| 489 | }; | 809 | }; |
| 490 | 810 | ||
| @@ -497,6 +817,8 @@ | |||
| 497 | dma-names = "tx", "rx"; | 817 | dma-names = "tx", "rx"; |
| 498 | pinctrl-names = "default"; | 818 | pinctrl-names = "default"; |
| 499 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | 819 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 820 | clocks = <&ssc0_clk>; | ||
| 821 | clock-names = "pclk"; | ||
| 500 | status = "disabled"; | 822 | status = "disabled"; |
| 501 | }; | 823 | }; |
| 502 | 824 | ||
| @@ -507,6 +829,8 @@ | |||
| 507 | dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; | 829 | dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; |
| 508 | dma-names = "rxtx"; | 830 | dma-names = "rxtx"; |
| 509 | pinctrl-names = "default"; | 831 | pinctrl-names = "default"; |
| 832 | clocks = <&mci0_clk>; | ||
| 833 | clock-names = "mci_clk"; | ||
| 510 | #address-cells = <1>; | 834 | #address-cells = <1>; |
| 511 | #size-cells = <0>; | 835 | #size-cells = <0>; |
| 512 | status = "disabled"; | 836 | status = "disabled"; |
| @@ -519,6 +843,8 @@ | |||
| 519 | dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; | 843 | dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; |
| 520 | dma-names = "rxtx"; | 844 | dma-names = "rxtx"; |
| 521 | pinctrl-names = "default"; | 845 | pinctrl-names = "default"; |
| 846 | clocks = <&mci1_clk>; | ||
| 847 | clock-names = "mci_clk"; | ||
| 522 | #address-cells = <1>; | 848 | #address-cells = <1>; |
| 523 | #size-cells = <0>; | 849 | #size-cells = <0>; |
| 524 | status = "disabled"; | 850 | status = "disabled"; |
| @@ -530,6 +856,8 @@ | |||
| 530 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | 856 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 531 | pinctrl-names = "default"; | 857 | pinctrl-names = "default"; |
| 532 | pinctrl-0 = <&pinctrl_dbgu>; | 858 | pinctrl-0 = <&pinctrl_dbgu>; |
| 859 | clocks = <&mck>; | ||
| 860 | clock-names = "usart"; | ||
| 533 | status = "disabled"; | 861 | status = "disabled"; |
| 534 | }; | 862 | }; |
| 535 | 863 | ||
| @@ -539,6 +867,8 @@ | |||
| 539 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; | 867 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; |
| 540 | pinctrl-names = "default"; | 868 | pinctrl-names = "default"; |
| 541 | pinctrl-0 = <&pinctrl_usart0>; | 869 | pinctrl-0 = <&pinctrl_usart0>; |
| 870 | clocks = <&usart0_clk>; | ||
| 871 | clock-names = "usart"; | ||
| 542 | status = "disabled"; | 872 | status = "disabled"; |
| 543 | }; | 873 | }; |
| 544 | 874 | ||
| @@ -548,6 +878,8 @@ | |||
| 548 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; | 878 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; |
| 549 | pinctrl-names = "default"; | 879 | pinctrl-names = "default"; |
| 550 | pinctrl-0 = <&pinctrl_usart1>; | 880 | pinctrl-0 = <&pinctrl_usart1>; |
| 881 | clocks = <&usart1_clk>; | ||
| 882 | clock-names = "usart"; | ||
| 551 | status = "disabled"; | 883 | status = "disabled"; |
| 552 | }; | 884 | }; |
| 553 | 885 | ||
| @@ -557,6 +889,8 @@ | |||
| 557 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; | 889 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
| 558 | pinctrl-names = "default"; | 890 | pinctrl-names = "default"; |
| 559 | pinctrl-0 = <&pinctrl_usart2>; | 891 | pinctrl-0 = <&pinctrl_usart2>; |
| 892 | clocks = <&usart2_clk>; | ||
| 893 | clock-names = "usart"; | ||
| 560 | status = "disabled"; | 894 | status = "disabled"; |
| 561 | }; | 895 | }; |
| 562 | 896 | ||
| @@ -571,6 +905,7 @@ | |||
| 571 | #size-cells = <0>; | 905 | #size-cells = <0>; |
| 572 | pinctrl-names = "default"; | 906 | pinctrl-names = "default"; |
| 573 | pinctrl-0 = <&pinctrl_i2c0>; | 907 | pinctrl-0 = <&pinctrl_i2c0>; |
| 908 | clocks = <&twi0_clk>; | ||
| 574 | status = "disabled"; | 909 | status = "disabled"; |
| 575 | }; | 910 | }; |
| 576 | 911 | ||
| @@ -585,6 +920,7 @@ | |||
| 585 | #size-cells = <0>; | 920 | #size-cells = <0>; |
| 586 | pinctrl-names = "default"; | 921 | pinctrl-names = "default"; |
| 587 | pinctrl-0 = <&pinctrl_i2c1>; | 922 | pinctrl-0 = <&pinctrl_i2c1>; |
| 923 | clocks = <&twi1_clk>; | ||
| 588 | status = "disabled"; | 924 | status = "disabled"; |
| 589 | }; | 925 | }; |
| 590 | 926 | ||
| @@ -599,6 +935,7 @@ | |||
| 599 | #size-cells = <0>; | 935 | #size-cells = <0>; |
| 600 | pinctrl-names = "default"; | 936 | pinctrl-names = "default"; |
| 601 | pinctrl-0 = <&pinctrl_i2c2>; | 937 | pinctrl-0 = <&pinctrl_i2c2>; |
| 938 | clocks = <&twi2_clk>; | ||
| 602 | status = "disabled"; | 939 | status = "disabled"; |
| 603 | }; | 940 | }; |
| 604 | 941 | ||
| @@ -608,6 +945,8 @@ | |||
| 608 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; | 945 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; |
| 609 | pinctrl-names = "default"; | 946 | pinctrl-names = "default"; |
| 610 | pinctrl-0 = <&pinctrl_uart0>; | 947 | pinctrl-0 = <&pinctrl_uart0>; |
| 948 | clocks = <&uart0_clk>; | ||
| 949 | clock-names = "usart"; | ||
| 611 | status = "disabled"; | 950 | status = "disabled"; |
| 612 | }; | 951 | }; |
| 613 | 952 | ||
| @@ -617,6 +956,8 @@ | |||
| 617 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; | 956 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; |
| 618 | pinctrl-names = "default"; | 957 | pinctrl-names = "default"; |
| 619 | pinctrl-0 = <&pinctrl_uart1>; | 958 | pinctrl-0 = <&pinctrl_uart1>; |
| 959 | clocks = <&uart1_clk>; | ||
| 960 | clock-names = "usart"; | ||
| 620 | status = "disabled"; | 961 | status = "disabled"; |
| 621 | }; | 962 | }; |
| 622 | 963 | ||
| @@ -626,6 +967,9 @@ | |||
| 626 | compatible = "atmel,at91sam9260-adc"; | 967 | compatible = "atmel,at91sam9260-adc"; |
| 627 | reg = <0xf804c000 0x100>; | 968 | reg = <0xf804c000 0x100>; |
| 628 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; | 969 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; |
| 970 | clocks = <&adc_clk>, | ||
| 971 | <&adc_op_clk>; | ||
| 972 | clock-names = "adc_clk", "adc_op_clk"; | ||
| 629 | atmel,adc-use-external-triggers; | 973 | atmel,adc-use-external-triggers; |
| 630 | atmel,adc-channels-used = <0xffff>; | 974 | atmel,adc-channels-used = <0xffff>; |
| 631 | atmel,adc-vref = <3300>; | 975 | atmel,adc-vref = <3300>; |
| @@ -673,6 +1017,8 @@ | |||
| 673 | dma-names = "tx", "rx"; | 1017 | dma-names = "tx", "rx"; |
| 674 | pinctrl-names = "default"; | 1018 | pinctrl-names = "default"; |
| 675 | pinctrl-0 = <&pinctrl_spi0>; | 1019 | pinctrl-0 = <&pinctrl_spi0>; |
| 1020 | clocks = <&spi0_clk>; | ||
| 1021 | clock-names = "spi_clk"; | ||
| 676 | status = "disabled"; | 1022 | status = "disabled"; |
| 677 | }; | 1023 | }; |
| 678 | 1024 | ||
| @@ -687,6 +1033,8 @@ | |||
| 687 | dma-names = "tx", "rx"; | 1033 | dma-names = "tx", "rx"; |
| 688 | pinctrl-names = "default"; | 1034 | pinctrl-names = "default"; |
| 689 | pinctrl-0 = <&pinctrl_spi1>; | 1035 | pinctrl-0 = <&pinctrl_spi1>; |
| 1036 | clocks = <&spi1_clk>; | ||
| 1037 | clock-names = "spi_clk"; | ||
| 690 | status = "disabled"; | 1038 | status = "disabled"; |
| 691 | }; | 1039 | }; |
| 692 | 1040 | ||
| @@ -805,6 +1153,9 @@ | |||
| 805 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 1153 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 806 | reg = <0x00600000 0x100000>; | 1154 | reg = <0x00600000 0x100000>; |
| 807 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; | 1155 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
| 1156 | clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>, | ||
| 1157 | <&uhpck>; | ||
| 1158 | clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; | ||
| 808 | status = "disabled"; | 1159 | status = "disabled"; |
| 809 | }; | 1160 | }; |
| 810 | 1161 | ||
| @@ -812,6 +1163,8 @@ | |||
| 812 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | 1163 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
| 813 | reg = <0x00700000 0x100000>; | 1164 | reg = <0x00700000 0x100000>; |
| 814 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; | 1165 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
| 1166 | clocks = <&usb>, <&uhphs_clk>, <&uhpck>; | ||
| 1167 | clock-names = "usb_clk", "ehci_clk", "uhpck"; | ||
| 815 | status = "disabled"; | 1168 | status = "disabled"; |
| 816 | }; | 1169 | }; |
| 817 | }; | 1170 | }; |
diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi new file mode 100644 index 000000000000..f44ab7702a12 --- /dev/null +++ b/arch/arm/boot/dts/at91sam9x5_can.dtsi | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /* | ||
| 2 | * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 | ||
| 3 | * Ethernet interface. | ||
| 4 | * | ||
| 5 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <dt-bindings/pinctrl/at91.h> | ||
| 11 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 12 | |||
| 13 | / { | ||
| 14 | ahb { | ||
| 15 | apb { | ||
| 16 | pmc: pmc@fffffc00 { | ||
| 17 | periphck { | ||
| 18 | can0_clk: can0_clk { | ||
| 19 | #clock-cells = <0>; | ||
| 20 | reg = <29>; | ||
| 21 | }; | ||
| 22 | |||
| 23 | can1_clk: can1_clk { | ||
| 24 | #clock-cells = <0>; | ||
| 25 | reg = <30>; | ||
| 26 | }; | ||
| 27 | }; | ||
| 28 | }; | ||
| 29 | }; | ||
| 30 | }; | ||
| 31 | }; | ||
diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/at91sam9x5_isi.dtsi new file mode 100644 index 000000000000..98bc877a68ef --- /dev/null +++ b/arch/arm/boot/dts/at91sam9x5_isi.dtsi | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an | ||
| 3 | * Image Sensor Interface. | ||
| 4 | * | ||
| 5 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <dt-bindings/pinctrl/at91.h> | ||
| 11 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 12 | |||
| 13 | / { | ||
| 14 | ahb { | ||
| 15 | apb { | ||
| 16 | pmc: pmc@fffffc00 { | ||
| 17 | periphck { | ||
| 18 | isi_clk: isi_clk { | ||
| 19 | #clock-cells = <0>; | ||
| 20 | reg = <25>; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | }; | ||
| 24 | }; | ||
| 25 | }; | ||
| 26 | }; | ||
diff --git a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi new file mode 100644 index 000000000000..485302e8233d --- /dev/null +++ b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an | ||
| 3 | * LCD controller. | ||
| 4 | * | ||
| 5 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <dt-bindings/pinctrl/at91.h> | ||
| 11 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 12 | |||
| 13 | / { | ||
| 14 | ahb { | ||
| 15 | apb { | ||
| 16 | pmc: pmc@fffffc00 { | ||
| 17 | periphck { | ||
| 18 | lcdc_clk: lcdc_clk { | ||
| 19 | #clock-cells = <0>; | ||
| 20 | reg = <25>; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | }; | ||
| 24 | }; | ||
| 25 | }; | ||
| 26 | }; | ||
diff --git a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi index 55731ffba764..57e89d1d0325 100644 --- a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi | |||
| @@ -43,12 +43,23 @@ | |||
| 43 | }; | 43 | }; |
| 44 | }; | 44 | }; |
| 45 | 45 | ||
| 46 | pmc: pmc@fffffc00 { | ||
| 47 | periphck { | ||
| 48 | macb0_clk: macb0_clk { | ||
| 49 | #clock-cells = <0>; | ||
| 50 | reg = <24>; | ||
| 51 | }; | ||
| 52 | }; | ||
| 53 | }; | ||
| 54 | |||
| 46 | macb0: ethernet@f802c000 { | 55 | macb0: ethernet@f802c000 { |
| 47 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 56 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 48 | reg = <0xf802c000 0x100>; | 57 | reg = <0xf802c000 0x100>; |
| 49 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; | 58 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; |
| 50 | pinctrl-names = "default"; | 59 | pinctrl-names = "default"; |
| 51 | pinctrl-0 = <&pinctrl_macb0_rmii>; | 60 | pinctrl-0 = <&pinctrl_macb0_rmii>; |
| 61 | clocks = <&macb0_clk>, <&macb0_clk>; | ||
| 62 | clock-names = "hclk", "pclk"; | ||
| 52 | status = "disabled"; | 63 | status = "disabled"; |
| 53 | }; | 64 | }; |
| 54 | }; | 65 | }; |
diff --git a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi index 77425a627a94..663676c02861 100644 --- a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi | |||
| @@ -31,12 +31,23 @@ | |||
| 31 | }; | 31 | }; |
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| 34 | pmc: pmc@fffffc00 { | ||
| 35 | periphck { | ||
| 36 | macb1_clk: macb1_clk { | ||
| 37 | #clock-cells = <0>; | ||
| 38 | reg = <27>; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | |||
| 34 | macb1: ethernet@f8030000 { | 43 | macb1: ethernet@f8030000 { |
| 35 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 44 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 36 | reg = <0xf8030000 0x100>; | 45 | reg = <0xf8030000 0x100>; |
| 37 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; | 46 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; |
| 38 | pinctrl-names = "default"; | 47 | pinctrl-names = "default"; |
| 39 | pinctrl-0 = <&pinctrl_macb1_rmii>; | 48 | pinctrl-0 = <&pinctrl_macb1_rmii>; |
| 49 | clocks = <&macb1_clk>, <&macb1_clk>; | ||
| 50 | clock-names = "hclk", "pclk"; | ||
| 40 | status = "disabled"; | 51 | status = "disabled"; |
| 41 | }; | 52 | }; |
| 42 | }; | 53 | }; |
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi index 6801106fa1f8..140217a54384 100644 --- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi | |||
| @@ -42,12 +42,23 @@ | |||
| 42 | }; | 42 | }; |
| 43 | }; | 43 | }; |
| 44 | 44 | ||
| 45 | pmc: pmc@fffffc00 { | ||
| 46 | periphck { | ||
| 47 | usart3_clk: usart3_clk { | ||
| 48 | #clock-cells = <0>; | ||
| 49 | reg = <8>; | ||
| 50 | }; | ||
| 51 | }; | ||
| 52 | }; | ||
| 53 | |||
| 45 | usart3: serial@f8028000 { | 54 | usart3: serial@f8028000 { |
| 46 | compatible = "atmel,at91sam9260-usart"; | 55 | compatible = "atmel,at91sam9260-usart"; |
| 47 | reg = <0xf8028000 0x200>; | 56 | reg = <0xf8028000 0x200>; |
| 48 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; | 57 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; |
| 49 | pinctrl-names = "default"; | 58 | pinctrl-names = "default"; |
| 50 | pinctrl-0 = <&pinctrl_usart3>; | 59 | pinctrl-0 = <&pinctrl_usart3>; |
| 60 | clocks = <&usart3_clk>; | ||
| 61 | clock-names = "usart"; | ||
| 51 | status = "disabled"; | 62 | status = "disabled"; |
| 52 | }; | 63 | }; |
| 53 | }; | 64 | }; |
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi index 4a5ee5cc115a..8413e21192eb 100644 --- a/arch/arm/boot/dts/at91sam9x5cm.dtsi +++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi | |||
| @@ -23,6 +23,14 @@ | |||
| 23 | }; | 23 | }; |
| 24 | }; | 24 | }; |
| 25 | 25 | ||
| 26 | slow_xtal { | ||
| 27 | clock-frequency = <32768>; | ||
| 28 | }; | ||
| 29 | |||
| 30 | main_xtal { | ||
| 31 | clock-frequency = <12000000>; | ||
| 32 | }; | ||
| 33 | |||
| 26 | ahb { | 34 | ahb { |
| 27 | apb { | 35 | apb { |
| 28 | pinctrl@fffff400 { | 36 | pinctrl@fffff400 { |
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index 9d72674049d6..bb22842a0826 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi | |||
| @@ -39,6 +39,11 @@ | |||
| 39 | }; | 39 | }; |
| 40 | }; | 40 | }; |
| 41 | 41 | ||
| 42 | arm-pmu { | ||
| 43 | compatible = "arm,cortex-a9-pmu"; | ||
| 44 | interrupts = <29>; | ||
| 45 | }; | ||
| 46 | |||
| 42 | axi { | 47 | axi { |
| 43 | compatible = "simple-bus"; | 48 | compatible = "simple-bus"; |
| 44 | #address-cells = <1>; | 49 | #address-cells = <1>; |
| @@ -167,6 +172,7 @@ | |||
| 167 | compatible = "sirf,prima2-dspif"; | 172 | compatible = "sirf,prima2-dspif"; |
| 168 | reg = <0xa8000000 0x10000>; | 173 | reg = <0xa8000000 0x10000>; |
| 169 | interrupts = <9>; | 174 | interrupts = <9>; |
| 175 | resets = <&rstc 1>; | ||
| 170 | }; | 176 | }; |
| 171 | 177 | ||
| 172 | gps@a8010000 { | 178 | gps@a8010000 { |
| @@ -174,6 +180,7 @@ | |||
| 174 | reg = <0xa8010000 0x10000>; | 180 | reg = <0xa8010000 0x10000>; |
| 175 | interrupts = <7>; | 181 | interrupts = <7>; |
| 176 | clocks = <&clks 9>; | 182 | clocks = <&clks 9>; |
| 183 | resets = <&rstc 2>; | ||
| 177 | }; | 184 | }; |
| 178 | 185 | ||
| 179 | dsp@a9000000 { | 186 | dsp@a9000000 { |
| @@ -181,6 +188,7 @@ | |||
| 181 | reg = <0xa9000000 0x1000000>; | 188 | reg = <0xa9000000 0x1000000>; |
| 182 | interrupts = <8>; | 189 | interrupts = <8>; |
| 183 | clocks = <&clks 8>; | 190 | clocks = <&clks 8>; |
| 191 | resets = <&rstc 0>; | ||
| 184 | }; | 192 | }; |
| 185 | }; | 193 | }; |
| 186 | 194 | ||
| @@ -195,6 +203,7 @@ | |||
| 195 | compatible = "sirf,prima2-tick"; | 203 | compatible = "sirf,prima2-tick"; |
| 196 | reg = <0xb0020000 0x1000>; | 204 | reg = <0xb0020000 0x1000>; |
| 197 | interrupts = <0>; | 205 | interrupts = <0>; |
| 206 | clocks = <&clks 11>; | ||
| 198 | }; | 207 | }; |
| 199 | 208 | ||
| 200 | nand@b0030000 { | 209 | nand@b0030000 { |
| @@ -297,9 +306,9 @@ | |||
| 297 | reg = <0xb00d0000 0x10000>; | 306 | reg = <0xb00d0000 0x10000>; |
| 298 | interrupts = <15>; | 307 | interrupts = <15>; |
| 299 | sirf,spi-num-chipselects = <1>; | 308 | sirf,spi-num-chipselects = <1>; |
| 300 | cs-gpios = <&gpio 0 0>; | 309 | dmas = <&dmac1 9>, |
| 301 | sirf,spi-dma-rx-channel = <25>; | 310 | <&dmac1 4>; |
| 302 | sirf,spi-dma-tx-channel = <20>; | 311 | dma-names = "rx", "tx"; |
| 303 | #address-cells = <1>; | 312 | #address-cells = <1>; |
| 304 | #size-cells = <0>; | 313 | #size-cells = <0>; |
| 305 | clocks = <&clks 19>; | 314 | clocks = <&clks 19>; |
| @@ -312,8 +321,9 @@ | |||
| 312 | reg = <0xb0170000 0x10000>; | 321 | reg = <0xb0170000 0x10000>; |
| 313 | interrupts = <16>; | 322 | interrupts = <16>; |
| 314 | sirf,spi-num-chipselects = <1>; | 323 | sirf,spi-num-chipselects = <1>; |
| 315 | sirf,spi-dma-rx-channel = <12>; | 324 | dmas = <&dmac0 12>, |
| 316 | sirf,spi-dma-tx-channel = <13>; | 325 | <&dmac0 13>; |
| 326 | dma-names = "rx", "tx"; | ||
| 317 | #address-cells = <1>; | 327 | #address-cells = <1>; |
| 318 | #size-cells = <0>; | 328 | #size-cells = <0>; |
| 319 | clocks = <&clks 20>; | 329 | clocks = <&clks 20>; |
| @@ -554,6 +564,18 @@ | |||
| 554 | sirf,function = "usp0_uart_nostreamctrl"; | 564 | sirf,function = "usp0_uart_nostreamctrl"; |
| 555 | }; | 565 | }; |
| 556 | }; | 566 | }; |
| 567 | usp0_only_utfs_pins_a: usp0@2 { | ||
| 568 | usp0 { | ||
| 569 | sirf,pins = "usp0_only_utfs_grp"; | ||
| 570 | sirf,function = "usp0_only_utfs"; | ||
| 571 | }; | ||
| 572 | }; | ||
| 573 | usp0_only_urfs_pins_a: usp0@3 { | ||
| 574 | usp0 { | ||
| 575 | sirf,pins = "usp0_only_urfs_grp"; | ||
| 576 | sirf,function = "usp0_only_urfs"; | ||
| 577 | }; | ||
| 578 | }; | ||
| 557 | usp1_pins_a: usp1@0 { | 579 | usp1_pins_a: usp1@0 { |
| 558 | usp1 { | 580 | usp1 { |
| 559 | sirf,pins = "usp1grp"; | 581 | sirf,pins = "usp1grp"; |
diff --git a/arch/arm/boot/dts/axm5516-amarillo.dts b/arch/arm/boot/dts/axm5516-amarillo.dts new file mode 100644 index 000000000000..a9d60471d9ff --- /dev/null +++ b/arch/arm/boot/dts/axm5516-amarillo.dts | |||
| @@ -0,0 +1,51 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/boot/dts/axm5516-amarillo.dts | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 LSI | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | |||
| 14 | /memreserve/ 0x00000000 0x00400000; | ||
| 15 | |||
| 16 | #include "axm55xx.dtsi" | ||
| 17 | #include "axm5516-cpus.dtsi" | ||
| 18 | |||
| 19 | / { | ||
| 20 | model = "Amarillo AXM5516"; | ||
| 21 | compatible = "lsi,axm5516-amarillo", "lsi,axm5516"; | ||
| 22 | |||
| 23 | memory { | ||
| 24 | device_type = "memory"; | ||
| 25 | reg = <0 0x00000000 0x02 0x00000000>; | ||
| 26 | }; | ||
| 27 | }; | ||
| 28 | |||
| 29 | &serial0 { | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | &serial1 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | |||
| 37 | &serial2 { | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | &serial3 { | ||
| 42 | status = "okay"; | ||
| 43 | }; | ||
| 44 | |||
| 45 | &gpio0 { | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
| 48 | |||
| 49 | &gpio1 { | ||
| 50 | status = "okay"; | ||
| 51 | }; | ||
diff --git a/arch/arm/boot/dts/axm5516-cpus.dtsi b/arch/arm/boot/dts/axm5516-cpus.dtsi new file mode 100644 index 000000000000..b85f360cb125 --- /dev/null +++ b/arch/arm/boot/dts/axm5516-cpus.dtsi | |||
| @@ -0,0 +1,204 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/boot/dts/axm5516-cpus.dtsi | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 LSI | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | / { | ||
| 13 | cpus { | ||
| 14 | #address-cells = <1>; | ||
| 15 | #size-cells = <0>; | ||
| 16 | |||
| 17 | cpu-map { | ||
| 18 | cluster0 { | ||
| 19 | core0 { | ||
| 20 | cpu = <&CPU0>; | ||
| 21 | }; | ||
| 22 | core1 { | ||
| 23 | cpu = <&CPU1>; | ||
| 24 | }; | ||
| 25 | core2 { | ||
| 26 | cpu = <&CPU2>; | ||
| 27 | }; | ||
| 28 | core3 { | ||
| 29 | cpu = <&CPU3>; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | cluster1 { | ||
| 33 | core0 { | ||
| 34 | cpu = <&CPU4>; | ||
| 35 | }; | ||
| 36 | core1 { | ||
| 37 | cpu = <&CPU5>; | ||
| 38 | }; | ||
| 39 | core2 { | ||
| 40 | cpu = <&CPU6>; | ||
| 41 | }; | ||
| 42 | core3 { | ||
| 43 | cpu = <&CPU7>; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | cluster2 { | ||
| 47 | core0 { | ||
| 48 | cpu = <&CPU8>; | ||
| 49 | }; | ||
| 50 | core1 { | ||
| 51 | cpu = <&CPU9>; | ||
| 52 | }; | ||
| 53 | core2 { | ||
| 54 | cpu = <&CPU10>; | ||
| 55 | }; | ||
| 56 | core3 { | ||
| 57 | cpu = <&CPU11>; | ||
| 58 | }; | ||
| 59 | }; | ||
| 60 | cluster3 { | ||
| 61 | core0 { | ||
| 62 | cpu = <&CPU12>; | ||
| 63 | }; | ||
| 64 | core1 { | ||
| 65 | cpu = <&CPU13>; | ||
| 66 | }; | ||
| 67 | core2 { | ||
| 68 | cpu = <&CPU14>; | ||
| 69 | }; | ||
| 70 | core3 { | ||
| 71 | cpu = <&CPU15>; | ||
| 72 | }; | ||
| 73 | }; | ||
| 74 | }; | ||
| 75 | |||
| 76 | CPU0: cpu@0 { | ||
| 77 | device_type = "cpu"; | ||
| 78 | compatible = "arm,cortex-a15"; | ||
| 79 | reg = <0x00>; | ||
| 80 | clock-frequency= <1400000000>; | ||
| 81 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
| 82 | }; | ||
| 83 | |||
| 84 | CPU1: cpu@1 { | ||
| 85 | device_type = "cpu"; | ||
| 86 | compatible = "arm,cortex-a15"; | ||
| 87 | reg = <0x01>; | ||
| 88 | clock-frequency= <1400000000>; | ||
| 89 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
| 90 | }; | ||
| 91 | |||
| 92 | CPU2: cpu@2 { | ||
| 93 | device_type = "cpu"; | ||
| 94 | compatible = "arm,cortex-a15"; | ||
| 95 | reg = <0x02>; | ||
| 96 | clock-frequency= <1400000000>; | ||
| 97 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
| 98 | }; | ||
| 99 | |||
| 100 | CPU3: cpu@3 { | ||
| 101 | device_type = "cpu"; | ||
| 102 | compatible = "arm,cortex-a15"; | ||
| 103 | reg = <0x03>; | ||
| 104 | clock-frequency= <1400000000>; | ||
| 105 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
| 106 | }; | ||
| 107 | |||
| 108 | CPU4: cpu@100 { | ||
| 109 | device_type = "cpu"; | ||
| 110 | compatible = "arm,cortex-a15"; | ||
| 111 | reg = <0x100>; | ||
| 112 | clock-frequency= <1400000000>; | ||
| 113 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
| 114 | }; | ||
| 115 | |||
| 116 | CPU5: cpu@101 { | ||
| 117 | device_type = "cpu"; | ||
| 118 | compatible = "arm,cortex-a15"; | ||
| 119 | reg = <0x101>; | ||
| 120 | clock-frequency= <1400000000>; | ||
| 121 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
| 122 | }; | ||
| 123 | |||
| 124 | CPU6: cpu@102 { | ||
| 125 | device_type = "cpu"; | ||
| 126 | compatible = "arm,cortex-a15"; | ||
| 127 | reg = <0x102>; | ||
| 128 | clock-frequency= <1400000000>; | ||
| 129 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
| 130 | }; | ||
| 131 | |||
| 132 | CPU7: cpu@103 { | ||
| 133 | device_type = "cpu"; | ||
| 134 | compatible = "arm,cortex-a15"; | ||
| 135 | reg = <0x103>; | ||
| 136 | clock-frequency= <1400000000>; | ||
| 137 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
| 138 | }; | ||
| 139 | |||
| 140 | CPU8: cpu@200 { | ||
| 141 | device_type = "cpu"; | ||
| 142 | compatible = "arm,cortex-a15"; | ||
| 143 | reg = <0x200>; | ||
| 144 | clock-frequency= <1400000000>; | ||
| 145 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
| 146 | }; | ||
| 147 | |||
| 148 | CPU9: cpu@201 { | ||
| 149 | device_type = "cpu"; | ||
| 150 | compatible = "arm,cortex-a15"; | ||
| 151 | reg = <0x201>; | ||
| 152 | clock-frequency= <1400000000>; | ||
| 153 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
| 154 | }; | ||
| 155 | |||
| 156 | CPU10: cpu@202 { | ||
| 157 | device_type = "cpu"; | ||
| 158 | compatible = "arm,cortex-a15"; | ||
| 159 | reg = <0x202>; | ||
| 160 | clock-frequency= <1400000000>; | ||
| 161 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
| 162 | }; | ||
| 163 | |||
| 164 | CPU11: cpu@203 { | ||
| 165 | device_type = "cpu"; | ||
| 166 | compatible = "arm,cortex-a15"; | ||
| 167 | reg = <0x203>; | ||
| 168 | clock-frequency= <1400000000>; | ||
| 169 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
| 170 | }; | ||
| 171 | |||
| 172 | CPU12: cpu@300 { | ||
| 173 | device_type = "cpu"; | ||
| 174 | compatible = "arm,cortex-a15"; | ||
| 175 | reg = <0x300>; | ||
| 176 | clock-frequency= <1400000000>; | ||
| 177 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
| 178 | }; | ||
| 179 | |||
| 180 | CPU13: cpu@301 { | ||
| 181 | device_type = "cpu"; | ||
| 182 | compatible = "arm,cortex-a15"; | ||
| 183 | reg = <0x301>; | ||
| 184 | clock-frequency= <1400000000>; | ||
| 185 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
| 186 | }; | ||
| 187 | |||
| 188 | CPU14: cpu@302 { | ||
| 189 | device_type = "cpu"; | ||
| 190 | compatible = "arm,cortex-a15"; | ||
| 191 | reg = <0x302>; | ||
| 192 | clock-frequency= <1400000000>; | ||
| 193 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
| 194 | }; | ||
| 195 | |||
| 196 | CPU15: cpu@303 { | ||
| 197 | device_type = "cpu"; | ||
| 198 | compatible = "arm,cortex-a15"; | ||
| 199 | reg = <0x303>; | ||
| 200 | clock-frequency= <1400000000>; | ||
| 201 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
| 202 | }; | ||
| 203 | }; | ||
| 204 | }; | ||
diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi new file mode 100644 index 000000000000..ea288f0a1d39 --- /dev/null +++ b/arch/arm/boot/dts/axm55xx.dtsi | |||
| @@ -0,0 +1,204 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/boot/dts/axm55xx.dtsi | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 LSI | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 13 | #include <dt-bindings/clock/lsi,axm5516-clks.h> | ||
| 14 | |||
| 15 | #include "skeleton64.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | interrupt-parent = <&gic>; | ||
| 19 | |||
| 20 | aliases { | ||
| 21 | serial0 = &serial0; | ||
| 22 | serial1 = &serial1; | ||
| 23 | serial2 = &serial2; | ||
| 24 | serial3 = &serial3; | ||
| 25 | timer = &timer0; | ||
| 26 | }; | ||
| 27 | |||
| 28 | clocks { | ||
| 29 | compatible = "simple-bus"; | ||
| 30 | #address-cells = <2>; | ||
| 31 | #size-cells = <2>; | ||
| 32 | ranges; | ||
| 33 | |||
| 34 | clk_ref0: clk_ref0 { | ||
| 35 | compatible = "fixed-clock"; | ||
| 36 | #clock-cells = <0>; | ||
| 37 | clock-frequency = <125000000>; | ||
| 38 | }; | ||
| 39 | |||
| 40 | clk_ref1: clk_ref1 { | ||
| 41 | compatible = "fixed-clock"; | ||
| 42 | #clock-cells = <0>; | ||
| 43 | clock-frequency = <125000000>; | ||
| 44 | }; | ||
| 45 | |||
| 46 | clk_ref2: clk_ref2 { | ||
| 47 | compatible = "fixed-clock"; | ||
| 48 | #clock-cells = <0>; | ||
| 49 | clock-frequency = <125000000>; | ||
| 50 | }; | ||
| 51 | |||
| 52 | clks: clock-controller@2010020000 { | ||
| 53 | compatible = "lsi,axm5516-clks"; | ||
| 54 | #clock-cells = <1>; | ||
| 55 | reg = <0x20 0x10020000 0 0x20000>; | ||
| 56 | }; | ||
| 57 | }; | ||
| 58 | |||
| 59 | gic: interrupt-controller@2001001000 { | ||
| 60 | compatible = "arm,cortex-a15-gic"; | ||
| 61 | #interrupt-cells = <3>; | ||
| 62 | #address-cells = <0>; | ||
| 63 | interrupt-controller; | ||
| 64 | reg = <0x20 0x01001000 0 0x1000>, | ||
| 65 | <0x20 0x01002000 0 0x1000>, | ||
| 66 | <0x20 0x01004000 0 0x2000>, | ||
| 67 | <0x20 0x01006000 0 0x2000>; | ||
| 68 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | | ||
| 69 | IRQ_TYPE_LEVEL_HIGH)>; | ||
| 70 | }; | ||
| 71 | |||
| 72 | timer { | ||
| 73 | compatible = "arm,armv7-timer"; | ||
| 74 | interrupts = | ||
| 75 | <GIC_PPI 13 | ||
| 76 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | ||
| 77 | <GIC_PPI 14 | ||
| 78 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | ||
| 79 | <GIC_PPI 11 | ||
| 80 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | ||
| 81 | <GIC_PPI 10 | ||
| 82 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | ||
| 83 | }; | ||
| 84 | |||
| 85 | |||
| 86 | pmu { | ||
| 87 | compatible = "arm,cortex-a15-pmu"; | ||
| 88 | interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; | ||
| 89 | }; | ||
| 90 | |||
| 91 | soc { | ||
| 92 | compatible = "simple-bus"; | ||
| 93 | device_type = "soc"; | ||
| 94 | #address-cells = <2>; | ||
| 95 | #size-cells = <2>; | ||
| 96 | interrupt-parent = <&gic>; | ||
| 97 | ranges; | ||
| 98 | |||
| 99 | syscon: syscon@2010030000 { | ||
| 100 | compatible = "lsi,axxia-syscon", "syscon"; | ||
| 101 | reg = <0x20 0x10030000 0 0x2000>; | ||
| 102 | }; | ||
| 103 | |||
| 104 | reset: reset@2010031000 { | ||
| 105 | compatible = "lsi,axm55xx-reset"; | ||
| 106 | syscon = <&syscon>; | ||
| 107 | }; | ||
| 108 | |||
| 109 | amba { | ||
| 110 | compatible = "arm,amba-bus"; | ||
| 111 | #address-cells = <2>; | ||
| 112 | #size-cells = <2>; | ||
| 113 | ranges; | ||
| 114 | |||
| 115 | serial0: uart@2010080000 { | ||
| 116 | compatible = "arm,pl011", "arm,primecell"; | ||
| 117 | reg = <0x20 0x10080000 0 0x1000>; | ||
| 118 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | ||
| 119 | clocks = <&clks AXXIA_CLK_PER>; | ||
| 120 | clock-names = "apb_pclk"; | ||
| 121 | status = "disabled"; | ||
| 122 | }; | ||
| 123 | |||
| 124 | serial1: uart@2010081000 { | ||
| 125 | compatible = "arm,pl011", "arm,primecell"; | ||
| 126 | reg = <0x20 0x10081000 0 0x1000>; | ||
| 127 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | ||
| 128 | clocks = <&clks AXXIA_CLK_PER>; | ||
| 129 | clock-names = "apb_pclk"; | ||
| 130 | status = "disabled"; | ||
| 131 | }; | ||
| 132 | |||
| 133 | serial2: uart@2010082000 { | ||
| 134 | compatible = "arm,pl011", "arm,primecell"; | ||
| 135 | reg = <0x20 0x10082000 0 0x1000>; | ||
| 136 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; | ||
| 137 | clocks = <&clks AXXIA_CLK_PER>; | ||
| 138 | clock-names = "apb_pclk"; | ||
| 139 | status = "disabled"; | ||
| 140 | }; | ||
| 141 | |||
| 142 | serial3: uart@2010083000 { | ||
| 143 | compatible = "arm,pl011", "arm,primecell"; | ||
| 144 | reg = <0x20 0x10083000 0 0x1000>; | ||
| 145 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; | ||
| 146 | clocks = <&clks AXXIA_CLK_PER>; | ||
| 147 | clock-names = "apb_pclk"; | ||
| 148 | status = "disabled"; | ||
| 149 | }; | ||
| 150 | |||
| 151 | timer0: timer@2010091000 { | ||
| 152 | compatible = "arm,sp804", "arm,primecell"; | ||
| 153 | reg = <0x20 0x10091000 0 0x1000>; | ||
| 154 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | ||
| 155 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | ||
| 156 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, | ||
| 157 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, | ||
| 158 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | ||
| 159 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, | ||
| 160 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | ||
| 161 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | ||
| 162 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; | ||
| 163 | clocks = <&clks AXXIA_CLK_PER>; | ||
| 164 | clock-names = "apb_pclk"; | ||
| 165 | status = "okay"; | ||
| 166 | }; | ||
| 167 | |||
| 168 | gpio0: gpio@2010092000 { | ||
| 169 | #gpio-cells = <2>; | ||
| 170 | compatible = "arm,pl061", "arm,primecell"; | ||
| 171 | gpio-controller; | ||
| 172 | reg = <0x20 0x10092000 0x00 0x1000>; | ||
| 173 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, | ||
| 174 | <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, | ||
| 175 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, | ||
| 176 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | ||
| 177 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | ||
| 178 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, | ||
| 179 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, | ||
| 180 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | ||
| 181 | clocks = <&clks AXXIA_CLK_PER>; | ||
| 182 | clock-names = "apb_pclk"; | ||
| 183 | status = "disabled"; | ||
| 184 | }; | ||
| 185 | |||
| 186 | gpio1: gpio@2010093000 { | ||
| 187 | #gpio-cells = <2>; | ||
| 188 | compatible = "arm,pl061", "arm,primecell"; | ||
| 189 | gpio-controller; | ||
| 190 | reg = <0x20 0x10093000 0x00 0x1000>; | ||
| 191 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; | ||
| 192 | clocks = <&clks AXXIA_CLK_PER>; | ||
| 193 | clock-names = "apb_pclk"; | ||
| 194 | status = "disabled"; | ||
| 195 | }; | ||
| 196 | }; | ||
| 197 | }; | ||
| 198 | }; | ||
| 199 | |||
| 200 | /* | ||
| 201 | Local Variables: | ||
| 202 | mode: C | ||
| 203 | End: | ||
| 204 | */ | ||
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 64d069bcc409..6b05ae6d476f 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi | |||
| @@ -193,6 +193,14 @@ | |||
| 193 | status = "disabled"; | 193 | status = "disabled"; |
| 194 | }; | 194 | }; |
| 195 | 195 | ||
| 196 | pwm: pwm@3e01a000 { | ||
| 197 | compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm"; | ||
| 198 | reg = <0x3e01a000 0xcc>; | ||
| 199 | clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>; | ||
| 200 | #pwm-cells = <3>; | ||
| 201 | status = "disabled"; | ||
| 202 | }; | ||
| 203 | |||
| 196 | clocks { | 204 | clocks { |
| 197 | #address-cells = <1>; | 205 | #address-cells = <1>; |
| 198 | #size-cells = <1>; | 206 | #size-cells = <1>; |
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 08a44d41b672..8b366822bb43 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi | |||
| @@ -14,6 +14,8 @@ | |||
| 14 | #include <dt-bindings/interrupt-controller/arm-gic.h> | 14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 15 | #include <dt-bindings/interrupt-controller/irq.h> | 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 16 | 16 | ||
| 17 | #include "dt-bindings/clock/bcm21664.h" | ||
| 18 | |||
| 17 | #include "skeleton.dtsi" | 19 | #include "skeleton.dtsi" |
| 18 | 20 | ||
| 19 | / { | 21 | / { |
| @@ -43,7 +45,7 @@ | |||
| 43 | compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; | 45 | compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; |
| 44 | status = "disabled"; | 46 | status = "disabled"; |
| 45 | reg = <0x3e000000 0x118>; | 47 | reg = <0x3e000000 0x118>; |
| 46 | clocks = <&uartb_clk>; | 48 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; |
| 47 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | 49 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| 48 | reg-shift = <2>; | 50 | reg-shift = <2>; |
| 49 | reg-io-width = <4>; | 51 | reg-io-width = <4>; |
| @@ -53,7 +55,7 @@ | |||
| 53 | compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; | 55 | compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; |
| 54 | status = "disabled"; | 56 | status = "disabled"; |
| 55 | reg = <0x3e001000 0x118>; | 57 | reg = <0x3e001000 0x118>; |
| 56 | clocks = <&uartb2_clk>; | 58 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; |
| 57 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; | 59 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
| 58 | reg-shift = <2>; | 60 | reg-shift = <2>; |
| 59 | reg-io-width = <4>; | 61 | reg-io-width = <4>; |
| @@ -63,7 +65,7 @@ | |||
| 63 | compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; | 65 | compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; |
| 64 | status = "disabled"; | 66 | status = "disabled"; |
| 65 | reg = <0x3e002000 0x118>; | 67 | reg = <0x3e002000 0x118>; |
| 66 | clocks = <&uartb3_clk>; | 68 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; |
| 67 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | 69 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| 68 | reg-shift = <2>; | 70 | reg-shift = <2>; |
| 69 | reg-io-width = <4>; | 71 | reg-io-width = <4>; |
| @@ -85,7 +87,7 @@ | |||
| 85 | compatible = "brcm,kona-timer"; | 87 | compatible = "brcm,kona-timer"; |
| 86 | reg = <0x35006000 0x1c>; | 88 | reg = <0x35006000 0x1c>; |
| 87 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | 89 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 88 | clocks = <&hub_timer_clk>; | 90 | clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; |
| 89 | }; | 91 | }; |
| 90 | 92 | ||
| 91 | gpio: gpio@35003000 { | 93 | gpio: gpio@35003000 { |
| @@ -106,7 +108,7 @@ | |||
| 106 | compatible = "brcm,kona-sdhci"; | 108 | compatible = "brcm,kona-sdhci"; |
| 107 | reg = <0x3f180000 0x801c>; | 109 | reg = <0x3f180000 0x801c>; |
| 108 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | 110 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 109 | clocks = <&sdio1_clk>; | 111 | clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; |
| 110 | status = "disabled"; | 112 | status = "disabled"; |
| 111 | }; | 113 | }; |
| 112 | 114 | ||
| @@ -114,7 +116,7 @@ | |||
| 114 | compatible = "brcm,kona-sdhci"; | 116 | compatible = "brcm,kona-sdhci"; |
| 115 | reg = <0x3f190000 0x801c>; | 117 | reg = <0x3f190000 0x801c>; |
| 116 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | 118 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 117 | clocks = <&sdio2_clk>; | 119 | clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; |
| 118 | status = "disabled"; | 120 | status = "disabled"; |
| 119 | }; | 121 | }; |
| 120 | 122 | ||
| @@ -122,7 +124,7 @@ | |||
| 122 | compatible = "brcm,kona-sdhci"; | 124 | compatible = "brcm,kona-sdhci"; |
| 123 | reg = <0x3f1a0000 0x801c>; | 125 | reg = <0x3f1a0000 0x801c>; |
| 124 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | 126 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 125 | clocks = <&sdio3_clk>; | 127 | clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; |
| 126 | status = "disabled"; | 128 | status = "disabled"; |
| 127 | }; | 129 | }; |
| 128 | 130 | ||
| @@ -130,7 +132,7 @@ | |||
| 130 | compatible = "brcm,kona-sdhci"; | 132 | compatible = "brcm,kona-sdhci"; |
| 131 | reg = <0x3f1b0000 0x801c>; | 133 | reg = <0x3f1b0000 0x801c>; |
| 132 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | 134 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 133 | clocks = <&sdio4_clk>; | 135 | clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; |
| 134 | status = "disabled"; | 136 | status = "disabled"; |
| 135 | }; | 137 | }; |
| 136 | 138 | ||
| @@ -140,7 +142,7 @@ | |||
| 140 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | 142 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| 141 | #address-cells = <1>; | 143 | #address-cells = <1>; |
| 142 | #size-cells = <0>; | 144 | #size-cells = <0>; |
| 143 | clocks = <&bsc1_clk>; | 145 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; |
| 144 | status = "disabled"; | 146 | status = "disabled"; |
| 145 | }; | 147 | }; |
| 146 | 148 | ||
| @@ -150,7 +152,7 @@ | |||
| 150 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | 152 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| 151 | #address-cells = <1>; | 153 | #address-cells = <1>; |
| 152 | #size-cells = <0>; | 154 | #size-cells = <0>; |
| 153 | clocks = <&bsc2_clk>; | 155 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; |
| 154 | status = "disabled"; | 156 | status = "disabled"; |
| 155 | }; | 157 | }; |
| 156 | 158 | ||
| @@ -160,7 +162,7 @@ | |||
| 160 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; | 162 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
| 161 | #address-cells = <1>; | 163 | #address-cells = <1>; |
| 162 | #size-cells = <0>; | 164 | #size-cells = <0>; |
| 163 | clocks = <&bsc3_clk>; | 165 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; |
| 164 | status = "disabled"; | 166 | status = "disabled"; |
| 165 | }; | 167 | }; |
| 166 | 168 | ||
| @@ -170,105 +172,149 @@ | |||
| 170 | interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; | 172 | interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; |
| 171 | #address-cells = <1>; | 173 | #address-cells = <1>; |
| 172 | #size-cells = <0>; | 174 | #size-cells = <0>; |
| 173 | clocks = <&bsc4_clk>; | 175 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; |
| 174 | status = "disabled"; | 176 | status = "disabled"; |
| 175 | }; | 177 | }; |
| 176 | 178 | ||
| 177 | clocks { | 179 | clocks { |
| 178 | bsc1_clk: bsc1 { | 180 | #address-cells = <1>; |
| 179 | compatible = "fixed-clock"; | 181 | #size-cells = <1>; |
| 180 | clock-frequency = <13000000>; | 182 | ranges; |
| 181 | #clock-cells = <0>; | ||
| 182 | }; | ||
| 183 | 183 | ||
| 184 | bsc2_clk: bsc2 { | 184 | /* |
| 185 | compatible = "fixed-clock"; | 185 | * Fixed clocks are defined before CCUs whose |
| 186 | clock-frequency = <13000000>; | 186 | * clocks may depend on them. |
| 187 | */ | ||
| 188 | |||
| 189 | ref_32k_clk: ref_32k { | ||
| 187 | #clock-cells = <0>; | 190 | #clock-cells = <0>; |
| 191 | compatible = "fixed-clock"; | ||
| 192 | clock-frequency = <32768>; | ||
| 188 | }; | 193 | }; |
| 189 | 194 | ||
| 190 | bsc3_clk: bsc3 { | 195 | bbl_32k_clk: bbl_32k { |
| 191 | compatible = "fixed-clock"; | ||
| 192 | clock-frequency = <13000000>; | ||
| 193 | #clock-cells = <0>; | 196 | #clock-cells = <0>; |
| 197 | compatible = "fixed-clock"; | ||
| 198 | clock-frequency = <32768>; | ||
| 194 | }; | 199 | }; |
| 195 | 200 | ||
| 196 | bsc4_clk: bsc4 { | 201 | ref_13m_clk: ref_13m { |
| 202 | #clock-cells = <0>; | ||
| 197 | compatible = "fixed-clock"; | 203 | compatible = "fixed-clock"; |
| 198 | clock-frequency = <13000000>; | 204 | clock-frequency = <13000000>; |
| 199 | #clock-cells = <0>; | ||
| 200 | }; | 205 | }; |
| 201 | 206 | ||
| 202 | pmu_bsc_clk: pmu_bsc { | 207 | var_13m_clk: var_13m { |
| 208 | #clock-cells = <0>; | ||
| 203 | compatible = "fixed-clock"; | 209 | compatible = "fixed-clock"; |
| 204 | clock-frequency = <13000000>; | 210 | clock-frequency = <13000000>; |
| 205 | #clock-cells = <0>; | ||
| 206 | }; | 211 | }; |
| 207 | 212 | ||
| 208 | hub_timer_clk: hub_timer { | 213 | dft_19_5m_clk: dft_19_5m { |
| 209 | compatible = "fixed-clock"; | ||
| 210 | clock-frequency = <32768>; | ||
| 211 | #clock-cells = <0>; | 214 | #clock-cells = <0>; |
| 215 | compatible = "fixed-clock"; | ||
| 216 | clock-frequency = <19500000>; | ||
| 212 | }; | 217 | }; |
| 213 | 218 | ||
| 214 | pwm_clk: pwm { | 219 | ref_crystal_clk: ref_crystal { |
| 220 | #clock-cells = <0>; | ||
| 215 | compatible = "fixed-clock"; | 221 | compatible = "fixed-clock"; |
| 216 | clock-frequency = <26000000>; | 222 | clock-frequency = <26000000>; |
| 217 | #clock-cells = <0>; | ||
| 218 | }; | 223 | }; |
| 219 | 224 | ||
| 220 | sdio1_clk: sdio1 { | 225 | ref_52m_clk: ref_52m { |
| 221 | compatible = "fixed-clock"; | ||
| 222 | clock-frequency = <48000000>; | ||
| 223 | #clock-cells = <0>; | 226 | #clock-cells = <0>; |
| 227 | compatible = "fixed-clock"; | ||
| 228 | clock-frequency = <52000000>; | ||
| 224 | }; | 229 | }; |
| 225 | 230 | ||
| 226 | sdio2_clk: sdio2 { | 231 | var_52m_clk: var_52m { |
| 227 | compatible = "fixed-clock"; | ||
| 228 | clock-frequency = <48000000>; | ||
| 229 | #clock-cells = <0>; | 232 | #clock-cells = <0>; |
| 233 | compatible = "fixed-clock"; | ||
| 234 | clock-frequency = <52000000>; | ||
| 230 | }; | 235 | }; |
| 231 | 236 | ||
| 232 | sdio3_clk: sdio3 { | 237 | usb_otg_ahb_clk: usb_otg_ahb { |
| 233 | compatible = "fixed-clock"; | ||
| 234 | clock-frequency = <48000000>; | ||
| 235 | #clock-cells = <0>; | 238 | #clock-cells = <0>; |
| 239 | compatible = "fixed-clock"; | ||
| 240 | clock-frequency = <52000000>; | ||
| 236 | }; | 241 | }; |
| 237 | 242 | ||
| 238 | sdio4_clk: sdio4 { | 243 | ref_96m_clk: ref_96m { |
| 239 | compatible = "fixed-clock"; | ||
| 240 | clock-frequency = <48000000>; | ||
| 241 | #clock-cells = <0>; | 244 | #clock-cells = <0>; |
| 245 | compatible = "fixed-clock"; | ||
| 246 | clock-frequency = <96000000>; | ||
| 242 | }; | 247 | }; |
| 243 | 248 | ||
| 244 | tmon_1m_clk: tmon_1m { | 249 | var_96m_clk: var_96m { |
| 245 | compatible = "fixed-clock"; | ||
| 246 | clock-frequency = <1000000>; | ||
| 247 | #clock-cells = <0>; | 250 | #clock-cells = <0>; |
| 251 | compatible = "fixed-clock"; | ||
| 252 | clock-frequency = <96000000>; | ||
| 248 | }; | 253 | }; |
| 249 | 254 | ||
| 250 | uartb_clk: uartb { | 255 | ref_104m_clk: ref_104m { |
| 251 | compatible = "fixed-clock"; | ||
| 252 | clock-frequency = <13000000>; | ||
| 253 | #clock-cells = <0>; | 256 | #clock-cells = <0>; |
| 257 | compatible = "fixed-clock"; | ||
| 258 | clock-frequency = <104000000>; | ||
| 254 | }; | 259 | }; |
| 255 | 260 | ||
| 256 | uartb2_clk: uartb2 { | 261 | var_104m_clk: var_104m { |
| 257 | compatible = "fixed-clock"; | ||
| 258 | clock-frequency = <13000000>; | ||
| 259 | #clock-cells = <0>; | 262 | #clock-cells = <0>; |
| 263 | compatible = "fixed-clock"; | ||
| 264 | clock-frequency = <104000000>; | ||
| 260 | }; | 265 | }; |
| 261 | 266 | ||
| 262 | uartb3_clk: uartb3 { | 267 | ref_156m_clk: ref_156m { |
| 263 | compatible = "fixed-clock"; | ||
| 264 | clock-frequency = <13000000>; | ||
| 265 | #clock-cells = <0>; | 268 | #clock-cells = <0>; |
| 269 | compatible = "fixed-clock"; | ||
| 270 | clock-frequency = <156000000>; | ||
| 266 | }; | 271 | }; |
| 267 | 272 | ||
| 268 | usb_otg_ahb_clk: usb_otg_ahb { | 273 | var_156m_clk: var_156m { |
| 269 | compatible = "fixed-clock"; | ||
| 270 | clock-frequency = <52000000>; | ||
| 271 | #clock-cells = <0>; | 274 | #clock-cells = <0>; |
| 275 | compatible = "fixed-clock"; | ||
| 276 | clock-frequency = <156000000>; | ||
| 277 | }; | ||
| 278 | |||
| 279 | root_ccu: root_ccu { | ||
| 280 | compatible = BCM21664_DT_ROOT_CCU_COMPAT; | ||
| 281 | reg = <0x35001000 0x0f00>; | ||
| 282 | #clock-cells = <1>; | ||
| 283 | clock-output-names = "frac_1m"; | ||
| 284 | }; | ||
| 285 | |||
| 286 | aon_ccu: aon_ccu { | ||
| 287 | compatible = BCM21664_DT_AON_CCU_COMPAT; | ||
| 288 | reg = <0x35002000 0x0f00>; | ||
| 289 | #clock-cells = <1>; | ||
| 290 | clock-output-names = "hub_timer"; | ||
| 291 | }; | ||
| 292 | |||
| 293 | master_ccu: master_ccu { | ||
| 294 | compatible = BCM21664_DT_MASTER_CCU_COMPAT; | ||
| 295 | reg = <0x3f001000 0x0f00>; | ||
| 296 | #clock-cells = <1>; | ||
| 297 | clock-output-names = "sdio1", | ||
| 298 | "sdio2", | ||
| 299 | "sdio3", | ||
| 300 | "sdio4", | ||
| 301 | "sdio1_sleep", | ||
| 302 | "sdio2_sleep", | ||
| 303 | "sdio3_sleep", | ||
| 304 | "sdio4_sleep"; | ||
| 305 | }; | ||
| 306 | |||
| 307 | slave_ccu: slave_ccu { | ||
| 308 | compatible = BCM21664_DT_SLAVE_CCU_COMPAT; | ||
| 309 | reg = <0x3e011000 0x0f00>; | ||
| 310 | #clock-cells = <1>; | ||
| 311 | clock-output-names = "uartb", | ||
| 312 | "uartb2", | ||
| 313 | "uartb3", | ||
| 314 | "bsc1", | ||
| 315 | "bsc2", | ||
| 316 | "bsc3", | ||
| 317 | "bsc4"; | ||
| 272 | }; | 318 | }; |
| 273 | }; | 319 | }; |
| 274 | 320 | ||
diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts index af3da55eef49..9ce91dd60cb6 100644 --- a/arch/arm/boot/dts/bcm28155-ap.dts +++ b/arch/arm/boot/dts/bcm28155-ap.dts | |||
| @@ -69,6 +69,10 @@ | |||
| 69 | status = "okay"; | 69 | status = "okay"; |
| 70 | }; | 70 | }; |
| 71 | 71 | ||
| 72 | pwm: pwm@3e01a000 { | ||
| 73 | status = "okay"; | ||
| 74 | }; | ||
| 75 | |||
| 72 | usbotg: usb@3f120000 { | 76 | usbotg: usb@3f120000 { |
| 73 | vusb_d-supply = <&usbldo_reg>; | 77 | vusb_d-supply = <&usbldo_reg>; |
| 74 | vusb_a-supply = <&iosr1_reg>; | 78 | vusb_a-supply = <&iosr1_reg>; |
diff --git a/arch/arm/boot/dts/bcm59056.dtsi b/arch/arm/boot/dts/bcm59056.dtsi index dfadaaa89b05..066adfb10bd5 100644 --- a/arch/arm/boot/dts/bcm59056.dtsi +++ b/arch/arm/boot/dts/bcm59056.dtsi | |||
| @@ -70,5 +70,26 @@ | |||
| 70 | 70 | ||
| 71 | vsr_reg: vsr { | 71 | vsr_reg: vsr { |
| 72 | }; | 72 | }; |
| 73 | |||
| 74 | gpldo1_reg: gpldo1 { | ||
| 75 | }; | ||
| 76 | |||
| 77 | gpldo2_reg: gpldo2 { | ||
| 78 | }; | ||
| 79 | |||
| 80 | gpldo3_reg: gpldo3 { | ||
| 81 | }; | ||
| 82 | |||
| 83 | gpldo4_reg: gpldo4 { | ||
| 84 | }; | ||
| 85 | |||
| 86 | gpldo5_reg: gpldo5 { | ||
| 87 | }; | ||
| 88 | |||
| 89 | gpldo6_reg: gpldo6 { | ||
| 90 | }; | ||
| 91 | |||
| 92 | vbus_reg: vbus { | ||
| 93 | }; | ||
| 73 | }; | 94 | }; |
| 74 | }; | 95 | }; |
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index 56a1af2f1052..2477dac4d643 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | #include "skeleton.dtsi" | 14 | #include "skeleton.dtsi" |
| 15 | #include <dt-bindings/clock/berlin2.h> | ||
| 15 | #include <dt-bindings/interrupt-controller/arm-gic.h> | 16 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 16 | 17 | ||
| 17 | / { | 18 | / { |
| @@ -37,24 +38,10 @@ | |||
| 37 | }; | 38 | }; |
| 38 | }; | 39 | }; |
| 39 | 40 | ||
| 40 | clocks { | 41 | refclk: oscillator { |
| 41 | smclk: sysmgr-clock { | 42 | compatible = "fixed-clock"; |
| 42 | compatible = "fixed-clock"; | 43 | #clock-cells = <0>; |
| 43 | #clock-cells = <0>; | 44 | clock-frequency = <25000000>; |
| 44 | clock-frequency = <25000000>; | ||
| 45 | }; | ||
| 46 | |||
| 47 | cfgclk: cfg-clock { | ||
| 48 | compatible = "fixed-clock"; | ||
| 49 | #clock-cells = <0>; | ||
| 50 | clock-frequency = <100000000>; | ||
| 51 | }; | ||
| 52 | |||
| 53 | sysclk: system-clock { | ||
| 54 | compatible = "fixed-clock"; | ||
| 55 | #clock-cells = <0>; | ||
| 56 | clock-frequency = <400000000>; | ||
| 57 | }; | ||
| 58 | }; | 45 | }; |
| 59 | 46 | ||
| 60 | soc { | 47 | soc { |
| @@ -72,6 +59,11 @@ | |||
| 72 | cache-level = <2>; | 59 | cache-level = <2>; |
| 73 | }; | 60 | }; |
| 74 | 61 | ||
| 62 | scu: snoop-control-unit@ad0000 { | ||
| 63 | compatible = "arm,cortex-a9-scu"; | ||
| 64 | reg = <0xad0000 0x58>; | ||
| 65 | }; | ||
| 66 | |||
| 75 | gic: interrupt-controller@ad1000 { | 67 | gic: interrupt-controller@ad1000 { |
| 76 | compatible = "arm,cortex-a9-gic"; | 68 | compatible = "arm,cortex-a9-gic"; |
| 77 | reg = <0xad1000 0x1000>, <0xad0100 0x0100>; | 69 | reg = <0xad1000 0x1000>, <0xad0100 0x0100>; |
| @@ -83,7 +75,7 @@ | |||
| 83 | compatible = "arm,cortex-a9-twd-timer"; | 75 | compatible = "arm,cortex-a9-twd-timer"; |
| 84 | reg = <0xad0600 0x20>; | 76 | reg = <0xad0600 0x20>; |
| 85 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; | 77 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| 86 | clocks = <&sysclk>; | 78 | clocks = <&chip CLKID_TWD>; |
| 87 | }; | 79 | }; |
| 88 | 80 | ||
| 89 | apb@e80000 { | 81 | apb@e80000 { |
| @@ -94,11 +86,83 @@ | |||
| 94 | ranges = <0 0xe80000 0x10000>; | 86 | ranges = <0 0xe80000 0x10000>; |
| 95 | interrupt-parent = <&aic>; | 87 | interrupt-parent = <&aic>; |
| 96 | 88 | ||
| 89 | gpio0: gpio@0400 { | ||
| 90 | compatible = "snps,dw-apb-gpio"; | ||
| 91 | reg = <0x0400 0x400>; | ||
| 92 | #address-cells = <1>; | ||
| 93 | #size-cells = <0>; | ||
| 94 | |||
| 95 | porta: gpio-port@0 { | ||
| 96 | compatible = "snps,dw-apb-gpio-port"; | ||
| 97 | gpio-controller; | ||
| 98 | #gpio-cells = <2>; | ||
| 99 | snps,nr-gpios = <8>; | ||
| 100 | reg = <0>; | ||
| 101 | interrupt-controller; | ||
| 102 | #interrupt-cells = <2>; | ||
| 103 | interrupts = <0>; | ||
| 104 | }; | ||
| 105 | }; | ||
| 106 | |||
| 107 | gpio1: gpio@0800 { | ||
| 108 | compatible = "snps,dw-apb-gpio"; | ||
| 109 | reg = <0x0800 0x400>; | ||
| 110 | #address-cells = <1>; | ||
| 111 | #size-cells = <0>; | ||
| 112 | |||
| 113 | portb: gpio-port@1 { | ||
| 114 | compatible = "snps,dw-apb-gpio-port"; | ||
| 115 | gpio-controller; | ||
| 116 | #gpio-cells = <2>; | ||
| 117 | snps,nr-gpios = <8>; | ||
| 118 | reg = <0>; | ||
| 119 | interrupt-controller; | ||
| 120 | #interrupt-cells = <2>; | ||
| 121 | interrupts = <1>; | ||
| 122 | }; | ||
| 123 | }; | ||
| 124 | |||
| 125 | gpio2: gpio@0c00 { | ||
| 126 | compatible = "snps,dw-apb-gpio"; | ||
| 127 | reg = <0x0c00 0x400>; | ||
| 128 | #address-cells = <1>; | ||
| 129 | #size-cells = <0>; | ||
| 130 | |||
| 131 | portc: gpio-port@2 { | ||
| 132 | compatible = "snps,dw-apb-gpio-port"; | ||
| 133 | gpio-controller; | ||
| 134 | #gpio-cells = <2>; | ||
| 135 | snps,nr-gpios = <8>; | ||
| 136 | reg = <0>; | ||
| 137 | interrupt-controller; | ||
| 138 | #interrupt-cells = <2>; | ||
| 139 | interrupts = <2>; | ||
| 140 | }; | ||
| 141 | }; | ||
| 142 | |||
| 143 | gpio3: gpio@1000 { | ||
| 144 | compatible = "snps,dw-apb-gpio"; | ||
| 145 | reg = <0x1000 0x400>; | ||
| 146 | #address-cells = <1>; | ||
| 147 | #size-cells = <0>; | ||
| 148 | |||
| 149 | portd: gpio-port@3 { | ||
| 150 | compatible = "snps,dw-apb-gpio-port"; | ||
| 151 | gpio-controller; | ||
| 152 | #gpio-cells = <2>; | ||
| 153 | snps,nr-gpios = <8>; | ||
| 154 | reg = <0>; | ||
| 155 | interrupt-controller; | ||
| 156 | #interrupt-cells = <2>; | ||
| 157 | interrupts = <3>; | ||
| 158 | }; | ||
| 159 | }; | ||
| 160 | |||
| 97 | timer0: timer@2c00 { | 161 | timer0: timer@2c00 { |
| 98 | compatible = "snps,dw-apb-timer"; | 162 | compatible = "snps,dw-apb-timer"; |
| 99 | reg = <0x2c00 0x14>; | 163 | reg = <0x2c00 0x14>; |
| 100 | interrupts = <8>; | 164 | interrupts = <8>; |
| 101 | clocks = <&cfgclk>; | 165 | clocks = <&chip CLKID_CFG>; |
| 102 | clock-names = "timer"; | 166 | clock-names = "timer"; |
| 103 | status = "okay"; | 167 | status = "okay"; |
| 104 | }; | 168 | }; |
| @@ -107,7 +171,7 @@ | |||
| 107 | compatible = "snps,dw-apb-timer"; | 171 | compatible = "snps,dw-apb-timer"; |
| 108 | reg = <0x2c14 0x14>; | 172 | reg = <0x2c14 0x14>; |
| 109 | interrupts = <9>; | 173 | interrupts = <9>; |
| 110 | clocks = <&cfgclk>; | 174 | clocks = <&chip CLKID_CFG>; |
| 111 | clock-names = "timer"; | 175 | clock-names = "timer"; |
| 112 | status = "okay"; | 176 | status = "okay"; |
| 113 | }; | 177 | }; |
| @@ -116,7 +180,7 @@ | |||
| 116 | compatible = "snps,dw-apb-timer"; | 180 | compatible = "snps,dw-apb-timer"; |
| 117 | reg = <0x2c28 0x14>; | 181 | reg = <0x2c28 0x14>; |
| 118 | interrupts = <10>; | 182 | interrupts = <10>; |
| 119 | clocks = <&cfgclk>; | 183 | clocks = <&chip CLKID_CFG>; |
| 120 | clock-names = "timer"; | 184 | clock-names = "timer"; |
| 121 | status = "disabled"; | 185 | status = "disabled"; |
| 122 | }; | 186 | }; |
| @@ -125,7 +189,7 @@ | |||
| 125 | compatible = "snps,dw-apb-timer"; | 189 | compatible = "snps,dw-apb-timer"; |
| 126 | reg = <0x2c3c 0x14>; | 190 | reg = <0x2c3c 0x14>; |
| 127 | interrupts = <11>; | 191 | interrupts = <11>; |
| 128 | clocks = <&cfgclk>; | 192 | clocks = <&chip CLKID_CFG>; |
| 129 | clock-names = "timer"; | 193 | clock-names = "timer"; |
| 130 | status = "disabled"; | 194 | status = "disabled"; |
| 131 | }; | 195 | }; |
| @@ -134,7 +198,7 @@ | |||
| 134 | compatible = "snps,dw-apb-timer"; | 198 | compatible = "snps,dw-apb-timer"; |
| 135 | reg = <0x2c50 0x14>; | 199 | reg = <0x2c50 0x14>; |
| 136 | interrupts = <12>; | 200 | interrupts = <12>; |
| 137 | clocks = <&cfgclk>; | 201 | clocks = <&chip CLKID_CFG>; |
| 138 | clock-names = "timer"; | 202 | clock-names = "timer"; |
| 139 | status = "disabled"; | 203 | status = "disabled"; |
| 140 | }; | 204 | }; |
| @@ -143,7 +207,7 @@ | |||
| 143 | compatible = "snps,dw-apb-timer"; | 207 | compatible = "snps,dw-apb-timer"; |
| 144 | reg = <0x2c64 0x14>; | 208 | reg = <0x2c64 0x14>; |
| 145 | interrupts = <13>; | 209 | interrupts = <13>; |
| 146 | clocks = <&cfgclk>; | 210 | clocks = <&chip CLKID_CFG>; |
| 147 | clock-names = "timer"; | 211 | clock-names = "timer"; |
| 148 | status = "disabled"; | 212 | status = "disabled"; |
| 149 | }; | 213 | }; |
| @@ -152,7 +216,7 @@ | |||
| 152 | compatible = "snps,dw-apb-timer"; | 216 | compatible = "snps,dw-apb-timer"; |
| 153 | reg = <0x2c78 0x14>; | 217 | reg = <0x2c78 0x14>; |
| 154 | interrupts = <14>; | 218 | interrupts = <14>; |
| 155 | clocks = <&cfgclk>; | 219 | clocks = <&chip CLKID_CFG>; |
| 156 | clock-names = "timer"; | 220 | clock-names = "timer"; |
| 157 | status = "disabled"; | 221 | status = "disabled"; |
| 158 | }; | 222 | }; |
| @@ -161,7 +225,7 @@ | |||
| 161 | compatible = "snps,dw-apb-timer"; | 225 | compatible = "snps,dw-apb-timer"; |
| 162 | reg = <0x2c8c 0x14>; | 226 | reg = <0x2c8c 0x14>; |
| 163 | interrupts = <15>; | 227 | interrupts = <15>; |
| 164 | clocks = <&cfgclk>; | 228 | clocks = <&chip CLKID_CFG>; |
| 165 | clock-names = "timer"; | 229 | clock-names = "timer"; |
| 166 | status = "disabled"; | 230 | status = "disabled"; |
| 167 | }; | 231 | }; |
| @@ -176,6 +240,14 @@ | |||
| 176 | }; | 240 | }; |
| 177 | }; | 241 | }; |
| 178 | 242 | ||
| 243 | chip: chip-control@ea0000 { | ||
| 244 | compatible = "marvell,berlin2-chip-ctrl"; | ||
| 245 | #clock-cells = <1>; | ||
| 246 | reg = <0xea0000 0x400>; | ||
| 247 | clocks = <&refclk>; | ||
| 248 | clock-names = "refclk"; | ||
| 249 | }; | ||
| 250 | |||
| 179 | apb@fc0000 { | 251 | apb@fc0000 { |
| 180 | compatible = "simple-bus"; | 252 | compatible = "simple-bus"; |
| 181 | #address-cells = <1>; | 253 | #address-cells = <1>; |
| @@ -184,13 +256,48 @@ | |||
| 184 | ranges = <0 0xfc0000 0x10000>; | 256 | ranges = <0 0xfc0000 0x10000>; |
| 185 | interrupt-parent = <&sic>; | 257 | interrupt-parent = <&sic>; |
| 186 | 258 | ||
| 259 | sm_gpio1: gpio@5000 { | ||
| 260 | compatible = "snps,dw-apb-gpio"; | ||
| 261 | reg = <0x5000 0x400>; | ||
| 262 | #address-cells = <1>; | ||
| 263 | #size-cells = <0>; | ||
| 264 | |||
| 265 | portf: gpio-port@5 { | ||
| 266 | compatible = "snps,dw-apb-gpio-port"; | ||
| 267 | gpio-controller; | ||
| 268 | #gpio-cells = <2>; | ||
| 269 | snps,nr-gpios = <8>; | ||
| 270 | reg = <0>; | ||
| 271 | }; | ||
| 272 | }; | ||
| 273 | |||
| 274 | sm_gpio0: gpio@c000 { | ||
| 275 | compatible = "snps,dw-apb-gpio"; | ||
| 276 | reg = <0xc000 0x400>; | ||
| 277 | #address-cells = <1>; | ||
| 278 | #size-cells = <0>; | ||
| 279 | |||
| 280 | porte: gpio-port@4 { | ||
| 281 | compatible = "snps,dw-apb-gpio-port"; | ||
| 282 | gpio-controller; | ||
| 283 | #gpio-cells = <2>; | ||
| 284 | snps,nr-gpios = <8>; | ||
| 285 | reg = <0>; | ||
| 286 | interrupt-controller; | ||
| 287 | #interrupt-cells = <2>; | ||
| 288 | interrupts = <11>; | ||
| 289 | }; | ||
| 290 | }; | ||
| 291 | |||
| 187 | uart0: serial@9000 { | 292 | uart0: serial@9000 { |
| 188 | compatible = "snps,dw-apb-uart"; | 293 | compatible = "snps,dw-apb-uart"; |
| 189 | reg = <0x9000 0x100>; | 294 | reg = <0x9000 0x100>; |
| 190 | reg-shift = <2>; | 295 | reg-shift = <2>; |
| 191 | reg-io-width = <1>; | 296 | reg-io-width = <1>; |
| 192 | interrupts = <8>; | 297 | interrupts = <8>; |
| 193 | clocks = <&smclk>; | 298 | clocks = <&refclk>; |
| 299 | pinctrl-0 = <&uart0_pmux>; | ||
| 300 | pinctrl-names = "default"; | ||
| 194 | status = "disabled"; | 301 | status = "disabled"; |
| 195 | }; | 302 | }; |
| 196 | 303 | ||
| @@ -200,7 +307,9 @@ | |||
| 200 | reg-shift = <2>; | 307 | reg-shift = <2>; |
| 201 | reg-io-width = <1>; | 308 | reg-io-width = <1>; |
| 202 | interrupts = <9>; | 309 | interrupts = <9>; |
| 203 | clocks = <&smclk>; | 310 | clocks = <&refclk>; |
| 311 | pinctrl-0 = <&uart1_pmux>; | ||
| 312 | pinctrl-names = "default"; | ||
| 204 | status = "disabled"; | 313 | status = "disabled"; |
| 205 | }; | 314 | }; |
| 206 | 315 | ||
| @@ -210,10 +319,32 @@ | |||
| 210 | reg-shift = <2>; | 319 | reg-shift = <2>; |
| 211 | reg-io-width = <1>; | 320 | reg-io-width = <1>; |
| 212 | interrupts = <10>; | 321 | interrupts = <10>; |
| 213 | clocks = <&smclk>; | 322 | clocks = <&refclk>; |
| 323 | pinctrl-0 = <&uart2_pmux>; | ||
| 324 | pinctrl-names = "default"; | ||
| 214 | status = "disabled"; | 325 | status = "disabled"; |
| 215 | }; | 326 | }; |
| 216 | 327 | ||
| 328 | sysctrl: system-controller@d000 { | ||
| 329 | compatible = "marvell,berlin2-system-ctrl"; | ||
| 330 | reg = <0xd000 0x100>; | ||
| 331 | |||
| 332 | uart0_pmux: uart0-pmux { | ||
| 333 | groups = "GSM4"; | ||
| 334 | function = "uart0"; | ||
| 335 | }; | ||
| 336 | |||
| 337 | uart1_pmux: uart1-pmux { | ||
| 338 | groups = "GSM5"; | ||
| 339 | function = "uart1"; | ||
| 340 | }; | ||
| 341 | |||
| 342 | uart2_pmux: uart2-pmux { | ||
| 343 | groups = "GSM3"; | ||
| 344 | function = "uart2"; | ||
| 345 | }; | ||
| 346 | }; | ||
| 347 | |||
| 217 | sic: interrupt-controller@e000 { | 348 | sic: interrupt-controller@e000 { |
| 218 | compatible = "snps,dw-apb-ictl"; | 349 | compatible = "snps,dw-apb-ictl"; |
| 219 | reg = <0xe000 0x400>; | 350 | reg = <0xe000 0x400>; |
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index 094968c27533..cc1df65da504 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | #include "skeleton.dtsi" | 14 | #include "skeleton.dtsi" |
| 15 | #include <dt-bindings/clock/berlin2.h> | ||
| 15 | #include <dt-bindings/interrupt-controller/arm-gic.h> | 16 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 16 | 17 | ||
| 17 | / { | 18 | / { |
| @@ -30,24 +31,10 @@ | |||
| 30 | }; | 31 | }; |
| 31 | }; | 32 | }; |
| 32 | 33 | ||
| 33 | clocks { | 34 | refclk: oscillator { |
| 34 | smclk: sysmgr-clock { | 35 | compatible = "fixed-clock"; |
| 35 | compatible = "fixed-clock"; | 36 | #clock-cells = <0>; |
| 36 | #clock-cells = <0>; | 37 | clock-frequency = <25000000>; |
| 37 | clock-frequency = <25000000>; | ||
| 38 | }; | ||
| 39 | |||
| 40 | cfgclk: cfg-clock { | ||
| 41 | compatible = "fixed-clock"; | ||
| 42 | #clock-cells = <0>; | ||
| 43 | clock-frequency = <75000000>; | ||
| 44 | }; | ||
| 45 | |||
| 46 | sysclk: system-clock { | ||
| 47 | compatible = "fixed-clock"; | ||
| 48 | #clock-cells = <0>; | ||
| 49 | clock-frequency = <300000000>; | ||
| 50 | }; | ||
| 51 | }; | 38 | }; |
| 52 | 39 | ||
| 53 | soc { | 40 | soc { |
| @@ -76,7 +63,7 @@ | |||
| 76 | compatible = "arm,cortex-a9-twd-timer"; | 63 | compatible = "arm,cortex-a9-twd-timer"; |
| 77 | reg = <0xad0600 0x20>; | 64 | reg = <0xad0600 0x20>; |
| 78 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; | 65 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| 79 | clocks = <&sysclk>; | 66 | clocks = <&chip CLKID_TWD>; |
| 80 | }; | 67 | }; |
| 81 | 68 | ||
| 82 | apb@e80000 { | 69 | apb@e80000 { |
| @@ -87,11 +74,83 @@ | |||
| 87 | ranges = <0 0xe80000 0x10000>; | 74 | ranges = <0 0xe80000 0x10000>; |
| 88 | interrupt-parent = <&aic>; | 75 | interrupt-parent = <&aic>; |
| 89 | 76 | ||
| 77 | gpio0: gpio@0400 { | ||
| 78 | compatible = "snps,dw-apb-gpio"; | ||
| 79 | reg = <0x0400 0x400>; | ||
| 80 | #address-cells = <1>; | ||
| 81 | #size-cells = <0>; | ||
| 82 | |||
| 83 | porta: gpio-port@0 { | ||
| 84 | compatible = "snps,dw-apb-gpio-port"; | ||
| 85 | gpio-controller; | ||
| 86 | #gpio-cells = <2>; | ||
| 87 | snps,nr-gpios = <8>; | ||
| 88 | reg = <0>; | ||
| 89 | interrupt-controller; | ||
| 90 | #interrupt-cells = <2>; | ||
| 91 | interrupts = <0>; | ||
| 92 | }; | ||
| 93 | }; | ||
| 94 | |||
| 95 | gpio1: gpio@0800 { | ||
| 96 | compatible = "snps,dw-apb-gpio"; | ||
| 97 | reg = <0x0800 0x400>; | ||
| 98 | #address-cells = <1>; | ||
| 99 | #size-cells = <0>; | ||
| 100 | |||
| 101 | portb: gpio-port@1 { | ||
| 102 | compatible = "snps,dw-apb-gpio-port"; | ||
| 103 | gpio-controller; | ||
| 104 | #gpio-cells = <2>; | ||
| 105 | snps,nr-gpios = <8>; | ||
| 106 | reg = <0>; | ||
| 107 | interrupt-controller; | ||
| 108 | #interrupt-cells = <2>; | ||
| 109 | interrupts = <1>; | ||
| 110 | }; | ||
| 111 | }; | ||
| 112 | |||
| 113 | gpio2: gpio@0c00 { | ||
| 114 | compatible = "snps,dw-apb-gpio"; | ||
| 115 | reg = <0x0c00 0x400>; | ||
| 116 | #address-cells = <1>; | ||
| 117 | #size-cells = <0>; | ||
| 118 | |||
| 119 | portc: gpio-port@2 { | ||
| 120 | compatible = "snps,dw-apb-gpio-port"; | ||
| 121 | gpio-controller; | ||
| 122 | #gpio-cells = <2>; | ||
| 123 | snps,nr-gpios = <8>; | ||
| 124 | reg = <0>; | ||
| 125 | interrupt-controller; | ||
| 126 | #interrupt-cells = <2>; | ||
| 127 | interrupts = <2>; | ||
| 128 | }; | ||
| 129 | }; | ||
| 130 | |||
| 131 | gpio3: gpio@1000 { | ||
| 132 | compatible = "snps,dw-apb-gpio"; | ||
| 133 | reg = <0x1000 0x400>; | ||
| 134 | #address-cells = <1>; | ||
| 135 | #size-cells = <0>; | ||
| 136 | |||
| 137 | portd: gpio-port@3 { | ||
| 138 | compatible = "snps,dw-apb-gpio-port"; | ||
| 139 | gpio-controller; | ||
| 140 | #gpio-cells = <2>; | ||
| 141 | snps,nr-gpios = <8>; | ||
| 142 | reg = <0>; | ||
| 143 | interrupt-controller; | ||
| 144 | #interrupt-cells = <2>; | ||
| 145 | interrupts = <3>; | ||
| 146 | }; | ||
| 147 | }; | ||
| 148 | |||
| 90 | timer0: timer@2c00 { | 149 | timer0: timer@2c00 { |
| 91 | compatible = "snps,dw-apb-timer"; | 150 | compatible = "snps,dw-apb-timer"; |
| 92 | reg = <0x2c00 0x14>; | 151 | reg = <0x2c00 0x14>; |
| 93 | interrupts = <8>; | 152 | interrupts = <8>; |
| 94 | clocks = <&cfgclk>; | 153 | clocks = <&chip CLKID_CFG>; |
| 95 | clock-names = "timer"; | 154 | clock-names = "timer"; |
| 96 | status = "okay"; | 155 | status = "okay"; |
| 97 | }; | 156 | }; |
| @@ -100,7 +159,7 @@ | |||
| 100 | compatible = "snps,dw-apb-timer"; | 159 | compatible = "snps,dw-apb-timer"; |
| 101 | reg = <0x2c14 0x14>; | 160 | reg = <0x2c14 0x14>; |
| 102 | interrupts = <9>; | 161 | interrupts = <9>; |
| 103 | clocks = <&cfgclk>; | 162 | clocks = <&chip CLKID_CFG>; |
| 104 | clock-names = "timer"; | 163 | clock-names = "timer"; |
| 105 | status = "okay"; | 164 | status = "okay"; |
| 106 | }; | 165 | }; |
| @@ -109,7 +168,7 @@ | |||
| 109 | compatible = "snps,dw-apb-timer"; | 168 | compatible = "snps,dw-apb-timer"; |
| 110 | reg = <0x2c28 0x14>; | 169 | reg = <0x2c28 0x14>; |
| 111 | interrupts = <10>; | 170 | interrupts = <10>; |
| 112 | clocks = <&cfgclk>; | 171 | clocks = <&chip CLKID_CFG>; |
| 113 | clock-names = "timer"; | 172 | clock-names = "timer"; |
| 114 | status = "disabled"; | 173 | status = "disabled"; |
| 115 | }; | 174 | }; |
| @@ -118,7 +177,7 @@ | |||
| 118 | compatible = "snps,dw-apb-timer"; | 177 | compatible = "snps,dw-apb-timer"; |
| 119 | reg = <0x2c3c 0x14>; | 178 | reg = <0x2c3c 0x14>; |
| 120 | interrupts = <11>; | 179 | interrupts = <11>; |
| 121 | clocks = <&cfgclk>; | 180 | clocks = <&chip CLKID_CFG>; |
| 122 | clock-names = "timer"; | 181 | clock-names = "timer"; |
| 123 | status = "disabled"; | 182 | status = "disabled"; |
| 124 | }; | 183 | }; |
| @@ -127,7 +186,7 @@ | |||
| 127 | compatible = "snps,dw-apb-timer"; | 186 | compatible = "snps,dw-apb-timer"; |
| 128 | reg = <0x2c50 0x14>; | 187 | reg = <0x2c50 0x14>; |
| 129 | interrupts = <12>; | 188 | interrupts = <12>; |
| 130 | clocks = <&cfgclk>; | 189 | clocks = <&chip CLKID_CFG>; |
| 131 | clock-names = "timer"; | 190 | clock-names = "timer"; |
| 132 | status = "disabled"; | 191 | status = "disabled"; |
| 133 | }; | 192 | }; |
| @@ -136,7 +195,7 @@ | |||
| 136 | compatible = "snps,dw-apb-timer"; | 195 | compatible = "snps,dw-apb-timer"; |
| 137 | reg = <0x2c64 0x14>; | 196 | reg = <0x2c64 0x14>; |
| 138 | interrupts = <13>; | 197 | interrupts = <13>; |
| 139 | clocks = <&cfgclk>; | 198 | clocks = <&chip CLKID_CFG>; |
| 140 | clock-names = "timer"; | 199 | clock-names = "timer"; |
| 141 | status = "disabled"; | 200 | status = "disabled"; |
| 142 | }; | 201 | }; |
| @@ -145,7 +204,7 @@ | |||
| 145 | compatible = "snps,dw-apb-timer"; | 204 | compatible = "snps,dw-apb-timer"; |
| 146 | reg = <0x2c78 0x14>; | 205 | reg = <0x2c78 0x14>; |
| 147 | interrupts = <14>; | 206 | interrupts = <14>; |
| 148 | clocks = <&cfgclk>; | 207 | clocks = <&chip CLKID_CFG>; |
| 149 | clock-names = "timer"; | 208 | clock-names = "timer"; |
| 150 | status = "disabled"; | 209 | status = "disabled"; |
| 151 | }; | 210 | }; |
| @@ -154,7 +213,7 @@ | |||
| 154 | compatible = "snps,dw-apb-timer"; | 213 | compatible = "snps,dw-apb-timer"; |
| 155 | reg = <0x2c8c 0x14>; | 214 | reg = <0x2c8c 0x14>; |
| 156 | interrupts = <15>; | 215 | interrupts = <15>; |
| 157 | clocks = <&cfgclk>; | 216 | clocks = <&chip CLKID_CFG>; |
| 158 | clock-names = "timer"; | 217 | clock-names = "timer"; |
| 159 | status = "disabled"; | 218 | status = "disabled"; |
| 160 | }; | 219 | }; |
| @@ -169,6 +228,19 @@ | |||
| 169 | }; | 228 | }; |
| 170 | }; | 229 | }; |
| 171 | 230 | ||
| 231 | chip: chip-control@ea0000 { | ||
| 232 | compatible = "marvell,berlin2cd-chip-ctrl"; | ||
| 233 | #clock-cells = <1>; | ||
| 234 | reg = <0xea0000 0x400>; | ||
| 235 | clocks = <&refclk>; | ||
| 236 | clock-names = "refclk"; | ||
| 237 | |||
| 238 | uart0_pmux: uart0-pmux { | ||
| 239 | groups = "G6"; | ||
| 240 | function = "uart0"; | ||
| 241 | }; | ||
| 242 | }; | ||
| 243 | |||
| 172 | apb@fc0000 { | 244 | apb@fc0000 { |
| 173 | compatible = "simple-bus"; | 245 | compatible = "simple-bus"; |
| 174 | #address-cells = <1>; | 246 | #address-cells = <1>; |
| @@ -177,13 +249,45 @@ | |||
| 177 | ranges = <0 0xfc0000 0x10000>; | 249 | ranges = <0 0xfc0000 0x10000>; |
| 178 | interrupt-parent = <&sic>; | 250 | interrupt-parent = <&sic>; |
| 179 | 251 | ||
| 252 | sm_gpio1: gpio@5000 { | ||
| 253 | compatible = "snps,dw-apb-gpio"; | ||
| 254 | reg = <0x5000 0x400>; | ||
| 255 | #address-cells = <1>; | ||
| 256 | #size-cells = <0>; | ||
| 257 | |||
| 258 | portf: gpio-port@5 { | ||
| 259 | compatible = "snps,dw-apb-gpio-port"; | ||
| 260 | gpio-controller; | ||
| 261 | #gpio-cells = <2>; | ||
| 262 | snps,nr-gpios = <8>; | ||
| 263 | reg = <0>; | ||
| 264 | }; | ||
| 265 | }; | ||
| 266 | |||
| 267 | sm_gpio0: gpio@c000 { | ||
| 268 | compatible = "snps,dw-apb-gpio"; | ||
| 269 | reg = <0xc000 0x400>; | ||
| 270 | #address-cells = <1>; | ||
| 271 | #size-cells = <0>; | ||
| 272 | |||
| 273 | porte: gpio-port@4 { | ||
| 274 | compatible = "snps,dw-apb-gpio-port"; | ||
| 275 | gpio-controller; | ||
| 276 | #gpio-cells = <2>; | ||
| 277 | snps,nr-gpios = <8>; | ||
| 278 | reg = <0>; | ||
| 279 | }; | ||
| 280 | }; | ||
| 281 | |||
| 180 | uart0: serial@9000 { | 282 | uart0: serial@9000 { |
| 181 | compatible = "snps,dw-apb-uart"; | 283 | compatible = "snps,dw-apb-uart"; |
| 182 | reg = <0x9000 0x100>; | 284 | reg = <0x9000 0x100>; |
| 183 | reg-shift = <2>; | 285 | reg-shift = <2>; |
| 184 | reg-io-width = <1>; | 286 | reg-io-width = <1>; |
| 185 | interrupts = <8>; | 287 | interrupts = <8>; |
| 186 | clocks = <&smclk>; | 288 | clocks = <&refclk>; |
| 289 | pinctrl-0 = <&uart0_pmux>; | ||
| 290 | pinctrl-names = "default"; | ||
| 187 | status = "disabled"; | 291 | status = "disabled"; |
| 188 | }; | 292 | }; |
| 189 | 293 | ||
| @@ -193,10 +297,15 @@ | |||
| 193 | reg-shift = <2>; | 297 | reg-shift = <2>; |
| 194 | reg-io-width = <1>; | 298 | reg-io-width = <1>; |
| 195 | interrupts = <9>; | 299 | interrupts = <9>; |
| 196 | clocks = <&smclk>; | 300 | clocks = <&refclk>; |
| 197 | status = "disabled"; | 301 | status = "disabled"; |
| 198 | }; | 302 | }; |
| 199 | 303 | ||
| 304 | sysctrl: system-controller@d000 { | ||
| 305 | compatible = "marvell,berlin2cd-system-ctrl"; | ||
| 306 | reg = <0xd000 0x100>; | ||
| 307 | }; | ||
| 308 | |||
| 200 | sic: interrupt-controller@e000 { | 309 | sic: interrupt-controller@e000 { |
| 201 | compatible = "snps,dw-apb-ictl"; | 310 | compatible = "snps,dw-apb-ictl"; |
| 202 | reg = <0xe000 0x400>; | 311 | reg = <0xe000 0x400>; |
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts new file mode 100644 index 000000000000..995150f93795 --- /dev/null +++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /dts-v1/; | ||
| 10 | #include "berlin2q.dtsi" | ||
| 11 | |||
| 12 | / { | ||
| 13 | model = "Marvell BG2-Q DMP"; | ||
| 14 | compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin"; | ||
| 15 | |||
| 16 | memory { | ||
| 17 | device_type = "memory"; | ||
| 18 | reg = <0x00000000 0x80000000>; | ||
| 19 | }; | ||
| 20 | |||
| 21 | choosen { | ||
| 22 | bootargs = "console=ttyS0,115200 earlyprintk"; | ||
| 23 | }; | ||
| 24 | }; | ||
| 25 | |||
| 26 | &sdhci1 { | ||
| 27 | broken-cd; | ||
| 28 | sdhci,wp-inverted; | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
| 31 | |||
| 32 | &sdhci2 { | ||
| 33 | non-removable; | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | |||
| 37 | &uart0 { | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi new file mode 100644 index 000000000000..635a16a64cb4 --- /dev/null +++ b/arch/arm/boot/dts/berlin2q.dtsi | |||
| @@ -0,0 +1,363 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <dt-bindings/clock/berlin2q.h> | ||
| 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 11 | |||
| 12 | #include "skeleton.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "Marvell Armada 1500 pro (BG2-Q) SoC"; | ||
| 16 | compatible = "marvell,berlin2q", "marvell,berlin"; | ||
| 17 | |||
| 18 | cpus { | ||
| 19 | #address-cells = <1>; | ||
| 20 | #size-cells = <0>; | ||
| 21 | |||
| 22 | cpu@0 { | ||
| 23 | compatible = "arm,cortex-a9"; | ||
| 24 | device_type = "cpu"; | ||
| 25 | next-level-cache = <&l2>; | ||
| 26 | reg = <0>; | ||
| 27 | }; | ||
| 28 | |||
| 29 | cpu@1 { | ||
| 30 | compatible = "arm,cortex-a9"; | ||
| 31 | device_type = "cpu"; | ||
| 32 | next-level-cache = <&l2>; | ||
| 33 | reg = <1>; | ||
| 34 | }; | ||
| 35 | |||
| 36 | cpu@2 { | ||
| 37 | compatible = "arm,cortex-a9"; | ||
| 38 | device_type = "cpu"; | ||
| 39 | next-level-cache = <&l2>; | ||
| 40 | reg = <2>; | ||
| 41 | }; | ||
| 42 | |||
| 43 | cpu@3 { | ||
| 44 | compatible = "arm,cortex-a9"; | ||
| 45 | device_type = "cpu"; | ||
| 46 | next-level-cache = <&l2>; | ||
| 47 | reg = <3>; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | refclk: oscillator { | ||
| 52 | compatible = "fixed-clock"; | ||
| 53 | #clock-cells = <0>; | ||
| 54 | clock-frequency = <25000000>; | ||
| 55 | }; | ||
| 56 | |||
| 57 | soc { | ||
| 58 | compatible = "simple-bus"; | ||
| 59 | #address-cells = <1>; | ||
| 60 | #size-cells = <1>; | ||
| 61 | |||
| 62 | ranges = <0 0xf7000000 0x1000000>; | ||
| 63 | interrupt-parent = <&gic>; | ||
| 64 | |||
| 65 | sdhci0: sdhci@ab0000 { | ||
| 66 | compatible = "mrvl,pxav3-mmc"; | ||
| 67 | reg = <0xab0000 0x200>; | ||
| 68 | clocks = <&chip CLKID_SDIO1XIN>; | ||
| 69 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | ||
| 70 | status = "disabled"; | ||
| 71 | }; | ||
| 72 | |||
| 73 | sdhci1: sdhci@ab0800 { | ||
| 74 | compatible = "mrvl,pxav3-mmc"; | ||
| 75 | reg = <0xab0800 0x200>; | ||
| 76 | clocks = <&chip CLKID_SDIO1XIN>; | ||
| 77 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | ||
| 78 | status = "disabled"; | ||
| 79 | }; | ||
| 80 | |||
| 81 | sdhci2: sdhci@ab1000 { | ||
| 82 | compatible = "mrvl,pxav3-mmc"; | ||
| 83 | reg = <0xab1000 0x200>; | ||
| 84 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | ||
| 85 | clocks = <&chip CLKID_SDIO1XIN>; | ||
| 86 | status = "disabled"; | ||
| 87 | }; | ||
| 88 | |||
| 89 | l2: l2-cache-controller@ac0000 { | ||
| 90 | compatible = "arm,pl310-cache"; | ||
| 91 | reg = <0xac0000 0x1000>; | ||
| 92 | cache-level = <2>; | ||
| 93 | }; | ||
| 94 | |||
| 95 | scu: snoop-control-unit@ad0000 { | ||
| 96 | compatible = "arm,cortex-a9-scu"; | ||
| 97 | reg = <0xad0000 0x58>; | ||
| 98 | }; | ||
| 99 | |||
| 100 | local-timer@ad0600 { | ||
| 101 | compatible = "arm,cortex-a9-twd-timer"; | ||
| 102 | reg = <0xad0600 0x20>; | ||
| 103 | clocks = <&chip CLKID_TWD>; | ||
| 104 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; | ||
| 105 | }; | ||
| 106 | |||
| 107 | gic: interrupt-controller@ad1000 { | ||
| 108 | compatible = "arm,cortex-a9-gic"; | ||
| 109 | reg = <0xad1000 0x1000>, <0xad0100 0x100>; | ||
| 110 | interrupt-controller; | ||
| 111 | #interrupt-cells = <3>; | ||
| 112 | }; | ||
| 113 | |||
| 114 | apb@e80000 { | ||
| 115 | compatible = "simple-bus"; | ||
| 116 | #address-cells = <1>; | ||
| 117 | #size-cells = <1>; | ||
| 118 | |||
| 119 | ranges = <0 0xe80000 0x10000>; | ||
| 120 | interrupt-parent = <&aic>; | ||
| 121 | |||
| 122 | gpio0: gpio@0400 { | ||
| 123 | compatible = "snps,dw-apb-gpio"; | ||
| 124 | reg = <0x0400 0x400>; | ||
| 125 | #address-cells = <1>; | ||
| 126 | #size-cells = <0>; | ||
| 127 | |||
| 128 | porta: gpio-port@0 { | ||
| 129 | compatible = "snps,dw-apb-gpio-port"; | ||
| 130 | gpio-controller; | ||
| 131 | #gpio-cells = <2>; | ||
| 132 | snps,nr-gpios = <32>; | ||
| 133 | reg = <0>; | ||
| 134 | interrupt-controller; | ||
| 135 | #interrupt-cells = <2>; | ||
| 136 | interrupts = <0>; | ||
| 137 | }; | ||
| 138 | }; | ||
| 139 | |||
| 140 | gpio1: gpio@0800 { | ||
| 141 | compatible = "snps,dw-apb-gpio"; | ||
| 142 | reg = <0x0800 0x400>; | ||
| 143 | #address-cells = <1>; | ||
| 144 | #size-cells = <0>; | ||
| 145 | |||
| 146 | portb: gpio-port@1 { | ||
| 147 | compatible = "snps,dw-apb-gpio-port"; | ||
| 148 | gpio-controller; | ||
| 149 | #gpio-cells = <2>; | ||
| 150 | snps,nr-gpios = <32>; | ||
| 151 | reg = <0>; | ||
| 152 | interrupt-controller; | ||
| 153 | #interrupt-cells = <2>; | ||
| 154 | interrupts = <1>; | ||
| 155 | }; | ||
| 156 | }; | ||
| 157 | |||
| 158 | gpio2: gpio@0c00 { | ||
| 159 | compatible = "snps,dw-apb-gpio"; | ||
| 160 | reg = <0x0c00 0x400>; | ||
| 161 | #address-cells = <1>; | ||
| 162 | #size-cells = <0>; | ||
| 163 | |||
| 164 | portc: gpio-port@2 { | ||
| 165 | compatible = "snps,dw-apb-gpio-port"; | ||
| 166 | gpio-controller; | ||
| 167 | #gpio-cells = <2>; | ||
| 168 | snps,nr-gpios = <32>; | ||
| 169 | reg = <0>; | ||
| 170 | interrupt-controller; | ||
| 171 | #interrupt-cells = <2>; | ||
| 172 | interrupts = <2>; | ||
| 173 | }; | ||
| 174 | }; | ||
| 175 | |||
| 176 | gpio3: gpio@1000 { | ||
| 177 | compatible = "snps,dw-apb-gpio"; | ||
| 178 | reg = <0x1000 0x400>; | ||
| 179 | #address-cells = <1>; | ||
| 180 | #size-cells = <0>; | ||
| 181 | |||
| 182 | portd: gpio-port@3 { | ||
| 183 | compatible = "snps,dw-apb-gpio-port"; | ||
| 184 | gpio-controller; | ||
| 185 | #gpio-cells = <2>; | ||
| 186 | snps,nr-gpios = <32>; | ||
| 187 | reg = <0>; | ||
| 188 | interrupt-controller; | ||
| 189 | #interrupt-cells = <2>; | ||
| 190 | interrupts = <3>; | ||
| 191 | }; | ||
| 192 | }; | ||
| 193 | |||
| 194 | timer0: timer@2c00 { | ||
| 195 | compatible = "snps,dw-apb-timer"; | ||
| 196 | reg = <0x2c00 0x14>; | ||
| 197 | clocks = <&chip CLKID_CFG>; | ||
| 198 | clock-names = "timer"; | ||
| 199 | interrupts = <8>; | ||
| 200 | }; | ||
| 201 | |||
| 202 | timer1: timer@2c14 { | ||
| 203 | compatible = "snps,dw-apb-timer"; | ||
| 204 | reg = <0x2c14 0x14>; | ||
| 205 | clocks = <&chip CLKID_CFG>; | ||
| 206 | clock-names = "timer"; | ||
| 207 | status = "disabled"; | ||
| 208 | }; | ||
| 209 | |||
| 210 | timer2: timer@2c28 { | ||
| 211 | compatible = "snps,dw-apb-timer"; | ||
| 212 | reg = <0x2c28 0x14>; | ||
| 213 | clocks = <&chip CLKID_CFG>; | ||
| 214 | clock-names = "timer"; | ||
| 215 | status = "disabled"; | ||
| 216 | }; | ||
| 217 | |||
| 218 | timer3: timer@2c3c { | ||
| 219 | compatible = "snps,dw-apb-timer"; | ||
| 220 | reg = <0x2c3c 0x14>; | ||
| 221 | clocks = <&chip CLKID_CFG>; | ||
| 222 | clock-names = "timer"; | ||
| 223 | status = "disabled"; | ||
| 224 | }; | ||
| 225 | |||
| 226 | timer4: timer@2c50 { | ||
| 227 | compatible = "snps,dw-apb-timer"; | ||
| 228 | reg = <0x2c50 0x14>; | ||
| 229 | clocks = <&chip CLKID_CFG>; | ||
| 230 | clock-names = "timer"; | ||
| 231 | status = "disabled"; | ||
| 232 | }; | ||
| 233 | |||
| 234 | timer5: timer@2c64 { | ||
| 235 | compatible = "snps,dw-apb-timer"; | ||
| 236 | reg = <0x2c64 0x14>; | ||
| 237 | clocks = <&chip CLKID_CFG>; | ||
| 238 | clock-names = "timer"; | ||
| 239 | status = "disabled"; | ||
| 240 | }; | ||
| 241 | |||
| 242 | timer6: timer@2c78 { | ||
| 243 | compatible = "snps,dw-apb-timer"; | ||
| 244 | reg = <0x2c78 0x14>; | ||
| 245 | clocks = <&chip CLKID_CFG>; | ||
| 246 | clock-names = "timer"; | ||
| 247 | status = "disabled"; | ||
| 248 | }; | ||
| 249 | |||
| 250 | timer7: timer@2c8c { | ||
| 251 | compatible = "snps,dw-apb-timer"; | ||
| 252 | reg = <0x2c8c 0x14>; | ||
| 253 | clocks = <&chip CLKID_CFG>; | ||
| 254 | clock-names = "timer"; | ||
| 255 | status = "disabled"; | ||
| 256 | }; | ||
| 257 | |||
| 258 | aic: interrupt-controller@3800 { | ||
| 259 | compatible = "snps,dw-apb-ictl"; | ||
| 260 | reg = <0x3800 0x30>; | ||
| 261 | interrupt-controller; | ||
| 262 | #interrupt-cells = <1>; | ||
| 263 | interrupt-parent = <&gic>; | ||
| 264 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | ||
| 265 | }; | ||
| 266 | |||
| 267 | gpio4: gpio@5000 { | ||
| 268 | compatible = "snps,dw-apb-gpio"; | ||
| 269 | reg = <0x5000 0x400>; | ||
| 270 | #address-cells = <1>; | ||
| 271 | #size-cells = <0>; | ||
| 272 | |||
| 273 | porte: gpio-port@4 { | ||
| 274 | compatible = "snps,dw-apb-gpio-port"; | ||
| 275 | gpio-controller; | ||
| 276 | #gpio-cells = <2>; | ||
| 277 | snps,nr-gpios = <32>; | ||
| 278 | reg = <0>; | ||
| 279 | }; | ||
| 280 | }; | ||
| 281 | |||
| 282 | gpio5: gpio@c000 { | ||
| 283 | compatible = "snps,dw-apb-gpio"; | ||
| 284 | reg = <0xc000 0x400>; | ||
| 285 | #address-cells = <1>; | ||
| 286 | #size-cells = <0>; | ||
| 287 | |||
| 288 | portf: gpio-port@5 { | ||
| 289 | compatible = "snps,dw-apb-gpio-port"; | ||
| 290 | gpio-controller; | ||
| 291 | #gpio-cells = <2>; | ||
| 292 | snps,nr-gpios = <32>; | ||
| 293 | reg = <0>; | ||
| 294 | }; | ||
| 295 | }; | ||
| 296 | }; | ||
| 297 | |||
| 298 | chip: chip-control@ea0000 { | ||
| 299 | compatible = "marvell,berlin2q-chip-ctrl"; | ||
| 300 | #clock-cells = <1>; | ||
| 301 | reg = <0xea0000 0x400>, <0xdd0170 0x10>; | ||
| 302 | clocks = <&refclk>; | ||
| 303 | clock-names = "refclk"; | ||
| 304 | }; | ||
| 305 | |||
| 306 | apb@fc0000 { | ||
| 307 | compatible = "simple-bus"; | ||
| 308 | #address-cells = <1>; | ||
| 309 | #size-cells = <1>; | ||
| 310 | |||
| 311 | ranges = <0 0xfc0000 0x10000>; | ||
| 312 | interrupt-parent = <&sic>; | ||
| 313 | |||
| 314 | uart0: uart@9000 { | ||
| 315 | compatible = "snps,dw-apb-uart"; | ||
| 316 | reg = <0x9000 0x100>; | ||
| 317 | interrupt-parent = <&sic>; | ||
| 318 | interrupts = <8>; | ||
| 319 | clocks = <&refclk>; | ||
| 320 | reg-shift = <2>; | ||
| 321 | pinctrl-0 = <&uart0_pmux>; | ||
| 322 | pinctrl-names = "default"; | ||
| 323 | status = "disabled"; | ||
| 324 | }; | ||
| 325 | |||
| 326 | uart1: uart@a000 { | ||
| 327 | compatible = "snps,dw-apb-uart"; | ||
| 328 | reg = <0xa000 0x100>; | ||
| 329 | interrupt-parent = <&sic>; | ||
| 330 | interrupts = <9>; | ||
| 331 | clocks = <&refclk>; | ||
| 332 | reg-shift = <2>; | ||
| 333 | pinctrl-0 = <&uart1_pmux>; | ||
| 334 | pinctrl-names = "default"; | ||
| 335 | status = "disabled"; | ||
| 336 | }; | ||
| 337 | |||
| 338 | sysctrl: pin-controller@d000 { | ||
| 339 | compatible = "marvell,berlin2q-system-ctrl"; | ||
| 340 | reg = <0xd000 0x100>; | ||
| 341 | |||
| 342 | uart0_pmux: uart0-pmux { | ||
| 343 | groups = "GSM12"; | ||
| 344 | function = "uart0"; | ||
| 345 | }; | ||
| 346 | |||
| 347 | uart1_pmux: uart1-pmux { | ||
| 348 | groups = "GSM14"; | ||
| 349 | function = "uart1"; | ||
| 350 | }; | ||
| 351 | }; | ||
| 352 | |||
| 353 | sic: interrupt-controller@e000 { | ||
| 354 | compatible = "snps,dw-apb-ictl"; | ||
| 355 | reg = <0xe000 0x30>; | ||
| 356 | interrupt-controller; | ||
| 357 | #interrupt-cells = <1>; | ||
| 358 | interrupt-parent = <&gic>; | ||
| 359 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | ||
| 360 | }; | ||
| 361 | }; | ||
| 362 | }; | ||
| 363 | }; | ||
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 5babba0a3a75..4adc28039c30 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts | |||
| @@ -7,11 +7,11 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | #include "dra7.dtsi" | 10 | #include "dra74x.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "TI DRA7"; | 13 | model = "TI DRA742"; |
| 14 | compatible = "ti,dra7-evm", "ti,dra752", "ti,dra7"; | 14 | compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; |
| 15 | 15 | ||
| 16 | memory { | 16 | memory { |
| 17 | device_type = "memory"; | 17 | device_type = "memory"; |
| @@ -93,6 +93,64 @@ | |||
| 93 | 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ | 93 | 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ |
| 94 | >; | 94 | >; |
| 95 | }; | 95 | }; |
| 96 | |||
| 97 | qspi1_pins: pinmux_qspi1_pins { | ||
| 98 | pinctrl-single,pins = < | ||
| 99 | 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */ | ||
| 100 | 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */ | ||
| 101 | 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ | ||
| 102 | 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ | ||
| 103 | 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ | ||
| 104 | 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ | ||
| 105 | 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ | ||
| 106 | 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ | ||
| 107 | 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ | ||
| 108 | 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ | ||
| 109 | >; | ||
| 110 | }; | ||
| 111 | |||
| 112 | usb1_pins: pinmux_usb1_pins { | ||
| 113 | pinctrl-single,pins = < | ||
| 114 | 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ | ||
| 115 | >; | ||
| 116 | }; | ||
| 117 | |||
| 118 | usb2_pins: pinmux_usb2_pins { | ||
| 119 | pinctrl-single,pins = < | ||
| 120 | 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ | ||
| 121 | >; | ||
| 122 | }; | ||
| 123 | |||
| 124 | nand_flash_x16: nand_flash_x16 { | ||
| 125 | /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch | ||
| 126 | * So NAND flash requires following switch settings: | ||
| 127 | * SW5.9 (GPMC_WPN) = LOW | ||
| 128 | * SW5.1 (NAND_BOOTn) = HIGH */ | ||
| 129 | pinctrl-single,pins = < | ||
| 130 | 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ | ||
| 131 | 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ | ||
| 132 | 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ | ||
| 133 | 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ | ||
| 134 | 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ | ||
| 135 | 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ | ||
| 136 | 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ | ||
| 137 | 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ | ||
| 138 | 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ | ||
| 139 | 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ | ||
| 140 | 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ | ||
| 141 | 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ | ||
| 142 | 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ | ||
| 143 | 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ | ||
| 144 | 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ | ||
| 145 | 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ | ||
| 146 | 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ | ||
| 147 | 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ | ||
| 148 | 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */ | ||
| 149 | 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ | ||
| 150 | 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ | ||
| 151 | 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ | ||
| 152 | >; | ||
| 153 | }; | ||
| 96 | }; | 154 | }; |
| 97 | 155 | ||
| 98 | &i2c1 { | 156 | &i2c1 { |
| @@ -273,3 +331,167 @@ | |||
| 273 | &cpu0 { | 331 | &cpu0 { |
| 274 | cpu0-supply = <&smps123_reg>; | 332 | cpu0-supply = <&smps123_reg>; |
| 275 | }; | 333 | }; |
| 334 | |||
| 335 | &qspi { | ||
| 336 | status = "okay"; | ||
| 337 | pinctrl-names = "default"; | ||
| 338 | pinctrl-0 = <&qspi1_pins>; | ||
| 339 | |||
| 340 | spi-max-frequency = <48000000>; | ||
| 341 | m25p80@0 { | ||
| 342 | compatible = "s25fl256s1"; | ||
| 343 | spi-max-frequency = <48000000>; | ||
| 344 | reg = <0>; | ||
| 345 | spi-tx-bus-width = <1>; | ||
| 346 | spi-rx-bus-width = <4>; | ||
| 347 | spi-cpol; | ||
| 348 | spi-cpha; | ||
| 349 | #address-cells = <1>; | ||
| 350 | #size-cells = <1>; | ||
| 351 | |||
| 352 | /* MTD partition table. | ||
| 353 | * The ROM checks the first four physical blocks | ||
| 354 | * for a valid file to boot and the flash here is | ||
| 355 | * 64KiB block size. | ||
| 356 | */ | ||
| 357 | partition@0 { | ||
| 358 | label = "QSPI.SPL"; | ||
| 359 | reg = <0x00000000 0x000010000>; | ||
| 360 | }; | ||
| 361 | partition@1 { | ||
| 362 | label = "QSPI.SPL.backup1"; | ||
| 363 | reg = <0x00010000 0x00010000>; | ||
| 364 | }; | ||
| 365 | partition@2 { | ||
| 366 | label = "QSPI.SPL.backup2"; | ||
| 367 | reg = <0x00020000 0x00010000>; | ||
| 368 | }; | ||
| 369 | partition@3 { | ||
| 370 | label = "QSPI.SPL.backup3"; | ||
| 371 | reg = <0x00030000 0x00010000>; | ||
| 372 | }; | ||
| 373 | partition@4 { | ||
| 374 | label = "QSPI.u-boot"; | ||
| 375 | reg = <0x00040000 0x00100000>; | ||
| 376 | }; | ||
| 377 | partition@5 { | ||
| 378 | label = "QSPI.u-boot-spl-os"; | ||
| 379 | reg = <0x00140000 0x00010000>; | ||
| 380 | }; | ||
| 381 | partition@6 { | ||
| 382 | label = "QSPI.u-boot-env"; | ||
| 383 | reg = <0x00150000 0x00010000>; | ||
| 384 | }; | ||
| 385 | partition@7 { | ||
| 386 | label = "QSPI.u-boot-env.backup1"; | ||
| 387 | reg = <0x00160000 0x0010000>; | ||
| 388 | }; | ||
| 389 | partition@8 { | ||
| 390 | label = "QSPI.kernel"; | ||
| 391 | reg = <0x00170000 0x0800000>; | ||
| 392 | }; | ||
| 393 | partition@9 { | ||
| 394 | label = "QSPI.file-system"; | ||
| 395 | reg = <0x00970000 0x01690000>; | ||
| 396 | }; | ||
| 397 | }; | ||
| 398 | }; | ||
| 399 | |||
| 400 | &usb1 { | ||
| 401 | dr_mode = "peripheral"; | ||
| 402 | pinctrl-names = "default"; | ||
| 403 | pinctrl-0 = <&usb1_pins>; | ||
| 404 | }; | ||
| 405 | |||
| 406 | &usb2 { | ||
| 407 | dr_mode = "host"; | ||
| 408 | pinctrl-names = "default"; | ||
| 409 | pinctrl-0 = <&usb2_pins>; | ||
| 410 | }; | ||
| 411 | |||
| 412 | &elm { | ||
| 413 | status = "okay"; | ||
| 414 | }; | ||
| 415 | |||
| 416 | &gpmc { | ||
| 417 | status = "okay"; | ||
| 418 | pinctrl-names = "default"; | ||
| 419 | pinctrl-0 = <&nand_flash_x16>; | ||
| 420 | ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ | ||
| 421 | nand@0,0 { | ||
| 422 | reg = <0 0 4>; /* device IO registers */ | ||
| 423 | ti,nand-ecc-opt = "bch8"; | ||
| 424 | ti,elm-id = <&elm>; | ||
| 425 | nand-bus-width = <16>; | ||
| 426 | gpmc,device-width = <2>; | ||
| 427 | gpmc,sync-clk-ps = <0>; | ||
| 428 | gpmc,cs-on-ns = <0>; | ||
| 429 | gpmc,cs-rd-off-ns = <40>; | ||
| 430 | gpmc,cs-wr-off-ns = <40>; | ||
| 431 | gpmc,adv-on-ns = <0>; | ||
| 432 | gpmc,adv-rd-off-ns = <30>; | ||
| 433 | gpmc,adv-wr-off-ns = <30>; | ||
| 434 | gpmc,we-on-ns = <5>; | ||
| 435 | gpmc,we-off-ns = <25>; | ||
| 436 | gpmc,oe-on-ns = <2>; | ||
| 437 | gpmc,oe-off-ns = <20>; | ||
| 438 | gpmc,access-ns = <20>; | ||
| 439 | gpmc,wr-access-ns = <40>; | ||
| 440 | gpmc,rd-cycle-ns = <40>; | ||
| 441 | gpmc,wr-cycle-ns = <40>; | ||
| 442 | gpmc,wait-pin = <0>; | ||
| 443 | gpmc,wait-on-read; | ||
| 444 | gpmc,wait-on-write; | ||
| 445 | gpmc,bus-turnaround-ns = <0>; | ||
| 446 | gpmc,cycle2cycle-delay-ns = <0>; | ||
| 447 | gpmc,clk-activation-ns = <0>; | ||
| 448 | gpmc,wait-monitoring-ns = <0>; | ||
| 449 | gpmc,wr-data-mux-bus-ns = <0>; | ||
| 450 | /* MTD partition table */ | ||
| 451 | /* All SPL-* partitions are sized to minimal length | ||
| 452 | * which can be independently programmable. For | ||
| 453 | * NAND flash this is equal to size of erase-block */ | ||
| 454 | #address-cells = <1>; | ||
| 455 | #size-cells = <1>; | ||
| 456 | partition@0 { | ||
| 457 | label = "NAND.SPL"; | ||
| 458 | reg = <0x00000000 0x000020000>; | ||
| 459 | }; | ||
| 460 | partition@1 { | ||
| 461 | label = "NAND.SPL.backup1"; | ||
| 462 | reg = <0x00020000 0x00020000>; | ||
| 463 | }; | ||
| 464 | partition@2 { | ||
| 465 | label = "NAND.SPL.backup2"; | ||
| 466 | reg = <0x00040000 0x00020000>; | ||
| 467 | }; | ||
| 468 | partition@3 { | ||
| 469 | label = "NAND.SPL.backup3"; | ||
| 470 | reg = <0x00060000 0x00020000>; | ||
| 471 | }; | ||
| 472 | partition@4 { | ||
| 473 | label = "NAND.u-boot-spl-os"; | ||
| 474 | reg = <0x00080000 0x00040000>; | ||
| 475 | }; | ||
| 476 | partition@5 { | ||
| 477 | label = "NAND.u-boot"; | ||
| 478 | reg = <0x000c0000 0x00100000>; | ||
| 479 | }; | ||
| 480 | partition@6 { | ||
| 481 | label = "NAND.u-boot-env"; | ||
| 482 | reg = <0x001c0000 0x00020000>; | ||
| 483 | }; | ||
| 484 | partition@7 { | ||
| 485 | label = "NAND.u-boot-env"; | ||
| 486 | reg = <0x001e0000 0x00020000>; | ||
| 487 | }; | ||
| 488 | partition@8 { | ||
| 489 | label = "NAND.kernel"; | ||
| 490 | reg = <0x00200000 0x00800000>; | ||
| 491 | }; | ||
| 492 | partition@9 { | ||
| 493 | label = "NAND.file-system"; | ||
| 494 | reg = <0x00a00000 0x0f600000>; | ||
| 495 | }; | ||
| 496 | }; | ||
| 497 | }; | ||
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 149b55099935..c29945e07c5a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi | |||
| @@ -33,33 +33,6 @@ | |||
| 33 | serial5 = &uart6; | 33 | serial5 = &uart6; |
| 34 | }; | 34 | }; |
| 35 | 35 | ||
| 36 | cpus { | ||
| 37 | #address-cells = <1>; | ||
| 38 | #size-cells = <0>; | ||
| 39 | |||
| 40 | cpu0: cpu@0 { | ||
| 41 | device_type = "cpu"; | ||
| 42 | compatible = "arm,cortex-a15"; | ||
| 43 | reg = <0>; | ||
| 44 | |||
| 45 | operating-points = < | ||
| 46 | /* kHz uV */ | ||
| 47 | 1000000 1060000 | ||
| 48 | 1176000 1160000 | ||
| 49 | >; | ||
| 50 | |||
| 51 | clocks = <&dpll_mpu_ck>; | ||
| 52 | clock-names = "cpu"; | ||
| 53 | |||
| 54 | clock-latency = <300000>; /* From omap-cpufreq driver */ | ||
| 55 | }; | ||
| 56 | cpu@1 { | ||
| 57 | device_type = "cpu"; | ||
| 58 | compatible = "arm,cortex-a15"; | ||
| 59 | reg = <1>; | ||
| 60 | }; | ||
| 61 | }; | ||
| 62 | |||
| 63 | timer { | 36 | timer { |
| 64 | compatible = "arm,armv7-timer"; | 37 | compatible = "arm,armv7-timer"; |
| 65 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | 38 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| @@ -99,13 +72,13 @@ | |||
| 99 | * hierarchy. | 72 | * hierarchy. |
| 100 | */ | 73 | */ |
| 101 | ocp { | 74 | ocp { |
| 102 | compatible = "ti,omap4-l3-noc", "simple-bus"; | 75 | compatible = "ti,dra7-l3-noc", "simple-bus"; |
| 103 | #address-cells = <1>; | 76 | #address-cells = <1>; |
| 104 | #size-cells = <1>; | 77 | #size-cells = <1>; |
| 105 | ranges; | 78 | ranges; |
| 106 | ti,hwmods = "l3_main_1", "l3_main_2"; | 79 | ti,hwmods = "l3_main_1", "l3_main_2"; |
| 107 | reg = <0x44000000 0x2000>, | 80 | reg = <0x44000000 0x1000000>, |
| 108 | <0x44800000 0x3000>; | 81 | <0x45000000 0x1000>; |
| 109 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | 82 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 110 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | 83 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| 111 | 84 | ||
| @@ -789,6 +762,228 @@ | |||
| 789 | dma-names = "tx0", "rx0"; | 762 | dma-names = "tx0", "rx0"; |
| 790 | status = "disabled"; | 763 | status = "disabled"; |
| 791 | }; | 764 | }; |
| 765 | |||
| 766 | qspi: qspi@4b300000 { | ||
| 767 | compatible = "ti,dra7xxx-qspi"; | ||
| 768 | reg = <0x4b300000 0x100>; | ||
| 769 | reg-names = "qspi_base"; | ||
| 770 | #address-cells = <1>; | ||
| 771 | #size-cells = <0>; | ||
| 772 | ti,hwmods = "qspi"; | ||
| 773 | clocks = <&qspi_gfclk_div>; | ||
| 774 | clock-names = "fck"; | ||
| 775 | num-cs = <4>; | ||
| 776 | interrupts = <0 343 0x4>; | ||
| 777 | status = "disabled"; | ||
| 778 | }; | ||
| 779 | |||
| 780 | omap_control_sata: control-phy@4a002374 { | ||
| 781 | compatible = "ti,control-phy-pipe3"; | ||
| 782 | reg = <0x4a002374 0x4>; | ||
| 783 | reg-names = "power"; | ||
| 784 | clocks = <&sys_clkin1>; | ||
| 785 | clock-names = "sysclk"; | ||
| 786 | }; | ||
| 787 | |||
| 788 | /* OCP2SCP3 */ | ||
| 789 | ocp2scp@4a090000 { | ||
| 790 | compatible = "ti,omap-ocp2scp"; | ||
| 791 | #address-cells = <1>; | ||
| 792 | #size-cells = <1>; | ||
| 793 | ranges; | ||
| 794 | reg = <0x4a090000 0x20>; | ||
| 795 | ti,hwmods = "ocp2scp3"; | ||
| 796 | sata_phy: phy@4A096000 { | ||
| 797 | compatible = "ti,phy-pipe3-sata"; | ||
| 798 | reg = <0x4A096000 0x80>, /* phy_rx */ | ||
| 799 | <0x4A096400 0x64>, /* phy_tx */ | ||
| 800 | <0x4A096800 0x40>; /* pll_ctrl */ | ||
| 801 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | ||
| 802 | ctrl-module = <&omap_control_sata>; | ||
| 803 | clocks = <&sys_clkin1>; | ||
| 804 | clock-names = "sysclk"; | ||
| 805 | #phy-cells = <0>; | ||
| 806 | }; | ||
| 807 | }; | ||
| 808 | |||
| 809 | sata: sata@4a141100 { | ||
| 810 | compatible = "snps,dwc-ahci"; | ||
| 811 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; | ||
| 812 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | ||
| 813 | phys = <&sata_phy>; | ||
| 814 | phy-names = "sata-phy"; | ||
| 815 | clocks = <&sata_ref_clk>; | ||
| 816 | ti,hwmods = "sata"; | ||
| 817 | }; | ||
| 818 | |||
| 819 | omap_control_usb2phy1: control-phy@4a002300 { | ||
| 820 | compatible = "ti,control-phy-usb2"; | ||
| 821 | reg = <0x4a002300 0x4>; | ||
| 822 | reg-names = "power"; | ||
| 823 | }; | ||
| 824 | |||
| 825 | omap_control_usb3phy1: control-phy@4a002370 { | ||
| 826 | compatible = "ti,control-phy-pipe3"; | ||
| 827 | reg = <0x4a002370 0x4>; | ||
| 828 | reg-names = "power"; | ||
| 829 | }; | ||
| 830 | |||
| 831 | omap_control_usb2phy2: control-phy@0x4a002e74 { | ||
| 832 | compatible = "ti,control-phy-usb2-dra7"; | ||
| 833 | reg = <0x4a002e74 0x4>; | ||
| 834 | reg-names = "power"; | ||
| 835 | }; | ||
| 836 | |||
| 837 | /* OCP2SCP1 */ | ||
| 838 | ocp2scp@4a080000 { | ||
| 839 | compatible = "ti,omap-ocp2scp"; | ||
| 840 | #address-cells = <1>; | ||
| 841 | #size-cells = <1>; | ||
| 842 | ranges; | ||
| 843 | reg = <0x4a080000 0x20>; | ||
| 844 | ti,hwmods = "ocp2scp1"; | ||
| 845 | |||
| 846 | usb2_phy1: phy@4a084000 { | ||
| 847 | compatible = "ti,omap-usb2"; | ||
| 848 | reg = <0x4a084000 0x400>; | ||
| 849 | ctrl-module = <&omap_control_usb2phy1>; | ||
| 850 | clocks = <&usb_phy1_always_on_clk32k>, | ||
| 851 | <&usb_otg_ss1_refclk960m>; | ||
| 852 | clock-names = "wkupclk", | ||
| 853 | "refclk"; | ||
| 854 | #phy-cells = <0>; | ||
| 855 | }; | ||
| 856 | |||
| 857 | usb2_phy2: phy@4a085000 { | ||
| 858 | compatible = "ti,omap-usb2"; | ||
| 859 | reg = <0x4a085000 0x400>; | ||
| 860 | ctrl-module = <&omap_control_usb2phy2>; | ||
| 861 | clocks = <&usb_phy2_always_on_clk32k>, | ||
| 862 | <&usb_otg_ss2_refclk960m>; | ||
| 863 | clock-names = "wkupclk", | ||
| 864 | "refclk"; | ||
| 865 | #phy-cells = <0>; | ||
| 866 | }; | ||
| 867 | |||
| 868 | usb3_phy1: phy@4a084400 { | ||
| 869 | compatible = "ti,omap-usb3"; | ||
| 870 | reg = <0x4a084400 0x80>, | ||
| 871 | <0x4a084800 0x64>, | ||
| 872 | <0x4a084c00 0x40>; | ||
| 873 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | ||
| 874 | ctrl-module = <&omap_control_usb3phy1>; | ||
| 875 | clocks = <&usb_phy3_always_on_clk32k>, | ||
| 876 | <&sys_clkin1>, | ||
| 877 | <&usb_otg_ss1_refclk960m>; | ||
| 878 | clock-names = "wkupclk", | ||
| 879 | "sysclk", | ||
| 880 | "refclk"; | ||
| 881 | #phy-cells = <0>; | ||
| 882 | }; | ||
| 883 | }; | ||
| 884 | |||
| 885 | omap_dwc3_1@48880000 { | ||
| 886 | compatible = "ti,dwc3"; | ||
| 887 | ti,hwmods = "usb_otg_ss1"; | ||
| 888 | reg = <0x48880000 0x10000>; | ||
| 889 | interrupts = <0 77 4>; | ||
| 890 | #address-cells = <1>; | ||
| 891 | #size-cells = <1>; | ||
| 892 | utmi-mode = <2>; | ||
| 893 | ranges; | ||
| 894 | usb1: usb@48890000 { | ||
| 895 | compatible = "snps,dwc3"; | ||
| 896 | reg = <0x48890000 0x17000>; | ||
| 897 | interrupts = <0 76 4>; | ||
| 898 | phys = <&usb2_phy1>, <&usb3_phy1>; | ||
| 899 | phy-names = "usb2-phy", "usb3-phy"; | ||
| 900 | tx-fifo-resize; | ||
| 901 | maximum-speed = "super-speed"; | ||
| 902 | dr_mode = "otg"; | ||
| 903 | }; | ||
| 904 | }; | ||
| 905 | |||
| 906 | omap_dwc3_2@488c0000 { | ||
| 907 | compatible = "ti,dwc3"; | ||
| 908 | ti,hwmods = "usb_otg_ss2"; | ||
| 909 | reg = <0x488c0000 0x10000>; | ||
| 910 | interrupts = <0 92 4>; | ||
| 911 | #address-cells = <1>; | ||
| 912 | #size-cells = <1>; | ||
| 913 | utmi-mode = <2>; | ||
| 914 | ranges; | ||
| 915 | usb2: usb@488d0000 { | ||
| 916 | compatible = "snps,dwc3"; | ||
| 917 | reg = <0x488d0000 0x17000>; | ||
| 918 | interrupts = <0 78 4>; | ||
| 919 | phys = <&usb2_phy2>; | ||
| 920 | phy-names = "usb2-phy"; | ||
| 921 | tx-fifo-resize; | ||
| 922 | maximum-speed = "high-speed"; | ||
| 923 | dr_mode = "otg"; | ||
| 924 | }; | ||
| 925 | }; | ||
| 926 | |||
| 927 | /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ | ||
| 928 | omap_dwc3_3@48900000 { | ||
| 929 | compatible = "ti,dwc3"; | ||
| 930 | ti,hwmods = "usb_otg_ss3"; | ||
| 931 | reg = <0x48900000 0x10000>; | ||
| 932 | /* interrupts = <0 TBD 4>; */ | ||
| 933 | #address-cells = <1>; | ||
| 934 | #size-cells = <1>; | ||
| 935 | utmi-mode = <2>; | ||
| 936 | ranges; | ||
| 937 | status = "disabled"; | ||
| 938 | usb3: usb@48910000 { | ||
| 939 | compatible = "snps,dwc3"; | ||
| 940 | reg = <0x48910000 0x17000>; | ||
| 941 | /* interrupts = <0 93 4>; */ | ||
| 942 | tx-fifo-resize; | ||
| 943 | maximum-speed = "high-speed"; | ||
| 944 | dr_mode = "otg"; | ||
| 945 | }; | ||
| 946 | }; | ||
| 947 | |||
| 948 | omap_dwc3_4@48940000 { | ||
| 949 | compatible = "ti,dwc3"; | ||
| 950 | ti,hwmods = "usb_otg_ss4"; | ||
| 951 | reg = <0x48940000 0x10000>; | ||
| 952 | /* interrupts = <0 TBD 4>; */ | ||
| 953 | #address-cells = <1>; | ||
| 954 | #size-cells = <1>; | ||
| 955 | utmi-mode = <2>; | ||
| 956 | ranges; | ||
| 957 | status = "disabled"; | ||
| 958 | usb4: usb@48950000 { | ||
| 959 | compatible = "snps,dwc3"; | ||
| 960 | reg = <0x48950000 0x17000>; | ||
| 961 | /* interrupts = <0 TBD 4>; */ | ||
| 962 | tx-fifo-resize; | ||
| 963 | maximum-speed = "high-speed"; | ||
| 964 | dr_mode = "otg"; | ||
| 965 | }; | ||
| 966 | }; | ||
| 967 | |||
| 968 | elm: elm@48078000 { | ||
| 969 | compatible = "ti,am3352-elm"; | ||
| 970 | reg = <0x48078000 0xfc0>; /* device IO registers */ | ||
| 971 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | ||
| 972 | ti,hwmods = "elm"; | ||
| 973 | status = "disabled"; | ||
| 974 | }; | ||
| 975 | |||
| 976 | gpmc: gpmc@50000000 { | ||
| 977 | compatible = "ti,am3352-gpmc"; | ||
| 978 | ti,hwmods = "gpmc"; | ||
| 979 | reg = <0x50000000 0x37c>; /* device IO registers */ | ||
| 980 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | ||
| 981 | gpmc,num-cs = <8>; | ||
| 982 | gpmc,num-waitpins = <2>; | ||
| 983 | #address-cells = <2>; | ||
| 984 | #size-cells = <1>; | ||
| 985 | status = "disabled"; | ||
| 986 | }; | ||
| 792 | }; | 987 | }; |
| 793 | }; | 988 | }; |
| 794 | 989 | ||
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts new file mode 100644 index 000000000000..514702348818 --- /dev/null +++ b/arch/arm/boot/dts/dra72-evm.dts | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | /dts-v1/; | ||
| 9 | |||
| 10 | #include "dra72x.dtsi" | ||
| 11 | |||
| 12 | / { | ||
| 13 | model = "TI DRA722"; | ||
| 14 | compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; | ||
| 15 | |||
| 16 | memory { | ||
| 17 | device_type = "memory"; | ||
| 18 | reg = <0x80000000 0x40000000>; /* 1024 MB */ | ||
| 19 | }; | ||
| 20 | }; | ||
| 21 | |||
| 22 | &uart1 { | ||
| 23 | status = "okay"; | ||
| 24 | }; | ||
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi new file mode 100644 index 000000000000..f1ec22f6ebf4 --- /dev/null +++ b/arch/arm/boot/dts/dra72x.dtsi | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * Based on "omap4.dtsi" | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include "dra7.dtsi" | ||
| 11 | |||
| 12 | / { | ||
| 13 | compatible = "ti,dra722", "ti,dra72", "ti,dra7"; | ||
| 14 | |||
| 15 | cpus { | ||
| 16 | #address-cells = <1>; | ||
| 17 | #size-cells = <0>; | ||
| 18 | |||
| 19 | cpu0: cpu@0 { | ||
| 20 | device_type = "cpu"; | ||
| 21 | compatible = "arm,cortex-a15"; | ||
| 22 | reg = <0>; | ||
| 23 | }; | ||
| 24 | }; | ||
| 25 | }; | ||
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi new file mode 100644 index 000000000000..a4e8bb9f95c0 --- /dev/null +++ b/arch/arm/boot/dts/dra74x.dtsi | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * Based on "omap4.dtsi" | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include "dra7.dtsi" | ||
| 11 | |||
| 12 | / { | ||
| 13 | compatible = "ti,dra742", "ti,dra74", "ti,dra7"; | ||
| 14 | |||
| 15 | cpus { | ||
| 16 | #address-cells = <1>; | ||
| 17 | #size-cells = <0>; | ||
| 18 | |||
| 19 | cpu0: cpu@0 { | ||
| 20 | device_type = "cpu"; | ||
| 21 | compatible = "arm,cortex-a15"; | ||
| 22 | reg = <0>; | ||
| 23 | |||
| 24 | operating-points = < | ||
| 25 | /* kHz uV */ | ||
| 26 | 1000000 1060000 | ||
| 27 | 1176000 1160000 | ||
| 28 | >; | ||
| 29 | |||
| 30 | clocks = <&dpll_mpu_ck>; | ||
| 31 | clock-names = "cpu"; | ||
| 32 | |||
| 33 | clock-latency = <300000>; /* From omap-cpufreq driver */ | ||
| 34 | }; | ||
| 35 | cpu@1 { | ||
| 36 | device_type = "cpu"; | ||
| 37 | compatible = "arm,cortex-a15"; | ||
| 38 | reg = <1>; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | }; | ||
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index cfb8fc753f50..c7676871d9c0 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi | |||
| @@ -1386,6 +1386,14 @@ | |||
| 1386 | ti,dividers = <1>, <8>; | 1386 | ti,dividers = <1>, <8>; |
| 1387 | }; | 1387 | }; |
| 1388 | 1388 | ||
| 1389 | l3init_960m_gfclk: l3init_960m_gfclk { | ||
| 1390 | #clock-cells = <0>; | ||
| 1391 | compatible = "ti,gate-clock"; | ||
| 1392 | clocks = <&dpll_usb_clkdcoldo>; | ||
| 1393 | ti,bit-shift = <8>; | ||
| 1394 | reg = <0x06c0>; | ||
| 1395 | }; | ||
| 1396 | |||
| 1389 | dss_32khz_clk: dss_32khz_clk { | 1397 | dss_32khz_clk: dss_32khz_clk { |
| 1390 | #clock-cells = <0>; | 1398 | #clock-cells = <0>; |
| 1391 | compatible = "ti,gate-clock"; | 1399 | compatible = "ti,gate-clock"; |
| @@ -1533,7 +1541,7 @@ | |||
| 1533 | usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { | 1541 | usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { |
| 1534 | #clock-cells = <0>; | 1542 | #clock-cells = <0>; |
| 1535 | compatible = "ti,gate-clock"; | 1543 | compatible = "ti,gate-clock"; |
| 1536 | clocks = <&dpll_usb_clkdcoldo>; | 1544 | clocks = <&l3init_960m_gfclk>; |
| 1537 | ti,bit-shift = <8>; | 1545 | ti,bit-shift = <8>; |
| 1538 | reg = <0x13f0>; | 1546 | reg = <0x13f0>; |
| 1539 | }; | 1547 | }; |
| @@ -1541,7 +1549,7 @@ | |||
| 1541 | usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m { | 1549 | usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m { |
| 1542 | #clock-cells = <0>; | 1550 | #clock-cells = <0>; |
| 1543 | compatible = "ti,gate-clock"; | 1551 | compatible = "ti,gate-clock"; |
| 1544 | clocks = <&dpll_usb_clkdcoldo>; | 1552 | clocks = <&l3init_960m_gfclk>; |
| 1545 | ti,bit-shift = <8>; | 1553 | ti,bit-shift = <8>; |
| 1546 | reg = <0x1340>; | 1554 | reg = <0x1340>; |
| 1547 | }; | 1555 | }; |
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi new file mode 100644 index 000000000000..47b92c150f4e --- /dev/null +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi | |||
| @@ -0,0 +1,475 @@ | |||
| 1 | /* | ||
| 2 | * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source | ||
| 3 | * | ||
| 4 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. | ||
| 5 | * http://www.samsung.com | ||
| 6 | * | ||
| 7 | * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device | ||
| 8 | * tree nodes are listed in this file. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | &pinctrl_0 { | ||
| 16 | gpa0: gpa0 { | ||
| 17 | gpio-controller; | ||
| 18 | #gpio-cells = <2>; | ||
| 19 | |||
| 20 | interrupt-controller; | ||
| 21 | #interrupt-cells = <2>; | ||
| 22 | }; | ||
| 23 | |||
| 24 | gpa1: gpa1 { | ||
| 25 | gpio-controller; | ||
| 26 | #gpio-cells = <2>; | ||
| 27 | |||
| 28 | interrupt-controller; | ||
| 29 | #interrupt-cells = <2>; | ||
| 30 | }; | ||
| 31 | |||
| 32 | gpb: gpb { | ||
| 33 | gpio-controller; | ||
| 34 | #gpio-cells = <2>; | ||
| 35 | |||
| 36 | interrupt-controller; | ||
| 37 | #interrupt-cells = <2>; | ||
| 38 | }; | ||
| 39 | |||
| 40 | gpc0: gpc0 { | ||
| 41 | gpio-controller; | ||
| 42 | #gpio-cells = <2>; | ||
| 43 | |||
| 44 | interrupt-controller; | ||
| 45 | #interrupt-cells = <2>; | ||
| 46 | }; | ||
| 47 | |||
| 48 | gpc1: gpc1 { | ||
| 49 | gpio-controller; | ||
| 50 | #gpio-cells = <2>; | ||
| 51 | |||
| 52 | interrupt-controller; | ||
| 53 | #interrupt-cells = <2>; | ||
| 54 | }; | ||
| 55 | |||
| 56 | gpd0: gpd0 { | ||
| 57 | gpio-controller; | ||
| 58 | #gpio-cells = <2>; | ||
| 59 | |||
| 60 | interrupt-controller; | ||
| 61 | #interrupt-cells = <2>; | ||
| 62 | }; | ||
| 63 | |||
| 64 | gpd1: gpd1 { | ||
| 65 | gpio-controller; | ||
| 66 | #gpio-cells = <2>; | ||
| 67 | |||
| 68 | interrupt-controller; | ||
| 69 | #interrupt-cells = <2>; | ||
| 70 | }; | ||
| 71 | |||
| 72 | uart0_data: uart0-data { | ||
| 73 | samsung,pins = "gpa0-0", "gpa0-1"; | ||
| 74 | samsung,pin-function = <0x2>; | ||
| 75 | samsung,pin-pud = <0>; | ||
| 76 | samsung,pin-drv = <0>; | ||
| 77 | }; | ||
| 78 | |||
| 79 | uart0_fctl: uart0-fctl { | ||
| 80 | samsung,pins = "gpa0-2", "gpa0-3"; | ||
| 81 | samsung,pin-function = <2>; | ||
| 82 | samsung,pin-pud = <0>; | ||
| 83 | samsung,pin-drv = <0>; | ||
| 84 | }; | ||
| 85 | |||
| 86 | uart1_data: uart1-data { | ||
| 87 | samsung,pins = "gpa0-4", "gpa0-5"; | ||
| 88 | samsung,pin-function = <2>; | ||
| 89 | samsung,pin-pud = <0>; | ||
| 90 | samsung,pin-drv = <0>; | ||
| 91 | }; | ||
| 92 | |||
| 93 | uart1_fctl: uart1-fctl { | ||
| 94 | samsung,pins = "gpa0-6", "gpa0-7"; | ||
| 95 | samsung,pin-function = <2>; | ||
| 96 | samsung,pin-pud = <0>; | ||
| 97 | samsung,pin-drv = <0>; | ||
| 98 | }; | ||
| 99 | |||
| 100 | i2c2_bus: i2c2-bus { | ||
| 101 | samsung,pins = "gpa0-6", "gpa0-7"; | ||
| 102 | samsung,pin-function = <3>; | ||
| 103 | samsung,pin-pud = <3>; | ||
| 104 | samsung,pin-drv = <0>; | ||
| 105 | }; | ||
| 106 | |||
| 107 | i2c3_bus: i2c3-bus { | ||
| 108 | samsung,pins = "gpa1-2", "gpa1-3"; | ||
| 109 | samsung,pin-function = <3>; | ||
| 110 | samsung,pin-pud = <3>; | ||
| 111 | samsung,pin-drv = <0>; | ||
| 112 | }; | ||
| 113 | |||
| 114 | spi0_bus: spi0-bus { | ||
| 115 | samsung,pins = "gpb-0", "gpb-2", "gpb-3"; | ||
| 116 | samsung,pin-function = <2>; | ||
| 117 | samsung,pin-pud = <3>; | ||
| 118 | samsung,pin-drv = <0>; | ||
| 119 | }; | ||
| 120 | |||
| 121 | i2c4_bus: i2c4-bus { | ||
| 122 | samsung,pins = "gpb-0", "gpb-1"; | ||
| 123 | samsung,pin-function = <3>; | ||
| 124 | samsung,pin-pud = <3>; | ||
| 125 | samsung,pin-drv = <0>; | ||
| 126 | }; | ||
| 127 | |||
| 128 | spi1_bus: spi1-bus { | ||
| 129 | samsung,pins = "gpb-4", "gpb-6", "gpb-7"; | ||
| 130 | samsung,pin-function = <2>; | ||
| 131 | samsung,pin-pud = <3>; | ||
| 132 | samsung,pin-drv = <0>; | ||
| 133 | }; | ||
| 134 | |||
| 135 | i2c5_bus: i2c5-bus { | ||
| 136 | samsung,pins = "gpb-2", "gpb-3"; | ||
| 137 | samsung,pin-function = <3>; | ||
| 138 | samsung,pin-pud = <3>; | ||
| 139 | samsung,pin-drv = <0>; | ||
| 140 | }; | ||
| 141 | |||
| 142 | i2s2_bus: i2s2-bus { | ||
| 143 | samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", | ||
| 144 | "gpc1-4"; | ||
| 145 | samsung,pin-function = <2>; | ||
| 146 | samsung,pin-pud = <0>; | ||
| 147 | samsung,pin-drv = <0>; | ||
| 148 | }; | ||
| 149 | |||
| 150 | pcm2_bus: pcm2-bus { | ||
| 151 | samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", | ||
| 152 | "gpc1-4"; | ||
| 153 | samsung,pin-function = <3>; | ||
| 154 | samsung,pin-pud = <0>; | ||
| 155 | samsung,pin-drv = <0>; | ||
| 156 | }; | ||
| 157 | |||
| 158 | i2c6_bus: i2c6-bus { | ||
| 159 | samsung,pins = "gpc1-3", "gpc1-4"; | ||
| 160 | samsung,pin-function = <4>; | ||
| 161 | samsung,pin-pud = <3>; | ||
| 162 | samsung,pin-drv = <0>; | ||
| 163 | }; | ||
| 164 | |||
| 165 | pwm0_out: pwm0-out { | ||
| 166 | samsung,pins = "gpd0-0"; | ||
| 167 | samsung,pin-function = <2>; | ||
| 168 | samsung,pin-pud = <0>; | ||
| 169 | samsung,pin-drv = <0>; | ||
| 170 | }; | ||
| 171 | |||
| 172 | pwm1_out: pwm1-out { | ||
| 173 | samsung,pins = "gpd0-1"; | ||
| 174 | samsung,pin-function = <2>; | ||
| 175 | samsung,pin-pud = <0>; | ||
| 176 | samsung,pin-drv = <0>; | ||
| 177 | }; | ||
| 178 | |||
| 179 | i2c7_bus: i2c7-bus { | ||
| 180 | samsung,pins = "gpd0-2", "gpd0-3"; | ||
| 181 | samsung,pin-function = <3>; | ||
| 182 | samsung,pin-pud = <3>; | ||
| 183 | samsung,pin-drv = <0>; | ||
| 184 | }; | ||
| 185 | |||
| 186 | pwm2_out: pwm2-out { | ||
| 187 | samsung,pins = "gpd0-2"; | ||
| 188 | samsung,pin-function = <2>; | ||
| 189 | samsung,pin-pud = <0>; | ||
| 190 | samsung,pin-drv = <0>; | ||
| 191 | }; | ||
| 192 | |||
| 193 | pwm3_out: pwm3-out { | ||
| 194 | samsung,pins = "gpd0-3"; | ||
| 195 | samsung,pin-function = <2>; | ||
| 196 | samsung,pin-pud = <0>; | ||
| 197 | samsung,pin-drv = <0>; | ||
| 198 | }; | ||
| 199 | |||
| 200 | i2c0_bus: i2c0-bus { | ||
| 201 | samsung,pins = "gpd1-0", "gpd1-1"; | ||
| 202 | samsung,pin-function = <2>; | ||
| 203 | samsung,pin-pud = <3>; | ||
| 204 | samsung,pin-drv = <0>; | ||
| 205 | }; | ||
| 206 | |||
| 207 | mipi0_clk: mipi0-clk { | ||
| 208 | samsung,pins = "gpd1-0", "gpd1-1"; | ||
| 209 | samsung,pin-function = <3>; | ||
| 210 | samsung,pin-pud = <0>; | ||
| 211 | samsung,pin-drv = <0>; | ||
| 212 | }; | ||
| 213 | |||
| 214 | i2c1_bus: i2c1-bus { | ||
| 215 | samsung,pins = "gpd1-2", "gpd1-3"; | ||
| 216 | samsung,pin-function = <2>; | ||
| 217 | samsung,pin-pud = <3>; | ||
| 218 | samsung,pin-drv = <0>; | ||
| 219 | }; | ||
| 220 | }; | ||
| 221 | |||
| 222 | &pinctrl_1 { | ||
| 223 | gpe0: gpe0 { | ||
| 224 | gpio-controller; | ||
| 225 | #gpio-cells = <2>; | ||
| 226 | }; | ||
| 227 | |||
| 228 | gpe1: gpe1 { | ||
| 229 | gpio-controller; | ||
| 230 | #gpio-cells = <2>; | ||
| 231 | }; | ||
| 232 | |||
| 233 | gpe2: gpe2 { | ||
| 234 | gpio-controller; | ||
| 235 | #gpio-cells = <2>; | ||
| 236 | }; | ||
| 237 | |||
| 238 | gpk0: gpk0 { | ||
| 239 | gpio-controller; | ||
| 240 | #gpio-cells = <2>; | ||
| 241 | |||
| 242 | interrupt-controller; | ||
| 243 | #interrupt-cells = <2>; | ||
| 244 | }; | ||
| 245 | |||
| 246 | gpk1: gpk1 { | ||
| 247 | gpio-controller; | ||
| 248 | #gpio-cells = <2>; | ||
| 249 | |||
| 250 | interrupt-controller; | ||
| 251 | #interrupt-cells = <2>; | ||
| 252 | }; | ||
| 253 | |||
| 254 | gpk2: gpk2 { | ||
| 255 | gpio-controller; | ||
| 256 | #gpio-cells = <2>; | ||
| 257 | |||
| 258 | interrupt-controller; | ||
| 259 | #interrupt-cells = <2>; | ||
| 260 | }; | ||
| 261 | |||
| 262 | gpl0: gpl0 { | ||
| 263 | gpio-controller; | ||
| 264 | #gpio-cells = <2>; | ||
| 265 | |||
| 266 | interrupt-controller; | ||
| 267 | #interrupt-cells = <2>; | ||
| 268 | }; | ||
| 269 | |||
| 270 | gpm0: gpm0 { | ||
| 271 | gpio-controller; | ||
| 272 | #gpio-cells = <2>; | ||
| 273 | |||
| 274 | interrupt-controller; | ||
| 275 | #interrupt-cells = <2>; | ||
| 276 | }; | ||
| 277 | |||
| 278 | gpm1: gpm1 { | ||
| 279 | gpio-controller; | ||
| 280 | #gpio-cells = <2>; | ||
| 281 | |||
| 282 | interrupt-controller; | ||
| 283 | #interrupt-cells = <2>; | ||
| 284 | }; | ||
| 285 | |||
| 286 | gpm2: gpm2 { | ||
| 287 | gpio-controller; | ||
| 288 | #gpio-cells = <2>; | ||
| 289 | |||
| 290 | interrupt-controller; | ||
| 291 | #interrupt-cells = <2>; | ||
| 292 | }; | ||
| 293 | |||
| 294 | gpm3: gpm3 { | ||
| 295 | gpio-controller; | ||
| 296 | #gpio-cells = <2>; | ||
| 297 | |||
| 298 | interrupt-controller; | ||
| 299 | #interrupt-cells = <2>; | ||
| 300 | }; | ||
| 301 | |||
| 302 | gpm4: gpm4 { | ||
| 303 | gpio-controller; | ||
| 304 | #gpio-cells = <2>; | ||
| 305 | |||
| 306 | interrupt-controller; | ||
| 307 | #interrupt-cells = <2>; | ||
| 308 | }; | ||
| 309 | |||
| 310 | gpx0: gpx0 { | ||
| 311 | gpio-controller; | ||
| 312 | #gpio-cells = <2>; | ||
| 313 | |||
| 314 | interrupt-controller; | ||
| 315 | interrupt-parent = <&gic>; | ||
| 316 | interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>, | ||
| 317 | <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>; | ||
| 318 | #interrupt-cells = <2>; | ||
| 319 | }; | ||
| 320 | |||
| 321 | gpx1: gpx1 { | ||
| 322 | gpio-controller; | ||
| 323 | #gpio-cells = <2>; | ||
| 324 | |||
| 325 | interrupt-controller; | ||
| 326 | interrupt-parent = <&gic>; | ||
| 327 | interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>, | ||
| 328 | <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>; | ||
| 329 | #interrupt-cells = <2>; | ||
| 330 | }; | ||
| 331 | |||
| 332 | gpx2: gpx2 { | ||
| 333 | gpio-controller; | ||
| 334 | #gpio-cells = <2>; | ||
| 335 | |||
| 336 | interrupt-controller; | ||
| 337 | #interrupt-cells = <2>; | ||
| 338 | }; | ||
| 339 | |||
| 340 | gpx3: gpx3 { | ||
| 341 | gpio-controller; | ||
| 342 | #gpio-cells = <2>; | ||
| 343 | |||
| 344 | interrupt-controller; | ||
| 345 | #interrupt-cells = <2>; | ||
| 346 | }; | ||
| 347 | |||
| 348 | sd0_clk: sd0-clk { | ||
| 349 | samsung,pins = "gpk0-0"; | ||
| 350 | samsung,pin-function = <2>; | ||
| 351 | samsung,pin-pud = <0>; | ||
| 352 | samsung,pin-drv = <3>; | ||
| 353 | }; | ||
| 354 | |||
| 355 | sd0_cmd: sd0-cmd { | ||
| 356 | samsung,pins = "gpk0-1"; | ||
| 357 | samsung,pin-function = <2>; | ||
| 358 | samsung,pin-pud = <0>; | ||
| 359 | samsung,pin-drv = <3>; | ||
| 360 | }; | ||
| 361 | |||
| 362 | sd0_cd: sd0-cd { | ||
| 363 | samsung,pins = "gpk0-2"; | ||
| 364 | samsung,pin-function = <2>; | ||
| 365 | samsung,pin-pud = <3>; | ||
| 366 | samsung,pin-drv = <3>; | ||
| 367 | }; | ||
| 368 | |||
| 369 | sd0_rdqs: sd0-rdqs { | ||
| 370 | samsung,pins = "gpk0-7"; | ||
| 371 | samsung,pin-function = <2>; | ||
| 372 | samsung,pin-pud = <0>; | ||
| 373 | samsung,pin-drv = <3>; | ||
| 374 | }; | ||
| 375 | |||
| 376 | sd0_bus1: sd0-bus-width1 { | ||
| 377 | samsung,pins = "gpk0-3"; | ||
| 378 | samsung,pin-function = <2>; | ||
| 379 | samsung,pin-pud = <3>; | ||
| 380 | samsung,pin-drv = <3>; | ||
| 381 | }; | ||
| 382 | |||
| 383 | sd0_bus4: sd0-bus-width4 { | ||
| 384 | samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; | ||
| 385 | samsung,pin-function = <2>; | ||
| 386 | samsung,pin-pud = <3>; | ||
| 387 | samsung,pin-drv = <3>; | ||
| 388 | }; | ||
| 389 | |||
| 390 | sd0_bus8: sd0-bus-width8 { | ||
| 391 | samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; | ||
| 392 | samsung,pin-function = <2>; | ||
| 393 | samsung,pin-pud = <3>; | ||
| 394 | samsung,pin-drv = <3>; | ||
| 395 | }; | ||
| 396 | |||
| 397 | sd1_clk: sd1-clk { | ||
| 398 | samsung,pins = "gpk1-0"; | ||
| 399 | samsung,pin-function = <2>; | ||
| 400 | samsung,pin-pud = <0>; | ||
| 401 | samsung,pin-drv = <3>; | ||
| 402 | }; | ||
| 403 | |||
| 404 | sd1_cmd: sd1-cmd { | ||
| 405 | samsung,pins = "gpk1-1"; | ||
| 406 | samsung,pin-function = <2>; | ||
| 407 | samsung,pin-pud = <0>; | ||
| 408 | samsung,pin-drv = <3>; | ||
| 409 | }; | ||
| 410 | |||
| 411 | sd1_cd: sd1-cd { | ||
| 412 | samsung,pins = "gpk1-2"; | ||
| 413 | samsung,pin-function = <2>; | ||
| 414 | samsung,pin-pud = <3>; | ||
| 415 | samsung,pin-drv = <3>; | ||
| 416 | }; | ||
| 417 | |||
| 418 | sd1_bus1: sd1-bus-width1 { | ||
| 419 | samsung,pins = "gpk1-3"; | ||
| 420 | samsung,pin-function = <2>; | ||
| 421 | samsung,pin-pud = <3>; | ||
| 422 | samsung,pin-drv = <3>; | ||
| 423 | }; | ||
| 424 | |||
| 425 | sd1_bus4: sd1-bus-width4 { | ||
| 426 | samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; | ||
| 427 | samsung,pin-function = <2>; | ||
| 428 | samsung,pin-pud = <3>; | ||
| 429 | samsung,pin-drv = <3>; | ||
| 430 | }; | ||
| 431 | |||
| 432 | cam_port_b_io: cam-port-b-io { | ||
| 433 | samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", | ||
| 434 | "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", | ||
| 435 | "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; | ||
| 436 | samsung,pin-function = <3>; | ||
| 437 | samsung,pin-pud = <3>; | ||
| 438 | samsung,pin-drv = <0>; | ||
| 439 | }; | ||
| 440 | |||
| 441 | cam_port_b_clk_active: cam-port-b-clk-active { | ||
| 442 | samsung,pins = "gpm2-2"; | ||
| 443 | samsung,pin-function = <3>; | ||
| 444 | samsung,pin-pud = <0>; | ||
| 445 | samsung,pin-drv = <3>; | ||
| 446 | }; | ||
| 447 | |||
| 448 | cam_port_b_clk_idle: cam-port-b-clk-idle { | ||
| 449 | samsung,pins = "gpm2-2"; | ||
| 450 | samsung,pin-function = <0>; | ||
| 451 | samsung,pin-pud = <0>; | ||
| 452 | samsung,pin-drv = <0>; | ||
| 453 | }; | ||
| 454 | |||
| 455 | fimc_is_i2c0: fimc-is-i2c0 { | ||
| 456 | samsung,pins = "gpm4-0", "gpm4-1"; | ||
| 457 | samsung,pin-function = <2>; | ||
| 458 | samsung,pin-pud = <0>; | ||
| 459 | samsung,pin-drv = <0>; | ||
| 460 | }; | ||
| 461 | |||
| 462 | fimc_is_i2c1: fimc-is-i2c1 { | ||
| 463 | samsung,pins = "gpm4-2", "gpm4-3"; | ||
| 464 | samsung,pin-function = <2>; | ||
| 465 | samsung,pin-pud = <0>; | ||
| 466 | samsung,pin-drv = <0>; | ||
| 467 | }; | ||
| 468 | |||
| 469 | fimc_is_uart: fimc-is-uart { | ||
| 470 | samsung,pins = "gpm3-5", "gpm3-7"; | ||
| 471 | samsung,pin-function = <3>; | ||
| 472 | samsung,pin-pud = <0>; | ||
| 473 | samsung,pin-drv = <0>; | ||
| 474 | }; | ||
| 475 | }; | ||
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi new file mode 100644 index 000000000000..3e678fa335bf --- /dev/null +++ b/arch/arm/boot/dts/exynos3250.dtsi | |||
| @@ -0,0 +1,444 @@ | |||
| 1 | /* | ||
| 2 | * Samsung's Exynos3250 SoC device tree source | ||
| 3 | * | ||
| 4 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. | ||
| 5 | * http://www.samsung.com | ||
| 6 | * | ||
| 7 | * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 | ||
| 8 | * based board files can include this file and provide values for board specfic | ||
| 9 | * bindings. | ||
| 10 | * | ||
| 11 | * Note: This file does not include device nodes for all the controllers in | ||
| 12 | * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional | ||
| 13 | * nodes can be added to this file. | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License version 2 as | ||
| 17 | * published by the Free Software Foundation. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #include "skeleton.dtsi" | ||
| 21 | #include <dt-bindings/clock/exynos3250.h> | ||
| 22 | |||
| 23 | / { | ||
| 24 | compatible = "samsung,exynos3250"; | ||
| 25 | interrupt-parent = <&gic>; | ||
| 26 | |||
| 27 | aliases { | ||
| 28 | pinctrl0 = &pinctrl_0; | ||
| 29 | pinctrl1 = &pinctrl_1; | ||
| 30 | mshc0 = &mshc_0; | ||
| 31 | mshc1 = &mshc_1; | ||
| 32 | spi0 = &spi_0; | ||
| 33 | spi1 = &spi_1; | ||
| 34 | i2c0 = &i2c_0; | ||
| 35 | i2c1 = &i2c_1; | ||
| 36 | i2c2 = &i2c_2; | ||
| 37 | i2c3 = &i2c_3; | ||
| 38 | i2c4 = &i2c_4; | ||
| 39 | i2c5 = &i2c_5; | ||
| 40 | i2c6 = &i2c_6; | ||
| 41 | i2c7 = &i2c_7; | ||
| 42 | }; | ||
| 43 | |||
| 44 | cpus { | ||
| 45 | #address-cells = <1>; | ||
| 46 | #size-cells = <0>; | ||
| 47 | |||
| 48 | cpu0: cpu@0 { | ||
| 49 | device_type = "cpu"; | ||
| 50 | compatible = "arm,cortex-a7"; | ||
| 51 | reg = <0>; | ||
| 52 | clock-frequency = <1000000000>; | ||
| 53 | }; | ||
| 54 | |||
| 55 | cpu1: cpu@1 { | ||
| 56 | device_type = "cpu"; | ||
| 57 | compatible = "arm,cortex-a7"; | ||
| 58 | reg = <1>; | ||
| 59 | clock-frequency = <1000000000>; | ||
| 60 | }; | ||
| 61 | }; | ||
| 62 | |||
| 63 | soc: soc { | ||
| 64 | compatible = "simple-bus"; | ||
| 65 | #address-cells = <1>; | ||
| 66 | #size-cells = <1>; | ||
| 67 | ranges; | ||
| 68 | |||
| 69 | fixed-rate-clocks { | ||
| 70 | #address-cells = <1>; | ||
| 71 | #size-cells = <0>; | ||
| 72 | |||
| 73 | xusbxti: clock@0 { | ||
| 74 | compatible = "fixed-clock"; | ||
| 75 | #address-cells = <1>; | ||
| 76 | #size-cells = <0>; | ||
| 77 | reg = <0>; | ||
| 78 | clock-frequency = <0>; | ||
| 79 | #clock-cells = <0>; | ||
| 80 | clock-output-names = "xusbxti"; | ||
| 81 | }; | ||
| 82 | |||
| 83 | xxti: clock@1 { | ||
| 84 | compatible = "fixed-clock"; | ||
| 85 | reg = <1>; | ||
| 86 | clock-frequency = <0>; | ||
| 87 | #clock-cells = <0>; | ||
| 88 | clock-output-names = "xxti"; | ||
| 89 | }; | ||
| 90 | |||
| 91 | xtcxo: clock@2 { | ||
| 92 | compatible = "fixed-clock"; | ||
| 93 | reg = <2>; | ||
| 94 | clock-frequency = <0>; | ||
| 95 | #clock-cells = <0>; | ||
| 96 | clock-output-names = "xtcxo"; | ||
| 97 | }; | ||
| 98 | }; | ||
| 99 | |||
| 100 | sysram@02020000 { | ||
| 101 | compatible = "mmio-sram"; | ||
| 102 | reg = <0x02020000 0x40000>; | ||
| 103 | #address-cells = <1>; | ||
| 104 | #size-cells = <1>; | ||
| 105 | ranges = <0 0x02020000 0x40000>; | ||
| 106 | |||
| 107 | smp-sysram@0 { | ||
| 108 | compatible = "samsung,exynos4210-sysram"; | ||
| 109 | reg = <0x0 0x1000>; | ||
| 110 | }; | ||
| 111 | |||
| 112 | smp-sysram@3f000 { | ||
| 113 | compatible = "samsung,exynos4210-sysram-ns"; | ||
| 114 | reg = <0x3f000 0x1000>; | ||
| 115 | }; | ||
| 116 | }; | ||
| 117 | |||
| 118 | chipid@10000000 { | ||
| 119 | compatible = "samsung,exynos4210-chipid"; | ||
| 120 | reg = <0x10000000 0x100>; | ||
| 121 | }; | ||
| 122 | |||
| 123 | sys_reg: syscon@10010000 { | ||
| 124 | compatible = "samsung,exynos3-sysreg", "syscon"; | ||
| 125 | reg = <0x10010000 0x400>; | ||
| 126 | }; | ||
| 127 | |||
| 128 | pmu_system_controller: system-controller@10020000 { | ||
| 129 | compatible = "samsung,exynos3250-pmu", "syscon"; | ||
| 130 | reg = <0x10020000 0x4000>; | ||
| 131 | }; | ||
| 132 | |||
| 133 | pd_cam: cam-power-domain@10023C00 { | ||
| 134 | compatible = "samsung,exynos4210-pd"; | ||
| 135 | reg = <0x10023C00 0x20>; | ||
| 136 | }; | ||
| 137 | |||
| 138 | pd_mfc: mfc-power-domain@10023C40 { | ||
| 139 | compatible = "samsung,exynos4210-pd"; | ||
| 140 | reg = <0x10023C40 0x20>; | ||
| 141 | }; | ||
| 142 | |||
| 143 | pd_g3d: g3d-power-domain@10023C60 { | ||
| 144 | compatible = "samsung,exynos4210-pd"; | ||
| 145 | reg = <0x10023C60 0x20>; | ||
| 146 | }; | ||
| 147 | |||
| 148 | pd_lcd0: lcd0-power-domain@10023C80 { | ||
| 149 | compatible = "samsung,exynos4210-pd"; | ||
| 150 | reg = <0x10023C80 0x20>; | ||
| 151 | }; | ||
| 152 | |||
| 153 | pd_isp: isp-power-domain@10023CA0 { | ||
| 154 | compatible = "samsung,exynos4210-pd"; | ||
| 155 | reg = <0x10023CA0 0x20>; | ||
| 156 | }; | ||
| 157 | |||
| 158 | cmu: clock-controller@10030000 { | ||
| 159 | compatible = "samsung,exynos3250-cmu"; | ||
| 160 | reg = <0x10030000 0x20000>; | ||
| 161 | #clock-cells = <1>; | ||
| 162 | }; | ||
| 163 | |||
| 164 | rtc: rtc@10070000 { | ||
| 165 | compatible = "samsung,s3c6410-rtc"; | ||
| 166 | reg = <0x10070000 0x100>; | ||
| 167 | interrupts = <0 73 0>, <0 74 0>; | ||
| 168 | status = "disabled"; | ||
| 169 | }; | ||
| 170 | |||
| 171 | gic: interrupt-controller@10481000 { | ||
| 172 | compatible = "arm,cortex-a15-gic"; | ||
| 173 | #interrupt-cells = <3>; | ||
| 174 | interrupt-controller; | ||
| 175 | reg = <0x10481000 0x1000>, | ||
| 176 | <0x10482000 0x1000>, | ||
| 177 | <0x10484000 0x2000>, | ||
| 178 | <0x10486000 0x2000>; | ||
| 179 | interrupts = <1 9 0xf04>; | ||
| 180 | }; | ||
| 181 | |||
| 182 | mct@10050000 { | ||
| 183 | compatible = "samsung,exynos4210-mct"; | ||
| 184 | reg = <0x10050000 0x800>; | ||
| 185 | interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, | ||
| 186 | <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; | ||
| 187 | clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; | ||
| 188 | clock-names = "fin_pll", "mct"; | ||
| 189 | }; | ||
| 190 | |||
| 191 | pinctrl_1: pinctrl@11000000 { | ||
| 192 | compatible = "samsung,exynos3250-pinctrl"; | ||
| 193 | reg = <0x11000000 0x1000>; | ||
| 194 | interrupts = <0 225 0>; | ||
| 195 | |||
| 196 | wakeup-interrupt-controller { | ||
| 197 | compatible = "samsung,exynos4210-wakeup-eint"; | ||
| 198 | interrupt-parent = <&gic>; | ||
| 199 | interrupts = <0 48 0>; | ||
| 200 | }; | ||
| 201 | }; | ||
| 202 | |||
| 203 | pinctrl_0: pinctrl@11400000 { | ||
| 204 | compatible = "samsung,exynos3250-pinctrl"; | ||
| 205 | reg = <0x11400000 0x1000>; | ||
| 206 | interrupts = <0 240 0>; | ||
| 207 | }; | ||
| 208 | |||
| 209 | mshc_0: mshc@12510000 { | ||
| 210 | compatible = "samsung,exynos5250-dw-mshc"; | ||
| 211 | reg = <0x12510000 0x1000>; | ||
| 212 | interrupts = <0 142 0>; | ||
| 213 | clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; | ||
| 214 | clock-names = "biu", "ciu"; | ||
| 215 | fifo-depth = <0x80>; | ||
| 216 | #address-cells = <1>; | ||
| 217 | #size-cells = <0>; | ||
| 218 | status = "disabled"; | ||
| 219 | }; | ||
| 220 | |||
| 221 | mshc_1: mshc@12520000 { | ||
| 222 | compatible = "samsung,exynos5250-dw-mshc"; | ||
| 223 | reg = <0x12520000 0x1000>; | ||
| 224 | interrupts = <0 143 0>; | ||
| 225 | clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; | ||
| 226 | clock-names = "biu", "ciu"; | ||
| 227 | fifo-depth = <0x80>; | ||
| 228 | #address-cells = <1>; | ||
| 229 | #size-cells = <0>; | ||
| 230 | status = "disabled"; | ||
| 231 | }; | ||
| 232 | |||
| 233 | amba { | ||
| 234 | compatible = "arm,amba-bus"; | ||
| 235 | #address-cells = <1>; | ||
| 236 | #size-cells = <1>; | ||
| 237 | interrupt-parent = <&gic>; | ||
| 238 | ranges; | ||
| 239 | |||
| 240 | pdma0: pdma@12680000 { | ||
| 241 | compatible = "arm,pl330", "arm,primecell"; | ||
| 242 | reg = <0x12680000 0x1000>; | ||
| 243 | interrupts = <0 138 0>; | ||
| 244 | clocks = <&cmu CLK_PDMA0>; | ||
| 245 | clock-names = "apb_pclk"; | ||
| 246 | #dma-cells = <1>; | ||
| 247 | #dma-channels = <8>; | ||
| 248 | #dma-requests = <32>; | ||
| 249 | }; | ||
| 250 | |||
| 251 | pdma1: pdma@12690000 { | ||
| 252 | compatible = "arm,pl330", "arm,primecell"; | ||
| 253 | reg = <0x12690000 0x1000>; | ||
| 254 | interrupts = <0 139 0>; | ||
| 255 | clocks = <&cmu CLK_PDMA1>; | ||
| 256 | clock-names = "apb_pclk"; | ||
| 257 | #dma-cells = <1>; | ||
| 258 | #dma-channels = <8>; | ||
| 259 | #dma-requests = <32>; | ||
| 260 | }; | ||
| 261 | }; | ||
| 262 | |||
| 263 | adc: adc@126C0000 { | ||
| 264 | compatible = "samsung,exynos-adc-v3"; | ||
| 265 | reg = <0x126C0000 0x100>, <0x10020718 0x4>; | ||
| 266 | interrupts = <0 137 0>; | ||
| 267 | clock-names = "adc", "sclk_tsadc"; | ||
| 268 | clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; | ||
| 269 | #io-channel-cells = <1>; | ||
| 270 | io-channel-ranges; | ||
| 271 | status = "disabled"; | ||
| 272 | }; | ||
| 273 | |||
| 274 | serial_0: serial@13800000 { | ||
| 275 | compatible = "samsung,exynos4210-uart"; | ||
| 276 | reg = <0x13800000 0x100>; | ||
| 277 | interrupts = <0 109 0>; | ||
| 278 | clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; | ||
| 279 | clock-names = "uart", "clk_uart_baud0"; | ||
| 280 | status = "disabled"; | ||
| 281 | }; | ||
| 282 | |||
| 283 | serial_1: serial@13810000 { | ||
| 284 | compatible = "samsung,exynos4210-uart"; | ||
| 285 | reg = <0x13810000 0x100>; | ||
| 286 | interrupts = <0 110 0>; | ||
| 287 | clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; | ||
| 288 | clock-names = "uart", "clk_uart_baud0"; | ||
| 289 | status = "disabled"; | ||
| 290 | }; | ||
| 291 | |||
| 292 | i2c_0: i2c@13860000 { | ||
| 293 | #address-cells = <1>; | ||
| 294 | #size-cells = <0>; | ||
| 295 | compatible = "samsung,s3c2440-i2c"; | ||
| 296 | reg = <0x13860000 0x100>; | ||
| 297 | interrupts = <0 113 0>; | ||
| 298 | clocks = <&cmu CLK_I2C0>; | ||
| 299 | clock-names = "i2c"; | ||
| 300 | pinctrl-names = "default"; | ||
| 301 | pinctrl-0 = <&i2c0_bus>; | ||
| 302 | status = "disabled"; | ||
| 303 | }; | ||
| 304 | |||
| 305 | i2c_1: i2c@13870000 { | ||
| 306 | #address-cells = <1>; | ||
| 307 | #size-cells = <0>; | ||
| 308 | compatible = "samsung,s3c2440-i2c"; | ||
| 309 | reg = <0x13870000 0x100>; | ||
| 310 | interrupts = <0 114 0>; | ||
| 311 | clocks = <&cmu CLK_I2C1>; | ||
| 312 | clock-names = "i2c"; | ||
| 313 | pinctrl-names = "default"; | ||
| 314 | pinctrl-0 = <&i2c1_bus>; | ||
| 315 | status = "disabled"; | ||
| 316 | }; | ||
| 317 | |||
| 318 | i2c_2: i2c@13880000 { | ||
| 319 | #address-cells = <1>; | ||
| 320 | #size-cells = <0>; | ||
| 321 | compatible = "samsung,s3c2440-i2c"; | ||
| 322 | reg = <0x13880000 0x100>; | ||
| 323 | interrupts = <0 115 0>; | ||
| 324 | clocks = <&cmu CLK_I2C2>; | ||
| 325 | clock-names = "i2c"; | ||
| 326 | pinctrl-names = "default"; | ||
| 327 | pinctrl-0 = <&i2c2_bus>; | ||
| 328 | status = "disabled"; | ||
| 329 | }; | ||
| 330 | |||
| 331 | i2c_3: i2c@13890000 { | ||
| 332 | #address-cells = <1>; | ||
| 333 | #size-cells = <0>; | ||
| 334 | compatible = "samsung,s3c2440-i2c"; | ||
| 335 | reg = <0x13890000 0x100>; | ||
| 336 | interrupts = <0 116 0>; | ||
| 337 | clocks = <&cmu CLK_I2C3>; | ||
| 338 | clock-names = "i2c"; | ||
| 339 | pinctrl-names = "default"; | ||
| 340 | pinctrl-0 = <&i2c3_bus>; | ||
| 341 | status = "disabled"; | ||
| 342 | }; | ||
| 343 | |||
| 344 | i2c_4: i2c@138A0000 { | ||
| 345 | #address-cells = <1>; | ||
| 346 | #size-cells = <0>; | ||
| 347 | compatible = "samsung,s3c2440-i2c"; | ||
| 348 | reg = <0x138A0000 0x100>; | ||
| 349 | interrupts = <0 117 0>; | ||
| 350 | clocks = <&cmu CLK_I2C4>; | ||
| 351 | clock-names = "i2c"; | ||
| 352 | pinctrl-names = "default"; | ||
| 353 | pinctrl-0 = <&i2c4_bus>; | ||
| 354 | status = "disabled"; | ||
| 355 | }; | ||
| 356 | |||
| 357 | i2c_5: i2c@138B0000 { | ||
| 358 | #address-cells = <1>; | ||
| 359 | #size-cells = <0>; | ||
| 360 | compatible = "samsung,s3c2440-i2c"; | ||
| 361 | reg = <0x138B0000 0x100>; | ||
| 362 | interrupts = <0 118 0>; | ||
| 363 | clocks = <&cmu CLK_I2C5>; | ||
| 364 | clock-names = "i2c"; | ||
| 365 | pinctrl-names = "default"; | ||
| 366 | pinctrl-0 = <&i2c5_bus>; | ||
| 367 | status = "disabled"; | ||
| 368 | }; | ||
| 369 | |||
| 370 | i2c_6: i2c@138C0000 { | ||
| 371 | #address-cells = <1>; | ||
| 372 | #size-cells = <0>; | ||
| 373 | compatible = "samsung,s3c2440-i2c"; | ||
| 374 | reg = <0x138C0000 0x100>; | ||
| 375 | interrupts = <0 119 0>; | ||
| 376 | clocks = <&cmu CLK_I2C6>; | ||
| 377 | clock-names = "i2c"; | ||
| 378 | pinctrl-names = "default"; | ||
| 379 | pinctrl-0 = <&i2c6_bus>; | ||
| 380 | status = "disabled"; | ||
| 381 | }; | ||
| 382 | |||
| 383 | i2c_7: i2c@138D0000 { | ||
| 384 | #address-cells = <1>; | ||
| 385 | #size-cells = <0>; | ||
| 386 | compatible = "samsung,s3c2440-i2c"; | ||
| 387 | reg = <0x138D0000 0x100>; | ||
| 388 | interrupts = <0 120 0>; | ||
| 389 | clocks = <&cmu CLK_I2C7>; | ||
| 390 | clock-names = "i2c"; | ||
| 391 | pinctrl-names = "default"; | ||
| 392 | pinctrl-0 = <&i2c7_bus>; | ||
| 393 | status = "disabled"; | ||
| 394 | }; | ||
| 395 | |||
| 396 | spi_0: spi@13920000 { | ||
| 397 | compatible = "samsung,exynos4210-spi"; | ||
| 398 | reg = <0x13920000 0x100>; | ||
| 399 | interrupts = <0 121 0>; | ||
| 400 | dmas = <&pdma0 7>, <&pdma0 6>; | ||
| 401 | dma-names = "tx", "rx"; | ||
| 402 | #address-cells = <1>; | ||
| 403 | #size-cells = <0>; | ||
| 404 | clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; | ||
| 405 | clock-names = "spi", "spi_busclk0"; | ||
| 406 | samsung,spi-src-clk = <0>; | ||
| 407 | pinctrl-names = "default"; | ||
| 408 | pinctrl-0 = <&spi0_bus>; | ||
| 409 | status = "disabled"; | ||
| 410 | }; | ||
| 411 | |||
| 412 | spi_1: spi@13930000 { | ||
| 413 | compatible = "samsung,exynos4210-spi"; | ||
| 414 | reg = <0x13930000 0x100>; | ||
| 415 | interrupts = <0 122 0>; | ||
| 416 | dmas = <&pdma1 7>, <&pdma1 6>; | ||
| 417 | dma-names = "tx", "rx"; | ||
| 418 | #address-cells = <1>; | ||
| 419 | #size-cells = <0>; | ||
| 420 | clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; | ||
| 421 | clock-names = "spi", "spi_busclk0"; | ||
| 422 | samsung,spi-src-clk = <0>; | ||
| 423 | pinctrl-names = "default"; | ||
| 424 | pinctrl-0 = <&spi1_bus>; | ||
| 425 | status = "disabled"; | ||
| 426 | }; | ||
| 427 | |||
| 428 | pwm: pwm@139D0000 { | ||
| 429 | compatible = "samsung,exynos4210-pwm"; | ||
| 430 | reg = <0x139D0000 0x1000>; | ||
| 431 | interrupts = <0 104 0>, <0 105 0>, <0 106 0>, | ||
| 432 | <0 107 0>, <0 108 0>; | ||
| 433 | #pwm-cells = <3>; | ||
| 434 | status = "disabled"; | ||
| 435 | }; | ||
| 436 | |||
| 437 | pmu { | ||
| 438 | compatible = "arm,cortex-a7-pmu"; | ||
| 439 | interrupts = <0 18 0>, <0 19 0>; | ||
| 440 | }; | ||
| 441 | }; | ||
| 442 | }; | ||
| 443 | |||
| 444 | #include "exynos3250-pinctrl.dtsi" | ||
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 2f8bcd068d17..b8ece4be41ca 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | */ | 20 | */ |
| 21 | 21 | ||
| 22 | #include <dt-bindings/clock/exynos4.h> | 22 | #include <dt-bindings/clock/exynos4.h> |
| 23 | #include <dt-bindings/clock/exynos-audss-clk.h> | ||
| 23 | #include "skeleton.dtsi" | 24 | #include "skeleton.dtsi" |
| 24 | 25 | ||
| 25 | / { | 26 | / { |
| @@ -45,6 +46,23 @@ | |||
| 45 | fimc3 = &fimc_3; | 46 | fimc3 = &fimc_3; |
| 46 | }; | 47 | }; |
| 47 | 48 | ||
| 49 | clock_audss: clock-controller@03810000 { | ||
| 50 | compatible = "samsung,exynos4210-audss-clock"; | ||
| 51 | reg = <0x03810000 0x0C>; | ||
| 52 | #clock-cells = <1>; | ||
| 53 | }; | ||
| 54 | |||
| 55 | i2s0: i2s@03830000 { | ||
| 56 | compatible = "samsung,s5pv210-i2s"; | ||
| 57 | reg = <0x03830000 0x100>; | ||
| 58 | clocks = <&clock_audss EXYNOS_I2S_BUS>; | ||
| 59 | clock-names = "iis"; | ||
| 60 | dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>; | ||
| 61 | dma-names = "tx", "rx", "tx-sec"; | ||
| 62 | samsung,idma-addr = <0x03000000>; | ||
| 63 | status = "disabled"; | ||
| 64 | }; | ||
| 65 | |||
| 48 | chipid@10000000 { | 66 | chipid@10000000 { |
| 49 | compatible = "samsung,exynos4210-chipid"; | 67 | compatible = "samsung,exynos4210-chipid"; |
| 50 | reg = <0x10000000 0x100>; | 68 | reg = <0x10000000 0x100>; |
| @@ -110,6 +128,11 @@ | |||
| 110 | reg = <0x10010000 0x400>; | 128 | reg = <0x10010000 0x400>; |
| 111 | }; | 129 | }; |
| 112 | 130 | ||
| 131 | pmu_system_controller: system-controller@10020000 { | ||
| 132 | compatible = "samsung,exynos4210-pmu", "syscon"; | ||
| 133 | reg = <0x10020000 0x4000>; | ||
| 134 | }; | ||
| 135 | |||
| 113 | dsi_0: dsi@11C80000 { | 136 | dsi_0: dsi@11C80000 { |
| 114 | compatible = "samsung,exynos4210-mipi-dsi"; | 137 | compatible = "samsung,exynos4210-mipi-dsi"; |
| 115 | reg = <0x11C80000 0x10000>; | 138 | reg = <0x11C80000 0x10000>; |
| @@ -117,7 +140,7 @@ | |||
| 117 | samsung,power-domain = <&pd_lcd0>; | 140 | samsung,power-domain = <&pd_lcd0>; |
| 118 | phys = <&mipi_phy 1>; | 141 | phys = <&mipi_phy 1>; |
| 119 | phy-names = "dsim"; | 142 | phy-names = "dsim"; |
| 120 | clocks = <&clock 286>, <&clock 143>; | 143 | clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; |
| 121 | clock-names = "bus_clk", "pll_clk"; | 144 | clock-names = "bus_clk", "pll_clk"; |
| 122 | status = "disabled"; | 145 | status = "disabled"; |
| 123 | #address-cells = <1>; | 146 | #address-cells = <1>; |
| @@ -129,12 +152,10 @@ | |||
| 129 | status = "disabled"; | 152 | status = "disabled"; |
| 130 | #address-cells = <1>; | 153 | #address-cells = <1>; |
| 131 | #size-cells = <1>; | 154 | #size-cells = <1>; |
| 155 | #clock-cells = <1>; | ||
| 156 | clock-output-names = "cam_a_clkout", "cam_b_clkout"; | ||
| 132 | ranges; | 157 | ranges; |
| 133 | 158 | ||
| 134 | clock_cam: clock-controller { | ||
| 135 | #clock-cells = <1>; | ||
| 136 | }; | ||
| 137 | |||
| 138 | fimc_0: fimc@11800000 { | 159 | fimc_0: fimc@11800000 { |
| 139 | compatible = "samsung,exynos4210-fimc"; | 160 | compatible = "samsung,exynos4210-fimc"; |
| 140 | reg = <0x11800000 0x1000>; | 161 | reg = <0x11800000 0x1000>; |
| @@ -273,6 +294,27 @@ | |||
| 273 | status = "disabled"; | 294 | status = "disabled"; |
| 274 | }; | 295 | }; |
| 275 | 296 | ||
| 297 | exynos_usbphy: exynos-usbphy@125B0000 { | ||
| 298 | compatible = "samsung,exynos4210-usb2-phy"; | ||
| 299 | reg = <0x125B0000 0x100>; | ||
| 300 | samsung,pmureg-phandle = <&pmu_system_controller>; | ||
| 301 | clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; | ||
| 302 | clock-names = "phy", "ref"; | ||
| 303 | #phy-cells = <1>; | ||
| 304 | status = "disabled"; | ||
| 305 | }; | ||
| 306 | |||
| 307 | hsotg@12480000 { | ||
| 308 | compatible = "samsung,s3c6400-hsotg"; | ||
| 309 | reg = <0x12480000 0x20000>; | ||
| 310 | interrupts = <0 71 0>; | ||
| 311 | clocks = <&clock CLK_USB_DEVICE>; | ||
| 312 | clock-names = "otg"; | ||
| 313 | phys = <&exynos_usbphy 0>; | ||
| 314 | phy-names = "usb2-phy"; | ||
| 315 | status = "disabled"; | ||
| 316 | }; | ||
| 317 | |||
| 276 | ehci@12580000 { | 318 | ehci@12580000 { |
| 277 | compatible = "samsung,exynos4210-ehci"; | 319 | compatible = "samsung,exynos4210-ehci"; |
| 278 | reg = <0x12580000 0x100>; | 320 | reg = <0x12580000 0x100>; |
| @@ -291,6 +333,26 @@ | |||
| 291 | status = "disabled"; | 333 | status = "disabled"; |
| 292 | }; | 334 | }; |
| 293 | 335 | ||
| 336 | i2s1: i2s@13960000 { | ||
| 337 | compatible = "samsung,s5pv210-i2s"; | ||
| 338 | reg = <0x13960000 0x100>; | ||
| 339 | clocks = <&clock CLK_I2S1>; | ||
| 340 | clock-names = "iis"; | ||
| 341 | dmas = <&pdma1 12>, <&pdma1 11>; | ||
| 342 | dma-names = "tx", "rx"; | ||
| 343 | status = "disabled"; | ||
| 344 | }; | ||
| 345 | |||
| 346 | i2s2: i2s@13970000 { | ||
| 347 | compatible = "samsung,s5pv210-i2s"; | ||
| 348 | reg = <0x13970000 0x100>; | ||
| 349 | clocks = <&clock CLK_I2S2>; | ||
| 350 | clock-names = "iis"; | ||
| 351 | dmas = <&pdma0 14>, <&pdma0 13>; | ||
| 352 | dma-names = "tx", "rx"; | ||
| 353 | status = "disabled"; | ||
| 354 | }; | ||
| 355 | |||
| 294 | mfc: codec@13400000 { | 356 | mfc: codec@13400000 { |
| 295 | compatible = "samsung,mfc-v5"; | 357 | compatible = "samsung,mfc-v5"; |
| 296 | reg = <0x13400000 0x10000>; | 358 | reg = <0x13400000 0x10000>; |
| @@ -371,6 +433,8 @@ | |||
| 371 | interrupts = <0 60 0>; | 433 | interrupts = <0 60 0>; |
| 372 | clocks = <&clock CLK_I2C2>; | 434 | clocks = <&clock CLK_I2C2>; |
| 373 | clock-names = "i2c"; | 435 | clock-names = "i2c"; |
| 436 | pinctrl-names = "default"; | ||
| 437 | pinctrl-0 = <&i2c2_bus>; | ||
| 374 | status = "disabled"; | 438 | status = "disabled"; |
| 375 | }; | 439 | }; |
| 376 | 440 | ||
| @@ -382,6 +446,8 @@ | |||
| 382 | interrupts = <0 61 0>; | 446 | interrupts = <0 61 0>; |
| 383 | clocks = <&clock CLK_I2C3>; | 447 | clocks = <&clock CLK_I2C3>; |
| 384 | clock-names = "i2c"; | 448 | clock-names = "i2c"; |
| 449 | pinctrl-names = "default"; | ||
| 450 | pinctrl-0 = <&i2c3_bus>; | ||
| 385 | status = "disabled"; | 451 | status = "disabled"; |
| 386 | }; | 452 | }; |
| 387 | 453 | ||
| @@ -393,6 +459,8 @@ | |||
| 393 | interrupts = <0 62 0>; | 459 | interrupts = <0 62 0>; |
| 394 | clocks = <&clock CLK_I2C4>; | 460 | clocks = <&clock CLK_I2C4>; |
| 395 | clock-names = "i2c"; | 461 | clock-names = "i2c"; |
| 462 | pinctrl-names = "default"; | ||
| 463 | pinctrl-0 = <&i2c4_bus>; | ||
| 396 | status = "disabled"; | 464 | status = "disabled"; |
| 397 | }; | 465 | }; |
| 398 | 466 | ||
| @@ -404,6 +472,8 @@ | |||
| 404 | interrupts = <0 63 0>; | 472 | interrupts = <0 63 0>; |
| 405 | clocks = <&clock CLK_I2C5>; | 473 | clocks = <&clock CLK_I2C5>; |
| 406 | clock-names = "i2c"; | 474 | clock-names = "i2c"; |
| 475 | pinctrl-names = "default"; | ||
| 476 | pinctrl-0 = <&i2c5_bus>; | ||
| 407 | status = "disabled"; | 477 | status = "disabled"; |
| 408 | }; | 478 | }; |
| 409 | 479 | ||
| @@ -415,6 +485,8 @@ | |||
| 415 | interrupts = <0 64 0>; | 485 | interrupts = <0 64 0>; |
| 416 | clocks = <&clock CLK_I2C6>; | 486 | clocks = <&clock CLK_I2C6>; |
| 417 | clock-names = "i2c"; | 487 | clock-names = "i2c"; |
| 488 | pinctrl-names = "default"; | ||
| 489 | pinctrl-0 = <&i2c6_bus>; | ||
| 418 | status = "disabled"; | 490 | status = "disabled"; |
| 419 | }; | 491 | }; |
| 420 | 492 | ||
| @@ -426,6 +498,8 @@ | |||
| 426 | interrupts = <0 65 0>; | 498 | interrupts = <0 65 0>; |
| 427 | clocks = <&clock CLK_I2C7>; | 499 | clocks = <&clock CLK_I2C7>; |
| 428 | clock-names = "i2c"; | 500 | clock-names = "i2c"; |
| 501 | pinctrl-names = "default"; | ||
| 502 | pinctrl-0 = <&i2c7_bus>; | ||
| 429 | status = "disabled"; | 503 | status = "disabled"; |
| 430 | }; | 504 | }; |
| 431 | 505 | ||
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 72fb11f7ea21..f767c425d0b5 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | 16 | ||
| 17 | /dts-v1/; | 17 | /dts-v1/; |
| 18 | #include "exynos4210.dtsi" | 18 | #include "exynos4210.dtsi" |
| 19 | #include <dt-bindings/input/input.h> | ||
| 19 | 20 | ||
| 20 | / { | 21 | / { |
| 21 | model = "Insignal Origen evaluation board based on Exynos4210"; | 22 | model = "Insignal Origen evaluation board based on Exynos4210"; |
| @@ -48,6 +49,14 @@ | |||
| 48 | }; | 49 | }; |
| 49 | }; | 50 | }; |
| 50 | 51 | ||
| 52 | watchdog@10060000 { | ||
| 53 | status = "okay"; | ||
| 54 | }; | ||
| 55 | |||
| 56 | rtc@10070000 { | ||
| 57 | status = "okay"; | ||
| 58 | }; | ||
| 59 | |||
| 51 | tmu@100C0000 { | 60 | tmu@100C0000 { |
| 52 | status = "okay"; | 61 | status = "okay"; |
| 53 | }; | 62 | }; |
| @@ -251,35 +260,35 @@ | |||
| 251 | up { | 260 | up { |
| 252 | label = "Up"; | 261 | label = "Up"; |
| 253 | gpios = <&gpx2 0 1>; | 262 | gpios = <&gpx2 0 1>; |
| 254 | linux,code = <103>; | 263 | linux,code = <KEY_UP>; |
| 255 | gpio-key,wakeup; | 264 | gpio-key,wakeup; |
| 256 | }; | 265 | }; |
| 257 | 266 | ||
| 258 | down { | 267 | down { |
| 259 | label = "Down"; | 268 | label = "Down"; |
| 260 | gpios = <&gpx2 1 1>; | 269 | gpios = <&gpx2 1 1>; |
| 261 | linux,code = <108>; | 270 | linux,code = <KEY_DOWN>; |
| 262 | gpio-key,wakeup; | 271 | gpio-key,wakeup; |
| 263 | }; | 272 | }; |
| 264 | 273 | ||
| 265 | back { | 274 | back { |
| 266 | label = "Back"; | 275 | label = "Back"; |
| 267 | gpios = <&gpx1 7 1>; | 276 | gpios = <&gpx1 7 1>; |
| 268 | linux,code = <158>; | 277 | linux,code = <KEY_BACK>; |
| 269 | gpio-key,wakeup; | 278 | gpio-key,wakeup; |
| 270 | }; | 279 | }; |
| 271 | 280 | ||
| 272 | home { | 281 | home { |
| 273 | label = "Home"; | 282 | label = "Home"; |
| 274 | gpios = <&gpx1 6 1>; | 283 | gpios = <&gpx1 6 1>; |
| 275 | linux,code = <102>; | 284 | linux,code = <KEY_HOME>; |
| 276 | gpio-key,wakeup; | 285 | gpio-key,wakeup; |
| 277 | }; | 286 | }; |
| 278 | 287 | ||
| 279 | menu { | 288 | menu { |
| 280 | label = "Menu"; | 289 | label = "Menu"; |
| 281 | gpios = <&gpx1 5 1>; | 290 | gpios = <&gpx1 5 1>; |
| 282 | linux,code = <139>; | 291 | linux,code = <KEY_MENU>; |
| 283 | gpio-key,wakeup; | 292 | gpio-key,wakeup; |
| 284 | }; | 293 | }; |
| 285 | }; | 294 | }; |
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 63aa2bb24a4b..f516da9e8b3a 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts | |||
| @@ -88,6 +88,12 @@ | |||
| 88 | }; | 88 | }; |
| 89 | }; | 89 | }; |
| 90 | 90 | ||
| 91 | hsotg@12480000 { | ||
| 92 | vusb_d-supply = <&vusb_reg>; | ||
| 93 | vusb_a-supply = <&vusbdac_reg>; | ||
| 94 | status = "okay"; | ||
| 95 | }; | ||
| 96 | |||
| 91 | sdhci_emmc: sdhci@12510000 { | 97 | sdhci_emmc: sdhci@12510000 { |
| 92 | bus-width = <8>; | 98 | bus-width = <8>; |
| 93 | non-removable; | 99 | non-removable; |
| @@ -97,6 +103,10 @@ | |||
| 97 | status = "okay"; | 103 | status = "okay"; |
| 98 | }; | 104 | }; |
| 99 | 105 | ||
| 106 | exynos-usbphy@125B0000 { | ||
| 107 | status = "okay"; | ||
| 108 | }; | ||
| 109 | |||
| 100 | serial@13800000 { | 110 | serial@13800000 { |
| 101 | status = "okay"; | 111 | status = "okay"; |
| 102 | }; | 112 | }; |
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 63e34b24b04f..d50eb3aa708e 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts | |||
| @@ -28,6 +28,21 @@ | |||
| 28 | bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; | 28 | bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; |
| 29 | }; | 29 | }; |
| 30 | 30 | ||
| 31 | sysram@02020000 { | ||
| 32 | smp-sysram@0 { | ||
| 33 | status = "disabled"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | smp-sysram@5000 { | ||
| 37 | compatible = "samsung,exynos4210-sysram"; | ||
| 38 | reg = <0x5000 0x1000>; | ||
| 39 | }; | ||
| 40 | |||
| 41 | smp-sysram@1f000 { | ||
| 42 | status = "disabled"; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | |||
| 31 | mct@10050000 { | 46 | mct@10050000 { |
| 32 | compatible = "none"; | 47 | compatible = "none"; |
| 33 | }; | 48 | }; |
| @@ -53,6 +68,12 @@ | |||
| 53 | enable-active-high; | 68 | enable-active-high; |
| 54 | }; | 69 | }; |
| 55 | 70 | ||
| 71 | hsotg@12480000 { | ||
| 72 | vusb_d-supply = <&ldo3_reg>; | ||
| 73 | vusb_a-supply = <&ldo8_reg>; | ||
| 74 | status = "okay"; | ||
| 75 | }; | ||
| 76 | |||
| 56 | sdhci_emmc: sdhci@12510000 { | 77 | sdhci_emmc: sdhci@12510000 { |
| 57 | bus-width = <8>; | 78 | bus-width = <8>; |
| 58 | non-removable; | 79 | non-removable; |
| @@ -62,6 +83,34 @@ | |||
| 62 | status = "okay"; | 83 | status = "okay"; |
| 63 | }; | 84 | }; |
| 64 | 85 | ||
| 86 | sdhci_sd: sdhci@12530000 { | ||
| 87 | bus-width = <4>; | ||
| 88 | pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; | ||
| 89 | pinctrl-names = "default"; | ||
| 90 | vmmc-supply = <&ldo5_reg>; | ||
| 91 | cd-gpios = <&gpx3 4 0>; | ||
| 92 | cd-inverted; | ||
| 93 | status = "okay"; | ||
| 94 | }; | ||
| 95 | |||
| 96 | ehci@12580000 { | ||
| 97 | status = "okay"; | ||
| 98 | port@0 { | ||
| 99 | status = "okay"; | ||
| 100 | }; | ||
| 101 | }; | ||
| 102 | |||
| 103 | ohci@12590000 { | ||
| 104 | status = "okay"; | ||
| 105 | port@0 { | ||
| 106 | status = "okay"; | ||
| 107 | }; | ||
| 108 | }; | ||
| 109 | |||
| 110 | exynos-usbphy@125B0000 { | ||
| 111 | status = "okay"; | ||
| 112 | }; | ||
| 113 | |||
| 65 | serial@13800000 { | 114 | serial@13800000 { |
| 66 | status = "okay"; | 115 | status = "okay"; |
| 67 | }; | 116 | }; |
| @@ -201,6 +250,7 @@ | |||
| 201 | regulator-name = "VUSB+MIPI_1.1V"; | 250 | regulator-name = "VUSB+MIPI_1.1V"; |
| 202 | regulator-min-microvolt = <1100000>; | 251 | regulator-min-microvolt = <1100000>; |
| 203 | regulator-max-microvolt = <1100000>; | 252 | regulator-max-microvolt = <1100000>; |
| 253 | regulator-always-on; | ||
| 204 | }; | 254 | }; |
| 205 | 255 | ||
| 206 | ldo4_reg: LDO4 { | 256 | ldo4_reg: LDO4 { |
| @@ -231,6 +281,7 @@ | |||
| 231 | regulator-name = "VUSB+VDAC_3.3V"; | 281 | regulator-name = "VUSB+VDAC_3.3V"; |
| 232 | regulator-min-microvolt = <3300000>; | 282 | regulator-min-microvolt = <3300000>; |
| 233 | regulator-max-microvolt = <3300000>; | 283 | regulator-max-microvolt = <3300000>; |
| 284 | regulator-always-on; | ||
| 234 | }; | 285 | }; |
| 235 | 286 | ||
| 236 | ldo9_reg: LDO9 { | 287 | ldo9_reg: LDO9 { |
| @@ -413,6 +464,29 @@ | |||
| 413 | compatible = "samsung,s5p6440-pwm"; | 464 | compatible = "samsung,s5p6440-pwm"; |
| 414 | status = "okay"; | 465 | status = "okay"; |
| 415 | }; | 466 | }; |
| 467 | |||
| 468 | camera { | ||
| 469 | status = "okay"; | ||
| 470 | |||
| 471 | pinctrl-names = "default"; | ||
| 472 | pinctrl-0 = <>; | ||
| 473 | |||
| 474 | fimc_0: fimc@11800000 { | ||
| 475 | status = "okay"; | ||
| 476 | }; | ||
| 477 | |||
| 478 | fimc_1: fimc@11810000 { | ||
| 479 | status = "okay"; | ||
| 480 | }; | ||
| 481 | |||
| 482 | fimc_2: fimc@11820000 { | ||
| 483 | status = "okay"; | ||
| 484 | }; | ||
| 485 | |||
| 486 | fimc_3: fimc@11830000 { | ||
| 487 | status = "okay"; | ||
| 488 | }; | ||
| 489 | }; | ||
| 416 | }; | 490 | }; |
| 417 | 491 | ||
| 418 | &mdma1 { | 492 | &mdma1 { |
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index cacf6140dd2f..ee3001f38821 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi | |||
| @@ -31,6 +31,24 @@ | |||
| 31 | pinctrl2 = &pinctrl_2; | 31 | pinctrl2 = &pinctrl_2; |
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| 34 | sysram@02020000 { | ||
| 35 | compatible = "mmio-sram"; | ||
| 36 | reg = <0x02020000 0x20000>; | ||
| 37 | #address-cells = <1>; | ||
| 38 | #size-cells = <1>; | ||
| 39 | ranges = <0 0x02020000 0x20000>; | ||
| 40 | |||
| 41 | smp-sysram@0 { | ||
| 42 | compatible = "samsung,exynos4210-sysram"; | ||
| 43 | reg = <0x0 0x1000>; | ||
| 44 | }; | ||
| 45 | |||
| 46 | smp-sysram@1f000 { | ||
| 47 | compatible = "samsung,exynos4210-sysram-ns"; | ||
| 48 | reg = <0x1f000 0x1000>; | ||
| 49 | }; | ||
| 50 | }; | ||
| 51 | |||
| 34 | pd_lcd1: lcd1-power-domain@10023CA0 { | 52 | pd_lcd1: lcd1-power-domain@10023CA0 { |
| 35 | compatible = "samsung,exynos4210-pd"; | 53 | compatible = "samsung,exynos4210-pd"; |
| 36 | reg = <0x10023CA0 0x20>; | 54 | reg = <0x10023CA0 0x20>; |
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index e2c0dcab4d81..e925c9fbfb07 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | 14 | ||
| 15 | /dts-v1/; | 15 | /dts-v1/; |
| 16 | #include "exynos4412.dtsi" | 16 | #include "exynos4412.dtsi" |
| 17 | #include <dt-bindings/input/input.h> | ||
| 17 | 18 | ||
| 18 | / { | 19 | / { |
| 19 | model = "Insignal Origen evaluation board based on Exynos4412"; | 20 | model = "Insignal Origen evaluation board based on Exynos4412"; |
| @@ -48,6 +49,14 @@ | |||
| 48 | }; | 49 | }; |
| 49 | }; | 50 | }; |
| 50 | 51 | ||
| 52 | watchdog@10060000 { | ||
| 53 | status = "okay"; | ||
| 54 | }; | ||
| 55 | |||
| 56 | rtc@10070000 { | ||
| 57 | status = "okay"; | ||
| 58 | }; | ||
| 59 | |||
| 51 | pinctrl@11000000 { | 60 | pinctrl@11000000 { |
| 52 | keypad_rows: keypad-rows { | 61 | keypad_rows: keypad-rows { |
| 53 | samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; | 62 | samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; |
| @@ -76,37 +85,37 @@ | |||
| 76 | key_home { | 85 | key_home { |
| 77 | keypad,row = <0>; | 86 | keypad,row = <0>; |
| 78 | keypad,column = <0>; | 87 | keypad,column = <0>; |
| 79 | linux,code = <102>; | 88 | linux,code = <KEY_HOME>; |
| 80 | }; | 89 | }; |
| 81 | 90 | ||
| 82 | key_down { | 91 | key_down { |
| 83 | keypad,row = <0>; | 92 | keypad,row = <0>; |
| 84 | keypad,column = <1>; | 93 | keypad,column = <1>; |
| 85 | linux,code = <108>; | 94 | linux,code = <KEY_DOWN>; |
| 86 | }; | 95 | }; |
| 87 | 96 | ||
| 88 | key_up { | 97 | key_up { |
| 89 | keypad,row = <1>; | 98 | keypad,row = <1>; |
| 90 | keypad,column = <0>; | 99 | keypad,column = <0>; |
| 91 | linux,code = <103>; | 100 | linux,code = <KEY_UP>; |
| 92 | }; | 101 | }; |
| 93 | 102 | ||
| 94 | key_menu { | 103 | key_menu { |
| 95 | keypad,row = <1>; | 104 | keypad,row = <1>; |
| 96 | keypad,column = <1>; | 105 | keypad,column = <1>; |
| 97 | linux,code = <139>; | 106 | linux,code = <KEY_MENU>; |
| 98 | }; | 107 | }; |
| 99 | 108 | ||
| 100 | key_back { | 109 | key_back { |
| 101 | keypad,row = <2>; | 110 | keypad,row = <2>; |
| 102 | keypad,column = <0>; | 111 | keypad,column = <0>; |
| 103 | linux,code = <158>; | 112 | linux,code = <KEY_BACK>; |
| 104 | }; | 113 | }; |
| 105 | 114 | ||
| 106 | key_enter { | 115 | key_enter { |
| 107 | keypad,row = <2>; | 116 | keypad,row = <2>; |
| 108 | keypad,column = <1>; | 117 | keypad,column = <1>; |
| 109 | linux,code = <28>; | 118 | linux,code = <KEY_ENTER>; |
| 110 | }; | 119 | }; |
| 111 | }; | 120 | }; |
| 112 | 121 | ||
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 8a558b7ac999..77878447b312 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts | |||
| @@ -20,7 +20,8 @@ | |||
| 20 | compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4"; | 20 | compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4"; |
| 21 | 21 | ||
| 22 | aliases { | 22 | aliases { |
| 23 | i2c8 = &i2c_ak8975; | 23 | i2c9 = &i2c_ak8975; |
| 24 | i2c10 = &i2c_cm36651; | ||
| 24 | }; | 25 | }; |
| 25 | 26 | ||
| 26 | memory { | 27 | memory { |
| @@ -80,39 +81,67 @@ | |||
| 80 | enable-active-high; | 81 | enable-active-high; |
| 81 | }; | 82 | }; |
| 82 | 83 | ||
| 83 | /* More to come */ | 84 | cam_af_reg: voltage-regulator-3 { |
| 85 | compatible = "regulator-fixed"; | ||
| 86 | regulator-name = "CAM_AF"; | ||
| 87 | regulator-min-microvolt = <2800000>; | ||
| 88 | regulator-max-microvolt = <2800000>; | ||
| 89 | gpio = <&gpm0 4 0>; | ||
| 90 | enable-active-high; | ||
| 91 | }; | ||
| 92 | |||
| 93 | cam_isp_core_reg: voltage-regulator-4 { | ||
| 94 | compatible = "regulator-fixed"; | ||
| 95 | regulator-name = "CAM_ISP_CORE_1.2V_EN"; | ||
| 96 | regulator-min-microvolt = <1200000>; | ||
| 97 | regulator-max-microvolt = <1200000>; | ||
| 98 | gpio = <&gpm0 3 0>; | ||
| 99 | enable-active-high; | ||
| 100 | regulator-always-on; | ||
| 101 | }; | ||
| 102 | |||
| 103 | ps_als_reg: voltage-regulator-5 { | ||
| 104 | compatible = "regulator-fixed"; | ||
| 105 | regulator-name = "LED_A_3.0V"; | ||
| 106 | regulator-min-microvolt = <3000000>; | ||
| 107 | regulator-max-microvolt = <3000000>; | ||
| 108 | gpio = <&gpj0 5 0>; | ||
| 109 | enable-active-high; | ||
| 110 | }; | ||
| 84 | }; | 111 | }; |
| 85 | 112 | ||
| 86 | gpio-keys { | 113 | gpio-keys { |
| 87 | compatible = "gpio-keys"; | 114 | compatible = "gpio-keys"; |
| 88 | 115 | ||
| 89 | key-down { | 116 | key-down { |
| 90 | interrupt-parent = <&gpj1>; | 117 | gpios = <&gpx3 3 1>; |
| 91 | interrupts = <2 0>; | ||
| 92 | gpios = <&gpj1 2 1>; | ||
| 93 | linux,code = <114>; | 118 | linux,code = <114>; |
| 94 | label = "volume down"; | 119 | label = "volume down"; |
| 95 | debounce-interval = <10>; | 120 | debounce-interval = <10>; |
| 96 | }; | 121 | }; |
| 97 | 122 | ||
| 98 | key-up { | 123 | key-up { |
| 99 | interrupt-parent = <&gpj1>; | 124 | gpios = <&gpx2 2 1>; |
| 100 | interrupts = <1 0>; | ||
| 101 | gpios = <&gpj1 1 1>; | ||
| 102 | linux,code = <115>; | 125 | linux,code = <115>; |
| 103 | label = "volume up"; | 126 | label = "volume up"; |
| 104 | debounce-interval = <10>; | 127 | debounce-interval = <10>; |
| 105 | }; | 128 | }; |
| 106 | 129 | ||
| 107 | key-power { | 130 | key-power { |
| 108 | interrupt-parent = <&gpx2>; | ||
| 109 | interrupts = <7 0>; | ||
| 110 | gpios = <&gpx2 7 1>; | 131 | gpios = <&gpx2 7 1>; |
| 111 | linux,code = <116>; | 132 | linux,code = <116>; |
| 112 | label = "power"; | 133 | label = "power"; |
| 113 | debounce-interval = <10>; | 134 | debounce-interval = <10>; |
| 114 | gpio-key,wakeup; | 135 | gpio-key,wakeup; |
| 115 | }; | 136 | }; |
| 137 | |||
| 138 | key-ok { | ||
| 139 | gpios = <&gpx0 1 1>; | ||
| 140 | linux,code = <139>; | ||
| 141 | label = "ok"; | ||
| 142 | debounce-inteval = <10>; | ||
| 143 | gpio-key,wakeup; | ||
| 144 | }; | ||
| 116 | }; | 145 | }; |
| 117 | 146 | ||
| 118 | adc: adc@126C0000 { | 147 | adc: adc@126C0000 { |
| @@ -140,6 +169,38 @@ | |||
| 140 | }; | 169 | }; |
| 141 | }; | 170 | }; |
| 142 | 171 | ||
| 172 | i2c_0: i2c@13860000 { | ||
| 173 | samsung,i2c-sda-delay = <100>; | ||
| 174 | samsung,i2c-slave-addr = <0x10>; | ||
| 175 | samsung,i2c-max-bus-freq = <400000>; | ||
| 176 | pinctrl-0 = <&i2c0_bus>; | ||
| 177 | pinctrl-names = "default"; | ||
| 178 | status = "okay"; | ||
| 179 | |||
| 180 | s5c73m3@3c { | ||
| 181 | compatible = "samsung,s5c73m3"; | ||
| 182 | reg = <0x3c>; | ||
| 183 | standby-gpios = <&gpm0 1 1>; /* ISP_STANDBY */ | ||
| 184 | xshutdown-gpios = <&gpf1 3 1>; /* ISP_RESET */ | ||
| 185 | vdd-int-supply = <&buck9_reg>; | ||
| 186 | vddio-cis-supply = <&ldo9_reg>; | ||
| 187 | vdda-supply = <&ldo17_reg>; | ||
| 188 | vddio-host-supply = <&ldo18_reg>; | ||
| 189 | vdd-af-supply = <&cam_af_reg>; | ||
| 190 | vdd-reg-supply = <&cam_io_reg>; | ||
| 191 | clock-frequency = <24000000>; | ||
| 192 | /* CAM_A_CLKOUT */ | ||
| 193 | clocks = <&camera 0>; | ||
| 194 | clock-names = "cis_extclk"; | ||
| 195 | port { | ||
| 196 | s5c73m3_ep: endpoint { | ||
| 197 | remote-endpoint = <&csis0_ep>; | ||
| 198 | data-lanes = <1 2 3 4>; | ||
| 199 | }; | ||
| 200 | }; | ||
| 201 | }; | ||
| 202 | }; | ||
| 203 | |||
| 143 | i2c@138D0000 { | 204 | i2c@138D0000 { |
| 144 | samsung,i2c-sda-delay = <100>; | 205 | samsung,i2c-sda-delay = <100>; |
| 145 | samsung,i2c-slave-addr = <0x10>; | 206 | samsung,i2c-slave-addr = <0x10>; |
| @@ -509,6 +570,22 @@ | |||
| 509 | }; | 570 | }; |
| 510 | }; | 571 | }; |
| 511 | 572 | ||
| 573 | i2c_cm36651: i2c-gpio-2 { | ||
| 574 | compatible = "i2c-gpio"; | ||
| 575 | gpios = <&gpf0 0 1>, <&gpf0 1 1>; | ||
| 576 | i2c-gpio,delay-us = <2>; | ||
| 577 | #address-cells = <1>; | ||
| 578 | #size-cells = <0>; | ||
| 579 | |||
| 580 | cm36651@18 { | ||
| 581 | compatible = "capella,cm36651"; | ||
| 582 | reg = <0x18>; | ||
| 583 | interrupt-parent = <&gpx0>; | ||
| 584 | interrupts = <2 2>; | ||
| 585 | vled-supply = <&ps_als_reg>; | ||
| 586 | }; | ||
| 587 | }; | ||
| 588 | |||
| 512 | spi_1: spi@13930000 { | 589 | spi_1: spi@13930000 { |
| 513 | pinctrl-names = "default"; | 590 | pinctrl-names = "default"; |
| 514 | pinctrl-0 = <&spi1_bus>; | 591 | pinctrl-0 = <&spi1_bus>; |
| @@ -586,8 +663,8 @@ | |||
| 586 | status = "okay"; | 663 | status = "okay"; |
| 587 | }; | 664 | }; |
| 588 | 665 | ||
| 589 | camera { | 666 | camera: camera { |
| 590 | pinctrl-0 = <&cam_port_b_clk_active>; | 667 | pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; |
| 591 | pinctrl-names = "default"; | 668 | pinctrl-names = "default"; |
| 592 | status = "okay"; | 669 | status = "okay"; |
| 593 | 670 | ||
| @@ -607,6 +684,23 @@ | |||
| 607 | status = "okay"; | 684 | status = "okay"; |
| 608 | }; | 685 | }; |
| 609 | 686 | ||
| 687 | csis_0: csis@11880000 { | ||
| 688 | status = "okay"; | ||
| 689 | vddcore-supply = <&ldo8_reg>; | ||
| 690 | vddio-supply = <&ldo10_reg>; | ||
| 691 | clock-frequency = <176000000>; | ||
| 692 | |||
| 693 | /* Camera C (3) MIPI CSI-2 (CSIS0) */ | ||
| 694 | port@3 { | ||
| 695 | reg = <3>; | ||
| 696 | csis0_ep: endpoint { | ||
| 697 | remote-endpoint = <&s5c73m3_ep>; | ||
| 698 | data-lanes = <1 2 3 4>; | ||
| 699 | samsung,csis-hs-settle = <12>; | ||
| 700 | }; | ||
| 701 | }; | ||
| 702 | }; | ||
| 703 | |||
| 610 | csis_1: csis@11890000 { | 704 | csis_1: csis@11890000 { |
| 611 | vddcore-supply = <&ldo8_reg>; | 705 | vddcore-supply = <&ldo8_reg>; |
| 612 | vddio-supply = <&ldo10_reg>; | 706 | vddio-supply = <&ldo10_reg>; |
| @@ -647,10 +741,11 @@ | |||
| 647 | reg = <0x10>; | 741 | reg = <0x10>; |
| 648 | svdda-supply = <&cam_io_reg>; | 742 | svdda-supply = <&cam_io_reg>; |
| 649 | svddio-supply = <&ldo19_reg>; | 743 | svddio-supply = <&ldo19_reg>; |
| 744 | afvdd-supply = <&ldo19_reg>; | ||
| 650 | clock-frequency = <24000000>; | 745 | clock-frequency = <24000000>; |
| 651 | /* CAM_B_CLKOUT */ | 746 | /* CAM_B_CLKOUT */ |
| 652 | clocks = <&clock_cam 1>; | 747 | clocks = <&camera 1>; |
| 653 | clock-names = "mclk"; | 748 | clock-names = "extclk"; |
| 654 | samsung,camclk-out = <1>; | 749 | samsung,camclk-out = <1>; |
| 655 | gpios = <&gpm1 6 0>; | 750 | gpios = <&gpm1 6 0>; |
| 656 | 751 | ||
| @@ -665,6 +760,16 @@ | |||
| 665 | }; | 760 | }; |
| 666 | }; | 761 | }; |
| 667 | 762 | ||
| 763 | exynos-usbphy@125B0000 { | ||
| 764 | status = "okay"; | ||
| 765 | }; | ||
| 766 | |||
| 767 | hsotg@12480000 { | ||
| 768 | vusb_d-supply = <&ldo15_reg>; | ||
| 769 | vusb_a-supply = <&ldo12_reg>; | ||
| 770 | status = "okay"; | ||
| 771 | }; | ||
| 772 | |||
| 668 | thermistor-ap@0 { | 773 | thermistor-ap@0 { |
| 669 | compatible = "ntc,ncp15wb473"; | 774 | compatible = "ntc,ncp15wb473"; |
| 670 | pullup-uv = <1800000>; /* VCC_1.8V_AP */ | 775 | pullup-uv = <1800000>; /* VCC_1.8V_AP */ |
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 15d3c0ac2f5f..c42a3e196cd5 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi | |||
| @@ -29,4 +29,8 @@ | |||
| 29 | gic: interrupt-controller@10490000 { | 29 | gic: interrupt-controller@10490000 { |
| 30 | cpu-offset = <0x4000>; | 30 | cpu-offset = <0x4000>; |
| 31 | }; | 31 | }; |
| 32 | |||
| 33 | pmu_system_controller: system-controller@10020000 { | ||
| 34 | compatible = "samsung,exynos4412-pmu", "syscon"; | ||
| 35 | }; | ||
| 32 | }; | 36 | }; |
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index c4a9306f8529..c5a943df1cd7 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi | |||
| @@ -37,6 +37,24 @@ | |||
| 37 | interrupts = <2 2>, <3 2>, <18 2>, <19 2>; | 37 | interrupts = <2 2>, <3 2>, <18 2>, <19 2>; |
| 38 | }; | 38 | }; |
| 39 | 39 | ||
| 40 | sysram@02020000 { | ||
| 41 | compatible = "mmio-sram"; | ||
| 42 | reg = <0x02020000 0x40000>; | ||
| 43 | #address-cells = <1>; | ||
| 44 | #size-cells = <1>; | ||
| 45 | ranges = <0 0x02020000 0x40000>; | ||
| 46 | |||
| 47 | smp-sysram@0 { | ||
| 48 | compatible = "samsung,exynos4210-sysram"; | ||
| 49 | reg = <0x0 0x1000>; | ||
| 50 | }; | ||
| 51 | |||
| 52 | smp-sysram@2f000 { | ||
| 53 | compatible = "samsung,exynos4210-sysram-ns"; | ||
| 54 | reg = <0x2f000 0x1000>; | ||
| 55 | }; | ||
| 56 | }; | ||
| 57 | |||
| 40 | pd_isp: isp-power-domain@10023CA0 { | 58 | pd_isp: isp-power-domain@10023CA0 { |
| 41 | compatible = "samsung,exynos4210-pd"; | 59 | compatible = "samsung,exynos4210-pd"; |
| 42 | reg = <0x10023CA0 0x20>; | 60 | reg = <0x10023CA0 0x20>; |
| @@ -119,6 +137,10 @@ | |||
| 119 | interrupts = <0 72 0>; | 137 | interrupts = <0 72 0>; |
| 120 | }; | 138 | }; |
| 121 | 139 | ||
| 140 | pmu_system_controller: system-controller@10020000 { | ||
| 141 | compatible = "samsung,exynos4212-pmu", "syscon"; | ||
| 142 | }; | ||
| 143 | |||
| 122 | g2d@10800000 { | 144 | g2d@10800000 { |
| 123 | compatible = "samsung,exynos4212-g2d"; | 145 | compatible = "samsung,exynos4212-g2d"; |
| 124 | reg = <0x10800000 0x1000>; | 146 | reg = <0x10800000 0x1000>; |
| @@ -243,4 +265,9 @@ | |||
| 243 | clock-names = "biu", "ciu"; | 265 | clock-names = "biu", "ciu"; |
| 244 | status = "disabled"; | 266 | status = "disabled"; |
| 245 | }; | 267 | }; |
| 268 | |||
| 269 | exynos-usbphy@125B0000 { | ||
| 270 | compatible = "samsung,exynos4x12-usb2-phy"; | ||
| 271 | samsung,sysreg-phandle = <&sys_reg>; | ||
| 272 | }; | ||
| 246 | }; | 273 | }; |
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index cde19c818667..d0de1f50d15b 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | #include "exynos5250.dtsi" | 13 | #include "exynos5250.dtsi" |
| 14 | #include <dt-bindings/interrupt-controller/irq.h> | 14 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | #include <dt-bindings/input/input.h> | ||
| 15 | 16 | ||
| 16 | / { | 17 | / { |
| 17 | model = "Insignal Arndale evaluation board based on EXYNOS5250"; | 18 | model = "Insignal Arndale evaluation board based on EXYNOS5250"; |
| @@ -445,42 +446,42 @@ | |||
| 445 | menu { | 446 | menu { |
| 446 | label = "SW-TACT2"; | 447 | label = "SW-TACT2"; |
| 447 | gpios = <&gpx1 4 1>; | 448 | gpios = <&gpx1 4 1>; |
| 448 | linux,code = <139>; | 449 | linux,code = <KEY_MENU>; |
| 449 | gpio-key,wakeup; | 450 | gpio-key,wakeup; |
| 450 | }; | 451 | }; |
| 451 | 452 | ||
| 452 | home { | 453 | home { |
| 453 | label = "SW-TACT3"; | 454 | label = "SW-TACT3"; |
| 454 | gpios = <&gpx1 5 1>; | 455 | gpios = <&gpx1 5 1>; |
| 455 | linux,code = <102>; | 456 | linux,code = <KEY_HOME>; |
| 456 | gpio-key,wakeup; | 457 | gpio-key,wakeup; |
| 457 | }; | 458 | }; |
| 458 | 459 | ||
| 459 | up { | 460 | up { |
| 460 | label = "SW-TACT4"; | 461 | label = "SW-TACT4"; |
| 461 | gpios = <&gpx1 6 1>; | 462 | gpios = <&gpx1 6 1>; |
| 462 | linux,code = <103>; | 463 | linux,code = <KEY_UP>; |
| 463 | gpio-key,wakeup; | 464 | gpio-key,wakeup; |
| 464 | }; | 465 | }; |
| 465 | 466 | ||
| 466 | down { | 467 | down { |
| 467 | label = "SW-TACT5"; | 468 | label = "SW-TACT5"; |
| 468 | gpios = <&gpx1 7 1>; | 469 | gpios = <&gpx1 7 1>; |
| 469 | linux,code = <108>; | 470 | linux,code = <KEY_DOWN>; |
| 470 | gpio-key,wakeup; | 471 | gpio-key,wakeup; |
| 471 | }; | 472 | }; |
| 472 | 473 | ||
| 473 | back { | 474 | back { |
| 474 | label = "SW-TACT6"; | 475 | label = "SW-TACT6"; |
| 475 | gpios = <&gpx2 0 1>; | 476 | gpios = <&gpx2 0 1>; |
| 476 | linux,code = <158>; | 477 | linux,code = <KEY_BACK>; |
| 477 | gpio-key,wakeup; | 478 | gpio-key,wakeup; |
| 478 | }; | 479 | }; |
| 479 | 480 | ||
| 480 | wakeup { | 481 | wakeup { |
| 481 | label = "SW-TACT7"; | 482 | label = "SW-TACT7"; |
| 482 | gpios = <&gpx2 1 1>; | 483 | gpios = <&gpx2 1 1>; |
| 483 | linux,code = <143>; | 484 | linux,code = <KEY_WAKEUP>; |
| 484 | gpio-key,wakeup; | 485 | gpio-key,wakeup; |
| 485 | }; | 486 | }; |
| 486 | }; | 487 | }; |
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi index 2c1560d52f1a..89ac90f59e2e 100644 --- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi | |||
| @@ -240,7 +240,7 @@ | |||
| 240 | samsung,i2c-sda-delay = <100>; | 240 | samsung,i2c-sda-delay = <100>; |
| 241 | samsung,i2c-max-bus-freq = <378000>; | 241 | samsung,i2c-max-bus-freq = <378000>; |
| 242 | 242 | ||
| 243 | hdmiphy@38 { | 243 | hdmiphy: hdmiphy@38 { |
| 244 | compatible = "samsung,exynos4212-hdmiphy"; | 244 | compatible = "samsung,exynos4212-hdmiphy"; |
| 245 | reg = <0x38>; | 245 | reg = <0x38>; |
| 246 | }; | 246 | }; |
| @@ -304,6 +304,10 @@ | |||
| 304 | 304 | ||
| 305 | hdmi { | 305 | hdmi { |
| 306 | hpd-gpio = <&gpx3 7 0>; | 306 | hpd-gpio = <&gpx3 7 0>; |
| 307 | pinctrl-names = "default"; | ||
| 308 | pinctrl-0 = <&hdmi_hpd_irq>; | ||
| 309 | phy = <&hdmiphy>; | ||
| 310 | ddc = <&i2c_2>; | ||
| 307 | }; | 311 | }; |
| 308 | 312 | ||
| 309 | gpio-keys { | 313 | gpio-keys { |
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index 9a49e6804ae1..886cfca044ac 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi | |||
| @@ -351,6 +351,34 @@ | |||
| 351 | samsung,pin-drv = <0>; | 351 | samsung,pin-drv = <0>; |
| 352 | }; | 352 | }; |
| 353 | 353 | ||
| 354 | pwm0_out: pwm0-out { | ||
| 355 | samsung,pins = "gpb2-0"; | ||
| 356 | samsung,pin-function = <2>; | ||
| 357 | samsung,pin-pud = <0>; | ||
| 358 | samsung,pin-drv = <0>; | ||
| 359 | }; | ||
| 360 | |||
| 361 | pwm1_out: pwm1-out { | ||
| 362 | samsung,pins = "gpb2-1"; | ||
| 363 | samsung,pin-function = <2>; | ||
| 364 | samsung,pin-pud = <0>; | ||
| 365 | samsung,pin-drv = <0>; | ||
| 366 | }; | ||
| 367 | |||
| 368 | pwm2_out: pwm2-out { | ||
| 369 | samsung,pins = "gpb2-2"; | ||
| 370 | samsung,pin-function = <2>; | ||
| 371 | samsung,pin-pud = <0>; | ||
| 372 | samsung,pin-drv = <0>; | ||
| 373 | }; | ||
| 374 | |||
| 375 | pwm3_out: pwm3-out { | ||
| 376 | samsung,pins = "gpb2-3"; | ||
| 377 | samsung,pin-function = <2>; | ||
| 378 | samsung,pin-pud = <0>; | ||
| 379 | samsung,pin-drv = <0>; | ||
| 380 | }; | ||
| 381 | |||
| 354 | i2c7_bus: i2c7-bus { | 382 | i2c7_bus: i2c7-bus { |
| 355 | samsung,pins = "gpb2-2", "gpb2-3"; | 383 | samsung,pins = "gpb2-2", "gpb2-3"; |
| 356 | samsung,pin-function = <3>; | 384 | samsung,pin-function = <3>; |
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 1ce1088a00fb..079fdf9e3f18 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts | |||
| @@ -25,6 +25,13 @@ | |||
| 25 | }; | 25 | }; |
| 26 | 26 | ||
| 27 | pinctrl@11400000 { | 27 | pinctrl@11400000 { |
| 28 | ec_irq: ec-irq { | ||
| 29 | samsung,pins = "gpx1-6"; | ||
| 30 | samsung,pin-function = <0>; | ||
| 31 | samsung,pin-pud = <0>; | ||
| 32 | samsung,pin-drv = <0>; | ||
| 33 | }; | ||
| 34 | |||
| 28 | sd3_clk: sd3-clk { | 35 | sd3_clk: sd3-clk { |
| 29 | samsung,pin-drv = <0>; | 36 | samsung,pin-drv = <0>; |
| 30 | }; | 37 | }; |
| @@ -37,6 +44,50 @@ | |||
| 37 | sd3_bus4: sd3-bus-width4 { | 44 | sd3_bus4: sd3-bus-width4 { |
| 38 | samsung,pin-drv = <0>; | 45 | samsung,pin-drv = <0>; |
| 39 | }; | 46 | }; |
| 47 | |||
| 48 | max98095_en: max98095-en { | ||
| 49 | samsung,pins = "gpx1-7"; | ||
| 50 | samsung,pin-function = <0>; | ||
| 51 | samsung,pin-pud = <3>; | ||
| 52 | samsung,pin-drv = <0>; | ||
| 53 | }; | ||
| 54 | |||
| 55 | tps65090_irq: tps65090-irq { | ||
| 56 | samsung,pins = "gpx2-6"; | ||
| 57 | samsung,pin-function = <0>; | ||
| 58 | samsung,pin-pud = <0>; | ||
| 59 | samsung,pin-drv = <0>; | ||
| 60 | }; | ||
| 61 | |||
| 62 | usb3_vbus_en: usb3-vbus-en { | ||
| 63 | samsung,pins = "gpx2-7"; | ||
| 64 | samsung,pin-function = <1>; | ||
| 65 | samsung,pin-pud = <0>; | ||
| 66 | samsung,pin-drv = <0>; | ||
| 67 | }; | ||
| 68 | |||
| 69 | hdmi_hpd_irq: hdmi-hpd-irq { | ||
| 70 | samsung,pins = "gpx3-7"; | ||
| 71 | samsung,pin-function = <0>; | ||
| 72 | samsung,pin-pud = <1>; | ||
| 73 | samsung,pin-drv = <0>; | ||
| 74 | }; | ||
| 75 | }; | ||
| 76 | |||
| 77 | pinctrl@13400000 { | ||
| 78 | arb_their_claim: arb-their-claim { | ||
| 79 | samsung,pins = "gpe0-4"; | ||
| 80 | samsung,pin-function = <0>; | ||
| 81 | samsung,pin-pud = <3>; | ||
| 82 | samsung,pin-drv = <0>; | ||
| 83 | }; | ||
| 84 | |||
| 85 | arb_our_claim: arb-our-claim { | ||
| 86 | samsung,pins = "gpf0-3"; | ||
| 87 | samsung,pin-function = <1>; | ||
| 88 | samsung,pin-pud = <0>; | ||
| 89 | samsung,pin-drv = <0>; | ||
| 90 | }; | ||
| 40 | }; | 91 | }; |
| 41 | 92 | ||
| 42 | gpio-keys { | 93 | gpio-keys { |
| @@ -52,6 +103,12 @@ | |||
| 52 | }; | 103 | }; |
| 53 | }; | 104 | }; |
| 54 | 105 | ||
| 106 | vbat: vbat-fixed-regulator { | ||
| 107 | compatible = "regulator-fixed"; | ||
| 108 | regulator-name = "vbat-supply"; | ||
| 109 | regulator-boot-on; | ||
| 110 | }; | ||
| 111 | |||
| 55 | i2c-arbitrator { | 112 | i2c-arbitrator { |
| 56 | compatible = "i2c-arb-gpio-challenge"; | 113 | compatible = "i2c-arb-gpio-challenge"; |
| 57 | #address-cells = <1>; | 114 | #address-cells = <1>; |
| @@ -65,6 +122,9 @@ | |||
| 65 | wait-retry-us = <3000>; | 122 | wait-retry-us = <3000>; |
| 66 | wait-free-us = <50000>; | 123 | wait-free-us = <50000>; |
| 67 | 124 | ||
| 125 | pinctrl-names = "default"; | ||
| 126 | pinctrl-0 = <&arb_our_claim &arb_their_claim>; | ||
| 127 | |||
| 68 | /* Use ID 104 as a hint that we're on physical bus 4 */ | 128 | /* Use ID 104 as a hint that we're on physical bus 4 */ |
| 69 | i2c_104: i2c@0 { | 129 | i2c_104: i2c@0 { |
| 70 | reg = <0>; | 130 | reg = <0>; |
| @@ -82,6 +142,8 @@ | |||
| 82 | reg = <0x1e>; | 142 | reg = <0x1e>; |
| 83 | interrupts = <6 0>; | 143 | interrupts = <6 0>; |
| 84 | interrupt-parent = <&gpx1>; | 144 | interrupt-parent = <&gpx1>; |
| 145 | pinctrl-names = "default"; | ||
| 146 | pinctrl-0 = <&ec_irq>; | ||
| 85 | wakeup-source; | 147 | wakeup-source; |
| 86 | 148 | ||
| 87 | keyboard-controller { | 149 | keyboard-controller { |
| @@ -173,6 +235,83 @@ | |||
| 173 | 0x070c0069>; /* LEFT */ | 235 | 0x070c0069>; /* LEFT */ |
| 174 | }; | 236 | }; |
| 175 | }; | 237 | }; |
| 238 | |||
| 239 | power-regulator { | ||
| 240 | compatible = "ti,tps65090"; | ||
| 241 | reg = <0x48>; | ||
| 242 | |||
| 243 | /* | ||
| 244 | * Config irq to disable internal pulls | ||
| 245 | * even though we run in polling mode. | ||
| 246 | */ | ||
| 247 | pinctrl-names = "default"; | ||
| 248 | pinctrl-0 = <&tps65090_irq>; | ||
| 249 | |||
| 250 | vsys1-supply = <&vbat>; | ||
| 251 | vsys2-supply = <&vbat>; | ||
| 252 | vsys3-supply = <&vbat>; | ||
| 253 | infet1-supply = <&vbat>; | ||
| 254 | infet2-supply = <&vbat>; | ||
| 255 | infet3-supply = <&vbat>; | ||
| 256 | infet4-supply = <&vbat>; | ||
| 257 | infet5-supply = <&vbat>; | ||
| 258 | infet6-supply = <&vbat>; | ||
| 259 | infet7-supply = <&vbat>; | ||
| 260 | vsys-l1-supply = <&vbat>; | ||
| 261 | vsys-l2-supply = <&vbat>; | ||
| 262 | |||
| 263 | regulators { | ||
| 264 | dcdc1 { | ||
| 265 | ti,enable-ext-control; | ||
| 266 | }; | ||
| 267 | dcdc2 { | ||
| 268 | ti,enable-ext-control; | ||
| 269 | }; | ||
| 270 | dcdc3 { | ||
| 271 | ti,enable-ext-control; | ||
| 272 | }; | ||
| 273 | fet1 { | ||
| 274 | regulator-name = "vcd_led"; | ||
| 275 | ti,overcurrent-wait = <3>; | ||
| 276 | }; | ||
| 277 | tps65090_fet2: fet2 { | ||
| 278 | regulator-name = "video_mid"; | ||
| 279 | regulator-always-on; | ||
| 280 | ti,overcurrent-wait = <3>; | ||
| 281 | }; | ||
| 282 | fet3 { | ||
| 283 | regulator-name = "wwan_r"; | ||
| 284 | regulator-always-on; | ||
| 285 | ti,overcurrent-wait = <3>; | ||
| 286 | }; | ||
| 287 | fet4 { | ||
| 288 | regulator-name = "sdcard"; | ||
| 289 | ti,overcurrent-wait = <3>; | ||
| 290 | }; | ||
| 291 | fet5 { | ||
| 292 | regulator-name = "camout"; | ||
| 293 | regulator-always-on; | ||
| 294 | ti,overcurrent-wait = <3>; | ||
| 295 | }; | ||
| 296 | fet6 { | ||
| 297 | regulator-name = "lcd_vdd"; | ||
| 298 | ti,overcurrent-wait = <3>; | ||
| 299 | }; | ||
| 300 | tps65090_fet7: fet7 { | ||
| 301 | regulator-name = "video_mid_1a"; | ||
| 302 | regulator-always-on; | ||
| 303 | ti,overcurrent-wait = <3>; | ||
| 304 | }; | ||
| 305 | ldo1 { | ||
| 306 | }; | ||
| 307 | ldo2 { | ||
| 308 | }; | ||
| 309 | }; | ||
| 310 | |||
| 311 | charger { | ||
| 312 | compatible = "ti,tps65090-charger"; | ||
| 313 | }; | ||
| 314 | }; | ||
| 176 | }; | 315 | }; |
| 177 | }; | 316 | }; |
| 178 | 317 | ||
| @@ -196,6 +335,41 @@ | |||
| 196 | }; | 335 | }; |
| 197 | }; | 336 | }; |
| 198 | 337 | ||
| 338 | i2c@12CD0000 { | ||
| 339 | max98095: codec@11 { | ||
| 340 | compatible = "maxim,max98095"; | ||
| 341 | reg = <0x11>; | ||
| 342 | pinctrl-0 = <&max98095_en>; | ||
| 343 | pinctrl-names = "default"; | ||
| 344 | }; | ||
| 345 | }; | ||
| 346 | |||
| 347 | i2s0: i2s@03830000 { | ||
| 348 | status = "okay"; | ||
| 349 | }; | ||
| 350 | |||
| 351 | sound { | ||
| 352 | compatible = "google,snow-audio-max98095"; | ||
| 353 | |||
| 354 | samsung,i2s-controller = <&i2s0>; | ||
| 355 | samsung,audio-codec = <&max98095>; | ||
| 356 | }; | ||
| 357 | |||
| 358 | usb3_vbus_reg: regulator-usb3 { | ||
| 359 | compatible = "regulator-fixed"; | ||
| 360 | regulator-name = "P5.0V_USB3CON"; | ||
| 361 | regulator-min-microvolt = <5000000>; | ||
| 362 | regulator-max-microvolt = <5000000>; | ||
| 363 | gpio = <&gpx2 7 0>; | ||
| 364 | pinctrl-names = "default"; | ||
| 365 | pinctrl-0 = <&usb3_vbus_en>; | ||
| 366 | enable-active-high; | ||
| 367 | }; | ||
| 368 | |||
| 369 | phy@12100000 { | ||
| 370 | vbus-supply = <&usb3_vbus_reg>; | ||
| 371 | }; | ||
| 372 | |||
| 199 | usb@12110000 { | 373 | usb@12110000 { |
| 200 | samsung,vbus-gpio = <&gpx1 1 0>; | 374 | samsung,vbus-gpio = <&gpx1 1 0>; |
| 201 | }; | 375 | }; |
| @@ -206,4 +380,54 @@ | |||
| 206 | clock-frequency = <24000000>; | 380 | clock-frequency = <24000000>; |
| 207 | }; | 381 | }; |
| 208 | }; | 382 | }; |
| 383 | |||
| 384 | hdmi { | ||
| 385 | hdmi-en-supply = <&tps65090_fet7>; | ||
| 386 | vdd-supply = <&ldo8_reg>; | ||
| 387 | vdd_osc-supply = <&ldo10_reg>; | ||
| 388 | vdd_pll-supply = <&ldo8_reg>; | ||
| 389 | }; | ||
| 390 | |||
| 391 | backlight { | ||
| 392 | compatible = "pwm-backlight"; | ||
| 393 | pwms = <&pwm 0 1000000 0>; | ||
| 394 | brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; | ||
| 395 | default-brightness-level = <7>; | ||
| 396 | pinctrl-0 = <&pwm0_out>; | ||
| 397 | pinctrl-names = "default"; | ||
| 398 | }; | ||
| 399 | |||
| 400 | fimd@14400000 { | ||
| 401 | status = "okay"; | ||
| 402 | samsung,invert-vclk; | ||
| 403 | }; | ||
| 404 | |||
| 405 | dp-controller@145B0000 { | ||
| 406 | status = "okay"; | ||
| 407 | pinctrl-names = "default"; | ||
| 408 | pinctrl-0 = <&dp_hpd>; | ||
| 409 | samsung,color-space = <0>; | ||
| 410 | samsung,dynamic-range = <0>; | ||
| 411 | samsung,ycbcr-coeff = <0>; | ||
| 412 | samsung,color-depth = <1>; | ||
| 413 | samsung,link-rate = <0x0a>; | ||
| 414 | samsung,lane-count = <2>; | ||
| 415 | samsung,hpd-gpio = <&gpx0 7 0>; | ||
| 416 | |||
| 417 | display-timings { | ||
| 418 | native-mode = <&timing1>; | ||
| 419 | |||
| 420 | timing1: timing@1 { | ||
| 421 | clock-frequency = <70589280>; | ||
| 422 | hactive = <1366>; | ||
| 423 | vactive = <768>; | ||
| 424 | hfront-porch = <40>; | ||
| 425 | hback-porch = <40>; | ||
| 426 | hsync-len = <32>; | ||
| 427 | vback-porch = <10>; | ||
| 428 | vfront-porch = <12>; | ||
| 429 | vsync-len = <6>; | ||
| 430 | }; | ||
| 431 | }; | ||
| 432 | }; | ||
| 209 | }; | 433 | }; |
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 37423314a028..834fb5a5306f 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi | |||
| @@ -72,6 +72,24 @@ | |||
| 72 | }; | 72 | }; |
| 73 | }; | 73 | }; |
| 74 | 74 | ||
| 75 | sysram@02020000 { | ||
| 76 | compatible = "mmio-sram"; | ||
| 77 | reg = <0x02020000 0x30000>; | ||
| 78 | #address-cells = <1>; | ||
| 79 | #size-cells = <1>; | ||
| 80 | ranges = <0 0x02020000 0x30000>; | ||
| 81 | |||
| 82 | smp-sysram@0 { | ||
| 83 | compatible = "samsung,exynos4210-sysram"; | ||
| 84 | reg = <0x0 0x1000>; | ||
| 85 | }; | ||
| 86 | |||
| 87 | smp-sysram@2f000 { | ||
| 88 | compatible = "samsung,exynos4210-sysram-ns"; | ||
| 89 | reg = <0x2f000 0x1000>; | ||
| 90 | }; | ||
| 91 | }; | ||
| 92 | |||
| 75 | pd_gsc: gsc-power-domain@10044000 { | 93 | pd_gsc: gsc-power-domain@10044000 { |
| 76 | compatible = "samsung,exynos4210-pd"; | 94 | compatible = "samsung,exynos4210-pd"; |
| 77 | reg = <0x10044000 0x20>; | 95 | reg = <0x10044000 0x20>; |
| @@ -175,6 +193,11 @@ | |||
| 175 | reg = <0x10040000 0x5000>; | 193 | reg = <0x10040000 0x5000>; |
| 176 | }; | 194 | }; |
| 177 | 195 | ||
| 196 | sysreg_system_controller: syscon@10050000 { | ||
| 197 | compatible = "samsung,exynos5-sysreg", "syscon"; | ||
| 198 | reg = <0x10050000 0x5000>; | ||
| 199 | }; | ||
| 200 | |||
| 178 | watchdog@101D0000 { | 201 | watchdog@101D0000 { |
| 179 | compatible = "samsung,exynos5250-wdt"; | 202 | compatible = "samsung,exynos5250-wdt"; |
| 180 | reg = <0x101D0000 0x100>; | 203 | reg = <0x101D0000 0x100>; |
| @@ -250,7 +273,7 @@ | |||
| 250 | sata_phy: sata-phy@12170000 { | 273 | sata_phy: sata-phy@12170000 { |
| 251 | compatible = "samsung,exynos5250-sata-phy"; | 274 | compatible = "samsung,exynos5250-sata-phy"; |
| 252 | reg = <0x12170000 0x1ff>; | 275 | reg = <0x12170000 0x1ff>; |
| 253 | clocks = <&clock 287>; | 276 | clocks = <&clock CLK_SATA_PHYCTRL>; |
| 254 | clock-names = "sata_phyctrl"; | 277 | clock-names = "sata_phyctrl"; |
| 255 | #phy-cells = <0>; | 278 | #phy-cells = <0>; |
| 256 | samsung,syscon-phandle = <&pmu_system_controller>; | 279 | samsung,syscon-phandle = <&pmu_system_controller>; |
| @@ -533,22 +556,18 @@ | |||
| 533 | compatible = "synopsys,dwc3"; | 556 | compatible = "synopsys,dwc3"; |
| 534 | reg = <0x12000000 0x10000>; | 557 | reg = <0x12000000 0x10000>; |
| 535 | interrupts = <0 72 0>; | 558 | interrupts = <0 72 0>; |
| 536 | usb-phy = <&usb2_phy &usb3_phy>; | 559 | phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; |
| 560 | phy-names = "usb2-phy", "usb3-phy"; | ||
| 537 | }; | 561 | }; |
| 538 | }; | 562 | }; |
| 539 | 563 | ||
| 540 | usb3_phy: usbphy@12100000 { | 564 | usbdrd_phy: phy@12100000 { |
| 541 | compatible = "samsung,exynos5250-usb3phy"; | 565 | compatible = "samsung,exynos5250-usbdrd-phy"; |
| 542 | reg = <0x12100000 0x100>; | 566 | reg = <0x12100000 0x100>; |
| 543 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB3>; | 567 | clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; |
| 544 | clock-names = "ext_xtal", "usbdrd30"; | 568 | clock-names = "phy", "ref"; |
| 545 | #address-cells = <1>; | 569 | samsung,pmu-syscon = <&pmu_system_controller>; |
| 546 | #size-cells = <1>; | 570 | #phy-cells = <1>; |
| 547 | ranges; | ||
| 548 | |||
| 549 | usbphy-sys { | ||
| 550 | reg = <0x10040704 0x8>; | ||
| 551 | }; | ||
| 552 | }; | 571 | }; |
| 553 | 572 | ||
| 554 | usb@12110000 { | 573 | usb@12110000 { |
| @@ -558,6 +577,12 @@ | |||
| 558 | 577 | ||
| 559 | clocks = <&clock CLK_USB2>; | 578 | clocks = <&clock CLK_USB2>; |
| 560 | clock-names = "usbhost"; | 579 | clock-names = "usbhost"; |
| 580 | #address-cells = <1>; | ||
| 581 | #size-cells = <0>; | ||
| 582 | port@0 { | ||
| 583 | reg = <0>; | ||
| 584 | phys = <&usb2_phy_gen 1>; | ||
| 585 | }; | ||
| 561 | }; | 586 | }; |
| 562 | 587 | ||
| 563 | usb@12120000 { | 588 | usb@12120000 { |
| @@ -567,6 +592,12 @@ | |||
| 567 | 592 | ||
| 568 | clocks = <&clock CLK_USB2>; | 593 | clocks = <&clock CLK_USB2>; |
| 569 | clock-names = "usbhost"; | 594 | clock-names = "usbhost"; |
| 595 | #address-cells = <1>; | ||
| 596 | #size-cells = <0>; | ||
| 597 | port@0 { | ||
| 598 | reg = <0>; | ||
| 599 | phys = <&usb2_phy_gen 1>; | ||
| 600 | }; | ||
| 570 | }; | 601 | }; |
| 571 | 602 | ||
| 572 | usb2_phy: usbphy@12130000 { | 603 | usb2_phy: usbphy@12130000 { |
| @@ -584,6 +615,16 @@ | |||
| 584 | }; | 615 | }; |
| 585 | }; | 616 | }; |
| 586 | 617 | ||
| 618 | usb2_phy_gen: phy@12130000 { | ||
| 619 | compatible = "samsung,exynos5250-usb2-phy"; | ||
| 620 | reg = <0x12130000 0x100>; | ||
| 621 | clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; | ||
| 622 | clock-names = "phy", "ref"; | ||
| 623 | #phy-cells = <1>; | ||
| 624 | samsung,sysreg-phandle = <&sysreg_system_controller>; | ||
| 625 | samsung,pmureg-phandle = <&pmu_system_controller>; | ||
| 626 | }; | ||
| 627 | |||
| 587 | pwm: pwm@12dd0000 { | 628 | pwm: pwm@12dd0000 { |
| 588 | compatible = "samsung,exynos4210-pwm"; | 629 | compatible = "samsung,exynos4210-pwm"; |
| 589 | reg = <0x12dd0000 0x100>; | 630 | reg = <0x12dd0000 0x100>; |
| @@ -690,6 +731,7 @@ | |||
| 690 | <&clock CLK_MOUT_HDMI>; | 731 | <&clock CLK_MOUT_HDMI>; |
| 691 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", | 732 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", |
| 692 | "sclk_hdmiphy", "mout_hdmi"; | 733 | "sclk_hdmiphy", "mout_hdmi"; |
| 734 | samsung,syscon-phandle = <&pmu_system_controller>; | ||
| 693 | }; | 735 | }; |
| 694 | 736 | ||
| 695 | mixer { | 737 | mixer { |
| @@ -733,7 +775,7 @@ | |||
| 733 | compatible = "samsung,exynos4210-secss"; | 775 | compatible = "samsung,exynos4210-secss"; |
| 734 | reg = <0x10830000 0x10000>; | 776 | reg = <0x10830000 0x10000>; |
| 735 | interrupts = <0 112 0>; | 777 | interrupts = <0 112 0>; |
| 736 | clocks = <&clock 348>; | 778 | clocks = <&clock CLK_SSS>; |
| 737 | clock-names = "secss"; | 779 | clock-names = "secss"; |
| 738 | }; | 780 | }; |
| 739 | }; | 781 | }; |
diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi new file mode 100644 index 000000000000..f6ee55ea0708 --- /dev/null +++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi | |||
| @@ -0,0 +1,574 @@ | |||
| 1 | /* | ||
| 2 | * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source | ||
| 3 | * | ||
| 4 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | ||
| 5 | * http://www.samsung.com | ||
| 6 | * | ||
| 7 | * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device | ||
| 8 | * tree nodes are listed in this file. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #define PIN_PULL_NONE 0 | ||
| 16 | #define PIN_PULL_DOWN 1 | ||
| 17 | #define PIN_PULL_UP 3 | ||
| 18 | |||
| 19 | &pinctrl_0 { | ||
| 20 | gpa0: gpa0 { | ||
| 21 | gpio-controller; | ||
| 22 | #gpio-cells = <2>; | ||
| 23 | |||
| 24 | interrupt-controller; | ||
| 25 | #interrupt-cells = <2>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | gpa1: gpa1 { | ||
| 29 | gpio-controller; | ||
| 30 | #gpio-cells = <2>; | ||
| 31 | |||
| 32 | interrupt-controller; | ||
| 33 | #interrupt-cells = <2>; | ||
| 34 | }; | ||
| 35 | |||
| 36 | gpa2: gpa2 { | ||
| 37 | gpio-controller; | ||
| 38 | #gpio-cells = <2>; | ||
| 39 | |||
| 40 | interrupt-controller; | ||
| 41 | #interrupt-cells = <2>; | ||
| 42 | }; | ||
| 43 | |||
| 44 | gpb0: gpb0 { | ||
| 45 | gpio-controller; | ||
| 46 | #gpio-cells = <2>; | ||
| 47 | |||
| 48 | interrupt-controller; | ||
| 49 | #interrupt-cells = <2>; | ||
| 50 | }; | ||
| 51 | |||
| 52 | gpb1: gpb1 { | ||
| 53 | gpio-controller; | ||
| 54 | #gpio-cells = <2>; | ||
| 55 | |||
| 56 | interrupt-controller; | ||
| 57 | #interrupt-cells = <2>; | ||
| 58 | }; | ||
| 59 | |||
| 60 | gpb2: gpb2 { | ||
| 61 | gpio-controller; | ||
| 62 | #gpio-cells = <2>; | ||
| 63 | |||
| 64 | interrupt-controller; | ||
| 65 | #interrupt-cells = <2>; | ||
| 66 | }; | ||
| 67 | |||
| 68 | gpb3: gpb3 { | ||
| 69 | gpio-controller; | ||
| 70 | #gpio-cells = <2>; | ||
| 71 | |||
| 72 | interrupt-controller; | ||
| 73 | #interrupt-cells = <2>; | ||
| 74 | }; | ||
| 75 | |||
| 76 | gpb4: gpb4 { | ||
| 77 | gpio-controller; | ||
| 78 | #gpio-cells = <2>; | ||
| 79 | |||
| 80 | interrupt-controller; | ||
| 81 | #interrupt-cells = <2>; | ||
| 82 | }; | ||
| 83 | |||
| 84 | gpb5: gpb5 { | ||
| 85 | gpio-controller; | ||
| 86 | #gpio-cells = <2>; | ||
| 87 | |||
| 88 | interrupt-controller; | ||
| 89 | #interrupt-cells = <2>; | ||
| 90 | }; | ||
| 91 | |||
| 92 | gpd0: gpd0 { | ||
| 93 | gpio-controller; | ||
| 94 | #gpio-cells = <2>; | ||
| 95 | |||
| 96 | interrupt-controller; | ||
| 97 | #interrupt-cells = <2>; | ||
| 98 | }; | ||
| 99 | |||
| 100 | gpd1: gpd1 { | ||
| 101 | gpio-controller; | ||
| 102 | #gpio-cells = <2>; | ||
| 103 | |||
| 104 | interrupt-controller; | ||
| 105 | #interrupt-cells = <2>; | ||
| 106 | }; | ||
| 107 | |||
| 108 | gpd2: gpd2 { | ||
| 109 | gpio-controller; | ||
| 110 | #gpio-cells = <2>; | ||
| 111 | |||
| 112 | interrupt-controller; | ||
| 113 | #interrupt-cells = <2>; | ||
| 114 | }; | ||
| 115 | |||
| 116 | gpe0: gpe0 { | ||
| 117 | gpio-controller; | ||
| 118 | #gpio-cells = <2>; | ||
| 119 | |||
| 120 | interrupt-controller; | ||
| 121 | #interrupt-cells = <2>; | ||
| 122 | }; | ||
| 123 | |||
| 124 | gpe1: gpe1 { | ||
| 125 | gpio-controller; | ||
| 126 | #gpio-cells = <2>; | ||
| 127 | |||
| 128 | interrupt-controller; | ||
| 129 | #interrupt-cells = <2>; | ||
| 130 | }; | ||
| 131 | |||
| 132 | gpf0: gpf0 { | ||
| 133 | gpio-controller; | ||
| 134 | #gpio-cells = <2>; | ||
| 135 | |||
| 136 | interrupt-controller; | ||
| 137 | #interrupt-cells = <2>; | ||
| 138 | }; | ||
| 139 | |||
| 140 | gpf1: gpf1 { | ||
| 141 | gpio-controller; | ||
| 142 | #gpio-cells = <2>; | ||
| 143 | |||
| 144 | interrupt-controller; | ||
| 145 | #interrupt-cells = <2>; | ||
| 146 | }; | ||
| 147 | |||
| 148 | gpk0: gpk0 { | ||
| 149 | gpio-controller; | ||
| 150 | #gpio-cells = <2>; | ||
| 151 | |||
| 152 | interrupt-controller; | ||
| 153 | #interrupt-cells = <2>; | ||
| 154 | }; | ||
| 155 | |||
| 156 | gpx0: gpx0 { | ||
| 157 | gpio-controller; | ||
| 158 | #gpio-cells = <2>; | ||
| 159 | |||
| 160 | interrupt-controller; | ||
| 161 | #interrupt-cells = <2>; | ||
| 162 | }; | ||
| 163 | |||
| 164 | gpx1: gpx1 { | ||
| 165 | gpio-controller; | ||
| 166 | #gpio-cells = <2>; | ||
| 167 | |||
| 168 | interrupt-controller; | ||
| 169 | #interrupt-cells = <2>; | ||
| 170 | }; | ||
| 171 | |||
| 172 | gpx2: gpx2 { | ||
| 173 | gpio-controller; | ||
| 174 | #gpio-cells = <2>; | ||
| 175 | |||
| 176 | interrupt-controller; | ||
| 177 | #interrupt-cells = <2>; | ||
| 178 | }; | ||
| 179 | |||
| 180 | gpx3: gpx3 { | ||
| 181 | gpio-controller; | ||
| 182 | #gpio-cells = <2>; | ||
| 183 | |||
| 184 | interrupt-controller; | ||
| 185 | #interrupt-cells = <2>; | ||
| 186 | }; | ||
| 187 | |||
| 188 | uart0_data: uart0-data { | ||
| 189 | samsung,pins = "gpa0-0", "gpa0-1"; | ||
| 190 | samsung,pin-function = <2>; | ||
| 191 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 192 | samsung,pin-drv = <0>; | ||
| 193 | }; | ||
| 194 | |||
| 195 | uart0_fctl: uart0-fctl { | ||
| 196 | samsung,pins = "gpa0-2", "gpa0-3"; | ||
| 197 | samsung,pin-function = <2>; | ||
| 198 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 199 | samsung,pin-drv = <0>; | ||
| 200 | }; | ||
| 201 | |||
| 202 | uart1_data: uart1-data { | ||
| 203 | samsung,pins = "gpa1-0", "gpa1-1"; | ||
| 204 | samsung,pin-function = <2>; | ||
| 205 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 206 | samsung,pin-drv = <0>; | ||
| 207 | }; | ||
| 208 | |||
| 209 | uart1_fctl: uart1-fctl { | ||
| 210 | samsung,pins = "gpa1-2", "gpa1-3"; | ||
| 211 | samsung,pin-function = <2>; | ||
| 212 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 213 | samsung,pin-drv = <0>; | ||
| 214 | }; | ||
| 215 | |||
| 216 | uart2_data: uart2-data { | ||
| 217 | samsung,pins = "gpa1-4", "gpa1-5"; | ||
| 218 | samsung,pin-function = <2>; | ||
| 219 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 220 | samsung,pin-drv = <0>; | ||
| 221 | }; | ||
| 222 | |||
| 223 | spi0_bus: spi0-bus { | ||
| 224 | samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; | ||
| 225 | samsung,pin-function = <2>; | ||
| 226 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 227 | samsung,pin-drv = <0>; | ||
| 228 | }; | ||
| 229 | |||
| 230 | spi1_bus: spi1-bus { | ||
| 231 | samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; | ||
| 232 | samsung,pin-function = <2>; | ||
| 233 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 234 | samsung,pin-drv = <0>; | ||
| 235 | }; | ||
| 236 | |||
| 237 | usb3_vbus0_en: usb3-vbus0-en { | ||
| 238 | samsung,pins = "gpa2-4"; | ||
| 239 | samsung,pin-function = <1>; | ||
| 240 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 241 | samsung,pin-drv = <0>; | ||
| 242 | }; | ||
| 243 | |||
| 244 | i2s1_bus: i2s1-bus { | ||
| 245 | samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", | ||
| 246 | "gpb0-4"; | ||
| 247 | samsung,pin-function = <2>; | ||
| 248 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 249 | samsung,pin-drv = <0>; | ||
| 250 | }; | ||
| 251 | |||
| 252 | pcm1_bus: pcm1-bus { | ||
| 253 | samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", | ||
| 254 | "gpb0-4"; | ||
| 255 | samsung,pin-function = <3>; | ||
| 256 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 257 | samsung,pin-drv = <0>; | ||
| 258 | }; | ||
| 259 | |||
| 260 | spdif1_bus: spdif1-bus { | ||
| 261 | samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2"; | ||
| 262 | samsung,pin-function = <4>; | ||
| 263 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 264 | samsung,pin-drv = <0>; | ||
| 265 | }; | ||
| 266 | |||
| 267 | spi2_bus: spi2-bus { | ||
| 268 | samsung,pins = "gpb1-0", "gpb1-2", "gpb1-3"; | ||
| 269 | samsung,pin-function = <2>; | ||
| 270 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 271 | samsung,pin-drv = <0>; | ||
| 272 | }; | ||
| 273 | |||
| 274 | i2c0_hs_bus: i2c0-hs-bus { | ||
| 275 | samsung,pins = "gpb3-0", "gpb3-1"; | ||
| 276 | samsung,pin-function = <2>; | ||
| 277 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 278 | samsung,pin-drv = <0>; | ||
| 279 | }; | ||
| 280 | |||
| 281 | i2c1_hs_bus: i2c1-hs-bus { | ||
| 282 | samsung,pins = "gpb3-2", "gpb3-3"; | ||
| 283 | samsung,pin-function = <2>; | ||
| 284 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 285 | samsung,pin-drv = <0>; | ||
| 286 | }; | ||
| 287 | |||
| 288 | i2c2_hs_bus: i2c2-hs-bus { | ||
| 289 | samsung,pins = "gpb3-4", "gpb3-5"; | ||
| 290 | samsung,pin-function = <2>; | ||
| 291 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 292 | samsung,pin-drv = <0>; | ||
| 293 | }; | ||
| 294 | |||
| 295 | i2c3_hs_bus: i2c3-hs-bus { | ||
| 296 | samsung,pins = "gpb3-6", "gpb3-7"; | ||
| 297 | samsung,pin-function = <2>; | ||
| 298 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 299 | samsung,pin-drv = <0>; | ||
| 300 | }; | ||
| 301 | |||
| 302 | i2c4_bus: i2c4-bus { | ||
| 303 | samsung,pins = "gpb4-0", "gpb4-1"; | ||
| 304 | samsung,pin-function = <2>; | ||
| 305 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 306 | samsung,pin-drv = <0>; | ||
| 307 | }; | ||
| 308 | |||
| 309 | i2c5_bus: i2c5-bus { | ||
| 310 | samsung,pins = "gpb4-2", "gpb4-3"; | ||
| 311 | samsung,pin-function = <2>; | ||
| 312 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 313 | samsung,pin-drv = <0>; | ||
| 314 | }; | ||
| 315 | |||
| 316 | i2c6_bus: i2c6-bus { | ||
| 317 | samsung,pins = "gpb4-4", "gpb4-5"; | ||
| 318 | samsung,pin-function = <2>; | ||
| 319 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 320 | samsung,pin-drv = <0>; | ||
| 321 | }; | ||
| 322 | |||
| 323 | i2c7_bus: i2c7-bus { | ||
| 324 | samsung,pins = "gpb4-6", "gpb4-7"; | ||
| 325 | samsung,pin-function = <2>; | ||
| 326 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 327 | samsung,pin-drv = <0>; | ||
| 328 | }; | ||
| 329 | |||
| 330 | i2c8_bus: i2c8-bus { | ||
| 331 | samsung,pins = "gpb5-0", "gpb5-1"; | ||
| 332 | samsung,pin-function = <2>; | ||
| 333 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 334 | samsung,pin-drv = <0>; | ||
| 335 | }; | ||
| 336 | |||
| 337 | i2c9_bus: i2c9-bus { | ||
| 338 | samsung,pins = "gpb5-2", "gpb5-3"; | ||
| 339 | samsung,pin-function = <2>; | ||
| 340 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 341 | samsung,pin-drv = <0>; | ||
| 342 | }; | ||
| 343 | |||
| 344 | i2c10_bus: i2c10-bus { | ||
| 345 | samsung,pins = "gpb5-4", "gpb5-5"; | ||
| 346 | samsung,pin-function = <2>; | ||
| 347 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 348 | samsung,pin-drv = <0>; | ||
| 349 | }; | ||
| 350 | |||
| 351 | i2c11_bus: i2c11-bus { | ||
| 352 | samsung,pins = "gpb5-6", "gpb5-7"; | ||
| 353 | samsung,pin-function = <2>; | ||
| 354 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 355 | samsung,pin-drv = <0>; | ||
| 356 | }; | ||
| 357 | |||
| 358 | cam_gpio_a: cam-gpio-a { | ||
| 359 | samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", | ||
| 360 | "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", | ||
| 361 | "gpe1-0", "gpe1-1"; | ||
| 362 | samsung,pin-function = <2>; | ||
| 363 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 364 | samsung,pin-drv = <0>; | ||
| 365 | }; | ||
| 366 | |||
| 367 | cam_gpio_b: cam-gpio-b { | ||
| 368 | samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", | ||
| 369 | "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; | ||
| 370 | samsung,pin-function = <3>; | ||
| 371 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 372 | samsung,pin-drv = <0>; | ||
| 373 | }; | ||
| 374 | |||
| 375 | cam_i2c1_bus: cam-i2c1-bus { | ||
| 376 | samsung,pins = "gpf0-2", "gpf0-3"; | ||
| 377 | samsung,pin-function = <2>; | ||
| 378 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 379 | samsung,pin-drv = <0>; | ||
| 380 | }; | ||
| 381 | |||
| 382 | cam_i2c0_bus: cam-i2c0-bus { | ||
| 383 | samsung,pins = "gpf0-0", "gpf0-1"; | ||
| 384 | samsung,pin-function = <2>; | ||
| 385 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 386 | samsung,pin-drv = <0>; | ||
| 387 | }; | ||
| 388 | |||
| 389 | cam_spi0_bus: cam-spi0-bus { | ||
| 390 | samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; | ||
| 391 | samsung,pin-function = <2>; | ||
| 392 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 393 | samsung,pin-drv = <0>; | ||
| 394 | }; | ||
| 395 | |||
| 396 | cam_spi1_bus: cam-spi1-bus { | ||
| 397 | samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; | ||
| 398 | samsung,pin-function = <2>; | ||
| 399 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 400 | samsung,pin-drv = <0>; | ||
| 401 | }; | ||
| 402 | }; | ||
| 403 | |||
| 404 | &pinctrl_1 { | ||
| 405 | gpc0: gpc0 { | ||
| 406 | gpio-controller; | ||
| 407 | #gpio-cells = <2>; | ||
| 408 | |||
| 409 | interrupt-controller; | ||
| 410 | #interrupt-cells = <2>; | ||
| 411 | }; | ||
| 412 | |||
| 413 | gpc1: gpc1 { | ||
| 414 | gpio-controller; | ||
| 415 | #gpio-cells = <2>; | ||
| 416 | |||
| 417 | interrupt-controller; | ||
| 418 | #interrupt-cells = <2>; | ||
| 419 | }; | ||
| 420 | |||
| 421 | gpc2: gpc2 { | ||
| 422 | gpio-controller; | ||
| 423 | #gpio-cells = <2>; | ||
| 424 | |||
| 425 | interrupt-controller; | ||
| 426 | #interrupt-cells = <2>; | ||
| 427 | }; | ||
| 428 | |||
| 429 | gpc3: gpc3 { | ||
| 430 | gpio-controller; | ||
| 431 | #gpio-cells = <2>; | ||
| 432 | |||
| 433 | interrupt-controller; | ||
| 434 | #interrupt-cells = <2>; | ||
| 435 | }; | ||
| 436 | |||
| 437 | gpc4: gpc4 { | ||
| 438 | gpio-controller; | ||
| 439 | #gpio-cells = <2>; | ||
| 440 | |||
| 441 | interrupt-controller; | ||
| 442 | #interrupt-cells = <2>; | ||
| 443 | }; | ||
| 444 | |||
| 445 | sd0_clk: sd0-clk { | ||
| 446 | samsung,pins = "gpc0-0"; | ||
| 447 | samsung,pin-function = <2>; | ||
| 448 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 449 | samsung,pin-drv = <3>; | ||
| 450 | }; | ||
| 451 | |||
| 452 | sd0_cmd: sd0-cmd { | ||
| 453 | samsung,pins = "gpc0-1"; | ||
| 454 | samsung,pin-function = <2>; | ||
| 455 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 456 | samsung,pin-drv = <3>; | ||
| 457 | }; | ||
| 458 | |||
| 459 | sd0_bus1: sd0-bus-width1 { | ||
| 460 | samsung,pins = "gpc0-2"; | ||
| 461 | samsung,pin-function = <2>; | ||
| 462 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 463 | samsung,pin-drv = <3>; | ||
| 464 | }; | ||
| 465 | |||
| 466 | sd0_bus4: sd0-bus-width4 { | ||
| 467 | samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5"; | ||
| 468 | samsung,pin-function = <2>; | ||
| 469 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 470 | samsung,pin-drv = <3>; | ||
| 471 | }; | ||
| 472 | |||
| 473 | sd0_bus8: sd0-bus-width8 { | ||
| 474 | samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; | ||
| 475 | samsung,pin-function = <2>; | ||
| 476 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 477 | samsung,pin-drv = <3>; | ||
| 478 | }; | ||
| 479 | |||
| 480 | sd0_rdqs: sd0-rdqs { | ||
| 481 | samsung,pins = "gpc0-6"; | ||
| 482 | samsung,pin-function = <2>; | ||
| 483 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 484 | samsung,pin-drv = <3>; | ||
| 485 | }; | ||
| 486 | |||
| 487 | sd1_clk: sd1-clk { | ||
| 488 | samsung,pins = "gpc1-0"; | ||
| 489 | samsung,pin-function = <2>; | ||
| 490 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 491 | samsung,pin-drv = <3>; | ||
| 492 | }; | ||
| 493 | |||
| 494 | sd1_cmd: sd1-cmd { | ||
| 495 | samsung,pins = "gpc1-1"; | ||
| 496 | samsung,pin-function = <2>; | ||
| 497 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 498 | samsung,pin-drv = <3>; | ||
| 499 | }; | ||
| 500 | |||
| 501 | sd1_bus1: sd1-bus-width1 { | ||
| 502 | samsung,pins = "gpc1-2"; | ||
| 503 | samsung,pin-function = <2>; | ||
| 504 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 505 | samsung,pin-drv = <3>; | ||
| 506 | }; | ||
| 507 | |||
| 508 | sd1_bus4: sd1-bus-width4 { | ||
| 509 | samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5"; | ||
| 510 | samsung,pin-function = <2>; | ||
| 511 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 512 | samsung,pin-drv = <3>; | ||
| 513 | }; | ||
| 514 | |||
| 515 | sd1_bus8: sd1-bus-width8 { | ||
| 516 | samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3"; | ||
| 517 | samsung,pin-function = <2>; | ||
| 518 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 519 | samsung,pin-drv = <3>; | ||
| 520 | }; | ||
| 521 | |||
| 522 | sd2_clk: sd2-clk { | ||
| 523 | samsung,pins = "gpc2-0"; | ||
| 524 | samsung,pin-function = <2>; | ||
| 525 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 526 | samsung,pin-drv = <3>; | ||
| 527 | }; | ||
| 528 | |||
| 529 | sd2_cmd: sd2-cmd { | ||
| 530 | samsung,pins = "gpc2-1"; | ||
| 531 | samsung,pin-function = <2>; | ||
| 532 | samsung,pin-pud = <PIN_PULL_NONE>; | ||
| 533 | samsung,pin-drv = <3>; | ||
| 534 | }; | ||
| 535 | |||
| 536 | sd2_cd: sd2-cd { | ||
| 537 | samsung,pins = "gpc2-2"; | ||
| 538 | samsung,pin-function = <2>; | ||
| 539 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 540 | samsung,pin-drv = <3>; | ||
| 541 | }; | ||
| 542 | |||
| 543 | sd2_bus1: sd2-bus-width1 { | ||
| 544 | samsung,pins = "gpc2-3"; | ||
| 545 | samsung,pin-function = <2>; | ||
| 546 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 547 | samsung,pin-drv = <3>; | ||
| 548 | }; | ||
| 549 | |||
| 550 | sd2_bus4: sd2-bus-width4 { | ||
| 551 | samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; | ||
| 552 | samsung,pin-function = <2>; | ||
| 553 | samsung,pin-pud = <PIN_PULL_UP>; | ||
| 554 | samsung,pin-drv = <3>; | ||
| 555 | }; | ||
| 556 | }; | ||
| 557 | |||
| 558 | &pinctrl_2 { | ||
| 559 | gpz0: gpz0 { | ||
| 560 | gpio-controller; | ||
| 561 | #gpio-cells = <2>; | ||
| 562 | |||
| 563 | interrupt-controller; | ||
| 564 | #interrupt-cells = <2>; | ||
| 565 | }; | ||
| 566 | |||
| 567 | gpz1: gpz1 { | ||
| 568 | gpio-controller; | ||
| 569 | #gpio-cells = <2>; | ||
| 570 | |||
| 571 | interrupt-controller; | ||
| 572 | #interrupt-cells = <2>; | ||
| 573 | }; | ||
| 574 | }; | ||
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts new file mode 100644 index 000000000000..8c84ab27c19b --- /dev/null +++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts | |||
| @@ -0,0 +1,103 @@ | |||
| 1 | /* | ||
| 2 | * SAMSUNG XYREF5260 board device tree source | ||
| 3 | * | ||
| 4 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | ||
| 5 | * http://www.samsung.com | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "exynos5260.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "SAMSUNG XYREF5260 board based on EXYNOS5260"; | ||
| 17 | compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5"; | ||
| 18 | |||
| 19 | memory { | ||
| 20 | reg = <0x20000000 0x80000000>; | ||
| 21 | }; | ||
| 22 | |||
| 23 | chosen { | ||
| 24 | bootargs = "console=ttySAC2,115200"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | fin_pll: xxti { | ||
| 28 | compatible = "fixed-clock"; | ||
| 29 | clock-frequency = <24000000>; | ||
| 30 | clock-output-names = "fin_pll"; | ||
| 31 | #clock-cells = <0>; | ||
| 32 | }; | ||
| 33 | |||
| 34 | xrtcxti: xrtcxti { | ||
| 35 | compatible = "fixed-clock"; | ||
| 36 | clock-frequency = <32768>; | ||
| 37 | clock-output-names = "xrtcxti"; | ||
| 38 | #clock-cells = <0>; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | |||
| 42 | &pinctrl_0 { | ||
| 43 | hdmi_hpd_irq: hdmi-hpd-irq { | ||
| 44 | samsung,pins = "gpx3-7"; | ||
| 45 | samsung,pin-function = <0>; | ||
| 46 | samsung,pin-pud = <1>; | ||
| 47 | samsung,pin-drv = <0>; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | &uart0 { | ||
| 52 | status = "okay"; | ||
| 53 | }; | ||
| 54 | |||
| 55 | &uart1 { | ||
| 56 | status = "okay"; | ||
| 57 | }; | ||
| 58 | |||
| 59 | &uart2 { | ||
| 60 | status = "okay"; | ||
| 61 | }; | ||
| 62 | |||
| 63 | &uart3 { | ||
| 64 | status = "okay"; | ||
| 65 | }; | ||
| 66 | |||
| 67 | &mmc_0 { | ||
| 68 | status = "okay"; | ||
| 69 | num-slots = <1>; | ||
| 70 | broken-cd; | ||
| 71 | bypass-smu; | ||
| 72 | supports-highspeed; | ||
| 73 | supports-hs200-mode; /* 200 Mhz */ | ||
| 74 | card-detect-delay = <200>; | ||
| 75 | samsung,dw-mshc-ciu-div = <3>; | ||
| 76 | samsung,dw-mshc-sdr-timing = <0 4>; | ||
| 77 | samsung,dw-mshc-ddr-timing = <0 2>; | ||
| 78 | pinctrl-names = "default"; | ||
| 79 | pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; | ||
| 80 | |||
| 81 | slot@0 { | ||
| 82 | reg = <0>; | ||
| 83 | bus-width = <8>; | ||
| 84 | }; | ||
| 85 | }; | ||
| 86 | |||
| 87 | &mmc_2 { | ||
| 88 | status = "okay"; | ||
| 89 | num-slots = <1>; | ||
| 90 | supports-highspeed; | ||
| 91 | card-detect-delay = <200>; | ||
| 92 | samsung,dw-mshc-ciu-div = <3>; | ||
| 93 | samsung,dw-mshc-sdr-timing = <2 3>; | ||
| 94 | samsung,dw-mshc-ddr-timing = <1 2>; | ||
| 95 | pinctrl-names = "default"; | ||
| 96 | pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; | ||
| 97 | |||
| 98 | slot@0 { | ||
| 99 | reg = <0>; | ||
| 100 | bus-width = <4>; | ||
| 101 | disable-wp; | ||
| 102 | }; | ||
| 103 | }; | ||
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi new file mode 100644 index 000000000000..5398a60207ca --- /dev/null +++ b/arch/arm/boot/dts/exynos5260.dtsi | |||
| @@ -0,0 +1,304 @@ | |||
| 1 | /* | ||
| 2 | * SAMSUNG EXYNOS5260 SoC device tree source | ||
| 3 | * | ||
| 4 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | ||
| 5 | * http://www.samsung.com | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include "skeleton.dtsi" | ||
| 13 | |||
| 14 | #include <dt-bindings/clock/exynos5260-clk.h> | ||
| 15 | |||
| 16 | / { | ||
| 17 | compatible = "samsung,exynos5260", "samsung,exynos5"; | ||
| 18 | interrupt-parent = <&gic>; | ||
| 19 | |||
| 20 | aliases { | ||
| 21 | pinctrl0 = &pinctrl_0; | ||
| 22 | pinctrl1 = &pinctrl_1; | ||
| 23 | pinctrl2 = &pinctrl_2; | ||
| 24 | }; | ||
| 25 | |||
| 26 | cpus { | ||
| 27 | #address-cells = <1>; | ||
| 28 | #size-cells = <0>; | ||
| 29 | |||
| 30 | cpu@0 { | ||
| 31 | device_type = "cpu"; | ||
| 32 | compatible = "arm,cortex-a15"; | ||
| 33 | reg = <0x0>; | ||
| 34 | cci-control-port = <&cci_control1>; | ||
| 35 | }; | ||
| 36 | |||
| 37 | cpu@1 { | ||
| 38 | device_type = "cpu"; | ||
| 39 | compatible = "arm,cortex-a15"; | ||
| 40 | reg = <0x1>; | ||
| 41 | cci-control-port = <&cci_control1>; | ||
| 42 | }; | ||
| 43 | |||
| 44 | cpu@100 { | ||
| 45 | device_type = "cpu"; | ||
| 46 | compatible = "arm,cortex-a7"; | ||
| 47 | reg = <0x100>; | ||
| 48 | cci-control-port = <&cci_control0>; | ||
| 49 | }; | ||
| 50 | |||
| 51 | cpu@101 { | ||
| 52 | device_type = "cpu"; | ||
| 53 | compatible = "arm,cortex-a7"; | ||
| 54 | reg = <0x101>; | ||
| 55 | cci-control-port = <&cci_control0>; | ||
| 56 | }; | ||
| 57 | |||
| 58 | cpu@102 { | ||
| 59 | device_type = "cpu"; | ||
| 60 | compatible = "arm,cortex-a7"; | ||
| 61 | reg = <0x102>; | ||
| 62 | cci-control-port = <&cci_control0>; | ||
| 63 | }; | ||
| 64 | |||
| 65 | cpu@103 { | ||
| 66 | device_type = "cpu"; | ||
| 67 | compatible = "arm,cortex-a7"; | ||
| 68 | reg = <0x103>; | ||
| 69 | cci-control-port = <&cci_control0>; | ||
| 70 | }; | ||
| 71 | }; | ||
| 72 | |||
| 73 | soc: soc { | ||
| 74 | compatible = "simple-bus"; | ||
| 75 | #address-cells = <1>; | ||
| 76 | #size-cells = <1>; | ||
| 77 | ranges; | ||
| 78 | |||
| 79 | clock_top: clock-controller@10010000 { | ||
| 80 | compatible = "samsung,exynos5260-clock-top"; | ||
| 81 | reg = <0x10010000 0x10000>; | ||
| 82 | #clock-cells = <1>; | ||
| 83 | }; | ||
| 84 | |||
| 85 | clock_peri: clock-controller@10200000 { | ||
| 86 | compatible = "samsung,exynos5260-clock-peri"; | ||
| 87 | reg = <0x10200000 0x10000>; | ||
| 88 | #clock-cells = <1>; | ||
| 89 | }; | ||
| 90 | |||
| 91 | clock_egl: clock-controller@10600000 { | ||
| 92 | compatible = "samsung,exynos5260-clock-egl"; | ||
| 93 | reg = <0x10600000 0x10000>; | ||
| 94 | #clock-cells = <1>; | ||
| 95 | }; | ||
| 96 | |||
| 97 | clock_kfc: clock-controller@10700000 { | ||
| 98 | compatible = "samsung,exynos5260-clock-kfc"; | ||
| 99 | reg = <0x10700000 0x10000>; | ||
| 100 | #clock-cells = <1>; | ||
| 101 | }; | ||
| 102 | |||
| 103 | clock_g2d: clock-controller@10A00000 { | ||
| 104 | compatible = "samsung,exynos5260-clock-g2d"; | ||
| 105 | reg = <0x10A00000 0x10000>; | ||
| 106 | #clock-cells = <1>; | ||
| 107 | }; | ||
| 108 | |||
| 109 | clock_mif: clock-controller@10CE0000 { | ||
| 110 | compatible = "samsung,exynos5260-clock-mif"; | ||
| 111 | reg = <0x10CE0000 0x10000>; | ||
| 112 | #clock-cells = <1>; | ||
| 113 | }; | ||
| 114 | |||
| 115 | clock_mfc: clock-controller@11090000 { | ||
| 116 | compatible = "samsung,exynos5260-clock-mfc"; | ||
| 117 | reg = <0x11090000 0x10000>; | ||
| 118 | #clock-cells = <1>; | ||
| 119 | }; | ||
| 120 | |||
| 121 | clock_g3d: clock-controller@11830000 { | ||
| 122 | compatible = "samsung,exynos5260-clock-g3d"; | ||
| 123 | reg = <0x11830000 0x10000>; | ||
| 124 | #clock-cells = <1>; | ||
| 125 | }; | ||
| 126 | |||
| 127 | clock_fsys: clock-controller@122E0000 { | ||
| 128 | compatible = "samsung,exynos5260-clock-fsys"; | ||
| 129 | reg = <0x122E0000 0x10000>; | ||
| 130 | #clock-cells = <1>; | ||
| 131 | }; | ||
| 132 | |||
| 133 | clock_aud: clock-controller@128C0000 { | ||
| 134 | compatible = "samsung,exynos5260-clock-aud"; | ||
| 135 | reg = <0x128C0000 0x10000>; | ||
| 136 | #clock-cells = <1>; | ||
| 137 | }; | ||
| 138 | |||
| 139 | clock_isp: clock-controller@133C0000 { | ||
| 140 | compatible = "samsung,exynos5260-clock-isp"; | ||
| 141 | reg = <0x133C0000 0x10000>; | ||
| 142 | #clock-cells = <1>; | ||
| 143 | }; | ||
| 144 | |||
| 145 | clock_gscl: clock-controller@13F00000 { | ||
| 146 | compatible = "samsung,exynos5260-clock-gscl"; | ||
| 147 | reg = <0x13F00000 0x10000>; | ||
| 148 | #clock-cells = <1>; | ||
| 149 | }; | ||
| 150 | |||
| 151 | clock_disp: clock-controller@14550000 { | ||
| 152 | compatible = "samsung,exynos5260-clock-disp"; | ||
| 153 | reg = <0x14550000 0x10000>; | ||
| 154 | #clock-cells = <1>; | ||
| 155 | }; | ||
| 156 | |||
| 157 | gic: interrupt-controller@10481000 { | ||
| 158 | compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; | ||
| 159 | #interrupt-cells = <3>; | ||
| 160 | #address-cells = <0>; | ||
| 161 | #size-cells = <0>; | ||
| 162 | interrupt-controller; | ||
| 163 | reg = <0x10481000 0x1000>, | ||
| 164 | <0x10482000 0x1000>, | ||
| 165 | <0x10484000 0x2000>, | ||
| 166 | <0x10486000 0x2000>; | ||
| 167 | interrupts = <1 9 0xf04>; | ||
| 168 | }; | ||
| 169 | |||
| 170 | chipid: chipid@10000000 { | ||
| 171 | compatible = "samsung,exynos4210-chipid"; | ||
| 172 | reg = <0x10000000 0x100>; | ||
| 173 | }; | ||
| 174 | |||
| 175 | mct: mct@100B0000 { | ||
| 176 | compatible = "samsung,exynos4210-mct"; | ||
| 177 | reg = <0x100B0000 0x1000>; | ||
| 178 | clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; | ||
| 179 | clock-names = "fin_pll", "mct"; | ||
| 180 | interrupts = <0 104 0>, <0 105 0>, <0 106 0>, | ||
| 181 | <0 107 0>, <0 122 0>, <0 123 0>, | ||
| 182 | <0 124 0>, <0 125 0>, <0 126 0>, | ||
| 183 | <0 127 0>, <0 128 0>, <0 129 0>; | ||
| 184 | }; | ||
| 185 | |||
| 186 | cci: cci@10F00000 { | ||
| 187 | compatible = "arm,cci-400"; | ||
| 188 | #address-cells = <1>; | ||
| 189 | #size-cells = <1>; | ||
| 190 | reg = <0x10F00000 0x1000>; | ||
| 191 | ranges = <0x0 0x10F00000 0x6000>; | ||
| 192 | |||
| 193 | cci_control0: slave-if@4000 { | ||
| 194 | compatible = "arm,cci-400-ctrl-if"; | ||
| 195 | interface-type = "ace"; | ||
| 196 | reg = <0x4000 0x1000>; | ||
| 197 | }; | ||
| 198 | |||
| 199 | cci_control1: slave-if@5000 { | ||
| 200 | compatible = "arm,cci-400-ctrl-if"; | ||
| 201 | interface-type = "ace"; | ||
| 202 | reg = <0x5000 0x1000>; | ||
| 203 | }; | ||
| 204 | }; | ||
| 205 | |||
| 206 | pinctrl_0: pinctrl@11600000 { | ||
| 207 | compatible = "samsung,exynos5260-pinctrl"; | ||
| 208 | reg = <0x11600000 0x1000>; | ||
| 209 | interrupts = <0 79 0>; | ||
| 210 | |||
| 211 | wakeup-interrupt-controller { | ||
| 212 | compatible = "samsung,exynos4210-wakeup-eint"; | ||
| 213 | interrupt-parent = <&gic>; | ||
| 214 | interrupts = <0 32 0>; | ||
| 215 | }; | ||
| 216 | }; | ||
| 217 | |||
| 218 | pinctrl_1: pinctrl@12290000 { | ||
| 219 | compatible = "samsung,exynos5260-pinctrl"; | ||
| 220 | reg = <0x12290000 0x1000>; | ||
| 221 | interrupts = <0 157 0>; | ||
| 222 | }; | ||
| 223 | |||
| 224 | pinctrl_2: pinctrl@128B0000 { | ||
| 225 | compatible = "samsung,exynos5260-pinctrl"; | ||
| 226 | reg = <0x128B0000 0x1000>; | ||
| 227 | interrupts = <0 243 0>; | ||
| 228 | }; | ||
| 229 | |||
| 230 | uart0: serial@12C00000 { | ||
| 231 | compatible = "samsung,exynos4210-uart"; | ||
| 232 | reg = <0x12C00000 0x100>; | ||
| 233 | interrupts = <0 146 0>; | ||
| 234 | clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>; | ||
| 235 | clock-names = "uart", "clk_uart_baud0"; | ||
| 236 | status = "disabled"; | ||
| 237 | }; | ||
| 238 | |||
| 239 | uart1: serial@12C10000 { | ||
| 240 | compatible = "samsung,exynos4210-uart"; | ||
| 241 | reg = <0x12C10000 0x100>; | ||
| 242 | interrupts = <0 147 0>; | ||
| 243 | clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>; | ||
| 244 | clock-names = "uart", "clk_uart_baud0"; | ||
| 245 | status = "disabled"; | ||
| 246 | }; | ||
| 247 | |||
| 248 | uart2: serial@12C20000 { | ||
| 249 | compatible = "samsung,exynos4210-uart"; | ||
| 250 | reg = <0x12C20000 0x100>; | ||
| 251 | interrupts = <0 148 0>; | ||
| 252 | clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>; | ||
| 253 | clock-names = "uart", "clk_uart_baud0"; | ||
| 254 | status = "disabled"; | ||
| 255 | }; | ||
| 256 | |||
| 257 | uart3: serial@12860000 { | ||
| 258 | compatible = "samsung,exynos4210-uart"; | ||
| 259 | reg = <0x12860000 0x100>; | ||
| 260 | interrupts = <0 145 0>; | ||
| 261 | clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>; | ||
| 262 | clock-names = "uart", "clk_uart_baud0"; | ||
| 263 | status = "disabled"; | ||
| 264 | }; | ||
| 265 | |||
| 266 | mmc_0: mmc@12140000 { | ||
| 267 | compatible = "samsung,exynos5250-dw-mshc"; | ||
| 268 | reg = <0x12140000 0x2000>; | ||
| 269 | interrupts = <0 156 0>; | ||
| 270 | #address-cells = <1>; | ||
| 271 | #size-cells = <0>; | ||
| 272 | clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; | ||
| 273 | clock-names = "biu", "ciu"; | ||
| 274 | fifo-depth = <64>; | ||
| 275 | status = "disabled"; | ||
| 276 | }; | ||
| 277 | |||
| 278 | mmc_1: mmc@12150000 { | ||
| 279 | compatible = "samsung,exynos5250-dw-mshc"; | ||
| 280 | reg = <0x12150000 0x2000>; | ||
| 281 | interrupts = <0 158 0>; | ||
| 282 | #address-cells = <1>; | ||
| 283 | #size-cells = <0>; | ||
| 284 | clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; | ||
| 285 | clock-names = "biu", "ciu"; | ||
| 286 | fifo-depth = <64>; | ||
| 287 | status = "disabled"; | ||
| 288 | }; | ||
| 289 | |||
| 290 | mmc_2: mmc@12160000 { | ||
| 291 | compatible = "samsung,exynos5250-dw-mshc"; | ||
| 292 | reg = <0x12160000 0x2000>; | ||
| 293 | interrupts = <0 159 0>; | ||
| 294 | #address-cells = <1>; | ||
| 295 | #size-cells = <0>; | ||
| 296 | clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>; | ||
| 297 | clock-names = "biu", "ciu"; | ||
| 298 | fifo-depth = <64>; | ||
| 299 | status = "disabled"; | ||
| 300 | }; | ||
| 301 | }; | ||
| 302 | }; | ||
| 303 | |||
| 304 | #include "exynos5260-pinctrl.dtsi" | ||
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts new file mode 100644 index 000000000000..7275bbd6fc4b --- /dev/null +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts | |||
| @@ -0,0 +1,82 @@ | |||
| 1 | /* | ||
| 2 | * SAMSUNG SMDK5410 board device tree source | ||
| 3 | * | ||
| 4 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | ||
| 5 | * http://www.samsung.com | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "exynos5410.dtsi" | ||
| 14 | / { | ||
| 15 | model = "Samsung SMDK5410 board based on EXYNOS5410"; | ||
| 16 | compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5"; | ||
| 17 | |||
| 18 | memory { | ||
| 19 | reg = <0x40000000 0x80000000>; | ||
| 20 | }; | ||
| 21 | |||
| 22 | chosen { | ||
| 23 | bootargs = "console=ttySAC2,115200"; | ||
| 24 | }; | ||
| 25 | |||
| 26 | fin_pll: xxti { | ||
| 27 | compatible = "fixed-clock"; | ||
| 28 | clock-frequency = <24000000>; | ||
| 29 | clock-output-names = "fin_pll"; | ||
| 30 | #clock-cells = <0>; | ||
| 31 | }; | ||
| 32 | |||
| 33 | firmware@02037000 { | ||
| 34 | compatible = "samsung,secure-firmware"; | ||
| 35 | reg = <0x02037000 0x1000>; | ||
| 36 | }; | ||
| 37 | |||
| 38 | }; | ||
| 39 | |||
| 40 | &mmc_0 { | ||
| 41 | status = "okay"; | ||
| 42 | num-slots = <1>; | ||
| 43 | supports-highspeed; | ||
| 44 | broken-cd; | ||
| 45 | card-detect-delay = <200>; | ||
| 46 | samsung,dw-mshc-ciu-div = <3>; | ||
| 47 | samsung,dw-mshc-sdr-timing = <2 3>; | ||
| 48 | samsung,dw-mshc-ddr-timing = <1 2>; | ||
| 49 | |||
| 50 | slot@0 { | ||
| 51 | reg = <0>; | ||
| 52 | bus-width = <8>; | ||
| 53 | }; | ||
| 54 | }; | ||
| 55 | |||
| 56 | &mmc_2 { | ||
| 57 | status = "okay"; | ||
| 58 | num-slots = <1>; | ||
| 59 | supports-highspeed; | ||
| 60 | card-detect-delay = <200>; | ||
| 61 | samsung,dw-mshc-ciu-div = <3>; | ||
| 62 | samsung,dw-mshc-sdr-timing = <2 3>; | ||
| 63 | samsung,dw-mshc-ddr-timing = <1 2>; | ||
| 64 | |||
| 65 | slot@0 { | ||
| 66 | reg = <0>; | ||
| 67 | bus-width = <4>; | ||
| 68 | disable-wp; | ||
| 69 | }; | ||
| 70 | }; | ||
| 71 | |||
| 72 | &uart0 { | ||
| 73 | status = "okay"; | ||
| 74 | }; | ||
| 75 | |||
| 76 | &uart1 { | ||
| 77 | status = "okay"; | ||
| 78 | }; | ||
| 79 | |||
| 80 | &uart2 { | ||
| 81 | status = "okay"; | ||
| 82 | }; | ||
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi new file mode 100644 index 000000000000..3839c26f467f --- /dev/null +++ b/arch/arm/boot/dts/exynos5410.dtsi | |||
| @@ -0,0 +1,206 @@ | |||
| 1 | /* | ||
| 2 | * SAMSUNG EXYNOS5410 SoC device tree source | ||
| 3 | * | ||
| 4 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | ||
| 5 | * http://www.samsung.com | ||
| 6 | * | ||
| 7 | * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file. | ||
| 8 | * EXYNOS5410 based board files can include this file and provide | ||
| 9 | * values for board specfic bindings. | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include "skeleton.dtsi" | ||
| 17 | #include <dt-bindings/clock/exynos5410.h> | ||
| 18 | |||
| 19 | / { | ||
| 20 | compatible = "samsung,exynos5410", "samsung,exynos5"; | ||
| 21 | interrupt-parent = <&gic>; | ||
| 22 | |||
| 23 | cpus { | ||
| 24 | #address-cells = <1>; | ||
| 25 | #size-cells = <0>; | ||
| 26 | |||
| 27 | CPU0: cpu@0 { | ||
| 28 | device_type = "cpu"; | ||
| 29 | compatible = "arm,cortex-a15"; | ||
| 30 | reg = <0x0>; | ||
| 31 | }; | ||
| 32 | |||
| 33 | CPU1: cpu@1 { | ||
| 34 | device_type = "cpu"; | ||
| 35 | compatible = "arm,cortex-a15"; | ||
| 36 | reg = <0x1>; | ||
| 37 | }; | ||
| 38 | |||
| 39 | CPU2: cpu@2 { | ||
| 40 | device_type = "cpu"; | ||
| 41 | compatible = "arm,cortex-a15"; | ||
| 42 | reg = <0x2>; | ||
| 43 | }; | ||
| 44 | |||
| 45 | CPU3: cpu@3 { | ||
| 46 | device_type = "cpu"; | ||
| 47 | compatible = "arm,cortex-a15"; | ||
| 48 | reg = <0x3>; | ||
| 49 | }; | ||
| 50 | }; | ||
| 51 | |||
| 52 | soc: soc { | ||
| 53 | compatible = "simple-bus"; | ||
| 54 | #address-cells = <1>; | ||
| 55 | #size-cells = <1>; | ||
| 56 | ranges; | ||
| 57 | |||
| 58 | combiner: interrupt-controller@10440000 { | ||
| 59 | compatible = "samsung,exynos4210-combiner"; | ||
| 60 | #interrupt-cells = <2>; | ||
| 61 | interrupt-controller; | ||
| 62 | samsung,combiner-nr = <32>; | ||
| 63 | reg = <0x10440000 0x1000>; | ||
| 64 | interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, | ||
| 65 | <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, | ||
| 66 | <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, | ||
| 67 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, | ||
| 68 | <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, | ||
| 69 | <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, | ||
| 70 | <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, | ||
| 71 | <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; | ||
| 72 | }; | ||
| 73 | |||
| 74 | gic: interrupt-controller@10481000 { | ||
| 75 | compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; | ||
| 76 | #interrupt-cells = <3>; | ||
| 77 | interrupt-controller; | ||
| 78 | reg = <0x10481000 0x1000>, | ||
| 79 | <0x10482000 0x1000>, | ||
| 80 | <0x10484000 0x2000>, | ||
| 81 | <0x10486000 0x2000>; | ||
| 82 | interrupts = <1 9 0xf04>; | ||
| 83 | }; | ||
| 84 | |||
| 85 | chipid@10000000 { | ||
| 86 | compatible = "samsung,exynos4210-chipid"; | ||
| 87 | reg = <0x10000000 0x100>; | ||
| 88 | }; | ||
| 89 | |||
| 90 | mct: mct@101C0000 { | ||
| 91 | compatible = "samsung,exynos4210-mct"; | ||
| 92 | reg = <0x101C0000 0xB00>; | ||
| 93 | interrupt-parent = <&interrupt_map>; | ||
| 94 | interrupts = <0>, <1>, <2>, <3>, | ||
| 95 | <4>, <5>, <6>, <7>, | ||
| 96 | <8>, <9>, <10>, <11>; | ||
| 97 | clocks = <&fin_pll>, <&clock CLK_MCT>; | ||
| 98 | clock-names = "fin_pll", "mct"; | ||
| 99 | |||
| 100 | interrupt_map: interrupt-map { | ||
| 101 | #interrupt-cells = <1>; | ||
| 102 | #address-cells = <0>; | ||
| 103 | #size-cells = <0>; | ||
| 104 | interrupt-map = <0 &combiner 23 3>, | ||
| 105 | <1 &combiner 23 4>, | ||
| 106 | <2 &combiner 25 2>, | ||
| 107 | <3 &combiner 25 3>, | ||
| 108 | <4 &gic 0 120 0>, | ||
| 109 | <5 &gic 0 121 0>, | ||
| 110 | <6 &gic 0 122 0>, | ||
| 111 | <7 &gic 0 123 0>, | ||
| 112 | <8 &gic 0 128 0>, | ||
| 113 | <9 &gic 0 129 0>, | ||
| 114 | <10 &gic 0 130 0>, | ||
| 115 | <11 &gic 0 131 0>; | ||
| 116 | }; | ||
| 117 | }; | ||
| 118 | |||
| 119 | sysram@02020000 { | ||
| 120 | compatible = "mmio-sram"; | ||
| 121 | reg = <0x02020000 0x54000>; | ||
| 122 | #address-cells = <1>; | ||
| 123 | #size-cells = <1>; | ||
| 124 | ranges = <0 0x02020000 0x54000>; | ||
| 125 | |||
| 126 | smp-sysram@0 { | ||
| 127 | compatible = "samsung,exynos4210-sysram"; | ||
| 128 | reg = <0x0 0x1000>; | ||
| 129 | }; | ||
| 130 | |||
| 131 | smp-sysram@53000 { | ||
| 132 | compatible = "samsung,exynos4210-sysram-ns"; | ||
| 133 | reg = <0x53000 0x1000>; | ||
| 134 | }; | ||
| 135 | }; | ||
| 136 | |||
| 137 | clock: clock-controller@10010000 { | ||
| 138 | compatible = "samsung,exynos5410-clock"; | ||
| 139 | reg = <0x10010000 0x30000>; | ||
| 140 | #clock-cells = <1>; | ||
| 141 | }; | ||
| 142 | |||
| 143 | mmc_0: mmc@12200000 { | ||
| 144 | compatible = "samsung,exynos5250-dw-mshc"; | ||
| 145 | reg = <0x12200000 0x1000>; | ||
| 146 | interrupts = <0 75 0>; | ||
| 147 | #address-cells = <1>; | ||
| 148 | #size-cells = <0>; | ||
| 149 | clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; | ||
| 150 | clock-names = "biu", "ciu"; | ||
| 151 | fifo-depth = <0x80>; | ||
| 152 | status = "disabled"; | ||
| 153 | }; | ||
| 154 | |||
| 155 | mmc_1: mmc@12210000 { | ||
| 156 | compatible = "samsung,exynos5250-dw-mshc"; | ||
| 157 | reg = <0x12210000 0x1000>; | ||
| 158 | interrupts = <0 76 0>; | ||
| 159 | #address-cells = <1>; | ||
| 160 | #size-cells = <0>; | ||
| 161 | clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; | ||
| 162 | clock-names = "biu", "ciu"; | ||
| 163 | fifo-depth = <0x80>; | ||
| 164 | status = "disabled"; | ||
| 165 | }; | ||
| 166 | |||
| 167 | mmc_2: mmc@12220000 { | ||
| 168 | compatible = "samsung,exynos5250-dw-mshc"; | ||
| 169 | reg = <0x12220000 0x1000>; | ||
| 170 | interrupts = <0 77 0>; | ||
| 171 | #address-cells = <1>; | ||
| 172 | #size-cells = <0>; | ||
| 173 | clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; | ||
| 174 | clock-names = "biu", "ciu"; | ||
| 175 | fifo-depth = <0x80>; | ||
| 176 | status = "disabled"; | ||
| 177 | }; | ||
| 178 | |||
| 179 | uart0: serial@12C00000 { | ||
| 180 | compatible = "samsung,exynos4210-uart"; | ||
| 181 | reg = <0x12C00000 0x100>; | ||
| 182 | interrupts = <0 51 0>; | ||
| 183 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; | ||
| 184 | clock-names = "uart", "clk_uart_baud0"; | ||
| 185 | status = "disabled"; | ||
| 186 | }; | ||
| 187 | |||
| 188 | uart1: serial@12C10000 { | ||
| 189 | compatible = "samsung,exynos4210-uart"; | ||
| 190 | reg = <0x12C10000 0x100>; | ||
| 191 | interrupts = <0 52 0>; | ||
| 192 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; | ||
| 193 | clock-names = "uart", "clk_uart_baud0"; | ||
| 194 | status = "disabled"; | ||
| 195 | }; | ||
| 196 | |||
| 197 | uart2: serial@12C20000 { | ||
| 198 | compatible = "samsung,exynos4210-uart"; | ||
| 199 | reg = <0x12C20000 0x100>; | ||
| 200 | interrupts = <0 53 0>; | ||
| 201 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; | ||
| 202 | clock-names = "uart", "clk_uart_baud0"; | ||
| 203 | status = "disabled"; | ||
| 204 | }; | ||
| 205 | }; | ||
| 206 | }; | ||
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 896a2a6619e0..434fd9d3e09d 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts | |||
| @@ -26,6 +26,11 @@ | |||
| 26 | bootargs = "console=ttySAC3,115200"; | 26 | bootargs = "console=ttySAC3,115200"; |
| 27 | }; | 27 | }; |
| 28 | 28 | ||
| 29 | firmware@02073000 { | ||
| 30 | compatible = "samsung,secure-firmware"; | ||
| 31 | reg = <0x02073000 0x1000>; | ||
| 32 | }; | ||
| 33 | |||
| 29 | fixed-rate-clocks { | 34 | fixed-rate-clocks { |
| 30 | oscclk { | 35 | oscclk { |
| 31 | compatible = "samsung,exynos5420-oscclk"; | 36 | compatible = "samsung,exynos5420-oscclk"; |
| @@ -37,6 +42,11 @@ | |||
| 37 | status = "okay"; | 42 | status = "okay"; |
| 38 | }; | 43 | }; |
| 39 | 44 | ||
| 45 | codec@11000000 { | ||
| 46 | samsung,mfc-r = <0x43000000 0x800000>; | ||
| 47 | samsung,mfc-l = <0x51000000 0x800000>; | ||
| 48 | }; | ||
| 49 | |||
| 40 | mmc@12200000 { | 50 | mmc@12200000 { |
| 41 | status = "okay"; | 51 | status = "okay"; |
| 42 | broken-cd; | 52 | broken-cd; |
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts new file mode 100644 index 000000000000..1c5b8f9f4a36 --- /dev/null +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts | |||
| @@ -0,0 +1,287 @@ | |||
| 1 | /* | ||
| 2 | * Google Peach Pit Rev 6+ board device tree source | ||
| 3 | * | ||
| 4 | * Copyright (c) 2014 Google, Inc | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /dts-v1/; | ||
| 12 | #include <dt-bindings/input/input.h> | ||
| 13 | #include <dt-bindings/gpio/gpio.h> | ||
| 14 | #include "exynos5420.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Google Peach Pit Rev 6+"; | ||
| 18 | |||
| 19 | compatible = "google,pit-rev16", | ||
| 20 | "google,pit-rev15", "google,pit-rev14", | ||
| 21 | "google,pit-rev13", "google,pit-rev12", | ||
| 22 | "google,pit-rev11", "google,pit-rev10", | ||
| 23 | "google,pit-rev9", "google,pit-rev8", | ||
| 24 | "google,pit-rev7", "google,pit-rev6", | ||
| 25 | "google,pit", "google,peach","samsung,exynos5420", | ||
| 26 | "samsung,exynos5"; | ||
| 27 | |||
| 28 | memory { | ||
| 29 | reg = <0x20000000 0x80000000>; | ||
| 30 | }; | ||
| 31 | |||
| 32 | fixed-rate-clocks { | ||
| 33 | oscclk { | ||
| 34 | compatible = "samsung,exynos5420-oscclk"; | ||
| 35 | clock-frequency = <24000000>; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | |||
| 39 | gpio-keys { | ||
| 40 | compatible = "gpio-keys"; | ||
| 41 | |||
| 42 | pinctrl-names = "default"; | ||
| 43 | pinctrl-0 = <&power_key_irq>; | ||
| 44 | |||
| 45 | power { | ||
| 46 | label = "Power"; | ||
| 47 | gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; | ||
| 48 | linux,code = <KEY_POWER>; | ||
| 49 | gpio-key,wakeup; | ||
| 50 | }; | ||
| 51 | }; | ||
| 52 | |||
| 53 | backlight { | ||
| 54 | compatible = "pwm-backlight"; | ||
| 55 | pwms = <&pwm 0 1000000 0>; | ||
| 56 | brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; | ||
| 57 | default-brightness-level = <7>; | ||
| 58 | pinctrl-0 = <&pwm0_out>; | ||
| 59 | pinctrl-names = "default"; | ||
| 60 | }; | ||
| 61 | |||
| 62 | sound { | ||
| 63 | compatible = "google,snow-audio-max98090"; | ||
| 64 | |||
| 65 | samsung,i2s-controller = <&i2s0>; | ||
| 66 | samsung,audio-codec = <&max98090>; | ||
| 67 | }; | ||
| 68 | |||
| 69 | usb300_vbus_reg: regulator-usb300 { | ||
| 70 | compatible = "regulator-fixed"; | ||
| 71 | regulator-name = "P5.0V_USB3CON0"; | ||
| 72 | regulator-min-microvolt = <5000000>; | ||
| 73 | regulator-max-microvolt = <5000000>; | ||
| 74 | gpio = <&gph0 0 0>; | ||
| 75 | pinctrl-names = "default"; | ||
| 76 | pinctrl-0 = <&usb300_vbus_en>; | ||
| 77 | enable-active-high; | ||
| 78 | }; | ||
| 79 | |||
| 80 | usb301_vbus_reg: regulator-usb301 { | ||
| 81 | compatible = "regulator-fixed"; | ||
| 82 | regulator-name = "P5.0V_USB3CON1"; | ||
| 83 | regulator-min-microvolt = <5000000>; | ||
| 84 | regulator-max-microvolt = <5000000>; | ||
| 85 | gpio = <&gph0 1 0>; | ||
| 86 | pinctrl-names = "default"; | ||
| 87 | pinctrl-0 = <&usb301_vbus_en>; | ||
| 88 | enable-active-high; | ||
| 89 | }; | ||
| 90 | }; | ||
| 91 | |||
| 92 | &pinctrl_0 { | ||
| 93 | max98090_irq: max98090-irq { | ||
| 94 | samsung,pins = "gpx0-2"; | ||
| 95 | samsung,pin-function = <0>; | ||
| 96 | samsung,pin-pud = <0>; | ||
| 97 | samsung,pin-drv = <0>; | ||
| 98 | }; | ||
| 99 | |||
| 100 | tpm_irq: tpm-irq { | ||
| 101 | samsung,pins = "gpx1-0"; | ||
| 102 | samsung,pin-function = <0>; | ||
| 103 | samsung,pin-pud = <0>; | ||
| 104 | samsung,pin-drv = <0>; | ||
| 105 | }; | ||
| 106 | |||
| 107 | power_key_irq: power-key-irq { | ||
| 108 | samsung,pins = "gpx1-2"; | ||
| 109 | samsung,pin-function = <0>; | ||
| 110 | samsung,pin-pud = <0>; | ||
| 111 | samsung,pin-drv = <0>; | ||
| 112 | }; | ||
| 113 | |||
| 114 | hdmi_hpd_irq: hdmi-hpd-irq { | ||
| 115 | samsung,pins = "gpx3-7"; | ||
| 116 | samsung,pin-function = <0>; | ||
| 117 | samsung,pin-pud = <1>; | ||
| 118 | samsung,pin-drv = <0>; | ||
| 119 | }; | ||
| 120 | |||
| 121 | dp_hpd_gpio: dp_hpd_gpio { | ||
| 122 | samsung,pins = "gpx2-6"; | ||
| 123 | samsung,pin-function = <0>; | ||
| 124 | samsung,pin-pud = <3>; | ||
| 125 | samsung,pin-drv = <0>; | ||
| 126 | }; | ||
| 127 | }; | ||
| 128 | |||
| 129 | &pinctrl_3 { | ||
| 130 | usb300_vbus_en: usb300-vbus-en { | ||
| 131 | samsung,pins = "gph0-0"; | ||
| 132 | samsung,pin-function = <1>; | ||
| 133 | samsung,pin-pud = <0>; | ||
| 134 | samsung,pin-drv = <0>; | ||
| 135 | }; | ||
| 136 | |||
| 137 | usb301_vbus_en: usb301-vbus-en { | ||
| 138 | samsung,pins = "gph0-1"; | ||
| 139 | samsung,pin-function = <1>; | ||
| 140 | samsung,pin-pud = <0>; | ||
| 141 | samsung,pin-drv = <0>; | ||
| 142 | }; | ||
| 143 | }; | ||
| 144 | |||
| 145 | &rtc { | ||
| 146 | status = "okay"; | ||
| 147 | }; | ||
| 148 | |||
| 149 | &uart_3 { | ||
| 150 | status = "okay"; | ||
| 151 | }; | ||
| 152 | |||
| 153 | &mmc_0 { | ||
| 154 | status = "okay"; | ||
| 155 | num-slots = <1>; | ||
| 156 | broken-cd; | ||
| 157 | caps2-mmc-hs200-1_8v; | ||
| 158 | supports-highspeed; | ||
| 159 | non-removable; | ||
| 160 | card-detect-delay = <200>; | ||
| 161 | clock-frequency = <400000000>; | ||
| 162 | samsung,dw-mshc-ciu-div = <3>; | ||
| 163 | samsung,dw-mshc-sdr-timing = <0 4>; | ||
| 164 | samsung,dw-mshc-ddr-timing = <0 2>; | ||
| 165 | pinctrl-names = "default"; | ||
| 166 | pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; | ||
| 167 | |||
| 168 | slot@0 { | ||
| 169 | reg = <0>; | ||
| 170 | bus-width = <8>; | ||
| 171 | }; | ||
| 172 | }; | ||
| 173 | |||
| 174 | &mmc_2 { | ||
| 175 | status = "okay"; | ||
| 176 | num-slots = <1>; | ||
| 177 | supports-highspeed; | ||
| 178 | card-detect-delay = <200>; | ||
| 179 | clock-frequency = <400000000>; | ||
| 180 | samsung,dw-mshc-ciu-div = <3>; | ||
| 181 | samsung,dw-mshc-sdr-timing = <2 3>; | ||
| 182 | samsung,dw-mshc-ddr-timing = <1 2>; | ||
| 183 | pinctrl-names = "default"; | ||
| 184 | pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; | ||
| 185 | |||
| 186 | slot@0 { | ||
| 187 | reg = <0>; | ||
| 188 | bus-width = <4>; | ||
| 189 | }; | ||
| 190 | }; | ||
| 191 | |||
| 192 | &hsi2c_7 { | ||
| 193 | status = "okay"; | ||
| 194 | |||
| 195 | max98090: codec@10 { | ||
| 196 | compatible = "maxim,max98090"; | ||
| 197 | reg = <0x10>; | ||
| 198 | interrupts = <2 0>; | ||
| 199 | interrupt-parent = <&gpx0>; | ||
| 200 | pinctrl-names = "default"; | ||
| 201 | pinctrl-0 = <&max98090_irq>; | ||
| 202 | }; | ||
| 203 | }; | ||
| 204 | |||
| 205 | &hsi2c_9 { | ||
| 206 | status = "okay"; | ||
| 207 | clock-frequency = <400000>; | ||
| 208 | |||
| 209 | tpm@20 { | ||
| 210 | compatible = "infineon,slb9645tt"; | ||
| 211 | reg = <0x20>; | ||
| 212 | |||
| 213 | /* Unused irq; but still need to configure the pins */ | ||
| 214 | pinctrl-names = "default"; | ||
| 215 | pinctrl-0 = <&tpm_irq>; | ||
| 216 | }; | ||
| 217 | }; | ||
| 218 | |||
| 219 | &i2c_2 { | ||
| 220 | status = "okay"; | ||
| 221 | samsung,i2c-sda-delay = <100>; | ||
| 222 | samsung,i2c-max-bus-freq = <66000>; | ||
| 223 | samsung,i2c-slave-addr = <0x50>; | ||
| 224 | }; | ||
| 225 | |||
| 226 | &hdmi { | ||
| 227 | status = "okay"; | ||
| 228 | hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; | ||
| 229 | pinctrl-names = "default"; | ||
| 230 | pinctrl-0 = <&hdmi_hpd_irq>; | ||
| 231 | ddc = <&i2c_2>; | ||
| 232 | }; | ||
| 233 | |||
| 234 | &usbdrd_phy0 { | ||
| 235 | vbus-supply = <&usb300_vbus_reg>; | ||
| 236 | }; | ||
| 237 | |||
| 238 | &usbdrd_phy1 { | ||
| 239 | vbus-supply = <&usb301_vbus_reg>; | ||
| 240 | }; | ||
| 241 | |||
| 242 | /* | ||
| 243 | * Use longest HW watchdog in SoC (32 seconds) since the hardware | ||
| 244 | * watchdog provides no debugging information (compared to soft/hard | ||
| 245 | * lockup detectors) and so should be last resort. | ||
| 246 | */ | ||
| 247 | &watchdog { | ||
| 248 | timeout-sec = <32>; | ||
| 249 | }; | ||
| 250 | |||
| 251 | &i2s0 { | ||
| 252 | status = "okay"; | ||
| 253 | }; | ||
| 254 | |||
| 255 | &fimd { | ||
| 256 | status = "okay"; | ||
| 257 | samsung,invert-vclk; | ||
| 258 | }; | ||
| 259 | |||
| 260 | &dp { | ||
| 261 | status = "okay"; | ||
| 262 | pinctrl-names = "default"; | ||
| 263 | pinctrl-0 = <&dp_hpd_gpio>; | ||
| 264 | samsung,color-space = <0>; | ||
| 265 | samsung,dynamic-range = <0>; | ||
| 266 | samsung,ycbcr-coeff = <0>; | ||
| 267 | samsung,color-depth = <1>; | ||
| 268 | samsung,link-rate = <0x06>; | ||
| 269 | samsung,lane-count = <2>; | ||
| 270 | samsung,hpd-gpio = <&gpx2 6 0>; | ||
| 271 | |||
| 272 | display-timings { | ||
| 273 | native-mode = <&timing1>; | ||
| 274 | |||
| 275 | timing1: timing@1 { | ||
| 276 | clock-frequency = <70589280>; | ||
| 277 | hactive = <1366>; | ||
| 278 | vactive = <768>; | ||
| 279 | hfront-porch = <40>; | ||
| 280 | hback-porch = <40>; | ||
| 281 | hsync-len = <32>; | ||
| 282 | vback-porch = <10>; | ||
| 283 | vfront-porch = <12>; | ||
| 284 | vsync-len = <6>; | ||
| 285 | }; | ||
| 286 | }; | ||
| 287 | }; | ||
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index e62c8eb57438..ba686e40eac7 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi | |||
| @@ -624,6 +624,34 @@ | |||
| 624 | samsung,pin-drv = <0>; | 624 | samsung,pin-drv = <0>; |
| 625 | }; | 625 | }; |
| 626 | 626 | ||
| 627 | pwm0_out: pwm0-out { | ||
| 628 | samsung,pins = "gpb2-0"; | ||
| 629 | samsung,pin-function = <2>; | ||
| 630 | samsung,pin-pud = <0>; | ||
| 631 | samsung,pin-drv = <0>; | ||
| 632 | }; | ||
| 633 | |||
| 634 | pwm1_out: pwm1-out { | ||
| 635 | samsung,pins = "gpb2-1"; | ||
| 636 | samsung,pin-function = <2>; | ||
| 637 | samsung,pin-pud = <0>; | ||
| 638 | samsung,pin-drv = <0>; | ||
| 639 | }; | ||
| 640 | |||
| 641 | pwm2_out: pwm2-out { | ||
| 642 | samsung,pins = "gpb2-2"; | ||
| 643 | samsung,pin-function = <2>; | ||
| 644 | samsung,pin-pud = <0>; | ||
| 645 | samsung,pin-drv = <0>; | ||
| 646 | }; | ||
| 647 | |||
| 648 | pwm3_out: pwm3-out { | ||
| 649 | samsung,pins = "gpb2-3"; | ||
| 650 | samsung,pin-function = <2>; | ||
| 651 | samsung,pin-pud = <0>; | ||
| 652 | samsung,pin-drv = <0>; | ||
| 653 | }; | ||
| 654 | |||
| 627 | i2c7_hs_bus: i2c7-hs-bus { | 655 | i2c7_hs_bus: i2c7-hs-bus { |
| 628 | samsung,pins = "gpb2-2", "gpb2-3"; | 656 | samsung,pins = "gpb2-2", "gpb2-3"; |
| 629 | samsung,pin-function = <3>; | 657 | samsung,pin-function = <3>; |
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 69104850eb5e..6052aa9c5659 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts | |||
| @@ -68,6 +68,11 @@ | |||
| 68 | status = "okay"; | 68 | status = "okay"; |
| 69 | }; | 69 | }; |
| 70 | 70 | ||
| 71 | codec@11000000 { | ||
| 72 | samsung,mfc-r = <0x43000000 0x800000>; | ||
| 73 | samsung,mfc-l = <0x51000000 0x800000>; | ||
| 74 | }; | ||
| 75 | |||
| 71 | mmc@12200000 { | 76 | mmc@12200000 { |
| 72 | status = "okay"; | 77 | status = "okay"; |
| 73 | broken-cd; | 78 | broken-cd; |
| @@ -140,6 +145,22 @@ | |||
| 140 | }; | 145 | }; |
| 141 | }; | 146 | }; |
| 142 | 147 | ||
| 148 | pinctrl@14000000 { | ||
| 149 | usb300_vbus_en: usb300-vbus-en { | ||
| 150 | samsung,pins = "gpg0-5"; | ||
| 151 | samsung,pin-function = <1>; | ||
| 152 | samsung,pin-pud = <0>; | ||
| 153 | samsung,pin-drv = <0>; | ||
| 154 | }; | ||
| 155 | |||
| 156 | usb301_vbus_en: usb301-vbus-en { | ||
| 157 | samsung,pins = "gpg1-4"; | ||
| 158 | samsung,pin-function = <1>; | ||
| 159 | samsung,pin-pud = <0>; | ||
| 160 | samsung,pin-drv = <0>; | ||
| 161 | }; | ||
| 162 | }; | ||
| 163 | |||
| 143 | hdmi@14530000 { | 164 | hdmi@14530000 { |
| 144 | status = "okay"; | 165 | status = "okay"; |
| 145 | hpd-gpio = <&gpx3 7 0>; | 166 | hpd-gpio = <&gpx3 7 0>; |
| @@ -147,6 +168,36 @@ | |||
| 147 | pinctrl-0 = <&hdmi_hpd_irq>; | 168 | pinctrl-0 = <&hdmi_hpd_irq>; |
| 148 | }; | 169 | }; |
| 149 | 170 | ||
| 171 | usb300_vbus_reg: regulator-usb300 { | ||
| 172 | compatible = "regulator-fixed"; | ||
| 173 | regulator-name = "VBUS0"; | ||
| 174 | regulator-min-microvolt = <5000000>; | ||
| 175 | regulator-max-microvolt = <5000000>; | ||
| 176 | gpio = <&gpg0 5 0>; | ||
| 177 | pinctrl-names = "default"; | ||
| 178 | pinctrl-0 = <&usb300_vbus_en>; | ||
| 179 | enable-active-high; | ||
| 180 | }; | ||
| 181 | |||
| 182 | usb301_vbus_reg: regulator-usb301 { | ||
| 183 | compatible = "regulator-fixed"; | ||
| 184 | regulator-name = "VBUS1"; | ||
| 185 | regulator-min-microvolt = <5000000>; | ||
| 186 | regulator-max-microvolt = <5000000>; | ||
| 187 | gpio = <&gpg1 4 0>; | ||
| 188 | pinctrl-names = "default"; | ||
| 189 | pinctrl-0 = <&usb301_vbus_en>; | ||
| 190 | enable-active-high; | ||
| 191 | }; | ||
| 192 | |||
| 193 | phy@12100000 { | ||
| 194 | vbus-supply = <&usb300_vbus_reg>; | ||
| 195 | }; | ||
| 196 | |||
| 197 | phy@12500000 { | ||
| 198 | vbus-supply = <&usb301_vbus_reg>; | ||
| 199 | }; | ||
| 200 | |||
| 150 | i2c_2: i2c@12C80000 { | 201 | i2c_2: i2c@12C80000 { |
| 151 | samsung,i2c-sda-delay = <100>; | 202 | samsung,i2c-sda-delay = <100>; |
| 152 | samsung,i2c-max-bus-freq = <66000>; | 203 | samsung,i2c-max-bus-freq = <66000>; |
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index b69fbcb7dcb8..e38532271ef9 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi | |||
| @@ -47,6 +47,8 @@ | |||
| 47 | spi0 = &spi_0; | 47 | spi0 = &spi_0; |
| 48 | spi1 = &spi_1; | 48 | spi1 = &spi_1; |
| 49 | spi2 = &spi_2; | 49 | spi2 = &spi_2; |
| 50 | usbdrdphy0 = &usbdrd_phy0; | ||
| 51 | usbdrdphy1 = &usbdrd_phy1; | ||
| 50 | }; | 52 | }; |
| 51 | 53 | ||
| 52 | cpus { | 54 | cpus { |
| @@ -58,6 +60,7 @@ | |||
| 58 | compatible = "arm,cortex-a15"; | 60 | compatible = "arm,cortex-a15"; |
| 59 | reg = <0x0>; | 61 | reg = <0x0>; |
| 60 | clock-frequency = <1800000000>; | 62 | clock-frequency = <1800000000>; |
| 63 | cci-control-port = <&cci_control1>; | ||
| 61 | }; | 64 | }; |
| 62 | 65 | ||
| 63 | cpu1: cpu@1 { | 66 | cpu1: cpu@1 { |
| @@ -65,6 +68,7 @@ | |||
| 65 | compatible = "arm,cortex-a15"; | 68 | compatible = "arm,cortex-a15"; |
| 66 | reg = <0x1>; | 69 | reg = <0x1>; |
| 67 | clock-frequency = <1800000000>; | 70 | clock-frequency = <1800000000>; |
| 71 | cci-control-port = <&cci_control1>; | ||
| 68 | }; | 72 | }; |
| 69 | 73 | ||
| 70 | cpu2: cpu@2 { | 74 | cpu2: cpu@2 { |
| @@ -72,6 +76,7 @@ | |||
| 72 | compatible = "arm,cortex-a15"; | 76 | compatible = "arm,cortex-a15"; |
| 73 | reg = <0x2>; | 77 | reg = <0x2>; |
| 74 | clock-frequency = <1800000000>; | 78 | clock-frequency = <1800000000>; |
| 79 | cci-control-port = <&cci_control1>; | ||
| 75 | }; | 80 | }; |
| 76 | 81 | ||
| 77 | cpu3: cpu@3 { | 82 | cpu3: cpu@3 { |
| @@ -79,6 +84,7 @@ | |||
| 79 | compatible = "arm,cortex-a15"; | 84 | compatible = "arm,cortex-a15"; |
| 80 | reg = <0x3>; | 85 | reg = <0x3>; |
| 81 | clock-frequency = <1800000000>; | 86 | clock-frequency = <1800000000>; |
| 87 | cci-control-port = <&cci_control1>; | ||
| 82 | }; | 88 | }; |
| 83 | 89 | ||
| 84 | cpu4: cpu@100 { | 90 | cpu4: cpu@100 { |
| @@ -86,6 +92,7 @@ | |||
| 86 | compatible = "arm,cortex-a7"; | 92 | compatible = "arm,cortex-a7"; |
| 87 | reg = <0x100>; | 93 | reg = <0x100>; |
| 88 | clock-frequency = <1000000000>; | 94 | clock-frequency = <1000000000>; |
| 95 | cci-control-port = <&cci_control0>; | ||
| 89 | }; | 96 | }; |
| 90 | 97 | ||
| 91 | cpu5: cpu@101 { | 98 | cpu5: cpu@101 { |
| @@ -93,6 +100,7 @@ | |||
| 93 | compatible = "arm,cortex-a7"; | 100 | compatible = "arm,cortex-a7"; |
| 94 | reg = <0x101>; | 101 | reg = <0x101>; |
| 95 | clock-frequency = <1000000000>; | 102 | clock-frequency = <1000000000>; |
| 103 | cci-control-port = <&cci_control0>; | ||
| 96 | }; | 104 | }; |
| 97 | 105 | ||
| 98 | cpu6: cpu@102 { | 106 | cpu6: cpu@102 { |
| @@ -100,6 +108,7 @@ | |||
| 100 | compatible = "arm,cortex-a7"; | 108 | compatible = "arm,cortex-a7"; |
| 101 | reg = <0x102>; | 109 | reg = <0x102>; |
| 102 | clock-frequency = <1000000000>; | 110 | clock-frequency = <1000000000>; |
| 111 | cci-control-port = <&cci_control0>; | ||
| 103 | }; | 112 | }; |
| 104 | 113 | ||
| 105 | cpu7: cpu@103 { | 114 | cpu7: cpu@103 { |
| @@ -107,6 +116,44 @@ | |||
| 107 | compatible = "arm,cortex-a7"; | 116 | compatible = "arm,cortex-a7"; |
| 108 | reg = <0x103>; | 117 | reg = <0x103>; |
| 109 | clock-frequency = <1000000000>; | 118 | clock-frequency = <1000000000>; |
| 119 | cci-control-port = <&cci_control0>; | ||
| 120 | }; | ||
| 121 | }; | ||
| 122 | |||
| 123 | cci@10d20000 { | ||
| 124 | compatible = "arm,cci-400"; | ||
| 125 | #address-cells = <1>; | ||
| 126 | #size-cells = <1>; | ||
| 127 | reg = <0x10d20000 0x1000>; | ||
| 128 | ranges = <0x0 0x10d20000 0x6000>; | ||
| 129 | |||
| 130 | cci_control0: slave-if@4000 { | ||
| 131 | compatible = "arm,cci-400-ctrl-if"; | ||
| 132 | interface-type = "ace"; | ||
| 133 | reg = <0x4000 0x1000>; | ||
| 134 | }; | ||
| 135 | cci_control1: slave-if@5000 { | ||
| 136 | compatible = "arm,cci-400-ctrl-if"; | ||
| 137 | interface-type = "ace"; | ||
| 138 | reg = <0x5000 0x1000>; | ||
| 139 | }; | ||
| 140 | }; | ||
| 141 | |||
| 142 | sysram@02020000 { | ||
| 143 | compatible = "mmio-sram"; | ||
| 144 | reg = <0x02020000 0x54000>; | ||
| 145 | #address-cells = <1>; | ||
| 146 | #size-cells = <1>; | ||
| 147 | ranges = <0 0x02020000 0x54000>; | ||
| 148 | |||
| 149 | smp-sysram@0 { | ||
| 150 | compatible = "samsung,exynos4210-sysram"; | ||
| 151 | reg = <0x0 0x1000>; | ||
| 152 | }; | ||
| 153 | |||
| 154 | smp-sysram@53000 { | ||
| 155 | compatible = "samsung,exynos4210-sysram-ns"; | ||
| 156 | reg = <0x53000 0x1000>; | ||
| 110 | }; | 157 | }; |
| 111 | }; | 158 | }; |
| 112 | 159 | ||
| @@ -125,12 +172,13 @@ | |||
| 125 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; | 172 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; |
| 126 | }; | 173 | }; |
| 127 | 174 | ||
| 128 | codec@11000000 { | 175 | mfc: codec@11000000 { |
| 129 | compatible = "samsung,mfc-v7"; | 176 | compatible = "samsung,mfc-v7"; |
| 130 | reg = <0x11000000 0x10000>; | 177 | reg = <0x11000000 0x10000>; |
| 131 | interrupts = <0 96 0>; | 178 | interrupts = <0 96 0>; |
| 132 | clocks = <&clock CLK_MFC>; | 179 | clocks = <&clock CLK_MFC>; |
| 133 | clock-names = "mfc"; | 180 | clock-names = "mfc"; |
| 181 | samsung,power-domain = <&mfc_pd>; | ||
| 134 | }; | 182 | }; |
| 135 | 183 | ||
| 136 | mmc_0: mmc@12200000 { | 184 | mmc_0: mmc@12200000 { |
| @@ -169,7 +217,7 @@ | |||
| 169 | status = "disabled"; | 217 | status = "disabled"; |
| 170 | }; | 218 | }; |
| 171 | 219 | ||
| 172 | mct@101C0000 { | 220 | mct: mct@101C0000 { |
| 173 | compatible = "samsung,exynos4210-mct"; | 221 | compatible = "samsung,exynos4210-mct"; |
| 174 | reg = <0x101C0000 0x800>; | 222 | reg = <0x101C0000 0x800>; |
| 175 | interrupt-controller; | 223 | interrupt-controller; |
| @@ -260,7 +308,7 @@ | |||
| 260 | interrupts = <0 47 0>; | 308 | interrupts = <0 47 0>; |
| 261 | }; | 309 | }; |
| 262 | 310 | ||
| 263 | rtc@101E0000 { | 311 | rtc: rtc@101E0000 { |
| 264 | clocks = <&clock CLK_RTC>; | 312 | clocks = <&clock CLK_RTC>; |
| 265 | clock-names = "rtc"; | 313 | clock-names = "rtc"; |
| 266 | status = "disabled"; | 314 | status = "disabled"; |
| @@ -427,22 +475,22 @@ | |||
| 427 | status = "disabled"; | 475 | status = "disabled"; |
| 428 | }; | 476 | }; |
| 429 | 477 | ||
| 430 | serial@12C00000 { | 478 | uart_0: serial@12C00000 { |
| 431 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; | 479 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; |
| 432 | clock-names = "uart", "clk_uart_baud0"; | 480 | clock-names = "uart", "clk_uart_baud0"; |
| 433 | }; | 481 | }; |
| 434 | 482 | ||
| 435 | serial@12C10000 { | 483 | uart_1: serial@12C10000 { |
| 436 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; | 484 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; |
| 437 | clock-names = "uart", "clk_uart_baud0"; | 485 | clock-names = "uart", "clk_uart_baud0"; |
| 438 | }; | 486 | }; |
| 439 | 487 | ||
| 440 | serial@12C20000 { | 488 | uart_2: serial@12C20000 { |
| 441 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; | 489 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; |
| 442 | clock-names = "uart", "clk_uart_baud0"; | 490 | clock-names = "uart", "clk_uart_baud0"; |
| 443 | }; | 491 | }; |
| 444 | 492 | ||
| 445 | serial@12C30000 { | 493 | uart_3: serial@12C30000 { |
| 446 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; | 494 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; |
| 447 | clock-names = "uart", "clk_uart_baud0"; | 495 | clock-names = "uart", "clk_uart_baud0"; |
| 448 | }; | 496 | }; |
| @@ -462,14 +510,14 @@ | |||
| 462 | #phy-cells = <0>; | 510 | #phy-cells = <0>; |
| 463 | }; | 511 | }; |
| 464 | 512 | ||
| 465 | dp-controller@145B0000 { | 513 | dp: dp-controller@145B0000 { |
| 466 | clocks = <&clock CLK_DP1>; | 514 | clocks = <&clock CLK_DP1>; |
| 467 | clock-names = "dp"; | 515 | clock-names = "dp"; |
| 468 | phys = <&dp_phy>; | 516 | phys = <&dp_phy>; |
| 469 | phy-names = "dp"; | 517 | phy-names = "dp"; |
| 470 | }; | 518 | }; |
| 471 | 519 | ||
| 472 | fimd@14400000 { | 520 | fimd: fimd@14400000 { |
| 473 | samsung,power-domain = <&disp_pd>; | 521 | samsung,power-domain = <&disp_pd>; |
| 474 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; | 522 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; |
| 475 | clock-names = "sclk_fimd", "fimd"; | 523 | clock-names = "sclk_fimd", "fimd"; |
| @@ -546,7 +594,7 @@ | |||
| 546 | #size-cells = <0>; | 594 | #size-cells = <0>; |
| 547 | pinctrl-names = "default"; | 595 | pinctrl-names = "default"; |
| 548 | pinctrl-0 = <&i2c4_hs_bus>; | 596 | pinctrl-0 = <&i2c4_hs_bus>; |
| 549 | clocks = <&clock CLK_I2C4>; | 597 | clocks = <&clock CLK_USI0>; |
| 550 | clock-names = "hsi2c"; | 598 | clock-names = "hsi2c"; |
| 551 | status = "disabled"; | 599 | status = "disabled"; |
| 552 | }; | 600 | }; |
| @@ -559,7 +607,7 @@ | |||
| 559 | #size-cells = <0>; | 607 | #size-cells = <0>; |
| 560 | pinctrl-names = "default"; | 608 | pinctrl-names = "default"; |
| 561 | pinctrl-0 = <&i2c5_hs_bus>; | 609 | pinctrl-0 = <&i2c5_hs_bus>; |
| 562 | clocks = <&clock CLK_I2C5>; | 610 | clocks = <&clock CLK_USI1>; |
| 563 | clock-names = "hsi2c"; | 611 | clock-names = "hsi2c"; |
| 564 | status = "disabled"; | 612 | status = "disabled"; |
| 565 | }; | 613 | }; |
| @@ -572,7 +620,7 @@ | |||
| 572 | #size-cells = <0>; | 620 | #size-cells = <0>; |
| 573 | pinctrl-names = "default"; | 621 | pinctrl-names = "default"; |
| 574 | pinctrl-0 = <&i2c6_hs_bus>; | 622 | pinctrl-0 = <&i2c6_hs_bus>; |
| 575 | clocks = <&clock CLK_I2C6>; | 623 | clocks = <&clock CLK_USI2>; |
| 576 | clock-names = "hsi2c"; | 624 | clock-names = "hsi2c"; |
| 577 | status = "disabled"; | 625 | status = "disabled"; |
| 578 | }; | 626 | }; |
| @@ -585,7 +633,7 @@ | |||
| 585 | #size-cells = <0>; | 633 | #size-cells = <0>; |
| 586 | pinctrl-names = "default"; | 634 | pinctrl-names = "default"; |
| 587 | pinctrl-0 = <&i2c7_hs_bus>; | 635 | pinctrl-0 = <&i2c7_hs_bus>; |
| 588 | clocks = <&clock CLK_I2C7>; | 636 | clocks = <&clock CLK_USI3>; |
| 589 | clock-names = "hsi2c"; | 637 | clock-names = "hsi2c"; |
| 590 | status = "disabled"; | 638 | status = "disabled"; |
| 591 | }; | 639 | }; |
| @@ -598,7 +646,7 @@ | |||
| 598 | #size-cells = <0>; | 646 | #size-cells = <0>; |
| 599 | pinctrl-names = "default"; | 647 | pinctrl-names = "default"; |
| 600 | pinctrl-0 = <&i2c8_hs_bus>; | 648 | pinctrl-0 = <&i2c8_hs_bus>; |
| 601 | clocks = <&clock CLK_I2C8>; | 649 | clocks = <&clock CLK_USI4>; |
| 602 | clock-names = "hsi2c"; | 650 | clock-names = "hsi2c"; |
| 603 | status = "disabled"; | 651 | status = "disabled"; |
| 604 | }; | 652 | }; |
| @@ -611,7 +659,7 @@ | |||
| 611 | #size-cells = <0>; | 659 | #size-cells = <0>; |
| 612 | pinctrl-names = "default"; | 660 | pinctrl-names = "default"; |
| 613 | pinctrl-0 = <&i2c9_hs_bus>; | 661 | pinctrl-0 = <&i2c9_hs_bus>; |
| 614 | clocks = <&clock CLK_I2C9>; | 662 | clocks = <&clock CLK_USI5>; |
| 615 | clock-names = "hsi2c"; | 663 | clock-names = "hsi2c"; |
| 616 | status = "disabled"; | 664 | status = "disabled"; |
| 617 | }; | 665 | }; |
| @@ -624,13 +672,13 @@ | |||
| 624 | #size-cells = <0>; | 672 | #size-cells = <0>; |
| 625 | pinctrl-names = "default"; | 673 | pinctrl-names = "default"; |
| 626 | pinctrl-0 = <&i2c10_hs_bus>; | 674 | pinctrl-0 = <&i2c10_hs_bus>; |
| 627 | clocks = <&clock CLK_I2C10>; | 675 | clocks = <&clock CLK_USI6>; |
| 628 | clock-names = "hsi2c"; | 676 | clock-names = "hsi2c"; |
| 629 | status = "disabled"; | 677 | status = "disabled"; |
| 630 | }; | 678 | }; |
| 631 | 679 | ||
| 632 | hdmi@14530000 { | 680 | hdmi: hdmi@14530000 { |
| 633 | compatible = "samsung,exynos4212-hdmi"; | 681 | compatible = "samsung,exynos5420-hdmi"; |
| 634 | reg = <0x14530000 0x70000>; | 682 | reg = <0x14530000 0x70000>; |
| 635 | interrupts = <0 95 0>; | 683 | interrupts = <0 95 0>; |
| 636 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, | 684 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, |
| @@ -638,10 +686,16 @@ | |||
| 638 | <&clock CLK_MOUT_HDMI>; | 686 | <&clock CLK_MOUT_HDMI>; |
| 639 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", | 687 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", |
| 640 | "sclk_hdmiphy", "mout_hdmi"; | 688 | "sclk_hdmiphy", "mout_hdmi"; |
| 689 | phy = <&hdmiphy>; | ||
| 690 | samsung,syscon-phandle = <&pmu_system_controller>; | ||
| 641 | status = "disabled"; | 691 | status = "disabled"; |
| 642 | }; | 692 | }; |
| 643 | 693 | ||
| 644 | mixer@14450000 { | 694 | hdmiphy: hdmiphy@145D0000 { |
| 695 | reg = <0x145D0000 0x20>; | ||
| 696 | }; | ||
| 697 | |||
| 698 | mixer: mixer@14450000 { | ||
| 645 | compatible = "samsung,exynos5420-mixer"; | 699 | compatible = "samsung,exynos5420-mixer"; |
| 646 | reg = <0x14450000 0x10000>; | 700 | reg = <0x14450000 0x10000>; |
| 647 | interrupts = <0 94 0>; | 701 | interrupts = <0 94 0>; |
| @@ -672,6 +726,11 @@ | |||
| 672 | reg = <0x10040000 0x5000>; | 726 | reg = <0x10040000 0x5000>; |
| 673 | }; | 727 | }; |
| 674 | 728 | ||
| 729 | sysreg_system_controller: syscon@10050000 { | ||
| 730 | compatible = "samsung,exynos5-sysreg", "syscon"; | ||
| 731 | reg = <0x10050000 0x5000>; | ||
| 732 | }; | ||
| 733 | |||
| 675 | tmu_cpu0: tmu@10060000 { | 734 | tmu_cpu0: tmu@10060000 { |
| 676 | compatible = "samsung,exynos5420-tmu"; | 735 | compatible = "samsung,exynos5420-tmu"; |
| 677 | reg = <0x10060000 0x100>; | 736 | reg = <0x10060000 0x100>; |
| @@ -712,7 +771,7 @@ | |||
| 712 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; | 771 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; |
| 713 | }; | 772 | }; |
| 714 | 773 | ||
| 715 | watchdog@101D0000 { | 774 | watchdog: watchdog@101D0000 { |
| 716 | compatible = "samsung,exynos5420-wdt"; | 775 | compatible = "samsung,exynos5420-wdt"; |
| 717 | reg = <0x101D0000 0x100>; | 776 | reg = <0x101D0000 0x100>; |
| 718 | interrupts = <0 42 0>; | 777 | interrupts = <0 42 0>; |
| @@ -721,11 +780,103 @@ | |||
| 721 | samsung,syscon-phandle = <&pmu_system_controller>; | 780 | samsung,syscon-phandle = <&pmu_system_controller>; |
| 722 | }; | 781 | }; |
| 723 | 782 | ||
| 724 | sss@10830000 { | 783 | sss: sss@10830000 { |
| 725 | compatible = "samsung,exynos4210-secss"; | 784 | compatible = "samsung,exynos4210-secss"; |
| 726 | reg = <0x10830000 0x10000>; | 785 | reg = <0x10830000 0x10000>; |
| 727 | interrupts = <0 112 0>; | 786 | interrupts = <0 112 0>; |
| 728 | clocks = <&clock 471>; | 787 | clocks = <&clock CLK_SSS>; |
| 729 | clock-names = "secss"; | 788 | clock-names = "secss"; |
| 730 | }; | 789 | }; |
| 790 | |||
| 791 | usbdrd3_0: usb@12000000 { | ||
| 792 | compatible = "samsung,exynos5250-dwusb3"; | ||
| 793 | clocks = <&clock CLK_USBD300>; | ||
| 794 | clock-names = "usbdrd30"; | ||
| 795 | #address-cells = <1>; | ||
| 796 | #size-cells = <1>; | ||
| 797 | ranges; | ||
| 798 | |||
| 799 | dwc3 { | ||
| 800 | compatible = "snps,dwc3"; | ||
| 801 | reg = <0x12000000 0x10000>; | ||
| 802 | interrupts = <0 72 0>; | ||
| 803 | phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; | ||
| 804 | phy-names = "usb2-phy", "usb3-phy"; | ||
| 805 | }; | ||
| 806 | }; | ||
| 807 | |||
| 808 | usbdrd_phy0: phy@12100000 { | ||
| 809 | compatible = "samsung,exynos5420-usbdrd-phy"; | ||
| 810 | reg = <0x12100000 0x100>; | ||
| 811 | clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; | ||
| 812 | clock-names = "phy", "ref"; | ||
| 813 | samsung,pmu-syscon = <&pmu_system_controller>; | ||
| 814 | #phy-cells = <1>; | ||
| 815 | }; | ||
| 816 | |||
| 817 | usbdrd3_1: usb@12400000 { | ||
| 818 | compatible = "samsung,exynos5250-dwusb3"; | ||
| 819 | clocks = <&clock CLK_USBD301>; | ||
| 820 | clock-names = "usbdrd30"; | ||
| 821 | #address-cells = <1>; | ||
| 822 | #size-cells = <1>; | ||
| 823 | ranges; | ||
| 824 | |||
| 825 | dwc3 { | ||
| 826 | compatible = "snps,dwc3"; | ||
| 827 | reg = <0x12400000 0x10000>; | ||
| 828 | interrupts = <0 73 0>; | ||
| 829 | phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; | ||
| 830 | phy-names = "usb2-phy", "usb3-phy"; | ||
| 831 | }; | ||
| 832 | }; | ||
| 833 | |||
| 834 | usbdrd_phy1: phy@12500000 { | ||
| 835 | compatible = "samsung,exynos5420-usbdrd-phy"; | ||
| 836 | reg = <0x12500000 0x100>; | ||
| 837 | clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; | ||
| 838 | clock-names = "phy", "ref"; | ||
| 839 | samsung,pmu-syscon = <&pmu_system_controller>; | ||
| 840 | #phy-cells = <1>; | ||
| 841 | }; | ||
| 842 | |||
| 843 | usbhost2: usb@12110000 { | ||
| 844 | compatible = "samsung,exynos4210-ehci"; | ||
| 845 | reg = <0x12110000 0x100>; | ||
| 846 | interrupts = <0 71 0>; | ||
| 847 | |||
| 848 | clocks = <&clock CLK_USBH20>; | ||
| 849 | clock-names = "usbhost"; | ||
| 850 | #address-cells = <1>; | ||
| 851 | #size-cells = <0>; | ||
| 852 | port@0 { | ||
| 853 | reg = <0>; | ||
| 854 | phys = <&usb2_phy 1>; | ||
| 855 | }; | ||
| 856 | }; | ||
| 857 | |||
| 858 | usbhost1: usb@12120000 { | ||
| 859 | compatible = "samsung,exynos4210-ohci"; | ||
| 860 | reg = <0x12120000 0x100>; | ||
| 861 | interrupts = <0 71 0>; | ||
| 862 | |||
| 863 | clocks = <&clock CLK_USBH20>; | ||
| 864 | clock-names = "usbhost"; | ||
| 865 | #address-cells = <1>; | ||
| 866 | #size-cells = <0>; | ||
| 867 | port@0 { | ||
| 868 | reg = <0>; | ||
| 869 | phys = <&usb2_phy 1>; | ||
| 870 | }; | ||
| 871 | }; | ||
| 872 | |||
| 873 | usb2_phy: phy@12130000 { | ||
| 874 | compatible = "samsung,exynos5250-usb2-phy"; | ||
| 875 | reg = <0x12130000 0x100>; | ||
| 876 | clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; | ||
| 877 | clock-names = "phy", "ref"; | ||
| 878 | #phy-cells = <1>; | ||
| 879 | samsung,sysreg-phandle = <&sysreg_system_controller>; | ||
| 880 | samsung,pmureg-phandle = <&pmu_system_controller>; | ||
| 881 | }; | ||
| 731 | }; | 882 | }; |
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 84f77c2fe4d4..ae3a17c791f6 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi | |||
| @@ -176,7 +176,7 @@ | |||
| 176 | clock-names = "i2c"; | 176 | clock-names = "i2c"; |
| 177 | }; | 177 | }; |
| 178 | 178 | ||
| 179 | watchdog { | 179 | watchdog@110000 { |
| 180 | compatible = "samsung,s3c2410-wdt"; | 180 | compatible = "samsung,s3c2410-wdt"; |
| 181 | reg = <0x110000 0x1000>; | 181 | reg = <0x110000 0x1000>; |
| 182 | interrupts = <0 1 0>; | 182 | interrupts = <0 1 0>; |
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts new file mode 100644 index 000000000000..f3af2079a063 --- /dev/null +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts | |||
| @@ -0,0 +1,253 @@ | |||
| 1 | /* | ||
| 2 | * Google Peach Pi Rev 10+ board device tree source | ||
| 3 | * | ||
| 4 | * Copyright (c) 2014 Google, Inc | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /dts-v1/; | ||
| 12 | #include <dt-bindings/input/input.h> | ||
| 13 | #include <dt-bindings/gpio/gpio.h> | ||
| 14 | #include "exynos5800.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Google Peach Pi Rev 10+"; | ||
| 18 | |||
| 19 | compatible = "google,pi-rev16", | ||
| 20 | "google,pi-rev15", "google,pi-rev14", | ||
| 21 | "google,pi-rev13", "google,pi-rev12", | ||
| 22 | "google,pi-rev11", "google,pi-rev10", | ||
| 23 | "google,pi", "google,peach", "samsung,exynos5800", | ||
| 24 | "samsung,exynos5"; | ||
| 25 | |||
| 26 | memory { | ||
| 27 | reg = <0x20000000 0x80000000>; | ||
| 28 | }; | ||
| 29 | |||
| 30 | fixed-rate-clocks { | ||
| 31 | oscclk { | ||
| 32 | compatible = "samsung,exynos5420-oscclk"; | ||
| 33 | clock-frequency = <24000000>; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | |||
| 37 | gpio-keys { | ||
| 38 | compatible = "gpio-keys"; | ||
| 39 | |||
| 40 | pinctrl-names = "default"; | ||
| 41 | pinctrl-0 = <&power_key_irq>; | ||
| 42 | |||
| 43 | power { | ||
| 44 | label = "Power"; | ||
| 45 | gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; | ||
| 46 | linux,code = <KEY_POWER>; | ||
| 47 | gpio-key,wakeup; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | backlight { | ||
| 52 | compatible = "pwm-backlight"; | ||
| 53 | pwms = <&pwm 0 1000000 0>; | ||
| 54 | brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; | ||
| 55 | default-brightness-level = <7>; | ||
| 56 | pinctrl-0 = <&pwm0_out>; | ||
| 57 | pinctrl-names = "default"; | ||
| 58 | }; | ||
| 59 | |||
| 60 | usb300_vbus_reg: regulator-usb300 { | ||
| 61 | compatible = "regulator-fixed"; | ||
| 62 | regulator-name = "P5.0V_USB3CON0"; | ||
| 63 | regulator-min-microvolt = <5000000>; | ||
| 64 | regulator-max-microvolt = <5000000>; | ||
| 65 | gpio = <&gph0 0 0>; | ||
| 66 | pinctrl-names = "default"; | ||
| 67 | pinctrl-0 = <&usb300_vbus_en>; | ||
| 68 | enable-active-high; | ||
| 69 | }; | ||
| 70 | |||
| 71 | usb301_vbus_reg: regulator-usb301 { | ||
| 72 | compatible = "regulator-fixed"; | ||
| 73 | regulator-name = "P5.0V_USB3CON1"; | ||
| 74 | regulator-min-microvolt = <5000000>; | ||
| 75 | regulator-max-microvolt = <5000000>; | ||
| 76 | gpio = <&gph0 1 0>; | ||
| 77 | pinctrl-names = "default"; | ||
| 78 | pinctrl-0 = <&usb301_vbus_en>; | ||
| 79 | enable-active-high; | ||
| 80 | }; | ||
| 81 | }; | ||
| 82 | |||
| 83 | &pinctrl_0 { | ||
| 84 | tpm_irq: tpm-irq { | ||
| 85 | samsung,pins = "gpx1-0"; | ||
| 86 | samsung,pin-function = <0>; | ||
| 87 | samsung,pin-pud = <0>; | ||
| 88 | samsung,pin-drv = <0>; | ||
| 89 | }; | ||
| 90 | |||
| 91 | power_key_irq: power-key-irq { | ||
| 92 | samsung,pins = "gpx1-2"; | ||
| 93 | samsung,pin-function = <0>; | ||
| 94 | samsung,pin-pud = <0>; | ||
| 95 | samsung,pin-drv = <0>; | ||
| 96 | }; | ||
| 97 | |||
| 98 | dp_hpd_gpio: dp_hpd_gpio { | ||
| 99 | samsung,pins = "gpx2-6"; | ||
| 100 | samsung,pin-function = <0>; | ||
| 101 | samsung,pin-pud = <3>; | ||
| 102 | samsung,pin-drv = <0>; | ||
| 103 | }; | ||
| 104 | |||
| 105 | hdmi_hpd_irq: hdmi-hpd-irq { | ||
| 106 | samsung,pins = "gpx3-7"; | ||
| 107 | samsung,pin-function = <0>; | ||
| 108 | samsung,pin-pud = <1>; | ||
| 109 | samsung,pin-drv = <0>; | ||
| 110 | }; | ||
| 111 | }; | ||
| 112 | |||
| 113 | &pinctrl_3 { | ||
| 114 | usb300_vbus_en: usb300-vbus-en { | ||
| 115 | samsung,pins = "gph0-0"; | ||
| 116 | samsung,pin-function = <1>; | ||
| 117 | samsung,pin-pud = <0>; | ||
| 118 | samsung,pin-drv = <0>; | ||
| 119 | }; | ||
| 120 | |||
| 121 | usb301_vbus_en: usb301-vbus-en { | ||
| 122 | samsung,pins = "gph0-1"; | ||
| 123 | samsung,pin-function = <1>; | ||
| 124 | samsung,pin-pud = <0>; | ||
| 125 | samsung,pin-drv = <0>; | ||
| 126 | }; | ||
| 127 | }; | ||
| 128 | |||
| 129 | &rtc { | ||
| 130 | status = "okay"; | ||
| 131 | }; | ||
| 132 | |||
| 133 | &uart_3 { | ||
| 134 | status = "okay"; | ||
| 135 | }; | ||
| 136 | |||
| 137 | &mmc_0 { | ||
| 138 | status = "okay"; | ||
| 139 | num-slots = <1>; | ||
| 140 | broken-cd; | ||
| 141 | caps2-mmc-hs200-1_8v; | ||
| 142 | supports-highspeed; | ||
| 143 | non-removable; | ||
| 144 | card-detect-delay = <200>; | ||
| 145 | clock-frequency = <400000000>; | ||
| 146 | samsung,dw-mshc-ciu-div = <3>; | ||
| 147 | samsung,dw-mshc-sdr-timing = <0 4>; | ||
| 148 | samsung,dw-mshc-ddr-timing = <0 2>; | ||
| 149 | pinctrl-names = "default"; | ||
| 150 | pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; | ||
| 151 | |||
| 152 | slot@0 { | ||
| 153 | reg = <0>; | ||
| 154 | bus-width = <8>; | ||
| 155 | }; | ||
| 156 | }; | ||
| 157 | |||
| 158 | &mmc_2 { | ||
| 159 | status = "okay"; | ||
| 160 | num-slots = <1>; | ||
| 161 | supports-highspeed; | ||
| 162 | card-detect-delay = <200>; | ||
| 163 | clock-frequency = <400000000>; | ||
| 164 | samsung,dw-mshc-ciu-div = <3>; | ||
| 165 | samsung,dw-mshc-sdr-timing = <2 3>; | ||
| 166 | samsung,dw-mshc-ddr-timing = <1 2>; | ||
| 167 | pinctrl-names = "default"; | ||
| 168 | pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; | ||
| 169 | |||
| 170 | slot@0 { | ||
| 171 | reg = <0>; | ||
| 172 | bus-width = <4>; | ||
| 173 | }; | ||
| 174 | }; | ||
| 175 | |||
| 176 | &dp { | ||
| 177 | status = "okay"; | ||
| 178 | pinctrl-names = "default"; | ||
| 179 | pinctrl-0 = <&dp_hpd_gpio>; | ||
| 180 | samsung,color-space = <0>; | ||
| 181 | samsung,dynamic-range = <0>; | ||
| 182 | samsung,ycbcr-coeff = <0>; | ||
| 183 | samsung,color-depth = <1>; | ||
| 184 | samsung,link-rate = <0x0a>; | ||
| 185 | samsung,lane-count = <2>; | ||
| 186 | samsung,hpd-gpio = <&gpx2 6 0>; | ||
| 187 | |||
| 188 | display-timings { | ||
| 189 | native-mode = <&timing1>; | ||
| 190 | |||
| 191 | timing1: timing@1 { | ||
| 192 | clock-frequency = <150660000>; | ||
| 193 | hactive = <1920>; | ||
| 194 | vactive = <1080>; | ||
| 195 | hfront-porch = <60>; | ||
| 196 | hback-porch = <172>; | ||
| 197 | hsync-len = <80>; | ||
| 198 | vback-porch = <25>; | ||
| 199 | vfront-porch = <10>; | ||
| 200 | vsync-len = <10>; | ||
| 201 | }; | ||
| 202 | }; | ||
| 203 | }; | ||
| 204 | |||
| 205 | &fimd { | ||
| 206 | status = "okay"; | ||
| 207 | samsung,invert-vclk; | ||
| 208 | }; | ||
| 209 | |||
| 210 | &hsi2c_9 { | ||
| 211 | status = "okay"; | ||
| 212 | clock-frequency = <400000>; | ||
| 213 | |||
| 214 | tpm@20 { | ||
| 215 | compatible = "infineon,slb9645tt"; | ||
| 216 | reg = <0x20>; | ||
| 217 | /* Unused irq; but still need to configure the pins */ | ||
| 218 | pinctrl-names = "default"; | ||
| 219 | pinctrl-0 = <&tpm_irq>; | ||
| 220 | }; | ||
| 221 | }; | ||
| 222 | |||
| 223 | &i2c_2 { | ||
| 224 | status = "okay"; | ||
| 225 | samsung,i2c-sda-delay = <100>; | ||
| 226 | samsung,i2c-max-bus-freq = <66000>; | ||
| 227 | samsung,i2c-slave-addr = <0x50>; | ||
| 228 | }; | ||
| 229 | |||
| 230 | &hdmi { | ||
| 231 | status = "okay"; | ||
| 232 | hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; | ||
| 233 | pinctrl-names = "default"; | ||
| 234 | pinctrl-0 = <&hdmi_hpd_irq>; | ||
| 235 | ddc = <&i2c_2>; | ||
| 236 | }; | ||
| 237 | |||
| 238 | &usbdrd_phy0 { | ||
| 239 | vbus-supply = <&usb300_vbus_reg>; | ||
| 240 | }; | ||
| 241 | |||
| 242 | &usbdrd_phy1 { | ||
| 243 | vbus-supply = <&usb301_vbus_reg>; | ||
| 244 | }; | ||
| 245 | |||
| 246 | /* | ||
| 247 | * Use longest HW watchdog in SoC (32 seconds) since the hardware | ||
| 248 | * watchdog provides no debugging information (compared to soft/hard | ||
| 249 | * lockup detectors) and so should be last resort. | ||
| 250 | */ | ||
| 251 | &watchdog { | ||
| 252 | timeout-sec = <32>; | ||
| 253 | }; | ||
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi new file mode 100644 index 000000000000..c0bb3563cac1 --- /dev/null +++ b/arch/arm/boot/dts/exynos5800.dtsi | |||
| @@ -0,0 +1,28 @@ | |||
| 1 | /* | ||
| 2 | * SAMSUNG EXYNOS5800 SoC device tree source | ||
| 3 | * | ||
| 4 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. | ||
| 5 | * http://www.samsung.com | ||
| 6 | * | ||
| 7 | * SAMSUNG EXYNOS5800 SoC device nodes are listed in this file. | ||
| 8 | * EXYNOS5800 based board files can include this file and provide | ||
| 9 | * values for board specfic bindings. | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include "exynos5420.dtsi" | ||
| 17 | |||
| 18 | / { | ||
| 19 | compatible = "samsung,exynos5800", "samsung,exynos5"; | ||
| 20 | }; | ||
| 21 | |||
| 22 | &clock { | ||
| 23 | compatible = "samsung,exynos5800-clock"; | ||
| 24 | }; | ||
| 25 | |||
| 26 | &mfc { | ||
| 27 | compatible = "samsung,mfc-v8"; | ||
| 28 | }; | ||
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts index 62fb3da50bdb..ad12da38fc92 100644 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts | |||
| @@ -172,3 +172,16 @@ | |||
| 172 | fsl,uart-has-rtscts; | 172 | fsl,uart-has-rtscts; |
| 173 | status = "okay"; | 173 | status = "okay"; |
| 174 | }; | 174 | }; |
| 175 | |||
| 176 | &usbhost1 { | ||
| 177 | phy_type = "serial"; | ||
| 178 | dr_mode = "host"; | ||
| 179 | status = "okay"; | ||
| 180 | }; | ||
| 181 | |||
| 182 | &usbotg { | ||
| 183 | phy_type = "utmi"; | ||
| 184 | dr_mode = "otg"; | ||
| 185 | external-vbus-divider; | ||
| 186 | status = "okay"; | ||
| 187 | }; | ||
diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts index f8db366c46ff..9b31faa96377 100644 --- a/arch/arm/boot/dts/imx25-karo-tx25.dts +++ b/arch/arm/boot/dts/imx25-karo-tx25.dts | |||
| @@ -16,21 +16,98 @@ | |||
| 16 | model = "Ka-Ro TX25"; | 16 | model = "Ka-Ro TX25"; |
| 17 | compatible = "karo,imx25-tx25", "fsl,imx25"; | 17 | compatible = "karo,imx25-tx25", "fsl,imx25"; |
| 18 | 18 | ||
| 19 | chosen { | ||
| 20 | stdout-path = &uart1; | ||
| 21 | }; | ||
| 22 | |||
| 23 | regulators { | ||
| 24 | compatible = "simple-bus"; | ||
| 25 | #address-cells = <1>; | ||
| 26 | #size-cells = <0>; | ||
| 27 | |||
| 28 | reg_fec_phy: regulator@0 { | ||
| 29 | compatible = "regulator-fixed"; | ||
| 30 | reg = <0>; | ||
| 31 | regulator-name = "fec-phy"; | ||
| 32 | regulator-min-microvolt = <3300000>; | ||
| 33 | regulator-max-microvolt = <3300000>; | ||
| 34 | gpio = <&gpio4 9 0>; | ||
| 35 | enable-active-high; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | |||
| 19 | memory { | 39 | memory { |
| 20 | reg = <0x80000000 0x02000000 0x90000000 0x02000000>; | 40 | reg = <0x80000000 0x02000000 0x90000000 0x02000000>; |
| 21 | }; | 41 | }; |
| 22 | }; | 42 | }; |
| 23 | 43 | ||
| 44 | &iomuxc { | ||
| 45 | pinctrl_uart1: uart1grp { | ||
| 46 | fsl,pins = < | ||
| 47 | MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 | ||
| 48 | MX25_PAD_UART1_RXD__UART1_RXD 0x80000000 | ||
| 49 | MX25_PAD_UART1_CTS__UART1_CTS 0x80000000 | ||
| 50 | MX25_PAD_UART1_RTS__UART1_RTS 0x80000000 | ||
| 51 | >; | ||
| 52 | }; | ||
| 53 | |||
| 54 | pinctrl_fec: fecgrp { | ||
| 55 | fsl,pins = < | ||
| 56 | MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */ | ||
| 57 | MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */ | ||
| 58 | MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 | ||
| 59 | MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000 | ||
| 60 | MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 | ||
| 61 | MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 | ||
| 62 | MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | ||
| 63 | MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 | ||
| 64 | MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 | ||
| 65 | MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 | ||
| 66 | MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 | ||
| 67 | >; | ||
| 68 | }; | ||
| 69 | |||
| 70 | pinctrl_nfc: nfcgrp { | ||
| 71 | fsl,pins = < | ||
| 72 | MX25_PAD_NF_CE0__NF_CE0 0x80000000 | ||
| 73 | MX25_PAD_NFWE_B__NFWE_B 0x80000000 | ||
| 74 | MX25_PAD_NFRE_B__NFRE_B 0x80000000 | ||
| 75 | MX25_PAD_NFALE__NFALE 0x80000000 | ||
| 76 | MX25_PAD_NFCLE__NFCLE 0x80000000 | ||
| 77 | MX25_PAD_NFWP_B__NFWP_B 0x80000000 | ||
| 78 | MX25_PAD_NFRB__NFRB 0x80000000 | ||
| 79 | MX25_PAD_D7__D7 0x80000000 | ||
| 80 | MX25_PAD_D6__D6 0x80000000 | ||
| 81 | MX25_PAD_D5__D5 0x80000000 | ||
| 82 | MX25_PAD_D4__D4 0x80000000 | ||
| 83 | MX25_PAD_D3__D3 0x80000000 | ||
| 84 | MX25_PAD_D2__D2 0x80000000 | ||
| 85 | MX25_PAD_D1__D1 0x80000000 | ||
| 86 | MX25_PAD_D0__D0 0x80000000 | ||
| 87 | >; | ||
| 88 | }; | ||
| 89 | }; | ||
| 90 | |||
| 24 | &uart1 { | 91 | &uart1 { |
| 92 | pinctrl-names = "default"; | ||
| 93 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 25 | status = "okay"; | 94 | status = "okay"; |
| 26 | }; | 95 | }; |
| 27 | 96 | ||
| 28 | &fec { | 97 | &fec { |
| 98 | pinctrl-names = "default"; | ||
| 99 | pinctrl-0 = <&pinctrl_fec>; | ||
| 100 | phy-reset-gpios = <&gpio3 7 0>; | ||
| 29 | phy-mode = "rmii"; | 101 | phy-mode = "rmii"; |
| 102 | phy-supply = <®_fec_phy>; | ||
| 30 | status = "okay"; | 103 | status = "okay"; |
| 31 | }; | 104 | }; |
| 32 | 105 | ||
| 33 | &nfc { | 106 | &nfc { |
| 107 | pinctrl-names = "default"; | ||
| 108 | pinctrl-0 = <&pinctrl_nfc>; | ||
| 34 | nand-on-flash-bbt; | 109 | nand-on-flash-bbt; |
| 110 | nand-ecc-mode = "hw"; | ||
| 111 | nand-bus-width = <8>; | ||
| 35 | status = "okay"; | 112 | status = "okay"; |
| 36 | }; | 113 | }; |
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index f607ce520eda..c608942b8a3b 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts | |||
| @@ -10,6 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | #include <dt-bindings/input/input.h> | ||
| 13 | #include "imx25.dtsi" | 14 | #include "imx25.dtsi" |
| 14 | 15 | ||
| 15 | / { | 16 | / { |
| @@ -19,18 +20,232 @@ | |||
| 19 | memory { | 20 | memory { |
| 20 | reg = <0x80000000 0x4000000>; | 21 | reg = <0x80000000 0x4000000>; |
| 21 | }; | 22 | }; |
| 23 | |||
| 24 | regulators { | ||
| 25 | compatible = "simple-bus"; | ||
| 26 | #address-cells = <1>; | ||
| 27 | #size-cells = <0>; | ||
| 28 | |||
| 29 | reg_fec_3v3: regulator@0 { | ||
| 30 | compatible = "regulator-fixed"; | ||
| 31 | reg = <0>; | ||
| 32 | regulator-name = "fec-3v3"; | ||
| 33 | regulator-min-microvolt = <3300000>; | ||
| 34 | regulator-max-microvolt = <3300000>; | ||
| 35 | gpio = <&gpio2 3 0>; | ||
| 36 | enable-active-high; | ||
| 37 | }; | ||
| 38 | |||
| 39 | reg_2p5v: regulator@1 { | ||
| 40 | compatible = "regulator-fixed"; | ||
| 41 | reg = <1>; | ||
| 42 | regulator-name = "2P5V"; | ||
| 43 | regulator-min-microvolt = <2500000>; | ||
| 44 | regulator-max-microvolt = <2500000>; | ||
| 45 | }; | ||
| 46 | |||
| 47 | reg_3p3v: regulator@2 { | ||
| 48 | compatible = "regulator-fixed"; | ||
| 49 | reg = <2>; | ||
| 50 | regulator-name = "3P3V"; | ||
| 51 | regulator-min-microvolt = <3300000>; | ||
| 52 | regulator-max-microvolt = <3300000>; | ||
| 53 | }; | ||
| 54 | |||
| 55 | reg_can_3v3: regulator@3 { | ||
| 56 | compatible = "regulator-fixed"; | ||
| 57 | reg = <3>; | ||
| 58 | regulator-name = "can-3v3"; | ||
| 59 | regulator-min-microvolt = <3300000>; | ||
| 60 | regulator-max-microvolt = <3300000>; | ||
| 61 | gpio = <&gpio4 6 0>; | ||
| 62 | }; | ||
| 63 | }; | ||
| 64 | |||
| 65 | sound { | ||
| 66 | compatible = "fsl,imx25-pdk-sgtl5000", | ||
| 67 | "fsl,imx-audio-sgtl5000"; | ||
| 68 | model = "imx25-pdk-sgtl5000"; | ||
| 69 | ssi-controller = <&ssi1>; | ||
| 70 | audio-codec = <&codec>; | ||
| 71 | audio-routing = | ||
| 72 | "MIC_IN", "Mic Jack", | ||
| 73 | "Mic Jack", "Mic Bias", | ||
| 74 | "Headphone Jack", "HP_OUT"; | ||
| 75 | mux-int-port = <1>; | ||
| 76 | mux-ext-port = <4>; | ||
| 77 | }; | ||
| 22 | }; | 78 | }; |
| 23 | 79 | ||
| 24 | &uart1 { | 80 | &audmux { |
| 81 | pinctrl-names = "default"; | ||
| 82 | pinctrl-0 = <&pinctrl_audmux>; | ||
| 83 | status = "okay"; | ||
| 84 | }; | ||
| 85 | |||
| 86 | &can1 { | ||
| 87 | pinctrl-names = "default"; | ||
| 88 | pinctrl-0 = <&pinctrl_can1>; | ||
| 89 | xceiver-supply = <®_can_3v3>; | ||
| 90 | status = "okay"; | ||
| 91 | }; | ||
| 92 | |||
| 93 | &esdhc1 { | ||
| 94 | pinctrl-names = "default"; | ||
| 95 | pinctrl-0 = <&pinctrl_esdhc1>; | ||
| 96 | cd-gpios = <&gpio2 1 0>; | ||
| 97 | wp-gpios = <&gpio2 0 0>; | ||
| 25 | status = "okay"; | 98 | status = "okay"; |
| 26 | }; | 99 | }; |
| 27 | 100 | ||
| 28 | &fec { | 101 | &fec { |
| 29 | phy-mode = "rmii"; | 102 | phy-mode = "rmii"; |
| 103 | pinctrl-names = "default"; | ||
| 104 | pinctrl-0 = <&pinctrl_fec>; | ||
| 105 | phy-supply = <®_fec_3v3>; | ||
| 106 | phy-reset-gpios = <&gpio4 8 0>; | ||
| 30 | status = "okay"; | 107 | status = "okay"; |
| 31 | }; | 108 | }; |
| 32 | 109 | ||
| 110 | &i2c1 { | ||
| 111 | clock-frequency = <100000>; | ||
| 112 | pinctrl-names = "default"; | ||
| 113 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 114 | status = "okay"; | ||
| 115 | |||
| 116 | codec: sgtl5000@0a { | ||
| 117 | compatible = "fsl,sgtl5000"; | ||
| 118 | reg = <0x0a>; | ||
| 119 | clocks = <&clks 129>; | ||
| 120 | VDDA-supply = <®_2p5v>; | ||
| 121 | VDDIO-supply = <®_3p3v>; | ||
| 122 | }; | ||
| 123 | }; | ||
| 124 | |||
| 125 | &iomuxc { | ||
| 126 | imx25-pdk { | ||
| 127 | pinctrl_audmux: audmuxgrp { | ||
| 128 | fsl,pins = < | ||
| 129 | MX25_PAD_RW__AUD4_TXFS 0xe0 | ||
| 130 | MX25_PAD_OE__AUD4_TXC 0xe0 | ||
| 131 | MX25_PAD_EB0__AUD4_TXD 0xe0 | ||
| 132 | MX25_PAD_EB1__AUD4_RXD 0xe0 | ||
| 133 | >; | ||
| 134 | }; | ||
| 135 | |||
| 136 | pinctrl_can1: can1grp { | ||
| 137 | fsl,pins = < | ||
| 138 | MX25_PAD_GPIO_A__CAN1_TX 0x0 | ||
| 139 | MX25_PAD_GPIO_B__CAN1_RX 0x0 | ||
| 140 | MX25_PAD_D14__GPIO_4_6 0x80000000 | ||
| 141 | >; | ||
| 142 | }; | ||
| 143 | |||
| 144 | pinctrl_esdhc1: esdhc1grp { | ||
| 145 | fsl,pins = < | ||
| 146 | MX25_PAD_SD1_CMD__SD1_CMD 0x80000000 | ||
| 147 | MX25_PAD_SD1_CLK__SD1_CLK 0x80000000 | ||
| 148 | MX25_PAD_SD1_DATA0__SD1_DATA0 0x80000000 | ||
| 149 | MX25_PAD_SD1_DATA1__SD1_DATA1 0x80000000 | ||
| 150 | MX25_PAD_SD1_DATA2__SD1_DATA2 0x80000000 | ||
| 151 | MX25_PAD_SD1_DATA3__SD1_DATA3 0x80000000 | ||
| 152 | MX25_PAD_A14__GPIO_2_0 0x80000000 | ||
| 153 | MX25_PAD_A15__GPIO_2_1 0x80000000 | ||
| 154 | >; | ||
| 155 | }; | ||
| 156 | |||
| 157 | pinctrl_fec: fecgrp { | ||
| 158 | fsl,pins = < | ||
| 159 | MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 | ||
| 160 | MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 | ||
| 161 | MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 | ||
| 162 | MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 | ||
| 163 | MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | ||
| 164 | MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 | ||
| 165 | MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 | ||
| 166 | MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 | ||
| 167 | MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 | ||
| 168 | MX25_PAD_A17__GPIO_2_3 0x80000000 | ||
| 169 | MX25_PAD_D12__GPIO_4_8 0x80000000 | ||
| 170 | >; | ||
| 171 | }; | ||
| 172 | |||
| 173 | pinctrl_i2c1: i2c1grp { | ||
| 174 | fsl,pins = < | ||
| 175 | MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 | ||
| 176 | MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 | ||
| 177 | >; | ||
| 178 | }; | ||
| 179 | |||
| 180 | pinctrl_kpp: kppgrp { | ||
| 181 | fsl,pins = < | ||
| 182 | MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000 | ||
| 183 | MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000 | ||
| 184 | MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000 | ||
| 185 | MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000 | ||
| 186 | MX25_PAD_KPP_COL0__KPP_COL0 0x80000000 | ||
| 187 | MX25_PAD_KPP_COL1__KPP_COL1 0x80000000 | ||
| 188 | MX25_PAD_KPP_COL2__KPP_COL2 0x80000000 | ||
| 189 | MX25_PAD_KPP_COL3__KPP_COL3 0x80000000 | ||
| 190 | >; | ||
| 191 | }; | ||
| 192 | |||
| 193 | |||
| 194 | pinctrl_uart1: uart1grp { | ||
| 195 | fsl,pins = < | ||
| 196 | MX25_PAD_UART1_RTS__UART1_RTS 0xe0 | ||
| 197 | MX25_PAD_UART1_CTS__UART1_CTS 0xe0 | ||
| 198 | MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 | ||
| 199 | MX25_PAD_UART1_RXD__UART1_RXD 0xc0 | ||
| 200 | >; | ||
| 201 | }; | ||
| 202 | }; | ||
| 203 | }; | ||
| 204 | |||
| 33 | &nfc { | 205 | &nfc { |
| 34 | nand-on-flash-bbt; | 206 | nand-on-flash-bbt; |
| 35 | status = "okay"; | 207 | status = "okay"; |
| 36 | }; | 208 | }; |
| 209 | |||
| 210 | &kpp { | ||
| 211 | pinctrl-names = "default"; | ||
| 212 | pinctrl-0 = <&pinctrl_kpp>; | ||
| 213 | linux,keymap = < | ||
| 214 | MATRIX_KEY(0x0, 0x0, KEY_UP) | ||
| 215 | MATRIX_KEY(0x0, 0x1, KEY_DOWN) | ||
| 216 | MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN) | ||
| 217 | MATRIX_KEY(0x0, 0x3, KEY_HOME) | ||
| 218 | MATRIX_KEY(0x1, 0x0, KEY_RIGHT) | ||
| 219 | MATRIX_KEY(0x1, 0x1, KEY_LEFT) | ||
| 220 | MATRIX_KEY(0x1, 0x2, KEY_ENTER) | ||
| 221 | MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP) | ||
| 222 | MATRIX_KEY(0x2, 0x0, KEY_F6) | ||
| 223 | MATRIX_KEY(0x2, 0x1, KEY_F8) | ||
| 224 | MATRIX_KEY(0x2, 0x2, KEY_F9) | ||
| 225 | MATRIX_KEY(0x2, 0x3, KEY_F10) | ||
| 226 | MATRIX_KEY(0x3, 0x0, KEY_F1) | ||
| 227 | MATRIX_KEY(0x3, 0x1, KEY_F2) | ||
| 228 | MATRIX_KEY(0x3, 0x2, KEY_F3) | ||
| 229 | MATRIX_KEY(0x3, 0x2, KEY_POWER) | ||
| 230 | >; | ||
| 231 | status = "okay"; | ||
| 232 | }; | ||
| 233 | |||
| 234 | &ssi1 { | ||
| 235 | codec-handle = <&codec>; | ||
| 236 | fsl,mode = "i2s-slave"; | ||
| 237 | status = "okay"; | ||
| 238 | }; | ||
| 239 | |||
| 240 | &uart1 { | ||
| 241 | pinctrl-names = "default"; | ||
| 242 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 243 | fsl,uart-has-rtscts; | ||
| 244 | status = "okay"; | ||
| 245 | }; | ||
| 246 | |||
| 247 | &usbhost1 { | ||
| 248 | phy_type = "serial"; | ||
| 249 | dr_mode = "host"; | ||
| 250 | status = "okay"; | ||
| 251 | }; | ||
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index ea323f09dc78..bb74d9582b7e 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | aliases { | 16 | aliases { |
| 17 | ethernet0 = &fec; | ||
| 17 | gpio0 = &gpio1; | 18 | gpio0 = &gpio1; |
| 18 | gpio1 = &gpio2; | 19 | gpio1 = &gpio2; |
| 19 | gpio2 = &gpio3; | 20 | gpio2 = &gpio3; |
| @@ -21,6 +22,8 @@ | |||
| 21 | i2c0 = &i2c1; | 22 | i2c0 = &i2c1; |
| 22 | i2c1 = &i2c2; | 23 | i2c1 = &i2c2; |
| 23 | i2c2 = &i2c3; | 24 | i2c2 = &i2c3; |
| 25 | mmc0 = &esdhc1; | ||
| 26 | mmc1 = &esdhc2; | ||
| 24 | serial0 = &uart1; | 27 | serial0 = &uart1; |
| 25 | serial1 = &uart2; | 28 | serial1 = &uart2; |
| 26 | serial2 = &uart3; | 29 | serial2 = &uart3; |
| @@ -165,9 +168,10 @@ | |||
| 165 | status = "disabled"; | 168 | status = "disabled"; |
| 166 | }; | 169 | }; |
| 167 | 170 | ||
| 168 | kpp@43fa8000 { | 171 | kpp: kpp@43fa8000 { |
| 169 | #address-cells = <1>; | 172 | #address-cells = <1>; |
| 170 | #size-cells = <0>; | 173 | #size-cells = <0>; |
| 174 | compatible = "fsl,imx25-kpp", "fsl,imx21-kpp"; | ||
| 171 | reg = <0x43fa8000 0x4000>; | 175 | reg = <0x43fa8000 0x4000>; |
| 172 | clocks = <&clks 102>; | 176 | clocks = <&clks 102>; |
| 173 | clock-names = ""; | 177 | clock-names = ""; |
| @@ -482,23 +486,13 @@ | |||
| 482 | clocks = <&clks 99>; | 486 | clocks = <&clks 99>; |
| 483 | }; | 487 | }; |
| 484 | 488 | ||
| 485 | usbphy1: usbphy@1 { | ||
| 486 | compatible = "nop-usbphy"; | ||
| 487 | status = "disabled"; | ||
| 488 | }; | ||
| 489 | |||
| 490 | usbphy2: usbphy@2 { | ||
| 491 | compatible = "nop-usbphy"; | ||
| 492 | status = "disabled"; | ||
| 493 | }; | ||
| 494 | |||
| 495 | usbotg: usb@53ff4000 { | 489 | usbotg: usb@53ff4000 { |
| 496 | compatible = "fsl,imx25-usb", "fsl,imx27-usb"; | 490 | compatible = "fsl,imx25-usb", "fsl,imx27-usb"; |
| 497 | reg = <0x53ff4000 0x0200>; | 491 | reg = <0x53ff4000 0x0200>; |
| 498 | interrupts = <37>; | 492 | interrupts = <37>; |
| 499 | clocks = <&clks 9>, <&clks 70>, <&clks 8>; | 493 | clocks = <&clks 70>; |
| 500 | clock-names = "ipg", "ahb", "per"; | ||
| 501 | fsl,usbmisc = <&usbmisc 0>; | 494 | fsl,usbmisc = <&usbmisc 0>; |
| 495 | fsl,usbphy = <&usbphy0>; | ||
| 502 | status = "disabled"; | 496 | status = "disabled"; |
| 503 | }; | 497 | }; |
| 504 | 498 | ||
| @@ -506,9 +500,9 @@ | |||
| 506 | compatible = "fsl,imx25-usb", "fsl,imx27-usb"; | 500 | compatible = "fsl,imx25-usb", "fsl,imx27-usb"; |
| 507 | reg = <0x53ff4400 0x0200>; | 501 | reg = <0x53ff4400 0x0200>; |
| 508 | interrupts = <35>; | 502 | interrupts = <35>; |
| 509 | clocks = <&clks 9>, <&clks 70>, <&clks 8>; | 503 | clocks = <&clks 70>; |
| 510 | clock-names = "ipg", "ahb", "per"; | ||
| 511 | fsl,usbmisc = <&usbmisc 1>; | 504 | fsl,usbmisc = <&usbmisc 1>; |
| 505 | fsl,usbphy = <&usbphy1>; | ||
| 512 | status = "disabled"; | 506 | status = "disabled"; |
| 513 | }; | 507 | }; |
| 514 | 508 | ||
| @@ -518,7 +512,6 @@ | |||
| 518 | clocks = <&clks 9>, <&clks 70>, <&clks 8>; | 512 | clocks = <&clks 9>, <&clks 70>, <&clks 8>; |
| 519 | clock-names = "ipg", "ahb", "per"; | 513 | clock-names = "ipg", "ahb", "per"; |
| 520 | reg = <0x53ff4600 0x00f>; | 514 | reg = <0x53ff4600 0x00f>; |
| 521 | status = "disabled"; | ||
| 522 | }; | 515 | }; |
| 523 | 516 | ||
| 524 | dryice@53ffc000 { | 517 | dryice@53ffc000 { |
| @@ -530,6 +523,11 @@ | |||
| 530 | }; | 523 | }; |
| 531 | }; | 524 | }; |
| 532 | 525 | ||
| 526 | iram: sram@78000000 { | ||
| 527 | compatible = "mmio-sram"; | ||
| 528 | reg = <0x78000000 0x20000>; | ||
| 529 | }; | ||
| 530 | |||
| 533 | emi@80000000 { | 531 | emi@80000000 { |
| 534 | compatible = "fsl,emi-bus", "simple-bus"; | 532 | compatible = "fsl,emi-bus", "simple-bus"; |
| 535 | #address-cells = <1>; | 533 | #address-cells = <1>; |
| @@ -550,4 +548,20 @@ | |||
| 550 | }; | 548 | }; |
| 551 | }; | 549 | }; |
| 552 | }; | 550 | }; |
| 551 | |||
| 552 | usbphy { | ||
| 553 | compatible = "simple-bus"; | ||
| 554 | #address-cells = <1>; | ||
| 555 | #size-cells = <0>; | ||
| 556 | |||
| 557 | usbphy0: usb-phy@0 { | ||
| 558 | reg = <0>; | ||
| 559 | compatible = "usb-nop-xceiv"; | ||
| 560 | }; | ||
| 561 | |||
| 562 | usbphy1: usb-phy@1 { | ||
| 563 | reg = <1>; | ||
| 564 | compatible = "usb-nop-xceiv"; | ||
| 565 | }; | ||
| 566 | }; | ||
| 553 | }; | 567 | }; |
diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index 5ce89aa275df..4c317716b510 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts | |||
| @@ -17,15 +17,181 @@ | |||
| 17 | compatible = "fsl,imx27-pdk", "fsl,imx27"; | 17 | compatible = "fsl,imx27-pdk", "fsl,imx27"; |
| 18 | 18 | ||
| 19 | memory { | 19 | memory { |
| 20 | reg = <0x0 0x0>; | 20 | reg = <0xa0000000 0x08000000>; |
| 21 | }; | 21 | }; |
| 22 | |||
| 23 | usbphy { | ||
| 24 | compatible = "simple-bus"; | ||
| 25 | #address-cells = <1>; | ||
| 26 | #size-cells = <0>; | ||
| 27 | |||
| 28 | usbphy0: usbphy@0 { | ||
| 29 | compatible = "usb-nop-xceiv"; | ||
| 30 | reg = <0>; | ||
| 31 | clocks = <&clks 0>; | ||
| 32 | clock-names = "main_clk"; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | |||
| 37 | &cspi2 { | ||
| 38 | pinctrl-names = "default"; | ||
| 39 | pinctrl-0 = <&pinctrl_cspi2>; | ||
| 40 | fsl,spi-num-chipselects = <1>; | ||
| 41 | cs-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; | ||
| 42 | status = "okay"; | ||
| 43 | |||
| 44 | pmic: mc13783@0 { | ||
| 45 | compatible = "fsl,mc13783"; | ||
| 46 | reg = <0>; | ||
| 47 | spi-cs-high; | ||
| 48 | spi-max-frequency = <1000000>; | ||
| 49 | interrupt-parent = <&gpio3>; | ||
| 50 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; | ||
| 51 | |||
| 52 | regulators { | ||
| 53 | vgen_reg: vgen { | ||
| 54 | regulator-min-microvolt = <1500000>; | ||
| 55 | regulator-max-microvolt = <1500000>; | ||
| 56 | regulator-always-on; | ||
| 57 | regulator-boot-on; | ||
| 58 | }; | ||
| 59 | |||
| 60 | vmmc1_reg: vmmc1 { | ||
| 61 | regulator-min-microvolt = <1600000>; | ||
| 62 | regulator-max-microvolt = <3000000>; | ||
| 63 | }; | ||
| 64 | |||
| 65 | gpo1_reg: gpo1 { | ||
| 66 | regulator-always-on; | ||
| 67 | regulator-boot-on; | ||
| 68 | }; | ||
| 69 | |||
| 70 | gpo3_reg: gpo3 { | ||
| 71 | regulator-always-on; | ||
| 72 | regulator-boot-on; | ||
| 73 | }; | ||
| 74 | }; | ||
| 75 | }; | ||
| 76 | }; | ||
| 77 | |||
| 78 | &fec { | ||
| 79 | phy-mode = "mii"; | ||
| 80 | pinctrl-names = "default"; | ||
| 81 | pinctrl-0 = <&pinctrl_fec>; | ||
| 82 | status = "okay"; | ||
| 83 | }; | ||
| 84 | |||
| 85 | &kpp { | ||
| 86 | linux,keymap = < | ||
| 87 | MATRIX_KEY(0, 0, KEY_UP) | ||
| 88 | MATRIX_KEY(0, 1, KEY_DOWN) | ||
| 89 | MATRIX_KEY(1, 0, KEY_RIGHT) | ||
| 90 | MATRIX_KEY(1, 1, KEY_LEFT) | ||
| 91 | MATRIX_KEY(1, 2, KEY_ENTER) | ||
| 92 | MATRIX_KEY(2, 0, KEY_F6) | ||
| 93 | MATRIX_KEY(2, 1, KEY_F8) | ||
| 94 | MATRIX_KEY(2, 2, KEY_F9) | ||
| 95 | MATRIX_KEY(2, 3, KEY_F10) | ||
| 96 | >; | ||
| 97 | status = "okay"; | ||
| 98 | }; | ||
| 99 | |||
| 100 | &nfc { | ||
| 101 | pinctrl-names = "default"; | ||
| 102 | pinctrl-0 = <&pinctrl_nand>; | ||
| 103 | nand-ecc-mode = "hw"; | ||
| 104 | nand-on-flash-bbt; | ||
| 105 | status = "okay"; | ||
| 22 | }; | 106 | }; |
| 23 | 107 | ||
| 24 | &uart1 { | 108 | &uart1 { |
| 25 | fsl,uart-has-rtscts; | 109 | fsl,uart-has-rtscts; |
| 110 | pinctrl-names = "default"; | ||
| 111 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 26 | status = "okay"; | 112 | status = "okay"; |
| 27 | }; | 113 | }; |
| 28 | 114 | ||
| 29 | &fec { | 115 | &usbotg { |
| 116 | pinctrl-names = "default"; | ||
| 117 | pinctrl-0 = <&pinctrl_usbotg>; | ||
| 118 | dr_mode = "otg"; | ||
| 119 | fsl,usbphy = <&usbphy0>; | ||
| 120 | phy_type = "ulpi"; | ||
| 30 | status = "okay"; | 121 | status = "okay"; |
| 31 | }; | 122 | }; |
| 123 | |||
| 124 | &iomuxc { | ||
| 125 | imx27-pdk { | ||
| 126 | pinctrl_cspi2: cspi2grp { | ||
| 127 | fsl,pins = < | ||
| 128 | MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 | ||
| 129 | MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 | ||
| 130 | MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 | ||
| 131 | MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 /* SPI2 CS0 */ | ||
| 132 | MX27_PAD_TOUT__GPIO3_14 0x0 /* PMIC IRQ */ | ||
| 133 | >; | ||
| 134 | }; | ||
| 135 | |||
| 136 | pinctrl_fec: fecgrp { | ||
| 137 | fsl,pins = < | ||
| 138 | MX27_PAD_SD3_CMD__FEC_TXD0 0x0 | ||
| 139 | MX27_PAD_SD3_CLK__FEC_TXD1 0x0 | ||
| 140 | MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 | ||
| 141 | MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 | ||
| 142 | MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 | ||
| 143 | MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 | ||
| 144 | MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 | ||
| 145 | MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 | ||
| 146 | MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 | ||
| 147 | MX27_PAD_ATA_DATA7__FEC_MDC 0x0 | ||
| 148 | MX27_PAD_ATA_DATA8__FEC_CRS 0x0 | ||
| 149 | MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 | ||
| 150 | MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 | ||
| 151 | MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 | ||
| 152 | MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 | ||
| 153 | MX27_PAD_ATA_DATA13__FEC_COL 0x0 | ||
| 154 | MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 | ||
| 155 | MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 | ||
| 156 | >; | ||
| 157 | }; | ||
| 158 | |||
| 159 | pinctrl_nand: nandgrp { | ||
| 160 | fsl,pins = < | ||
| 161 | MX27_PAD_NFRB__NFRB 0x0 | ||
| 162 | MX27_PAD_NFCLE__NFCLE 0x0 | ||
| 163 | MX27_PAD_NFWP_B__NFWP_B 0x0 | ||
| 164 | MX27_PAD_NFCE_B__NFCE_B 0x0 | ||
| 165 | MX27_PAD_NFALE__NFALE 0x0 | ||
| 166 | MX27_PAD_NFRE_B__NFRE_B 0x0 | ||
| 167 | MX27_PAD_NFWE_B__NFWE_B 0x0 | ||
| 168 | >; | ||
| 169 | }; | ||
| 170 | |||
| 171 | pinctrl_uart1: uart1grp { | ||
| 172 | fsl,pins = < | ||
| 173 | MX27_PAD_UART1_TXD__UART1_TXD 0x0 | ||
| 174 | MX27_PAD_UART1_RXD__UART1_RXD 0x0 | ||
| 175 | MX27_PAD_UART1_CTS__UART1_CTS 0x0 | ||
| 176 | MX27_PAD_UART1_RTS__UART1_RTS 0x0 | ||
| 177 | >; | ||
| 178 | }; | ||
| 179 | |||
| 180 | pinctrl_usbotg: usbotggrp { | ||
| 181 | fsl,pins = < | ||
| 182 | MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 | ||
| 183 | MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 | ||
| 184 | MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 | ||
| 185 | MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 | ||
| 186 | MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 | ||
| 187 | MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 | ||
| 188 | MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 | ||
| 189 | MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 | ||
| 190 | MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 | ||
| 191 | MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 | ||
| 192 | MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 | ||
| 193 | MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 | ||
| 194 | >; | ||
| 195 | }; | ||
| 196 | }; | ||
| 197 | }; | ||
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts index 3c3964a99637..7c869fe3c30b 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts | |||
| @@ -15,6 +15,10 @@ | |||
| 15 | model = "Phytec pca100 rapid development kit"; | 15 | model = "Phytec pca100 rapid development kit"; |
| 16 | compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27"; | 16 | compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27"; |
| 17 | 17 | ||
| 18 | chosen { | ||
| 19 | stdout-path = &uart1; | ||
| 20 | }; | ||
| 21 | |||
| 18 | display: display { | 22 | display: display { |
| 19 | model = "Primeview-PD050VL1"; | 23 | model = "Primeview-PD050VL1"; |
| 20 | native-mode = <&timing0>; | 24 | native-mode = <&timing0>; |
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index df3b2e731835..fe02bc7a24fd 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | |||
| @@ -12,14 +12,79 @@ | |||
| 12 | / { | 12 | / { |
| 13 | model = "Phytec pcm970"; | 13 | model = "Phytec pcm970"; |
| 14 | compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27"; | 14 | compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27"; |
| 15 | |||
| 16 | chosen { | ||
| 17 | stdout-path = &uart1; | ||
| 18 | }; | ||
| 19 | |||
| 20 | display0: LQ035Q7 { | ||
| 21 | model = "Sharp-LQ035Q7"; | ||
| 22 | native-mode = <&timing0>; | ||
| 23 | bits-per-pixel = <16>; | ||
| 24 | fsl,pcr = <0xf00080c0>; | ||
| 25 | |||
| 26 | display-timings { | ||
| 27 | timing0: 240x320 { | ||
| 28 | clock-frequency = <5500000>; | ||
| 29 | hactive = <240>; | ||
| 30 | vactive = <320>; | ||
| 31 | hback-porch = <5>; | ||
| 32 | hsync-len = <7>; | ||
| 33 | hfront-porch = <16>; | ||
| 34 | vback-porch = <7>; | ||
| 35 | vsync-len = <1>; | ||
| 36 | vfront-porch = <9>; | ||
| 37 | pixelclk-active = <1>; | ||
| 38 | hsync-active = <1>; | ||
| 39 | vsync-active = <1>; | ||
| 40 | de-active = <0>; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | }; | ||
| 44 | |||
| 45 | regulators { | ||
| 46 | regulator@2 { | ||
| 47 | compatible = "regulator-fixed"; | ||
| 48 | pinctrl-names = "default"; | ||
| 49 | pinctrl-0 = <&pinctrl_csien>; | ||
| 50 | reg = <2>; | ||
| 51 | regulator-name = "CSI_EN"; | ||
| 52 | regulator-min-microvolt = <3300000>; | ||
| 53 | regulator-max-microvolt = <3300000>; | ||
| 54 | gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; | ||
| 55 | regulator-always-on; | ||
| 56 | }; | ||
| 57 | }; | ||
| 58 | |||
| 59 | usbphy { | ||
| 60 | usbphy2: usbphy@2 { | ||
| 61 | compatible = "usb-nop-xceiv"; | ||
| 62 | reg = <2>; | ||
| 63 | vcc-supply = <®_5v0>; | ||
| 64 | clocks = <&clks 0>; | ||
| 65 | clock-names = "main_clk"; | ||
| 66 | }; | ||
| 67 | }; | ||
| 15 | }; | 68 | }; |
| 16 | 69 | ||
| 17 | &cspi1 { | 70 | &cspi1 { |
| 71 | pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>; | ||
| 18 | fsl,spi-num-chipselects = <2>; | 72 | fsl,spi-num-chipselects = <2>; |
| 19 | cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, | 73 | cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, |
| 20 | <&gpio4 27 GPIO_ACTIVE_LOW>; | 74 | <&gpio4 27 GPIO_ACTIVE_LOW>; |
| 21 | }; | 75 | }; |
| 22 | 76 | ||
| 77 | &fb { | ||
| 78 | pinctrl-names = "default"; | ||
| 79 | pinctrl-0 = <&pinctrl_imxfb1>; | ||
| 80 | display = <&display0>; | ||
| 81 | lcd-supply = <®_5v0>; | ||
| 82 | fsl,dmacr = <0x00020010>; | ||
| 83 | fsl,lscr1 = <0x00120300>; | ||
| 84 | fsl,lpccr = <0x00a903ff>; | ||
| 85 | status = "okay"; | ||
| 86 | }; | ||
| 87 | |||
| 23 | &i2c1 { | 88 | &i2c1 { |
| 24 | clock-frequency = <400000>; | 89 | clock-frequency = <400000>; |
| 25 | pinctrl-names = "default"; | 90 | pinctrl-names = "default"; |
| @@ -36,6 +101,50 @@ | |||
| 36 | 101 | ||
| 37 | &iomuxc { | 102 | &iomuxc { |
| 38 | imx27_phycore_rdk { | 103 | imx27_phycore_rdk { |
| 104 | pinctrl_csien: csiengrp { | ||
| 105 | fsl,pins = < | ||
| 106 | MX27_PAD_USB_OC_B__GPIO2_24 0x0 | ||
| 107 | >; | ||
| 108 | }; | ||
| 109 | |||
| 110 | pinctrl_cspi1cs1: cspi1cs1grp { | ||
| 111 | fsl,pins = < | ||
| 112 | MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 | ||
| 113 | >; | ||
| 114 | }; | ||
| 115 | |||
| 116 | pinctrl_imxfb1: imxfbgrp { | ||
| 117 | fsl,pins = < | ||
| 118 | MX27_PAD_LD0__LD0 0x0 | ||
| 119 | MX27_PAD_LD1__LD1 0x0 | ||
| 120 | MX27_PAD_LD2__LD2 0x0 | ||
| 121 | MX27_PAD_LD3__LD3 0x0 | ||
| 122 | MX27_PAD_LD4__LD4 0x0 | ||
| 123 | MX27_PAD_LD5__LD5 0x0 | ||
| 124 | MX27_PAD_LD6__LD6 0x0 | ||
| 125 | MX27_PAD_LD7__LD7 0x0 | ||
| 126 | MX27_PAD_LD8__LD8 0x0 | ||
| 127 | MX27_PAD_LD9__LD9 0x0 | ||
| 128 | MX27_PAD_LD10__LD10 0x0 | ||
| 129 | MX27_PAD_LD11__LD11 0x0 | ||
| 130 | MX27_PAD_LD12__LD12 0x0 | ||
| 131 | MX27_PAD_LD13__LD13 0x0 | ||
| 132 | MX27_PAD_LD14__LD14 0x0 | ||
| 133 | MX27_PAD_LD15__LD15 0x0 | ||
| 134 | MX27_PAD_LD16__LD16 0x0 | ||
| 135 | MX27_PAD_LD17__LD17 0x0 | ||
| 136 | MX27_PAD_CLS__CLS 0x0 | ||
| 137 | MX27_PAD_CONTRAST__CONTRAST 0x0 | ||
| 138 | MX27_PAD_LSCLK__LSCLK 0x0 | ||
| 139 | MX27_PAD_OE_ACD__OE_ACD 0x0 | ||
| 140 | MX27_PAD_PS__PS 0x0 | ||
| 141 | MX27_PAD_REV__REV 0x0 | ||
| 142 | MX27_PAD_SPL_SPR__SPL_SPR 0x0 | ||
| 143 | MX27_PAD_HSYNC__HSYNC 0x0 | ||
| 144 | MX27_PAD_VSYNC__VSYNC 0x0 | ||
| 145 | >; | ||
| 146 | }; | ||
| 147 | |||
| 39 | pinctrl_i2c1: i2c1grp { | 148 | pinctrl_i2c1: i2c1grp { |
| 40 | /* Add pullup to DATA line */ | 149 | /* Add pullup to DATA line */ |
| 41 | fsl,pins = < | 150 | fsl,pins = < |
| @@ -193,19 +302,16 @@ | |||
| 193 | dr_mode = "host"; | 302 | dr_mode = "host"; |
| 194 | phy_type = "ulpi"; | 303 | phy_type = "ulpi"; |
| 195 | vbus-supply = <®_5v0>; | 304 | vbus-supply = <®_5v0>; |
| 305 | fsl,usbphy = <&usbphy2>; | ||
| 196 | disable-over-current; | 306 | disable-over-current; |
| 197 | status = "okay"; | 307 | status = "okay"; |
| 198 | }; | 308 | }; |
| 199 | 309 | ||
| 200 | &usbphy2 { | ||
| 201 | vcc-supply = <®_5v0>; | ||
| 202 | }; | ||
| 203 | |||
| 204 | &weim { | 310 | &weim { |
| 205 | pinctrl-names = "default"; | 311 | pinctrl-names = "default"; |
| 206 | pinctrl-0 = <&pinctrl_weim>; | 312 | pinctrl-0 = <&pinctrl_weim>; |
| 207 | 313 | ||
| 208 | can@d4000000 { | 314 | can@4,0 { |
| 209 | compatible = "nxp,sja1000"; | 315 | compatible = "nxp,sja1000"; |
| 210 | reg = <4 0x00000000 0x00000100>; | 316 | reg = <4 0x00000000 0x00000100>; |
| 211 | interrupt-parent = <&gpio5>; | 317 | interrupt-parent = <&gpio5>; |
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index cefaa6994623..31e9f7049f73 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | |||
| @@ -41,6 +41,20 @@ | |||
| 41 | regulator-max-microvolt = <5000000>; | 41 | regulator-max-microvolt = <5000000>; |
| 42 | }; | 42 | }; |
| 43 | }; | 43 | }; |
| 44 | |||
| 45 | usbphy { | ||
| 46 | compatible = "simple-bus"; | ||
| 47 | #address-cells = <1>; | ||
| 48 | #size-cells = <0>; | ||
| 49 | |||
| 50 | usbphy0: usbphy@0 { | ||
| 51 | compatible = "usb-nop-xceiv"; | ||
| 52 | reg = <0>; | ||
| 53 | vcc-supply = <&sw3_reg>; | ||
| 54 | clocks = <&clks 0>; | ||
| 55 | clock-names = "main_clk"; | ||
| 56 | }; | ||
| 57 | }; | ||
| 44 | }; | 58 | }; |
| 45 | 59 | ||
| 46 | &audmux { | 60 | &audmux { |
| @@ -66,9 +80,9 @@ | |||
| 66 | status = "okay"; | 80 | status = "okay"; |
| 67 | 81 | ||
| 68 | pmic: mc13783@0 { | 82 | pmic: mc13783@0 { |
| 69 | #address-cells = <1>; | ||
| 70 | #size-cells = <0>; | ||
| 71 | compatible = "fsl,mc13783"; | 83 | compatible = "fsl,mc13783"; |
| 84 | pinctrl-names = "default"; | ||
| 85 | pinctrl-0 = <&pinctrl_pmic>; | ||
| 72 | reg = <0>; | 86 | reg = <0>; |
| 73 | spi-cs-high; | 87 | spi-cs-high; |
| 74 | spi-max-frequency = <20000000>; | 88 | spi-max-frequency = <20000000>; |
| @@ -166,7 +180,7 @@ | |||
| 166 | 180 | ||
| 167 | &fec { | 181 | &fec { |
| 168 | phy-mode = "mii"; | 182 | phy-mode = "mii"; |
| 169 | phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>; | 183 | phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; |
| 170 | phy-supply = <®_3v3>; | 184 | phy-supply = <®_3v3>; |
| 171 | pinctrl-names = "default"; | 185 | pinctrl-names = "default"; |
| 172 | pinctrl-0 = <&pinctrl_fec1>; | 186 | pinctrl-0 = <&pinctrl_fec1>; |
| @@ -204,7 +218,6 @@ | |||
| 204 | MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 | 218 | MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 |
| 205 | MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 | 219 | MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 |
| 206 | MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ | 220 | MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ |
| 207 | MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ | ||
| 208 | >; | 221 | >; |
| 209 | }; | 222 | }; |
| 210 | 223 | ||
| @@ -251,6 +264,21 @@ | |||
| 251 | >; | 264 | >; |
| 252 | }; | 265 | }; |
| 253 | 266 | ||
| 267 | pinctrl_pmic: pmicgrp { | ||
| 268 | fsl,pins = < | ||
| 269 | MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ | ||
| 270 | >; | ||
| 271 | }; | ||
| 272 | |||
| 273 | pinctrl_ssi1: ssi1grp { | ||
| 274 | fsl,pins = < | ||
| 275 | MX27_PAD_SSI1_FS__SSI1_FS 0x0 | ||
| 276 | MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0 | ||
| 277 | MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0 | ||
| 278 | MX27_PAD_SSI1_CLK__SSI1_CLK 0x0 | ||
| 279 | >; | ||
| 280 | }; | ||
| 281 | |||
| 254 | pinctrl_usbotg: usbotggrp { | 282 | pinctrl_usbotg: usbotggrp { |
| 255 | fsl,pins = < | 283 | fsl,pins = < |
| 256 | MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 | 284 | MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 |
| @@ -279,23 +307,28 @@ | |||
| 279 | status = "okay"; | 307 | status = "okay"; |
| 280 | }; | 308 | }; |
| 281 | 309 | ||
| 310 | &ssi1 { | ||
| 311 | pinctrl-names = "default"; | ||
| 312 | pinctrl-0 = <&pinctrl_ssi1>; | ||
| 313 | fsl,mode = "i2s-slave"; | ||
| 314 | status = "okay"; | ||
| 315 | }; | ||
| 316 | |||
| 282 | &usbotg { | 317 | &usbotg { |
| 283 | pinctrl-names = "default"; | 318 | pinctrl-names = "default"; |
| 284 | pinctrl-0 = <&pinctrl_usbotg>; | 319 | pinctrl-0 = <&pinctrl_usbotg>; |
| 285 | dr_mode = "otg"; | 320 | dr_mode = "otg"; |
| 286 | phy_type = "ulpi"; | 321 | phy_type = "ulpi"; |
| 322 | fsl,usbphy = <&usbphy0>; | ||
| 287 | vbus-supply = <&sw3_reg>; | 323 | vbus-supply = <&sw3_reg>; |
| 324 | disable-over-current; | ||
| 288 | status = "okay"; | 325 | status = "okay"; |
| 289 | }; | 326 | }; |
| 290 | 327 | ||
| 291 | &usbphy0 { | ||
| 292 | vcc-supply = <&sw3_reg>; | ||
| 293 | }; | ||
| 294 | |||
| 295 | &weim { | 328 | &weim { |
| 296 | status = "okay"; | 329 | status = "okay"; |
| 297 | 330 | ||
| 298 | nor: nor@c0000000 { | 331 | nor: nor@0,0 { |
| 299 | compatible = "cfi-flash"; | 332 | compatible = "cfi-flash"; |
| 300 | reg = <0 0x00000000 0x02000000>; | 333 | reg = <0 0x00000000 0x02000000>; |
| 301 | bank-width = <2>; | 334 | bank-width = <2>; |
| @@ -305,7 +338,7 @@ | |||
| 305 | #size-cells = <1>; | 338 | #size-cells = <1>; |
| 306 | }; | 339 | }; |
| 307 | 340 | ||
| 308 | sram: sram@c8000000 { | 341 | sram: sram@1,0 { |
| 309 | compatible = "mtd-ram"; | 342 | compatible = "mtd-ram"; |
| 310 | reg = <1 0x00000000 0x00800000>; | 343 | reg = <1 0x00000000 0x00800000>; |
| 311 | bank-width = <2>; | 344 | bank-width = <2>; |
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 137e010eab35..a75555c39533 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi | |||
| @@ -11,11 +11,13 @@ | |||
| 11 | 11 | ||
| 12 | #include "skeleton.dtsi" | 12 | #include "skeleton.dtsi" |
| 13 | #include "imx27-pinfunc.h" | 13 | #include "imx27-pinfunc.h" |
| 14 | #include <dt-bindings/input/input.h> | ||
| 14 | #include <dt-bindings/interrupt-controller/irq.h> | 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | #include <dt-bindings/gpio/gpio.h> | 16 | #include <dt-bindings/gpio/gpio.h> |
| 16 | 17 | ||
| 17 | / { | 18 | / { |
| 18 | aliases { | 19 | aliases { |
| 20 | ethernet0 = &fec; | ||
| 19 | gpio0 = &gpio1; | 21 | gpio0 = &gpio1; |
| 20 | gpio1 = &gpio2; | 22 | gpio1 = &gpio2; |
| 21 | gpio2 = &gpio3; | 23 | gpio2 = &gpio3; |
| @@ -71,26 +73,6 @@ | |||
| 71 | }; | 73 | }; |
| 72 | }; | 74 | }; |
| 73 | 75 | ||
| 74 | usbphy { | ||
| 75 | compatible = "simple-bus"; | ||
| 76 | #address-cells = <1>; | ||
| 77 | #size-cells = <0>; | ||
| 78 | |||
| 79 | usbphy0: usbphy@0 { | ||
| 80 | compatible = "usb-nop-xceiv"; | ||
| 81 | reg = <0>; | ||
| 82 | clocks = <&clks 75>; | ||
| 83 | clock-names = "main_clk"; | ||
| 84 | }; | ||
| 85 | |||
| 86 | usbphy2: usbphy@2 { | ||
| 87 | compatible = "usb-nop-xceiv"; | ||
| 88 | reg = <2>; | ||
| 89 | clocks = <&clks 75>; | ||
| 90 | clock-names = "main_clk"; | ||
| 91 | }; | ||
| 92 | }; | ||
| 93 | |||
| 94 | soc { | 76 | soc { |
| 95 | #address-cells = <1>; | 77 | #address-cells = <1>; |
| 96 | #size-cells = <1>; | 78 | #size-cells = <1>; |
| @@ -464,9 +446,8 @@ | |||
| 464 | compatible = "fsl,imx27-usb"; | 446 | compatible = "fsl,imx27-usb"; |
| 465 | reg = <0x10024000 0x200>; | 447 | reg = <0x10024000 0x200>; |
| 466 | interrupts = <56>; | 448 | interrupts = <56>; |
| 467 | clocks = <&clks 15>; | 449 | clocks = <&clks 75>; |
| 468 | fsl,usbmisc = <&usbmisc 0>; | 450 | fsl,usbmisc = <&usbmisc 0>; |
| 469 | fsl,usbphy = <&usbphy0>; | ||
| 470 | status = "disabled"; | 451 | status = "disabled"; |
| 471 | }; | 452 | }; |
| 472 | 453 | ||
| @@ -474,7 +455,7 @@ | |||
| 474 | compatible = "fsl,imx27-usb"; | 455 | compatible = "fsl,imx27-usb"; |
| 475 | reg = <0x10024200 0x200>; | 456 | reg = <0x10024200 0x200>; |
| 476 | interrupts = <54>; | 457 | interrupts = <54>; |
| 477 | clocks = <&clks 15>; | 458 | clocks = <&clks 75>; |
| 478 | fsl,usbmisc = <&usbmisc 1>; | 459 | fsl,usbmisc = <&usbmisc 1>; |
| 479 | status = "disabled"; | 460 | status = "disabled"; |
| 480 | }; | 461 | }; |
| @@ -483,9 +464,8 @@ | |||
| 483 | compatible = "fsl,imx27-usb"; | 464 | compatible = "fsl,imx27-usb"; |
| 484 | reg = <0x10024400 0x200>; | 465 | reg = <0x10024400 0x200>; |
| 485 | interrupts = <55>; | 466 | interrupts = <55>; |
| 486 | clocks = <&clks 15>; | 467 | clocks = <&clks 75>; |
| 487 | fsl,usbmisc = <&usbmisc 2>; | 468 | fsl,usbmisc = <&usbmisc 2>; |
| 488 | fsl,usbphy = <&usbphy2>; | ||
| 489 | status = "disabled"; | 469 | status = "disabled"; |
| 490 | }; | 470 | }; |
| 491 | 471 | ||
diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts index 5f326c1c1850..ce1a7effba37 100644 --- a/arch/arm/boot/dts/imx28-duckbill.dts +++ b/arch/arm/boot/dts/imx28-duckbill.dts | |||
| @@ -25,9 +25,9 @@ | |||
| 25 | ssp0: ssp@80010000 { | 25 | ssp0: ssp@80010000 { |
| 26 | compatible = "fsl,imx28-mmc"; | 26 | compatible = "fsl,imx28-mmc"; |
| 27 | pinctrl-names = "default"; | 27 | pinctrl-names = "default"; |
| 28 | pinctrl-0 = <&mmc0_8bit_pins_a | 28 | pinctrl-0 = <&mmc0_4bit_pins_a |
| 29 | &mmc0_cd_cfg &mmc0_sck_cfg>; | 29 | &mmc0_cd_cfg &mmc0_sck_cfg>; |
| 30 | bus-width = <8>; | 30 | bus-width = <4>; |
| 31 | vmmc-supply = <®_3p3v>; | 31 | vmmc-supply = <®_3p3v>; |
| 32 | status = "okay"; | 32 | status = "okay"; |
| 33 | }; | 33 | }; |
| @@ -39,7 +39,7 @@ | |||
| 39 | hog_pins_a: hog@0 { | 39 | hog_pins_a: hog@0 { |
| 40 | reg = <0>; | 40 | reg = <0>; |
| 41 | fsl,pinmux-ids = < | 41 | fsl,pinmux-ids = < |
| 42 | MX28_PAD_ENET0_RX_CLK__GPIO_4_13 /* PHY Reset */ | 42 | MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */ |
| 43 | >; | 43 | >; |
| 44 | fsl,drive-strength = <MXS_DRIVE_4mA>; | 44 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
| 45 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | 45 | fsl,voltage = <MXS_VOLTAGE_HIGH>; |
| @@ -82,7 +82,7 @@ | |||
| 82 | pinctrl-names = "default"; | 82 | pinctrl-names = "default"; |
| 83 | pinctrl-0 = <&mac0_pins_a>; | 83 | pinctrl-0 = <&mac0_pins_a>; |
| 84 | phy-supply = <®_3p3v>; | 84 | phy-supply = <®_3p3v>; |
| 85 | phy-reset-gpios = <&gpio4 13 0>; | 85 | phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; |
| 86 | phy-reset-duration = <100>; | 86 | phy-reset-duration = <100>; |
| 87 | status = "okay"; | 87 | status = "okay"; |
| 88 | }; | 88 | }; |
| @@ -110,12 +110,12 @@ | |||
| 110 | 110 | ||
| 111 | status { | 111 | status { |
| 112 | label = "duckbill:green:status"; | 112 | label = "duckbill:green:status"; |
| 113 | gpios = <&gpio3 5 0>; | 113 | gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; |
| 114 | }; | 114 | }; |
| 115 | 115 | ||
| 116 | failure { | 116 | failure { |
| 117 | label = "duckbill:red:status"; | 117 | label = "duckbill:red:status"; |
| 118 | gpios = <&gpio3 4 0>; | 118 | gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; |
| 119 | }; | 119 | }; |
| 120 | }; | 120 | }; |
| 121 | }; | 121 | }; |
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 90a579532b8b..a95cc5358ff4 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi | |||
| @@ -9,6 +9,7 @@ | |||
| 9 | * http://www.gnu.org/copyleft/gpl.html | 9 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include <dt-bindings/gpio/gpio.h> | ||
| 12 | #include "skeleton.dtsi" | 13 | #include "skeleton.dtsi" |
| 13 | #include "imx28-pinfunc.h" | 14 | #include "imx28-pinfunc.h" |
| 14 | 15 | ||
diff --git a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi index 906ae937b013..9c2b715ab8bf 100644 --- a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi +++ b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi | |||
| @@ -37,6 +37,17 @@ | |||
| 37 | compatible = "nxp,pcf8563"; | 37 | compatible = "nxp,pcf8563"; |
| 38 | reg = <0x51>; | 38 | reg = <0x51>; |
| 39 | }; | 39 | }; |
| 40 | |||
| 41 | tsc2007: tsc2007@48 { | ||
| 42 | compatible = "ti,tsc2007"; | ||
| 43 | gpios = <&gpio3 2 0>; | ||
| 44 | interrupt-parent = <&gpio3>; | ||
| 45 | interrupts = <0x2 0x8>; | ||
| 46 | pinctrl-names = "default"; | ||
| 47 | pinctrl-0 = <&pinctrl_tsc2007_1>; | ||
| 48 | reg = <0x48>; | ||
| 49 | ti,x-plate-ohms = <180>; | ||
| 50 | }; | ||
| 40 | }; | 51 | }; |
| 41 | 52 | ||
| 42 | &iomuxc { | 53 | &iomuxc { |
| @@ -70,6 +81,10 @@ | |||
| 70 | MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 | 81 | MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 |
| 71 | >; | 82 | >; |
| 72 | }; | 83 | }; |
| 84 | |||
| 85 | pinctrl_tsc2007_1: tsc2007grp-1 { | ||
| 86 | fsl,pins = <MX35_PAD_ATA_DA2__GPIO3_2 0x80000000>; | ||
| 87 | }; | ||
| 73 | }; | 88 | }; |
| 74 | }; | 89 | }; |
| 75 | 90 | ||
diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts index 1bdec21f4533..f04ae91eea89 100644 --- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts +++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts | |||
| @@ -46,6 +46,14 @@ | |||
| 46 | linux,default-trigger = "heartbeat"; | 46 | linux,default-trigger = "heartbeat"; |
| 47 | }; | 47 | }; |
| 48 | }; | 48 | }; |
| 49 | |||
| 50 | sound { | ||
| 51 | compatible = "eukrea,asoc-tlv320"; | ||
| 52 | eukrea,model = "imx35-eukrea-tlv320aic23"; | ||
| 53 | ssi-controller = <&ssi1>; | ||
| 54 | fsl,mux-int-port = <1>; | ||
| 55 | fsl,mux-ext-port = <4>; | ||
| 56 | }; | ||
| 49 | }; | 57 | }; |
| 50 | 58 | ||
| 51 | &audmux { | 59 | &audmux { |
| @@ -124,6 +132,7 @@ | |||
| 124 | }; | 132 | }; |
| 125 | 133 | ||
| 126 | &ssi1 { | 134 | &ssi1 { |
| 135 | codec-handle = <&tlv320aic23>; | ||
| 127 | fsl,mode = "i2s-slave"; | 136 | fsl,mode = "i2s-slave"; |
| 128 | status = "okay"; | 137 | status = "okay"; |
| 129 | }; | 138 | }; |
| @@ -141,3 +150,16 @@ | |||
| 141 | fsl,uart-has-rtscts; | 150 | fsl,uart-has-rtscts; |
| 142 | status = "okay"; | 151 | status = "okay"; |
| 143 | }; | 152 | }; |
| 153 | |||
| 154 | &usbhost1 { | ||
| 155 | phy_type = "serial"; | ||
| 156 | dr_mode = "host"; | ||
| 157 | status = "okay"; | ||
| 158 | }; | ||
| 159 | |||
| 160 | &usbotg { | ||
| 161 | phy_type = "utmi"; | ||
| 162 | dr_mode = "otg"; | ||
| 163 | external-vbus-divider; | ||
| 164 | status = "okay"; | ||
| 165 | }; | ||
diff --git a/arch/arm/boot/dts/imx35-pdk.dts b/arch/arm/boot/dts/imx35-pdk.dts new file mode 100644 index 000000000000..8d715523708f --- /dev/null +++ b/arch/arm/boot/dts/imx35-pdk.dts | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> | ||
| 3 | * Copyright 2014 Freescale Semiconductor, Inc. | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | /dts-v1/; | ||
| 14 | #include "imx35.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Freescale i.MX35 Product Development Kit"; | ||
| 18 | compatible = "fsl,imx35-pdk", "fsl,imx35"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | reg = <0x80000000 0x8000000>, | ||
| 22 | <0x90000000 0x8000000>; | ||
| 23 | }; | ||
| 24 | }; | ||
| 25 | |||
| 26 | &esdhc1 { | ||
| 27 | pinctrl-names = "default"; | ||
| 28 | pinctrl-0 = <&pinctrl_esdhc1>; | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
| 31 | |||
| 32 | &iomuxc { | ||
| 33 | imx35-pdk { | ||
| 34 | pinctrl_esdhc1: esdhc1grp { | ||
| 35 | fsl,pins = < | ||
| 36 | MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 | ||
| 37 | MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 | ||
| 38 | MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 | ||
| 39 | MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 | ||
| 40 | MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 | ||
| 41 | MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 | ||
| 42 | >; | ||
| 43 | }; | ||
| 44 | |||
| 45 | pinctrl_uart1: uart1grp { | ||
| 46 | fsl,pins = < | ||
| 47 | MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 | ||
| 48 | MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 | ||
| 49 | MX35_PAD_CTS1__UART1_CTS 0x1c5 | ||
| 50 | MX35_PAD_RTS1__UART1_RTS 0x1c5 | ||
| 51 | >; | ||
| 52 | }; | ||
| 53 | }; | ||
| 54 | }; | ||
| 55 | |||
| 56 | &nfc { | ||
| 57 | nand-bus-width = <16>; | ||
| 58 | nand-ecc-mode = "hw"; | ||
| 59 | nand-on-flash-bbt; | ||
| 60 | status = "okay"; | ||
| 61 | }; | ||
| 62 | |||
| 63 | &uart1 { | ||
| 64 | pinctrl-names = "default"; | ||
| 65 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 66 | fsl,uart-has-rtscts; | ||
| 67 | status = "okay"; | ||
| 68 | }; | ||
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 88b218f8f810..4759abb49436 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | 13 | ||
| 14 | / { | 14 | / { |
| 15 | aliases { | 15 | aliases { |
| 16 | ethernet0 = &fec; | ||
| 16 | gpio0 = &gpio1; | 17 | gpio0 = &gpio1; |
| 17 | gpio1 = &gpio2; | 18 | gpio1 = &gpio2; |
| 18 | gpio2 = &gpio3; | 19 | gpio2 = &gpio3; |
| @@ -295,9 +296,9 @@ | |||
| 295 | compatible = "fsl,imx35-usb", "fsl,imx27-usb"; | 296 | compatible = "fsl,imx35-usb", "fsl,imx27-usb"; |
| 296 | reg = <0x53ff4000 0x0200>; | 297 | reg = <0x53ff4000 0x0200>; |
| 297 | interrupts = <37>; | 298 | interrupts = <37>; |
| 298 | clocks = <&clks 9>, <&clks 73>, <&clks 28>; | 299 | clocks = <&clks 73>; |
| 299 | clock-names = "ipg", "ahb", "per"; | ||
| 300 | fsl,usbmisc = <&usbmisc 0>; | 300 | fsl,usbmisc = <&usbmisc 0>; |
| 301 | fsl,usbphy = <&usbphy0>; | ||
| 301 | status = "disabled"; | 302 | status = "disabled"; |
| 302 | }; | 303 | }; |
| 303 | 304 | ||
| @@ -305,9 +306,9 @@ | |||
| 305 | compatible = "fsl,imx35-usb", "fsl,imx27-usb"; | 306 | compatible = "fsl,imx35-usb", "fsl,imx27-usb"; |
| 306 | reg = <0x53ff4400 0x0200>; | 307 | reg = <0x53ff4400 0x0200>; |
| 307 | interrupts = <35>; | 308 | interrupts = <35>; |
| 308 | clocks = <&clks 9>, <&clks 73>, <&clks 28>; | 309 | clocks = <&clks 73>; |
| 309 | clock-names = "ipg", "ahb", "per"; | ||
| 310 | fsl,usbmisc = <&usbmisc 1>; | 310 | fsl,usbmisc = <&usbmisc 1>; |
| 311 | fsl,usbphy = <&usbphy1>; | ||
| 311 | status = "disabled"; | 312 | status = "disabled"; |
| 312 | }; | 313 | }; |
| 313 | 314 | ||
| @@ -356,4 +357,20 @@ | |||
| 356 | }; | 357 | }; |
| 357 | }; | 358 | }; |
| 358 | }; | 359 | }; |
| 360 | |||
| 361 | usbphy { | ||
| 362 | compatible = "simple-bus"; | ||
| 363 | #address-cells = <1>; | ||
| 364 | #size-cells = <0>; | ||
| 365 | |||
| 366 | usbphy0: usb-phy@0 { | ||
| 367 | reg = <0>; | ||
| 368 | compatible = "usb-nop-xceiv"; | ||
| 369 | }; | ||
| 370 | |||
| 371 | usbphy1: usb-phy@1 { | ||
| 372 | reg = <1>; | ||
| 373 | compatible = "usb-nop-xceiv"; | ||
| 374 | }; | ||
| 375 | }; | ||
| 359 | }; | 376 | }; |
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 9c89d1ca97c2..6a201cf54366 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | 17 | ||
| 18 | / { | 18 | / { |
| 19 | aliases { | 19 | aliases { |
| 20 | ethernet0 = &fec; | ||
| 20 | gpio0 = &gpio1; | 21 | gpio0 = &gpio1; |
| 21 | gpio1 = &gpio2; | 22 | gpio1 = &gpio2; |
| 22 | gpio2 = &gpio3; | 23 | gpio2 = &gpio3; |
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 9e9deb244b76..6bc3243a80d3 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts | |||
| @@ -17,10 +17,28 @@ | |||
| 17 | model = "Freescale i.MX51 Babbage Board"; | 17 | model = "Freescale i.MX51 Babbage Board"; |
| 18 | compatible = "fsl,imx51-babbage", "fsl,imx51"; | 18 | compatible = "fsl,imx51-babbage", "fsl,imx51"; |
| 19 | 19 | ||
| 20 | chosen { | ||
| 21 | stdout-path = &uart1; | ||
| 22 | }; | ||
| 23 | |||
| 20 | memory { | 24 | memory { |
| 21 | reg = <0x90000000 0x20000000>; | 25 | reg = <0x90000000 0x20000000>; |
| 22 | }; | 26 | }; |
| 23 | 27 | ||
| 28 | clocks { | ||
| 29 | ckih1 { | ||
| 30 | clock-frequency = <22579200>; | ||
| 31 | }; | ||
| 32 | |||
| 33 | clk_26M: codec_clock { | ||
| 34 | compatible = "fixed-clock"; | ||
| 35 | reg=<0>; | ||
| 36 | #clock-cells = <0>; | ||
| 37 | clock-frequency = <26000000>; | ||
| 38 | gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | |||
| 24 | display0: display@di0 { | 42 | display0: display@di0 { |
| 25 | compatible = "fsl,imx-parallel-display"; | 43 | compatible = "fsl,imx-parallel-display"; |
| 26 | interface-pix-fmt = "rgb24"; | 44 | interface-pix-fmt = "rgb24"; |
| @@ -82,11 +100,13 @@ | |||
| 82 | 100 | ||
| 83 | gpio-keys { | 101 | gpio-keys { |
| 84 | compatible = "gpio-keys"; | 102 | compatible = "gpio-keys"; |
| 103 | pinctrl-names = "default"; | ||
| 104 | pinctrl-0 = <&pinctrl_gpio_keys>; | ||
| 85 | 105 | ||
| 86 | power { | 106 | power { |
| 87 | label = "Power Button"; | 107 | label = "Power Button"; |
| 88 | gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; | 108 | gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; |
| 89 | linux,code = <116>; /* KEY_POWER */ | 109 | linux,code = <KEY_POWER>; |
| 90 | gpio-key,wakeup; | 110 | gpio-key,wakeup; |
| 91 | }; | 111 | }; |
| 92 | }; | 112 | }; |
| @@ -102,6 +122,36 @@ | |||
| 102 | }; | 122 | }; |
| 103 | }; | 123 | }; |
| 104 | 124 | ||
| 125 | regulators { | ||
| 126 | compatible = "simple-bus"; | ||
| 127 | #address-cells = <1>; | ||
| 128 | #size-cells = <0>; | ||
| 129 | |||
| 130 | reg_usbh1_vbus: regulator@0 { | ||
| 131 | compatible = "regulator-fixed"; | ||
| 132 | pinctrl-names = "default"; | ||
| 133 | pinctrl-0 = <&pinctrl_usbh1reg>; | ||
| 134 | reg = <0>; | ||
| 135 | regulator-name = "usbh1_vbus"; | ||
| 136 | regulator-min-microvolt = <5000000>; | ||
| 137 | regulator-max-microvolt = <5000000>; | ||
| 138 | gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; | ||
| 139 | enable-active-high; | ||
| 140 | }; | ||
| 141 | |||
| 142 | reg_usbotg_vbus: regulator@1 { | ||
| 143 | compatible = "regulator-fixed"; | ||
| 144 | pinctrl-names = "default"; | ||
| 145 | pinctrl-0 = <&pinctrl_usbotgreg>; | ||
| 146 | reg = <1>; | ||
| 147 | regulator-name = "usbotg_vbus"; | ||
| 148 | regulator-min-microvolt = <5000000>; | ||
| 149 | regulator-max-microvolt = <5000000>; | ||
| 150 | gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; | ||
| 151 | enable-active-high; | ||
| 152 | }; | ||
| 153 | }; | ||
| 154 | |||
| 105 | sound { | 155 | sound { |
| 106 | compatible = "fsl,imx51-babbage-sgtl5000", | 156 | compatible = "fsl,imx51-babbage-sgtl5000", |
| 107 | "fsl,imx-audio-sgtl5000"; | 157 | "fsl,imx-audio-sgtl5000"; |
| @@ -116,41 +166,23 @@ | |||
| 116 | mux-ext-port = <3>; | 166 | mux-ext-port = <3>; |
| 117 | }; | 167 | }; |
| 118 | 168 | ||
| 119 | clocks { | 169 | usbphy { |
| 120 | ckih1 { | 170 | #address-cells = <1>; |
| 121 | clock-frequency = <22579200>; | 171 | #size-cells = <0>; |
| 122 | }; | 172 | compatible = "simple-bus"; |
| 123 | 173 | ||
| 124 | clk_26M: codec_clock { | 174 | usbh1phy: usbh1phy@0 { |
| 125 | compatible = "fixed-clock"; | 175 | compatible = "usb-nop-xceiv"; |
| 126 | reg=<0>; | 176 | reg = <0>; |
| 127 | #clock-cells = <0>; | 177 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 128 | clock-frequency = <26000000>; | 178 | clock-names = "main_clk"; |
| 129 | gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; | ||
| 130 | }; | 179 | }; |
| 131 | }; | 180 | }; |
| 132 | }; | 181 | }; |
| 133 | 182 | ||
| 134 | &esdhc1 { | 183 | &audmux { |
| 135 | pinctrl-names = "default"; | ||
| 136 | pinctrl-0 = <&pinctrl_esdhc1>; | ||
| 137 | fsl,cd-controller; | ||
| 138 | fsl,wp-controller; | ||
| 139 | status = "okay"; | ||
| 140 | }; | ||
| 141 | |||
| 142 | &esdhc2 { | ||
| 143 | pinctrl-names = "default"; | ||
| 144 | pinctrl-0 = <&pinctrl_esdhc2>; | ||
| 145 | cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; | ||
| 146 | wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; | ||
| 147 | status = "okay"; | ||
| 148 | }; | ||
| 149 | |||
| 150 | &uart3 { | ||
| 151 | pinctrl-names = "default"; | 184 | pinctrl-names = "default"; |
| 152 | pinctrl-0 = <&pinctrl_uart3>; | 185 | pinctrl-0 = <&pinctrl_audmux>; |
| 153 | fsl,uart-has-rtscts; | ||
| 154 | status = "okay"; | 186 | status = "okay"; |
| 155 | }; | 187 | }; |
| 156 | 188 | ||
| @@ -163,9 +195,9 @@ | |||
| 163 | status = "okay"; | 195 | status = "okay"; |
| 164 | 196 | ||
| 165 | pmic: mc13892@0 { | 197 | pmic: mc13892@0 { |
| 166 | #address-cells = <1>; | ||
| 167 | #size-cells = <0>; | ||
| 168 | compatible = "fsl,mc13892"; | 198 | compatible = "fsl,mc13892"; |
| 199 | pinctrl-names = "default"; | ||
| 200 | pinctrl-0 = <&pinctrl_pmic>; | ||
| 169 | spi-max-frequency = <6000000>; | 201 | spi-max-frequency = <6000000>; |
| 170 | spi-cs-high; | 202 | spi-cs-high; |
| 171 | reg = <0>; | 203 | reg = <0>; |
| @@ -280,6 +312,53 @@ | |||
| 280 | }; | 312 | }; |
| 281 | }; | 313 | }; |
| 282 | 314 | ||
| 315 | &esdhc1 { | ||
| 316 | pinctrl-names = "default"; | ||
| 317 | pinctrl-0 = <&pinctrl_esdhc1>; | ||
| 318 | fsl,cd-controller; | ||
| 319 | fsl,wp-controller; | ||
| 320 | status = "okay"; | ||
| 321 | }; | ||
| 322 | |||
| 323 | &esdhc2 { | ||
| 324 | pinctrl-names = "default"; | ||
| 325 | pinctrl-0 = <&pinctrl_esdhc2>; | ||
| 326 | cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; | ||
| 327 | wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; | ||
| 328 | status = "okay"; | ||
| 329 | }; | ||
| 330 | |||
| 331 | &fec { | ||
| 332 | pinctrl-names = "default"; | ||
| 333 | pinctrl-0 = <&pinctrl_fec>; | ||
| 334 | phy-mode = "mii"; | ||
| 335 | phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; | ||
| 336 | phy-reset-duration = <1>; | ||
| 337 | status = "okay"; | ||
| 338 | }; | ||
| 339 | |||
| 340 | &i2c1 { | ||
| 341 | pinctrl-names = "default"; | ||
| 342 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 343 | status = "okay"; | ||
| 344 | }; | ||
| 345 | |||
| 346 | &i2c2 { | ||
| 347 | pinctrl-names = "default"; | ||
| 348 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 349 | status = "okay"; | ||
| 350 | |||
| 351 | sgtl5000: codec@0a { | ||
| 352 | compatible = "fsl,sgtl5000"; | ||
| 353 | pinctrl-names = "default"; | ||
| 354 | pinctrl-0 = <&pinctrl_clkcodec>; | ||
| 355 | reg = <0x0a>; | ||
| 356 | clocks = <&clk_26M>; | ||
| 357 | VDDA-supply = <&vdig_reg>; | ||
| 358 | VDDIO-supply = <&vvideo_reg>; | ||
| 359 | }; | ||
| 360 | }; | ||
| 361 | |||
| 283 | &ipu_di0_disp0 { | 362 | &ipu_di0_disp0 { |
| 284 | remote-endpoint = <&display0_in>; | 363 | remote-endpoint = <&display0_in>; |
| 285 | }; | 364 | }; |
| @@ -288,29 +367,74 @@ | |||
| 288 | remote-endpoint = <&display1_in>; | 367 | remote-endpoint = <&display1_in>; |
| 289 | }; | 368 | }; |
| 290 | 369 | ||
| 370 | &kpp { | ||
| 371 | pinctrl-names = "default"; | ||
| 372 | pinctrl-0 = <&pinctrl_kpp>; | ||
| 373 | linux,keymap = < | ||
| 374 | MATRIX_KEY(0, 0, KEY_UP) | ||
| 375 | MATRIX_KEY(0, 1, KEY_DOWN) | ||
| 376 | MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) | ||
| 377 | MATRIX_KEY(0, 3, KEY_HOME) | ||
| 378 | MATRIX_KEY(1, 0, KEY_RIGHT) | ||
| 379 | MATRIX_KEY(1, 1, KEY_LEFT) | ||
| 380 | MATRIX_KEY(1, 2, KEY_ENTER) | ||
| 381 | MATRIX_KEY(1, 3, KEY_VOLUMEUP) | ||
| 382 | MATRIX_KEY(2, 0, KEY_F6) | ||
| 383 | MATRIX_KEY(2, 1, KEY_F8) | ||
| 384 | MATRIX_KEY(2, 2, KEY_F9) | ||
| 385 | MATRIX_KEY(2, 3, KEY_F10) | ||
| 386 | MATRIX_KEY(3, 0, KEY_F1) | ||
| 387 | MATRIX_KEY(3, 1, KEY_F2) | ||
| 388 | MATRIX_KEY(3, 2, KEY_F3) | ||
| 389 | MATRIX_KEY(3, 3, KEY_POWER) | ||
| 390 | >; | ||
| 391 | status = "okay"; | ||
| 392 | }; | ||
| 393 | |||
| 291 | &ssi2 { | 394 | &ssi2 { |
| 292 | fsl,mode = "i2s-slave"; | 395 | fsl,mode = "i2s-slave"; |
| 293 | status = "okay"; | 396 | status = "okay"; |
| 294 | }; | 397 | }; |
| 295 | 398 | ||
| 296 | &iomuxc { | 399 | &uart1 { |
| 297 | pinctrl-names = "default"; | 400 | pinctrl-names = "default"; |
| 298 | pinctrl-0 = <&pinctrl_hog>; | 401 | pinctrl-0 = <&pinctrl_uart1>; |
| 402 | fsl,uart-has-rtscts; | ||
| 403 | status = "okay"; | ||
| 404 | }; | ||
| 299 | 405 | ||
| 300 | imx51-babbage { | 406 | &uart2 { |
| 301 | pinctrl_hog: hoggrp { | 407 | pinctrl-names = "default"; |
| 302 | fsl,pins = < | 408 | pinctrl-0 = <&pinctrl_uart2>; |
| 303 | MX51_PAD_GPIO1_0__SD1_CD 0x20d5 | 409 | status = "okay"; |
| 304 | MX51_PAD_GPIO1_1__SD1_WP 0x20d5 | 410 | }; |
| 305 | MX51_PAD_GPIO1_5__GPIO1_5 0x100 | 411 | |
| 306 | MX51_PAD_GPIO1_6__GPIO1_6 0x100 | 412 | &uart3 { |
| 307 | MX51_PAD_EIM_A27__GPIO2_21 0x5 | 413 | pinctrl-names = "default"; |
| 308 | MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 | 414 | pinctrl-0 = <&pinctrl_uart3>; |
| 309 | MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 | 415 | fsl,uart-has-rtscts; |
| 310 | MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 | 416 | status = "okay"; |
| 311 | >; | 417 | }; |
| 312 | }; | 418 | |
| 419 | &usbh1 { | ||
| 420 | pinctrl-names = "default"; | ||
| 421 | pinctrl-0 = <&pinctrl_usbh1>; | ||
| 422 | vbus-supply = <®_usbh1_vbus>; | ||
| 423 | fsl,usbphy = <&usbh1phy>; | ||
| 424 | phy_type = "ulpi"; | ||
| 425 | status = "okay"; | ||
| 426 | }; | ||
| 313 | 427 | ||
| 428 | &usbotg { | ||
| 429 | dr_mode = "otg"; | ||
| 430 | disable-over-current; | ||
| 431 | phy_type = "utmi_wide"; | ||
| 432 | vbus-supply = <®_usbotg_vbus>; | ||
| 433 | status = "okay"; | ||
| 434 | }; | ||
| 435 | |||
| 436 | &iomuxc { | ||
| 437 | imx51-babbage { | ||
| 314 | pinctrl_audmux: audmuxgrp { | 438 | pinctrl_audmux: audmuxgrp { |
| 315 | fsl,pins = < | 439 | fsl,pins = < |
| 316 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 | 440 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 |
| @@ -320,11 +444,19 @@ | |||
| 320 | >; | 444 | >; |
| 321 | }; | 445 | }; |
| 322 | 446 | ||
| 447 | pinctrl_clkcodec: clkcodecgrp { | ||
| 448 | fsl,pins = < | ||
| 449 | MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 | ||
| 450 | >; | ||
| 451 | }; | ||
| 452 | |||
| 323 | pinctrl_ecspi1: ecspi1grp { | 453 | pinctrl_ecspi1: ecspi1grp { |
| 324 | fsl,pins = < | 454 | fsl,pins = < |
| 325 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 | 455 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 |
| 326 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 | 456 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 |
| 327 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 | 457 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 |
| 458 | MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ | ||
| 459 | MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */ | ||
| 328 | >; | 460 | >; |
| 329 | }; | 461 | }; |
| 330 | 462 | ||
| @@ -336,6 +468,8 @@ | |||
| 336 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 | 468 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 |
| 337 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 | 469 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 |
| 338 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 | 470 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 |
| 471 | MX51_PAD_GPIO1_0__SD1_CD 0x20d5 | ||
| 472 | MX51_PAD_GPIO1_1__SD1_WP 0x20d5 | ||
| 339 | >; | 473 | >; |
| 340 | }; | 474 | }; |
| 341 | 475 | ||
| @@ -347,29 +481,38 @@ | |||
| 347 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 | 481 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 |
| 348 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 | 482 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 |
| 349 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 | 483 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 |
| 484 | MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */ | ||
| 485 | MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */ | ||
| 350 | >; | 486 | >; |
| 351 | }; | 487 | }; |
| 352 | 488 | ||
| 353 | pinctrl_fec: fecgrp { | 489 | pinctrl_fec: fecgrp { |
| 354 | fsl,pins = < | 490 | fsl,pins = < |
| 355 | MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 | 491 | MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 |
| 356 | MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 | 492 | MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 |
| 357 | MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 | 493 | MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 |
| 358 | MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 | 494 | MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 |
| 359 | MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 | 495 | MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 |
| 360 | MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 | 496 | MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 |
| 361 | MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 | 497 | MX51_PAD_NANDF_RB2__FEC_COL 0x00000180 |
| 362 | MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 | 498 | MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180 |
| 363 | MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 | 499 | MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180 |
| 364 | MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 | 500 | MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004 |
| 365 | MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 | 501 | MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 |
| 366 | MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 | 502 | MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004 |
| 367 | MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 | 503 | MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004 |
| 368 | MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 | 504 | MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004 |
| 369 | MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 | 505 | MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004 |
| 370 | MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 | 506 | MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004 |
| 371 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 | 507 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180 |
| 372 | MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */ | 508 | MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4 |
| 509 | MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ | ||
| 510 | >; | ||
| 511 | }; | ||
| 512 | |||
| 513 | pinctrl_gpio_keys: gpiokeysgrp { | ||
| 514 | fsl,pins = < | ||
| 515 | MX51_PAD_EIM_A27__GPIO2_21 0x5 | ||
| 373 | >; | 516 | >; |
| 374 | }; | 517 | }; |
| 375 | 518 | ||
| @@ -379,6 +522,13 @@ | |||
| 379 | >; | 522 | >; |
| 380 | }; | 523 | }; |
| 381 | 524 | ||
| 525 | pinctrl_i2c1: i2c1grp { | ||
| 526 | fsl,pins = < | ||
| 527 | MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed | ||
| 528 | MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed | ||
| 529 | >; | ||
| 530 | }; | ||
| 531 | |||
| 382 | pinctrl_i2c2: i2c2grp { | 532 | pinctrl_i2c2: i2c2grp { |
| 383 | fsl,pins = < | 533 | fsl,pins = < |
| 384 | MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed | 534 | MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed |
| @@ -455,6 +605,12 @@ | |||
| 455 | >; | 605 | >; |
| 456 | }; | 606 | }; |
| 457 | 607 | ||
| 608 | pinctrl_pmic: pmicgrp { | ||
| 609 | fsl,pins = < | ||
| 610 | MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */ | ||
| 611 | >; | ||
| 612 | }; | ||
| 613 | |||
| 458 | pinctrl_uart1: uart1grp { | 614 | pinctrl_uart1: uart1grp { |
| 459 | fsl,pins = < | 615 | fsl,pins = < |
| 460 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 | 616 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 |
| @@ -479,71 +635,33 @@ | |||
| 479 | MX51_PAD_EIM_D24__UART3_CTS 0x1c5 | 635 | MX51_PAD_EIM_D24__UART3_CTS 0x1c5 |
| 480 | >; | 636 | >; |
| 481 | }; | 637 | }; |
| 482 | }; | ||
| 483 | }; | ||
| 484 | 638 | ||
| 485 | &uart1 { | 639 | pinctrl_usbh1: usbh1grp { |
| 486 | pinctrl-names = "default"; | 640 | fsl,pins = < |
| 487 | pinctrl-0 = <&pinctrl_uart1>; | 641 | MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000 |
| 488 | fsl,uart-has-rtscts; | 642 | MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000 |
| 489 | status = "okay"; | 643 | MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000 |
| 490 | }; | 644 | MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000 |
| 491 | 645 | MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000 | |
| 492 | &uart2 { | 646 | MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000 |
| 493 | pinctrl-names = "default"; | 647 | MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000 |
| 494 | pinctrl-0 = <&pinctrl_uart2>; | 648 | MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000 |
| 495 | status = "okay"; | 649 | MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000 |
| 496 | }; | 650 | MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000 |
| 651 | MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 | ||
| 652 | >; | ||
| 653 | }; | ||
| 497 | 654 | ||
| 498 | &i2c2 { | 655 | pinctrl_usbh1reg: usbh1reggrp { |
| 499 | pinctrl-names = "default"; | 656 | fsl,pins = < |
| 500 | pinctrl-0 = <&pinctrl_i2c2>; | 657 | MX51_PAD_EIM_D21__GPIO2_5 0x85 |
| 501 | status = "okay"; | 658 | >; |
| 659 | }; | ||
| 502 | 660 | ||
| 503 | sgtl5000: codec@0a { | 661 | pinctrl_usbotgreg: usbotgreggrp { |
| 504 | compatible = "fsl,sgtl5000"; | 662 | fsl,pins = < |
| 505 | reg = <0x0a>; | 663 | MX51_PAD_GPIO1_7__GPIO1_7 0x85 |
| 506 | clocks = <&clk_26M>; | 664 | >; |
| 507 | VDDA-supply = <&vdig_reg>; | 665 | }; |
| 508 | VDDIO-supply = <&vvideo_reg>; | ||
| 509 | }; | 666 | }; |
| 510 | }; | 667 | }; |
| 511 | |||
| 512 | &audmux { | ||
| 513 | pinctrl-names = "default"; | ||
| 514 | pinctrl-0 = <&pinctrl_audmux>; | ||
| 515 | status = "okay"; | ||
| 516 | }; | ||
| 517 | |||
| 518 | &fec { | ||
| 519 | pinctrl-names = "default"; | ||
| 520 | pinctrl-0 = <&pinctrl_fec>; | ||
| 521 | phy-mode = "mii"; | ||
| 522 | phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; | ||
| 523 | phy-reset-duration = <1>; | ||
| 524 | status = "okay"; | ||
| 525 | }; | ||
| 526 | |||
| 527 | &kpp { | ||
| 528 | pinctrl-names = "default"; | ||
| 529 | pinctrl-0 = <&pinctrl_kpp>; | ||
| 530 | linux,keymap = < | ||
| 531 | MATRIX_KEY(0, 0, KEY_UP) | ||
| 532 | MATRIX_KEY(0, 1, KEY_DOWN) | ||
| 533 | MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) | ||
| 534 | MATRIX_KEY(0, 3, KEY_HOME) | ||
| 535 | MATRIX_KEY(1, 0, KEY_RIGHT) | ||
| 536 | MATRIX_KEY(1, 1, KEY_LEFT) | ||
| 537 | MATRIX_KEY(1, 2, KEY_ENTER) | ||
| 538 | MATRIX_KEY(1, 3, KEY_VOLUMEUP) | ||
| 539 | MATRIX_KEY(2, 0, KEY_F6) | ||
| 540 | MATRIX_KEY(2, 1, KEY_F8) | ||
| 541 | MATRIX_KEY(2, 2, KEY_F9) | ||
| 542 | MATRIX_KEY(2, 3, KEY_F10) | ||
| 543 | MATRIX_KEY(3, 0, KEY_F1) | ||
| 544 | MATRIX_KEY(3, 1, KEY_F2) | ||
| 545 | MATRIX_KEY(3, 2, KEY_F3) | ||
| 546 | MATRIX_KEY(3, 3, KEY_POWER) | ||
| 547 | >; | ||
| 548 | status = "okay"; | ||
| 549 | }; | ||
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts new file mode 100644 index 000000000000..1db517d3d497 --- /dev/null +++ b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts | |||
| @@ -0,0 +1,108 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include "imx51-digi-connectcore-som.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "Digi ConnectCore CC(W)-MX51 JSK"; | ||
| 16 | compatible = "digi,connectcore-ccxmx51-jsk", | ||
| 17 | "digi,connectcore-ccxmx51-som", "fsl,imx51"; | ||
| 18 | |||
| 19 | chosen { | ||
| 20 | linux,stdout-path = &uart1; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | |||
| 24 | &owire { | ||
| 25 | pinctrl-names = "default"; | ||
| 26 | pinctrl-0 = <&pinctrl_owire>; | ||
| 27 | status = "okay"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | &uart1 { | ||
| 31 | pinctrl-names = "default"; | ||
| 32 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | &uart2 { | ||
| 37 | pinctrl-names = "default"; | ||
| 38 | pinctrl-0 = <&pinctrl_uart2>; | ||
| 39 | status = "okay"; | ||
| 40 | }; | ||
| 41 | |||
| 42 | &uart3 { | ||
| 43 | pinctrl-names = "default"; | ||
| 44 | pinctrl-0 = <&pinctrl_uart3>; | ||
| 45 | status = "okay"; | ||
| 46 | }; | ||
| 47 | |||
| 48 | &usbotg { | ||
| 49 | dr_mode = "otg"; | ||
| 50 | status = "okay"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | &usbh1 { | ||
| 54 | pinctrl-names = "default"; | ||
| 55 | pinctrl-0 = <&pinctrl_usbh1>; | ||
| 56 | dr_mode = "host"; | ||
| 57 | phy_type = "ulpi"; | ||
| 58 | disable-over-current; | ||
| 59 | status = "okay"; | ||
| 60 | }; | ||
| 61 | |||
| 62 | &iomuxc { | ||
| 63 | imx51-digi-connectcore-jsk { | ||
| 64 | pinctrl_owire: owiregrp { | ||
| 65 | fsl,pins = < | ||
| 66 | MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000 | ||
| 67 | >; | ||
| 68 | }; | ||
| 69 | |||
| 70 | pinctrl_uart1: uart1grp { | ||
| 71 | fsl,pins = < | ||
| 72 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 | ||
| 73 | MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 | ||
| 74 | >; | ||
| 75 | }; | ||
| 76 | |||
| 77 | pinctrl_uart2: uart2grp { | ||
| 78 | fsl,pins = < | ||
| 79 | MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 | ||
| 80 | MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 | ||
| 81 | >; | ||
| 82 | }; | ||
| 83 | |||
| 84 | pinctrl_uart3: uart3grp { | ||
| 85 | fsl,pins = < | ||
| 86 | MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 | ||
| 87 | MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 | ||
| 88 | >; | ||
| 89 | }; | ||
| 90 | |||
| 91 | pinctrl_usbh1: usbh1grp { | ||
| 92 | fsl,pins = < | ||
| 93 | MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 | ||
| 94 | MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 | ||
| 95 | MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 | ||
| 96 | MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 | ||
| 97 | MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 | ||
| 98 | MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 | ||
| 99 | MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 | ||
| 100 | MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 | ||
| 101 | MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 | ||
| 102 | MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 | ||
| 103 | MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 | ||
| 104 | MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 | ||
| 105 | >; | ||
| 106 | }; | ||
| 107 | }; | ||
| 108 | }; | ||
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi new file mode 100644 index 000000000000..321662f53e33 --- /dev/null +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | |||
| @@ -0,0 +1,377 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx51.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "Digi ConnectCore CC(W)-MX51"; | ||
| 17 | compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51"; | ||
| 18 | |||
| 19 | memory { | ||
| 20 | reg = <0x90000000 0x08000000>; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | |||
| 24 | &ecspi1 { | ||
| 25 | pinctrl-names = "default"; | ||
| 26 | pinctrl-0 = <&pinctrl_ecspi1>; | ||
| 27 | fsl,spi-num-chipselects = <1>; | ||
| 28 | cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; | ||
| 29 | status = "okay"; | ||
| 30 | |||
| 31 | pmic: mc13892@0 { | ||
| 32 | pinctrl-names = "default"; | ||
| 33 | pinctrl-0 = <&pinctrl_mc13892>; | ||
| 34 | compatible = "fsl,mc13892"; | ||
| 35 | spi-max-frequency = <16000000>; | ||
| 36 | spi-cs-high; | ||
| 37 | reg = <0>; | ||
| 38 | interrupt-parent = <&gpio1>; | ||
| 39 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; | ||
| 40 | fsl,mc13xxx-uses-rtc; | ||
| 41 | |||
| 42 | regulators { | ||
| 43 | sw1_reg: sw1 { | ||
| 44 | regulator-min-microvolt = <1000000>; | ||
| 45 | regulator-max-microvolt = <1100000>; | ||
| 46 | regulator-boot-on; | ||
| 47 | regulator-always-on; | ||
| 48 | }; | ||
| 49 | |||
| 50 | sw2_reg: sw2 { | ||
| 51 | regulator-min-microvolt = <1225000>; | ||
| 52 | regulator-max-microvolt = <1225000>; | ||
| 53 | regulator-boot-on; | ||
| 54 | regulator-always-on; | ||
| 55 | }; | ||
| 56 | |||
| 57 | sw3_reg: sw3 { | ||
| 58 | regulator-min-microvolt = <1200000>; | ||
| 59 | regulator-max-microvolt = <1200000>; | ||
| 60 | regulator-boot-on; | ||
| 61 | regulator-always-on; | ||
| 62 | }; | ||
| 63 | |||
| 64 | swbst_reg: swbst { }; | ||
| 65 | |||
| 66 | viohi_reg: viohi { | ||
| 67 | regulator-always-on; | ||
| 68 | }; | ||
| 69 | |||
| 70 | vpll_reg: vpll { | ||
| 71 | regulator-min-microvolt = <1800000>; | ||
| 72 | regulator-max-microvolt = <1800000>; | ||
| 73 | regulator-always-on; | ||
| 74 | }; | ||
| 75 | |||
| 76 | vdig_reg: vdig { | ||
| 77 | regulator-min-microvolt = <1250000>; | ||
| 78 | regulator-max-microvolt = <1250000>; | ||
| 79 | regulator-always-on; | ||
| 80 | }; | ||
| 81 | |||
| 82 | vsd_reg: vsd { | ||
| 83 | regulator-min-microvolt = <3150000>; | ||
| 84 | regulator-max-microvolt = <3150000>; | ||
| 85 | regulator-always-on; | ||
| 86 | }; | ||
| 87 | |||
| 88 | vusb2_reg: vusb2 { | ||
| 89 | regulator-min-microvolt = <2600000>; | ||
| 90 | regulator-max-microvolt = <2600000>; | ||
| 91 | regulator-always-on; | ||
| 92 | }; | ||
| 93 | |||
| 94 | vvideo_reg: vvideo { | ||
| 95 | regulator-min-microvolt = <2775000>; | ||
| 96 | regulator-max-microvolt = <2775000>; | ||
| 97 | regulator-always-on; | ||
| 98 | }; | ||
| 99 | |||
| 100 | vaudio_reg: vaudio { | ||
| 101 | regulator-min-microvolt = <3000000>; | ||
| 102 | regulator-max-microvolt = <3000000>; | ||
| 103 | regulator-always-on; | ||
| 104 | }; | ||
| 105 | |||
| 106 | vcam_reg: vcam { | ||
| 107 | regulator-min-microvolt = <2750000>; | ||
| 108 | regulator-max-microvolt = <2750000>; | ||
| 109 | regulator-always-on; | ||
| 110 | }; | ||
| 111 | |||
| 112 | vgen1_reg: vgen1 { | ||
| 113 | regulator-min-microvolt = <1200000>; | ||
| 114 | regulator-max-microvolt = <1200000>; | ||
| 115 | regulator-always-on; | ||
| 116 | }; | ||
| 117 | |||
| 118 | vgen2_reg: vgen2 { | ||
| 119 | regulator-min-microvolt = <3150000>; | ||
| 120 | regulator-max-microvolt = <3150000>; | ||
| 121 | regulator-always-on; | ||
| 122 | }; | ||
| 123 | |||
| 124 | vgen3_reg: vgen3 { | ||
| 125 | regulator-min-microvolt = <1800000>; | ||
| 126 | regulator-max-microvolt = <1800000>; | ||
| 127 | regulator-always-on; | ||
| 128 | }; | ||
| 129 | |||
| 130 | vusb_reg: vusb { | ||
| 131 | regulator-always-on; | ||
| 132 | }; | ||
| 133 | |||
| 134 | gpo1_reg: gpo1 { }; | ||
| 135 | |||
| 136 | gpo2_reg: gpo2 { }; | ||
| 137 | |||
| 138 | gpo3_reg: gpo3 { }; | ||
| 139 | |||
| 140 | gpo4_reg: gpo4 { }; | ||
| 141 | |||
| 142 | pwgt2spi_reg: pwgt2spi { | ||
| 143 | regulator-always-on; | ||
| 144 | }; | ||
| 145 | |||
| 146 | vcoincell_reg: vcoincell { | ||
| 147 | regulator-min-microvolt = <3000000>; | ||
| 148 | regulator-max-microvolt = <3000000>; | ||
| 149 | regulator-always-on; | ||
| 150 | }; | ||
| 151 | }; | ||
| 152 | }; | ||
| 153 | }; | ||
| 154 | |||
| 155 | &esdhc2 { | ||
| 156 | pinctrl-names = "default"; | ||
| 157 | pinctrl-0 = <&pinctrl_esdhc2>; | ||
| 158 | cap-sdio-irq; | ||
| 159 | enable-sdio-wakeup; | ||
| 160 | keep-power-in-suspend; | ||
| 161 | max-frequency = <50000000>; | ||
| 162 | no-1-8-v; | ||
| 163 | non-removable; | ||
| 164 | vmmc-supply = <&gpo4_reg>; | ||
| 165 | status = "okay"; | ||
| 166 | }; | ||
| 167 | |||
| 168 | &fec { | ||
| 169 | pinctrl-names = "default"; | ||
| 170 | pinctrl-0 = <&pinctrl_fec>; | ||
| 171 | phy-mode = "mii"; | ||
| 172 | phy-supply = <&gpo3_reg>; | ||
| 173 | /* Pins shared with LCD2, keep status disabled */ | ||
| 174 | }; | ||
| 175 | |||
| 176 | &i2c2 { | ||
| 177 | pinctrl-names = "default"; | ||
| 178 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 179 | clock-frequency = <400000>; | ||
| 180 | status = "okay"; | ||
| 181 | |||
| 182 | mma7455l@1d { | ||
| 183 | pinctrl-names = "default"; | ||
| 184 | pinctrl-0 = <&pinctrl_mma7455l>; | ||
| 185 | compatible = "fsl,mma7455l"; | ||
| 186 | reg = <0x1d>; | ||
| 187 | interrupt-parent = <&gpio1>; | ||
| 188 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>; | ||
| 189 | }; | ||
| 190 | }; | ||
| 191 | |||
| 192 | &nfc { | ||
| 193 | pinctrl-names = "default"; | ||
| 194 | pinctrl-0 = <&pinctrl_nfc>; | ||
| 195 | nand-bus-width = <8>; | ||
| 196 | nand-ecc-mode = "hw"; | ||
| 197 | nand-on-flash-bbt; | ||
| 198 | status = "okay"; | ||
| 199 | }; | ||
| 200 | |||
| 201 | &usbotg { | ||
| 202 | phy_type = "utmi_wide"; | ||
| 203 | disable-over-current; | ||
| 204 | /* Device role is not known, keep status disabled */ | ||
| 205 | }; | ||
| 206 | |||
| 207 | &weim { | ||
| 208 | pinctrl-names = "default"; | ||
| 209 | pinctrl-0 = <&pinctrl_weim>; | ||
| 210 | status = "okay"; | ||
| 211 | |||
| 212 | lan9221: lan9221@5,0 { | ||
| 213 | pinctrl-names = "default"; | ||
| 214 | pinctrl-0 = <&pinctrl_lan9221>; | ||
| 215 | compatible = "smsc,lan9221", "smsc,lan9115"; | ||
| 216 | reg = <5 0x00000000 0x1000>; | ||
| 217 | fsl,weim-cs-timing = < | ||
| 218 | 0x00420081 0x00000000 | ||
| 219 | 0x32260000 0x00000000 | ||
| 220 | 0x72080f00 0x00000000 | ||
| 221 | >; | ||
| 222 | clocks = <&clks IMX5_CLK_DUMMY>; | ||
| 223 | interrupt-parent = <&gpio1>; | ||
| 224 | interrupts = <9 IRQ_TYPE_LEVEL_LOW>; | ||
| 225 | phy-mode = "mii"; | ||
| 226 | reg-io-width = <2>; | ||
| 227 | smsc,irq-push-pull; | ||
| 228 | vdd33a-supply = <&gpo2_reg>; | ||
| 229 | vddvario-supply = <&gpo2_reg>; | ||
| 230 | }; | ||
| 231 | }; | ||
| 232 | |||
| 233 | &iomuxc { | ||
| 234 | imx51-digi-connectcore-som { | ||
| 235 | pinctrl_ecspi1: ecspi1grp { | ||
| 236 | fsl,pins = < | ||
| 237 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 | ||
| 238 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 | ||
| 239 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 | ||
| 240 | MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ | ||
| 241 | >; | ||
| 242 | }; | ||
| 243 | |||
| 244 | pinctrl_esdhc2: esdhc2grp { | ||
| 245 | fsl,pins = < | ||
| 246 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 | ||
| 247 | MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 | ||
| 248 | MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 | ||
| 249 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 | ||
| 250 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 | ||
| 251 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 | ||
| 252 | >; | ||
| 253 | }; | ||
| 254 | |||
| 255 | pinctrl_fec: fecgrp { | ||
| 256 | fsl,pins = < | ||
| 257 | MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 | ||
| 258 | MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 | ||
| 259 | MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 | ||
| 260 | MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 | ||
| 261 | MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 | ||
| 262 | MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 | ||
| 263 | MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 | ||
| 264 | MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 | ||
| 265 | MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 | ||
| 266 | MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 | ||
| 267 | MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 | ||
| 268 | MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 | ||
| 269 | MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 | ||
| 270 | MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 | ||
| 271 | MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 | ||
| 272 | MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 | ||
| 273 | MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 | ||
| 274 | MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 | ||
| 275 | >; | ||
| 276 | }; | ||
| 277 | |||
| 278 | pinctrl_i2c2: i2c2grp { | ||
| 279 | fsl,pins = < | ||
| 280 | MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed | ||
| 281 | MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed | ||
| 282 | >; | ||
| 283 | }; | ||
| 284 | |||
| 285 | pinctrl_nfc: nfcgrp { | ||
| 286 | fsl,pins = < | ||
| 287 | MX51_PAD_NANDF_D0__NANDF_D0 0x80000000 | ||
| 288 | MX51_PAD_NANDF_D1__NANDF_D1 0x80000000 | ||
| 289 | MX51_PAD_NANDF_D2__NANDF_D2 0x80000000 | ||
| 290 | MX51_PAD_NANDF_D3__NANDF_D3 0x80000000 | ||
| 291 | MX51_PAD_NANDF_D4__NANDF_D4 0x80000000 | ||
| 292 | MX51_PAD_NANDF_D5__NANDF_D5 0x80000000 | ||
| 293 | MX51_PAD_NANDF_D6__NANDF_D6 0x80000000 | ||
| 294 | MX51_PAD_NANDF_D7__NANDF_D7 0x80000000 | ||
| 295 | MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000 | ||
| 296 | MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000 | ||
| 297 | MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000 | ||
| 298 | MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000 | ||
| 299 | MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000 | ||
| 300 | MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000 | ||
| 301 | MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000 | ||
| 302 | >; | ||
| 303 | }; | ||
| 304 | |||
| 305 | pinctrl_lan9221: lan9221grp { | ||
| 306 | fsl,pins = < | ||
| 307 | MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */ | ||
| 308 | >; | ||
| 309 | }; | ||
| 310 | |||
| 311 | pinctrl_mc13892: mc13892grp { | ||
| 312 | fsl,pins = < | ||
| 313 | MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */ | ||
| 314 | >; | ||
| 315 | }; | ||
| 316 | |||
| 317 | pinctrl_mma7455l: mma7455lgrp { | ||
| 318 | fsl,pins = < | ||
| 319 | MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */ | ||
| 320 | MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */ | ||
| 321 | >; | ||
| 322 | }; | ||
| 323 | |||
| 324 | pinctrl_weim: weimgrp { | ||
| 325 | fsl,pins = < | ||
| 326 | MX51_PAD_EIM_DA0__EIM_DA0 0x80000000 | ||
| 327 | MX51_PAD_EIM_DA1__EIM_DA1 0x80000000 | ||
| 328 | MX51_PAD_EIM_DA2__EIM_DA2 0x80000000 | ||
| 329 | MX51_PAD_EIM_DA3__EIM_DA3 0x80000000 | ||
| 330 | MX51_PAD_EIM_DA4__EIM_DA4 0x80000000 | ||
| 331 | MX51_PAD_EIM_DA5__EIM_DA5 0x80000000 | ||
| 332 | MX51_PAD_EIM_DA6__EIM_DA6 0x80000000 | ||
| 333 | MX51_PAD_EIM_DA7__EIM_DA7 0x80000000 | ||
| 334 | MX51_PAD_EIM_DA8__EIM_DA8 0x80000000 | ||
| 335 | MX51_PAD_EIM_DA9__EIM_DA9 0x80000000 | ||
| 336 | MX51_PAD_EIM_DA10__EIM_DA10 0x80000000 | ||
| 337 | MX51_PAD_EIM_DA11__EIM_DA11 0x80000000 | ||
| 338 | MX51_PAD_EIM_DA12__EIM_DA12 0x80000000 | ||
| 339 | MX51_PAD_EIM_DA13__EIM_DA13 0x80000000 | ||
| 340 | MX51_PAD_EIM_DA14__EIM_DA14 0x80000000 | ||
| 341 | MX51_PAD_EIM_DA15__EIM_DA15 0x80000000 | ||
| 342 | MX51_PAD_EIM_A16__EIM_A16 0x80000000 | ||
| 343 | MX51_PAD_EIM_A17__EIM_A17 0x80000000 | ||
| 344 | MX51_PAD_EIM_A18__EIM_A18 0x80000000 | ||
| 345 | MX51_PAD_EIM_A19__EIM_A19 0x80000000 | ||
| 346 | MX51_PAD_EIM_A20__EIM_A20 0x80000000 | ||
| 347 | MX51_PAD_EIM_A21__EIM_A21 0x80000000 | ||
| 348 | MX51_PAD_EIM_A22__EIM_A22 0x80000000 | ||
| 349 | MX51_PAD_EIM_A23__EIM_A23 0x80000000 | ||
| 350 | MX51_PAD_EIM_A24__EIM_A24 0x80000000 | ||
| 351 | MX51_PAD_EIM_A25__EIM_A25 0x80000000 | ||
| 352 | MX51_PAD_EIM_A26__EIM_A26 0x80000000 | ||
| 353 | MX51_PAD_EIM_A27__EIM_A27 0x80000000 | ||
| 354 | MX51_PAD_EIM_D16__EIM_D16 0x80000000 | ||
| 355 | MX51_PAD_EIM_D17__EIM_D17 0x80000000 | ||
| 356 | MX51_PAD_EIM_D18__EIM_D18 0x80000000 | ||
| 357 | MX51_PAD_EIM_D19__EIM_D19 0x80000000 | ||
| 358 | MX51_PAD_EIM_D20__EIM_D20 0x80000000 | ||
| 359 | MX51_PAD_EIM_D21__EIM_D21 0x80000000 | ||
| 360 | MX51_PAD_EIM_D22__EIM_D22 0x80000000 | ||
| 361 | MX51_PAD_EIM_D23__EIM_D23 0x80000000 | ||
| 362 | MX51_PAD_EIM_D24__EIM_D24 0x80000000 | ||
| 363 | MX51_PAD_EIM_D25__EIM_D25 0x80000000 | ||
| 364 | MX51_PAD_EIM_D26__EIM_D26 0x80000000 | ||
| 365 | MX51_PAD_EIM_D27__EIM_D27 0x80000000 | ||
| 366 | MX51_PAD_EIM_D28__EIM_D28 0x80000000 | ||
| 367 | MX51_PAD_EIM_D29__EIM_D29 0x80000000 | ||
| 368 | MX51_PAD_EIM_D30__EIM_D30 0x80000000 | ||
| 369 | MX51_PAD_EIM_D31__EIM_D31 0x80000000 | ||
| 370 | MX51_PAD_EIM_OE__EIM_OE 0x80000000 | ||
| 371 | MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000 | ||
| 372 | MX51_PAD_EIM_LBA__EIM_LBA 0x80000000 | ||
| 373 | MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */ | ||
| 374 | >; | ||
| 375 | }; | ||
| 376 | }; | ||
| 377 | }; | ||
diff --git a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi index 9b3acf6e4282..63164266af83 100644 --- a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi +++ b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi | |||
| @@ -42,6 +42,17 @@ | |||
| 42 | compatible = "nxp,pcf8563"; | 42 | compatible = "nxp,pcf8563"; |
| 43 | reg = <0x51>; | 43 | reg = <0x51>; |
| 44 | }; | 44 | }; |
| 45 | |||
| 46 | tsc2007: tsc2007@49 { | ||
| 47 | compatible = "ti,tsc2007"; | ||
| 48 | gpios = <&gpio4 0 1>; | ||
| 49 | interrupt-parent = <&gpio4>; | ||
| 50 | interrupts = <0x0 0x8>; | ||
| 51 | pinctrl-names = "default"; | ||
| 52 | pinctrl-0 = <&pinctrl_tsc2007_1>; | ||
| 53 | reg = <0x49>; | ||
| 54 | ti,x-plate-ohms = <180>; | ||
| 55 | }; | ||
| 45 | }; | 56 | }; |
| 46 | 57 | ||
| 47 | &iomuxc { | 58 | &iomuxc { |
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts index 5cec4f322096..75e66c9c6144 100644 --- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts | |||
| @@ -24,6 +24,14 @@ | |||
| 24 | model = "Eukrea CPUIMX51"; | 24 | model = "Eukrea CPUIMX51"; |
| 25 | compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51"; | 25 | compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51"; |
| 26 | 26 | ||
| 27 | clocks { | ||
| 28 | clk24M: can_clock { | ||
| 29 | compatible = "fixed-clock"; | ||
| 30 | #clock-cells = <0>; | ||
| 31 | clock-frequency = <24000000>; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | |||
| 27 | gpio_keys { | 35 | gpio_keys { |
| 28 | compatible = "gpio-keys"; | 36 | compatible = "gpio-keys"; |
| 29 | pinctrl-names = "default"; | 37 | pinctrl-names = "default"; |
| @@ -50,6 +58,23 @@ | |||
| 50 | }; | 58 | }; |
| 51 | }; | 59 | }; |
| 52 | 60 | ||
| 61 | regulators { | ||
| 62 | compatible = "simple-bus"; | ||
| 63 | #address-cells = <1>; | ||
| 64 | #size-cells = <0>; | ||
| 65 | |||
| 66 | reg_can: regulator@0 { | ||
| 67 | compatible = "regulator-fixed"; | ||
| 68 | reg = <0>; | ||
| 69 | regulator-name = "CAN_RST"; | ||
| 70 | regulator-min-microvolt = <3300000>; | ||
| 71 | regulator-max-microvolt = <3300000>; | ||
| 72 | gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; | ||
| 73 | startup-delay-us = <20000>; | ||
| 74 | enable-active-high; | ||
| 75 | }; | ||
| 76 | }; | ||
| 77 | |||
| 53 | sound { | 78 | sound { |
| 54 | compatible = "eukrea,asoc-tlv320"; | 79 | compatible = "eukrea,asoc-tlv320"; |
| 55 | eukrea,model = "imx51-eukrea-tlv320aic23"; | 80 | eukrea,model = "imx51-eukrea-tlv320aic23"; |
| @@ -57,6 +82,20 @@ | |||
| 57 | fsl,mux-int-port = <2>; | 82 | fsl,mux-int-port = <2>; |
| 58 | fsl,mux-ext-port = <3>; | 83 | fsl,mux-ext-port = <3>; |
| 59 | }; | 84 | }; |
| 85 | |||
| 86 | usbphy { | ||
| 87 | #address-cells = <1>; | ||
| 88 | #size-cells = <0>; | ||
| 89 | compatible = "simple-bus"; | ||
| 90 | |||
| 91 | usbh1phy: usbh1phy@0 { | ||
| 92 | compatible = "usb-nop-xceiv"; | ||
| 93 | reg = <0>; | ||
| 94 | clocks = <&clks IMX5_CLK_USB_PHY_GATE>; | ||
| 95 | clock-names = "main_clk"; | ||
| 96 | clock-frequency = <19200000>; | ||
| 97 | }; | ||
| 98 | }; | ||
| 60 | }; | 99 | }; |
| 61 | 100 | ||
| 62 | &audmux { | 101 | &audmux { |
| @@ -72,6 +111,26 @@ | |||
| 72 | status = "okay"; | 111 | status = "okay"; |
| 73 | }; | 112 | }; |
| 74 | 113 | ||
| 114 | &ecspi1 { | ||
| 115 | pinctrl-names = "default"; | ||
| 116 | pinctrl-0 = <&pinctrl_ecspi1>; | ||
| 117 | fsl,spi-num-chipselects = <1>; | ||
| 118 | cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; | ||
| 119 | status = "okay"; | ||
| 120 | |||
| 121 | can0: can@0 { | ||
| 122 | pinctrl-names = "default"; | ||
| 123 | pinctrl-0 = <&pinctrl_can>; | ||
| 124 | compatible = "microchip,mcp2515"; | ||
| 125 | reg = <0>; | ||
| 126 | clocks = <&clk24M>; | ||
| 127 | spi-max-frequency = <10000000>; | ||
| 128 | interrupt-parent = <&gpio1>; | ||
| 129 | interrupts = <1 IRQ_TYPE_EDGE_FALLING>; | ||
| 130 | vdd-supply = <®_can>; | ||
| 131 | }; | ||
| 132 | }; | ||
| 133 | |||
| 75 | &i2c1 { | 134 | &i2c1 { |
| 76 | tlv320aic23: codec@1a { | 135 | tlv320aic23: codec@1a { |
| 77 | compatible = "ti,tlv320aic23"; | 136 | compatible = "ti,tlv320aic23"; |
| @@ -90,6 +149,23 @@ | |||
| 90 | >; | 149 | >; |
| 91 | }; | 150 | }; |
| 92 | 151 | ||
| 152 | |||
| 153 | pinctrl_can: cangrp { | ||
| 154 | fsl,pins = < | ||
| 155 | MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* nReset */ | ||
| 156 | MX51_PAD_GPIO1_1__GPIO1_1 0x80000000 /* IRQ */ | ||
| 157 | >; | ||
| 158 | }; | ||
| 159 | |||
| 160 | pinctrl_ecspi1: ecspi1grp { | ||
| 161 | fsl,pins = < | ||
| 162 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 | ||
| 163 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 | ||
| 164 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 | ||
| 165 | MX51_PAD_CSPI1_SS0__GPIO4_24 0x80000000 /* CS0 */ | ||
| 166 | >; | ||
| 167 | }; | ||
| 168 | |||
| 93 | pinctrl_esdhc1: esdhc1grp { | 169 | pinctrl_esdhc1: esdhc1grp { |
| 94 | fsl,pins = < | 170 | fsl,pins = < |
| 95 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 | 171 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 |
| @@ -151,6 +227,29 @@ | |||
| 151 | MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 | 227 | MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 |
| 152 | >; | 228 | >; |
| 153 | }; | 229 | }; |
| 230 | |||
| 231 | pinctrl_usbh1: usbh1grp { | ||
| 232 | fsl,pins = < | ||
| 233 | MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 | ||
| 234 | MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 | ||
| 235 | MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 | ||
| 236 | MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 | ||
| 237 | MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 | ||
| 238 | MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 | ||
| 239 | MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 | ||
| 240 | MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 | ||
| 241 | MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 | ||
| 242 | MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 | ||
| 243 | MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 | ||
| 244 | MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 | ||
| 245 | >; | ||
| 246 | }; | ||
| 247 | |||
| 248 | pinctrl_usbh1_vbus: usbh1-vbusgrp { | ||
| 249 | fsl,pins = < | ||
| 250 | MX51_PAD_EIM_CS3__GPIO2_28 0x1f5 | ||
| 251 | >; | ||
| 252 | }; | ||
| 154 | }; | 253 | }; |
| 155 | }; | 254 | }; |
| 156 | 255 | ||
| @@ -173,3 +272,24 @@ | |||
| 173 | fsl,uart-has-rtscts; | 272 | fsl,uart-has-rtscts; |
| 174 | status = "okay"; | 273 | status = "okay"; |
| 175 | }; | 274 | }; |
| 275 | |||
| 276 | &usbh1 { | ||
| 277 | pinctrl-names = "default"; | ||
| 278 | pinctrl-0 = <&pinctrl_usbh1>; | ||
| 279 | fsl,usbphy = <&usbh1phy>; | ||
| 280 | dr_mode = "host"; | ||
| 281 | phy_type = "ulpi"; | ||
| 282 | status = "okay"; | ||
| 283 | }; | ||
| 284 | |||
| 285 | &usbotg { | ||
| 286 | dr_mode = "otg"; | ||
| 287 | phy_type = "utmi_wide"; | ||
| 288 | status = "okay"; | ||
| 289 | }; | ||
| 290 | |||
| 291 | &usbphy0 { | ||
| 292 | pinctrl-names = "default"; | ||
| 293 | pinctrl-0 = <&pinctrl_usbh1_vbus>; | ||
| 294 | reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; | ||
| 295 | }; | ||
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 150bb4e2f744..bebbf3ba0d5e 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | 19 | ||
| 20 | / { | 20 | / { |
| 21 | aliases { | 21 | aliases { |
| 22 | ethernet0 = &fec; | ||
| 22 | gpio0 = &gpio1; | 23 | gpio0 = &gpio1; |
| 23 | gpio1 = &gpio2; | 24 | gpio1 = &gpio2; |
| 24 | gpio2 = &gpio3; | 25 | gpio2 = &gpio3; |
| @@ -537,6 +538,8 @@ | |||
| 537 | }; | 538 | }; |
| 538 | 539 | ||
| 539 | nfc: nand@83fdb000 { | 540 | nfc: nand@83fdb000 { |
| 541 | #address-cells = <1>; | ||
| 542 | #size-cells = <1>; | ||
| 540 | compatible = "fsl,imx51-nand"; | 543 | compatible = "fsl,imx51-nand"; |
| 541 | reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; | 544 | reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; |
| 542 | interrupts = <8>; | 545 | interrupts = <8>; |
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts index a3431d784870..3e3f17aa93a1 100644 --- a/arch/arm/boot/dts/imx53-mba53.dts +++ b/arch/arm/boot/dts/imx53-mba53.dts | |||
| @@ -17,6 +17,10 @@ | |||
| 17 | model = "TQ MBa53 starter kit"; | 17 | model = "TQ MBa53 starter kit"; |
| 18 | compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; | 18 | compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; |
| 19 | 19 | ||
| 20 | chosen { | ||
| 21 | stdout-path = &uart2; | ||
| 22 | }; | ||
| 23 | |||
| 20 | backlight { | 24 | backlight { |
| 21 | compatible = "pwm-backlight"; | 25 | compatible = "pwm-backlight"; |
| 22 | pwms = <&pwm2 0 50000>; | 26 | pwms = <&pwm2 0 50000>; |
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi index ede04fa4161f..fd8c60dde7de 100644 --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi | |||
| @@ -13,6 +13,10 @@ | |||
| 13 | #include "imx53.dtsi" | 13 | #include "imx53.dtsi" |
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | chosen { | ||
| 17 | stdout-path = &uart1; | ||
| 18 | }; | ||
| 19 | |||
| 16 | memory { | 20 | memory { |
| 17 | reg = <0x70000000 0x20000000>, | 21 | reg = <0x70000000 0x20000000>, |
| 18 | <0xb0000000 0x20000000>; | 22 | <0xb0000000 0x20000000>; |
| @@ -272,6 +276,14 @@ | |||
| 272 | >; | 276 | >; |
| 273 | }; | 277 | }; |
| 274 | 278 | ||
| 279 | pinctrl_vga_sync: vgasync-grp { | ||
| 280 | fsl,pins = < | ||
| 281 | /* VGA_HSYNC, VSYNC with max drive strength */ | ||
| 282 | MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6 | ||
| 283 | MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6 | ||
| 284 | >; | ||
| 285 | }; | ||
| 286 | |||
| 275 | pinctrl_uart1: uart1grp { | 287 | pinctrl_uart1: uart1grp { |
| 276 | fsl,pins = < | 288 | fsl,pins = < |
| 277 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 | 289 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 |
| @@ -281,6 +293,15 @@ | |||
| 281 | }; | 293 | }; |
| 282 | }; | 294 | }; |
| 283 | 295 | ||
| 296 | &tve { | ||
| 297 | pinctrl-names = "default"; | ||
| 298 | pinctrl-0 = <&pinctrl_vga_sync>; | ||
| 299 | fsl,tve-mode = "vga"; | ||
| 300 | fsl,hsync-pin = <4>; | ||
| 301 | fsl,vsync-pin = <6>; | ||
| 302 | status = "okay"; | ||
| 303 | }; | ||
| 304 | |||
| 284 | &uart1 { | 305 | &uart1 { |
| 285 | pinctrl-names = "default"; | 306 | pinctrl-names = "default"; |
| 286 | pinctrl-0 = <&pinctrl_uart1>; | 307 | pinctrl-0 = <&pinctrl_uart1>; |
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 6a1bf4ff83d5..6456a0084388 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | 18 | ||
| 19 | / { | 19 | / { |
| 20 | aliases { | 20 | aliases { |
| 21 | ethernet0 = &fec; | ||
| 21 | gpio0 = &gpio1; | 22 | gpio0 = &gpio1; |
| 22 | gpio1 = &gpio2; | 23 | gpio1 = &gpio2; |
| 23 | gpio2 = &gpio3; | 24 | gpio2 = &gpio3; |
| @@ -726,8 +727,8 @@ | |||
| 726 | clocks = <&clks IMX5_CLK_VPU_GATE>, | 727 | clocks = <&clks IMX5_CLK_VPU_GATE>, |
| 727 | <&clks IMX5_CLK_VPU_GATE>; | 728 | <&clks IMX5_CLK_VPU_GATE>; |
| 728 | clock-names = "per", "ahb"; | 729 | clock-names = "per", "ahb"; |
| 730 | resets = <&src 1>; | ||
| 729 | iram = <&ocram>; | 731 | iram = <&ocram>; |
| 730 | status = "disabled"; | ||
| 731 | }; | 732 | }; |
| 732 | }; | 733 | }; |
| 733 | 734 | ||
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts index 5bfae54fb780..5373a5f2782b 100644 --- a/arch/arm/boot/dts/imx6dl-hummingboard.dts +++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts | |||
| @@ -11,6 +11,10 @@ | |||
| 11 | model = "SolidRun HummingBoard DL/Solo"; | 11 | model = "SolidRun HummingBoard DL/Solo"; |
| 12 | compatible = "solidrun,hummingboard", "fsl,imx6dl"; | 12 | compatible = "solidrun,hummingboard", "fsl,imx6dl"; |
| 13 | 13 | ||
| 14 | chosen { | ||
| 15 | stdout-path = &uart1; | ||
| 16 | }; | ||
| 17 | |||
| 14 | ir_recv: ir-receiver { | 18 | ir_recv: ir-receiver { |
| 15 | compatible = "gpio-ir-receiver"; | 19 | compatible = "gpio-ir-receiver"; |
| 16 | gpios = <&gpio1 2 1>; | 20 | gpios = <&gpio1 2 1>; |
| @@ -67,6 +71,13 @@ | |||
| 67 | status = "okay"; | 71 | status = "okay"; |
| 68 | }; | 72 | }; |
| 69 | 73 | ||
| 74 | &hdmi { | ||
| 75 | pinctrl-names = "default"; | ||
| 76 | pinctrl-0 = <&pinctrl_hummingboard_hdmi>; | ||
| 77 | ddc-i2c-bus = <&i2c2>; | ||
| 78 | status = "okay"; | ||
| 79 | }; | ||
| 80 | |||
| 70 | &i2c1 { | 81 | &i2c1 { |
| 71 | pinctrl-names = "default"; | 82 | pinctrl-names = "default"; |
| 72 | pinctrl-0 = <&pinctrl_hummingboard_i2c1>; | 83 | pinctrl-0 = <&pinctrl_hummingboard_i2c1>; |
| @@ -82,6 +93,13 @@ | |||
| 82 | */ | 93 | */ |
| 83 | }; | 94 | }; |
| 84 | 95 | ||
| 96 | &i2c2 { | ||
| 97 | clock-frequency = <100000>; | ||
| 98 | pinctrl-names = "default"; | ||
| 99 | pinctrl-0 = <&pinctrl_hummingboard_i2c2>; | ||
| 100 | status = "okay"; | ||
| 101 | }; | ||
| 102 | |||
| 85 | &iomuxc { | 103 | &iomuxc { |
| 86 | hummingboard { | 104 | hummingboard { |
| 87 | pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { | 105 | pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { |
| @@ -97,6 +115,12 @@ | |||
| 97 | >; | 115 | >; |
| 98 | }; | 116 | }; |
| 99 | 117 | ||
| 118 | pinctrl_hummingboard_hdmi: hummingboard-hdmi { | ||
| 119 | fsl,pins = < | ||
| 120 | MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 | ||
| 121 | >; | ||
| 122 | }; | ||
| 123 | |||
| 100 | pinctrl_hummingboard_i2c1: hummingboard-i2c1 { | 124 | pinctrl_hummingboard_i2c1: hummingboard-i2c1 { |
| 101 | fsl,pins = < | 125 | fsl,pins = < |
| 102 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | 126 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 |
| @@ -104,6 +128,13 @@ | |||
| 104 | >; | 128 | >; |
| 105 | }; | 129 | }; |
| 106 | 130 | ||
| 131 | pinctrl_hummingboard_i2c2: hummingboard-i2c2 { | ||
| 132 | fsl,pins = < | ||
| 133 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | ||
| 134 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 135 | >; | ||
| 136 | }; | ||
| 137 | |||
| 107 | pinctrl_hummingboard_spdif: hummingboard-spdif { | 138 | pinctrl_hummingboard_spdif: hummingboard-spdif { |
| 108 | fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>; | 139 | fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>; |
| 109 | }; | 140 | }; |
diff --git a/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts b/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts new file mode 100644 index 000000000000..08e97801494e --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx6dl-phytec-pfla02.dtsi" | ||
| 14 | #include "imx6qdl-phytec-pbab01.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Phytec phyFLEX-i.MX6 DualLite/Solo Carrier-Board"; | ||
| 18 | compatible = "phytec,imx6dl-pbab01", "phytec,imx6dl-pfla02", "fsl,imx6dl"; | ||
| 19 | }; | ||
diff --git a/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi new file mode 100644 index 000000000000..964bc2ad3c5d --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include "imx6dl.dtsi" | ||
| 13 | #include "imx6qdl-phytec-pfla02.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "Phytec phyFLEX-i.MX6 DualLite/Solo"; | ||
| 17 | compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl"; | ||
| 18 | |||
| 19 | memory { | ||
| 20 | reg = <0x10000000 0x20000000>; | ||
| 21 | }; | ||
| 22 | }; | ||
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts new file mode 100644 index 000000000000..909fafc0b650 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts | |||
| @@ -0,0 +1,539 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2014 Iain Paton <ipaton0@gmail.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | #include "imx6dl.dtsi" | ||
| 12 | #include <dt-bindings/gpio/gpio.h> | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "RIoTboard i.MX6S"; | ||
| 16 | compatible = "riot,imx6s-riotboard", "fsl,imx6dl"; | ||
| 17 | |||
| 18 | memory { | ||
| 19 | reg = <0x10000000 0x40000000>; | ||
| 20 | }; | ||
| 21 | |||
| 22 | regulators { | ||
| 23 | compatible = "simple-bus"; | ||
| 24 | #address-cells = <1>; | ||
| 25 | #size-cells = <0>; | ||
| 26 | |||
| 27 | reg_2p5v: regulator@0 { | ||
| 28 | compatible = "regulator-fixed"; | ||
| 29 | reg = <0>; | ||
| 30 | regulator-name = "2P5V"; | ||
| 31 | regulator-min-microvolt = <2500000>; | ||
| 32 | regulator-max-microvolt = <2500000>; | ||
| 33 | }; | ||
| 34 | |||
| 35 | reg_3p3v: regulator@1 { | ||
| 36 | compatible = "regulator-fixed"; | ||
| 37 | reg = <1>; | ||
| 38 | regulator-name = "3P3V"; | ||
| 39 | regulator-min-microvolt = <3300000>; | ||
| 40 | regulator-max-microvolt = <3300000>; | ||
| 41 | }; | ||
| 42 | |||
| 43 | reg_usb_otg_vbus: regulator@2 { | ||
| 44 | compatible = "regulator-fixed"; | ||
| 45 | reg = <2>; | ||
| 46 | regulator-name = "usb_otg_vbus"; | ||
| 47 | regulator-min-microvolt = <5000000>; | ||
| 48 | regulator-max-microvolt = <5000000>; | ||
| 49 | gpio = <&gpio3 22 0>; | ||
| 50 | enable-active-high; | ||
| 51 | }; | ||
| 52 | }; | ||
| 53 | |||
| 54 | leds { | ||
| 55 | compatible = "gpio-leds"; | ||
| 56 | pinctrl-names = "default"; | ||
| 57 | pinctrl-0 = <&pinctrl_led>; | ||
| 58 | |||
| 59 | led0: user1 { | ||
| 60 | label = "user1"; | ||
| 61 | gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; | ||
| 62 | default-state = "on"; | ||
| 63 | linux,default-trigger = "heartbeat"; | ||
| 64 | }; | ||
| 65 | |||
| 66 | led1: user2 { | ||
| 67 | label = "user2"; | ||
| 68 | gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; | ||
| 69 | default-state = "off"; | ||
| 70 | }; | ||
| 71 | }; | ||
| 72 | |||
| 73 | sound { | ||
| 74 | compatible = "fsl,imx-audio-sgtl5000"; | ||
| 75 | model = "imx6-riotboard-sgtl5000"; | ||
| 76 | ssi-controller = <&ssi1>; | ||
| 77 | audio-codec = <&codec>; | ||
| 78 | audio-routing = | ||
| 79 | "MIC_IN", "Mic Jack", | ||
| 80 | "Mic Jack", "Mic Bias", | ||
| 81 | "Headphone Jack", "HP_OUT"; | ||
| 82 | mux-int-port = <1>; | ||
| 83 | mux-ext-port = <3>; | ||
| 84 | }; | ||
| 85 | }; | ||
| 86 | |||
| 87 | &audmux { | ||
| 88 | pinctrl-names = "default"; | ||
| 89 | pinctrl-0 = <&pinctrl_audmux>; | ||
| 90 | status = "okay"; | ||
| 91 | }; | ||
| 92 | |||
| 93 | &fec { | ||
| 94 | pinctrl-names = "default"; | ||
| 95 | pinctrl-0 = <&pinctrl_enet>; | ||
| 96 | phy-mode = "rgmii"; | ||
| 97 | phy-reset-gpios = <&gpio3 31 0>; | ||
| 98 | interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, | ||
| 99 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; | ||
| 100 | status = "okay"; | ||
| 101 | }; | ||
| 102 | |||
| 103 | &hdmi { | ||
| 104 | ddc-i2c-bus = <&i2c2>; | ||
| 105 | status = "okay"; | ||
| 106 | }; | ||
| 107 | |||
| 108 | &i2c1 { | ||
| 109 | clock-frequency = <100000>; | ||
| 110 | pinctrl-names = "default"; | ||
| 111 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 112 | status = "okay"; | ||
| 113 | |||
| 114 | codec: sgtl5000@0a { | ||
| 115 | compatible = "fsl,sgtl5000"; | ||
| 116 | reg = <0x0a>; | ||
| 117 | clocks = <&clks 201>; | ||
| 118 | VDDA-supply = <®_2p5v>; | ||
| 119 | VDDIO-supply = <®_3p3v>; | ||
| 120 | }; | ||
| 121 | |||
| 122 | pmic: pf0100@08 { | ||
| 123 | compatible = "fsl,pfuze100"; | ||
| 124 | reg = <0x08>; | ||
| 125 | interrupt-parent = <&gpio5>; | ||
| 126 | interrupts = <16 8>; | ||
| 127 | |||
| 128 | regulators { | ||
| 129 | reg_vddcore: sw1ab { /* VDDARM_IN */ | ||
| 130 | regulator-min-microvolt = <300000>; | ||
| 131 | regulator-max-microvolt = <1875000>; | ||
| 132 | regulator-always-on; | ||
| 133 | }; | ||
| 134 | |||
| 135 | reg_vddsoc: sw1c { /* VDDSOC_IN */ | ||
| 136 | regulator-min-microvolt = <300000>; | ||
| 137 | regulator-max-microvolt = <1875000>; | ||
| 138 | regulator-always-on; | ||
| 139 | }; | ||
| 140 | |||
| 141 | reg_gen_3v3: sw2 { /* VDDHIGH_IN */ | ||
| 142 | regulator-min-microvolt = <800000>; | ||
| 143 | regulator-max-microvolt = <3300000>; | ||
| 144 | regulator-always-on; | ||
| 145 | }; | ||
| 146 | |||
| 147 | reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */ | ||
| 148 | regulator-min-microvolt = <400000>; | ||
| 149 | regulator-max-microvolt = <1975000>; | ||
| 150 | regulator-always-on; | ||
| 151 | }; | ||
| 152 | |||
| 153 | reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */ | ||
| 154 | regulator-min-microvolt = <400000>; | ||
| 155 | regulator-max-microvolt = <1975000>; | ||
| 156 | regulator-always-on; | ||
| 157 | }; | ||
| 158 | |||
| 159 | reg_ddr_vtt: sw4 { /* MIPI conn */ | ||
| 160 | regulator-min-microvolt = <400000>; | ||
| 161 | regulator-max-microvolt = <1975000>; | ||
| 162 | regulator-always-on; | ||
| 163 | }; | ||
| 164 | |||
| 165 | reg_5v_600mA: swbst { /* not used */ | ||
| 166 | regulator-min-microvolt = <5000000>; | ||
| 167 | regulator-max-microvolt = <5150000>; | ||
| 168 | }; | ||
| 169 | |||
| 170 | reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */ | ||
| 171 | regulator-min-microvolt = <1500000>; | ||
| 172 | regulator-max-microvolt = <3000000>; | ||
| 173 | regulator-always-on; | ||
| 174 | }; | ||
| 175 | |||
| 176 | vref_reg: vrefddr { /* VREF_DDR */ | ||
| 177 | regulator-boot-on; | ||
| 178 | regulator-always-on; | ||
| 179 | }; | ||
| 180 | |||
| 181 | reg_vgen1_1v5: vgen1 { /* not used */ | ||
| 182 | regulator-min-microvolt = <800000>; | ||
| 183 | regulator-max-microvolt = <1550000>; | ||
| 184 | }; | ||
| 185 | |||
| 186 | reg_vgen2_1v2_eth: vgen2 { /* pcie ? */ | ||
| 187 | regulator-min-microvolt = <800000>; | ||
| 188 | regulator-max-microvolt = <1550000>; | ||
| 189 | regulator-always-on; | ||
| 190 | }; | ||
| 191 | |||
| 192 | reg_vgen3_2v8: vgen3 { /* not used */ | ||
| 193 | regulator-min-microvolt = <1800000>; | ||
| 194 | regulator-max-microvolt = <3300000>; | ||
| 195 | }; | ||
| 196 | reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */ | ||
| 197 | regulator-min-microvolt = <1800000>; | ||
| 198 | regulator-max-microvolt = <3300000>; | ||
| 199 | regulator-always-on; | ||
| 200 | }; | ||
| 201 | |||
| 202 | reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */ | ||
| 203 | regulator-min-microvolt = <1800000>; | ||
| 204 | regulator-max-microvolt = <3300000>; | ||
| 205 | regulator-always-on; | ||
| 206 | }; | ||
| 207 | |||
| 208 | reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */ | ||
| 209 | regulator-min-microvolt = <1800000>; | ||
| 210 | regulator-max-microvolt = <3300000>; | ||
| 211 | regulator-always-on; | ||
| 212 | }; | ||
| 213 | }; | ||
| 214 | }; | ||
| 215 | }; | ||
| 216 | |||
| 217 | &i2c2 { | ||
| 218 | clock-frequency = <100000>; | ||
| 219 | pinctrl-names = "default"; | ||
| 220 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 221 | status = "okay"; | ||
| 222 | }; | ||
| 223 | |||
| 224 | &i2c4 { | ||
| 225 | clock-frequency = <100000>; | ||
| 226 | pinctrl-names = "default"; | ||
| 227 | pinctrl-0 = <&pinctrl_i2c4>; | ||
| 228 | clocks = <&clks 116>; | ||
| 229 | status = "okay"; | ||
| 230 | }; | ||
| 231 | |||
| 232 | &pwm1 { | ||
| 233 | pinctrl-names = "default"; | ||
| 234 | pinctrl-0 = <&pinctrl_pwm1>; | ||
| 235 | status = "okay"; | ||
| 236 | }; | ||
| 237 | |||
| 238 | &pwm2 { | ||
| 239 | pinctrl-names = "default"; | ||
| 240 | pinctrl-0 = <&pinctrl_pwm2>; | ||
| 241 | status = "okay"; | ||
| 242 | }; | ||
| 243 | |||
| 244 | &pwm3 { | ||
| 245 | pinctrl-names = "default"; | ||
| 246 | pinctrl-0 = <&pinctrl_pwm3>; | ||
| 247 | status = "okay"; | ||
| 248 | }; | ||
| 249 | |||
| 250 | &pwm4 { | ||
| 251 | pinctrl-names = "default"; | ||
| 252 | pinctrl-0 = <&pinctrl_pwm4>; | ||
| 253 | status = "okay"; | ||
| 254 | }; | ||
| 255 | |||
| 256 | &ssi1 { | ||
| 257 | fsl,mode = "i2s-slave"; | ||
| 258 | status = "okay"; | ||
| 259 | }; | ||
| 260 | |||
| 261 | &uart1 { | ||
| 262 | pinctrl-names = "default"; | ||
| 263 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 264 | status = "okay"; | ||
| 265 | }; | ||
| 266 | |||
| 267 | &uart2 { | ||
| 268 | pinctrl-names = "default"; | ||
| 269 | pinctrl-0 = <&pinctrl_uart2>; | ||
| 270 | status = "okay"; | ||
| 271 | }; | ||
| 272 | |||
| 273 | &uart3 { | ||
| 274 | pinctrl-names = "default"; | ||
| 275 | pinctrl-0 = <&pinctrl_uart3>; | ||
| 276 | status = "okay"; | ||
| 277 | }; | ||
| 278 | |||
| 279 | &uart4 { | ||
| 280 | pinctrl-names = "default"; | ||
| 281 | pinctrl-0 = <&pinctrl_uart4>; | ||
| 282 | status = "okay"; | ||
| 283 | }; | ||
| 284 | |||
| 285 | &uart5 { | ||
| 286 | pinctrl-names = "default"; | ||
| 287 | pinctrl-0 = <&pinctrl_uart5>; | ||
| 288 | status = "okay"; | ||
| 289 | }; | ||
| 290 | |||
| 291 | &usbh1 { | ||
| 292 | dr_mode = "host"; | ||
| 293 | disable-over-current; | ||
| 294 | status = "okay"; | ||
| 295 | }; | ||
| 296 | |||
| 297 | &usbotg { | ||
| 298 | vbus-supply = <®_usb_otg_vbus>; | ||
| 299 | pinctrl-names = "default"; | ||
| 300 | pinctrl-0 = <&pinctrl_usbotg>; | ||
| 301 | disable-over-current; | ||
| 302 | dr_mode = "otg"; | ||
| 303 | status = "okay"; | ||
| 304 | }; | ||
| 305 | |||
| 306 | &usdhc2 { | ||
| 307 | pinctrl-names = "default"; | ||
| 308 | pinctrl-0 = <&pinctrl_usdhc2>; | ||
| 309 | cd-gpios = <&gpio1 4 0>; | ||
| 310 | wp-gpios = <&gpio1 2 0>; | ||
| 311 | vmmc-supply = <®_3p3v>; | ||
| 312 | status = "okay"; | ||
| 313 | }; | ||
| 314 | |||
| 315 | &usdhc3 { | ||
| 316 | pinctrl-names = "default"; | ||
| 317 | pinctrl-0 = <&pinctrl_usdhc3>; | ||
| 318 | cd-gpios = <&gpio7 0 0>; | ||
| 319 | wp-gpios = <&gpio7 1 0>; | ||
| 320 | vmmc-supply = <®_3p3v>; | ||
| 321 | status = "okay"; | ||
| 322 | }; | ||
| 323 | |||
| 324 | &usdhc4 { | ||
| 325 | pinctrl-names = "default"; | ||
| 326 | pinctrl-0 = <&pinctrl_usdhc4>; | ||
| 327 | vmmc-supply = <®_3p3v>; | ||
| 328 | non-removable; | ||
| 329 | status = "okay"; | ||
| 330 | }; | ||
| 331 | |||
| 332 | &iomuxc { | ||
| 333 | pinctrl-names = "default"; | ||
| 334 | |||
| 335 | imx6-riotboard { | ||
| 336 | pinctrl_audmux: audmuxgrp { | ||
| 337 | fsl,pins = < | ||
| 338 | MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x8000000 | ||
| 339 | MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x8000000 | ||
| 340 | MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x8000000 | ||
| 341 | MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x8000000 | ||
| 342 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ | ||
| 343 | >; | ||
| 344 | }; | ||
| 345 | |||
| 346 | pinctrl_ecspi1: ecspi1grp { | ||
| 347 | fsl,pins = < | ||
| 348 | MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 | ||
| 349 | MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 | ||
| 350 | MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 | ||
| 351 | MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */ | ||
| 352 | >; | ||
| 353 | }; | ||
| 354 | |||
| 355 | pinctrl_ecspi2: ecspi2grp { | ||
| 356 | fsl,pins = < | ||
| 357 | MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */ | ||
| 358 | MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 | ||
| 359 | MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 | ||
| 360 | MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */ | ||
| 361 | MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 | ||
| 362 | >; | ||
| 363 | }; | ||
| 364 | |||
| 365 | pinctrl_ecspi3: ecspi3grp { | ||
| 366 | fsl,pins = < | ||
| 367 | MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 | ||
| 368 | MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 | ||
| 369 | MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 | ||
| 370 | MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */ | ||
| 371 | MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */ | ||
| 372 | >; | ||
| 373 | }; | ||
| 374 | |||
| 375 | pinctrl_enet: enetgrp { | ||
| 376 | fsl,pins = < | ||
| 377 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 378 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 379 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000 | ||
| 380 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 381 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 382 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 383 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 384 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 385 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ | ||
| 386 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 /* AR8035 pin strapping: IO voltage: pull up */ | ||
| 387 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 /* AR8035 pin strapping: PHYADDR#0: pull down */ | ||
| 388 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 /* AR8035 pin strapping: PHYADDR#1: pull down */ | ||
| 389 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 /* AR8035 pin strapping: MODE#1: pull up */ | ||
| 390 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 /* AR8035 pin strapping: MODE#3: pull up */ | ||
| 391 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ | ||
| 392 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 /* GPIO16 -> AR8035 25MHz */ | ||
| 393 | MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ | ||
| 394 | MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* AR8035 interrupt */ | ||
| 395 | MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 | ||
| 396 | >; | ||
| 397 | }; | ||
| 398 | |||
| 399 | pinctrl_i2c1: i2c1grp { | ||
| 400 | fsl,pins = < | ||
| 401 | MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 | ||
| 402 | MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 | ||
| 403 | >; | ||
| 404 | }; | ||
| 405 | |||
| 406 | pinctrl_i2c2: i2c2grp { | ||
| 407 | fsl,pins = < | ||
| 408 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | ||
| 409 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 410 | >; | ||
| 411 | }; | ||
| 412 | |||
| 413 | pinctrl_i2c3: i2c3grp { | ||
| 414 | fsl,pins = < | ||
| 415 | MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 | ||
| 416 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 | ||
| 417 | >; | ||
| 418 | }; | ||
| 419 | |||
| 420 | pinctrl_i2c4: i2c4grp { | ||
| 421 | fsl,pins = < | ||
| 422 | MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 | ||
| 423 | MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 | ||
| 424 | >; | ||
| 425 | }; | ||
| 426 | |||
| 427 | pinctrl_led: ledgrp { | ||
| 428 | fsl,pins = < | ||
| 429 | MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* user led0 */ | ||
| 430 | MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x80000000 /* user led1 */ | ||
| 431 | >; | ||
| 432 | }; | ||
| 433 | |||
| 434 | pinctrl_pwm1: pwm1grp { | ||
| 435 | fsl,pins = < | ||
| 436 | MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 | ||
| 437 | >; | ||
| 438 | }; | ||
| 439 | |||
| 440 | pinctrl_pwm2: pwm2grp { | ||
| 441 | fsl,pins = < | ||
| 442 | MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 | ||
| 443 | >; | ||
| 444 | }; | ||
| 445 | |||
| 446 | pinctrl_pwm3: pwm3grp { | ||
| 447 | fsl,pins = < | ||
| 448 | MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 | ||
| 449 | >; | ||
| 450 | }; | ||
| 451 | |||
| 452 | pinctrl_pwm4: pwm4grp { | ||
| 453 | fsl,pins = < | ||
| 454 | MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 | ||
| 455 | >; | ||
| 456 | }; | ||
| 457 | |||
| 458 | pinctrl_uart1: uart1grp { | ||
| 459 | fsl,pins = < | ||
| 460 | MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | ||
| 461 | MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | ||
| 462 | >; | ||
| 463 | }; | ||
| 464 | |||
| 465 | pinctrl_uart2: uart2grp { | ||
| 466 | fsl,pins = < | ||
| 467 | MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 | ||
| 468 | MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 | ||
| 469 | >; | ||
| 470 | }; | ||
| 471 | |||
| 472 | pinctrl_uart3: uart3grp { | ||
| 473 | fsl,pins = < | ||
| 474 | MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 | ||
| 475 | MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 | ||
| 476 | >; | ||
| 477 | }; | ||
| 478 | |||
| 479 | pinctrl_uart4: uart4grp { | ||
| 480 | fsl,pins = < | ||
| 481 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | ||
| 482 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | ||
| 483 | >; | ||
| 484 | }; | ||
| 485 | |||
| 486 | pinctrl_uart5: uart5grp { | ||
| 487 | fsl,pins = < | ||
| 488 | MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 | ||
| 489 | MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 | ||
| 490 | >; | ||
| 491 | }; | ||
| 492 | |||
| 493 | pinctrl_usbotg: usbotggrp { | ||
| 494 | fsl,pins = < | ||
| 495 | MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | ||
| 496 | MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ | ||
| 497 | MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x80000000 | ||
| 498 | >; | ||
| 499 | }; | ||
| 500 | |||
| 501 | pinctrl_usdhc2: usdhc2grp { | ||
| 502 | fsl,pins = < | ||
| 503 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 504 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 505 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 506 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 507 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 508 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 509 | MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* SD2 CD */ | ||
| 510 | MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* SD2 WP */ | ||
| 511 | >; | ||
| 512 | }; | ||
| 513 | |||
| 514 | pinctrl_usdhc3: usdhc3grp { | ||
| 515 | fsl,pins = < | ||
| 516 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 517 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 518 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 519 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 520 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 521 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 522 | MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3 CD */ | ||
| 523 | MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x80000000 /* SD3 WP */ | ||
| 524 | >; | ||
| 525 | }; | ||
| 526 | |||
| 527 | pinctrl_usdhc4: usdhc4grp { | ||
| 528 | fsl,pins = < | ||
| 529 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 530 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 531 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 532 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 533 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 534 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 535 | MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 /* SD4 RST (eMMC) */ | ||
| 536 | >; | ||
| 537 | }; | ||
| 538 | }; | ||
| 539 | }; | ||
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 5c5f574330f9..0a9c49d69d41 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi | |||
| @@ -84,9 +84,10 @@ | |||
| 84 | i2c4: i2c@021f8000 { | 84 | i2c4: i2c@021f8000 { |
| 85 | #address-cells = <1>; | 85 | #address-cells = <1>; |
| 86 | #size-cells = <0>; | 86 | #size-cells = <0>; |
| 87 | compatible = "fsl,imx1-i2c"; | 87 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| 88 | reg = <0x021f8000 0x4000>; | 88 | reg = <0x021f8000 0x4000>; |
| 89 | interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; | 89 | interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; |
| 90 | clocks = <&clks 116>; | ||
| 90 | status = "disabled"; | 91 | status = "disabled"; |
| 91 | }; | 92 | }; |
| 92 | }; | 93 | }; |
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index e4ae38fd0269..e0302636aff5 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | |||
| @@ -18,6 +18,10 @@ | |||
| 18 | model = "Data Modul eDM-QMX6 Board"; | 18 | model = "Data Modul eDM-QMX6 Board"; |
| 19 | compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q"; | 19 | compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q"; |
| 20 | 20 | ||
| 21 | chosen { | ||
| 22 | stdout-path = &uart2; | ||
| 23 | }; | ||
| 24 | |||
| 21 | aliases { | 25 | aliases { |
| 22 | gpio7 = &stmpe_gpio1; | 26 | gpio7 = &stmpe_gpio1; |
| 23 | gpio8 = &stmpe_gpio2; | 27 | gpio8 = &stmpe_gpio2; |
| @@ -91,6 +95,20 @@ | |||
| 91 | }; | 95 | }; |
| 92 | }; | 96 | }; |
| 93 | 97 | ||
| 98 | &ecspi5 { | ||
| 99 | pinctrl-names = "default"; | ||
| 100 | pinctrl-0 = <&pinctrl_ecspi5>; | ||
| 101 | fsl,spi-num-chipselects = <1>; | ||
| 102 | cs-gpios = <&gpio1 12 0>; | ||
| 103 | status = "okay"; | ||
| 104 | |||
| 105 | flash: m25p80@0 { | ||
| 106 | compatible = "m25p80"; | ||
| 107 | spi-max-frequency = <40000000>; | ||
| 108 | reg = <0>; | ||
| 109 | }; | ||
| 110 | }; | ||
| 111 | |||
| 94 | &fec { | 112 | &fec { |
| 95 | pinctrl-names = "default"; | 113 | pinctrl-names = "default"; |
| 96 | pinctrl-0 = <&pinctrl_enet>; | 114 | pinctrl-0 = <&pinctrl_enet>; |
| @@ -105,7 +123,8 @@ | |||
| 105 | pinctrl-names = "default"; | 123 | pinctrl-names = "default"; |
| 106 | pinctrl-0 = <&pinctrl_i2c2 | 124 | pinctrl-0 = <&pinctrl_i2c2 |
| 107 | &pinctrl_stmpe1 | 125 | &pinctrl_stmpe1 |
| 108 | &pinctrl_stmpe2>; | 126 | &pinctrl_stmpe2 |
| 127 | &pinctrl_pfuze>; | ||
| 109 | status = "okay"; | 128 | status = "okay"; |
| 110 | 129 | ||
| 111 | pmic: pfuze100@08 { | 130 | pmic: pfuze100@08 { |
| @@ -216,6 +235,8 @@ | |||
| 216 | reg = <0x40>; | 235 | reg = <0x40>; |
| 217 | interrupts = <30 0>; | 236 | interrupts = <30 0>; |
| 218 | interrupt-parent = <&gpio3>; | 237 | interrupt-parent = <&gpio3>; |
| 238 | vcc-supply = <&sw2_reg>; | ||
| 239 | vio-supply = <&sw2_reg>; | ||
| 219 | 240 | ||
| 220 | stmpe_gpio1: stmpe_gpio { | 241 | stmpe_gpio1: stmpe_gpio { |
| 221 | #gpio-cells = <2>; | 242 | #gpio-cells = <2>; |
| @@ -228,6 +249,8 @@ | |||
| 228 | reg = <0x44>; | 249 | reg = <0x44>; |
| 229 | interrupts = <2 0>; | 250 | interrupts = <2 0>; |
| 230 | interrupt-parent = <&gpio5>; | 251 | interrupt-parent = <&gpio5>; |
| 252 | vcc-supply = <&sw2_reg>; | ||
| 253 | vio-supply = <&sw2_reg>; | ||
| 231 | 254 | ||
| 232 | stmpe_gpio2: stmpe_gpio { | 255 | stmpe_gpio2: stmpe_gpio { |
| 233 | #gpio-cells = <2>; | 256 | #gpio-cells = <2>; |
| @@ -263,6 +286,15 @@ | |||
| 263 | >; | 286 | >; |
| 264 | }; | 287 | }; |
| 265 | 288 | ||
| 289 | pinctrl_ecspi5: ecspi5rp-1 { | ||
| 290 | fsl,pins = < | ||
| 291 | MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000 | ||
| 292 | MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000 | ||
| 293 | MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000 | ||
| 294 | MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000 | ||
| 295 | >; | ||
| 296 | }; | ||
| 297 | |||
| 266 | pinctrl_enet: enetgrp { | 298 | pinctrl_enet: enetgrp { |
| 267 | fsl,pins = < | 299 | fsl,pins = < |
| 268 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | 300 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 |
| @@ -291,6 +323,12 @@ | |||
| 291 | >; | 323 | >; |
| 292 | }; | 324 | }; |
| 293 | 325 | ||
| 326 | pinctrl_pfuze: pfuze100grp1 { | ||
| 327 | fsl,pins = < | ||
| 328 | MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000 | ||
| 329 | >; | ||
| 330 | }; | ||
| 331 | |||
| 294 | pinctrl_stmpe1: stmpe1grp { | 332 | pinctrl_stmpe1: stmpe1grp { |
| 295 | fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>; | 333 | fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>; |
| 296 | }; | 334 | }; |
diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts index 4a9b4dc9afc0..703539cf36d3 100644 --- a/arch/arm/boot/dts/imx6q-gk802.dts +++ b/arch/arm/boot/dts/imx6q-gk802.dts | |||
| @@ -14,7 +14,7 @@ | |||
| 14 | compatible = "zealz,imx6q-gk802", "fsl,imx6q"; | 14 | compatible = "zealz,imx6q-gk802", "fsl,imx6q"; |
| 15 | 15 | ||
| 16 | chosen { | 16 | chosen { |
| 17 | linux,stdout-path = &uart4; | 17 | stdout-path = &uart4; |
| 18 | }; | 18 | }; |
| 19 | 19 | ||
| 20 | memory { | 20 | memory { |
| @@ -48,6 +48,11 @@ | |||
| 48 | }; | 48 | }; |
| 49 | }; | 49 | }; |
| 50 | 50 | ||
| 51 | &hdmi { | ||
| 52 | ddc-i2c-bus = <&i2c3>; | ||
| 53 | status = "okay"; | ||
| 54 | }; | ||
| 55 | |||
| 51 | /* Internal I2C */ | 56 | /* Internal I2C */ |
| 52 | &i2c2 { | 57 | &i2c2 { |
| 53 | pinctrl-names = "default"; | 58 | pinctrl-names = "default"; |
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index e51bb3f0fd56..3689eaa58826 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts | |||
| @@ -157,6 +157,11 @@ | |||
| 157 | status = "okay"; | 157 | status = "okay"; |
| 158 | }; | 158 | }; |
| 159 | 159 | ||
| 160 | &hdmi { | ||
| 161 | ddc-i2c-bus = <&i2c3>; | ||
| 162 | status = "okay"; | ||
| 163 | }; | ||
| 164 | |||
| 160 | &i2c1 { | 165 | &i2c1 { |
| 161 | clock-frequency = <100000>; | 166 | clock-frequency = <100000>; |
| 162 | pinctrl-names = "default"; | 167 | pinctrl-names = "default"; |
diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts index 5607c331fca8..c139ac0ebe15 100644 --- a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts +++ b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts | |||
| @@ -11,40 +11,17 @@ | |||
| 11 | 11 | ||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | #include "imx6q-phytec-pfla02.dtsi" | 13 | #include "imx6q-phytec-pfla02.dtsi" |
| 14 | #include "imx6qdl-phytec-pbab01.dtsi" | ||
| 14 | 15 | ||
| 15 | / { | 16 | / { |
| 16 | model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board"; | 17 | model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board"; |
| 17 | compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q"; | 18 | compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q"; |
| 18 | }; | ||
| 19 | |||
| 20 | &fec { | ||
| 21 | status = "okay"; | ||
| 22 | }; | ||
| 23 | 19 | ||
| 24 | &gpmi { | 20 | chosen { |
| 25 | status = "okay"; | 21 | stdout-path = &uart4; |
| 22 | }; | ||
| 26 | }; | 23 | }; |
| 27 | 24 | ||
| 28 | &sata { | 25 | &sata { |
| 29 | status = "okay"; | 26 | status = "okay"; |
| 30 | }; | ||
| 31 | |||
| 32 | &uart4 { | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | &usbh1 { | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | |||
| 40 | &usbotg { | ||
| 41 | status = "okay"; | ||
| 42 | }; | ||
| 43 | |||
| 44 | &usdhc2 { | ||
| 45 | status = "okay"; | ||
| 46 | }; | ||
| 47 | |||
| 48 | &usdhc3 { | ||
| 49 | status = "okay"; | ||
| 50 | }; | 27 | }; |
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi index 324f1550976b..cd20d0a948de 100644 --- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi | |||
| @@ -10,316 +10,13 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include "imx6q.dtsi" | 12 | #include "imx6q.dtsi" |
| 13 | #include "imx6qdl-phytec-pfla02.dtsi" | ||
| 13 | 14 | ||
| 14 | / { | 15 | / { |
| 15 | model = "Phytec phyFLEX-i.MX6 Ouad"; | 16 | model = "Phytec phyFLEX-i.MX6 Quad"; |
| 16 | compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; | 17 | compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; |
| 17 | 18 | ||
| 18 | memory { | 19 | memory { |
| 19 | reg = <0x10000000 0x80000000>; | 20 | reg = <0x10000000 0x80000000>; |
| 20 | }; | 21 | }; |
| 21 | |||
| 22 | regulators { | ||
| 23 | compatible = "simple-bus"; | ||
| 24 | #address-cells = <1>; | ||
| 25 | #size-cells = <0>; | ||
| 26 | |||
| 27 | reg_usb_otg_vbus: regulator@0 { | ||
| 28 | compatible = "regulator-fixed"; | ||
| 29 | reg = <0>; | ||
| 30 | regulator-name = "usb_otg_vbus"; | ||
| 31 | regulator-min-microvolt = <5000000>; | ||
| 32 | regulator-max-microvolt = <5000000>; | ||
| 33 | gpio = <&gpio4 15 0>; | ||
| 34 | }; | ||
| 35 | |||
| 36 | reg_usb_h1_vbus: regulator@1 { | ||
| 37 | compatible = "regulator-fixed"; | ||
| 38 | reg = <1>; | ||
| 39 | regulator-name = "usb_h1_vbus"; | ||
| 40 | regulator-min-microvolt = <5000000>; | ||
| 41 | regulator-max-microvolt = <5000000>; | ||
| 42 | gpio = <&gpio1 0 0>; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | |||
| 47 | &ecspi3 { | ||
| 48 | pinctrl-names = "default"; | ||
| 49 | pinctrl-0 = <&pinctrl_ecspi3>; | ||
| 50 | status = "okay"; | ||
| 51 | fsl,spi-num-chipselects = <1>; | ||
| 52 | cs-gpios = <&gpio4 24 0>; | ||
| 53 | |||
| 54 | flash@0 { | ||
| 55 | compatible = "m25p80"; | ||
| 56 | spi-max-frequency = <20000000>; | ||
| 57 | reg = <0>; | ||
| 58 | }; | ||
| 59 | }; | ||
| 60 | |||
| 61 | &i2c1 { | ||
| 62 | pinctrl-names = "default"; | ||
| 63 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 64 | status = "okay"; | ||
| 65 | |||
| 66 | eeprom@50 { | ||
| 67 | compatible = "atmel,24c32"; | ||
| 68 | reg = <0x50>; | ||
| 69 | }; | ||
| 70 | |||
| 71 | pmic@58 { | ||
| 72 | compatible = "dialog,da9063"; | ||
| 73 | reg = <0x58>; | ||
| 74 | interrupt-parent = <&gpio4>; | ||
| 75 | interrupts = <17 0x8>; /* active-low GPIO4_17 */ | ||
| 76 | |||
| 77 | regulators { | ||
| 78 | vddcore_reg: bcore1 { | ||
| 79 | regulator-min-microvolt = <730000>; | ||
| 80 | regulator-max-microvolt = <1380000>; | ||
| 81 | regulator-always-on; | ||
| 82 | }; | ||
| 83 | |||
| 84 | vddsoc_reg: bcore2 { | ||
| 85 | regulator-min-microvolt = <730000>; | ||
| 86 | regulator-max-microvolt = <1380000>; | ||
| 87 | regulator-always-on; | ||
| 88 | }; | ||
| 89 | |||
| 90 | vdd_ddr3_reg: bpro { | ||
| 91 | regulator-min-microvolt = <1500000>; | ||
| 92 | regulator-max-microvolt = <1500000>; | ||
| 93 | regulator-always-on; | ||
| 94 | }; | ||
| 95 | |||
| 96 | vdd_3v3_reg: bperi { | ||
| 97 | regulator-min-microvolt = <3300000>; | ||
| 98 | regulator-max-microvolt = <3300000>; | ||
| 99 | regulator-always-on; | ||
| 100 | }; | ||
| 101 | |||
| 102 | vdd_buckmem_reg: bmem { | ||
| 103 | regulator-min-microvolt = <3300000>; | ||
| 104 | regulator-max-microvolt = <3300000>; | ||
| 105 | regulator-always-on; | ||
| 106 | }; | ||
| 107 | |||
| 108 | vdd_eth_reg: bio { | ||
| 109 | regulator-min-microvolt = <1200000>; | ||
| 110 | regulator-max-microvolt = <1200000>; | ||
| 111 | regulator-always-on; | ||
| 112 | }; | ||
| 113 | |||
| 114 | vdd_eth_io_reg: ldo4 { | ||
| 115 | regulator-min-microvolt = <2500000>; | ||
| 116 | regulator-max-microvolt = <2500000>; | ||
| 117 | regulator-always-on; | ||
| 118 | }; | ||
| 119 | |||
| 120 | vdd_mx6_snvs_reg: ldo5 { | ||
| 121 | regulator-min-microvolt = <3000000>; | ||
| 122 | regulator-max-microvolt = <3000000>; | ||
| 123 | regulator-always-on; | ||
| 124 | }; | ||
| 125 | |||
| 126 | vdd_3v3_pmic_io_reg: ldo6 { | ||
| 127 | regulator-min-microvolt = <3300000>; | ||
| 128 | regulator-max-microvolt = <3300000>; | ||
| 129 | regulator-always-on; | ||
| 130 | }; | ||
| 131 | |||
| 132 | vdd_sd0_reg: ldo9 { | ||
| 133 | regulator-min-microvolt = <3300000>; | ||
| 134 | regulator-max-microvolt = <3300000>; | ||
| 135 | }; | ||
| 136 | |||
| 137 | vdd_sd1_reg: ldo10 { | ||
| 138 | regulator-min-microvolt = <3300000>; | ||
| 139 | regulator-max-microvolt = <3300000>; | ||
| 140 | }; | ||
| 141 | |||
| 142 | vdd_mx6_high_reg: ldo11 { | ||
| 143 | regulator-min-microvolt = <3000000>; | ||
| 144 | regulator-max-microvolt = <3000000>; | ||
| 145 | regulator-always-on; | ||
| 146 | }; | ||
| 147 | }; | ||
| 148 | }; | ||
| 149 | }; | ||
| 150 | |||
| 151 | &iomuxc { | ||
| 152 | pinctrl-names = "default"; | ||
| 153 | pinctrl-0 = <&pinctrl_hog>; | ||
| 154 | |||
| 155 | imx6q-phytec-pfla02 { | ||
| 156 | pinctrl_hog: hoggrp { | ||
| 157 | fsl,pins = < | ||
| 158 | MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 | ||
| 159 | MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ | ||
| 160 | MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ | ||
| 161 | >; | ||
| 162 | }; | ||
| 163 | |||
| 164 | pinctrl_ecspi3: ecspi3grp { | ||
| 165 | fsl,pins = < | ||
| 166 | MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 | ||
| 167 | MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 | ||
| 168 | MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 | ||
| 169 | >; | ||
| 170 | }; | ||
| 171 | |||
| 172 | pinctrl_enet: enetgrp { | ||
| 173 | fsl,pins = < | ||
| 174 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 175 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 176 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 177 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 178 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 179 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 180 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 181 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 182 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 183 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 184 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 185 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 186 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 187 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 188 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 189 | MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 | ||
| 190 | >; | ||
| 191 | }; | ||
| 192 | |||
| 193 | pinctrl_gpmi_nand: gpminandgrp { | ||
| 194 | fsl,pins = < | ||
| 195 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 196 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 197 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 198 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 199 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 200 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 201 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 202 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 203 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 204 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 205 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 206 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 207 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 208 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 209 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 210 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 211 | MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 | ||
| 212 | >; | ||
| 213 | }; | ||
| 214 | |||
| 215 | pinctrl_i2c1: i2c1grp { | ||
| 216 | fsl,pins = < | ||
| 217 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | ||
| 218 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | ||
| 219 | >; | ||
| 220 | }; | ||
| 221 | |||
| 222 | pinctrl_uart4: uart4grp { | ||
| 223 | fsl,pins = < | ||
| 224 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | ||
| 225 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | ||
| 226 | >; | ||
| 227 | }; | ||
| 228 | |||
| 229 | pinctrl_usbh1: usbh1grp { | ||
| 230 | fsl,pins = < | ||
| 231 | MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000 | ||
| 232 | >; | ||
| 233 | }; | ||
| 234 | |||
| 235 | pinctrl_usbotg: usbotggrp { | ||
| 236 | fsl,pins = < | ||
| 237 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 238 | MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 | ||
| 239 | MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 | ||
| 240 | >; | ||
| 241 | }; | ||
| 242 | |||
| 243 | pinctrl_usdhc2: usdhc2grp { | ||
| 244 | fsl,pins = < | ||
| 245 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 246 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 247 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 248 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 249 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 250 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 251 | >; | ||
| 252 | }; | ||
| 253 | |||
| 254 | pinctrl_usdhc3: usdhc3grp { | ||
| 255 | fsl,pins = < | ||
| 256 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 257 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 258 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 259 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 260 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 261 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 262 | >; | ||
| 263 | }; | ||
| 264 | |||
| 265 | pinctrl_usdhc3_cdwp: usdhc3cdwp { | ||
| 266 | fsl,pins = < | ||
| 267 | MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 | ||
| 268 | MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 | ||
| 269 | >; | ||
| 270 | }; | ||
| 271 | }; | ||
| 272 | }; | ||
| 273 | |||
| 274 | &fec { | ||
| 275 | pinctrl-names = "default"; | ||
| 276 | pinctrl-0 = <&pinctrl_enet>; | ||
| 277 | phy-mode = "rgmii"; | ||
| 278 | phy-reset-gpios = <&gpio3 23 0>; | ||
| 279 | status = "disabled"; | ||
| 280 | }; | ||
| 281 | |||
| 282 | &gpmi { | ||
| 283 | pinctrl-names = "default"; | ||
| 284 | pinctrl-0 = <&pinctrl_gpmi_nand>; | ||
| 285 | nand-on-flash-bbt; | ||
| 286 | status = "disabled"; | ||
| 287 | }; | ||
| 288 | |||
| 289 | &uart4 { | ||
| 290 | pinctrl-names = "default"; | ||
| 291 | pinctrl-0 = <&pinctrl_uart4>; | ||
| 292 | status = "disabled"; | ||
| 293 | }; | ||
| 294 | |||
| 295 | &usbh1 { | ||
| 296 | vbus-supply = <®_usb_h1_vbus>; | ||
| 297 | pinctrl-names = "default"; | ||
| 298 | pinctrl-0 = <&pinctrl_usbh1>; | ||
| 299 | status = "disabled"; | ||
| 300 | }; | ||
| 301 | |||
| 302 | &usbotg { | ||
| 303 | vbus-supply = <®_usb_otg_vbus>; | ||
| 304 | pinctrl-names = "default"; | ||
| 305 | pinctrl-0 = <&pinctrl_usbotg>; | ||
| 306 | disable-over-current; | ||
| 307 | status = "disabled"; | ||
| 308 | }; | ||
| 309 | |||
| 310 | &usdhc2 { | ||
| 311 | pinctrl-names = "default"; | ||
| 312 | pinctrl-0 = <&pinctrl_usdhc2>; | ||
| 313 | cd-gpios = <&gpio1 4 0>; | ||
| 314 | wp-gpios = <&gpio1 2 0>; | ||
| 315 | status = "disabled"; | ||
| 316 | }; | ||
| 317 | |||
| 318 | &usdhc3 { | ||
| 319 | pinctrl-names = "default"; | ||
| 320 | pinctrl-0 = <&pinctrl_usdhc3 | ||
| 321 | &pinctrl_usdhc3_cdwp>; | ||
| 322 | cd-gpios = <&gpio1 27 0>; | ||
| 323 | wp-gpios = <&gpio1 29 0>; | ||
| 324 | status = "disabled"; | ||
| 325 | }; | 22 | }; |
diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts index ed397d149ab6..6c561060bf5c 100644 --- a/arch/arm/boot/dts/imx6q-udoo.dts +++ b/arch/arm/boot/dts/imx6q-udoo.dts | |||
| @@ -16,6 +16,10 @@ | |||
| 16 | model = "Udoo i.MX6 Quad Board"; | 16 | model = "Udoo i.MX6 Quad Board"; |
| 17 | compatible = "udoo,imx6q-udoo", "fsl,imx6q"; | 17 | compatible = "udoo,imx6q-udoo", "fsl,imx6q"; |
| 18 | 18 | ||
| 19 | chosen { | ||
| 20 | stdout-path = &uart2; | ||
| 21 | }; | ||
| 22 | |||
| 19 | memory { | 23 | memory { |
| 20 | reg = <0x10000000 0x40000000>; | 24 | reg = <0x10000000 0x40000000>; |
| 21 | }; | 25 | }; |
| @@ -28,6 +32,18 @@ | |||
| 28 | status = "okay"; | 32 | status = "okay"; |
| 29 | }; | 33 | }; |
| 30 | 34 | ||
| 35 | &hdmi { | ||
| 36 | ddc-i2c-bus = <&i2c2>; | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | |||
| 40 | &i2c2 { | ||
| 41 | clock-frequency = <100000>; | ||
| 42 | pinctrl-names = "default"; | ||
| 43 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 44 | status = "okay"; | ||
| 45 | }; | ||
| 46 | |||
| 31 | &iomuxc { | 47 | &iomuxc { |
| 32 | imx6q-udoo { | 48 | imx6q-udoo { |
| 33 | pinctrl_enet: enetgrp { | 49 | pinctrl_enet: enetgrp { |
| @@ -51,6 +67,13 @@ | |||
| 51 | >; | 67 | >; |
| 52 | }; | 68 | }; |
| 53 | 69 | ||
| 70 | pinctrl_i2c2: i2c2grp { | ||
| 71 | fsl,pins = < | ||
| 72 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | ||
| 73 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 74 | >; | ||
| 75 | }; | ||
| 76 | |||
| 54 | pinctrl_uart2: uart2grp { | 77 | pinctrl_uart2: uart2grp { |
| 55 | fsl,pins = < | 78 | fsl,pins = < |
| 56 | MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 | 79 | MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 |
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi index c2a24888a276..25da82a03110 100644 --- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi | |||
| @@ -55,6 +55,20 @@ | |||
| 55 | }; | 55 | }; |
| 56 | }; | 56 | }; |
| 57 | 57 | ||
| 58 | &hdmi { | ||
| 59 | pinctrl-names = "default"; | ||
| 60 | pinctrl-0 = <&pinctrl_cubox_i_hdmi>; | ||
| 61 | ddc-i2c-bus = <&i2c2>; | ||
| 62 | status = "okay"; | ||
| 63 | }; | ||
| 64 | |||
| 65 | &i2c2 { | ||
| 66 | clock-frequency = <100000>; | ||
| 67 | pinctrl-names = "default"; | ||
| 68 | pinctrl-0 = <&pinctrl_cubox_i_i2c2>; | ||
| 69 | status = "okay"; | ||
| 70 | }; | ||
| 71 | |||
| 58 | &i2c3 { | 72 | &i2c3 { |
| 59 | pinctrl-names = "default"; | 73 | pinctrl-names = "default"; |
| 60 | pinctrl-0 = <&pinctrl_cubox_i_i2c3>; | 74 | pinctrl-0 = <&pinctrl_cubox_i_i2c3>; |
| @@ -69,6 +83,19 @@ | |||
| 69 | 83 | ||
| 70 | &iomuxc { | 84 | &iomuxc { |
| 71 | cubox_i { | 85 | cubox_i { |
| 86 | pinctrl_cubox_i_hdmi: cubox-i-hdmi { | ||
| 87 | fsl,pins = < | ||
| 88 | MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 | ||
| 89 | >; | ||
| 90 | }; | ||
| 91 | |||
| 92 | pinctrl_cubox_i_i2c2: cubox-i-i2c2 { | ||
| 93 | fsl,pins = < | ||
| 94 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | ||
| 95 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 96 | >; | ||
| 97 | }; | ||
| 98 | |||
| 72 | pinctrl_cubox_i_i2c3: cubox-i-i2c3 { | 99 | pinctrl_cubox_i_i2c3: cubox-i-i2c3 { |
| 73 | fsl,pins = < | 100 | fsl,pins = < |
| 74 | MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 | 101 | MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 |
diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi index 25cf035dd36e..2c253d6d20bd 100644 --- a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | |||
| @@ -22,7 +22,7 @@ | |||
| 22 | }; | 22 | }; |
| 23 | 23 | ||
| 24 | chosen { | 24 | chosen { |
| 25 | linux,stdout-path = &uart1; | 25 | stdout-path = &uart1; |
| 26 | }; | 26 | }; |
| 27 | }; | 27 | }; |
| 28 | 28 | ||
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index 98a422153ce7..31665adcbf39 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | |||
| @@ -101,6 +101,11 @@ | |||
| 101 | status = "okay"; | 101 | status = "okay"; |
| 102 | }; | 102 | }; |
| 103 | 103 | ||
| 104 | &hdmi { | ||
| 105 | ddc-i2c-bus = <&i2c3>; | ||
| 106 | status = "okay"; | ||
| 107 | }; | ||
| 108 | |||
| 104 | &i2c1 { | 109 | &i2c1 { |
| 105 | clock-frequency = <100000>; | 110 | clock-frequency = <100000>; |
| 106 | pinctrl-names = "default"; | 111 | pinctrl-names = "default"; |
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 035d3a85c318..367af3ec9435 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | |||
| @@ -27,6 +27,13 @@ | |||
| 27 | bootargs = "console=ttymxc1,115200"; | 27 | bootargs = "console=ttymxc1,115200"; |
| 28 | }; | 28 | }; |
| 29 | 29 | ||
| 30 | backlight { | ||
| 31 | compatible = "pwm-backlight"; | ||
| 32 | pwms = <&pwm4 0 5000000>; | ||
| 33 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
| 34 | default-brightness-level = <7>; | ||
| 35 | }; | ||
| 36 | |||
| 30 | leds { | 37 | leds { |
| 31 | compatible = "gpio-leds"; | 38 | compatible = "gpio-leds"; |
| 32 | 39 | ||
| @@ -148,6 +155,11 @@ | |||
| 148 | status = "okay"; | 155 | status = "okay"; |
| 149 | }; | 156 | }; |
| 150 | 157 | ||
| 158 | &hdmi { | ||
| 159 | ddc-i2c-bus = <&i2c3>; | ||
| 160 | status = "okay"; | ||
| 161 | }; | ||
| 162 | |||
| 151 | &i2c1 { | 163 | &i2c1 { |
| 152 | clock-frequency = <100000>; | 164 | clock-frequency = <100000>; |
| 153 | pinctrl-names = "default"; | 165 | pinctrl-names = "default"; |
| @@ -394,6 +406,12 @@ | |||
| 394 | >; | 406 | >; |
| 395 | }; | 407 | }; |
| 396 | 408 | ||
| 409 | pinctrl_pwm4: pwm4grp { | ||
| 410 | fsl,pins = < | ||
| 411 | MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 | ||
| 412 | >; | ||
| 413 | }; | ||
| 414 | |||
| 397 | pinctrl_uart1: uart1grp { | 415 | pinctrl_uart1: uart1grp { |
| 398 | fsl,pins = < | 416 | fsl,pins = < |
| 399 | MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 | 417 | MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 |
| @@ -436,6 +454,27 @@ | |||
| 436 | 454 | ||
| 437 | &ldb { | 455 | &ldb { |
| 438 | status = "okay"; | 456 | status = "okay"; |
| 457 | |||
| 458 | lvds-channel@0 { | ||
| 459 | fsl,data-mapping = "spwg"; | ||
| 460 | fsl,data-width = <18>; | ||
| 461 | status = "okay"; | ||
| 462 | |||
| 463 | display-timings { | ||
| 464 | native-mode = <&timing0>; | ||
| 465 | timing0: hsd100pxn1 { | ||
| 466 | clock-frequency = <65000000>; | ||
| 467 | hactive = <1024>; | ||
| 468 | vactive = <768>; | ||
| 469 | hback-porch = <220>; | ||
| 470 | hfront-porch = <40>; | ||
| 471 | vback-porch = <21>; | ||
| 472 | vfront-porch = <7>; | ||
| 473 | hsync-len = <60>; | ||
| 474 | vsync-len = <10>; | ||
| 475 | }; | ||
| 476 | }; | ||
| 477 | }; | ||
| 439 | }; | 478 | }; |
| 440 | 479 | ||
| 441 | &pcie { | 480 | &pcie { |
| @@ -443,6 +482,12 @@ | |||
| 443 | status = "okay"; | 482 | status = "okay"; |
| 444 | }; | 483 | }; |
| 445 | 484 | ||
| 485 | &pwm4 { | ||
| 486 | pinctrl-names = "default"; | ||
| 487 | pinctrl-0 = <&pinctrl_pwm4>; | ||
| 488 | status = "okay"; | ||
| 489 | }; | ||
| 490 | |||
| 446 | &ssi1 { | 491 | &ssi1 { |
| 447 | fsl,mode = "i2s-slave"; | 492 | fsl,mode = "i2s-slave"; |
| 448 | status = "okay"; | 493 | status = "okay"; |
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index c8e5ae06deaf..c91b5a6c769b 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | |||
| @@ -30,6 +30,13 @@ | |||
| 30 | bootargs = "console=ttymxc1,115200"; | 30 | bootargs = "console=ttymxc1,115200"; |
| 31 | }; | 31 | }; |
| 32 | 32 | ||
| 33 | backlight { | ||
| 34 | compatible = "pwm-backlight"; | ||
| 35 | pwms = <&pwm4 0 5000000>; | ||
| 36 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
| 37 | default-brightness-level = <7>; | ||
| 38 | }; | ||
| 39 | |||
| 33 | leds { | 40 | leds { |
| 34 | compatible = "gpio-leds"; | 41 | compatible = "gpio-leds"; |
| 35 | 42 | ||
| @@ -157,6 +164,11 @@ | |||
| 157 | status = "okay"; | 164 | status = "okay"; |
| 158 | }; | 165 | }; |
| 159 | 166 | ||
| 167 | &hdmi { | ||
| 168 | ddc-i2c-bus = <&i2c3>; | ||
| 169 | status = "okay"; | ||
| 170 | }; | ||
| 171 | |||
| 160 | &i2c1 { | 172 | &i2c1 { |
| 161 | clock-frequency = <100000>; | 173 | clock-frequency = <100000>; |
| 162 | pinctrl-names = "default"; | 174 | pinctrl-names = "default"; |
| @@ -434,6 +446,12 @@ | |||
| 434 | >; | 446 | >; |
| 435 | }; | 447 | }; |
| 436 | 448 | ||
| 449 | pinctrl_pwm4: pwm4grp { | ||
| 450 | fsl,pins = < | ||
| 451 | MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 | ||
| 452 | >; | ||
| 453 | }; | ||
| 454 | |||
| 437 | pinctrl_uart1: uart1grp { | 455 | pinctrl_uart1: uart1grp { |
| 438 | fsl,pins = < | 456 | fsl,pins = < |
| 439 | MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 | 457 | MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 |
| @@ -508,6 +526,12 @@ | |||
| 508 | }; | 526 | }; |
| 509 | }; | 527 | }; |
| 510 | 528 | ||
| 529 | &pwm4 { | ||
| 530 | pinctrl-names = "default"; | ||
| 531 | pinctrl-0 = <&pinctrl_pwm4>; | ||
| 532 | status = "okay"; | ||
| 533 | }; | ||
| 534 | |||
| 511 | &ssi1 { | 535 | &ssi1 { |
| 512 | fsl,mode = "i2s-slave"; | 536 | fsl,mode = "i2s-slave"; |
| 513 | status = "okay"; | 537 | status = "okay"; |
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 2795dfc8c926..698d3063b295 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | |||
| @@ -30,6 +30,13 @@ | |||
| 30 | bootargs = "console=ttymxc1,115200"; | 30 | bootargs = "console=ttymxc1,115200"; |
| 31 | }; | 31 | }; |
| 32 | 32 | ||
| 33 | backlight { | ||
| 34 | compatible = "pwm-backlight"; | ||
| 35 | pwms = <&pwm4 0 5000000>; | ||
| 36 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
| 37 | default-brightness-level = <7>; | ||
| 38 | }; | ||
| 39 | |||
| 33 | leds { | 40 | leds { |
| 34 | compatible = "gpio-leds"; | 41 | compatible = "gpio-leds"; |
| 35 | 42 | ||
| @@ -147,6 +154,11 @@ | |||
| 147 | status = "okay"; | 154 | status = "okay"; |
| 148 | }; | 155 | }; |
| 149 | 156 | ||
| 157 | &hdmi { | ||
| 158 | ddc-i2c-bus = <&i2c3>; | ||
| 159 | status = "okay"; | ||
| 160 | }; | ||
| 161 | |||
| 150 | &i2c1 { | 162 | &i2c1 { |
| 151 | clock-frequency = <100000>; | 163 | clock-frequency = <100000>; |
| 152 | pinctrl-names = "default"; | 164 | pinctrl-names = "default"; |
| @@ -456,6 +468,12 @@ | |||
| 456 | >; | 468 | >; |
| 457 | }; | 469 | }; |
| 458 | 470 | ||
| 471 | pinctrl_pwm4: pwm4grp { | ||
| 472 | fsl,pins = < | ||
| 473 | MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 | ||
| 474 | >; | ||
| 475 | }; | ||
| 476 | |||
| 459 | pinctrl_uart1: uart1grp { | 477 | pinctrl_uart1: uart1grp { |
| 460 | fsl,pins = < | 478 | fsl,pins = < |
| 461 | MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 | 479 | MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 |
| @@ -530,6 +548,12 @@ | |||
| 530 | }; | 548 | }; |
| 531 | }; | 549 | }; |
| 532 | 550 | ||
| 551 | &pwm4 { | ||
| 552 | pinctrl-names = "default"; | ||
| 553 | pinctrl-0 = <&pinctrl_pwm4>; | ||
| 554 | status = "okay"; | ||
| 555 | }; | ||
| 556 | |||
| 533 | &ssi1 { | 557 | &ssi1 { |
| 534 | fsl,mode = "i2s-slave"; | 558 | fsl,mode = "i2s-slave"; |
| 535 | status = "okay"; | 559 | status = "okay"; |
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 99be301b5232..4c4b17596c8b 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | |||
| @@ -14,6 +14,10 @@ | |||
| 14 | #include <dt-bindings/input/input.h> | 14 | #include <dt-bindings/input/input.h> |
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | chosen { | ||
| 18 | stdout-path = &uart2; | ||
| 19 | }; | ||
| 20 | |||
| 17 | memory { | 21 | memory { |
| 18 | reg = <0x10000000 0x40000000>; | 22 | reg = <0x10000000 0x40000000>; |
| 19 | }; | 23 | }; |
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi new file mode 100644 index 000000000000..584721264121 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi | |||
| @@ -0,0 +1,102 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | / { | ||
| 13 | chosen { | ||
| 14 | linux,stdout-path = &uart4; | ||
| 15 | }; | ||
| 16 | }; | ||
| 17 | |||
| 18 | &fec { | ||
| 19 | status = "okay"; | ||
| 20 | }; | ||
| 21 | |||
| 22 | &gpmi { | ||
| 23 | status = "okay"; | ||
| 24 | }; | ||
| 25 | |||
| 26 | &hdmi { | ||
| 27 | status = "okay"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | &i2c2 { | ||
| 31 | pinctrl-names = "default"; | ||
| 32 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 33 | clock-frequency = <100000>; | ||
| 34 | status = "okay"; | ||
| 35 | |||
| 36 | tlv320@18 { | ||
| 37 | compatible = "ti,tlv320aic3x"; | ||
| 38 | reg = <0x18>; | ||
| 39 | }; | ||
| 40 | |||
| 41 | stmpe@41 { | ||
| 42 | compatible = "st,stmpe811"; | ||
| 43 | reg = <0x41>; | ||
| 44 | }; | ||
| 45 | |||
| 46 | rtc@51 { | ||
| 47 | compatible = "nxp,rtc8564"; | ||
| 48 | reg = <0x51>; | ||
| 49 | }; | ||
| 50 | |||
| 51 | adc@64 { | ||
| 52 | compatible = "maxim,max1037"; | ||
| 53 | reg = <0x64>; | ||
| 54 | }; | ||
| 55 | }; | ||
| 56 | |||
| 57 | &i2c3 { | ||
| 58 | pinctrl-names = "default"; | ||
| 59 | pinctrl-0 = <&pinctrl_i2c3>; | ||
| 60 | clock-frequency = <100000>; | ||
| 61 | status = "okay"; | ||
| 62 | }; | ||
| 63 | |||
| 64 | &uart3 { | ||
| 65 | status = "okay"; | ||
| 66 | }; | ||
| 67 | |||
| 68 | &uart4 { | ||
| 69 | status = "okay"; | ||
| 70 | }; | ||
| 71 | |||
| 72 | &usbh1 { | ||
| 73 | status = "okay"; | ||
| 74 | }; | ||
| 75 | |||
| 76 | &usbotg { | ||
| 77 | status = "okay"; | ||
| 78 | }; | ||
| 79 | |||
| 80 | &usdhc2 { | ||
| 81 | status = "okay"; | ||
| 82 | }; | ||
| 83 | |||
| 84 | &usdhc3 { | ||
| 85 | status = "okay"; | ||
| 86 | }; | ||
| 87 | |||
| 88 | &iomuxc { | ||
| 89 | pinctrl_i2c2: i2c2grp { | ||
| 90 | fsl,pins = < | ||
| 91 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | ||
| 92 | MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 | ||
| 93 | >; | ||
| 94 | }; | ||
| 95 | |||
| 96 | pinctrl_i2c3: i2c3grp { | ||
| 97 | fsl,pins = < | ||
| 98 | MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 | ||
| 99 | MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | ||
| 100 | >; | ||
| 101 | }; | ||
| 102 | }; | ||
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi new file mode 100644 index 000000000000..faa3494a69d4 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | |||
| @@ -0,0 +1,356 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <dt-bindings/gpio/gpio.h> | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "Phytec phyFLEX-i.MX6 Ouad"; | ||
| 16 | compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; | ||
| 17 | |||
| 18 | memory { | ||
| 19 | reg = <0x10000000 0x80000000>; | ||
| 20 | }; | ||
| 21 | |||
| 22 | regulators { | ||
| 23 | compatible = "simple-bus"; | ||
| 24 | #address-cells = <1>; | ||
| 25 | #size-cells = <0>; | ||
| 26 | |||
| 27 | reg_usb_otg_vbus: regulator@0 { | ||
| 28 | compatible = "regulator-fixed"; | ||
| 29 | reg = <0>; | ||
| 30 | regulator-name = "usb_otg_vbus"; | ||
| 31 | regulator-min-microvolt = <5000000>; | ||
| 32 | regulator-max-microvolt = <5000000>; | ||
| 33 | gpio = <&gpio4 15 0>; | ||
| 34 | }; | ||
| 35 | |||
| 36 | reg_usb_h1_vbus: regulator@1 { | ||
| 37 | compatible = "regulator-fixed"; | ||
| 38 | reg = <1>; | ||
| 39 | regulator-name = "usb_h1_vbus"; | ||
| 40 | regulator-min-microvolt = <5000000>; | ||
| 41 | regulator-max-microvolt = <5000000>; | ||
| 42 | gpio = <&gpio1 0 0>; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | |||
| 46 | gpio_leds: leds { | ||
| 47 | compatible = "gpio-leds"; | ||
| 48 | |||
| 49 | green { | ||
| 50 | label = "phyflex:green"; | ||
| 51 | gpios = <&gpio1 30 0>; | ||
| 52 | }; | ||
| 53 | |||
| 54 | red { | ||
| 55 | label = "phyflex:red"; | ||
| 56 | gpios = <&gpio2 31 0>; | ||
| 57 | }; | ||
| 58 | }; | ||
| 59 | }; | ||
| 60 | |||
| 61 | &ecspi3 { | ||
| 62 | pinctrl-names = "default"; | ||
| 63 | pinctrl-0 = <&pinctrl_ecspi3>; | ||
| 64 | status = "okay"; | ||
| 65 | fsl,spi-num-chipselects = <1>; | ||
| 66 | cs-gpios = <&gpio4 24 0>; | ||
| 67 | |||
| 68 | flash@0 { | ||
| 69 | compatible = "m25p80"; | ||
| 70 | spi-max-frequency = <20000000>; | ||
| 71 | reg = <0>; | ||
| 72 | }; | ||
| 73 | }; | ||
| 74 | |||
| 75 | &i2c1 { | ||
| 76 | pinctrl-names = "default"; | ||
| 77 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 78 | status = "okay"; | ||
| 79 | |||
| 80 | eeprom@50 { | ||
| 81 | compatible = "atmel,24c32"; | ||
| 82 | reg = <0x50>; | ||
| 83 | }; | ||
| 84 | |||
| 85 | pmic@58 { | ||
| 86 | compatible = "dialog,da9063"; | ||
| 87 | reg = <0x58>; | ||
| 88 | interrupt-parent = <&gpio4>; | ||
| 89 | interrupts = <17 0x8>; /* active-low GPIO4_17 */ | ||
| 90 | |||
| 91 | regulators { | ||
| 92 | vddcore_reg: bcore1 { | ||
| 93 | regulator-min-microvolt = <730000>; | ||
| 94 | regulator-max-microvolt = <1380000>; | ||
| 95 | regulator-always-on; | ||
| 96 | }; | ||
| 97 | |||
| 98 | vddsoc_reg: bcore2 { | ||
| 99 | regulator-min-microvolt = <730000>; | ||
| 100 | regulator-max-microvolt = <1380000>; | ||
| 101 | regulator-always-on; | ||
| 102 | }; | ||
| 103 | |||
| 104 | vdd_ddr3_reg: bpro { | ||
| 105 | regulator-min-microvolt = <1500000>; | ||
| 106 | regulator-max-microvolt = <1500000>; | ||
| 107 | regulator-always-on; | ||
| 108 | }; | ||
| 109 | |||
| 110 | vdd_3v3_reg: bperi { | ||
| 111 | regulator-min-microvolt = <3300000>; | ||
| 112 | regulator-max-microvolt = <3300000>; | ||
| 113 | regulator-always-on; | ||
| 114 | }; | ||
| 115 | |||
| 116 | vdd_buckmem_reg: bmem { | ||
| 117 | regulator-min-microvolt = <3300000>; | ||
| 118 | regulator-max-microvolt = <3300000>; | ||
| 119 | regulator-always-on; | ||
| 120 | }; | ||
| 121 | |||
| 122 | vdd_eth_reg: bio { | ||
| 123 | regulator-min-microvolt = <1200000>; | ||
| 124 | regulator-max-microvolt = <1200000>; | ||
| 125 | regulator-always-on; | ||
| 126 | }; | ||
| 127 | |||
| 128 | vdd_eth_io_reg: ldo4 { | ||
| 129 | regulator-min-microvolt = <2500000>; | ||
| 130 | regulator-max-microvolt = <2500000>; | ||
| 131 | regulator-always-on; | ||
| 132 | }; | ||
| 133 | |||
| 134 | vdd_mx6_snvs_reg: ldo5 { | ||
| 135 | regulator-min-microvolt = <3000000>; | ||
| 136 | regulator-max-microvolt = <3000000>; | ||
| 137 | regulator-always-on; | ||
| 138 | }; | ||
| 139 | |||
| 140 | vdd_3v3_pmic_io_reg: ldo6 { | ||
| 141 | regulator-min-microvolt = <3300000>; | ||
| 142 | regulator-max-microvolt = <3300000>; | ||
| 143 | regulator-always-on; | ||
| 144 | }; | ||
| 145 | |||
| 146 | vdd_sd0_reg: ldo9 { | ||
| 147 | regulator-min-microvolt = <3300000>; | ||
| 148 | regulator-max-microvolt = <3300000>; | ||
| 149 | }; | ||
| 150 | |||
| 151 | vdd_sd1_reg: ldo10 { | ||
| 152 | regulator-min-microvolt = <3300000>; | ||
| 153 | regulator-max-microvolt = <3300000>; | ||
| 154 | }; | ||
| 155 | |||
| 156 | vdd_mx6_high_reg: ldo11 { | ||
| 157 | regulator-min-microvolt = <3000000>; | ||
| 158 | regulator-max-microvolt = <3000000>; | ||
| 159 | regulator-always-on; | ||
| 160 | }; | ||
| 161 | }; | ||
| 162 | }; | ||
| 163 | }; | ||
| 164 | |||
| 165 | &iomuxc { | ||
| 166 | pinctrl-names = "default"; | ||
| 167 | pinctrl-0 = <&pinctrl_hog>; | ||
| 168 | |||
| 169 | imx6q-phytec-pfla02 { | ||
| 170 | pinctrl_hog: hoggrp { | ||
| 171 | fsl,pins = < | ||
| 172 | MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 | ||
| 173 | MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ | ||
| 174 | MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ | ||
| 175 | MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ | ||
| 176 | MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ | ||
| 177 | >; | ||
| 178 | }; | ||
| 179 | |||
| 180 | pinctrl_ecspi3: ecspi3grp { | ||
| 181 | fsl,pins = < | ||
| 182 | MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 | ||
| 183 | MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 | ||
| 184 | MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 | ||
| 185 | >; | ||
| 186 | }; | ||
| 187 | |||
| 188 | pinctrl_enet: enetgrp { | ||
| 189 | fsl,pins = < | ||
| 190 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 191 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 192 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 193 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 194 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 195 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 196 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 197 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 198 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 199 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 200 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 201 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 202 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 203 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 204 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 205 | MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 | ||
| 206 | >; | ||
| 207 | }; | ||
| 208 | |||
| 209 | pinctrl_gpmi_nand: gpminandgrp { | ||
| 210 | fsl,pins = < | ||
| 211 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 212 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 213 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 214 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 215 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 216 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 217 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 218 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 219 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 220 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 221 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 222 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 223 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 224 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 225 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 226 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 227 | MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 | ||
| 228 | >; | ||
| 229 | }; | ||
| 230 | |||
| 231 | pinctrl_i2c1: i2c1grp { | ||
| 232 | fsl,pins = < | ||
| 233 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | ||
| 234 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | ||
| 235 | >; | ||
| 236 | }; | ||
| 237 | |||
| 238 | pinctrl_uart3: uart3grp { | ||
| 239 | fsl,pins = < | ||
| 240 | MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 | ||
| 241 | MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 | ||
| 242 | MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 | ||
| 243 | MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 | ||
| 244 | >; | ||
| 245 | }; | ||
| 246 | |||
| 247 | pinctrl_uart4: uart4grp { | ||
| 248 | fsl,pins = < | ||
| 249 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | ||
| 250 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | ||
| 251 | >; | ||
| 252 | }; | ||
| 253 | |||
| 254 | pinctrl_usbh1: usbh1grp { | ||
| 255 | fsl,pins = < | ||
| 256 | MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000 | ||
| 257 | >; | ||
| 258 | }; | ||
| 259 | |||
| 260 | pinctrl_usbotg: usbotggrp { | ||
| 261 | fsl,pins = < | ||
| 262 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 263 | MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 | ||
| 264 | MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 | ||
| 265 | >; | ||
| 266 | }; | ||
| 267 | |||
| 268 | pinctrl_usdhc2: usdhc2grp { | ||
| 269 | fsl,pins = < | ||
| 270 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 271 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 272 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 273 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 274 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 275 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 276 | >; | ||
| 277 | }; | ||
| 278 | |||
| 279 | pinctrl_usdhc3: usdhc3grp { | ||
| 280 | fsl,pins = < | ||
| 281 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 282 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 283 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 284 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 285 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 286 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 287 | >; | ||
| 288 | }; | ||
| 289 | |||
| 290 | pinctrl_usdhc3_cdwp: usdhc3cdwp { | ||
| 291 | fsl,pins = < | ||
| 292 | MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 | ||
| 293 | MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 | ||
| 294 | >; | ||
| 295 | }; | ||
| 296 | }; | ||
| 297 | }; | ||
| 298 | |||
| 299 | &fec { | ||
| 300 | pinctrl-names = "default"; | ||
| 301 | pinctrl-0 = <&pinctrl_enet>; | ||
| 302 | phy-mode = "rgmii"; | ||
| 303 | phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; | ||
| 304 | status = "disabled"; | ||
| 305 | }; | ||
| 306 | |||
| 307 | &gpmi { | ||
| 308 | pinctrl-names = "default"; | ||
| 309 | pinctrl-0 = <&pinctrl_gpmi_nand>; | ||
| 310 | nand-on-flash-bbt; | ||
| 311 | status = "disabled"; | ||
| 312 | }; | ||
| 313 | |||
| 314 | &uart3 { | ||
| 315 | pinctrl-names = "default"; | ||
| 316 | pinctrl-0 = <&pinctrl_uart3>; | ||
| 317 | status = "disabled"; | ||
| 318 | }; | ||
| 319 | |||
| 320 | &uart4 { | ||
| 321 | pinctrl-names = "default"; | ||
| 322 | pinctrl-0 = <&pinctrl_uart4>; | ||
| 323 | status = "disabled"; | ||
| 324 | }; | ||
| 325 | |||
| 326 | &usbh1 { | ||
| 327 | vbus-supply = <®_usb_h1_vbus>; | ||
| 328 | pinctrl-names = "default"; | ||
| 329 | pinctrl-0 = <&pinctrl_usbh1>; | ||
| 330 | status = "disabled"; | ||
| 331 | }; | ||
| 332 | |||
| 333 | &usbotg { | ||
| 334 | vbus-supply = <®_usb_otg_vbus>; | ||
| 335 | pinctrl-names = "default"; | ||
| 336 | pinctrl-0 = <&pinctrl_usbotg>; | ||
| 337 | disable-over-current; | ||
| 338 | status = "disabled"; | ||
| 339 | }; | ||
| 340 | |||
| 341 | &usdhc2 { | ||
| 342 | pinctrl-names = "default"; | ||
| 343 | pinctrl-0 = <&pinctrl_usdhc2>; | ||
| 344 | cd-gpios = <&gpio1 4 0>; | ||
| 345 | wp-gpios = <&gpio1 2 0>; | ||
| 346 | status = "disabled"; | ||
| 347 | }; | ||
| 348 | |||
| 349 | &usdhc3 { | ||
| 350 | pinctrl-names = "default"; | ||
| 351 | pinctrl-0 = <&pinctrl_usdhc3 | ||
| 352 | &pinctrl_usdhc3_cdwp>; | ||
| 353 | cd-gpios = <&gpio1 27 0>; | ||
| 354 | wp-gpios = <&gpio1 29 0>; | ||
| 355 | status = "disabled"; | ||
| 356 | }; | ||
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 3bec128c7971..6df6127bf835 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | |||
| @@ -13,6 +13,10 @@ | |||
| 13 | #include <dt-bindings/input/input.h> | 13 | #include <dt-bindings/input/input.h> |
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | chosen { | ||
| 17 | stdout-path = &uart2; | ||
| 18 | }; | ||
| 19 | |||
| 16 | memory { | 20 | memory { |
| 17 | reg = <0x10000000 0x40000000>; | 21 | reg = <0x10000000 0x40000000>; |
| 18 | }; | 22 | }; |
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 0d816d3be4b6..40ea36534643 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi | |||
| @@ -14,6 +14,10 @@ | |||
| 14 | #include <dt-bindings/input/input.h> | 14 | #include <dt-bindings/input/input.h> |
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | chosen { | ||
| 18 | stdout-path = &uart1; | ||
| 19 | }; | ||
| 20 | |||
| 17 | memory { | 21 | memory { |
| 18 | reg = <0x10000000 0x40000000>; | 22 | reg = <0x10000000 0x40000000>; |
| 19 | }; | 23 | }; |
| @@ -105,6 +109,17 @@ | |||
| 105 | default-brightness-level = <7>; | 109 | default-brightness-level = <7>; |
| 106 | status = "okay"; | 110 | status = "okay"; |
| 107 | }; | 111 | }; |
| 112 | |||
| 113 | leds { | ||
| 114 | compatible = "gpio-leds"; | ||
| 115 | pinctrl-names = "default"; | ||
| 116 | pinctrl-0 = <&pinctrl_gpio_leds>; | ||
| 117 | |||
| 118 | red { | ||
| 119 | gpios = <&gpio1 2 0>; | ||
| 120 | default-state = "on"; | ||
| 121 | }; | ||
| 122 | }; | ||
| 108 | }; | 123 | }; |
| 109 | 124 | ||
| 110 | &audmux { | 125 | &audmux { |
| @@ -137,6 +152,11 @@ | |||
| 137 | status = "okay"; | 152 | status = "okay"; |
| 138 | }; | 153 | }; |
| 139 | 154 | ||
| 155 | &hdmi { | ||
| 156 | ddc-i2c-bus = <&i2c2>; | ||
| 157 | status = "okay"; | ||
| 158 | }; | ||
| 159 | |||
| 140 | &i2c1 { | 160 | &i2c1 { |
| 141 | clock-frequency = <100000>; | 161 | clock-frequency = <100000>; |
| 142 | pinctrl-names = "default"; | 162 | pinctrl-names = "default"; |
| @@ -373,6 +393,12 @@ | |||
| 373 | >; | 393 | >; |
| 374 | }; | 394 | }; |
| 375 | 395 | ||
| 396 | pinctrl_pcie: pciegrp { | ||
| 397 | fsl,pins = < | ||
| 398 | MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 | ||
| 399 | >; | ||
| 400 | }; | ||
| 401 | |||
| 376 | pinctrl_pwm1: pwm1grp { | 402 | pinctrl_pwm1: pwm1grp { |
| 377 | fsl,pins = < | 403 | fsl,pins = < |
| 378 | MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 | 404 | MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 |
| @@ -421,6 +447,29 @@ | |||
| 421 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 | 447 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 |
| 422 | >; | 448 | >; |
| 423 | }; | 449 | }; |
| 450 | |||
| 451 | pinctrl_usdhc4: usdhc4grp { | ||
| 452 | fsl,pins = < | ||
| 453 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 454 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 455 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 456 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 457 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 458 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 459 | MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 | ||
| 460 | MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 | ||
| 461 | MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 | ||
| 462 | MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 | ||
| 463 | >; | ||
| 464 | }; | ||
| 465 | }; | ||
| 466 | |||
| 467 | gpio_leds { | ||
| 468 | pinctrl_gpio_leds: gpioledsgrp { | ||
| 469 | fsl,pins = < | ||
| 470 | MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 | ||
| 471 | >; | ||
| 472 | }; | ||
| 424 | }; | 473 | }; |
| 425 | }; | 474 | }; |
| 426 | 475 | ||
| @@ -449,6 +498,13 @@ | |||
| 449 | }; | 498 | }; |
| 450 | }; | 499 | }; |
| 451 | 500 | ||
| 501 | &pcie { | ||
| 502 | pinctrl-names = "default"; | ||
| 503 | pinctrl-0 = <&pinctrl_pcie>; | ||
| 504 | reset-gpio = <&gpio7 12 0>; | ||
| 505 | status = "okay"; | ||
| 506 | }; | ||
| 507 | |||
| 452 | &pwm1 { | 508 | &pwm1 { |
| 453 | pinctrl-names = "default"; | 509 | pinctrl-names = "default"; |
| 454 | pinctrl-0 = <&pinctrl_pwm1>; | 510 | pinctrl-0 = <&pinctrl_pwm1>; |
| @@ -496,3 +552,12 @@ | |||
| 496 | wp-gpios = <&gpio2 1 0>; | 552 | wp-gpios = <&gpio2 1 0>; |
| 497 | status = "okay"; | 553 | status = "okay"; |
| 498 | }; | 554 | }; |
| 555 | |||
| 556 | &usdhc4 { | ||
| 557 | pinctrl-names = "default"; | ||
| 558 | pinctrl-0 = <&pinctrl_usdhc4>; | ||
| 559 | bus-width = <8>; | ||
| 560 | non-removable; | ||
| 561 | no-1-8-v; | ||
| 562 | status = "okay"; | ||
| 563 | }; | ||
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index bdfdf89d405f..5c6f10c43f65 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi | |||
| @@ -62,6 +62,18 @@ | |||
| 62 | status = "okay"; | 62 | status = "okay"; |
| 63 | }; | 63 | }; |
| 64 | 64 | ||
| 65 | &hdmi { | ||
| 66 | ddc-i2c-bus = <&i2c1>; | ||
| 67 | status = "okay"; | ||
| 68 | }; | ||
| 69 | |||
| 70 | &i2c1 { | ||
| 71 | clock-frequency = <100000>; | ||
| 72 | pinctrl-names = "default"; | ||
| 73 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 74 | status = "okay"; | ||
| 75 | }; | ||
| 76 | |||
| 65 | &i2c2 { | 77 | &i2c2 { |
| 66 | clock-frequency = <100000>; | 78 | clock-frequency = <100000>; |
| 67 | pinctrl-names = "default"; | 79 | pinctrl-names = "default"; |
| @@ -127,6 +139,13 @@ | |||
| 127 | >; | 139 | >; |
| 128 | }; | 140 | }; |
| 129 | 141 | ||
| 142 | pinctrl_i2c1: i2c1grp { | ||
| 143 | fsl,pins = < | ||
| 144 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | ||
| 145 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | ||
| 146 | >; | ||
| 147 | }; | ||
| 148 | |||
| 130 | pinctrl_i2c2: i2c2grp { | 149 | pinctrl_i2c2: i2c2grp { |
| 131 | fsl,pins = < | 150 | fsl,pins = < |
| 132 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | 151 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 |
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index eca0971d4db1..ce0599134a69 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | 16 | ||
| 17 | / { | 17 | / { |
| 18 | aliases { | 18 | aliases { |
| 19 | ethernet0 = &fec; | ||
| 19 | can0 = &can1; | 20 | can0 = &can1; |
| 20 | can1 = &can2; | 21 | can1 = &can2; |
| 21 | gpio0 = &gpio1; | 22 | gpio0 = &gpio1; |
| @@ -140,15 +141,16 @@ | |||
| 140 | 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ | 141 | 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ |
| 141 | 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ | 142 | 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ |
| 142 | num-lanes = <1>; | 143 | num-lanes = <1>; |
| 143 | interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>; | 144 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
| 145 | interrupt-names = "msi"; | ||
| 144 | #interrupt-cells = <1>; | 146 | #interrupt-cells = <1>; |
| 145 | interrupt-map-mask = <0 0 0 0x7>; | 147 | interrupt-map-mask = <0 0 0 0x7>; |
| 146 | interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | 148 | interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
| 147 | <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | 149 | <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, |
| 148 | <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | 150 | <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 149 | <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | 151 | <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
| 150 | clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; | 152 | clocks = <&clks 144>, <&clks 206>, <&clks 189>; |
| 151 | clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; | 153 | clock-names = "pcie", "pcie_bus", "pcie_phy"; |
| 152 | status = "disabled"; | 154 | status = "disabled"; |
| 153 | }; | 155 | }; |
| 154 | 156 | ||
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index d26b099260a3..2d4e5285f3f3 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | aliases { | 16 | aliases { |
| 17 | ethernet0 = &fec; | ||
| 17 | gpio0 = &gpio1; | 18 | gpio0 = &gpio1; |
| 18 | gpio1 = &gpio2; | 19 | gpio1 = &gpio2; |
| 19 | gpio2 = &gpio3; | 20 | gpio2 = &gpio3; |
diff --git a/arch/arm/boot/dts/k2e-evm.dts b/arch/arm/boot/dts/k2e-evm.dts index 74b3b63e94cf..c568f067604d 100644 --- a/arch/arm/boot/dts/k2e-evm.dts +++ b/arch/arm/boot/dts/k2e-evm.dts | |||
| @@ -58,3 +58,84 @@ | |||
| 58 | &usb1 { | 58 | &usb1 { |
| 59 | status = "okay"; | 59 | status = "okay"; |
| 60 | }; | 60 | }; |
| 61 | |||
| 62 | &i2c0 { | ||
| 63 | dtt@50 { | ||
| 64 | compatible = "at,24c1024"; | ||
| 65 | reg = <0x50>; | ||
| 66 | }; | ||
| 67 | }; | ||
| 68 | |||
| 69 | &aemif { | ||
| 70 | cs0 { | ||
| 71 | #address-cells = <2>; | ||
| 72 | #size-cells = <1>; | ||
| 73 | clock-ranges; | ||
| 74 | ranges; | ||
| 75 | |||
| 76 | ti,cs-chipselect = <0>; | ||
| 77 | /* all timings in nanoseconds */ | ||
| 78 | ti,cs-min-turnaround-ns = <12>; | ||
| 79 | ti,cs-read-hold-ns = <6>; | ||
| 80 | ti,cs-read-strobe-ns = <23>; | ||
| 81 | ti,cs-read-setup-ns = <9>; | ||
| 82 | ti,cs-write-hold-ns = <8>; | ||
| 83 | ti,cs-write-strobe-ns = <23>; | ||
| 84 | ti,cs-write-setup-ns = <8>; | ||
| 85 | |||
| 86 | nand@0,0 { | ||
| 87 | compatible = "ti,keystone-nand","ti,davinci-nand"; | ||
| 88 | #address-cells = <1>; | ||
| 89 | #size-cells = <1>; | ||
| 90 | reg = <0 0 0x4000000 | ||
| 91 | 1 0 0x0000100>; | ||
| 92 | |||
| 93 | ti,davinci-chipselect = <0>; | ||
| 94 | ti,davinci-mask-ale = <0x2000>; | ||
| 95 | ti,davinci-mask-cle = <0x4000>; | ||
| 96 | ti,davinci-mask-chipsel = <0>; | ||
| 97 | nand-ecc-mode = "hw"; | ||
| 98 | ti,davinci-ecc-bits = <4>; | ||
| 99 | nand-on-flash-bbt; | ||
| 100 | |||
| 101 | partition@0 { | ||
| 102 | label = "u-boot"; | ||
| 103 | reg = <0x0 0x100000>; | ||
| 104 | read-only; | ||
| 105 | }; | ||
| 106 | |||
| 107 | partition@100000 { | ||
| 108 | label = "params"; | ||
| 109 | reg = <0x100000 0x80000>; | ||
| 110 | read-only; | ||
| 111 | }; | ||
| 112 | |||
| 113 | partition@180000 { | ||
| 114 | label = "ubifs"; | ||
| 115 | reg = <0x180000 0x1FE80000>; | ||
| 116 | }; | ||
| 117 | }; | ||
| 118 | }; | ||
| 119 | }; | ||
| 120 | |||
| 121 | &spi0 { | ||
| 122 | nor_flash: n25q128a11@0 { | ||
| 123 | #address-cells = <1>; | ||
| 124 | #size-cells = <1>; | ||
| 125 | compatible = "Micron,n25q128a11"; | ||
| 126 | spi-max-frequency = <54000000>; | ||
| 127 | m25p,fast-read; | ||
| 128 | reg = <0>; | ||
| 129 | |||
| 130 | partition@0 { | ||
| 131 | label = "u-boot-spl"; | ||
| 132 | reg = <0x0 0x80000>; | ||
| 133 | read-only; | ||
| 134 | }; | ||
| 135 | |||
| 136 | partition@1 { | ||
| 137 | label = "misc"; | ||
| 138 | reg = <0x80000 0xf80000>; | ||
| 139 | }; | ||
| 140 | }; | ||
| 141 | }; | ||
diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts index c93d06f9f2a8..1f90cbf27fd7 100644 --- a/arch/arm/boot/dts/k2hk-evm.dts +++ b/arch/arm/boot/dts/k2hk-evm.dts | |||
| @@ -138,3 +138,32 @@ | |||
| 138 | }; | 138 | }; |
| 139 | }; | 139 | }; |
| 140 | }; | 140 | }; |
| 141 | |||
| 142 | &i2c0 { | ||
| 143 | dtt@50 { | ||
| 144 | compatible = "at,24c1024"; | ||
| 145 | reg = <0x50>; | ||
| 146 | }; | ||
| 147 | }; | ||
| 148 | |||
| 149 | &spi0 { | ||
| 150 | nor_flash: n25q128a11@0 { | ||
| 151 | #address-cells = <1>; | ||
| 152 | #size-cells = <1>; | ||
| 153 | compatible = "Micron,n25q128a11"; | ||
| 154 | spi-max-frequency = <54000000>; | ||
| 155 | m25p,fast-read; | ||
| 156 | reg = <0>; | ||
| 157 | |||
| 158 | partition@0 { | ||
| 159 | label = "u-boot-spl"; | ||
| 160 | reg = <0x0 0x80000>; | ||
| 161 | read-only; | ||
| 162 | }; | ||
| 163 | |||
| 164 | partition@1 { | ||
| 165 | label = "misc"; | ||
| 166 | reg = <0x80000 0xf80000>; | ||
| 167 | }; | ||
| 168 | }; | ||
| 169 | }; | ||
diff --git a/arch/arm/boot/dts/k2l-evm.dts b/arch/arm/boot/dts/k2l-evm.dts index 50a70132ac9e..fec43128a2e0 100644 --- a/arch/arm/boot/dts/k2l-evm.dts +++ b/arch/arm/boot/dts/k2l-evm.dts | |||
| @@ -35,3 +35,84 @@ | |||
| 35 | &usb { | 35 | &usb { |
| 36 | status = "okay"; | 36 | status = "okay"; |
| 37 | }; | 37 | }; |
| 38 | |||
| 39 | &i2c0 { | ||
| 40 | dtt@50 { | ||
| 41 | compatible = "at,24c1024"; | ||
| 42 | reg = <0x50>; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | |||
| 46 | &aemif { | ||
| 47 | cs0 { | ||
| 48 | #address-cells = <2>; | ||
| 49 | #size-cells = <1>; | ||
| 50 | clock-ranges; | ||
| 51 | ranges; | ||
| 52 | |||
| 53 | ti,cs-chipselect = <0>; | ||
| 54 | /* all timings in nanoseconds */ | ||
| 55 | ti,cs-min-turnaround-ns = <12>; | ||
| 56 | ti,cs-read-hold-ns = <6>; | ||
| 57 | ti,cs-read-strobe-ns = <23>; | ||
| 58 | ti,cs-read-setup-ns = <9>; | ||
| 59 | ti,cs-write-hold-ns = <8>; | ||
| 60 | ti,cs-write-strobe-ns = <23>; | ||
| 61 | ti,cs-write-setup-ns = <8>; | ||
| 62 | |||
| 63 | nand@0,0 { | ||
| 64 | compatible = "ti,keystone-nand","ti,davinci-nand"; | ||
| 65 | #address-cells = <1>; | ||
| 66 | #size-cells = <1>; | ||
| 67 | reg = <0 0 0x4000000 | ||
| 68 | 1 0 0x0000100>; | ||
| 69 | |||
| 70 | ti,davinci-chipselect = <0>; | ||
| 71 | ti,davinci-mask-ale = <0x2000>; | ||
| 72 | ti,davinci-mask-cle = <0x4000>; | ||
| 73 | ti,davinci-mask-chipsel = <0>; | ||
| 74 | nand-ecc-mode = "hw"; | ||
| 75 | ti,davinci-ecc-bits = <4>; | ||
| 76 | nand-on-flash-bbt; | ||
| 77 | |||
| 78 | partition@0 { | ||
| 79 | label = "u-boot"; | ||
| 80 | reg = <0x0 0x100000>; | ||
| 81 | read-only; | ||
| 82 | }; | ||
| 83 | |||
| 84 | partition@100000 { | ||
| 85 | label = "params"; | ||
| 86 | reg = <0x100000 0x80000>; | ||
| 87 | read-only; | ||
| 88 | }; | ||
| 89 | |||
| 90 | partition@180000 { | ||
| 91 | label = "ubifs"; | ||
| 92 | reg = <0x180000 0x7FE80000>; | ||
| 93 | }; | ||
| 94 | }; | ||
| 95 | }; | ||
| 96 | }; | ||
| 97 | |||
| 98 | &spi0 { | ||
| 99 | nor_flash: n25q128a11@0 { | ||
| 100 | #address-cells = <1>; | ||
| 101 | #size-cells = <1>; | ||
| 102 | compatible = "Micron,n25q128a11"; | ||
| 103 | spi-max-frequency = <54000000>; | ||
| 104 | m25p,fast-read; | ||
| 105 | reg = <0>; | ||
| 106 | |||
| 107 | partition@0 { | ||
| 108 | label = "u-boot-spl"; | ||
| 109 | reg = <0x0 0x80000>; | ||
| 110 | read-only; | ||
| 111 | }; | ||
| 112 | |||
| 113 | partition@1 { | ||
| 114 | label = "misc"; | ||
| 115 | reg = <0x80000 0xf80000>; | ||
| 116 | }; | ||
| 117 | }; | ||
| 118 | }; | ||
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 90823eb90c1b..d9f99e7deb83 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi | |||
| @@ -28,8 +28,6 @@ | |||
| 28 | gic: interrupt-controller { | 28 | gic: interrupt-controller { |
| 29 | compatible = "arm,cortex-a15-gic"; | 29 | compatible = "arm,cortex-a15-gic"; |
| 30 | #interrupt-cells = <3>; | 30 | #interrupt-cells = <3>; |
| 31 | #size-cells = <0>; | ||
| 32 | #address-cells = <1>; | ||
| 33 | interrupt-controller; | 31 | interrupt-controller; |
| 34 | reg = <0x0 0x02561000 0x0 0x1000>, | 32 | reg = <0x0 0x02561000 0x0 0x1000>, |
| 35 | <0x0 0x02562000 0x0 0x2000>, | 33 | <0x0 0x02562000 0x0 0x2000>, |
| @@ -66,6 +64,7 @@ | |||
| 66 | compatible = "ti,keystone","simple-bus"; | 64 | compatible = "ti,keystone","simple-bus"; |
| 67 | interrupt-parent = <&gic>; | 65 | interrupt-parent = <&gic>; |
| 68 | ranges = <0x0 0x0 0x0 0xc0000000>; | 66 | ranges = <0x0 0x0 0x0 0xc0000000>; |
| 67 | dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; | ||
| 69 | 68 | ||
| 70 | rstctrl: reset-controller { | 69 | rstctrl: reset-controller { |
| 71 | compatible = "ti,keystone-reset"; | 70 | compatible = "ti,keystone-reset"; |
| @@ -102,11 +101,6 @@ | |||
| 102 | interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>; | 101 | interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>; |
| 103 | #address-cells = <1>; | 102 | #address-cells = <1>; |
| 104 | #size-cells = <0>; | 103 | #size-cells = <0>; |
| 105 | |||
| 106 | dtt@50 { | ||
| 107 | compatible = "at,24c1024"; | ||
| 108 | reg = <0x50>; | ||
| 109 | }; | ||
| 110 | }; | 104 | }; |
| 111 | 105 | ||
| 112 | i2c1: i2c@2530400 { | 106 | i2c1: i2c@2530400 { |
| @@ -115,6 +109,8 @@ | |||
| 115 | clock-frequency = <100000>; | 109 | clock-frequency = <100000>; |
| 116 | clocks = <&clki2c>; | 110 | clocks = <&clki2c>; |
| 117 | interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>; | 111 | interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>; |
| 112 | #address-cells = <1>; | ||
| 113 | #size-cells = <0>; | ||
| 118 | }; | 114 | }; |
| 119 | 115 | ||
| 120 | i2c2: i2c@2530800 { | 116 | i2c2: i2c@2530800 { |
| @@ -123,6 +119,8 @@ | |||
| 123 | clock-frequency = <100000>; | 119 | clock-frequency = <100000>; |
| 124 | clocks = <&clki2c>; | 120 | clocks = <&clki2c>; |
| 125 | interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; | 121 | interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; |
| 122 | #address-cells = <1>; | ||
| 123 | #size-cells = <0>; | ||
| 126 | }; | 124 | }; |
| 127 | 125 | ||
| 128 | spi0: spi@21000400 { | 126 | spi0: spi@21000400 { |
| @@ -132,6 +130,8 @@ | |||
| 132 | ti,davinci-spi-intr-line = <0>; | 130 | ti,davinci-spi-intr-line = <0>; |
| 133 | interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>; | 131 | interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>; |
| 134 | clocks = <&clkspi>; | 132 | clocks = <&clkspi>; |
| 133 | #address-cells = <1>; | ||
| 134 | #size-cells = <0>; | ||
| 135 | }; | 135 | }; |
| 136 | 136 | ||
| 137 | spi1: spi@21000600 { | 137 | spi1: spi@21000600 { |
| @@ -141,6 +141,8 @@ | |||
| 141 | ti,davinci-spi-intr-line = <0>; | 141 | ti,davinci-spi-intr-line = <0>; |
| 142 | interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>; | 142 | interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>; |
| 143 | clocks = <&clkspi>; | 143 | clocks = <&clkspi>; |
| 144 | #address-cells = <1>; | ||
| 145 | #size-cells = <0>; | ||
| 144 | }; | 146 | }; |
| 145 | 147 | ||
| 146 | spi2: spi@21000800 { | 148 | spi2: spi@21000800 { |
| @@ -150,6 +152,8 @@ | |||
| 150 | ti,davinci-spi-intr-line = <0>; | 152 | ti,davinci-spi-intr-line = <0>; |
| 151 | interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>; | 153 | interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>; |
| 152 | clocks = <&clkspi>; | 154 | clocks = <&clkspi>; |
| 155 | #address-cells = <1>; | ||
| 156 | #size-cells = <0>; | ||
| 153 | }; | 157 | }; |
| 154 | 158 | ||
| 155 | usb_phy: usb_phy@2620738 { | 159 | usb_phy: usb_phy@2620738 { |
| @@ -169,6 +173,8 @@ | |||
| 169 | clock-names = "usb"; | 173 | clock-names = "usb"; |
| 170 | interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; | 174 | interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; |
| 171 | ranges; | 175 | ranges; |
| 176 | dma-coherent; | ||
| 177 | dma-ranges; | ||
| 172 | status = "disabled"; | 178 | status = "disabled"; |
| 173 | 179 | ||
| 174 | dwc3@2690000 { | 180 | dwc3@2690000 { |
diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi index 3916937d6818..dd81508b919b 100644 --- a/arch/arm/boot/dts/kirkwood-6192.dtsi +++ b/arch/arm/boot/dts/kirkwood-6192.dtsi | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | / { | 1 | / { |
| 2 | mbus { | 2 | mbus { |
| 3 | pcie-controller { | 3 | pciec: pcie-controller { |
| 4 | compatible = "marvell,kirkwood-pcie"; | 4 | compatible = "marvell,kirkwood-pcie"; |
| 5 | status = "disabled"; | 5 | status = "disabled"; |
| 6 | device_type = "pci"; | 6 | device_type = "pci"; |
| @@ -15,7 +15,7 @@ | |||
| 15 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ | 15 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ |
| 16 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; | 16 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; |
| 17 | 17 | ||
| 18 | pcie@1,0 { | 18 | pcie0: pcie@1,0 { |
| 19 | device_type = "pci"; | 19 | device_type = "pci"; |
| 20 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; | 20 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; |
| 21 | reg = <0x0800 0 0 0 0>; | 21 | reg = <0x0800 0 0 0 0>; |
| @@ -35,16 +35,9 @@ | |||
| 35 | }; | 35 | }; |
| 36 | 36 | ||
| 37 | ocp@f1000000 { | 37 | ocp@f1000000 { |
| 38 | pinctrl: pinctrl@10000 { | 38 | pinctrl: pin-controller@10000 { |
| 39 | compatible = "marvell,88f6192-pinctrl"; | 39 | compatible = "marvell,88f6192-pinctrl"; |
| 40 | reg = <0x10000 0x20>; | ||
| 41 | 40 | ||
| 42 | pmx_nand: pmx-nand { | ||
| 43 | marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", | ||
| 44 | "mpp4", "mpp5", "mpp18", | ||
| 45 | "mpp19"; | ||
| 46 | marvell,function = "nand"; | ||
| 47 | }; | ||
| 48 | pmx_sata0: pmx-sata0 { | 41 | pmx_sata0: pmx-sata0 { |
| 49 | marvell,pins = "mpp5", "mpp21", "mpp23"; | 42 | marvell,pins = "mpp5", "mpp21", "mpp23"; |
| 50 | marvell,function = "sata0"; | 43 | marvell,function = "sata0"; |
| @@ -53,22 +46,6 @@ | |||
| 53 | marvell,pins = "mpp4", "mpp20", "mpp22"; | 46 | marvell,pins = "mpp4", "mpp20", "mpp22"; |
| 54 | marvell,function = "sata1"; | 47 | marvell,function = "sata1"; |
| 55 | }; | 48 | }; |
| 56 | pmx_spi: pmx-spi { | ||
| 57 | marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; | ||
| 58 | marvell,function = "spi"; | ||
| 59 | }; | ||
| 60 | pmx_twsi0: pmx-twsi0 { | ||
| 61 | marvell,pins = "mpp8", "mpp9"; | ||
| 62 | marvell,function = "twsi0"; | ||
| 63 | }; | ||
| 64 | pmx_uart0: pmx-uart0 { | ||
| 65 | marvell,pins = "mpp10", "mpp11"; | ||
| 66 | marvell,function = "uart0"; | ||
| 67 | }; | ||
| 68 | pmx_uart1: pmx-uart1 { | ||
| 69 | marvell,pins = "mpp13", "mpp14"; | ||
| 70 | marvell,function = "uart1"; | ||
| 71 | }; | ||
| 72 | pmx_sdio: pmx-sdio { | 49 | pmx_sdio: pmx-sdio { |
| 73 | marvell,pins = "mpp12", "mpp13", "mpp14", | 50 | marvell,pins = "mpp12", "mpp13", "mpp14", |
| 74 | "mpp15", "mpp16", "mpp17"; | 51 | "mpp15", "mpp16", "mpp17"; |
| @@ -76,14 +53,14 @@ | |||
| 76 | }; | 53 | }; |
| 77 | }; | 54 | }; |
| 78 | 55 | ||
| 79 | rtc@10300 { | 56 | rtc: rtc@10300 { |
| 80 | compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; | 57 | compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; |
| 81 | reg = <0x10300 0x20>; | 58 | reg = <0x10300 0x20>; |
| 82 | interrupts = <53>; | 59 | interrupts = <53>; |
| 83 | clocks = <&gate_clk 7>; | 60 | clocks = <&gate_clk 7>; |
| 84 | }; | 61 | }; |
| 85 | 62 | ||
| 86 | sata@80000 { | 63 | sata: sata@80000 { |
| 87 | compatible = "marvell,orion-sata"; | 64 | compatible = "marvell,orion-sata"; |
| 88 | reg = <0x80000 0x5000>; | 65 | reg = <0x80000 0x5000>; |
| 89 | interrupts = <21>; | 66 | interrupts = <21>; |
| @@ -92,7 +69,7 @@ | |||
| 92 | status = "disabled"; | 69 | status = "disabled"; |
| 93 | }; | 70 | }; |
| 94 | 71 | ||
| 95 | mvsdio@90000 { | 72 | sdio: mvsdio@90000 { |
| 96 | compatible = "marvell,orion-sdio"; | 73 | compatible = "marvell,orion-sdio"; |
| 97 | reg = <0x90000 0x200>; | 74 | reg = <0x90000 0x200>; |
| 98 | interrupts = <28>; | 75 | interrupts = <28>; |
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index 416d96e1302f..7dc7d6782e83 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | / { | 1 | / { |
| 2 | mbus { | 2 | mbus { |
| 3 | pcie-controller { | 3 | pciec: pcie-controller { |
| 4 | compatible = "marvell,kirkwood-pcie"; | 4 | compatible = "marvell,kirkwood-pcie"; |
| 5 | status = "disabled"; | 5 | status = "disabled"; |
| 6 | device_type = "pci"; | 6 | device_type = "pci"; |
| @@ -15,7 +15,7 @@ | |||
| 15 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ | 15 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ |
| 16 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; | 16 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; |
| 17 | 17 | ||
| 18 | pcie@1,0 { | 18 | pcie0: pcie@1,0 { |
| 19 | device_type = "pci"; | 19 | device_type = "pci"; |
| 20 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; | 20 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; |
| 21 | reg = <0x0800 0 0 0 0>; | 21 | reg = <0x0800 0 0 0 0>; |
| @@ -35,16 +35,9 @@ | |||
| 35 | }; | 35 | }; |
| 36 | 36 | ||
| 37 | ocp@f1000000 { | 37 | ocp@f1000000 { |
| 38 | pinctrl: pinctrl@10000 { | 38 | pinctrl: pin-controller@10000 { |
| 39 | compatible = "marvell,88f6281-pinctrl"; | 39 | compatible = "marvell,88f6281-pinctrl"; |
| 40 | reg = <0x10000 0x20>; | ||
| 41 | 40 | ||
| 42 | pmx_nand: pmx-nand { | ||
| 43 | marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", | ||
| 44 | "mpp4", "mpp5", "mpp18", | ||
| 45 | "mpp19"; | ||
| 46 | marvell,function = "nand"; | ||
| 47 | }; | ||
| 48 | pmx_sata0: pmx-sata0 { | 41 | pmx_sata0: pmx-sata0 { |
| 49 | marvell,pins = "mpp5", "mpp21", "mpp23"; | 42 | marvell,pins = "mpp5", "mpp21", "mpp23"; |
| 50 | marvell,function = "sata0"; | 43 | marvell,function = "sata0"; |
| @@ -53,22 +46,6 @@ | |||
| 53 | marvell,pins = "mpp4", "mpp20", "mpp22"; | 46 | marvell,pins = "mpp4", "mpp20", "mpp22"; |
| 54 | marvell,function = "sata1"; | 47 | marvell,function = "sata1"; |
| 55 | }; | 48 | }; |
| 56 | pmx_spi: pmx-spi { | ||
| 57 | marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; | ||
| 58 | marvell,function = "spi"; | ||
| 59 | }; | ||
| 60 | pmx_twsi0: pmx-twsi0 { | ||
| 61 | marvell,pins = "mpp8", "mpp9"; | ||
| 62 | marvell,function = "twsi0"; | ||
| 63 | }; | ||
| 64 | pmx_uart0: pmx-uart0 { | ||
| 65 | marvell,pins = "mpp10", "mpp11"; | ||
| 66 | marvell,function = "uart0"; | ||
| 67 | }; | ||
| 68 | pmx_uart1: pmx-uart1 { | ||
| 69 | marvell,pins = "mpp13", "mpp14"; | ||
| 70 | marvell,function = "uart1"; | ||
| 71 | }; | ||
| 72 | pmx_sdio: pmx-sdio { | 49 | pmx_sdio: pmx-sdio { |
| 73 | marvell,pins = "mpp12", "mpp13", "mpp14", | 50 | marvell,pins = "mpp12", "mpp13", "mpp14", |
| 74 | "mpp15", "mpp16", "mpp17"; | 51 | "mpp15", "mpp16", "mpp17"; |
| @@ -76,14 +53,14 @@ | |||
| 76 | }; | 53 | }; |
| 77 | }; | 54 | }; |
| 78 | 55 | ||
| 79 | rtc@10300 { | 56 | rtc: rtc@10300 { |
| 80 | compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; | 57 | compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; |
| 81 | reg = <0x10300 0x20>; | 58 | reg = <0x10300 0x20>; |
| 82 | interrupts = <53>; | 59 | interrupts = <53>; |
| 83 | clocks = <&gate_clk 7>; | 60 | clocks = <&gate_clk 7>; |
| 84 | }; | 61 | }; |
| 85 | 62 | ||
| 86 | sata@80000 { | 63 | sata: sata@80000 { |
| 87 | compatible = "marvell,orion-sata"; | 64 | compatible = "marvell,orion-sata"; |
| 88 | reg = <0x80000 0x5000>; | 65 | reg = <0x80000 0x5000>; |
| 89 | interrupts = <21>; | 66 | interrupts = <21>; |
| @@ -94,7 +71,7 @@ | |||
| 94 | status = "disabled"; | 71 | status = "disabled"; |
| 95 | }; | 72 | }; |
| 96 | 73 | ||
| 97 | mvsdio@90000 { | 74 | sdio: mvsdio@90000 { |
| 98 | compatible = "marvell,orion-sdio"; | 75 | compatible = "marvell,orion-sdio"; |
| 99 | reg = <0x90000 0x200>; | 76 | reg = <0x90000 0x200>; |
| 100 | interrupts = <28>; | 77 | interrupts = <28>; |
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index 2902e0d7971d..4680eec990f0 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | / { | 1 | / { |
| 2 | mbus { | 2 | mbus { |
| 3 | pcie-controller { | 3 | pciec: pcie-controller { |
| 4 | compatible = "marvell,kirkwood-pcie"; | 4 | compatible = "marvell,kirkwood-pcie"; |
| 5 | status = "disabled"; | 5 | status = "disabled"; |
| 6 | device_type = "pci"; | 6 | device_type = "pci"; |
| @@ -19,7 +19,7 @@ | |||
| 19 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ | 19 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ |
| 20 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; | 20 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; |
| 21 | 21 | ||
| 22 | pcie@1,0 { | 22 | pcie0: pcie@1,0 { |
| 23 | device_type = "pci"; | 23 | device_type = "pci"; |
| 24 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; | 24 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; |
| 25 | reg = <0x0800 0 0 0 0>; | 25 | reg = <0x0800 0 0 0 0>; |
| @@ -36,7 +36,7 @@ | |||
| 36 | status = "disabled"; | 36 | status = "disabled"; |
| 37 | }; | 37 | }; |
| 38 | 38 | ||
| 39 | pcie@2,0 { | 39 | pcie1: pcie@2,0 { |
| 40 | device_type = "pci"; | 40 | device_type = "pci"; |
| 41 | assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; | 41 | assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; |
| 42 | reg = <0x1000 0 0 0 0>; | 42 | reg = <0x1000 0 0 0 0>; |
| @@ -56,15 +56,8 @@ | |||
| 56 | }; | 56 | }; |
| 57 | ocp@f1000000 { | 57 | ocp@f1000000 { |
| 58 | 58 | ||
| 59 | pinctrl: pinctrl@10000 { | 59 | pinctrl: pin-controller@10000 { |
| 60 | compatible = "marvell,88f6282-pinctrl"; | 60 | compatible = "marvell,88f6282-pinctrl"; |
| 61 | reg = <0x10000 0x20>; | ||
| 62 | |||
| 63 | pmx_nand: pmx-nand { | ||
| 64 | marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", | ||
| 65 | "mpp4", "mpp5", "mpp18", "mpp19"; | ||
| 66 | marvell,function = "nand"; | ||
| 67 | }; | ||
| 68 | 61 | ||
| 69 | pmx_sata0: pmx-sata0 { | 62 | pmx_sata0: pmx-sata0 { |
| 70 | marvell,pins = "mpp5", "mpp21", "mpp23"; | 63 | marvell,pins = "mpp5", "mpp21", "mpp23"; |
| @@ -74,29 +67,16 @@ | |||
| 74 | marvell,pins = "mpp4", "mpp20", "mpp22"; | 67 | marvell,pins = "mpp4", "mpp20", "mpp22"; |
| 75 | marvell,function = "sata1"; | 68 | marvell,function = "sata1"; |
| 76 | }; | 69 | }; |
| 77 | pmx_spi: pmx-spi { | ||
| 78 | marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; | ||
| 79 | marvell,function = "spi"; | ||
| 80 | }; | ||
| 81 | pmx_twsi0: pmx-twsi0 { | ||
| 82 | marvell,pins = "mpp8", "mpp9"; | ||
| 83 | marvell,function = "twsi0"; | ||
| 84 | }; | ||
| 85 | 70 | ||
| 71 | /* | ||
| 72 | * Default I2C1 pinctrl setting on mpp36/mpp37, | ||
| 73 | * overwrite marvell,pins on board level if required. | ||
| 74 | */ | ||
| 86 | pmx_twsi1: pmx-twsi1 { | 75 | pmx_twsi1: pmx-twsi1 { |
| 87 | marvell,pins = "mpp36", "mpp37"; | 76 | marvell,pins = "mpp36", "mpp37"; |
| 88 | marvell,function = "twsi1"; | 77 | marvell,function = "twsi1"; |
| 89 | }; | 78 | }; |
| 90 | 79 | ||
| 91 | pmx_uart0: pmx-uart0 { | ||
| 92 | marvell,pins = "mpp10", "mpp11"; | ||
| 93 | marvell,function = "uart0"; | ||
| 94 | }; | ||
| 95 | |||
| 96 | pmx_uart1: pmx-uart1 { | ||
| 97 | marvell,pins = "mpp13", "mpp14"; | ||
| 98 | marvell,function = "uart1"; | ||
| 99 | }; | ||
| 100 | pmx_sdio: pmx-sdio { | 80 | pmx_sdio: pmx-sdio { |
| 101 | marvell,pins = "mpp12", "mpp13", "mpp14", | 81 | marvell,pins = "mpp12", "mpp13", "mpp14", |
| 102 | "mpp15", "mpp16", "mpp17"; | 82 | "mpp15", "mpp16", "mpp17"; |
| @@ -104,20 +84,20 @@ | |||
| 104 | }; | 84 | }; |
| 105 | }; | 85 | }; |
| 106 | 86 | ||
| 107 | thermal@10078 { | 87 | thermal: thermal@10078 { |
| 108 | compatible = "marvell,kirkwood-thermal"; | 88 | compatible = "marvell,kirkwood-thermal"; |
| 109 | reg = <0x10078 0x4>; | 89 | reg = <0x10078 0x4>; |
| 110 | status = "okay"; | 90 | status = "okay"; |
| 111 | }; | 91 | }; |
| 112 | 92 | ||
| 113 | rtc@10300 { | 93 | rtc: rtc@10300 { |
| 114 | compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; | 94 | compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; |
| 115 | reg = <0x10300 0x20>; | 95 | reg = <0x10300 0x20>; |
| 116 | interrupts = <53>; | 96 | interrupts = <53>; |
| 117 | clocks = <&gate_clk 7>; | 97 | clocks = <&gate_clk 7>; |
| 118 | }; | 98 | }; |
| 119 | 99 | ||
| 120 | i2c@11100 { | 100 | i2c1: i2c@11100 { |
| 121 | compatible = "marvell,mv64xxx-i2c"; | 101 | compatible = "marvell,mv64xxx-i2c"; |
| 122 | reg = <0x11100 0x20>; | 102 | reg = <0x11100 0x20>; |
| 123 | #address-cells = <1>; | 103 | #address-cells = <1>; |
| @@ -125,10 +105,12 @@ | |||
| 125 | interrupts = <32>; | 105 | interrupts = <32>; |
| 126 | clock-frequency = <100000>; | 106 | clock-frequency = <100000>; |
| 127 | clocks = <&gate_clk 7>; | 107 | clocks = <&gate_clk 7>; |
| 108 | pinctrl-0 = <&pmx_twsi1>; | ||
| 109 | pinctrl-names = "default"; | ||
| 128 | status = "disabled"; | 110 | status = "disabled"; |
| 129 | }; | 111 | }; |
| 130 | 112 | ||
| 131 | sata@80000 { | 113 | sata: sata@80000 { |
| 132 | compatible = "marvell,orion-sata"; | 114 | compatible = "marvell,orion-sata"; |
| 133 | reg = <0x80000 0x5000>; | 115 | reg = <0x80000 0x5000>; |
| 134 | interrupts = <21>; | 116 | interrupts = <21>; |
| @@ -139,7 +121,7 @@ | |||
| 139 | status = "disabled"; | 121 | status = "disabled"; |
| 140 | }; | 122 | }; |
| 141 | 123 | ||
| 142 | mvsdio@90000 { | 124 | sdio: mvsdio@90000 { |
| 143 | compatible = "marvell,orion-sdio"; | 125 | compatible = "marvell,orion-sdio"; |
| 144 | reg = <0x90000 0x200>; | 126 | reg = <0x90000 0x200>; |
| 145 | interrupts = <28>; | 127 | interrupts = <28>; |
diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi index 3271e4c8ea07..9e1f741d74ff 100644 --- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi | |||
| @@ -1,31 +1,51 @@ | |||
| 1 | / { | 1 | / { |
| 2 | mbus { | ||
| 3 | pciec: pcie-controller { | ||
| 4 | compatible = "marvell,kirkwood-pcie"; | ||
| 5 | status = "disabled"; | ||
| 6 | device_type = "pci"; | ||
| 7 | |||
| 8 | #address-cells = <3>; | ||
| 9 | #size-cells = <2>; | ||
| 10 | |||
| 11 | bus-range = <0x00 0xff>; | ||
| 12 | |||
| 13 | ranges = | ||
| 14 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | ||
| 15 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ | ||
| 16 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; | ||
| 17 | |||
| 18 | pcie0: pcie@1,0 { | ||
| 19 | device_type = "pci"; | ||
| 20 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; | ||
| 21 | reg = <0x0800 0 0 0 0>; | ||
| 22 | #address-cells = <3>; | ||
| 23 | #size-cells = <2>; | ||
| 24 | #interrupt-cells = <1>; | ||
| 25 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | ||
| 26 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | ||
| 27 | interrupt-map-mask = <0 0 0 0>; | ||
| 28 | interrupt-map = <0 0 0 0 &intc 9>; | ||
| 29 | marvell,pcie-port = <0>; | ||
| 30 | marvell,pcie-lane = <0>; | ||
| 31 | clocks = <&gate_clk 2>; | ||
| 32 | status = "disabled"; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | |||
| 2 | ocp@f1000000 { | 37 | ocp@f1000000 { |
| 3 | pinctrl: pinctrl@10000 { | 38 | pinctrl: pin-controller@10000 { |
| 4 | compatible = "marvell,98dx4122-pinctrl"; | 39 | compatible = "marvell,98dx4122-pinctrl"; |
| 5 | reg = <0x10000 0x20>; | ||
| 6 | 40 | ||
| 7 | pmx_nand: pmx-nand { | ||
| 8 | marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", | ||
| 9 | "mpp4", "mpp5", "mpp18", | ||
| 10 | "mpp19"; | ||
| 11 | marvell,function = "nand"; | ||
| 12 | }; | ||
| 13 | pmx_spi: pmx-spi { | ||
| 14 | marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; | ||
| 15 | marvell,function = "spi"; | ||
| 16 | }; | ||
| 17 | pmx_twsi0: pmx-twsi0 { | ||
| 18 | marvell,pins = "mpp8", "mpp9"; | ||
| 19 | marvell,function = "twsi0"; | ||
| 20 | }; | ||
| 21 | pmx_uart0: pmx-uart0 { | ||
| 22 | marvell,pins = "mpp10", "mpp11"; | ||
| 23 | marvell,function = "uart0"; | ||
| 24 | }; | ||
| 25 | pmx_uart1: pmx-uart1 { | ||
| 26 | marvell,pins = "mpp13", "mpp14"; | ||
| 27 | marvell,function = "uart1"; | ||
| 28 | }; | ||
| 29 | }; | 41 | }; |
| 30 | }; | 42 | }; |
| 31 | }; | 43 | }; |
| 44 | |||
| 45 | &sata_phy0 { | ||
| 46 | status = "disabled"; | ||
| 47 | }; | ||
| 48 | |||
| 49 | &sata_phy1 { | ||
| 50 | status = "disabled"; | ||
| 51 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts index 6becedebaa4e..c9247f8672ae 100644 --- a/arch/arm/boot/dts/kirkwood-b3.dts +++ b/arch/arm/boot/dts/kirkwood-b3.dts | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | 30 | ||
| 31 | chosen { | 31 | chosen { |
| 32 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 32 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 33 | stdout-path = &uart0; | ||
| 33 | }; | 34 | }; |
| 34 | 35 | ||
| 35 | mbus { | 36 | mbus { |
| @@ -44,7 +45,7 @@ | |||
| 44 | }; | 45 | }; |
| 45 | 46 | ||
| 46 | ocp@f1000000 { | 47 | ocp@f1000000 { |
| 47 | pinctrl: pinctrl@10000 { | 48 | pinctrl: pin-controller@10000 { |
| 48 | pmx_button_power: pmx-button-power { | 49 | pmx_button_power: pmx-button-power { |
| 49 | marvell,pins = "mpp39"; | 50 | marvell,pins = "mpp39"; |
| 50 | marvell,function = "gpio"; | 51 | marvell,function = "gpio"; |
| @@ -69,8 +70,6 @@ | |||
| 69 | 70 | ||
| 70 | spi@10600 { | 71 | spi@10600 { |
| 71 | status = "okay"; | 72 | status = "okay"; |
| 72 | pinctrl-0 = <&pmx_spi>; | ||
| 73 | pinctrl-names = "default"; | ||
| 74 | 73 | ||
| 75 | m25p16@0 { | 74 | m25p16@0 { |
| 76 | #address-cells = <1>; | 75 | #address-cells = <1>; |
| @@ -113,8 +112,6 @@ | |||
| 113 | * UART0_TX = Testpoint 66 | 112 | * UART0_TX = Testpoint 66 |
| 114 | * See the Excito Wiki for more details. | 113 | * See the Excito Wiki for more details. |
| 115 | */ | 114 | */ |
| 116 | pinctrl-0 = <&pmx_uart0>; | ||
| 117 | pinctrl-names = "default"; | ||
| 118 | status = "okay"; | 115 | status = "okay"; |
| 119 | }; | 116 | }; |
| 120 | 117 | ||
diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts index 3b62aeeaa3a2..ab6ab4933e6b 100644 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts | |||
| @@ -14,10 +14,11 @@ | |||
| 14 | 14 | ||
| 15 | chosen { | 15 | chosen { |
| 16 | bootargs = "console=ttyS0,115200n8"; | 16 | bootargs = "console=ttyS0,115200n8"; |
| 17 | stdout-path = &uart0; | ||
| 17 | }; | 18 | }; |
| 18 | 19 | ||
| 19 | ocp@f1000000 { | 20 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 21 | pinctrl: pin-controller@10000 { |
| 21 | pmx_cloudbox_sata0: pmx-cloudbox-sata0 { | 22 | pmx_cloudbox_sata0: pmx-cloudbox-sata0 { |
| 22 | marvell,pins = "mpp15"; | 23 | marvell,pins = "mpp15"; |
| 23 | marvell,function = "sata0"; | 24 | marvell,function = "sata0"; |
| @@ -25,9 +26,6 @@ | |||
| 25 | }; | 26 | }; |
| 26 | 27 | ||
| 27 | serial@12000 { | 28 | serial@12000 { |
| 28 | pinctrl-0 = <&pmx_uart0>; | ||
| 29 | pinctrl-names = "default"; | ||
| 30 | clock-frequency = <166666667>; | ||
| 31 | status = "okay"; | 29 | status = "okay"; |
| 32 | }; | 30 | }; |
| 33 | 31 | ||
| @@ -39,8 +37,6 @@ | |||
| 39 | }; | 37 | }; |
| 40 | 38 | ||
| 41 | spi@10600 { | 39 | spi@10600 { |
| 42 | pinctrl-0 = <&pmx_spi>; | ||
| 43 | pinctrl-names = "default"; | ||
| 44 | status = "okay"; | 40 | status = "okay"; |
| 45 | 41 | ||
| 46 | flash@0 { | 42 | flash@0 { |
diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi index 02d1225ef99f..812df691ae3d 100644 --- a/arch/arm/boot/dts/kirkwood-db.dtsi +++ b/arch/arm/boot/dts/kirkwood-db.dtsi | |||
| @@ -22,10 +22,11 @@ | |||
| 22 | 22 | ||
| 23 | chosen { | 23 | chosen { |
| 24 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 24 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 25 | stdout-path = &uart0; | ||
| 25 | }; | 26 | }; |
| 26 | 27 | ||
| 27 | ocp@f1000000 { | 28 | ocp@f1000000 { |
| 28 | pinctrl@10000 { | 29 | pin-controller@10000 { |
| 29 | pmx_sdio_gpios: pmx-sdio-gpios { | 30 | pmx_sdio_gpios: pmx-sdio-gpios { |
| 30 | marvell,pins = "mpp37", "mpp38"; | 31 | marvell,pins = "mpp37", "mpp38"; |
| 31 | marvell,function = "gpio"; | 32 | marvell,function = "gpio"; |
| @@ -33,10 +34,7 @@ | |||
| 33 | }; | 34 | }; |
| 34 | 35 | ||
| 35 | serial@12000 { | 36 | serial@12000 { |
| 36 | pinctrl-0 = <&pmx_uart0>; | 37 | status = "okay"; |
| 37 | pinctrl-names = "default"; | ||
| 38 | clock-frequency = <200000000>; | ||
| 39 | status = "ok"; | ||
| 40 | }; | 38 | }; |
| 41 | 39 | ||
| 42 | sata@80000 { | 40 | sata@80000 { |
| @@ -59,8 +57,6 @@ | |||
| 59 | }; | 57 | }; |
| 60 | 58 | ||
| 61 | &nand { | 59 | &nand { |
| 62 | pinctrl-0 = <&pmx_nand>; | ||
| 63 | pinctrl-names = "default"; | ||
| 64 | chip-delay = <25>; | 60 | chip-delay = <25>; |
| 65 | status = "okay"; | 61 | status = "okay"; |
| 66 | 62 | ||
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts index bf7fe8ab88f4..d85ef0a91b50 100644 --- a/arch/arm/boot/dts/kirkwood-dns320.dts +++ b/arch/arm/boot/dts/kirkwood-dns320.dts | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | 13 | ||
| 14 | chosen { | 14 | chosen { |
| 15 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 15 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 16 | stdout-path = &uart0; | ||
| 16 | }; | 17 | }; |
| 17 | 18 | ||
| 18 | gpio-leds { | 19 | gpio-leds { |
| @@ -51,8 +52,6 @@ | |||
| 51 | }; | 52 | }; |
| 52 | 53 | ||
| 53 | serial@12100 { | 54 | serial@12100 { |
| 54 | pinctrl-0 = <&pmx_uart1>; | ||
| 55 | pinctrl-names = "default"; | ||
| 56 | status = "okay"; | 55 | status = "okay"; |
| 57 | }; | 56 | }; |
| 58 | }; | 57 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts index cb9978c652f2..5e586ed04c58 100644 --- a/arch/arm/boot/dts/kirkwood-dns325.dts +++ b/arch/arm/boot/dts/kirkwood-dns325.dts | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | 13 | ||
| 14 | chosen { | 14 | chosen { |
| 15 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 15 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 16 | stdout-path = &uart0; | ||
| 16 | }; | 17 | }; |
| 17 | 18 | ||
| 18 | gpio-leds { | 19 | gpio-leds { |
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index d5aa9564a287..113dcf056dcf 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi | |||
| @@ -50,7 +50,7 @@ | |||
| 50 | }; | 50 | }; |
| 51 | 51 | ||
| 52 | ocp@f1000000 { | 52 | ocp@f1000000 { |
| 53 | pinctrl: pinctrl@10000 { | 53 | pinctrl: pin-controller@10000 { |
| 54 | 54 | ||
| 55 | pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0 | 55 | pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0 |
| 56 | &pmx_present_sata1 &pmx_fan_tacho | 56 | &pmx_present_sata1 &pmx_fan_tacho |
| @@ -183,8 +183,6 @@ | |||
| 183 | }; | 183 | }; |
| 184 | 184 | ||
| 185 | &nand { | 185 | &nand { |
| 186 | pinctrl-0 = <&pmx_nand>; | ||
| 187 | pinctrl-names = "default"; | ||
| 188 | status = "okay"; | 186 | status = "okay"; |
| 189 | chip-delay = <35>; | 187 | chip-delay = <35>; |
| 190 | 188 | ||
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index f31312ebd0d6..849736349511 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts | |||
| @@ -14,10 +14,11 @@ | |||
| 14 | 14 | ||
| 15 | chosen { | 15 | chosen { |
| 16 | bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; | 16 | bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; |
| 17 | stdout-path = &uart0; | ||
| 17 | }; | 18 | }; |
| 18 | 19 | ||
| 19 | ocp@f1000000 { | 20 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 21 | pinctrl: pin-controller@10000 { |
| 21 | pmx_usb_power_enable: pmx-usb-power-enable { | 22 | pmx_usb_power_enable: pmx-usb-power-enable { |
| 22 | marvell,pins = "mpp29"; | 23 | marvell,pins = "mpp29"; |
| 23 | marvell,function = "gpio"; | 24 | marvell,function = "gpio"; |
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts index 28b3ee369778..6467c7924195 100644 --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts | |||
| @@ -14,10 +14,11 @@ | |||
| 14 | 14 | ||
| 15 | chosen { | 15 | chosen { |
| 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 17 | stdout-path = &uart0; | ||
| 17 | }; | 18 | }; |
| 18 | 19 | ||
| 19 | ocp@f1000000 { | 20 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 21 | pinctrl: pin-controller@10000 { |
| 21 | pmx_led_bluetooth: pmx-led-bluetooth { | 22 | pmx_led_bluetooth: pmx-led-bluetooth { |
| 22 | marvell,pins = "mpp47"; | 23 | marvell,pins = "mpp47"; |
| 23 | marvell,function = "gpio"; | 24 | marvell,function = "gpio"; |
| @@ -37,8 +38,6 @@ | |||
| 37 | 38 | ||
| 38 | spi@10600 { | 39 | spi@10600 { |
| 39 | status = "okay"; | 40 | status = "okay"; |
| 40 | pinctrl-0 = <&pmx_spi>; | ||
| 41 | pinctrl-names = "default"; | ||
| 42 | 41 | ||
| 43 | m25p40@0 { | 42 | m25p40@0 { |
| 44 | #address-cells = <1>; | 43 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/kirkwood-ds109.dts b/arch/arm/boot/dts/kirkwood-ds109.dts index 772092c94ca3..d4bcc1c7f6b3 100644 --- a/arch/arm/boot/dts/kirkwood-ds109.dts +++ b/arch/arm/boot/dts/kirkwood-ds109.dts | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | 25 | ||
| 26 | chosen { | 26 | chosen { |
| 27 | bootargs = "console=ttyS0,115200n8"; | 27 | bootargs = "console=ttyS0,115200n8"; |
| 28 | stdout-path = &uart0; | ||
| 28 | }; | 29 | }; |
| 29 | 30 | ||
| 30 | gpio-fan-150-32-35 { | 31 | gpio-fan-150-32-35 { |
diff --git a/arch/arm/boot/dts/kirkwood-ds110jv10.dts b/arch/arm/boot/dts/kirkwood-ds110jv10.dts index aabafbe0da4c..95bf83b91b4a 100644 --- a/arch/arm/boot/dts/kirkwood-ds110jv10.dts +++ b/arch/arm/boot/dts/kirkwood-ds110jv10.dts | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | 25 | ||
| 26 | chosen { | 26 | chosen { |
| 27 | bootargs = "console=ttyS0,115200n8"; | 27 | bootargs = "console=ttyS0,115200n8"; |
| 28 | stdout-path = &uart0; | ||
| 28 | }; | 29 | }; |
| 29 | 30 | ||
| 30 | gpio-fan-150-32-35 { | 31 | gpio-fan-150-32-35 { |
diff --git a/arch/arm/boot/dts/kirkwood-ds111.dts b/arch/arm/boot/dts/kirkwood-ds111.dts index 16ec7fbab573..61f47fbe44d0 100644 --- a/arch/arm/boot/dts/kirkwood-ds111.dts +++ b/arch/arm/boot/dts/kirkwood-ds111.dts | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | 24 | ||
| 25 | chosen { | 25 | chosen { |
| 26 | bootargs = "console=ttyS0,115200n8"; | 26 | bootargs = "console=ttyS0,115200n8"; |
| 27 | stdout-path = &uart0; | ||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | gpio-fan-100-15-35-1 { | 30 | gpio-fan-100-15-35-1 { |
diff --git a/arch/arm/boot/dts/kirkwood-ds112.dts b/arch/arm/boot/dts/kirkwood-ds112.dts index cff1b2388765..bf4143c6cb8f 100644 --- a/arch/arm/boot/dts/kirkwood-ds112.dts +++ b/arch/arm/boot/dts/kirkwood-ds112.dts | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | 24 | ||
| 25 | chosen { | 25 | chosen { |
| 26 | bootargs = "console=ttyS0,115200n8"; | 26 | bootargs = "console=ttyS0,115200n8"; |
| 27 | stdout-path = &uart0; | ||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | gpio-fan-100-15-35-1 { | 30 | gpio-fan-100-15-35-1 { |
diff --git a/arch/arm/boot/dts/kirkwood-ds209.dts b/arch/arm/boot/dts/kirkwood-ds209.dts index 330411993d38..6d25093a9ac4 100644 --- a/arch/arm/boot/dts/kirkwood-ds209.dts +++ b/arch/arm/boot/dts/kirkwood-ds209.dts | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | 24 | ||
| 25 | chosen { | 25 | chosen { |
| 26 | bootargs = "console=ttyS0,115200n8"; | 26 | bootargs = "console=ttyS0,115200n8"; |
| 27 | stdout-path = &uart0; | ||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | gpio-fan-150-32-35 { | 30 | gpio-fan-150-32-35 { |
diff --git a/arch/arm/boot/dts/kirkwood-ds210.dts b/arch/arm/boot/dts/kirkwood-ds210.dts index 6052eaa37d4f..2f1933efcac1 100644 --- a/arch/arm/boot/dts/kirkwood-ds210.dts +++ b/arch/arm/boot/dts/kirkwood-ds210.dts | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | 26 | ||
| 27 | chosen { | 27 | chosen { |
| 28 | bootargs = "console=ttyS0,115200n8"; | 28 | bootargs = "console=ttyS0,115200n8"; |
| 29 | stdout-path = &uart0; | ||
| 29 | }; | 30 | }; |
| 30 | 31 | ||
| 31 | gpio-fan-150-32-35 { | 32 | gpio-fan-150-32-35 { |
diff --git a/arch/arm/boot/dts/kirkwood-ds212.dts b/arch/arm/boot/dts/kirkwood-ds212.dts index 7f76cd30e84e..99afd462f956 100644 --- a/arch/arm/boot/dts/kirkwood-ds212.dts +++ b/arch/arm/boot/dts/kirkwood-ds212.dts | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | 27 | ||
| 28 | chosen { | 28 | chosen { |
| 29 | bootargs = "console=ttyS0,115200n8"; | 29 | bootargs = "console=ttyS0,115200n8"; |
| 30 | stdout-path = &uart0; | ||
| 30 | }; | 31 | }; |
| 31 | 32 | ||
| 32 | gpio-fan-100-15-35-1 { | 33 | gpio-fan-100-15-35-1 { |
diff --git a/arch/arm/boot/dts/kirkwood-ds212j.dts b/arch/arm/boot/dts/kirkwood-ds212j.dts index 1f83a00f1f74..f5c4213fc67c 100644 --- a/arch/arm/boot/dts/kirkwood-ds212j.dts +++ b/arch/arm/boot/dts/kirkwood-ds212j.dts | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | 25 | ||
| 26 | chosen { | 26 | chosen { |
| 27 | bootargs = "console=ttyS0,115200n8"; | 27 | bootargs = "console=ttyS0,115200n8"; |
| 28 | stdout-path = &uart0; | ||
| 28 | }; | 29 | }; |
| 29 | 30 | ||
| 30 | gpio-fan-100-32-35 { | 31 | gpio-fan-100-32-35 { |
diff --git a/arch/arm/boot/dts/kirkwood-ds409.dts b/arch/arm/boot/dts/kirkwood-ds409.dts index 0a573add44a2..e80a962ebba0 100644 --- a/arch/arm/boot/dts/kirkwood-ds409.dts +++ b/arch/arm/boot/dts/kirkwood-ds409.dts | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | 24 | ||
| 25 | chosen { | 25 | chosen { |
| 26 | bootargs = "console=ttyS0,115200n8"; | 26 | bootargs = "console=ttyS0,115200n8"; |
| 27 | stdout-path = &uart0; | ||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | gpio-fan-150-15-18 { | 30 | gpio-fan-150-15-18 { |
diff --git a/arch/arm/boot/dts/kirkwood-ds409slim.dts b/arch/arm/boot/dts/kirkwood-ds409slim.dts index 1848a6245fd3..cae5af4b88b5 100644 --- a/arch/arm/boot/dts/kirkwood-ds409slim.dts +++ b/arch/arm/boot/dts/kirkwood-ds409slim.dts | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | 24 | ||
| 25 | chosen { | 25 | chosen { |
| 26 | bootargs = "console=ttyS0,115200n8"; | 26 | bootargs = "console=ttyS0,115200n8"; |
| 27 | stdout-path = &uart0; | ||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | gpio-fan-150-32-35 { | 30 | gpio-fan-150-32-35 { |
diff --git a/arch/arm/boot/dts/kirkwood-ds411.dts b/arch/arm/boot/dts/kirkwood-ds411.dts index a1737b4311c6..623cd4a37d71 100644 --- a/arch/arm/boot/dts/kirkwood-ds411.dts +++ b/arch/arm/boot/dts/kirkwood-ds411.dts | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | 24 | ||
| 25 | chosen { | 25 | chosen { |
| 26 | bootargs = "console=ttyS0,115200n8"; | 26 | bootargs = "console=ttyS0,115200n8"; |
| 27 | stdout-path = &uart0; | ||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | gpio-fan-100-15-35-1 { | 30 | gpio-fan-100-15-35-1 { |
diff --git a/arch/arm/boot/dts/kirkwood-ds411j.dts b/arch/arm/boot/dts/kirkwood-ds411j.dts index 0cde914eceae..3348e330f074 100644 --- a/arch/arm/boot/dts/kirkwood-ds411j.dts +++ b/arch/arm/boot/dts/kirkwood-ds411j.dts | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | 24 | ||
| 25 | chosen { | 25 | chosen { |
| 26 | bootargs = "console=ttyS0,115200n8"; | 26 | bootargs = "console=ttyS0,115200n8"; |
| 27 | stdout-path = &uart0; | ||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | gpio-fan-150-15-18 { | 30 | gpio-fan-150-15-18 { |
diff --git a/arch/arm/boot/dts/kirkwood-ds411slim.dts b/arch/arm/boot/dts/kirkwood-ds411slim.dts index aef0cadc2c78..a0a1fad8b4de 100644 --- a/arch/arm/boot/dts/kirkwood-ds411slim.dts +++ b/arch/arm/boot/dts/kirkwood-ds411slim.dts | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | 24 | ||
| 25 | chosen { | 25 | chosen { |
| 26 | bootargs = "console=ttyS0,115200n8"; | 26 | bootargs = "console=ttyS0,115200n8"; |
| 27 | stdout-path = &uart0; | ||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | gpio-fan-100-15-35-1 { | 30 | gpio-fan-100-15-35-1 { |
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index eb9329420107..aa60a0b049a7 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts | |||
| @@ -14,10 +14,11 @@ | |||
| 14 | 14 | ||
| 15 | chosen { | 15 | chosen { |
| 16 | bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; | 16 | bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; |
| 17 | stdout-path = &uart0; | ||
| 17 | }; | 18 | }; |
| 18 | 19 | ||
| 19 | ocp@f1000000 { | 20 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 21 | pinctrl: pin-controller@10000 { |
| 21 | pmx_usb_power_enable: pmx-usb-power-enable { | 22 | pmx_usb_power_enable: pmx-usb-power-enable { |
| 22 | marvell,pins = "mpp29"; | 23 | marvell,pins = "mpp29"; |
| 23 | marvell,function = "gpio"; | 24 | marvell,function = "gpio"; |
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index 2d51fce74a5a..c5a1fc75c7a3 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts | |||
| @@ -14,10 +14,11 @@ | |||
| 14 | 14 | ||
| 15 | chosen { | 15 | chosen { |
| 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 17 | stdout-path = &uart0; | ||
| 17 | }; | 18 | }; |
| 18 | 19 | ||
| 19 | ocp@f1000000 { | 20 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 21 | pinctrl: pin-controller@10000 { |
| 21 | pmx_led_health_r: pmx-led-health-r { | 22 | pmx_led_health_r: pmx-led-health-r { |
| 22 | marvell,pins = "mpp46"; | 23 | marvell,pins = "mpp46"; |
| 23 | marvell,function = "gpio"; | 24 | marvell,function = "gpio"; |
| @@ -36,7 +37,6 @@ | |||
| 36 | }; | 37 | }; |
| 37 | }; | 38 | }; |
| 38 | serial@12000 { | 39 | serial@12000 { |
| 39 | clock-frequency = <200000000>; | ||
| 40 | status = "ok"; | 40 | status = "ok"; |
| 41 | }; | 41 | }; |
| 42 | 42 | ||
| @@ -101,13 +101,19 @@ | |||
| 101 | status = "okay"; | 101 | status = "okay"; |
| 102 | 102 | ||
| 103 | ethphy0: ethernet-phy@0 { | 103 | ethphy0: ethernet-phy@0 { |
| 104 | compatible = "marvell,88e1121"; | 104 | /* Marvell 88E1121R */ |
| 105 | compatible = "ethernet-phy-id0141.0cb0", | ||
| 106 | "ethernet-phy-ieee802.3-c22"; | ||
| 105 | reg = <0>; | 107 | reg = <0>; |
| 108 | phy-connection-type = "rgmii-id"; | ||
| 106 | }; | 109 | }; |
| 107 | 110 | ||
| 108 | ethphy1: ethernet-phy@1 { | 111 | ethphy1: ethernet-phy@1 { |
| 109 | compatible = "marvell,88e1121"; | 112 | /* Marvell 88E1121R */ |
| 113 | compatible = "ethernet-phy-id0141.0cb0", | ||
| 114 | "ethernet-phy-ieee802.3-c22"; | ||
| 110 | reg = <1>; | 115 | reg = <1>; |
| 116 | phy-connection-type = "rgmii-id"; | ||
| 111 | }; | 117 | }; |
| 112 | }; | 118 | }; |
| 113 | 119 | ||
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index a1add3f215e3..bfa5edde179c 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts | |||
| @@ -14,10 +14,11 @@ | |||
| 14 | 14 | ||
| 15 | chosen { | 15 | chosen { |
| 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 17 | stdout-path = &uart0; | ||
| 17 | }; | 18 | }; |
| 18 | 19 | ||
| 19 | ocp@f1000000 { | 20 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 21 | pinctrl: pin-controller@10000 { |
| 21 | pmx_led_os_red: pmx-led-os-red { | 22 | pmx_led_os_red: pmx-led-os-red { |
| 22 | marvell,pins = "mpp22"; | 23 | marvell,pins = "mpp22"; |
| 23 | marvell,function = "gpio"; | 24 | marvell,function = "gpio"; |
| @@ -104,8 +105,6 @@ | |||
| 104 | 105 | ||
| 105 | &nand { | 106 | &nand { |
| 106 | status = "okay"; | 107 | status = "okay"; |
| 107 | pinctrl-0 = <&pmx_nand>; | ||
| 108 | pinctrl-names = "default"; | ||
| 109 | 108 | ||
| 110 | partition@0 { | 109 | partition@0 { |
| 111 | label = "u-boot"; | 110 | label = "u-boot"; |
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 8d8c80e3656d..38e31d15a62d 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | 14 | ||
| 15 | chosen { | 15 | chosen { |
| 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 17 | stdout-path = &uart0; | ||
| 17 | linux,initrd-start = <0x4500040>; | 18 | linux,initrd-start = <0x4500040>; |
| 18 | linux,initrd-end = <0x4800000>; | 19 | linux,initrd-end = <0x4800000>; |
| 19 | }; | 20 | }; |
| @@ -29,7 +30,7 @@ | |||
| 29 | }; | 30 | }; |
| 30 | 31 | ||
| 31 | ocp@f1000000 { | 32 | ocp@f1000000 { |
| 32 | pinctrl: pinctrl@10000 { | 33 | pinctrl: pin-controller@10000 { |
| 33 | pmx_button_reset: pmx-button-reset { | 34 | pmx_button_reset: pmx-button-reset { |
| 34 | marvell,pins = "mpp12"; | 35 | marvell,pins = "mpp12"; |
| 35 | marvell,function = "gpio"; | 36 | marvell,function = "gpio"; |
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 59e7a5adeedb..05291f3990d0 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | |||
| @@ -14,10 +14,11 @@ | |||
| 14 | 14 | ||
| 15 | chosen { | 15 | chosen { |
| 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 17 | stdout-path = &uart0; | ||
| 17 | }; | 18 | }; |
| 18 | 19 | ||
| 19 | ocp@f1000000 { | 20 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 21 | pinctrl: pin-controller@10000 { |
| 21 | pinctrl-0 = < &pmx_led_sata_brt_ctrl_1 | 22 | pinctrl-0 = < &pmx_led_sata_brt_ctrl_1 |
| 22 | &pmx_led_sata_brt_ctrl_2 | 23 | &pmx_led_sata_brt_ctrl_2 |
| 23 | &pmx_led_backup_brt_ctrl_1 | 24 | &pmx_led_backup_brt_ctrl_1 |
diff --git a/arch/arm/boot/dts/kirkwood-km_common.dtsi b/arch/arm/boot/dts/kirkwood-km_common.dtsi new file mode 100644 index 000000000000..8367c772c764 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-km_common.dtsi | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | / { | ||
| 2 | chosen { | ||
| 3 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | ||
| 4 | stdout-path = &uart0; | ||
| 5 | }; | ||
| 6 | |||
| 7 | mbus { | ||
| 8 | pcie-controller { | ||
| 9 | status = "okay"; | ||
| 10 | |||
| 11 | pcie@1,0 { | ||
| 12 | status = "okay"; | ||
| 13 | }; | ||
| 14 | }; | ||
| 15 | }; | ||
| 16 | |||
| 17 | ocp@f1000000 { | ||
| 18 | pinctrl: pin-controller@10000 { | ||
| 19 | pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >; | ||
| 20 | pinctrl-names = "default"; | ||
| 21 | |||
| 22 | pmx_i2c_gpio_sda: pmx-gpio-sda { | ||
| 23 | marvell,pins = "mpp8"; | ||
| 24 | marvell,function = "gpio"; | ||
| 25 | }; | ||
| 26 | pmx_i2c_gpio_scl: pmx-gpio-scl { | ||
| 27 | marvell,pins = "mpp9"; | ||
| 28 | marvell,function = "gpio"; | ||
| 29 | }; | ||
| 30 | }; | ||
| 31 | |||
| 32 | serial@12000 { | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | |||
| 37 | i2c@0 { | ||
| 38 | compatible = "i2c-gpio"; | ||
| 39 | gpios = < &gpio0 8 GPIO_ACTIVE_HIGH /* sda */ | ||
| 40 | &gpio0 9 GPIO_ACTIVE_HIGH>; /* scl */ | ||
| 41 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | ||
| 42 | }; | ||
| 43 | }; | ||
| 44 | |||
| 45 | &nand { | ||
| 46 | status = "okay"; | ||
| 47 | chip-delay = <25>; | ||
| 48 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-km_fixedeth.dts b/arch/arm/boot/dts/kirkwood-km_fixedeth.dts new file mode 100644 index 000000000000..9895f2b10f8a --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-km_fixedeth.dts | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | #include "kirkwood.dtsi" | ||
| 4 | #include "kirkwood-98dx4122.dtsi" | ||
| 5 | #include "kirkwood-km_common.dtsi" | ||
| 6 | |||
| 7 | / { | ||
| 8 | model = "Keymile Kirkwood Fixed Eth"; | ||
| 9 | compatible = "keymile,km_fixedeth", "marvell,kirkwood-98DX4122", "marvell,kirkwood"; | ||
| 10 | |||
| 11 | memory { | ||
| 12 | device_type = "memory"; | ||
| 13 | reg = <0x00000000 0x10000000>; | ||
| 14 | }; | ||
| 15 | }; | ||
| 16 | |||
| 17 | ð0 { | ||
| 18 | status = "okay"; | ||
| 19 | ethernet0-port@0 { | ||
| 20 | speed = <1000>; /* <SPEED_1000> */ | ||
| 21 | duplex = <1>; /* <DUPLEX_FULL> */ | ||
| 22 | }; | ||
| 23 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts index 04a1e44541b3..235bf382fff9 100644 --- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts | |||
| @@ -2,6 +2,7 @@ | |||
| 2 | 2 | ||
| 3 | #include "kirkwood.dtsi" | 3 | #include "kirkwood.dtsi" |
| 4 | #include "kirkwood-98dx4122.dtsi" | 4 | #include "kirkwood-98dx4122.dtsi" |
| 5 | #include "kirkwood-km_common.dtsi" | ||
| 5 | 6 | ||
| 6 | / { | 7 | / { |
| 7 | model = "Keymile Kirkwood Reference Design"; | 8 | model = "Keymile Kirkwood Reference Design"; |
| @@ -11,44 +12,6 @@ | |||
| 11 | device_type = "memory"; | 12 | device_type = "memory"; |
| 12 | reg = <0x00000000 0x08000000>; | 13 | reg = <0x00000000 0x08000000>; |
| 13 | }; | 14 | }; |
| 14 | |||
| 15 | chosen { | ||
| 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | ||
| 17 | }; | ||
| 18 | |||
| 19 | ocp@f1000000 { | ||
| 20 | pinctrl: pinctrl@10000 { | ||
| 21 | pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >; | ||
| 22 | pinctrl-names = "default"; | ||
| 23 | |||
| 24 | pmx_i2c_gpio_sda: pmx-gpio-sda { | ||
| 25 | marvell,pins = "mpp8"; | ||
| 26 | marvell,function = "gpio"; | ||
| 27 | }; | ||
| 28 | pmx_i2c_gpio_scl: pmx-gpio-scl { | ||
| 29 | marvell,pins = "mpp9"; | ||
| 30 | marvell,function = "gpio"; | ||
| 31 | }; | ||
| 32 | }; | ||
| 33 | |||
| 34 | serial@12000 { | ||
| 35 | status = "ok"; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | |||
| 39 | i2c@0 { | ||
| 40 | compatible = "i2c-gpio"; | ||
| 41 | gpios = < &gpio0 8 GPIO_ACTIVE_HIGH /* sda */ | ||
| 42 | &gpio0 9 GPIO_ACTIVE_HIGH>; /* scl */ | ||
| 43 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | |||
| 47 | &nand { | ||
| 48 | pinctrl-0 = <&pmx_nand>; | ||
| 49 | pinctrl-names = "default"; | ||
| 50 | status = "ok"; | ||
| 51 | chip-delay = <25>; | ||
| 52 | }; | 15 | }; |
| 53 | 16 | ||
| 54 | &mdio { | 17 | &mdio { |
diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts index 6761ffa2c4ab..24425660e973 100644 --- a/arch/arm/boot/dts/kirkwood-laplug.dts +++ b/arch/arm/boot/dts/kirkwood-laplug.dts | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | 24 | ||
| 25 | chosen { | 25 | chosen { |
| 26 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 26 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 27 | stdout-path = &uart0; | ||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | mbus { | 30 | mbus { |
| @@ -37,14 +38,10 @@ | |||
| 37 | 38 | ||
| 38 | ocp@f1000000 { | 39 | ocp@f1000000 { |
| 39 | serial@12000 { | 40 | serial@12000 { |
| 40 | pinctrl-0 = <&pmx_uart0>; | ||
| 41 | pinctrl-names = "default"; | ||
| 42 | status = "okay"; | 41 | status = "okay"; |
| 43 | }; | 42 | }; |
| 44 | 43 | ||
| 45 | i2c@11000 { | 44 | i2c@11000 { |
| 46 | pinctrl-0 = <&pmx_twsi0>; | ||
| 47 | pinctrl-names = "default"; | ||
| 48 | status = "okay"; | 45 | status = "okay"; |
| 49 | 46 | ||
| 50 | eeprom@50 { | 47 | eeprom@50 { |
| @@ -54,7 +51,7 @@ | |||
| 54 | }; | 51 | }; |
| 55 | }; | 52 | }; |
| 56 | 53 | ||
| 57 | pinctrl: pinctrl@10000 { | 54 | pinctrl: pin-controller@10000 { |
| 58 | pmx_usb_power_enable: pmx-usb-power-enable { | 55 | pmx_usb_power_enable: pmx-usb-power-enable { |
| 59 | marvell,pins = "mpp14"; | 56 | marvell,pins = "mpp14"; |
| 60 | marvell,function = "gpio"; | 57 | marvell,function = "gpio"; |
| @@ -139,7 +136,6 @@ | |||
| 139 | &nand { | 136 | &nand { |
| 140 | /* Total size : 512MB */ | 137 | /* Total size : 512MB */ |
| 141 | status = "okay"; | 138 | status = "okay"; |
| 142 | pinctrl-0 = <&pmx_nand>; | ||
| 143 | 139 | ||
| 144 | partition@0 { | 140 | partition@0 { |
| 145 | label = "u-boot"; | 141 | label = "u-boot"; |
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index 1656653d339b..53484474df1f 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi | |||
| @@ -4,10 +4,11 @@ | |||
| 4 | / { | 4 | / { |
| 5 | chosen { | 5 | chosen { |
| 6 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 6 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 7 | stdout-path = &uart0; | ||
| 7 | }; | 8 | }; |
| 8 | 9 | ||
| 9 | ocp@f1000000 { | 10 | ocp@f1000000 { |
| 10 | pinctrl: pinctrl@10000 { | 11 | pinctrl: pin-controller@10000 { |
| 11 | pmx_power_hdd: pmx-power-hdd { | 12 | pmx_power_hdd: pmx-power-hdd { |
| 12 | marvell,pins = "mpp10"; | 13 | marvell,pins = "mpp10"; |
| 13 | marvell,function = "gpo"; | 14 | marvell,function = "gpo"; |
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index 73722c067501..f3a991837515 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts | |||
| @@ -12,9 +12,10 @@ | |||
| 12 | reg = <0x00000000 0x20000000>; | 12 | reg = <0x00000000 0x20000000>; |
| 13 | }; | 13 | }; |
| 14 | 14 | ||
| 15 | chosen { | 15 | chosen { |
| 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 17 | }; | 17 | stdout-path = &uart0; |
| 18 | }; | ||
| 18 | 19 | ||
| 19 | mbus { | 20 | mbus { |
| 20 | pcie-controller { | 21 | pcie-controller { |
| @@ -27,7 +28,7 @@ | |||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | ocp@f1000000 { | 30 | ocp@f1000000 { |
| 30 | pinctrl: pinctrl@10000 { | 31 | pinctrl: pin-controller@10000 { |
| 31 | pmx_led_health: pmx-led-health { | 32 | pmx_led_health: pmx-led-health { |
| 32 | marvell,pins = "mpp7"; | 33 | marvell,pins = "mpp7"; |
| 33 | marvell,function = "gpo"; | 34 | marvell,function = "gpo"; |
| @@ -89,11 +90,9 @@ | |||
| 89 | 90 | ||
| 90 | }; | 91 | }; |
| 91 | 92 | ||
| 92 | serial@12000 { | 93 | serial@12000 { |
| 93 | status = "ok"; | 94 | status = "okay"; |
| 94 | pinctrl-0 = <&pmx_uart0>; | 95 | }; |
| 95 | pinctrl-names = "default"; | ||
| 96 | }; | ||
| 97 | 96 | ||
| 98 | rtc@10300 { | 97 | rtc@10300 { |
| 99 | status = "disabled"; | 98 | status = "disabled"; |
| @@ -163,8 +162,6 @@ | |||
| 163 | }; | 162 | }; |
| 164 | 163 | ||
| 165 | &nand { | 164 | &nand { |
| 166 | pinctrl-0 = <&pmx_nand>; | ||
| 167 | pinctrl-names = "default"; | ||
| 168 | status = "okay"; | 165 | status = "okay"; |
| 169 | 166 | ||
| 170 | partition@0 { | 167 | partition@0 { |
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index b939f4f52d16..8f76d28759a3 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | 28 | ||
| 29 | chosen { | 29 | chosen { |
| 30 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 30 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 31 | stdout-path = &uart0; | ||
| 31 | }; | 32 | }; |
| 32 | 33 | ||
| 33 | mbus { | 34 | mbus { |
| @@ -41,7 +42,7 @@ | |||
| 41 | }; | 42 | }; |
| 42 | 43 | ||
| 43 | ocp@f1000000 { | 44 | ocp@f1000000 { |
| 44 | pinctrl@10000 { | 45 | pin-controller@10000 { |
| 45 | pmx_usb_led: pmx-usb-led { | 46 | pmx_usb_led: pmx-usb-led { |
| 46 | marvell,pins = "mpp12"; | 47 | marvell,pins = "mpp12"; |
| 47 | marvell,function = "gpo"; | 48 | marvell,function = "gpo"; |
| @@ -59,8 +60,6 @@ | |||
| 59 | }; | 60 | }; |
| 60 | 61 | ||
| 61 | spi@10600 { | 62 | spi@10600 { |
| 62 | pinctrl-0 = <&pmx_spi>; | ||
| 63 | pinctrl-names = "default"; | ||
| 64 | status = "okay"; | 63 | status = "okay"; |
| 65 | 64 | ||
| 66 | flash@0 { | 65 | flash@0 { |
| @@ -74,10 +73,7 @@ | |||
| 74 | }; | 73 | }; |
| 75 | 74 | ||
| 76 | serial@12000 { | 75 | serial@12000 { |
| 77 | pinctrl-0 = <&pmx_uart0>; | 76 | status = "okay"; |
| 78 | pinctrl-names = "default"; | ||
| 79 | clock-frequency = <200000000>; | ||
| 80 | status = "ok"; | ||
| 81 | }; | 77 | }; |
| 82 | 78 | ||
| 83 | ehci@50000 { | 79 | ehci@50000 { |
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index 4838478019cc..fd733c63bc27 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | 25 | ||
| 26 | chosen { | 26 | chosen { |
| 27 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 27 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 28 | stdout-path = &uart0; | ||
| 28 | }; | 29 | }; |
| 29 | 30 | ||
| 30 | mbus { | 31 | mbus { |
| @@ -38,7 +39,7 @@ | |||
| 38 | }; | 39 | }; |
| 39 | 40 | ||
| 40 | ocp@f1000000 { | 41 | ocp@f1000000 { |
| 41 | pinctrl: pinctrl@10000 { | 42 | pinctrl: pin-controller@10000 { |
| 42 | pmx_button_power: pmx-button-power { | 43 | pmx_button_power: pmx-button-power { |
| 43 | marvell,pins = "mpp47"; | 44 | marvell,pins = "mpp47"; |
| 44 | marvell,function = "gpio"; | 45 | marvell,function = "gpio"; |
| @@ -112,8 +113,6 @@ | |||
| 112 | }; | 113 | }; |
| 113 | 114 | ||
| 114 | serial@12000 { | 115 | serial@12000 { |
| 115 | pinctrl-0 = <&pmx_uart0>; | ||
| 116 | pinctrl-names = "default"; | ||
| 117 | status = "okay"; | 116 | status = "okay"; |
| 118 | }; | 117 | }; |
| 119 | 118 | ||
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts index 7c8a0d9d8d1f..b514d643fb6c 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | 25 | ||
| 26 | chosen { | 26 | chosen { |
| 27 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 27 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 28 | stdout-path = &uart0; | ||
| 28 | }; | 29 | }; |
| 29 | 30 | ||
| 30 | mbus { | 31 | mbus { |
| @@ -40,7 +41,7 @@ | |||
| 40 | }; | 41 | }; |
| 41 | 42 | ||
| 42 | ocp@f1000000 { | 43 | ocp@f1000000 { |
| 43 | pinctrl: pinctrl@10000 { | 44 | pinctrl: pin-controller@10000 { |
| 44 | pmx_button_power: pmx-button-power { | 45 | pmx_button_power: pmx-button-power { |
| 45 | marvell,pins = "mpp47"; | 46 | marvell,pins = "mpp47"; |
| 46 | marvell,function = "gpio"; | 47 | marvell,function = "gpio"; |
| @@ -119,8 +120,6 @@ | |||
| 119 | }; | 120 | }; |
| 120 | 121 | ||
| 121 | serial@12000 { | 122 | serial@12000 { |
| 122 | pinctrl-0 = <&pmx_uart0>; | ||
| 123 | pinctrl-names = "default"; | ||
| 124 | status = "okay"; | 123 | status = "okay"; |
| 125 | }; | 124 | }; |
| 126 | 125 | ||
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index e6e5ec4fe6b9..fe6c0246db1a 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi | |||
| @@ -4,10 +4,11 @@ | |||
| 4 | / { | 4 | / { |
| 5 | chosen { | 5 | chosen { |
| 6 | bootargs = "console=ttyS0,115200n8"; | 6 | bootargs = "console=ttyS0,115200n8"; |
| 7 | stdout-path = &uart0; | ||
| 7 | }; | 8 | }; |
| 8 | 9 | ||
| 9 | ocp@f1000000 { | 10 | ocp@f1000000 { |
| 10 | pinctrl: pinctrl@10000 { | 11 | pinctrl: pin-controller@10000 { |
| 11 | pmx_ns2_sata0: pmx-ns2-sata0 { | 12 | pmx_ns2_sata0: pmx-ns2-sata0 { |
| 12 | marvell,pins = "mpp21"; | 13 | marvell,pins = "mpp21"; |
| 13 | marvell,function = "sata0"; | 14 | marvell,function = "sata0"; |
| @@ -19,14 +20,10 @@ | |||
| 19 | }; | 20 | }; |
| 20 | 21 | ||
| 21 | serial@12000 { | 22 | serial@12000 { |
| 22 | pinctrl-0 = <&pmx_uart0>; | ||
| 23 | pinctrl-names = "default"; | ||
| 24 | status = "okay"; | 23 | status = "okay"; |
| 25 | }; | 24 | }; |
| 26 | 25 | ||
| 27 | spi@10600 { | 26 | spi@10600 { |
| 28 | pinctrl-0 = <&pmx_spi>; | ||
| 29 | pinctrl-names = "default"; | ||
| 30 | status = "okay"; | 27 | status = "okay"; |
| 31 | 28 | ||
| 32 | flash@0 { | 29 | flash@0 { |
| @@ -45,8 +42,6 @@ | |||
| 45 | }; | 42 | }; |
| 46 | 43 | ||
| 47 | i2c@11000 { | 44 | i2c@11000 { |
| 48 | pinctrl-0 = <&pmx_twsi0>; | ||
| 49 | pinctrl-names = "default"; | ||
| 50 | status = "okay"; | 45 | status = "okay"; |
| 51 | 46 | ||
| 52 | eeprom@50 { | 47 | eeprom@50 { |
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index 0a07af9d8e58..6139df0f376c 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | #include "kirkwood-nsa310-common.dtsi" | 3 | #include "kirkwood-nsa3x0-common.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; | 6 | compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; |
| @@ -12,6 +12,7 @@ | |||
| 12 | 12 | ||
| 13 | chosen { | 13 | chosen { |
| 14 | bootargs = "console=ttyS0,115200"; | 14 | bootargs = "console=ttyS0,115200"; |
| 15 | stdout-path = &uart0; | ||
| 15 | }; | 16 | }; |
| 16 | 17 | ||
| 17 | mbus { | 18 | mbus { |
| @@ -25,7 +26,7 @@ | |||
| 25 | }; | 26 | }; |
| 26 | 27 | ||
| 27 | ocp@f1000000 { | 28 | ocp@f1000000 { |
| 28 | pinctrl: pinctrl@10000 { | 29 | pinctrl: pin-controller@10000 { |
| 29 | pinctrl-0 = <&pmx_unknown>; | 30 | pinctrl-0 = <&pmx_unknown>; |
| 30 | pinctrl-names = "default"; | 31 | pinctrl-names = "default"; |
| 31 | 32 | ||
| @@ -59,26 +60,6 @@ | |||
| 59 | marvell,function = "gpio"; | 60 | marvell,function = "gpio"; |
| 60 | }; | 61 | }; |
| 61 | 62 | ||
| 62 | pmx_btn_reset: pmx-btn-reset { | ||
| 63 | marvell,pins = "mpp36"; | ||
| 64 | marvell,function = "gpio"; | ||
| 65 | }; | ||
| 66 | |||
| 67 | pmx_btn_copy: pmx-btn-copy { | ||
| 68 | marvell,pins = "mpp37"; | ||
| 69 | marvell,function = "gpio"; | ||
| 70 | }; | ||
| 71 | |||
| 72 | pmx_led_copy_green: pmx-led-copy-green { | ||
| 73 | marvell,pins = "mpp39"; | ||
| 74 | marvell,function = "gpio"; | ||
| 75 | }; | ||
| 76 | |||
| 77 | pmx_led_copy_red: pmx-led-copy-red { | ||
| 78 | marvell,pins = "mpp40"; | ||
| 79 | marvell,function = "gpio"; | ||
| 80 | }; | ||
| 81 | |||
| 82 | pmx_led_hdd_green: pmx-led-hdd-green { | 63 | pmx_led_hdd_green: pmx-led-hdd-green { |
| 83 | marvell,pins = "mpp41"; | 64 | marvell,pins = "mpp41"; |
| 84 | marvell,function = "gpio"; | 65 | marvell,function = "gpio"; |
| @@ -94,10 +75,6 @@ | |||
| 94 | marvell,function = "gpio"; | 75 | marvell,function = "gpio"; |
| 95 | }; | 76 | }; |
| 96 | 77 | ||
| 97 | pmx_btn_power: pmx-btn-power { | ||
| 98 | marvell,pins = "mpp46"; | ||
| 99 | marvell,function = "gpio"; | ||
| 100 | }; | ||
| 101 | }; | 78 | }; |
| 102 | 79 | ||
| 103 | i2c@11000 { | 80 | i2c@11000 { |
| @@ -110,30 +87,6 @@ | |||
| 110 | }; | 87 | }; |
| 111 | }; | 88 | }; |
| 112 | 89 | ||
| 113 | gpio_keys { | ||
| 114 | compatible = "gpio-keys"; | ||
| 115 | #address-cells = <1>; | ||
| 116 | #size-cells = <0>; | ||
| 117 | pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; | ||
| 118 | pinctrl-names = "default"; | ||
| 119 | |||
| 120 | button@1 { | ||
| 121 | label = "Power Button"; | ||
| 122 | linux,code = <KEY_POWER>; | ||
| 123 | gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; | ||
| 124 | }; | ||
| 125 | button@2 { | ||
| 126 | label = "Copy Button"; | ||
| 127 | linux,code = <KEY_COPY>; | ||
| 128 | gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; | ||
| 129 | }; | ||
| 130 | button@3 { | ||
| 131 | label = "Reset Button"; | ||
| 132 | linux,code = <KEY_RESTART>; | ||
| 133 | gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; | ||
| 134 | }; | ||
| 135 | }; | ||
| 136 | |||
| 137 | gpio-leds { | 90 | gpio-leds { |
| 138 | compatible = "gpio-leds"; | 91 | compatible = "gpio-leds"; |
| 139 | pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red | 92 | pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red |
diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts index 27ca6a79c48a..3d2b3d494c19 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310a.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | #include "kirkwood-nsa310-common.dtsi" | 3 | #include "kirkwood-nsa3x0-common.dtsi" |
| 4 | 4 | ||
| 5 | /* | 5 | /* |
| 6 | * There are at least two different NSA310 designs. This variant does | 6 | * There are at least two different NSA310 designs. This variant does |
| @@ -17,10 +17,11 @@ | |||
| 17 | 17 | ||
| 18 | chosen { | 18 | chosen { |
| 19 | bootargs = "console=ttyS0,115200"; | 19 | bootargs = "console=ttyS0,115200"; |
| 20 | stdout-path = &uart0; | ||
| 20 | }; | 21 | }; |
| 21 | 22 | ||
| 22 | ocp@f1000000 { | 23 | ocp@f1000000 { |
| 23 | pinctrl: pinctrl@10000 { | 24 | pinctrl: pin-controller@10000 { |
| 24 | pinctrl-names = "default"; | 25 | pinctrl-names = "default"; |
| 25 | 26 | ||
| 26 | pmx_led_esata_green: pmx-led-esata-green { | 27 | pmx_led_esata_green: pmx-led-esata-green { |
| @@ -38,11 +39,6 @@ | |||
| 38 | marvell,function = "gpio"; | 39 | marvell,function = "gpio"; |
| 39 | }; | 40 | }; |
| 40 | 41 | ||
| 41 | pmx_usb_power_off: pmx-usb-power-off { | ||
| 42 | marvell,pins = "mpp21"; | ||
| 43 | marvell,function = "gpio"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | pmx_led_sys_green: pmx-led-sys-green { | 42 | pmx_led_sys_green: pmx-led-sys-green { |
| 47 | marvell,pins = "mpp28"; | 43 | marvell,pins = "mpp28"; |
| 48 | marvell,function = "gpio"; | 44 | marvell,function = "gpio"; |
| @@ -53,26 +49,6 @@ | |||
| 53 | marvell,function = "gpio"; | 49 | marvell,function = "gpio"; |
| 54 | }; | 50 | }; |
| 55 | 51 | ||
| 56 | pmx_btn_reset: pmx-btn-reset { | ||
| 57 | marvell,pins = "mpp36"; | ||
| 58 | marvell,function = "gpio"; | ||
| 59 | }; | ||
| 60 | |||
| 61 | pmx_btn_copy: pmx-btn-copy { | ||
| 62 | marvell,pins = "mpp37"; | ||
| 63 | marvell,function = "gpio"; | ||
| 64 | }; | ||
| 65 | |||
| 66 | pmx_led_copy_green: pmx-led-copy-green { | ||
| 67 | marvell,pins = "mpp39"; | ||
| 68 | marvell,function = "gpio"; | ||
| 69 | }; | ||
| 70 | |||
| 71 | pmx_led_copy_red: pmx-led-copy-red { | ||
| 72 | marvell,pins = "mpp40"; | ||
| 73 | marvell,function = "gpio"; | ||
| 74 | }; | ||
| 75 | |||
| 76 | pmx_led_hdd_green: pmx-led-hdd-green { | 52 | pmx_led_hdd_green: pmx-led-hdd-green { |
| 77 | marvell,pins = "mpp41"; | 53 | marvell,pins = "mpp41"; |
| 78 | marvell,function = "gpio"; | 54 | marvell,function = "gpio"; |
| @@ -83,11 +59,6 @@ | |||
| 83 | marvell,function = "gpio"; | 59 | marvell,function = "gpio"; |
| 84 | }; | 60 | }; |
| 85 | 61 | ||
| 86 | pmx_btn_power: pmx-btn-power { | ||
| 87 | marvell,pins = "mpp46"; | ||
| 88 | marvell,function = "gpio"; | ||
| 89 | }; | ||
| 90 | |||
| 91 | }; | 62 | }; |
| 92 | 63 | ||
| 93 | i2c@11000 { | 64 | i2c@11000 { |
| @@ -100,28 +71,6 @@ | |||
| 100 | }; | 71 | }; |
| 101 | }; | 72 | }; |
| 102 | 73 | ||
| 103 | gpio_keys { | ||
| 104 | compatible = "gpio-keys"; | ||
| 105 | #address-cells = <1>; | ||
| 106 | #size-cells = <0>; | ||
| 107 | |||
| 108 | button@1 { | ||
| 109 | label = "Power Button"; | ||
| 110 | linux,code = <KEY_POWER>; | ||
| 111 | gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; | ||
| 112 | }; | ||
| 113 | button@2 { | ||
| 114 | label = "Copy Button"; | ||
| 115 | linux,code = <KEY_COPY>; | ||
| 116 | gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; | ||
| 117 | }; | ||
| 118 | button@3 { | ||
| 119 | label = "Reset Button"; | ||
| 120 | linux,code = <KEY_RESTART>; | ||
| 121 | gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; | ||
| 122 | }; | ||
| 123 | }; | ||
| 124 | |||
| 125 | gpio-leds { | 74 | gpio-leds { |
| 126 | compatible = "gpio-leds"; | 75 | compatible = "gpio-leds"; |
| 127 | 76 | ||
diff --git a/arch/arm/boot/dts/kirkwood-nsa320.dts b/arch/arm/boot/dts/kirkwood-nsa320.dts new file mode 100644 index 000000000000..24f686d1044d --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-nsa320.dts | |||
| @@ -0,0 +1,215 @@ | |||
| 1 | /* Device tree file for the Zyxel NSA 320 NAS box. | ||
| 2 | * | ||
| 3 | * Copyright (c) 2014, Adam Baker <linux@baker-net.org.uk> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version | ||
| 8 | * 2 of the License, or (at your option) any later version. | ||
| 9 | * | ||
| 10 | * Based upon the board setup file created by Peter Schildmann */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | |||
| 14 | #include "kirkwood-nsa3x0-common.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Zyxel NSA320"; | ||
| 18 | compatible = "zyxel,nsa320", "marvell,kirkwood-88f6281", "marvell,kirkwood"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | device_type = "memory"; | ||
| 22 | reg = <0x00000000 0x20000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | chosen { | ||
| 26 | bootargs = "console=ttyS0,115200"; | ||
| 27 | stdout-path = &uart0; | ||
| 28 | }; | ||
| 29 | |||
| 30 | mbus { | ||
| 31 | pcie-controller { | ||
| 32 | status = "okay"; | ||
| 33 | |||
| 34 | pcie@1,0 { | ||
| 35 | status = "okay"; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | |||
| 40 | ocp@f1000000 { | ||
| 41 | pinctrl: pin-controller@10000 { | ||
| 42 | pinctrl-names = "default"; | ||
| 43 | |||
| 44 | /* SATA Activity and Present pins are not connected */ | ||
| 45 | pmx_sata0: pmx-sata0 { | ||
| 46 | marvell,pins ; | ||
| 47 | marvell,function = "sata0"; | ||
| 48 | }; | ||
| 49 | |||
| 50 | pmx_sata1: pmx-sata1 { | ||
| 51 | marvell,pins ; | ||
| 52 | marvell,function = "sata1"; | ||
| 53 | }; | ||
| 54 | |||
| 55 | pmx_led_hdd2_green: pmx-led-hdd2-green { | ||
| 56 | marvell,pins = "mpp12"; | ||
| 57 | marvell,function = "gpio"; | ||
| 58 | }; | ||
| 59 | |||
| 60 | pmx_led_hdd2_red: pmx-led-hdd2-red { | ||
| 61 | marvell,pins = "mpp13"; | ||
| 62 | marvell,function = "gpio"; | ||
| 63 | }; | ||
| 64 | |||
| 65 | pmx_mcu_data: pmx-mcu-data { | ||
| 66 | marvell,pins = "mpp14"; | ||
| 67 | marvell,function = "gpio"; | ||
| 68 | }; | ||
| 69 | |||
| 70 | pmx_led_usb_green: pmx-led-usb-green { | ||
| 71 | marvell,pins = "mpp15"; | ||
| 72 | marvell,function = "gpio"; | ||
| 73 | }; | ||
| 74 | |||
| 75 | pmx_mcu_clk: pmx-mcu-clk { | ||
| 76 | marvell,pins = "mpp16"; | ||
| 77 | marvell,function = "gpio"; | ||
| 78 | }; | ||
| 79 | |||
| 80 | pmx_mcu_act: pmx-mcu-act { | ||
| 81 | marvell,pins = "mpp17"; | ||
| 82 | marvell,function = "gpio"; | ||
| 83 | }; | ||
| 84 | |||
| 85 | pmx_led_sys_green: pmx-led-sys-green { | ||
| 86 | marvell,pins = "mpp28"; | ||
| 87 | marvell,function = "gpio"; | ||
| 88 | }; | ||
| 89 | |||
| 90 | pmx_led_sys_orange: pmx-led-sys-orange { | ||
| 91 | marvell,pins = "mpp29"; | ||
| 92 | marvell,function = "gpio"; | ||
| 93 | }; | ||
| 94 | |||
| 95 | pmx_led_hdd1_green: pmx-led-hdd1-green { | ||
| 96 | marvell,pins = "mpp41"; | ||
| 97 | marvell,function = "gpio"; | ||
| 98 | }; | ||
| 99 | |||
| 100 | pmx_led_hdd1_red: pmx-led-hdd1-red { | ||
| 101 | marvell,pins = "mpp42"; | ||
| 102 | marvell,function = "gpio"; | ||
| 103 | }; | ||
| 104 | |||
| 105 | pmx_htp: pmx-htp { | ||
| 106 | marvell,pins = "mpp43"; | ||
| 107 | marvell,function = "gpio"; | ||
| 108 | }; | ||
| 109 | |||
| 110 | /* Buzzer needs to be switched at around 1kHz so is | ||
| 111 | not compatible with the gpio-beeper driver. */ | ||
| 112 | pmx_buzzer: pmx-buzzer { | ||
| 113 | marvell,pins = "mpp44"; | ||
| 114 | marvell,function = "gpio"; | ||
| 115 | }; | ||
| 116 | |||
| 117 | pmx_vid_b1: pmx-vid-b1 { | ||
| 118 | marvell,pins = "mpp45"; | ||
| 119 | marvell,function = "gpio"; | ||
| 120 | }; | ||
| 121 | |||
| 122 | pmx_power_resume_data: pmx-power-resume-data { | ||
| 123 | marvell,pins = "mpp47"; | ||
| 124 | marvell,function = "gpio"; | ||
| 125 | }; | ||
| 126 | |||
| 127 | pmx_power_resume_clk: pmx-power-resume-clk { | ||
| 128 | marvell,pins = "mpp49"; | ||
| 129 | marvell,function = "gpio"; | ||
| 130 | }; | ||
| 131 | }; | ||
| 132 | |||
| 133 | i2c@11000 { | ||
| 134 | status = "okay"; | ||
| 135 | |||
| 136 | pcf8563: pcf8563@51 { | ||
| 137 | compatible = "nxp,pcf8563"; | ||
| 138 | reg = <0x51>; | ||
| 139 | }; | ||
| 140 | }; | ||
| 141 | }; | ||
| 142 | |||
| 143 | regulators { | ||
| 144 | usb0_power: regulator@1 { | ||
| 145 | enable-active-high; | ||
| 146 | }; | ||
| 147 | }; | ||
| 148 | |||
| 149 | gpio-leds { | ||
| 150 | compatible = "gpio-leds"; | ||
| 151 | pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red | ||
| 152 | &pmx_led_usb_green | ||
| 153 | &pmx_led_sys_green &pmx_led_sys_orange | ||
| 154 | &pmx_led_copy_green &pmx_led_copy_red | ||
| 155 | &pmx_led_hdd1_green &pmx_led_hdd1_red>; | ||
| 156 | pinctrl-names = "default"; | ||
| 157 | |||
| 158 | green-sys { | ||
| 159 | label = "nsa320:green:sys"; | ||
| 160 | gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; | ||
| 161 | }; | ||
| 162 | orange-sys { | ||
| 163 | label = "nsa320:orange:sys"; | ||
| 164 | gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; | ||
| 165 | }; | ||
| 166 | green-hdd1 { | ||
| 167 | label = "nsa320:green:hdd1"; | ||
| 168 | gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; | ||
| 169 | }; | ||
| 170 | red-hdd1 { | ||
| 171 | label = "nsa320:red:hdd1"; | ||
| 172 | gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; | ||
| 173 | }; | ||
| 174 | green-hdd2 { | ||
| 175 | label = "nsa320:green:hdd2"; | ||
| 176 | gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; | ||
| 177 | }; | ||
| 178 | red-hdd2 { | ||
| 179 | label = "nsa320:red:hdd2"; | ||
| 180 | gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; | ||
| 181 | }; | ||
| 182 | green-usb { | ||
| 183 | label = "nsa320:green:usb"; | ||
| 184 | gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; | ||
| 185 | }; | ||
| 186 | green-copy { | ||
| 187 | label = "nsa320:green:copy"; | ||
| 188 | gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; | ||
| 189 | }; | ||
| 190 | red-copy { | ||
| 191 | label = "nsa320:red:copy"; | ||
| 192 | gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; | ||
| 193 | }; | ||
| 194 | }; | ||
| 195 | |||
| 196 | /* The following pins are currently not assigned to a driver, | ||
| 197 | some of them should be configured as inputs. | ||
| 198 | pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act | ||
| 199 | &pmx_htp &pmx_vid_b1 | ||
| 200 | &pmx_power_resume_data &pmx_power_resume_clk>; */ | ||
| 201 | }; | ||
| 202 | |||
| 203 | &mdio { | ||
| 204 | status = "okay"; | ||
| 205 | ethphy0: ethernet-phy@1 { | ||
| 206 | reg = <1>; | ||
| 207 | }; | ||
| 208 | }; | ||
| 209 | |||
| 210 | ð0 { | ||
| 211 | status = "okay"; | ||
| 212 | ethernet0-port@0 { | ||
| 213 | phy-handle = <ðphy0>; | ||
| 214 | }; | ||
| 215 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi index e2cc85cc3b87..2075a2e828f1 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi | |||
| @@ -15,17 +15,42 @@ | |||
| 15 | }; | 15 | }; |
| 16 | 16 | ||
| 17 | ocp@f1000000 { | 17 | ocp@f1000000 { |
| 18 | pinctrl: pinctrl@10000 { | 18 | pinctrl: pin-controller@10000 { |
| 19 | 19 | ||
| 20 | pmx_usb_power_off: pmx-usb-power-off { | 20 | pmx_usb_power: pmx-usb-power { |
| 21 | marvell,pins = "mpp21"; | 21 | marvell,pins = "mpp21"; |
| 22 | marvell,function = "gpio"; | 22 | marvell,function = "gpio"; |
| 23 | }; | 23 | }; |
| 24 | |||
| 24 | pmx_pwr_off: pmx-pwr-off { | 25 | pmx_pwr_off: pmx-pwr-off { |
| 25 | marvell,pins = "mpp48"; | 26 | marvell,pins = "mpp48"; |
| 26 | marvell,function = "gpio"; | 27 | marvell,function = "gpio"; |
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 30 | pmx_btn_reset: pmx-btn-reset { | ||
| 31 | marvell,pins = "mpp36"; | ||
| 32 | marvell,function = "gpio"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | pmx_btn_copy: pmx-btn-copy { | ||
| 36 | marvell,pins = "mpp37"; | ||
| 37 | marvell,function = "gpio"; | ||
| 38 | }; | ||
| 39 | |||
| 40 | pmx_btn_power: pmx-btn-power { | ||
| 41 | marvell,pins = "mpp46"; | ||
| 42 | marvell,function = "gpio"; | ||
| 43 | }; | ||
| 44 | |||
| 45 | pmx_led_copy_green: pmx-led-copy-green { | ||
| 46 | marvell,pins = "mpp39"; | ||
| 47 | marvell,function = "gpio"; | ||
| 48 | }; | ||
| 49 | |||
| 50 | pmx_led_copy_red: pmx-led-copy-red { | ||
| 51 | marvell,pins = "mpp40"; | ||
| 52 | marvell,function = "gpio"; | ||
| 53 | }; | ||
| 29 | }; | 54 | }; |
| 30 | 55 | ||
| 31 | serial@12000 { | 56 | serial@12000 { |
| @@ -45,17 +70,42 @@ | |||
| 45 | gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; | 70 | gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; |
| 46 | }; | 71 | }; |
| 47 | 72 | ||
| 73 | gpio_keys { | ||
| 74 | compatible = "gpio-keys"; | ||
| 75 | #address-cells = <1>; | ||
| 76 | #size-cells = <0>; | ||
| 77 | pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; | ||
| 78 | pinctrl-names = "default"; | ||
| 79 | |||
| 80 | button@1 { | ||
| 81 | label = "Power Button"; | ||
| 82 | linux,code = <KEY_POWER>; | ||
| 83 | gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; | ||
| 84 | }; | ||
| 85 | button@2 { | ||
| 86 | label = "Copy Button"; | ||
| 87 | linux,code = <KEY_COPY>; | ||
| 88 | gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; | ||
| 89 | }; | ||
| 90 | button@3 { | ||
| 91 | label = "Reset Button"; | ||
| 92 | linux,code = <KEY_RESTART>; | ||
| 93 | gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; | ||
| 94 | }; | ||
| 95 | }; | ||
| 96 | |||
| 97 | |||
| 48 | regulators { | 98 | regulators { |
| 49 | compatible = "simple-bus"; | 99 | compatible = "simple-bus"; |
| 50 | #address-cells = <1>; | 100 | #address-cells = <1>; |
| 51 | #size-cells = <0>; | 101 | #size-cells = <0>; |
| 52 | pinctrl-0 = <&pmx_usb_power_off>; | 102 | pinctrl-0 = <&pmx_usb_power>; |
| 53 | pinctrl-names = "default"; | 103 | pinctrl-names = "default"; |
| 54 | 104 | ||
| 55 | usb0_power_off: regulator@1 { | 105 | usb0_power: regulator@1 { |
| 56 | compatible = "regulator-fixed"; | 106 | compatible = "regulator-fixed"; |
| 57 | reg = <1>; | 107 | reg = <1>; |
| 58 | regulator-name = "USB Power Off"; | 108 | regulator-name = "USB Power"; |
| 59 | regulator-min-microvolt = <5000000>; | 109 | regulator-min-microvolt = <5000000>; |
| 60 | regulator-max-microvolt = <5000000>; | 110 | regulator-max-microvolt = <5000000>; |
| 61 | regulator-always-on; | 111 | regulator-always-on; |
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index 0650beafc1de..fb9dc227255d 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts | |||
| @@ -14,19 +14,16 @@ | |||
| 14 | 14 | ||
| 15 | chosen { | 15 | chosen { |
| 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 17 | stdout-path = &uart0; | ||
| 17 | }; | 18 | }; |
| 18 | 19 | ||
| 19 | ocp@f1000000 { | 20 | ocp@f1000000 { |
| 20 | serial@12000 { | 21 | serial@12000 { |
| 21 | status = "ok"; | 22 | status = "okay"; |
| 22 | pinctrl-0 = <&pmx_uart0>; | ||
| 23 | pinctrl-names = "default"; | ||
| 24 | }; | 23 | }; |
| 25 | 24 | ||
| 26 | serial@12100 { | 25 | serial@12100 { |
| 27 | status = "ok"; | 26 | status = "okay"; |
| 28 | pinctrl-0 = <&pmx_uart1>; | ||
| 29 | pinctrl-names = "default"; | ||
| 30 | }; | 27 | }; |
| 31 | 28 | ||
| 32 | sata@80000 { | 29 | sata@80000 { |
| @@ -36,8 +33,6 @@ | |||
| 36 | 33 | ||
| 37 | i2c@11100 { | 34 | i2c@11100 { |
| 38 | status = "okay"; | 35 | status = "okay"; |
| 39 | pinctrl-0 = <&pmx_twsi1>; | ||
| 40 | pinctrl-names = "default"; | ||
| 41 | 36 | ||
| 42 | s35390a: s35390a@30 { | 37 | s35390a: s35390a@30 { |
| 43 | compatible = "sii,s35390a"; | 38 | compatible = "sii,s35390a"; |
| @@ -45,7 +40,7 @@ | |||
| 45 | }; | 40 | }; |
| 46 | }; | 41 | }; |
| 47 | 42 | ||
| 48 | pinctrl: pinctrl@10000 { | 43 | pinctrl: pin-controller@10000 { |
| 49 | pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; | 44 | pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; |
| 50 | pinctrl-names = "default"; | 45 | pinctrl-names = "default"; |
| 51 | 46 | ||
| @@ -133,8 +128,6 @@ | |||
| 133 | &nand { | 128 | &nand { |
| 134 | chip-delay = <25>; | 129 | chip-delay = <25>; |
| 135 | status = "okay"; | 130 | status = "okay"; |
| 136 | pinctrl-0 = <&pmx_nand>; | ||
| 137 | pinctrl-names = "default"; | ||
| 138 | 131 | ||
| 139 | partition@0 { | 132 | partition@0 { |
| 140 | label = "uboot"; | 133 | label = "uboot"; |
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts index 38520a287514..d5e3bc518968 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts | |||
| @@ -26,19 +26,16 @@ | |||
| 26 | 26 | ||
| 27 | chosen { | 27 | chosen { |
| 28 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 28 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 29 | stdout-path = &uart0; | ||
| 29 | }; | 30 | }; |
| 30 | 31 | ||
| 31 | ocp@f1000000 { | 32 | ocp@f1000000 { |
| 32 | serial@12000 { | 33 | serial@12000 { |
| 33 | status = "ok"; | 34 | status = "okay"; |
| 34 | pinctrl-0 = <&pmx_uart0>; | ||
| 35 | pinctrl-names = "default"; | ||
| 36 | }; | 35 | }; |
| 37 | 36 | ||
| 38 | serial@12100 { | 37 | serial@12100 { |
| 39 | status = "ok"; | 38 | status = "okay"; |
| 40 | pinctrl-0 = <&pmx_uart1>; | ||
| 41 | pinctrl-names = "default"; | ||
| 42 | }; | 39 | }; |
| 43 | 40 | ||
| 44 | sata@80000 { | 41 | sata@80000 { |
| @@ -48,8 +45,6 @@ | |||
| 48 | 45 | ||
| 49 | i2c@11100 { | 46 | i2c@11100 { |
| 50 | status = "okay"; | 47 | status = "okay"; |
| 51 | pinctrl-0 = <&pmx_twsi1>; | ||
| 52 | pinctrl-names = "default"; | ||
| 53 | 48 | ||
| 54 | s24c02: s24c02@50 { | 49 | s24c02: s24c02@50 { |
| 55 | compatible = "atmel,24c02"; | 50 | compatible = "atmel,24c02"; |
| @@ -57,7 +52,7 @@ | |||
| 57 | }; | 52 | }; |
| 58 | }; | 53 | }; |
| 59 | 54 | ||
| 60 | pinctrl: pinctrl@10000 { | 55 | pinctrl: pin-controller@10000 { |
| 61 | pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; | 56 | pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; |
| 62 | pinctrl-names = "default"; | 57 | pinctrl-names = "default"; |
| 63 | 58 | ||
| @@ -109,13 +104,6 @@ | |||
| 109 | marvell,pins = "mpp41", "mpp42", "mpp43"; | 104 | marvell,pins = "mpp41", "mpp42", "mpp43"; |
| 110 | marvell,function = "gpio"; | 105 | marvell,function = "gpio"; |
| 111 | }; | 106 | }; |
| 112 | |||
| 113 | pmx_ge1: pmx-ge1 { | ||
| 114 | marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", | ||
| 115 | "mpp24", "mpp25", "mpp26", "mpp27", | ||
| 116 | "mpp30", "mpp31", "mpp32", "mpp33"; | ||
| 117 | marvell,function = "ge1"; | ||
| 118 | }; | ||
| 119 | }; | 107 | }; |
| 120 | }; | 108 | }; |
| 121 | 109 | ||
| @@ -158,8 +146,6 @@ | |||
| 158 | &nand { | 146 | &nand { |
| 159 | chip-delay = <25>; | 147 | chip-delay = <25>; |
| 160 | status = "okay"; | 148 | status = "okay"; |
| 161 | pinctrl-0 = <&pmx_nand>; | ||
| 162 | pinctrl-names = "default"; | ||
| 163 | 149 | ||
| 164 | partition@0 { | 150 | partition@0 { |
| 165 | label = "uboot"; | 151 | label = "uboot"; |
| @@ -213,8 +199,6 @@ | |||
| 213 | 199 | ||
| 214 | ð1 { | 200 | ð1 { |
| 215 | status = "okay"; | 201 | status = "okay"; |
| 216 | pinctrl-0 = <&pmx_ge1>; | ||
| 217 | pinctrl-names = "default"; | ||
| 218 | ethernet1-port@0 { | 202 | ethernet1-port@0 { |
| 219 | phy-handle = <ðphy1>; | 203 | phy-handle = <ðphy1>; |
| 220 | }; | 204 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-openrd-base.dts b/arch/arm/boot/dts/kirkwood-openrd-base.dts new file mode 100644 index 000000000000..8af58999606d --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-openrd-base.dts | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | /* | ||
| 2 | * Marvell OpenRD Base Board Description | ||
| 3 | * | ||
| 4 | * Andrew Lunn <andrew@lunn.ch> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | * | ||
| 10 | * This file contains the definitions that are specific to OpenRD | ||
| 11 | * base variant of the Marvell Kirkwood Development Board. | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | |||
| 16 | #include "kirkwood-openrd.dtsi" | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "OpenRD Base"; | ||
| 20 | compatible = "marvell,openrd-base", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; | ||
| 21 | |||
| 22 | ocp@f1000000 { | ||
| 23 | serial@12100 { | ||
| 24 | status = "okay"; | ||
| 25 | }; | ||
| 26 | }; | ||
| 27 | }; | ||
| 28 | |||
| 29 | &mdio { | ||
| 30 | status = "okay"; | ||
| 31 | |||
| 32 | ethphy0: ethernet-phy@8 { | ||
| 33 | reg = <8>; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | |||
| 37 | ð0 { | ||
| 38 | status = "okay"; | ||
| 39 | ethernet0-port@0 { | ||
| 40 | phy-handle = <ðphy0>; | ||
| 41 | }; | ||
| 42 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-openrd-client.dts b/arch/arm/boot/dts/kirkwood-openrd-client.dts new file mode 100644 index 000000000000..887b9c1fee43 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-openrd-client.dts | |||
| @@ -0,0 +1,73 @@ | |||
| 1 | /* | ||
| 2 | * Marvell OpenRD Client Board Description | ||
| 3 | * | ||
| 4 | * Andrew Lunn <andrew@lunn.ch> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | * | ||
| 10 | * This file contains the definitions that are specific to OpenRD | ||
| 11 | * client variant of the Marvell Kirkwood Development Board. | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | |||
| 16 | #include "kirkwood-openrd.dtsi" | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "OpenRD Client"; | ||
| 20 | compatible = "marvell,openrd-client", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; | ||
| 21 | |||
| 22 | ocp@f1000000 { | ||
| 23 | i2c@11000 { | ||
| 24 | status = "okay"; | ||
| 25 | clock-frequency = <400000>; | ||
| 26 | |||
| 27 | cs42l51: cs42l51@4a { | ||
| 28 | compatible = "cirrus,cs42l51"; | ||
| 29 | reg = <0x4a>; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | }; | ||
| 33 | |||
| 34 | sound { | ||
| 35 | compatible = "simple-audio-card"; | ||
| 36 | simple-audio-card,format = "i2s"; | ||
| 37 | simple-audio-card,mclk-fs = <256>; | ||
| 38 | |||
| 39 | simple-audio-card,cpu { | ||
| 40 | sound-dai = <&audio0>; | ||
| 41 | }; | ||
| 42 | |||
| 43 | simple-audio-card,codec { | ||
| 44 | sound-dai = <&cs42l51>; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | }; | ||
| 48 | |||
| 49 | &mdio { | ||
| 50 | status = "okay"; | ||
| 51 | |||
| 52 | ethphy0: ethernet-phy@8 { | ||
| 53 | reg = <8>; | ||
| 54 | }; | ||
| 55 | ethphy1: ethernet-phy@24 { | ||
| 56 | reg = <24>; | ||
| 57 | }; | ||
| 58 | }; | ||
| 59 | |||
| 60 | ð0 { | ||
| 61 | status = "okay"; | ||
| 62 | ethernet0-port@0 { | ||
| 63 | phy-handle = <ðphy0>; | ||
| 64 | }; | ||
| 65 | }; | ||
| 66 | |||
| 67 | ð1 { | ||
| 68 | status = "okay"; | ||
| 69 | ethernet1-port@0 { | ||
| 70 | phy-handle = <ðphy1>; | ||
| 71 | }; | ||
| 72 | }; | ||
| 73 | |||
diff --git a/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts b/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts new file mode 100644 index 000000000000..9f12f8b53e24 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts | |||
| @@ -0,0 +1,58 @@ | |||
| 1 | /* | ||
| 2 | * Marvell OpenRD Ultimate Board Description | ||
| 3 | * | ||
| 4 | * Andrew Lunn <andrew@lunn.ch> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | * | ||
| 10 | * This file contains the definitions that are specific to OpenRD | ||
| 11 | * ultimate variant of the Marvell Kirkwood Development Board. | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | |||
| 16 | #include "kirkwood-openrd.dtsi" | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "OpenRD Ultimate"; | ||
| 20 | compatible = "marvell,openrd-ultimate", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; | ||
| 21 | |||
| 22 | ocp@f1000000 { | ||
| 23 | i2c@11000 { | ||
| 24 | status = "okay"; | ||
| 25 | clock-frequency = <400000>; | ||
| 26 | |||
| 27 | cs42l51: cs42l51@4a { | ||
| 28 | compatible = "cirrus,cs42l51"; | ||
| 29 | reg = <0x4a>; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | |||
| 35 | &mdio { | ||
| 36 | status = "okay"; | ||
| 37 | |||
| 38 | ethphy0: ethernet-phy@0 { | ||
| 39 | reg = <0>; | ||
| 40 | }; | ||
| 41 | ethphy1: ethernet-phy@1 { | ||
| 42 | reg = <1>; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | |||
| 46 | ð0 { | ||
| 47 | status = "okay"; | ||
| 48 | ethernet0-port@0 { | ||
| 49 | phy-handle = <ðphy0>; | ||
| 50 | }; | ||
| 51 | }; | ||
| 52 | |||
| 53 | ð1 { | ||
| 54 | status = "okay"; | ||
| 55 | ethernet1-port@0 { | ||
| 56 | phy-handle = <ðphy1>; | ||
| 57 | }; | ||
| 58 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-openrd.dtsi b/arch/arm/boot/dts/kirkwood-openrd.dtsi new file mode 100644 index 000000000000..d3330dadf7ed --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-openrd.dtsi | |||
| @@ -0,0 +1,90 @@ | |||
| 1 | /* | ||
| 2 | * Marvell OpenRD (Base|Client|Ultimate) Board Description | ||
| 3 | * | ||
| 4 | * Andrew Lunn <andrew@lunn.ch> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | * | ||
| 10 | * This file contains the definitions that are common between the three | ||
| 11 | * variants of the Marvell Kirkwood Development Board. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include "kirkwood.dtsi" | ||
| 15 | #include "kirkwood-6281.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | memory { | ||
| 19 | device_type = "memory"; | ||
| 20 | reg = <0x00000000 0x20000000>; | ||
| 21 | }; | ||
| 22 | |||
| 23 | chosen { | ||
| 24 | bootargs = "console=ttyS0,115200n8"; | ||
| 25 | stdout-path = &uart0; | ||
| 26 | }; | ||
| 27 | |||
| 28 | mbus { | ||
| 29 | pcie-controller { | ||
| 30 | status = "okay"; | ||
| 31 | |||
| 32 | pcie@1,0 { | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | }; | ||
| 37 | |||
| 38 | ocp@f1000000 { | ||
| 39 | pinctrl: pin-controller@10000 { | ||
| 40 | pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>; | ||
| 41 | pinctrl-names = "default"; | ||
| 42 | |||
| 43 | pmx_select28: pmx-select-uart-sd { | ||
| 44 | marvell,pins = "mpp28"; | ||
| 45 | marvell,function = "gpio"; | ||
| 46 | }; | ||
| 47 | pmx_sdio_cd: pmx-sdio-cd { | ||
| 48 | marvell,pins = "mpp29"; | ||
| 49 | marvell,function = "gpio"; | ||
| 50 | }; | ||
| 51 | pmx_select34: pmx-select-rs232-rs484 { | ||
| 52 | marvell,pins = "mpp34"; | ||
| 53 | marvell,function = "gpio"; | ||
| 54 | }; | ||
| 55 | }; | ||
| 56 | serial@12000 { | ||
| 57 | status = "okay"; | ||
| 58 | |||
| 59 | }; | ||
| 60 | sata@80000 { | ||
| 61 | status = "okay"; | ||
| 62 | nr-ports = <2>; | ||
| 63 | }; | ||
| 64 | mvsdio@90000 { | ||
| 65 | status = "okay"; | ||
| 66 | cd-gpios = <&gpio0 29 9>; | ||
| 67 | }; | ||
| 68 | }; | ||
| 69 | }; | ||
| 70 | |||
| 71 | &nand { | ||
| 72 | status = "okay"; | ||
| 73 | pinctrl-0 = <&pmx_nand>; | ||
| 74 | pinctrl-names = "default"; | ||
| 75 | |||
| 76 | partition@0 { | ||
| 77 | label = "u-boot"; | ||
| 78 | reg = <0x0000000 0x100000>; | ||
| 79 | }; | ||
| 80 | |||
| 81 | partition@100000 { | ||
| 82 | label = "uImage"; | ||
| 83 | reg = <0x0100000 0x400000>; | ||
| 84 | }; | ||
| 85 | |||
| 86 | partition@600000 { | ||
| 87 | label = "root"; | ||
| 88 | reg = <0x0600000 0x1FA00000>; | ||
| 89 | }; | ||
| 90 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/kirkwood-rd88f6192.dts index e9dd85049297..35a29dee8dd8 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6192.dts +++ b/arch/arm/boot/dts/kirkwood-rd88f6192.dts | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | 26 | ||
| 27 | chosen { | 27 | chosen { |
| 28 | bootargs = "console=ttyS0,115200n8"; | 28 | bootargs = "console=ttyS0,115200n8"; |
| 29 | stdout-path = &uart0; | ||
| 29 | }; | 30 | }; |
| 30 | 31 | ||
| 31 | mbus { | 32 | mbus { |
| @@ -39,7 +40,7 @@ | |||
| 39 | }; | 40 | }; |
| 40 | 41 | ||
| 41 | ocp@f1000000 { | 42 | ocp@f1000000 { |
| 42 | pinctrl: pinctrl@10000 { | 43 | pinctrl: pin-controller@10000 { |
| 43 | pinctrl-0 = <&pmx_usb_power>; | 44 | pinctrl-0 = <&pmx_usb_power>; |
| 44 | pinctrl-names = "default"; | 45 | pinctrl-names = "default"; |
| 45 | 46 | ||
| @@ -56,8 +57,6 @@ | |||
| 56 | 57 | ||
| 57 | spi@10600 { | 58 | spi@10600 { |
| 58 | status = "okay"; | 59 | status = "okay"; |
| 59 | pinctrl-0 = <&pmx_spi>; | ||
| 60 | pinctrl-names = "default"; | ||
| 61 | 60 | ||
| 62 | m25p128@0 { | 61 | m25p128@0 { |
| 63 | #address-cells = <1>; | 62 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi index d6368c39102e..26cf0e0ccefd 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | 22 | ||
| 23 | chosen { | 23 | chosen { |
| 24 | bootargs = "console=ttyS0,115200n8"; | 24 | bootargs = "console=ttyS0,115200n8"; |
| 25 | stdout-path = &uart0; | ||
| 25 | }; | 26 | }; |
| 26 | 27 | ||
| 27 | mbus { | 28 | mbus { |
| @@ -35,7 +36,7 @@ | |||
| 35 | }; | 36 | }; |
| 36 | 37 | ||
| 37 | ocp@f1000000 { | 38 | ocp@f1000000 { |
| 38 | pinctrl: pinctrl@10000 { | 39 | pinctrl: pin-controller@10000 { |
| 39 | pinctrl-0 = <&pmx_sdio_cd>; | 40 | pinctrl-0 = <&pmx_sdio_cd>; |
| 40 | pinctrl-names = "default"; | 41 | pinctrl-names = "default"; |
| 41 | 42 | ||
diff --git a/arch/arm/boot/dts/kirkwood-rs212.dts b/arch/arm/boot/dts/kirkwood-rs212.dts index 93ec3d00c6ab..3b19f1fd4cac 100644 --- a/arch/arm/boot/dts/kirkwood-rs212.dts +++ b/arch/arm/boot/dts/kirkwood-rs212.dts | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | 24 | ||
| 25 | chosen { | 25 | chosen { |
| 26 | bootargs = "console=ttyS0,115200n8"; | 26 | bootargs = "console=ttyS0,115200n8"; |
| 27 | stdout-path = &uart0; | ||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | gpio-fan-100-15-35-3 { | 30 | gpio-fan-100-15-35-3 { |
diff --git a/arch/arm/boot/dts/kirkwood-rs409.dts b/arch/arm/boot/dts/kirkwood-rs409.dts index 311df4e5aa28..921ca49e85a4 100644 --- a/arch/arm/boot/dts/kirkwood-rs409.dts +++ b/arch/arm/boot/dts/kirkwood-rs409.dts | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | 24 | ||
| 25 | chosen { | 25 | chosen { |
| 26 | bootargs = "console=ttyS0,115200n8"; | 26 | bootargs = "console=ttyS0,115200n8"; |
| 27 | stdout-path = &uart0; | ||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | gpio-fan-150-15-18 { | 30 | gpio-fan-150-15-18 { |
diff --git a/arch/arm/boot/dts/kirkwood-rs411.dts b/arch/arm/boot/dts/kirkwood-rs411.dts index f90da850bb31..02852b0c809f 100644 --- a/arch/arm/boot/dts/kirkwood-rs411.dts +++ b/arch/arm/boot/dts/kirkwood-rs411.dts | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | 24 | ||
| 25 | chosen { | 25 | chosen { |
| 26 | bootargs = "console=ttyS0,115200n8"; | 26 | bootargs = "console=ttyS0,115200n8"; |
| 27 | stdout-path = &uart0; | ||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | gpio-fan-100-15-35-3 { | 30 | gpio-fan-100-15-35-3 { |
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi index 1ff848d570a9..7196c7f3e109 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi | |||
| @@ -17,10 +17,11 @@ | |||
| 17 | 17 | ||
| 18 | chosen { | 18 | chosen { |
| 19 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 19 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 20 | stdout-path = &uart0; | ||
| 20 | }; | 21 | }; |
| 21 | 22 | ||
| 22 | ocp@f1000000 { | 23 | ocp@f1000000 { |
| 23 | pinctrl: pinctrl@10000 { | 24 | pinctrl: pin-controller@10000 { |
| 24 | 25 | ||
| 25 | pmx_usb_power_enable: pmx-usb-power-enable { | 26 | pmx_usb_power_enable: pmx-usb-power-enable { |
| 26 | marvell,pins = "mpp29"; | 27 | marvell,pins = "mpp29"; |
| @@ -44,8 +45,6 @@ | |||
| 44 | }; | 45 | }; |
| 45 | }; | 46 | }; |
| 46 | serial@12000 { | 47 | serial@12000 { |
| 47 | pinctrl-0 = <&pmx_uart0>; | ||
| 48 | pinctrl-names = "default"; | ||
| 49 | status = "okay"; | 48 | status = "okay"; |
| 50 | }; | 49 | }; |
| 51 | }; | 50 | }; |
| @@ -72,8 +71,6 @@ | |||
| 72 | }; | 71 | }; |
| 73 | 72 | ||
| 74 | &nand { | 73 | &nand { |
| 75 | pinctrl-0 = <&pmx_nand>; | ||
| 76 | pinctrl-names = "default"; | ||
| 77 | status = "okay"; | 74 | status = "okay"; |
| 78 | 75 | ||
| 79 | partition@0 { | 76 | partition@0 { |
diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi index 4227c974729d..811e0971fc58 100644 --- a/arch/arm/boot/dts/kirkwood-synology.dtsi +++ b/arch/arm/boot/dts/kirkwood-synology.dtsi | |||
| @@ -25,7 +25,7 @@ | |||
| 25 | }; | 25 | }; |
| 26 | 26 | ||
| 27 | ocp@f1000000 { | 27 | ocp@f1000000 { |
| 28 | pinctrl: pinctrl@10000 { | 28 | pinctrl: pin-controller@10000 { |
| 29 | pmx_alarmled_12: pmx-alarmled-12 { | 29 | pmx_alarmled_12: pmx-alarmled-12 { |
| 30 | marvell,pins = "mpp12"; | 30 | marvell,pins = "mpp12"; |
| 31 | marvell,function = "gpio"; | 31 | marvell,function = "gpio"; |
| @@ -213,8 +213,6 @@ | |||
| 213 | 213 | ||
| 214 | spi@10600 { | 214 | spi@10600 { |
| 215 | status = "okay"; | 215 | status = "okay"; |
| 216 | pinctrl-0 = <&pmx_spi>; | ||
| 217 | pinctrl-names = "default"; | ||
| 218 | 216 | ||
| 219 | m25p80@0 { | 217 | m25p80@0 { |
| 220 | #address-cells = <1>; | 218 | #address-cells = <1>; |
| @@ -259,8 +257,6 @@ | |||
| 259 | i2c@11000 { | 257 | i2c@11000 { |
| 260 | status = "okay"; | 258 | status = "okay"; |
| 261 | clock-frequency = <400000>; | 259 | clock-frequency = <400000>; |
| 262 | pinctrl-0 = <&pmx_twsi0>; | ||
| 263 | pinctrl-names = "default"; | ||
| 264 | 260 | ||
| 265 | rs5c372: rs5c372@32 { | 261 | rs5c372: rs5c372@32 { |
| 266 | status = "disabled"; | 262 | status = "disabled"; |
| @@ -277,14 +273,10 @@ | |||
| 277 | 273 | ||
| 278 | serial@12000 { | 274 | serial@12000 { |
| 279 | status = "okay"; | 275 | status = "okay"; |
| 280 | pinctrl-0 = <&pmx_uart0>; | ||
| 281 | pinctrl-names = "default"; | ||
| 282 | }; | 276 | }; |
| 283 | 277 | ||
| 284 | serial@12100 { | 278 | serial@12100 { |
| 285 | status = "okay"; | 279 | status = "okay"; |
| 286 | pinctrl-0 = <&pmx_uart1>; | ||
| 287 | pinctrl-names = "default"; | ||
| 288 | }; | 280 | }; |
| 289 | 281 | ||
| 290 | poweroff@12100 { | 282 | poweroff@12100 { |
diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts index 0bd70d928c69..610ec0f95858 100644 --- a/arch/arm/boot/dts/kirkwood-t5325.dts +++ b/arch/arm/boot/dts/kirkwood-t5325.dts | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | 27 | ||
| 28 | chosen { | 28 | chosen { |
| 29 | bootargs = "console=ttyS0,115200n8"; | 29 | bootargs = "console=ttyS0,115200n8"; |
| 30 | stdout-path = &uart0; | ||
| 30 | }; | 31 | }; |
| 31 | 32 | ||
| 32 | mbus { | 33 | mbus { |
| @@ -40,7 +41,7 @@ | |||
| 40 | }; | 41 | }; |
| 41 | 42 | ||
| 42 | ocp@f1000000 { | 43 | ocp@f1000000 { |
| 43 | pinctrl: pinctrl@10000 { | 44 | pinctrl: pin-controller@10000 { |
| 44 | pinctrl-0 = <&pmx_i2s &pmx_sysrst>; | 45 | pinctrl-0 = <&pmx_i2s &pmx_sysrst>; |
| 45 | pinctrl-names = "default"; | 46 | pinctrl-names = "default"; |
| 46 | 47 | ||
| @@ -64,10 +65,6 @@ | |||
| 64 | marvell,function = "gpio"; | 65 | marvell,function = "gpio"; |
| 65 | }; | 66 | }; |
| 66 | 67 | ||
| 67 | /* | ||
| 68 | * Redefined from kirkwood-6281.dtsi, because | ||
| 69 | * we don't use SPI CS on MPP0, but on MPP7. | ||
| 70 | */ | ||
| 71 | pmx_spi: pmx-spi { | 68 | pmx_spi: pmx-spi { |
| 72 | marvell,pins = "mpp1", "mpp2", "mpp3", "mpp7"; | 69 | marvell,pins = "mpp1", "mpp2", "mpp3", "mpp7"; |
| 73 | marvell,function = "spi"; | 70 | marvell,function = "spi"; |
| @@ -86,8 +83,6 @@ | |||
| 86 | }; | 83 | }; |
| 87 | 84 | ||
| 88 | spi@10600 { | 85 | spi@10600 { |
| 89 | pinctrl-0 = <&pmx_spi>; | ||
| 90 | pinctrl-names = "default"; | ||
| 91 | status = "okay"; | 86 | status = "okay"; |
| 92 | 87 | ||
| 93 | flash@0 { | 88 | flash@0 { |
| @@ -127,6 +122,14 @@ | |||
| 127 | 122 | ||
| 128 | i2c@11000 { | 123 | i2c@11000 { |
| 129 | status = "okay"; | 124 | status = "okay"; |
| 125 | |||
| 126 | alc5621: alc5621@1a { | ||
| 127 | compatible = "realtek,alc5621"; | ||
| 128 | reg = <0x1a>; | ||
| 129 | #sound-dai-cells = <0>; | ||
| 130 | add-ctrl = <0x3700>; | ||
| 131 | jack-det-ctrl = <0x4810>; | ||
| 132 | }; | ||
| 130 | }; | 133 | }; |
| 131 | 134 | ||
| 132 | serial@12000 { | 135 | serial@12000 { |
| @@ -184,6 +187,31 @@ | |||
| 184 | gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; | 187 | gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; |
| 185 | }; | 188 | }; |
| 186 | 189 | ||
| 190 | sound { | ||
| 191 | compatible = "simple-audio-card"; | ||
| 192 | simple-audio-card,format = "i2s"; | ||
| 193 | simple-audio-card,routing = | ||
| 194 | "Headphone Jack", "HPL", | ||
| 195 | "Headphone Jack", "HPR", | ||
| 196 | "Speaker", "SPKOUT", | ||
| 197 | "Speaker", "SPKOUTN", | ||
| 198 | "MIC1", "Mic Jack", | ||
| 199 | "MIC2", "Mic Jack"; | ||
| 200 | simple-audio-card,widgets = | ||
| 201 | "Headphone", "Headphone Jack", | ||
| 202 | "Speaker", "Speaker", | ||
| 203 | "Microphone", "Mic Jack"; | ||
| 204 | |||
| 205 | simple-audio-card,mclk-fs = <256>; | ||
| 206 | |||
| 207 | simple-audio-card,cpu { | ||
| 208 | sound-dai = <&audio>; | ||
| 209 | }; | ||
| 210 | |||
| 211 | simple-audio-card,codec { | ||
| 212 | sound-dai = <&alc5621>; | ||
| 213 | }; | ||
| 214 | }; | ||
| 187 | }; | 215 | }; |
| 188 | 216 | ||
| 189 | &mdio { | 217 | &mdio { |
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index 5fc817c2cb87..f5c8c0dd41dc 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts | |||
| @@ -14,10 +14,11 @@ | |||
| 14 | 14 | ||
| 15 | chosen { | 15 | chosen { |
| 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 17 | stdout-path = &uart0; | ||
| 17 | }; | 18 | }; |
| 18 | 19 | ||
| 19 | ocp@f1000000 { | 20 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 21 | pinctrl: pin-controller@10000 { |
| 21 | /* | 22 | /* |
| 22 | * Switch positions | 23 | * Switch positions |
| 23 | * | 24 | * |
| @@ -85,9 +86,7 @@ | |||
| 85 | }; | 86 | }; |
| 86 | 87 | ||
| 87 | serial@12000 { | 88 | serial@12000 { |
| 88 | status = "ok"; | 89 | status = "okay"; |
| 89 | pinctrl-0 = <&pmx_uart0>; | ||
| 90 | pinctrl-names = "default"; | ||
| 91 | }; | 90 | }; |
| 92 | 91 | ||
| 93 | sata@80000 { | 92 | sata@80000 { |
| @@ -96,9 +95,7 @@ | |||
| 96 | }; | 95 | }; |
| 97 | 96 | ||
| 98 | i2c@11000 { | 97 | i2c@11000 { |
| 99 | status = "ok"; | 98 | status = "okay"; |
| 100 | pinctrl-0 = <&pmx_twsi0>; | ||
| 101 | pinctrl-names = "default"; | ||
| 102 | }; | 99 | }; |
| 103 | 100 | ||
| 104 | mvsdio@90000 { | 101 | mvsdio@90000 { |
| @@ -175,8 +172,6 @@ | |||
| 175 | 172 | ||
| 176 | &nand { | 173 | &nand { |
| 177 | status = "okay"; | 174 | status = "okay"; |
| 178 | pinctrl-0 = <&pmx_nand>; | ||
| 179 | pinctrl-names = "default"; | ||
| 180 | 175 | ||
| 181 | partition@0 { | 176 | partition@0 { |
| 182 | label = "u-boot"; | 177 | label = "u-boot"; |
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts index c17ae45e19be..9767d73f3857 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | 6 | ||
| 7 | / { | 7 | / { |
| 8 | ocp@f1000000 { | 8 | ocp@f1000000 { |
| 9 | pinctrl: pinctrl@10000 { | 9 | pinctrl: pin-controller@10000 { |
| 10 | 10 | ||
| 11 | pinctrl-0 = <&pmx_ram_size &pmx_board_id>; | 11 | pinctrl-0 = <&pmx_ram_size &pmx_board_id>; |
| 12 | pinctrl-names = "default"; | 12 | pinctrl-names = "default"; |
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index 0713d072758a..bfc1a32d4e42 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts | |||
| @@ -16,7 +16,7 @@ | |||
| 16 | }; | 16 | }; |
| 17 | 17 | ||
| 18 | ocp@f1000000 { | 18 | ocp@f1000000 { |
| 19 | pinctrl: pinctrl@10000 { | 19 | pinctrl: pin-controller@10000 { |
| 20 | 20 | ||
| 21 | pinctrl-0 = <&pmx_ram_size &pmx_board_id>; | 21 | pinctrl-0 = <&pmx_ram_size &pmx_board_id>; |
| 22 | pinctrl-names = "default"; | 22 | pinctrl-names = "default"; |
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 911f3a8cee23..df7f15276575 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi | |||
| @@ -9,6 +9,7 @@ | |||
| 9 | 9 | ||
| 10 | chosen { | 10 | chosen { |
| 11 | bootargs = "console=ttyS0,115200n8"; | 11 | bootargs = "console=ttyS0,115200n8"; |
| 12 | stdout-path = &uart0; | ||
| 12 | }; | 13 | }; |
| 13 | 14 | ||
| 14 | mbus { | 15 | mbus { |
| @@ -25,8 +26,6 @@ | |||
| 25 | i2c@11000 { | 26 | i2c@11000 { |
| 26 | status = "okay"; | 27 | status = "okay"; |
| 27 | clock-frequency = <400000>; | 28 | clock-frequency = <400000>; |
| 28 | pinctrl-0 = <&pmx_twsi0>; | ||
| 29 | pinctrl-names = "default"; | ||
| 30 | 29 | ||
| 31 | s35390a: s35390a@30 { | 30 | s35390a: s35390a@30 { |
| 32 | compatible = "s35390a"; | 31 | compatible = "s35390a"; |
| @@ -34,16 +33,10 @@ | |||
| 34 | }; | 33 | }; |
| 35 | }; | 34 | }; |
| 36 | serial@12000 { | 35 | serial@12000 { |
| 37 | clock-frequency = <200000000>; | ||
| 38 | status = "okay"; | 36 | status = "okay"; |
| 39 | pinctrl-0 = <&pmx_uart0>; | ||
| 40 | pinctrl-names = "default"; | ||
| 41 | }; | 37 | }; |
| 42 | serial@12100 { | 38 | serial@12100 { |
| 43 | clock-frequency = <200000000>; | ||
| 44 | status = "okay"; | 39 | status = "okay"; |
| 45 | pinctrl-0 = <&pmx_uart1>; | ||
| 46 | pinctrl-names = "default"; | ||
| 47 | }; | 40 | }; |
| 48 | poweroff@12100 { | 41 | poweroff@12100 { |
| 49 | compatible = "qnap,power-off"; | 42 | compatible = "qnap,power-off"; |
| @@ -52,8 +45,6 @@ | |||
| 52 | }; | 45 | }; |
| 53 | spi@10600 { | 46 | spi@10600 { |
| 54 | status = "okay"; | 47 | status = "okay"; |
| 55 | pinctrl-0 = <&pmx_spi>; | ||
| 56 | pinctrl-names = "default"; | ||
| 57 | 48 | ||
| 58 | m25p128@0 { | 49 | m25p128@0 { |
| 59 | #address-cells = <1>; | 50 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/kirkwood-ts419.dtsi b/arch/arm/boot/dts/kirkwood-ts419.dtsi index 1a9c624c7a92..30ab93bfb1e4 100644 --- a/arch/arm/boot/dts/kirkwood-ts419.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts419.dtsi | |||
| @@ -14,7 +14,7 @@ | |||
| 14 | compatible = "qnap,ts419", "marvell,kirkwood"; | 14 | compatible = "qnap,ts419", "marvell,kirkwood"; |
| 15 | 15 | ||
| 16 | ocp@f1000000 { | 16 | ocp@f1000000 { |
| 17 | pinctrl: pinctrl@10000 { | 17 | pinctrl: pin-controller@10000 { |
| 18 | pinctrl-names = "default"; | 18 | pinctrl-names = "default"; |
| 19 | 19 | ||
| 20 | pmx_USB_copy_button: pmx-USB-copy-button { | 20 | pmx_USB_copy_button: pmx-USB-copy-button { |
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 90384587c278..afc640cd80c5 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi | |||
| @@ -40,7 +40,7 @@ | |||
| 40 | pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ | 40 | pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ |
| 41 | pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ | 41 | pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ |
| 42 | 42 | ||
| 43 | crypto@0301 { | 43 | cesa: crypto@0301 { |
| 44 | compatible = "marvell,orion-crypto"; | 44 | compatible = "marvell,orion-crypto"; |
| 45 | reg = <MBUS_ID(0xf0, 0x01) 0x30000 0x10000>, | 45 | reg = <MBUS_ID(0xf0, 0x01) 0x30000 0x10000>, |
| 46 | <MBUS_ID(0x03, 0x01) 0 0x800>; | 46 | <MBUS_ID(0x03, 0x01) 0 0x800>; |
| @@ -61,6 +61,8 @@ | |||
| 61 | chip-delay = <25>; | 61 | chip-delay = <25>; |
| 62 | /* set partition map and/or chip-delay in board dts */ | 62 | /* set partition map and/or chip-delay in board dts */ |
| 63 | clocks = <&gate_clk 7>; | 63 | clocks = <&gate_clk 7>; |
| 64 | pinctrl-0 = <&pmx_nand>; | ||
| 65 | pinctrl-names = "default"; | ||
| 64 | status = "disabled"; | 66 | status = "disabled"; |
| 65 | }; | 67 | }; |
| 66 | }; | 68 | }; |
| @@ -71,13 +73,59 @@ | |||
| 71 | #address-cells = <1>; | 73 | #address-cells = <1>; |
| 72 | #size-cells = <1>; | 74 | #size-cells = <1>; |
| 73 | 75 | ||
| 76 | pinctrl: pin-controller@10000 { | ||
| 77 | /* set compatible property in SoC file */ | ||
| 78 | reg = <0x10000 0x20>; | ||
| 79 | |||
| 80 | pmx_ge1: pmx-ge1 { | ||
| 81 | marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", | ||
| 82 | "mpp24", "mpp25", "mpp26", "mpp27", | ||
| 83 | "mpp30", "mpp31", "mpp32", "mpp33"; | ||
| 84 | marvell,function = "ge1"; | ||
| 85 | }; | ||
| 86 | |||
| 87 | pmx_nand: pmx-nand { | ||
| 88 | marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", | ||
| 89 | "mpp4", "mpp5", "mpp18", "mpp19"; | ||
| 90 | marvell,function = "nand"; | ||
| 91 | }; | ||
| 92 | |||
| 93 | /* | ||
| 94 | * Default SPI0 pinctrl setting with CSn on mpp0, | ||
| 95 | * overwrite marvell,pins on board level if required. | ||
| 96 | */ | ||
| 97 | pmx_spi: pmx-spi { | ||
| 98 | marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; | ||
| 99 | marvell,function = "spi"; | ||
| 100 | }; | ||
| 101 | |||
| 102 | pmx_twsi0: pmx-twsi0 { | ||
| 103 | marvell,pins = "mpp8", "mpp9"; | ||
| 104 | marvell,function = "twsi0"; | ||
| 105 | }; | ||
| 106 | |||
| 107 | /* | ||
| 108 | * Default UART pinctrl setting without RTS/CTS, | ||
| 109 | * overwrite marvell,pins on board level if required. | ||
| 110 | */ | ||
| 111 | pmx_uart0: pmx-uart0 { | ||
| 112 | marvell,pins = "mpp10", "mpp11"; | ||
| 113 | marvell,function = "uart0"; | ||
| 114 | }; | ||
| 115 | |||
| 116 | pmx_uart1: pmx-uart1 { | ||
| 117 | marvell,pins = "mpp13", "mpp14"; | ||
| 118 | marvell,function = "uart1"; | ||
| 119 | }; | ||
| 120 | }; | ||
| 121 | |||
| 74 | core_clk: core-clocks@10030 { | 122 | core_clk: core-clocks@10030 { |
| 75 | compatible = "marvell,kirkwood-core-clock"; | 123 | compatible = "marvell,kirkwood-core-clock"; |
| 76 | reg = <0x10030 0x4>; | 124 | reg = <0x10030 0x4>; |
| 77 | #clock-cells = <1>; | 125 | #clock-cells = <1>; |
| 78 | }; | 126 | }; |
| 79 | 127 | ||
| 80 | spi@10600 { | 128 | spi0: spi@10600 { |
| 81 | compatible = "marvell,orion-spi"; | 129 | compatible = "marvell,orion-spi"; |
| 82 | #address-cells = <1>; | 130 | #address-cells = <1>; |
| 83 | #size-cells = <0>; | 131 | #size-cells = <0>; |
| @@ -85,6 +133,8 @@ | |||
| 85 | interrupts = <23>; | 133 | interrupts = <23>; |
| 86 | reg = <0x10600 0x28>; | 134 | reg = <0x10600 0x28>; |
| 87 | clocks = <&gate_clk 7>; | 135 | clocks = <&gate_clk 7>; |
| 136 | pinctrl-0 = <&pmx_spi>; | ||
| 137 | pinctrl-names = "default"; | ||
| 88 | status = "disabled"; | 138 | status = "disabled"; |
| 89 | }; | 139 | }; |
| 90 | 140 | ||
| @@ -120,24 +170,30 @@ | |||
| 120 | interrupts = <29>; | 170 | interrupts = <29>; |
| 121 | clock-frequency = <100000>; | 171 | clock-frequency = <100000>; |
| 122 | clocks = <&gate_clk 7>; | 172 | clocks = <&gate_clk 7>; |
| 173 | pinctrl-0 = <&pmx_twsi0>; | ||
| 174 | pinctrl-names = "default"; | ||
| 123 | status = "disabled"; | 175 | status = "disabled"; |
| 124 | }; | 176 | }; |
| 125 | 177 | ||
| 126 | serial@12000 { | 178 | uart0: serial@12000 { |
| 127 | compatible = "ns16550a"; | 179 | compatible = "ns16550a"; |
| 128 | reg = <0x12000 0x100>; | 180 | reg = <0x12000 0x100>; |
| 129 | reg-shift = <2>; | 181 | reg-shift = <2>; |
| 130 | interrupts = <33>; | 182 | interrupts = <33>; |
| 131 | clocks = <&gate_clk 7>; | 183 | clocks = <&gate_clk 7>; |
| 184 | pinctrl-0 = <&pmx_uart0>; | ||
| 185 | pinctrl-names = "default"; | ||
| 132 | status = "disabled"; | 186 | status = "disabled"; |
| 133 | }; | 187 | }; |
| 134 | 188 | ||
| 135 | serial@12100 { | 189 | uart1: serial@12100 { |
| 136 | compatible = "ns16550a"; | 190 | compatible = "ns16550a"; |
| 137 | reg = <0x12100 0x100>; | 191 | reg = <0x12100 0x100>; |
| 138 | reg-shift = <2>; | 192 | reg-shift = <2>; |
| 139 | interrupts = <34>; | 193 | interrupts = <34>; |
| 140 | clocks = <&gate_clk 7>; | 194 | clocks = <&gate_clk 7>; |
| 195 | pinctrl-0 = <&pmx_uart1>; | ||
| 196 | pinctrl-names = "default"; | ||
| 141 | status = "disabled"; | 197 | status = "disabled"; |
| 142 | }; | 198 | }; |
| 143 | 199 | ||
| @@ -146,7 +202,7 @@ | |||
| 146 | reg = <0x20000 0x80>, <0x1500 0x20>; | 202 | reg = <0x20000 0x80>, <0x1500 0x20>; |
| 147 | }; | 203 | }; |
| 148 | 204 | ||
| 149 | system-controller@20000 { | 205 | sysc: system-controller@20000 { |
| 150 | compatible = "marvell,orion-system-controller"; | 206 | compatible = "marvell,orion-system-controller"; |
| 151 | reg = <0x20000 0x120>; | 207 | reg = <0x20000 0x120>; |
| 152 | }; | 208 | }; |
| @@ -196,7 +252,7 @@ | |||
| 196 | status = "okay"; | 252 | status = "okay"; |
| 197 | }; | 253 | }; |
| 198 | 254 | ||
| 199 | ehci@50000 { | 255 | usb0: ehci@50000 { |
| 200 | compatible = "marvell,orion-ehci"; | 256 | compatible = "marvell,orion-ehci"; |
| 201 | reg = <0x50000 0x1000>; | 257 | reg = <0x50000 0x1000>; |
| 202 | interrupts = <19>; | 258 | interrupts = <19>; |
| @@ -204,7 +260,7 @@ | |||
| 204 | status = "okay"; | 260 | status = "okay"; |
| 205 | }; | 261 | }; |
| 206 | 262 | ||
| 207 | xor@60800 { | 263 | dma0: xor@60800 { |
| 208 | compatible = "marvell,orion-xor"; | 264 | compatible = "marvell,orion-xor"; |
| 209 | reg = <0x60800 0x100 | 265 | reg = <0x60800 0x100 |
| 210 | 0x60A00 0x100>; | 266 | 0x60A00 0x100>; |
| @@ -224,7 +280,7 @@ | |||
| 224 | }; | 280 | }; |
| 225 | }; | 281 | }; |
| 226 | 282 | ||
| 227 | xor@60900 { | 283 | dma1: xor@60900 { |
| 228 | compatible = "marvell,orion-xor"; | 284 | compatible = "marvell,orion-xor"; |
| 229 | reg = <0x60900 0x100 | 285 | reg = <0x60900 0x100 |
| 230 | 0x60B00 0x100>; | 286 | 0x60B00 0x100>; |
| @@ -282,6 +338,8 @@ | |||
| 282 | reg = <0x76000 0x4000>; | 338 | reg = <0x76000 0x4000>; |
| 283 | clocks = <&gate_clk 19>; | 339 | clocks = <&gate_clk 19>; |
| 284 | marvell,tx-checksum-limit = <1600>; | 340 | marvell,tx-checksum-limit = <1600>; |
| 341 | pinctrl-0 = <&pmx_ge1>; | ||
| 342 | pinctrl-names = "default"; | ||
| 285 | status = "disabled"; | 343 | status = "disabled"; |
| 286 | 344 | ||
| 287 | ethernet1-port@0 { | 345 | ethernet1-port@0 { |
| @@ -314,6 +372,7 @@ | |||
| 314 | 372 | ||
| 315 | audio0: audio-controller@a0000 { | 373 | audio0: audio-controller@a0000 { |
| 316 | compatible = "marvell,kirkwood-audio"; | 374 | compatible = "marvell,kirkwood-audio"; |
| 375 | #sound-dai-cells = <0>; | ||
| 317 | reg = <0xa0000 0x2210>; | 376 | reg = <0xa0000 0x2210>; |
| 318 | interrupts = <24>; | 377 | interrupts = <24>; |
| 319 | clocks = <&gate_clk 9>; | 378 | clocks = <&gate_clk 9>; |
diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi index 0c9647d28765..fb354225740a 100644 --- a/arch/arm/boot/dts/marco.dtsi +++ b/arch/arm/boot/dts/marco.dtsi | |||
| @@ -36,7 +36,7 @@ | |||
| 36 | ranges = <0x40000000 0x40000000 0xa0000000>; | 36 | ranges = <0x40000000 0x40000000 0xa0000000>; |
| 37 | 37 | ||
| 38 | l2-cache-controller@c0030000 { | 38 | l2-cache-controller@c0030000 { |
| 39 | compatible = "sirf,marco-pl310-cache", "arm,pl310-cache"; | 39 | compatible = "arm,pl310-cache"; |
| 40 | reg = <0xc0030000 0x1000>; | 40 | reg = <0xc0030000 0x1000>; |
| 41 | interrupts = <0 59 0>; | 41 | interrupts = <0 59 0>; |
| 42 | arm,tag-latency = <1 1 1>; | 42 | arm,tag-latency = <1 1 1>; |
diff --git a/arch/arm/boot/dts/omap2420-clocks.dtsi b/arch/arm/boot/dts/omap2420-clocks.dtsi new file mode 100644 index 000000000000..ce8c742d7e92 --- /dev/null +++ b/arch/arm/boot/dts/omap2420-clocks.dtsi | |||
| @@ -0,0 +1,270 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree Source for OMAP2420 clock data | ||
| 3 | * | ||
| 4 | * Copyright (C) 2014 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | &prcm_clocks { | ||
| 12 | sys_clkout2_src_gate: sys_clkout2_src_gate { | ||
| 13 | #clock-cells = <0>; | ||
| 14 | compatible = "ti,composite-no-wait-gate-clock"; | ||
| 15 | clocks = <&core_ck>; | ||
| 16 | ti,bit-shift = <15>; | ||
| 17 | reg = <0x0070>; | ||
| 18 | }; | ||
| 19 | |||
| 20 | sys_clkout2_src_mux: sys_clkout2_src_mux { | ||
| 21 | #clock-cells = <0>; | ||
| 22 | compatible = "ti,composite-mux-clock"; | ||
| 23 | clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; | ||
| 24 | ti,bit-shift = <8>; | ||
| 25 | reg = <0x0070>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | sys_clkout2_src: sys_clkout2_src { | ||
| 29 | #clock-cells = <0>; | ||
| 30 | compatible = "ti,composite-clock"; | ||
| 31 | clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>; | ||
| 32 | }; | ||
| 33 | |||
| 34 | sys_clkout2: sys_clkout2 { | ||
| 35 | #clock-cells = <0>; | ||
| 36 | compatible = "ti,divider-clock"; | ||
| 37 | clocks = <&sys_clkout2_src>; | ||
| 38 | ti,bit-shift = <11>; | ||
| 39 | ti,max-div = <64>; | ||
| 40 | reg = <0x0070>; | ||
| 41 | ti,index-power-of-two; | ||
| 42 | }; | ||
| 43 | |||
| 44 | dsp_gate_ick: dsp_gate_ick { | ||
| 45 | #clock-cells = <0>; | ||
| 46 | compatible = "ti,composite-interface-clock"; | ||
| 47 | clocks = <&dsp_fck>; | ||
| 48 | ti,bit-shift = <1>; | ||
| 49 | reg = <0x0810>; | ||
| 50 | }; | ||
| 51 | |||
| 52 | dsp_div_ick: dsp_div_ick { | ||
| 53 | #clock-cells = <0>; | ||
| 54 | compatible = "ti,composite-divider-clock"; | ||
| 55 | clocks = <&dsp_fck>; | ||
| 56 | ti,bit-shift = <5>; | ||
| 57 | ti,max-div = <3>; | ||
| 58 | reg = <0x0840>; | ||
| 59 | ti,index-starts-at-one; | ||
| 60 | }; | ||
| 61 | |||
| 62 | dsp_ick: dsp_ick { | ||
| 63 | #clock-cells = <0>; | ||
| 64 | compatible = "ti,composite-clock"; | ||
| 65 | clocks = <&dsp_gate_ick>, <&dsp_div_ick>; | ||
| 66 | }; | ||
| 67 | |||
| 68 | iva1_gate_ifck: iva1_gate_ifck { | ||
| 69 | #clock-cells = <0>; | ||
| 70 | compatible = "ti,composite-gate-clock"; | ||
| 71 | clocks = <&core_ck>; | ||
| 72 | ti,bit-shift = <10>; | ||
| 73 | reg = <0x0800>; | ||
| 74 | }; | ||
| 75 | |||
| 76 | iva1_div_ifck: iva1_div_ifck { | ||
| 77 | #clock-cells = <0>; | ||
| 78 | compatible = "ti,composite-divider-clock"; | ||
| 79 | clocks = <&core_ck>; | ||
| 80 | ti,bit-shift = <8>; | ||
| 81 | reg = <0x0840>; | ||
| 82 | ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>; | ||
| 83 | }; | ||
| 84 | |||
| 85 | iva1_ifck: iva1_ifck { | ||
| 86 | #clock-cells = <0>; | ||
| 87 | compatible = "ti,composite-clock"; | ||
| 88 | clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>; | ||
| 89 | }; | ||
| 90 | |||
| 91 | iva1_ifck_div: iva1_ifck_div { | ||
| 92 | #clock-cells = <0>; | ||
| 93 | compatible = "fixed-factor-clock"; | ||
| 94 | clocks = <&iva1_ifck>; | ||
| 95 | clock-mult = <1>; | ||
| 96 | clock-div = <2>; | ||
| 97 | }; | ||
| 98 | |||
| 99 | iva1_mpu_int_ifck: iva1_mpu_int_ifck { | ||
| 100 | #clock-cells = <0>; | ||
| 101 | compatible = "ti,wait-gate-clock"; | ||
| 102 | clocks = <&iva1_ifck_div>; | ||
| 103 | ti,bit-shift = <8>; | ||
| 104 | reg = <0x0800>; | ||
| 105 | }; | ||
| 106 | |||
| 107 | wdt3_ick: wdt3_ick { | ||
| 108 | #clock-cells = <0>; | ||
| 109 | compatible = "ti,omap3-interface-clock"; | ||
| 110 | clocks = <&l4_ck>; | ||
| 111 | ti,bit-shift = <28>; | ||
| 112 | reg = <0x0210>; | ||
| 113 | }; | ||
| 114 | |||
| 115 | wdt3_fck: wdt3_fck { | ||
| 116 | #clock-cells = <0>; | ||
| 117 | compatible = "ti,wait-gate-clock"; | ||
| 118 | clocks = <&func_32k_ck>; | ||
| 119 | ti,bit-shift = <28>; | ||
| 120 | reg = <0x0200>; | ||
| 121 | }; | ||
| 122 | |||
| 123 | mmc_ick: mmc_ick { | ||
| 124 | #clock-cells = <0>; | ||
| 125 | compatible = "ti,omap3-interface-clock"; | ||
| 126 | clocks = <&l4_ck>; | ||
| 127 | ti,bit-shift = <26>; | ||
| 128 | reg = <0x0210>; | ||
| 129 | }; | ||
| 130 | |||
| 131 | mmc_fck: mmc_fck { | ||
| 132 | #clock-cells = <0>; | ||
| 133 | compatible = "ti,wait-gate-clock"; | ||
| 134 | clocks = <&func_96m_ck>; | ||
| 135 | ti,bit-shift = <26>; | ||
| 136 | reg = <0x0200>; | ||
| 137 | }; | ||
| 138 | |||
| 139 | eac_ick: eac_ick { | ||
| 140 | #clock-cells = <0>; | ||
| 141 | compatible = "ti,omap3-interface-clock"; | ||
| 142 | clocks = <&l4_ck>; | ||
| 143 | ti,bit-shift = <24>; | ||
| 144 | reg = <0x0210>; | ||
| 145 | }; | ||
| 146 | |||
| 147 | eac_fck: eac_fck { | ||
| 148 | #clock-cells = <0>; | ||
| 149 | compatible = "ti,wait-gate-clock"; | ||
| 150 | clocks = <&func_96m_ck>; | ||
| 151 | ti,bit-shift = <24>; | ||
| 152 | reg = <0x0200>; | ||
| 153 | }; | ||
| 154 | |||
| 155 | i2c1_fck: i2c1_fck { | ||
| 156 | #clock-cells = <0>; | ||
| 157 | compatible = "ti,wait-gate-clock"; | ||
| 158 | clocks = <&func_12m_ck>; | ||
| 159 | ti,bit-shift = <19>; | ||
| 160 | reg = <0x0200>; | ||
| 161 | }; | ||
| 162 | |||
| 163 | i2c2_fck: i2c2_fck { | ||
| 164 | #clock-cells = <0>; | ||
| 165 | compatible = "ti,wait-gate-clock"; | ||
| 166 | clocks = <&func_12m_ck>; | ||
| 167 | ti,bit-shift = <20>; | ||
| 168 | reg = <0x0200>; | ||
| 169 | }; | ||
| 170 | |||
| 171 | vlynq_ick: vlynq_ick { | ||
| 172 | #clock-cells = <0>; | ||
| 173 | compatible = "ti,omap3-interface-clock"; | ||
| 174 | clocks = <&core_l3_ck>; | ||
| 175 | ti,bit-shift = <3>; | ||
| 176 | reg = <0x0210>; | ||
| 177 | }; | ||
| 178 | |||
| 179 | vlynq_gate_fck: vlynq_gate_fck { | ||
| 180 | #clock-cells = <0>; | ||
| 181 | compatible = "ti,composite-gate-clock"; | ||
| 182 | clocks = <&core_ck>; | ||
| 183 | ti,bit-shift = <3>; | ||
| 184 | reg = <0x0200>; | ||
| 185 | }; | ||
| 186 | |||
| 187 | core_d18_ck: core_d18_ck { | ||
| 188 | #clock-cells = <0>; | ||
| 189 | compatible = "fixed-factor-clock"; | ||
| 190 | clocks = <&core_ck>; | ||
| 191 | clock-mult = <1>; | ||
| 192 | clock-div = <18>; | ||
| 193 | }; | ||
| 194 | |||
| 195 | vlynq_mux_fck: vlynq_mux_fck { | ||
| 196 | #clock-cells = <0>; | ||
| 197 | compatible = "ti,composite-mux-clock"; | ||
| 198 | clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>; | ||
| 199 | ti,bit-shift = <15>; | ||
| 200 | reg = <0x0240>; | ||
| 201 | }; | ||
| 202 | |||
| 203 | vlynq_fck: vlynq_fck { | ||
| 204 | #clock-cells = <0>; | ||
| 205 | compatible = "ti,composite-clock"; | ||
| 206 | clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>; | ||
| 207 | }; | ||
| 208 | }; | ||
| 209 | |||
| 210 | &prcm_clockdomains { | ||
| 211 | gfx_clkdm: gfx_clkdm { | ||
| 212 | compatible = "ti,clockdomain"; | ||
| 213 | clocks = <&gfx_ick>; | ||
| 214 | }; | ||
| 215 | |||
| 216 | core_l3_clkdm: core_l3_clkdm { | ||
| 217 | compatible = "ti,clockdomain"; | ||
| 218 | clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>; | ||
| 219 | }; | ||
| 220 | |||
| 221 | wkup_clkdm: wkup_clkdm { | ||
| 222 | compatible = "ti,clockdomain"; | ||
| 223 | clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>, | ||
| 224 | <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>, | ||
| 225 | <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>; | ||
| 226 | }; | ||
| 227 | |||
| 228 | iva1_clkdm: iva1_clkdm { | ||
| 229 | compatible = "ti,clockdomain"; | ||
| 230 | clocks = <&iva1_mpu_int_ifck>; | ||
| 231 | }; | ||
| 232 | |||
| 233 | dss_clkdm: dss_clkdm { | ||
| 234 | compatible = "ti,clockdomain"; | ||
| 235 | clocks = <&dss_ick>, <&dss_54m_fck>; | ||
| 236 | }; | ||
| 237 | |||
| 238 | core_l4_clkdm: core_l4_clkdm { | ||
| 239 | compatible = "ti,clockdomain"; | ||
| 240 | clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>, | ||
| 241 | <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>, | ||
| 242 | <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>, | ||
| 243 | <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>, | ||
| 244 | <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>, | ||
| 245 | <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, | ||
| 246 | <&uart3_ick>, <&uart3_fck>, <&cam_ick>, | ||
| 247 | <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>, | ||
| 248 | <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>, | ||
| 249 | <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>, | ||
| 250 | <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>, | ||
| 251 | <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>, | ||
| 252 | <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>, | ||
| 253 | <&pka_ick>; | ||
| 254 | }; | ||
| 255 | }; | ||
| 256 | |||
| 257 | &func_96m_ck { | ||
| 258 | compatible = "fixed-factor-clock"; | ||
| 259 | clocks = <&apll96_ck>; | ||
| 260 | clock-mult = <1>; | ||
| 261 | clock-div = <1>; | ||
| 262 | }; | ||
| 263 | |||
| 264 | &dsp_div_fck { | ||
| 265 | ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>; | ||
| 266 | }; | ||
| 267 | |||
| 268 | &ssi_ssr_sst_div_fck { | ||
| 269 | ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; | ||
| 270 | }; | ||
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index 2d9979835f24..e83b0468080c 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi | |||
| @@ -14,6 +14,32 @@ | |||
| 14 | compatible = "ti,omap2420", "ti,omap2"; | 14 | compatible = "ti,omap2420", "ti,omap2"; |
| 15 | 15 | ||
| 16 | ocp { | 16 | ocp { |
| 17 | prcm: prcm@48008000 { | ||
| 18 | compatible = "ti,omap2-prcm"; | ||
| 19 | reg = <0x48008000 0x1000>; | ||
| 20 | |||
| 21 | prcm_clocks: clocks { | ||
| 22 | #address-cells = <1>; | ||
| 23 | #size-cells = <0>; | ||
| 24 | }; | ||
| 25 | |||
| 26 | prcm_clockdomains: clockdomains { | ||
| 27 | }; | ||
| 28 | }; | ||
| 29 | |||
| 30 | scrm: scrm@48000000 { | ||
| 31 | compatible = "ti,omap2-scrm"; | ||
| 32 | reg = <0x48000000 0x1000>; | ||
| 33 | |||
| 34 | scrm_clocks: clocks { | ||
| 35 | #address-cells = <1>; | ||
| 36 | #size-cells = <0>; | ||
| 37 | }; | ||
| 38 | |||
| 39 | scrm_clockdomains: clockdomains { | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | |||
| 17 | counter32k: counter@48004000 { | 43 | counter32k: counter@48004000 { |
| 18 | compatible = "ti,omap-counter32k"; | 44 | compatible = "ti,omap-counter32k"; |
| 19 | reg = <0x48004000 0x20>; | 45 | reg = <0x48004000 0x20>; |
diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/omap2430-clocks.dtsi new file mode 100644 index 000000000000..805f75df1cf2 --- /dev/null +++ b/arch/arm/boot/dts/omap2430-clocks.dtsi | |||
| @@ -0,0 +1,344 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree Source for OMAP2430 clock data | ||
| 3 | * | ||
| 4 | * Copyright (C) 2014 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | &scrm_clocks { | ||
| 12 | mcbsp3_mux_fck: mcbsp3_mux_fck { | ||
| 13 | #clock-cells = <0>; | ||
| 14 | compatible = "ti,composite-mux-clock"; | ||
| 15 | clocks = <&func_96m_ck>, <&mcbsp_clks>; | ||
| 16 | reg = <0x02e8>; | ||
| 17 | }; | ||
| 18 | |||
| 19 | mcbsp3_fck: mcbsp3_fck { | ||
| 20 | #clock-cells = <0>; | ||
| 21 | compatible = "ti,composite-clock"; | ||
| 22 | clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | mcbsp4_mux_fck: mcbsp4_mux_fck { | ||
| 26 | #clock-cells = <0>; | ||
| 27 | compatible = "ti,composite-mux-clock"; | ||
| 28 | clocks = <&func_96m_ck>, <&mcbsp_clks>; | ||
| 29 | ti,bit-shift = <2>; | ||
| 30 | reg = <0x02e8>; | ||
| 31 | }; | ||
| 32 | |||
| 33 | mcbsp4_fck: mcbsp4_fck { | ||
| 34 | #clock-cells = <0>; | ||
| 35 | compatible = "ti,composite-clock"; | ||
| 36 | clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; | ||
| 37 | }; | ||
| 38 | |||
| 39 | mcbsp5_mux_fck: mcbsp5_mux_fck { | ||
| 40 | #clock-cells = <0>; | ||
| 41 | compatible = "ti,composite-mux-clock"; | ||
| 42 | clocks = <&func_96m_ck>, <&mcbsp_clks>; | ||
| 43 | ti,bit-shift = <4>; | ||
| 44 | reg = <0x02e8>; | ||
| 45 | }; | ||
| 46 | |||
| 47 | mcbsp5_fck: mcbsp5_fck { | ||
| 48 | #clock-cells = <0>; | ||
| 49 | compatible = "ti,composite-clock"; | ||
| 50 | clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; | ||
| 51 | }; | ||
| 52 | }; | ||
| 53 | |||
| 54 | &prcm_clocks { | ||
| 55 | iva2_1_gate_ick: iva2_1_gate_ick { | ||
| 56 | #clock-cells = <0>; | ||
| 57 | compatible = "ti,composite-gate-clock"; | ||
| 58 | clocks = <&dsp_fck>; | ||
| 59 | ti,bit-shift = <0>; | ||
| 60 | reg = <0x0800>; | ||
| 61 | }; | ||
| 62 | |||
| 63 | iva2_1_div_ick: iva2_1_div_ick { | ||
| 64 | #clock-cells = <0>; | ||
| 65 | compatible = "ti,composite-divider-clock"; | ||
| 66 | clocks = <&dsp_fck>; | ||
| 67 | ti,bit-shift = <5>; | ||
| 68 | ti,max-div = <3>; | ||
| 69 | reg = <0x0840>; | ||
| 70 | ti,index-starts-at-one; | ||
| 71 | }; | ||
| 72 | |||
| 73 | iva2_1_ick: iva2_1_ick { | ||
| 74 | #clock-cells = <0>; | ||
| 75 | compatible = "ti,composite-clock"; | ||
| 76 | clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>; | ||
| 77 | }; | ||
| 78 | |||
| 79 | mdm_gate_ick: mdm_gate_ick { | ||
| 80 | #clock-cells = <0>; | ||
| 81 | compatible = "ti,composite-interface-clock"; | ||
| 82 | clocks = <&core_ck>; | ||
| 83 | ti,bit-shift = <0>; | ||
| 84 | reg = <0x0c10>; | ||
| 85 | }; | ||
| 86 | |||
| 87 | mdm_div_ick: mdm_div_ick { | ||
| 88 | #clock-cells = <0>; | ||
| 89 | compatible = "ti,composite-divider-clock"; | ||
| 90 | clocks = <&core_ck>; | ||
| 91 | reg = <0x0c40>; | ||
| 92 | ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>; | ||
| 93 | }; | ||
| 94 | |||
| 95 | mdm_ick: mdm_ick { | ||
| 96 | #clock-cells = <0>; | ||
| 97 | compatible = "ti,composite-clock"; | ||
| 98 | clocks = <&mdm_gate_ick>, <&mdm_div_ick>; | ||
| 99 | }; | ||
| 100 | |||
| 101 | mdm_osc_ck: mdm_osc_ck { | ||
| 102 | #clock-cells = <0>; | ||
| 103 | compatible = "ti,omap3-interface-clock"; | ||
| 104 | clocks = <&osc_ck>; | ||
| 105 | ti,bit-shift = <1>; | ||
| 106 | reg = <0x0c00>; | ||
| 107 | }; | ||
| 108 | |||
| 109 | mcbsp3_ick: mcbsp3_ick { | ||
| 110 | #clock-cells = <0>; | ||
| 111 | compatible = "ti,omap3-interface-clock"; | ||
| 112 | clocks = <&l4_ck>; | ||
| 113 | ti,bit-shift = <3>; | ||
| 114 | reg = <0x0214>; | ||
| 115 | }; | ||
| 116 | |||
| 117 | mcbsp3_gate_fck: mcbsp3_gate_fck { | ||
| 118 | #clock-cells = <0>; | ||
| 119 | compatible = "ti,composite-gate-clock"; | ||
| 120 | clocks = <&mcbsp_clks>; | ||
| 121 | ti,bit-shift = <3>; | ||
| 122 | reg = <0x0204>; | ||
| 123 | }; | ||
| 124 | |||
| 125 | mcbsp4_ick: mcbsp4_ick { | ||
| 126 | #clock-cells = <0>; | ||
| 127 | compatible = "ti,omap3-interface-clock"; | ||
| 128 | clocks = <&l4_ck>; | ||
| 129 | ti,bit-shift = <4>; | ||
| 130 | reg = <0x0214>; | ||
| 131 | }; | ||
| 132 | |||
| 133 | mcbsp4_gate_fck: mcbsp4_gate_fck { | ||
| 134 | #clock-cells = <0>; | ||
| 135 | compatible = "ti,composite-gate-clock"; | ||
| 136 | clocks = <&mcbsp_clks>; | ||
| 137 | ti,bit-shift = <4>; | ||
| 138 | reg = <0x0204>; | ||
| 139 | }; | ||
| 140 | |||
| 141 | mcbsp5_ick: mcbsp5_ick { | ||
| 142 | #clock-cells = <0>; | ||
| 143 | compatible = "ti,omap3-interface-clock"; | ||
| 144 | clocks = <&l4_ck>; | ||
| 145 | ti,bit-shift = <5>; | ||
| 146 | reg = <0x0214>; | ||
| 147 | }; | ||
| 148 | |||
| 149 | mcbsp5_gate_fck: mcbsp5_gate_fck { | ||
| 150 | #clock-cells = <0>; | ||
| 151 | compatible = "ti,composite-gate-clock"; | ||
| 152 | clocks = <&mcbsp_clks>; | ||
| 153 | ti,bit-shift = <5>; | ||
| 154 | reg = <0x0204>; | ||
| 155 | }; | ||
| 156 | |||
| 157 | mcspi3_ick: mcspi3_ick { | ||
| 158 | #clock-cells = <0>; | ||
| 159 | compatible = "ti,omap3-interface-clock"; | ||
| 160 | clocks = <&l4_ck>; | ||
| 161 | ti,bit-shift = <9>; | ||
| 162 | reg = <0x0214>; | ||
| 163 | }; | ||
| 164 | |||
| 165 | mcspi3_fck: mcspi3_fck { | ||
| 166 | #clock-cells = <0>; | ||
| 167 | compatible = "ti,wait-gate-clock"; | ||
| 168 | clocks = <&func_48m_ck>; | ||
| 169 | ti,bit-shift = <9>; | ||
| 170 | reg = <0x0204>; | ||
| 171 | }; | ||
| 172 | |||
| 173 | icr_ick: icr_ick { | ||
| 174 | #clock-cells = <0>; | ||
| 175 | compatible = "ti,omap3-interface-clock"; | ||
| 176 | clocks = <&sys_ck>; | ||
| 177 | ti,bit-shift = <6>; | ||
| 178 | reg = <0x0410>; | ||
| 179 | }; | ||
| 180 | |||
| 181 | i2chs1_fck: i2chs1_fck { | ||
| 182 | #clock-cells = <0>; | ||
| 183 | compatible = "ti,omap2430-interface-clock"; | ||
| 184 | clocks = <&func_96m_ck>; | ||
| 185 | ti,bit-shift = <19>; | ||
| 186 | reg = <0x0204>; | ||
| 187 | }; | ||
| 188 | |||
| 189 | i2chs2_fck: i2chs2_fck { | ||
| 190 | #clock-cells = <0>; | ||
| 191 | compatible = "ti,omap2430-interface-clock"; | ||
| 192 | clocks = <&func_96m_ck>; | ||
| 193 | ti,bit-shift = <20>; | ||
| 194 | reg = <0x0204>; | ||
| 195 | }; | ||
| 196 | |||
| 197 | usbhs_ick: usbhs_ick { | ||
| 198 | #clock-cells = <0>; | ||
| 199 | compatible = "ti,omap3-interface-clock"; | ||
| 200 | clocks = <&core_l3_ck>; | ||
| 201 | ti,bit-shift = <6>; | ||
| 202 | reg = <0x0214>; | ||
| 203 | }; | ||
| 204 | |||
| 205 | mmchs1_ick: mmchs1_ick { | ||
| 206 | #clock-cells = <0>; | ||
| 207 | compatible = "ti,omap3-interface-clock"; | ||
| 208 | clocks = <&l4_ck>; | ||
| 209 | ti,bit-shift = <7>; | ||
| 210 | reg = <0x0214>; | ||
| 211 | }; | ||
| 212 | |||
| 213 | mmchs1_fck: mmchs1_fck { | ||
| 214 | #clock-cells = <0>; | ||
| 215 | compatible = "ti,wait-gate-clock"; | ||
| 216 | clocks = <&func_96m_ck>; | ||
| 217 | ti,bit-shift = <7>; | ||
| 218 | reg = <0x0204>; | ||
| 219 | }; | ||
| 220 | |||
| 221 | mmchs2_ick: mmchs2_ick { | ||
| 222 | #clock-cells = <0>; | ||
| 223 | compatible = "ti,omap3-interface-clock"; | ||
| 224 | clocks = <&l4_ck>; | ||
| 225 | ti,bit-shift = <8>; | ||
| 226 | reg = <0x0214>; | ||
| 227 | }; | ||
| 228 | |||
| 229 | mmchs2_fck: mmchs2_fck { | ||
| 230 | #clock-cells = <0>; | ||
| 231 | compatible = "ti,wait-gate-clock"; | ||
| 232 | clocks = <&func_96m_ck>; | ||
| 233 | ti,bit-shift = <8>; | ||
| 234 | reg = <0x0204>; | ||
| 235 | }; | ||
| 236 | |||
| 237 | gpio5_ick: gpio5_ick { | ||
| 238 | #clock-cells = <0>; | ||
| 239 | compatible = "ti,omap3-interface-clock"; | ||
| 240 | clocks = <&l4_ck>; | ||
| 241 | ti,bit-shift = <10>; | ||
| 242 | reg = <0x0214>; | ||
| 243 | }; | ||
| 244 | |||
| 245 | gpio5_fck: gpio5_fck { | ||
| 246 | #clock-cells = <0>; | ||
| 247 | compatible = "ti,wait-gate-clock"; | ||
| 248 | clocks = <&func_32k_ck>; | ||
| 249 | ti,bit-shift = <10>; | ||
| 250 | reg = <0x0204>; | ||
| 251 | }; | ||
| 252 | |||
| 253 | mdm_intc_ick: mdm_intc_ick { | ||
| 254 | #clock-cells = <0>; | ||
| 255 | compatible = "ti,omap3-interface-clock"; | ||
| 256 | clocks = <&l4_ck>; | ||
| 257 | ti,bit-shift = <11>; | ||
| 258 | reg = <0x0214>; | ||
| 259 | }; | ||
| 260 | |||
| 261 | mmchsdb1_fck: mmchsdb1_fck { | ||
| 262 | #clock-cells = <0>; | ||
| 263 | compatible = "ti,wait-gate-clock"; | ||
| 264 | clocks = <&func_32k_ck>; | ||
| 265 | ti,bit-shift = <16>; | ||
| 266 | reg = <0x0204>; | ||
| 267 | }; | ||
| 268 | |||
| 269 | mmchsdb2_fck: mmchsdb2_fck { | ||
| 270 | #clock-cells = <0>; | ||
| 271 | compatible = "ti,wait-gate-clock"; | ||
| 272 | clocks = <&func_32k_ck>; | ||
| 273 | ti,bit-shift = <17>; | ||
| 274 | reg = <0x0204>; | ||
| 275 | }; | ||
| 276 | }; | ||
| 277 | |||
| 278 | &prcm_clockdomains { | ||
| 279 | gfx_clkdm: gfx_clkdm { | ||
| 280 | compatible = "ti,clockdomain"; | ||
| 281 | clocks = <&gfx_ick>; | ||
| 282 | }; | ||
| 283 | |||
| 284 | core_l3_clkdm: core_l3_clkdm { | ||
| 285 | compatible = "ti,clockdomain"; | ||
| 286 | clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>; | ||
| 287 | }; | ||
| 288 | |||
| 289 | wkup_clkdm: wkup_clkdm { | ||
| 290 | compatible = "ti,clockdomain"; | ||
| 291 | clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>, | ||
| 292 | <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>, | ||
| 293 | <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>, | ||
| 294 | <&icr_ick>; | ||
| 295 | }; | ||
| 296 | |||
| 297 | dss_clkdm: dss_clkdm { | ||
| 298 | compatible = "ti,clockdomain"; | ||
| 299 | clocks = <&dss_ick>, <&dss_54m_fck>; | ||
| 300 | }; | ||
| 301 | |||
| 302 | core_l4_clkdm: core_l4_clkdm { | ||
| 303 | compatible = "ti,clockdomain"; | ||
| 304 | clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>, | ||
| 305 | <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>, | ||
| 306 | <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>, | ||
| 307 | <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, | ||
| 308 | <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>, | ||
| 309 | <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>, | ||
| 310 | <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>, | ||
| 311 | <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>, | ||
| 312 | <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>, | ||
| 313 | <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>, | ||
| 314 | <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>, | ||
| 315 | <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>, | ||
| 316 | <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>, | ||
| 317 | <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>, | ||
| 318 | <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>, | ||
| 319 | <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>, | ||
| 320 | <&mmchsdb2_fck>; | ||
| 321 | }; | ||
| 322 | |||
| 323 | mdm_clkdm: mdm_clkdm { | ||
| 324 | compatible = "ti,clockdomain"; | ||
| 325 | clocks = <&mdm_osc_ck>; | ||
| 326 | }; | ||
| 327 | }; | ||
| 328 | |||
| 329 | &func_96m_ck { | ||
| 330 | compatible = "ti,mux-clock"; | ||
| 331 | clocks = <&apll96_ck>, <&alt_ck>; | ||
| 332 | ti,bit-shift = <4>; | ||
| 333 | reg = <0x0540>; | ||
| 334 | }; | ||
| 335 | |||
| 336 | &dsp_div_fck { | ||
| 337 | ti,max-div = <4>; | ||
| 338 | ti,index-starts-at-one; | ||
| 339 | }; | ||
| 340 | |||
| 341 | &ssi_ssr_sst_div_fck { | ||
| 342 | ti,max-div = <5>; | ||
| 343 | ti,index-starts-at-one; | ||
| 344 | }; | ||
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 42d2c61c9e2d..c4e8013801ee 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi | |||
| @@ -14,6 +14,32 @@ | |||
| 14 | compatible = "ti,omap2430", "ti,omap2"; | 14 | compatible = "ti,omap2430", "ti,omap2"; |
| 15 | 15 | ||
| 16 | ocp { | 16 | ocp { |
| 17 | prcm: prcm@49006000 { | ||
| 18 | compatible = "ti,omap2-prcm"; | ||
| 19 | reg = <0x49006000 0x1000>; | ||
| 20 | |||
| 21 | prcm_clocks: clocks { | ||
| 22 | #address-cells = <1>; | ||
| 23 | #size-cells = <0>; | ||
| 24 | }; | ||
| 25 | |||
| 26 | prcm_clockdomains: clockdomains { | ||
| 27 | }; | ||
| 28 | }; | ||
| 29 | |||
| 30 | scrm: scrm@49002000 { | ||
| 31 | compatible = "ti,omap2-scrm"; | ||
| 32 | reg = <0x49002000 0x1000>; | ||
| 33 | |||
| 34 | scrm_clocks: clocks { | ||
| 35 | #address-cells = <1>; | ||
| 36 | #size-cells = <0>; | ||
| 37 | }; | ||
| 38 | |||
| 39 | scrm_clockdomains: clockdomains { | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | |||
| 17 | counter32k: counter@49020000 { | 43 | counter32k: counter@49020000 { |
| 18 | compatible = "ti,omap-counter32k"; | 44 | compatible = "ti,omap-counter32k"; |
| 19 | reg = <0x49020000 0x20>; | 45 | reg = <0x49020000 0x20>; |
diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi new file mode 100644 index 000000000000..a1365ca926eb --- /dev/null +++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi | |||
| @@ -0,0 +1,1244 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree Source for OMAP24xx clock data | ||
| 3 | * | ||
| 4 | * Copyright (C) 2014 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | &scrm_clocks { | ||
| 11 | mcbsp1_mux_fck: mcbsp1_mux_fck { | ||
| 12 | #clock-cells = <0>; | ||
| 13 | compatible = "ti,composite-mux-clock"; | ||
| 14 | clocks = <&func_96m_ck>, <&mcbsp_clks>; | ||
| 15 | ti,bit-shift = <2>; | ||
| 16 | reg = <0x0274>; | ||
| 17 | }; | ||
| 18 | |||
| 19 | mcbsp1_fck: mcbsp1_fck { | ||
| 20 | #clock-cells = <0>; | ||
| 21 | compatible = "ti,composite-clock"; | ||
| 22 | clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | mcbsp2_mux_fck: mcbsp2_mux_fck { | ||
| 26 | #clock-cells = <0>; | ||
| 27 | compatible = "ti,composite-mux-clock"; | ||
| 28 | clocks = <&func_96m_ck>, <&mcbsp_clks>; | ||
| 29 | ti,bit-shift = <6>; | ||
| 30 | reg = <0x0274>; | ||
| 31 | }; | ||
| 32 | |||
| 33 | mcbsp2_fck: mcbsp2_fck { | ||
| 34 | #clock-cells = <0>; | ||
| 35 | compatible = "ti,composite-clock"; | ||
| 36 | clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | |||
| 40 | &prcm_clocks { | ||
| 41 | func_32k_ck: func_32k_ck { | ||
| 42 | #clock-cells = <0>; | ||
| 43 | compatible = "fixed-clock"; | ||
| 44 | clock-frequency = <32768>; | ||
| 45 | }; | ||
| 46 | |||
| 47 | secure_32k_ck: secure_32k_ck { | ||
| 48 | #clock-cells = <0>; | ||
| 49 | compatible = "fixed-clock"; | ||
| 50 | clock-frequency = <32768>; | ||
| 51 | }; | ||
| 52 | |||
| 53 | virt_12m_ck: virt_12m_ck { | ||
| 54 | #clock-cells = <0>; | ||
| 55 | compatible = "fixed-clock"; | ||
| 56 | clock-frequency = <12000000>; | ||
| 57 | }; | ||
| 58 | |||
| 59 | virt_13m_ck: virt_13m_ck { | ||
| 60 | #clock-cells = <0>; | ||
| 61 | compatible = "fixed-clock"; | ||
| 62 | clock-frequency = <13000000>; | ||
| 63 | }; | ||
| 64 | |||
| 65 | virt_19200000_ck: virt_19200000_ck { | ||
| 66 | #clock-cells = <0>; | ||
| 67 | compatible = "fixed-clock"; | ||
| 68 | clock-frequency = <19200000>; | ||
| 69 | }; | ||
| 70 | |||
| 71 | virt_26m_ck: virt_26m_ck { | ||
| 72 | #clock-cells = <0>; | ||
| 73 | compatible = "fixed-clock"; | ||
| 74 | clock-frequency = <26000000>; | ||
| 75 | }; | ||
| 76 | |||
| 77 | aplls_clkin_ck: aplls_clkin_ck { | ||
| 78 | #clock-cells = <0>; | ||
| 79 | compatible = "ti,mux-clock"; | ||
| 80 | clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>; | ||
| 81 | ti,bit-shift = <23>; | ||
| 82 | reg = <0x0540>; | ||
| 83 | }; | ||
| 84 | |||
| 85 | aplls_clkin_x2_ck: aplls_clkin_x2_ck { | ||
| 86 | #clock-cells = <0>; | ||
| 87 | compatible = "fixed-factor-clock"; | ||
| 88 | clocks = <&aplls_clkin_ck>; | ||
| 89 | clock-mult = <2>; | ||
| 90 | clock-div = <1>; | ||
| 91 | }; | ||
| 92 | |||
| 93 | osc_ck: osc_ck { | ||
| 94 | #clock-cells = <0>; | ||
| 95 | compatible = "ti,mux-clock"; | ||
| 96 | clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>; | ||
| 97 | ti,bit-shift = <6>; | ||
| 98 | reg = <0x0060>; | ||
| 99 | ti,index-starts-at-one; | ||
| 100 | }; | ||
| 101 | |||
| 102 | sys_ck: sys_ck { | ||
| 103 | #clock-cells = <0>; | ||
| 104 | compatible = "ti,divider-clock"; | ||
| 105 | clocks = <&osc_ck>; | ||
| 106 | ti,bit-shift = <6>; | ||
| 107 | ti,max-div = <3>; | ||
| 108 | reg = <0x0060>; | ||
| 109 | ti,index-starts-at-one; | ||
| 110 | }; | ||
| 111 | |||
| 112 | alt_ck: alt_ck { | ||
| 113 | #clock-cells = <0>; | ||
| 114 | compatible = "fixed-clock"; | ||
| 115 | clock-frequency = <54000000>; | ||
| 116 | }; | ||
| 117 | |||
| 118 | mcbsp_clks: mcbsp_clks { | ||
| 119 | #clock-cells = <0>; | ||
| 120 | compatible = "fixed-clock"; | ||
| 121 | clock-frequency = <0x0>; | ||
| 122 | }; | ||
| 123 | |||
| 124 | dpll_ck: dpll_ck { | ||
| 125 | #clock-cells = <0>; | ||
| 126 | compatible = "ti,omap2-dpll-core-clock"; | ||
| 127 | clocks = <&sys_ck>, <&sys_ck>; | ||
| 128 | reg = <0x0500>, <0x0540>; | ||
| 129 | }; | ||
| 130 | |||
| 131 | apll96_ck: apll96_ck { | ||
| 132 | #clock-cells = <0>; | ||
| 133 | compatible = "ti,omap2-apll-clock"; | ||
| 134 | clocks = <&sys_ck>; | ||
| 135 | ti,bit-shift = <2>; | ||
| 136 | ti,idlest-shift = <8>; | ||
| 137 | ti,clock-frequency = <96000000>; | ||
| 138 | reg = <0x0500>, <0x0530>, <0x0520>; | ||
| 139 | }; | ||
| 140 | |||
| 141 | apll54_ck: apll54_ck { | ||
| 142 | #clock-cells = <0>; | ||
| 143 | compatible = "ti,omap2-apll-clock"; | ||
| 144 | clocks = <&sys_ck>; | ||
| 145 | ti,bit-shift = <6>; | ||
| 146 | ti,idlest-shift = <9>; | ||
| 147 | ti,clock-frequency = <54000000>; | ||
| 148 | reg = <0x0500>, <0x0530>, <0x0520>; | ||
| 149 | }; | ||
| 150 | |||
| 151 | func_54m_ck: func_54m_ck { | ||
| 152 | #clock-cells = <0>; | ||
| 153 | compatible = "ti,mux-clock"; | ||
| 154 | clocks = <&apll54_ck>, <&alt_ck>; | ||
| 155 | ti,bit-shift = <5>; | ||
| 156 | reg = <0x0540>; | ||
| 157 | }; | ||
| 158 | |||
| 159 | core_ck: core_ck { | ||
| 160 | #clock-cells = <0>; | ||
| 161 | compatible = "fixed-factor-clock"; | ||
| 162 | clocks = <&dpll_ck>; | ||
| 163 | clock-mult = <1>; | ||
| 164 | clock-div = <1>; | ||
| 165 | }; | ||
| 166 | |||
| 167 | func_96m_ck: func_96m_ck { | ||
| 168 | #clock-cells = <0>; | ||
| 169 | }; | ||
| 170 | |||
| 171 | apll96_d2_ck: apll96_d2_ck { | ||
| 172 | #clock-cells = <0>; | ||
| 173 | compatible = "fixed-factor-clock"; | ||
| 174 | clocks = <&apll96_ck>; | ||
| 175 | clock-mult = <1>; | ||
| 176 | clock-div = <2>; | ||
| 177 | }; | ||
| 178 | |||
| 179 | func_48m_ck: func_48m_ck { | ||
| 180 | #clock-cells = <0>; | ||
| 181 | compatible = "ti,mux-clock"; | ||
| 182 | clocks = <&apll96_d2_ck>, <&alt_ck>; | ||
| 183 | ti,bit-shift = <3>; | ||
| 184 | reg = <0x0540>; | ||
| 185 | }; | ||
| 186 | |||
| 187 | func_12m_ck: func_12m_ck { | ||
| 188 | #clock-cells = <0>; | ||
| 189 | compatible = "fixed-factor-clock"; | ||
| 190 | clocks = <&func_48m_ck>; | ||
| 191 | clock-mult = <1>; | ||
| 192 | clock-div = <4>; | ||
| 193 | }; | ||
| 194 | |||
| 195 | sys_clkout_src_gate: sys_clkout_src_gate { | ||
| 196 | #clock-cells = <0>; | ||
| 197 | compatible = "ti,composite-no-wait-gate-clock"; | ||
| 198 | clocks = <&core_ck>; | ||
| 199 | ti,bit-shift = <7>; | ||
| 200 | reg = <0x0070>; | ||
| 201 | }; | ||
| 202 | |||
| 203 | sys_clkout_src_mux: sys_clkout_src_mux { | ||
| 204 | #clock-cells = <0>; | ||
| 205 | compatible = "ti,composite-mux-clock"; | ||
| 206 | clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; | ||
| 207 | reg = <0x0070>; | ||
| 208 | }; | ||
| 209 | |||
| 210 | sys_clkout_src: sys_clkout_src { | ||
| 211 | #clock-cells = <0>; | ||
| 212 | compatible = "ti,composite-clock"; | ||
| 213 | clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>; | ||
| 214 | }; | ||
| 215 | |||
| 216 | sys_clkout: sys_clkout { | ||
| 217 | #clock-cells = <0>; | ||
| 218 | compatible = "ti,divider-clock"; | ||
| 219 | clocks = <&sys_clkout_src>; | ||
| 220 | ti,bit-shift = <3>; | ||
| 221 | ti,max-div = <64>; | ||
| 222 | reg = <0x0070>; | ||
| 223 | ti,index-power-of-two; | ||
| 224 | }; | ||
| 225 | |||
| 226 | emul_ck: emul_ck { | ||
| 227 | #clock-cells = <0>; | ||
| 228 | compatible = "ti,gate-clock"; | ||
| 229 | clocks = <&func_54m_ck>; | ||
| 230 | ti,bit-shift = <0>; | ||
| 231 | reg = <0x0078>; | ||
| 232 | }; | ||
| 233 | |||
| 234 | mpu_ck: mpu_ck { | ||
| 235 | #clock-cells = <0>; | ||
| 236 | compatible = "ti,divider-clock"; | ||
| 237 | clocks = <&core_ck>; | ||
| 238 | ti,max-div = <31>; | ||
| 239 | reg = <0x0140>; | ||
| 240 | ti,index-starts-at-one; | ||
| 241 | }; | ||
| 242 | |||
| 243 | dsp_gate_fck: dsp_gate_fck { | ||
| 244 | #clock-cells = <0>; | ||
| 245 | compatible = "ti,composite-gate-clock"; | ||
| 246 | clocks = <&core_ck>; | ||
| 247 | ti,bit-shift = <0>; | ||
| 248 | reg = <0x0800>; | ||
| 249 | }; | ||
| 250 | |||
| 251 | dsp_div_fck: dsp_div_fck { | ||
| 252 | #clock-cells = <0>; | ||
| 253 | compatible = "ti,composite-divider-clock"; | ||
| 254 | clocks = <&core_ck>; | ||
| 255 | reg = <0x0840>; | ||
| 256 | }; | ||
| 257 | |||
| 258 | dsp_fck: dsp_fck { | ||
| 259 | #clock-cells = <0>; | ||
| 260 | compatible = "ti,composite-clock"; | ||
| 261 | clocks = <&dsp_gate_fck>, <&dsp_div_fck>; | ||
| 262 | }; | ||
| 263 | |||
| 264 | core_l3_ck: core_l3_ck { | ||
| 265 | #clock-cells = <0>; | ||
| 266 | compatible = "ti,divider-clock"; | ||
| 267 | clocks = <&core_ck>; | ||
| 268 | ti,max-div = <31>; | ||
| 269 | reg = <0x0240>; | ||
| 270 | ti,index-starts-at-one; | ||
| 271 | }; | ||
| 272 | |||
| 273 | gfx_3d_gate_fck: gfx_3d_gate_fck { | ||
| 274 | #clock-cells = <0>; | ||
| 275 | compatible = "ti,composite-gate-clock"; | ||
| 276 | clocks = <&core_l3_ck>; | ||
| 277 | ti,bit-shift = <2>; | ||
| 278 | reg = <0x0300>; | ||
| 279 | }; | ||
| 280 | |||
| 281 | gfx_3d_div_fck: gfx_3d_div_fck { | ||
| 282 | #clock-cells = <0>; | ||
| 283 | compatible = "ti,composite-divider-clock"; | ||
| 284 | clocks = <&core_l3_ck>; | ||
| 285 | ti,max-div = <4>; | ||
| 286 | reg = <0x0340>; | ||
| 287 | ti,index-starts-at-one; | ||
| 288 | }; | ||
| 289 | |||
| 290 | gfx_3d_fck: gfx_3d_fck { | ||
| 291 | #clock-cells = <0>; | ||
| 292 | compatible = "ti,composite-clock"; | ||
| 293 | clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>; | ||
| 294 | }; | ||
| 295 | |||
| 296 | gfx_2d_gate_fck: gfx_2d_gate_fck { | ||
| 297 | #clock-cells = <0>; | ||
| 298 | compatible = "ti,composite-gate-clock"; | ||
| 299 | clocks = <&core_l3_ck>; | ||
| 300 | ti,bit-shift = <1>; | ||
| 301 | reg = <0x0300>; | ||
| 302 | }; | ||
| 303 | |||
| 304 | gfx_2d_div_fck: gfx_2d_div_fck { | ||
| 305 | #clock-cells = <0>; | ||
| 306 | compatible = "ti,composite-divider-clock"; | ||
| 307 | clocks = <&core_l3_ck>; | ||
| 308 | ti,max-div = <4>; | ||
| 309 | reg = <0x0340>; | ||
| 310 | ti,index-starts-at-one; | ||
| 311 | }; | ||
| 312 | |||
| 313 | gfx_2d_fck: gfx_2d_fck { | ||
| 314 | #clock-cells = <0>; | ||
| 315 | compatible = "ti,composite-clock"; | ||
| 316 | clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>; | ||
| 317 | }; | ||
| 318 | |||
| 319 | gfx_ick: gfx_ick { | ||
| 320 | #clock-cells = <0>; | ||
| 321 | compatible = "ti,wait-gate-clock"; | ||
| 322 | clocks = <&core_l3_ck>; | ||
| 323 | ti,bit-shift = <0>; | ||
| 324 | reg = <0x0310>; | ||
| 325 | }; | ||
| 326 | |||
| 327 | l4_ck: l4_ck { | ||
| 328 | #clock-cells = <0>; | ||
| 329 | compatible = "ti,divider-clock"; | ||
| 330 | clocks = <&core_l3_ck>; | ||
| 331 | ti,bit-shift = <5>; | ||
| 332 | ti,max-div = <3>; | ||
| 333 | reg = <0x0240>; | ||
| 334 | ti,index-starts-at-one; | ||
| 335 | }; | ||
| 336 | |||
| 337 | dss_ick: dss_ick { | ||
| 338 | #clock-cells = <0>; | ||
| 339 | compatible = "ti,omap3-no-wait-interface-clock"; | ||
| 340 | clocks = <&l4_ck>; | ||
| 341 | ti,bit-shift = <0>; | ||
| 342 | reg = <0x0210>; | ||
| 343 | }; | ||
| 344 | |||
| 345 | dss1_gate_fck: dss1_gate_fck { | ||
| 346 | #clock-cells = <0>; | ||
| 347 | compatible = "ti,composite-no-wait-gate-clock"; | ||
| 348 | clocks = <&core_ck>; | ||
| 349 | ti,bit-shift = <0>; | ||
| 350 | reg = <0x0200>; | ||
| 351 | }; | ||
| 352 | |||
| 353 | core_d2_ck: core_d2_ck { | ||
| 354 | #clock-cells = <0>; | ||
| 355 | compatible = "fixed-factor-clock"; | ||
| 356 | clocks = <&core_ck>; | ||
| 357 | clock-mult = <1>; | ||
| 358 | clock-div = <2>; | ||
| 359 | }; | ||
| 360 | |||
| 361 | core_d3_ck: core_d3_ck { | ||
| 362 | #clock-cells = <0>; | ||
| 363 | compatible = "fixed-factor-clock"; | ||
| 364 | clocks = <&core_ck>; | ||
| 365 | clock-mult = <1>; | ||
| 366 | clock-div = <3>; | ||
| 367 | }; | ||
| 368 | |||
| 369 | core_d4_ck: core_d4_ck { | ||
| 370 | #clock-cells = <0>; | ||
| 371 | compatible = "fixed-factor-clock"; | ||
| 372 | clocks = <&core_ck>; | ||
| 373 | clock-mult = <1>; | ||
| 374 | clock-div = <4>; | ||
| 375 | }; | ||
| 376 | |||
| 377 | core_d5_ck: core_d5_ck { | ||
| 378 | #clock-cells = <0>; | ||
| 379 | compatible = "fixed-factor-clock"; | ||
| 380 | clocks = <&core_ck>; | ||
| 381 | clock-mult = <1>; | ||
| 382 | clock-div = <5>; | ||
| 383 | }; | ||
| 384 | |||
| 385 | core_d6_ck: core_d6_ck { | ||
| 386 | #clock-cells = <0>; | ||
| 387 | compatible = "fixed-factor-clock"; | ||
| 388 | clocks = <&core_ck>; | ||
| 389 | clock-mult = <1>; | ||
| 390 | clock-div = <6>; | ||
| 391 | }; | ||
| 392 | |||
| 393 | dummy_ck: dummy_ck { | ||
| 394 | #clock-cells = <0>; | ||
| 395 | compatible = "fixed-clock"; | ||
| 396 | clock-frequency = <0>; | ||
| 397 | }; | ||
| 398 | |||
| 399 | core_d8_ck: core_d8_ck { | ||
| 400 | #clock-cells = <0>; | ||
| 401 | compatible = "fixed-factor-clock"; | ||
| 402 | clocks = <&core_ck>; | ||
| 403 | clock-mult = <1>; | ||
| 404 | clock-div = <8>; | ||
| 405 | }; | ||
| 406 | |||
| 407 | core_d9_ck: core_d9_ck { | ||
| 408 | #clock-cells = <0>; | ||
| 409 | compatible = "fixed-factor-clock"; | ||
| 410 | clocks = <&core_ck>; | ||
| 411 | clock-mult = <1>; | ||
| 412 | clock-div = <9>; | ||
| 413 | }; | ||
| 414 | |||
| 415 | core_d12_ck: core_d12_ck { | ||
| 416 | #clock-cells = <0>; | ||
| 417 | compatible = "fixed-factor-clock"; | ||
| 418 | clocks = <&core_ck>; | ||
| 419 | clock-mult = <1>; | ||
| 420 | clock-div = <12>; | ||
| 421 | }; | ||
| 422 | |||
| 423 | core_d16_ck: core_d16_ck { | ||
| 424 | #clock-cells = <0>; | ||
| 425 | compatible = "fixed-factor-clock"; | ||
| 426 | clocks = <&core_ck>; | ||
| 427 | clock-mult = <1>; | ||
| 428 | clock-div = <16>; | ||
| 429 | }; | ||
| 430 | |||
| 431 | dss1_mux_fck: dss1_mux_fck { | ||
| 432 | #clock-cells = <0>; | ||
| 433 | compatible = "ti,composite-mux-clock"; | ||
| 434 | clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>; | ||
| 435 | ti,bit-shift = <8>; | ||
| 436 | reg = <0x0240>; | ||
| 437 | }; | ||
| 438 | |||
| 439 | dss1_fck: dss1_fck { | ||
| 440 | #clock-cells = <0>; | ||
| 441 | compatible = "ti,composite-clock"; | ||
| 442 | clocks = <&dss1_gate_fck>, <&dss1_mux_fck>; | ||
| 443 | }; | ||
| 444 | |||
| 445 | dss2_gate_fck: dss2_gate_fck { | ||
| 446 | #clock-cells = <0>; | ||
| 447 | compatible = "ti,composite-no-wait-gate-clock"; | ||
| 448 | clocks = <&func_48m_ck>; | ||
| 449 | ti,bit-shift = <1>; | ||
| 450 | reg = <0x0200>; | ||
| 451 | }; | ||
| 452 | |||
| 453 | dss2_mux_fck: dss2_mux_fck { | ||
| 454 | #clock-cells = <0>; | ||
| 455 | compatible = "ti,composite-mux-clock"; | ||
| 456 | clocks = <&sys_ck>, <&func_48m_ck>; | ||
| 457 | ti,bit-shift = <13>; | ||
| 458 | reg = <0x0240>; | ||
| 459 | }; | ||
| 460 | |||
| 461 | dss2_fck: dss2_fck { | ||
| 462 | #clock-cells = <0>; | ||
| 463 | compatible = "ti,composite-clock"; | ||
| 464 | clocks = <&dss2_gate_fck>, <&dss2_mux_fck>; | ||
| 465 | }; | ||
| 466 | |||
| 467 | dss_54m_fck: dss_54m_fck { | ||
| 468 | #clock-cells = <0>; | ||
| 469 | compatible = "ti,wait-gate-clock"; | ||
| 470 | clocks = <&func_54m_ck>; | ||
| 471 | ti,bit-shift = <2>; | ||
| 472 | reg = <0x0200>; | ||
| 473 | }; | ||
| 474 | |||
| 475 | ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck { | ||
| 476 | #clock-cells = <0>; | ||
| 477 | compatible = "ti,composite-gate-clock"; | ||
| 478 | clocks = <&core_ck>; | ||
| 479 | ti,bit-shift = <1>; | ||
| 480 | reg = <0x0204>; | ||
| 481 | }; | ||
| 482 | |||
| 483 | ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck { | ||
| 484 | #clock-cells = <0>; | ||
| 485 | compatible = "ti,composite-divider-clock"; | ||
| 486 | clocks = <&core_ck>; | ||
| 487 | ti,bit-shift = <20>; | ||
| 488 | reg = <0x0240>; | ||
| 489 | }; | ||
| 490 | |||
| 491 | ssi_ssr_sst_fck: ssi_ssr_sst_fck { | ||
| 492 | #clock-cells = <0>; | ||
| 493 | compatible = "ti,composite-clock"; | ||
| 494 | clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>; | ||
| 495 | }; | ||
| 496 | |||
| 497 | usb_l4_gate_ick: usb_l4_gate_ick { | ||
| 498 | #clock-cells = <0>; | ||
| 499 | compatible = "ti,composite-interface-clock"; | ||
| 500 | clocks = <&core_l3_ck>; | ||
| 501 | ti,bit-shift = <0>; | ||
| 502 | reg = <0x0214>; | ||
| 503 | }; | ||
| 504 | |||
| 505 | usb_l4_div_ick: usb_l4_div_ick { | ||
| 506 | #clock-cells = <0>; | ||
| 507 | compatible = "ti,composite-divider-clock"; | ||
| 508 | clocks = <&core_l3_ck>; | ||
| 509 | ti,bit-shift = <25>; | ||
| 510 | reg = <0x0240>; | ||
| 511 | ti,dividers = <0>, <1>, <2>, <0>, <4>; | ||
| 512 | }; | ||
| 513 | |||
| 514 | usb_l4_ick: usb_l4_ick { | ||
| 515 | #clock-cells = <0>; | ||
| 516 | compatible = "ti,composite-clock"; | ||
| 517 | clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; | ||
| 518 | }; | ||
| 519 | |||
| 520 | ssi_l4_ick: ssi_l4_ick { | ||
| 521 | #clock-cells = <0>; | ||
| 522 | compatible = "ti,omap3-interface-clock"; | ||
| 523 | clocks = <&l4_ck>; | ||
| 524 | ti,bit-shift = <1>; | ||
| 525 | reg = <0x0214>; | ||
| 526 | }; | ||
| 527 | |||
| 528 | gpt1_ick: gpt1_ick { | ||
| 529 | #clock-cells = <0>; | ||
| 530 | compatible = "ti,omap3-interface-clock"; | ||
| 531 | clocks = <&sys_ck>; | ||
| 532 | ti,bit-shift = <0>; | ||
| 533 | reg = <0x0410>; | ||
| 534 | }; | ||
| 535 | |||
| 536 | gpt1_gate_fck: gpt1_gate_fck { | ||
| 537 | #clock-cells = <0>; | ||
| 538 | compatible = "ti,composite-gate-clock"; | ||
| 539 | clocks = <&func_32k_ck>; | ||
| 540 | ti,bit-shift = <0>; | ||
| 541 | reg = <0x0400>; | ||
| 542 | }; | ||
| 543 | |||
| 544 | gpt1_mux_fck: gpt1_mux_fck { | ||
| 545 | #clock-cells = <0>; | ||
| 546 | compatible = "ti,composite-mux-clock"; | ||
| 547 | clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; | ||
| 548 | reg = <0x0440>; | ||
| 549 | }; | ||
| 550 | |||
| 551 | gpt1_fck: gpt1_fck { | ||
| 552 | #clock-cells = <0>; | ||
| 553 | compatible = "ti,composite-clock"; | ||
| 554 | clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; | ||
| 555 | }; | ||
| 556 | |||
| 557 | gpt2_ick: gpt2_ick { | ||
| 558 | #clock-cells = <0>; | ||
| 559 | compatible = "ti,omap3-interface-clock"; | ||
| 560 | clocks = <&l4_ck>; | ||
| 561 | ti,bit-shift = <4>; | ||
| 562 | reg = <0x0210>; | ||
| 563 | }; | ||
| 564 | |||
| 565 | gpt2_gate_fck: gpt2_gate_fck { | ||
| 566 | #clock-cells = <0>; | ||
| 567 | compatible = "ti,composite-gate-clock"; | ||
| 568 | clocks = <&func_32k_ck>; | ||
| 569 | ti,bit-shift = <4>; | ||
| 570 | reg = <0x0200>; | ||
| 571 | }; | ||
| 572 | |||
| 573 | gpt2_mux_fck: gpt2_mux_fck { | ||
| 574 | #clock-cells = <0>; | ||
| 575 | compatible = "ti,composite-mux-clock"; | ||
| 576 | clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; | ||
| 577 | ti,bit-shift = <2>; | ||
| 578 | reg = <0x0244>; | ||
| 579 | }; | ||
| 580 | |||
| 581 | gpt2_fck: gpt2_fck { | ||
| 582 | #clock-cells = <0>; | ||
| 583 | compatible = "ti,composite-clock"; | ||
| 584 | clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; | ||
| 585 | }; | ||
| 586 | |||
| 587 | gpt3_ick: gpt3_ick { | ||
| 588 | #clock-cells = <0>; | ||
| 589 | compatible = "ti,omap3-interface-clock"; | ||
| 590 | clocks = <&l4_ck>; | ||
| 591 | ti,bit-shift = <5>; | ||
| 592 | reg = <0x0210>; | ||
| 593 | }; | ||
| 594 | |||
| 595 | gpt3_gate_fck: gpt3_gate_fck { | ||
| 596 | #clock-cells = <0>; | ||
| 597 | compatible = "ti,composite-gate-clock"; | ||
| 598 | clocks = <&func_32k_ck>; | ||
| 599 | ti,bit-shift = <5>; | ||
| 600 | reg = <0x0200>; | ||
| 601 | }; | ||
| 602 | |||
| 603 | gpt3_mux_fck: gpt3_mux_fck { | ||
| 604 | #clock-cells = <0>; | ||
| 605 | compatible = "ti,composite-mux-clock"; | ||
| 606 | clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; | ||
| 607 | ti,bit-shift = <4>; | ||
| 608 | reg = <0x0244>; | ||
| 609 | }; | ||
| 610 | |||
| 611 | gpt3_fck: gpt3_fck { | ||
| 612 | #clock-cells = <0>; | ||
| 613 | compatible = "ti,composite-clock"; | ||
| 614 | clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; | ||
| 615 | }; | ||
| 616 | |||
| 617 | gpt4_ick: gpt4_ick { | ||
| 618 | #clock-cells = <0>; | ||
| 619 | compatible = "ti,omap3-interface-clock"; | ||
| 620 | clocks = <&l4_ck>; | ||
| 621 | ti,bit-shift = <6>; | ||
| 622 | reg = <0x0210>; | ||
| 623 | }; | ||
| 624 | |||
| 625 | gpt4_gate_fck: gpt4_gate_fck { | ||
| 626 | #clock-cells = <0>; | ||
| 627 | compatible = "ti,composite-gate-clock"; | ||
| 628 | clocks = <&func_32k_ck>; | ||
| 629 | ti,bit-shift = <6>; | ||
| 630 | reg = <0x0200>; | ||
| 631 | }; | ||
| 632 | |||
| 633 | gpt4_mux_fck: gpt4_mux_fck { | ||
| 634 | #clock-cells = <0>; | ||
| 635 | compatible = "ti,composite-mux-clock"; | ||
| 636 | clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; | ||
| 637 | ti,bit-shift = <6>; | ||
| 638 | reg = <0x0244>; | ||
| 639 | }; | ||
| 640 | |||
| 641 | gpt4_fck: gpt4_fck { | ||
| 642 | #clock-cells = <0>; | ||
| 643 | compatible = "ti,composite-clock"; | ||
| 644 | clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; | ||
| 645 | }; | ||
| 646 | |||
| 647 | gpt5_ick: gpt5_ick { | ||
| 648 | #clock-cells = <0>; | ||
| 649 | compatible = "ti,omap3-interface-clock"; | ||
| 650 | clocks = <&l4_ck>; | ||
| 651 | ti,bit-shift = <7>; | ||
| 652 | reg = <0x0210>; | ||
| 653 | }; | ||
| 654 | |||
| 655 | gpt5_gate_fck: gpt5_gate_fck { | ||
| 656 | #clock-cells = <0>; | ||
| 657 | compatible = "ti,composite-gate-clock"; | ||
| 658 | clocks = <&func_32k_ck>; | ||
| 659 | ti,bit-shift = <7>; | ||
| 660 | reg = <0x0200>; | ||
| 661 | }; | ||
| 662 | |||
| 663 | gpt5_mux_fck: gpt5_mux_fck { | ||
| 664 | #clock-cells = <0>; | ||
| 665 | compatible = "ti,composite-mux-clock"; | ||
| 666 | clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; | ||
| 667 | ti,bit-shift = <8>; | ||
| 668 | reg = <0x0244>; | ||
| 669 | }; | ||
| 670 | |||
| 671 | gpt5_fck: gpt5_fck { | ||
| 672 | #clock-cells = <0>; | ||
| 673 | compatible = "ti,composite-clock"; | ||
| 674 | clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; | ||
| 675 | }; | ||
| 676 | |||
| 677 | gpt6_ick: gpt6_ick { | ||
| 678 | #clock-cells = <0>; | ||
| 679 | compatible = "ti,omap3-interface-clock"; | ||
| 680 | clocks = <&l4_ck>; | ||
| 681 | ti,bit-shift = <8>; | ||
| 682 | reg = <0x0210>; | ||
| 683 | }; | ||
| 684 | |||
| 685 | gpt6_gate_fck: gpt6_gate_fck { | ||
| 686 | #clock-cells = <0>; | ||
| 687 | compatible = "ti,composite-gate-clock"; | ||
| 688 | clocks = <&func_32k_ck>; | ||
| 689 | ti,bit-shift = <8>; | ||
| 690 | reg = <0x0200>; | ||
| 691 | }; | ||
| 692 | |||
| 693 | gpt6_mux_fck: gpt6_mux_fck { | ||
| 694 | #clock-cells = <0>; | ||
| 695 | compatible = "ti,composite-mux-clock"; | ||
| 696 | clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; | ||
| 697 | ti,bit-shift = <10>; | ||
| 698 | reg = <0x0244>; | ||
| 699 | }; | ||
| 700 | |||
| 701 | gpt6_fck: gpt6_fck { | ||
| 702 | #clock-cells = <0>; | ||
| 703 | compatible = "ti,composite-clock"; | ||
| 704 | clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; | ||
| 705 | }; | ||
| 706 | |||
| 707 | gpt7_ick: gpt7_ick { | ||
| 708 | #clock-cells = <0>; | ||
| 709 | compatible = "ti,omap3-interface-clock"; | ||
| 710 | clocks = <&l4_ck>; | ||
| 711 | ti,bit-shift = <9>; | ||
| 712 | reg = <0x0210>; | ||
| 713 | }; | ||
| 714 | |||
| 715 | gpt7_gate_fck: gpt7_gate_fck { | ||
| 716 | #clock-cells = <0>; | ||
| 717 | compatible = "ti,composite-gate-clock"; | ||
| 718 | clocks = <&func_32k_ck>; | ||
| 719 | ti,bit-shift = <9>; | ||
| 720 | reg = <0x0200>; | ||
| 721 | }; | ||
| 722 | |||
| 723 | gpt7_mux_fck: gpt7_mux_fck { | ||
| 724 | #clock-cells = <0>; | ||
| 725 | compatible = "ti,composite-mux-clock"; | ||
| 726 | clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; | ||
| 727 | ti,bit-shift = <12>; | ||
| 728 | reg = <0x0244>; | ||
| 729 | }; | ||
| 730 | |||
| 731 | gpt7_fck: gpt7_fck { | ||
| 732 | #clock-cells = <0>; | ||
| 733 | compatible = "ti,composite-clock"; | ||
| 734 | clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; | ||
| 735 | }; | ||
| 736 | |||
| 737 | gpt8_ick: gpt8_ick { | ||
| 738 | #clock-cells = <0>; | ||
| 739 | compatible = "ti,omap3-interface-clock"; | ||
| 740 | clocks = <&l4_ck>; | ||
| 741 | ti,bit-shift = <10>; | ||
| 742 | reg = <0x0210>; | ||
| 743 | }; | ||
| 744 | |||
| 745 | gpt8_gate_fck: gpt8_gate_fck { | ||
| 746 | #clock-cells = <0>; | ||
| 747 | compatible = "ti,composite-gate-clock"; | ||
| 748 | clocks = <&func_32k_ck>; | ||
| 749 | ti,bit-shift = <10>; | ||
| 750 | reg = <0x0200>; | ||
| 751 | }; | ||
| 752 | |||
| 753 | gpt8_mux_fck: gpt8_mux_fck { | ||
| 754 | #clock-cells = <0>; | ||
| 755 | compatible = "ti,composite-mux-clock"; | ||
| 756 | clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; | ||
| 757 | ti,bit-shift = <14>; | ||
| 758 | reg = <0x0244>; | ||
| 759 | }; | ||
| 760 | |||
| 761 | gpt8_fck: gpt8_fck { | ||
| 762 | #clock-cells = <0>; | ||
| 763 | compatible = "ti,composite-clock"; | ||
| 764 | clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; | ||
| 765 | }; | ||
| 766 | |||
| 767 | gpt9_ick: gpt9_ick { | ||
| 768 | #clock-cells = <0>; | ||
| 769 | compatible = "ti,omap3-interface-clock"; | ||
| 770 | clocks = <&l4_ck>; | ||
| 771 | ti,bit-shift = <11>; | ||
| 772 | reg = <0x0210>; | ||
| 773 | }; | ||
| 774 | |||
| 775 | gpt9_gate_fck: gpt9_gate_fck { | ||
| 776 | #clock-cells = <0>; | ||
| 777 | compatible = "ti,composite-gate-clock"; | ||
| 778 | clocks = <&func_32k_ck>; | ||
| 779 | ti,bit-shift = <11>; | ||
| 780 | reg = <0x0200>; | ||
| 781 | }; | ||
| 782 | |||
| 783 | gpt9_mux_fck: gpt9_mux_fck { | ||
| 784 | #clock-cells = <0>; | ||
| 785 | compatible = "ti,composite-mux-clock"; | ||
| 786 | clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; | ||
| 787 | ti,bit-shift = <16>; | ||
| 788 | reg = <0x0244>; | ||
| 789 | }; | ||
| 790 | |||
| 791 | gpt9_fck: gpt9_fck { | ||
| 792 | #clock-cells = <0>; | ||
| 793 | compatible = "ti,composite-clock"; | ||
| 794 | clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; | ||
| 795 | }; | ||
| 796 | |||
| 797 | gpt10_ick: gpt10_ick { | ||
| 798 | #clock-cells = <0>; | ||
| 799 | compatible = "ti,omap3-interface-clock"; | ||
| 800 | clocks = <&l4_ck>; | ||
| 801 | ti,bit-shift = <12>; | ||
| 802 | reg = <0x0210>; | ||
| 803 | }; | ||
| 804 | |||
| 805 | gpt10_gate_fck: gpt10_gate_fck { | ||
| 806 | #clock-cells = <0>; | ||
| 807 | compatible = "ti,composite-gate-clock"; | ||
| 808 | clocks = <&func_32k_ck>; | ||
| 809 | ti,bit-shift = <12>; | ||
| 810 | reg = <0x0200>; | ||
| 811 | }; | ||
| 812 | |||
| 813 | gpt10_mux_fck: gpt10_mux_fck { | ||
| 814 | #clock-cells = <0>; | ||
| 815 | compatible = "ti,composite-mux-clock"; | ||
| 816 | clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; | ||
| 817 | ti,bit-shift = <18>; | ||
| 818 | reg = <0x0244>; | ||
| 819 | }; | ||
| 820 | |||
| 821 | gpt10_fck: gpt10_fck { | ||
| 822 | #clock-cells = <0>; | ||
| 823 | compatible = "ti,composite-clock"; | ||
| 824 | clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; | ||
| 825 | }; | ||
| 826 | |||
| 827 | gpt11_ick: gpt11_ick { | ||
| 828 | #clock-cells = <0>; | ||
| 829 | compatible = "ti,omap3-interface-clock"; | ||
| 830 | clocks = <&l4_ck>; | ||
| 831 | ti,bit-shift = <13>; | ||
| 832 | reg = <0x0210>; | ||
| 833 | }; | ||
| 834 | |||
| 835 | gpt11_gate_fck: gpt11_gate_fck { | ||
| 836 | #clock-cells = <0>; | ||
| 837 | compatible = "ti,composite-gate-clock"; | ||
| 838 | clocks = <&func_32k_ck>; | ||
| 839 | ti,bit-shift = <13>; | ||
| 840 | reg = <0x0200>; | ||
| 841 | }; | ||
| 842 | |||
| 843 | gpt11_mux_fck: gpt11_mux_fck { | ||
| 844 | #clock-cells = <0>; | ||
| 845 | compatible = "ti,composite-mux-clock"; | ||
| 846 | clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; | ||
| 847 | ti,bit-shift = <20>; | ||
| 848 | reg = <0x0244>; | ||
| 849 | }; | ||
| 850 | |||
| 851 | gpt11_fck: gpt11_fck { | ||
| 852 | #clock-cells = <0>; | ||
| 853 | compatible = "ti,composite-clock"; | ||
| 854 | clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; | ||
| 855 | }; | ||
| 856 | |||
| 857 | gpt12_ick: gpt12_ick { | ||
| 858 | #clock-cells = <0>; | ||
| 859 | compatible = "ti,omap3-interface-clock"; | ||
| 860 | clocks = <&l4_ck>; | ||
| 861 | ti,bit-shift = <14>; | ||
| 862 | reg = <0x0210>; | ||
| 863 | }; | ||
| 864 | |||
| 865 | gpt12_gate_fck: gpt12_gate_fck { | ||
| 866 | #clock-cells = <0>; | ||
| 867 | compatible = "ti,composite-gate-clock"; | ||
| 868 | clocks = <&func_32k_ck>; | ||
| 869 | ti,bit-shift = <14>; | ||
| 870 | reg = <0x0200>; | ||
| 871 | }; | ||
| 872 | |||
| 873 | gpt12_mux_fck: gpt12_mux_fck { | ||
| 874 | #clock-cells = <0>; | ||
| 875 | compatible = "ti,composite-mux-clock"; | ||
| 876 | clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; | ||
| 877 | ti,bit-shift = <22>; | ||
| 878 | reg = <0x0244>; | ||
| 879 | }; | ||
| 880 | |||
| 881 | gpt12_fck: gpt12_fck { | ||
| 882 | #clock-cells = <0>; | ||
| 883 | compatible = "ti,composite-clock"; | ||
| 884 | clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>; | ||
| 885 | }; | ||
| 886 | |||
| 887 | mcbsp1_ick: mcbsp1_ick { | ||
| 888 | #clock-cells = <0>; | ||
| 889 | compatible = "ti,omap3-interface-clock"; | ||
| 890 | clocks = <&l4_ck>; | ||
| 891 | ti,bit-shift = <15>; | ||
| 892 | reg = <0x0210>; | ||
| 893 | }; | ||
| 894 | |||
| 895 | mcbsp1_gate_fck: mcbsp1_gate_fck { | ||
| 896 | #clock-cells = <0>; | ||
| 897 | compatible = "ti,composite-gate-clock"; | ||
| 898 | clocks = <&mcbsp_clks>; | ||
| 899 | ti,bit-shift = <15>; | ||
| 900 | reg = <0x0200>; | ||
| 901 | }; | ||
| 902 | |||
| 903 | mcbsp2_ick: mcbsp2_ick { | ||
| 904 | #clock-cells = <0>; | ||
| 905 | compatible = "ti,omap3-interface-clock"; | ||
| 906 | clocks = <&l4_ck>; | ||
| 907 | ti,bit-shift = <16>; | ||
| 908 | reg = <0x0210>; | ||
| 909 | }; | ||
| 910 | |||
| 911 | mcbsp2_gate_fck: mcbsp2_gate_fck { | ||
| 912 | #clock-cells = <0>; | ||
| 913 | compatible = "ti,composite-gate-clock"; | ||
| 914 | clocks = <&mcbsp_clks>; | ||
| 915 | ti,bit-shift = <16>; | ||
| 916 | reg = <0x0200>; | ||
| 917 | }; | ||
| 918 | |||
| 919 | mcspi1_ick: mcspi1_ick { | ||
| 920 | #clock-cells = <0>; | ||
| 921 | compatible = "ti,omap3-interface-clock"; | ||
| 922 | clocks = <&l4_ck>; | ||
| 923 | ti,bit-shift = <17>; | ||
| 924 | reg = <0x0210>; | ||
| 925 | }; | ||
| 926 | |||
| 927 | mcspi1_fck: mcspi1_fck { | ||
| 928 | #clock-cells = <0>; | ||
| 929 | compatible = "ti,wait-gate-clock"; | ||
| 930 | clocks = <&func_48m_ck>; | ||
| 931 | ti,bit-shift = <17>; | ||
| 932 | reg = <0x0200>; | ||
| 933 | }; | ||
| 934 | |||
| 935 | mcspi2_ick: mcspi2_ick { | ||
| 936 | #clock-cells = <0>; | ||
| 937 | compatible = "ti,omap3-interface-clock"; | ||
| 938 | clocks = <&l4_ck>; | ||
| 939 | ti,bit-shift = <18>; | ||
| 940 | reg = <0x0210>; | ||
| 941 | }; | ||
| 942 | |||
| 943 | mcspi2_fck: mcspi2_fck { | ||
| 944 | #clock-cells = <0>; | ||
| 945 | compatible = "ti,wait-gate-clock"; | ||
| 946 | clocks = <&func_48m_ck>; | ||
| 947 | ti,bit-shift = <18>; | ||
| 948 | reg = <0x0200>; | ||
| 949 | }; | ||
| 950 | |||
| 951 | uart1_ick: uart1_ick { | ||
| 952 | #clock-cells = <0>; | ||
| 953 | compatible = "ti,omap3-interface-clock"; | ||
| 954 | clocks = <&l4_ck>; | ||
| 955 | ti,bit-shift = <21>; | ||
| 956 | reg = <0x0210>; | ||
| 957 | }; | ||
| 958 | |||
| 959 | uart1_fck: uart1_fck { | ||
| 960 | #clock-cells = <0>; | ||
| 961 | compatible = "ti,wait-gate-clock"; | ||
| 962 | clocks = <&func_48m_ck>; | ||
| 963 | ti,bit-shift = <21>; | ||
| 964 | reg = <0x0200>; | ||
| 965 | }; | ||
| 966 | |||
| 967 | uart2_ick: uart2_ick { | ||
| 968 | #clock-cells = <0>; | ||
| 969 | compatible = "ti,omap3-interface-clock"; | ||
| 970 | clocks = <&l4_ck>; | ||
| 971 | ti,bit-shift = <22>; | ||
| 972 | reg = <0x0210>; | ||
| 973 | }; | ||
| 974 | |||
| 975 | uart2_fck: uart2_fck { | ||
| 976 | #clock-cells = <0>; | ||
| 977 | compatible = "ti,wait-gate-clock"; | ||
| 978 | clocks = <&func_48m_ck>; | ||
| 979 | ti,bit-shift = <22>; | ||
| 980 | reg = <0x0200>; | ||
| 981 | }; | ||
| 982 | |||
| 983 | uart3_ick: uart3_ick { | ||
| 984 | #clock-cells = <0>; | ||
| 985 | compatible = "ti,omap3-interface-clock"; | ||
| 986 | clocks = <&l4_ck>; | ||
| 987 | ti,bit-shift = <2>; | ||
| 988 | reg = <0x0214>; | ||
| 989 | }; | ||
| 990 | |||
| 991 | uart3_fck: uart3_fck { | ||
| 992 | #clock-cells = <0>; | ||
| 993 | compatible = "ti,wait-gate-clock"; | ||
| 994 | clocks = <&func_48m_ck>; | ||
| 995 | ti,bit-shift = <2>; | ||
| 996 | reg = <0x0204>; | ||
| 997 | }; | ||
| 998 | |||
| 999 | gpios_ick: gpios_ick { | ||
| 1000 | #clock-cells = <0>; | ||
| 1001 | compatible = "ti,omap3-interface-clock"; | ||
| 1002 | clocks = <&sys_ck>; | ||
| 1003 | ti,bit-shift = <2>; | ||
| 1004 | reg = <0x0410>; | ||
| 1005 | }; | ||
| 1006 | |||
| 1007 | gpios_fck: gpios_fck { | ||
| 1008 | #clock-cells = <0>; | ||
| 1009 | compatible = "ti,wait-gate-clock"; | ||
| 1010 | clocks = <&func_32k_ck>; | ||
| 1011 | ti,bit-shift = <2>; | ||
| 1012 | reg = <0x0400>; | ||
| 1013 | }; | ||
| 1014 | |||
| 1015 | mpu_wdt_ick: mpu_wdt_ick { | ||
| 1016 | #clock-cells = <0>; | ||
| 1017 | compatible = "ti,omap3-interface-clock"; | ||
| 1018 | clocks = <&sys_ck>; | ||
| 1019 | ti,bit-shift = <3>; | ||
| 1020 | reg = <0x0410>; | ||
| 1021 | }; | ||
| 1022 | |||
| 1023 | mpu_wdt_fck: mpu_wdt_fck { | ||
| 1024 | #clock-cells = <0>; | ||
| 1025 | compatible = "ti,wait-gate-clock"; | ||
| 1026 | clocks = <&func_32k_ck>; | ||
| 1027 | ti,bit-shift = <3>; | ||
| 1028 | reg = <0x0400>; | ||
| 1029 | }; | ||
| 1030 | |||
| 1031 | sync_32k_ick: sync_32k_ick { | ||
| 1032 | #clock-cells = <0>; | ||
| 1033 | compatible = "ti,omap3-interface-clock"; | ||
| 1034 | clocks = <&sys_ck>; | ||
| 1035 | ti,bit-shift = <1>; | ||
| 1036 | reg = <0x0410>; | ||
| 1037 | }; | ||
| 1038 | |||
| 1039 | wdt1_ick: wdt1_ick { | ||
| 1040 | #clock-cells = <0>; | ||
| 1041 | compatible = "ti,omap3-interface-clock"; | ||
| 1042 | clocks = <&sys_ck>; | ||
| 1043 | ti,bit-shift = <4>; | ||
| 1044 | reg = <0x0410>; | ||
| 1045 | }; | ||
| 1046 | |||
| 1047 | omapctrl_ick: omapctrl_ick { | ||
| 1048 | #clock-cells = <0>; | ||
| 1049 | compatible = "ti,omap3-interface-clock"; | ||
| 1050 | clocks = <&sys_ck>; | ||
| 1051 | ti,bit-shift = <5>; | ||
| 1052 | reg = <0x0410>; | ||
| 1053 | }; | ||
| 1054 | |||
| 1055 | cam_fck: cam_fck { | ||
| 1056 | #clock-cells = <0>; | ||
| 1057 | compatible = "ti,gate-clock"; | ||
| 1058 | clocks = <&func_96m_ck>; | ||
| 1059 | ti,bit-shift = <31>; | ||
| 1060 | reg = <0x0200>; | ||
| 1061 | }; | ||
| 1062 | |||
| 1063 | cam_ick: cam_ick { | ||
| 1064 | #clock-cells = <0>; | ||
| 1065 | compatible = "ti,omap3-no-wait-interface-clock"; | ||
| 1066 | clocks = <&l4_ck>; | ||
| 1067 | ti,bit-shift = <31>; | ||
| 1068 | reg = <0x0210>; | ||
| 1069 | }; | ||
| 1070 | |||
| 1071 | mailboxes_ick: mailboxes_ick { | ||
| 1072 | #clock-cells = <0>; | ||
| 1073 | compatible = "ti,omap3-interface-clock"; | ||
| 1074 | clocks = <&l4_ck>; | ||
| 1075 | ti,bit-shift = <30>; | ||
| 1076 | reg = <0x0210>; | ||
| 1077 | }; | ||
| 1078 | |||
| 1079 | wdt4_ick: wdt4_ick { | ||
| 1080 | #clock-cells = <0>; | ||
| 1081 | compatible = "ti,omap3-interface-clock"; | ||
| 1082 | clocks = <&l4_ck>; | ||
| 1083 | ti,bit-shift = <29>; | ||
| 1084 | reg = <0x0210>; | ||
| 1085 | }; | ||
| 1086 | |||
| 1087 | wdt4_fck: wdt4_fck { | ||
| 1088 | #clock-cells = <0>; | ||
| 1089 | compatible = "ti,wait-gate-clock"; | ||
| 1090 | clocks = <&func_32k_ck>; | ||
| 1091 | ti,bit-shift = <29>; | ||
| 1092 | reg = <0x0200>; | ||
| 1093 | }; | ||
| 1094 | |||
| 1095 | mspro_ick: mspro_ick { | ||
| 1096 | #clock-cells = <0>; | ||
| 1097 | compatible = "ti,omap3-interface-clock"; | ||
| 1098 | clocks = <&l4_ck>; | ||
| 1099 | ti,bit-shift = <27>; | ||
| 1100 | reg = <0x0210>; | ||
| 1101 | }; | ||
| 1102 | |||
| 1103 | mspro_fck: mspro_fck { | ||
| 1104 | #clock-cells = <0>; | ||
| 1105 | compatible = "ti,wait-gate-clock"; | ||
| 1106 | clocks = <&func_96m_ck>; | ||
| 1107 | ti,bit-shift = <27>; | ||
| 1108 | reg = <0x0200>; | ||
| 1109 | }; | ||
| 1110 | |||
| 1111 | fac_ick: fac_ick { | ||
| 1112 | #clock-cells = <0>; | ||
| 1113 | compatible = "ti,omap3-interface-clock"; | ||
| 1114 | clocks = <&l4_ck>; | ||
| 1115 | ti,bit-shift = <25>; | ||
| 1116 | reg = <0x0210>; | ||
| 1117 | }; | ||
| 1118 | |||
| 1119 | fac_fck: fac_fck { | ||
| 1120 | #clock-cells = <0>; | ||
| 1121 | compatible = "ti,wait-gate-clock"; | ||
| 1122 | clocks = <&func_12m_ck>; | ||
| 1123 | ti,bit-shift = <25>; | ||
| 1124 | reg = <0x0200>; | ||
| 1125 | }; | ||
| 1126 | |||
| 1127 | hdq_ick: hdq_ick { | ||
| 1128 | #clock-cells = <0>; | ||
| 1129 | compatible = "ti,omap3-interface-clock"; | ||
| 1130 | clocks = <&l4_ck>; | ||
| 1131 | ti,bit-shift = <23>; | ||
| 1132 | reg = <0x0210>; | ||
| 1133 | }; | ||
| 1134 | |||
| 1135 | hdq_fck: hdq_fck { | ||
| 1136 | #clock-cells = <0>; | ||
| 1137 | compatible = "ti,wait-gate-clock"; | ||
| 1138 | clocks = <&func_12m_ck>; | ||
| 1139 | ti,bit-shift = <23>; | ||
| 1140 | reg = <0x0200>; | ||
| 1141 | }; | ||
| 1142 | |||
| 1143 | i2c1_ick: i2c1_ick { | ||
| 1144 | #clock-cells = <0>; | ||
| 1145 | compatible = "ti,omap3-interface-clock"; | ||
| 1146 | clocks = <&l4_ck>; | ||
| 1147 | ti,bit-shift = <19>; | ||
| 1148 | reg = <0x0210>; | ||
| 1149 | }; | ||
| 1150 | |||
| 1151 | i2c2_ick: i2c2_ick { | ||
| 1152 | #clock-cells = <0>; | ||
| 1153 | compatible = "ti,omap3-interface-clock"; | ||
| 1154 | clocks = <&l4_ck>; | ||
| 1155 | ti,bit-shift = <20>; | ||
| 1156 | reg = <0x0210>; | ||
| 1157 | }; | ||
| 1158 | |||
| 1159 | gpmc_fck: gpmc_fck { | ||
| 1160 | #clock-cells = <0>; | ||
| 1161 | compatible = "ti,fixed-factor-clock"; | ||
| 1162 | clocks = <&core_l3_ck>; | ||
| 1163 | ti,clock-div = <1>; | ||
| 1164 | ti,autoidle-shift = <1>; | ||
| 1165 | reg = <0x0238>; | ||
| 1166 | ti,clock-mult = <1>; | ||
| 1167 | }; | ||
| 1168 | |||
| 1169 | sdma_fck: sdma_fck { | ||
| 1170 | #clock-cells = <0>; | ||
| 1171 | compatible = "fixed-factor-clock"; | ||
| 1172 | clocks = <&core_l3_ck>; | ||
| 1173 | clock-mult = <1>; | ||
| 1174 | clock-div = <1>; | ||
| 1175 | }; | ||
| 1176 | |||
| 1177 | sdma_ick: sdma_ick { | ||
| 1178 | #clock-cells = <0>; | ||
| 1179 | compatible = "ti,fixed-factor-clock"; | ||
| 1180 | clocks = <&core_l3_ck>; | ||
| 1181 | ti,clock-div = <1>; | ||
| 1182 | ti,autoidle-shift = <0>; | ||
| 1183 | reg = <0x0238>; | ||
| 1184 | ti,clock-mult = <1>; | ||
| 1185 | }; | ||
| 1186 | |||
| 1187 | sdrc_ick: sdrc_ick { | ||
| 1188 | #clock-cells = <0>; | ||
| 1189 | compatible = "ti,fixed-factor-clock"; | ||
| 1190 | clocks = <&core_l3_ck>; | ||
| 1191 | ti,clock-div = <1>; | ||
| 1192 | ti,autoidle-shift = <2>; | ||
| 1193 | reg = <0x0238>; | ||
| 1194 | ti,clock-mult = <1>; | ||
| 1195 | }; | ||
| 1196 | |||
| 1197 | des_ick: des_ick { | ||
| 1198 | #clock-cells = <0>; | ||
| 1199 | compatible = "ti,omap3-interface-clock"; | ||
| 1200 | clocks = <&l4_ck>; | ||
| 1201 | ti,bit-shift = <0>; | ||
| 1202 | reg = <0x021c>; | ||
| 1203 | }; | ||
| 1204 | |||
| 1205 | sha_ick: sha_ick { | ||
| 1206 | #clock-cells = <0>; | ||
| 1207 | compatible = "ti,omap3-interface-clock"; | ||
| 1208 | clocks = <&l4_ck>; | ||
| 1209 | ti,bit-shift = <1>; | ||
| 1210 | reg = <0x021c>; | ||
| 1211 | }; | ||
| 1212 | |||
| 1213 | rng_ick: rng_ick { | ||
| 1214 | #clock-cells = <0>; | ||
| 1215 | compatible = "ti,omap3-interface-clock"; | ||
| 1216 | clocks = <&l4_ck>; | ||
| 1217 | ti,bit-shift = <2>; | ||
| 1218 | reg = <0x021c>; | ||
| 1219 | }; | ||
| 1220 | |||
| 1221 | aes_ick: aes_ick { | ||
| 1222 | #clock-cells = <0>; | ||
| 1223 | compatible = "ti,omap3-interface-clock"; | ||
| 1224 | clocks = <&l4_ck>; | ||
| 1225 | ti,bit-shift = <3>; | ||
| 1226 | reg = <0x021c>; | ||
| 1227 | }; | ||
| 1228 | |||
| 1229 | pka_ick: pka_ick { | ||
| 1230 | #clock-cells = <0>; | ||
| 1231 | compatible = "ti,omap3-interface-clock"; | ||
| 1232 | clocks = <&l4_ck>; | ||
| 1233 | ti,bit-shift = <4>; | ||
| 1234 | reg = <0x021c>; | ||
| 1235 | }; | ||
| 1236 | |||
| 1237 | usb_fck: usb_fck { | ||
| 1238 | #clock-cells = <0>; | ||
| 1239 | compatible = "ti,wait-gate-clock"; | ||
| 1240 | clocks = <&func_48m_ck>; | ||
| 1241 | ti,bit-shift = <0>; | ||
| 1242 | reg = <0x0204>; | ||
| 1243 | }; | ||
| 1244 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts index 4df68ad3736a..9cba94bed7ad 100644 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts | |||
| @@ -89,7 +89,16 @@ | |||
| 89 | status = "disabled"; | 89 | status = "disabled"; |
| 90 | }; | 90 | }; |
| 91 | 91 | ||
| 92 | &uart1 { | ||
| 93 | interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; | ||
| 94 | }; | ||
| 95 | |||
| 96 | &uart2 { | ||
| 97 | interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; | ||
| 98 | }; | ||
| 99 | |||
| 92 | &uart3 { | 100 | &uart3 { |
| 101 | interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; | ||
| 93 | pinctrl-names = "default"; | 102 | pinctrl-names = "default"; |
| 94 | pinctrl-0 = <&uart3_pins>; | 103 | pinctrl-0 = <&uart3_pins>; |
| 95 | }; | 104 | }; |
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts index 0abe986a4ecc..476ff158ddb3 100644 --- a/arch/arm/boot/dts/omap3-ldp.dts +++ b/arch/arm/boot/dts/omap3-ldp.dts | |||
| @@ -234,6 +234,10 @@ | |||
| 234 | }; | 234 | }; |
| 235 | }; | 235 | }; |
| 236 | 236 | ||
| 237 | &uart3 { | ||
| 238 | interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; | ||
| 239 | }; | ||
| 240 | |||
| 237 | &usb_otg_hs { | 241 | &usb_otg_hs { |
| 238 | pinctrl-names = "default"; | 242 | pinctrl-names = "default"; |
| 239 | pinctrl-0 = <&musb_pins>; | 243 | pinctrl-0 = <&musb_pins>; |
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi index cc1dce6978f5..d97308896f0c 100644 --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi | |||
| @@ -176,9 +176,6 @@ | |||
| 176 | 176 | ||
| 177 | &omap3_pmx_core2 { | 177 | &omap3_pmx_core2 { |
| 178 | pinctrl-names = "default"; | 178 | pinctrl-names = "default"; |
| 179 | pinctrl-0 = < | ||
| 180 | &hsusb1_2_pins | ||
| 181 | >; | ||
| 182 | 179 | ||
| 183 | hsusb1_2_pins: pinmux_hsusb1_2_pins { | 180 | hsusb1_2_pins: pinmux_hsusb1_2_pins { |
| 184 | pinctrl-single,pins = < | 181 | pinctrl-single,pins = < |
| @@ -357,6 +354,10 @@ | |||
| 357 | power = <50>; | 354 | power = <50>; |
| 358 | }; | 355 | }; |
| 359 | 356 | ||
| 357 | &mcbsp2 { | ||
| 358 | status = "okay"; | ||
| 359 | }; | ||
| 360 | |||
| 360 | &gpmc { | 361 | &gpmc { |
| 361 | ranges = <0 0 0x30000000 0x1000000>, | 362 | ranges = <0 0 0x30000000 0x1000000>, |
| 362 | <7 0 0x15000000 0x01000000>; | 363 | <7 0 0x15000000 0x01000000>; |
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 1a57b61f5e24..059a8ff1e6ac 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts | |||
| @@ -10,6 +10,7 @@ | |||
| 10 | /dts-v1/; | 10 | /dts-v1/; |
| 11 | 11 | ||
| 12 | #include "omap34xx-hs.dtsi" | 12 | #include "omap34xx-hs.dtsi" |
| 13 | #include <dt-bindings/input/input.h> | ||
| 13 | 14 | ||
| 14 | / { | 15 | / { |
| 15 | model = "Nokia N900"; | 16 | model = "Nokia N900"; |
| @@ -21,6 +22,17 @@ | |||
| 21 | }; | 22 | }; |
| 22 | }; | 23 | }; |
| 23 | 24 | ||
| 25 | leds { | ||
| 26 | compatible = "gpio-leds"; | ||
| 27 | heartbeat { | ||
| 28 | label = "debug::sleep"; | ||
| 29 | gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio162 */ | ||
| 30 | linux,default-trigger = "default-on"; | ||
| 31 | pinctrl-names = "default"; | ||
| 32 | pinctrl-0 = <&debug_leds>; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | |||
| 24 | memory { | 36 | memory { |
| 25 | device_type = "memory"; | 37 | device_type = "memory"; |
| 26 | reg = <0x80000000 0x10000000>; /* 256 MB */ | 38 | reg = <0x80000000 0x10000000>; /* 256 MB */ |
| @@ -90,6 +102,19 @@ | |||
| 90 | }; | 102 | }; |
| 91 | }; | 103 | }; |
| 92 | }; | 104 | }; |
| 105 | |||
| 106 | sound: n900-audio { | ||
| 107 | compatible = "nokia,n900-audio"; | ||
| 108 | |||
| 109 | nokia,cpu-dai = <&mcbsp2>; | ||
| 110 | nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>; | ||
| 111 | nokia,headphone-amplifier = <&tpa6130a2>; | ||
| 112 | |||
| 113 | tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */ | ||
| 114 | jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */ | ||
| 115 | eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */ | ||
| 116 | speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; | ||
| 117 | }; | ||
| 93 | }; | 118 | }; |
| 94 | 119 | ||
| 95 | &omap3_pmx_core { | 120 | &omap3_pmx_core { |
| @@ -130,6 +155,21 @@ | |||
| 130 | >; | 155 | >; |
| 131 | }; | 156 | }; |
| 132 | 157 | ||
| 158 | debug_leds: pinmux_debug_led_pins { | ||
| 159 | pinctrl-single,pins = < | ||
| 160 | OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */ | ||
| 161 | >; | ||
| 162 | }; | ||
| 163 | |||
| 164 | mcspi4_pins: pinmux_mcspi4_pins { | ||
| 165 | pinctrl-single,pins = < | ||
| 166 | 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ | ||
| 167 | 0x162 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ | ||
| 168 | 0x160 (PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ | ||
| 169 | 0x166 (PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ | ||
| 170 | >; | ||
| 171 | }; | ||
| 172 | |||
| 133 | mmc1_pins: pinmux_mmc1_pins { | 173 | mmc1_pins: pinmux_mmc1_pins { |
| 134 | pinctrl-single,pins = < | 174 | pinctrl-single,pins = < |
| 135 | 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ | 175 | 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ |
| @@ -173,6 +213,37 @@ | |||
| 173 | 0x0da (PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */ | 213 | 0x0da (PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */ |
| 174 | >; | 214 | >; |
| 175 | }; | 215 | }; |
| 216 | |||
| 217 | wl1251_pins: pinmux_wl1251 { | ||
| 218 | pinctrl-single,pins = < | ||
| 219 | 0x0ce (PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */ | ||
| 220 | 0x05a (PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */ | ||
| 221 | >; | ||
| 222 | }; | ||
| 223 | |||
| 224 | ssi_pins: pinmux_ssi { | ||
| 225 | pinctrl-single,pins = < | ||
| 226 | 0x150 (PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ | ||
| 227 | 0x14e (PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ | ||
| 228 | 0x152 (PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */ | ||
| 229 | 0x14c (PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ | ||
| 230 | 0x154 (PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ | ||
| 231 | 0x156 (PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ | ||
| 232 | 0x158 (PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ | ||
| 233 | 0x15a (PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ | ||
| 234 | >; | ||
| 235 | }; | ||
| 236 | |||
| 237 | modem_pins: pinmux_modem { | ||
| 238 | pinctrl-single,pins = < | ||
| 239 | 0x0ac (PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */ | ||
| 240 | 0x0b0 (PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio 72 => ape_rst_rq */ | ||
| 241 | 0x0b2 (PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */ | ||
| 242 | 0x0b4 (PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */ | ||
| 243 | 0x0b6 (PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */ | ||
| 244 | 0x15e (PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */ | ||
| 245 | >; | ||
| 246 | }; | ||
| 176 | }; | 247 | }; |
| 177 | 248 | ||
| 178 | &i2c1 { | 249 | &i2c1 { |
| @@ -283,57 +354,57 @@ | |||
| 283 | }; | 354 | }; |
| 284 | 355 | ||
| 285 | &twl_keypad { | 356 | &twl_keypad { |
| 286 | linux,keymap = < 0x00000010 /* KEY_Q */ | 357 | linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q) |
| 287 | 0x00010018 /* KEY_O */ | 358 | MATRIX_KEY(0x00, 0x01, KEY_O) |
| 288 | 0x00020019 /* KEY_P */ | 359 | MATRIX_KEY(0x00, 0x02, KEY_P) |
| 289 | 0x00030033 /* KEY_COMMA */ | 360 | MATRIX_KEY(0x00, 0x03, KEY_COMMA) |
| 290 | 0x0004000e /* KEY_BACKSPACE */ | 361 | MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE) |
| 291 | 0x0006001e /* KEY_A */ | 362 | MATRIX_KEY(0x00, 0x06, KEY_A) |
| 292 | 0x0007001f /* KEY_S */ | 363 | MATRIX_KEY(0x00, 0x07, KEY_S) |
| 293 | 364 | ||
| 294 | 0x01000011 /* KEY_W */ | 365 | MATRIX_KEY(0x01, 0x00, KEY_W) |
| 295 | 0x01010020 /* KEY_D */ | 366 | MATRIX_KEY(0x01, 0x01, KEY_D) |
| 296 | 0x01020021 /* KEY_F */ | 367 | MATRIX_KEY(0x01, 0x02, KEY_F) |
| 297 | 0x01030022 /* KEY_G */ | 368 | MATRIX_KEY(0x01, 0x03, KEY_G) |
| 298 | 0x01040023 /* KEY_H */ | 369 | MATRIX_KEY(0x01, 0x04, KEY_H) |
| 299 | 0x01050024 /* KEY_J */ | 370 | MATRIX_KEY(0x01, 0x05, KEY_J) |
| 300 | 0x01060025 /* KEY_K */ | 371 | MATRIX_KEY(0x01, 0x06, KEY_K) |
| 301 | 0x01070026 /* KEY_L */ | 372 | MATRIX_KEY(0x01, 0x07, KEY_L) |
| 302 | 373 | ||
| 303 | 0x02000012 /* KEY_E */ | 374 | MATRIX_KEY(0x02, 0x00, KEY_E) |
| 304 | 0x02010034 /* KEY_DOT */ | 375 | MATRIX_KEY(0x02, 0x01, KEY_DOT) |
| 305 | 0x02020067 /* KEY_UP */ | 376 | MATRIX_KEY(0x02, 0x02, KEY_UP) |
| 306 | 0x0203001c /* KEY_ENTER */ | 377 | MATRIX_KEY(0x02, 0x03, KEY_ENTER) |
| 307 | 0x0205002c /* KEY_Z */ | 378 | MATRIX_KEY(0x02, 0x05, KEY_Z) |
| 308 | 0x0206002d /* KEY_X */ | 379 | MATRIX_KEY(0x02, 0x06, KEY_X) |
| 309 | 0x0207002e /* KEY_C */ | 380 | MATRIX_KEY(0x02, 0x07, KEY_C) |
| 310 | 0x02080043 /* KEY_F9 */ | 381 | MATRIX_KEY(0x02, 0x08, KEY_F9) |
| 311 | 382 | ||
| 312 | 0x03000013 /* KEY_R */ | 383 | MATRIX_KEY(0x03, 0x00, KEY_R) |
| 313 | 0x0301002f /* KEY_V */ | 384 | MATRIX_KEY(0x03, 0x01, KEY_V) |
| 314 | 0x03020030 /* KEY_B */ | 385 | MATRIX_KEY(0x03, 0x02, KEY_B) |
| 315 | 0x03030031 /* KEY_N */ | 386 | MATRIX_KEY(0x03, 0x03, KEY_N) |
| 316 | 0x03040032 /* KEY_M */ | 387 | MATRIX_KEY(0x03, 0x04, KEY_M) |
| 317 | 0x03050039 /* KEY_SPACE */ | 388 | MATRIX_KEY(0x03, 0x05, KEY_SPACE) |
| 318 | 0x03060039 /* KEY_SPACE */ | 389 | MATRIX_KEY(0x03, 0x06, KEY_SPACE) |
| 319 | 0x03070069 /* KEY_LEFT */ | 390 | MATRIX_KEY(0x03, 0x07, KEY_LEFT) |
| 320 | 391 | ||
| 321 | 0x04000014 /* KEY_T */ | 392 | MATRIX_KEY(0x04, 0x00, KEY_T) |
| 322 | 0x0401006c /* KEY_DOWN */ | 393 | MATRIX_KEY(0x04, 0x01, KEY_DOWN) |
| 323 | 0x0402006a /* KEY_RIGHT */ | 394 | MATRIX_KEY(0x04, 0x02, KEY_RIGHT) |
| 324 | 0x0404001d /* KEY_LEFTCTRL */ | 395 | MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL) |
| 325 | 0x04050064 /* KEY_RIGHTALT */ | 396 | MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT) |
| 326 | 0x0406002a /* KEY_LEFTSHIFT */ | 397 | MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT) |
| 327 | 0x04080044 /* KEY_F10 */ | 398 | MATRIX_KEY(0x04, 0x08, KEY_F10) |
| 328 | 399 | ||
| 329 | 0x05000015 /* KEY_Y */ | 400 | MATRIX_KEY(0x05, 0x00, KEY_Y) |
| 330 | 0x05080057 /* KEY_F11 */ | 401 | MATRIX_KEY(0x05, 0x08, KEY_F11) |
| 331 | 402 | ||
| 332 | 0x06000016 /* KEY_U */ | 403 | MATRIX_KEY(0x06, 0x00, KEY_U) |
| 333 | 404 | ||
| 334 | 0x07000017 /* KEY_I */ | 405 | MATRIX_KEY(0x07, 0x00, KEY_I) |
| 335 | 0x07010041 /* KEY_F7 */ | 406 | MATRIX_KEY(0x07, 0x01, KEY_F7) |
| 336 | 0x07020042 /* KEY_F8 */ | 407 | MATRIX_KEY(0x07, 0x02, KEY_F8) |
| 337 | >; | 408 | >; |
| 338 | }; | 409 | }; |
| 339 | 410 | ||
| @@ -604,6 +675,30 @@ | |||
| 604 | }; | 675 | }; |
| 605 | }; | 676 | }; |
| 606 | 677 | ||
| 678 | &mcspi4 { | ||
| 679 | pinctrl-names = "default"; | ||
| 680 | pinctrl-0 = <&mcspi4_pins>; | ||
| 681 | |||
| 682 | wl1251@0 { | ||
| 683 | pinctrl-names = "default"; | ||
| 684 | pinctrl-0 = <&wl1251_pins>; | ||
| 685 | |||
| 686 | vio-supply = <&vio>; | ||
| 687 | |||
| 688 | compatible = "ti,wl1251"; | ||
| 689 | reg = <0>; | ||
| 690 | spi-max-frequency = <48000000>; | ||
| 691 | |||
| 692 | spi-cpol; | ||
| 693 | spi-cpha; | ||
| 694 | |||
| 695 | ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ | ||
| 696 | |||
| 697 | interrupt-parent = <&gpio2>; | ||
| 698 | interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */ | ||
| 699 | }; | ||
| 700 | }; | ||
| 701 | |||
| 607 | &usb_otg_hs { | 702 | &usb_otg_hs { |
| 608 | interface-type = <0>; | 703 | interface-type = <0>; |
| 609 | usb-phy = <&usb2_phy>; | 704 | usb-phy = <&usb2_phy>; |
| @@ -618,11 +713,13 @@ | |||
| 618 | }; | 713 | }; |
| 619 | 714 | ||
| 620 | &uart2 { | 715 | &uart2 { |
| 716 | interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; | ||
| 621 | pinctrl-names = "default"; | 717 | pinctrl-names = "default"; |
| 622 | pinctrl-0 = <&uart2_pins>; | 718 | pinctrl-0 = <&uart2_pins>; |
| 623 | }; | 719 | }; |
| 624 | 720 | ||
| 625 | &uart3 { | 721 | &uart3 { |
| 722 | interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; | ||
| 626 | pinctrl-names = "default"; | 723 | pinctrl-names = "default"; |
| 627 | pinctrl-0 = <&uart3_pins>; | 724 | pinctrl-0 = <&uart3_pins>; |
| 628 | }; | 725 | }; |
| @@ -662,3 +759,48 @@ | |||
| 662 | }; | 759 | }; |
| 663 | }; | 760 | }; |
| 664 | }; | 761 | }; |
| 762 | |||
| 763 | &mcbsp2 { | ||
| 764 | status = "ok"; | ||
| 765 | }; | ||
| 766 | |||
| 767 | &ssi_port1 { | ||
| 768 | pinctrl-names = "default"; | ||
| 769 | pinctrl-0 = <&ssi_pins>; | ||
| 770 | |||
| 771 | ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ | ||
| 772 | |||
| 773 | modem: hsi-client { | ||
| 774 | compatible = "nokia,n900-modem"; | ||
| 775 | |||
| 776 | pinctrl-names = "default"; | ||
| 777 | pinctrl-0 = <&modem_pins>; | ||
| 778 | |||
| 779 | hsi-channel-ids = <0>, <1>, <2>, <3>; | ||
| 780 | hsi-channel-names = "mcsaab-control", | ||
| 781 | "speech-control", | ||
| 782 | "speech-data", | ||
| 783 | "mcsaab-data"; | ||
| 784 | hsi-speed-kbps = <55000>; | ||
| 785 | hsi-mode = "frame"; | ||
| 786 | hsi-flow = "synchronized"; | ||
| 787 | hsi-arb-mode = "round-robin"; | ||
| 788 | |||
| 789 | interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */ | ||
| 790 | |||
| 791 | gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */ | ||
| 792 | <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */ | ||
| 793 | <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */ | ||
| 794 | <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */ | ||
| 795 | <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */ | ||
| 796 | gpio-names = "cmt_apeslpx", | ||
| 797 | "cmt_rst_rq", | ||
| 798 | "cmt_en", | ||
| 799 | "cmt_rst", | ||
| 800 | "cmt_bsi"; | ||
| 801 | }; | ||
| 802 | }; | ||
| 803 | |||
| 804 | &ssi_port2 { | ||
| 805 | status = "disabled"; | ||
| 806 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index 5c26c184f2c1..70addcba37c5 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi | |||
| @@ -67,6 +67,20 @@ | |||
| 67 | ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ | 67 | ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ |
| 68 | }; | 68 | }; |
| 69 | 69 | ||
| 70 | /* CSI-2 receiver */ | ||
| 71 | &vaux2 { | ||
| 72 | regulator-name = "vaux2"; | ||
| 73 | regulator-min-microvolt = <1800000>; | ||
| 74 | regulator-max-microvolt = <1800000>; | ||
| 75 | }; | ||
| 76 | |||
| 77 | /* Cameras */ | ||
| 78 | &vaux3 { | ||
| 79 | regulator-name = "vaux3"; | ||
| 80 | regulator-min-microvolt = <2800000>; | ||
| 81 | regulator-max-microvolt = <2800000>; | ||
| 82 | }; | ||
| 83 | |||
| 70 | &i2c2 { | 84 | &i2c2 { |
| 71 | clock-frequency = <400000>; | 85 | clock-frequency = <400000>; |
| 72 | }; | 86 | }; |
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 4231191ade06..b2891a9a6975 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi | |||
| @@ -267,7 +267,7 @@ | |||
| 267 | uart1: serial@4806a000 { | 267 | uart1: serial@4806a000 { |
| 268 | compatible = "ti,omap3-uart"; | 268 | compatible = "ti,omap3-uart"; |
| 269 | reg = <0x4806a000 0x2000>; | 269 | reg = <0x4806a000 0x2000>; |
| 270 | interrupts = <72>; | 270 | interrupts-extended = <&intc 72>; |
| 271 | dmas = <&sdma 49 &sdma 50>; | 271 | dmas = <&sdma 49 &sdma 50>; |
| 272 | dma-names = "tx", "rx"; | 272 | dma-names = "tx", "rx"; |
| 273 | ti,hwmods = "uart1"; | 273 | ti,hwmods = "uart1"; |
| @@ -277,7 +277,7 @@ | |||
| 277 | uart2: serial@4806c000 { | 277 | uart2: serial@4806c000 { |
| 278 | compatible = "ti,omap3-uart"; | 278 | compatible = "ti,omap3-uart"; |
| 279 | reg = <0x4806c000 0x400>; | 279 | reg = <0x4806c000 0x400>; |
| 280 | interrupts = <73>; | 280 | interrupts-extended = <&intc 73>; |
| 281 | dmas = <&sdma 51 &sdma 52>; | 281 | dmas = <&sdma 51 &sdma 52>; |
| 282 | dma-names = "tx", "rx"; | 282 | dma-names = "tx", "rx"; |
| 283 | ti,hwmods = "uart2"; | 283 | ti,hwmods = "uart2"; |
| @@ -287,7 +287,7 @@ | |||
| 287 | uart3: serial@49020000 { | 287 | uart3: serial@49020000 { |
| 288 | compatible = "ti,omap3-uart"; | 288 | compatible = "ti,omap3-uart"; |
| 289 | reg = <0x49020000 0x400>; | 289 | reg = <0x49020000 0x400>; |
| 290 | interrupts = <74>; | 290 | interrupts-extended = <&intc 74>; |
| 291 | dmas = <&sdma 53 &sdma 54>; | 291 | dmas = <&sdma 53 &sdma 54>; |
| 292 | dma-names = "tx", "rx"; | 292 | dma-names = "tx", "rx"; |
| 293 | ti,hwmods = "uart3"; | 293 | ti,hwmods = "uart3"; |
| @@ -757,6 +757,51 @@ | |||
| 757 | clock-names = "fck"; | 757 | clock-names = "fck"; |
| 758 | }; | 758 | }; |
| 759 | }; | 759 | }; |
| 760 | |||
| 761 | ssi: ssi-controller@48058000 { | ||
| 762 | compatible = "ti,omap3-ssi"; | ||
| 763 | ti,hwmods = "ssi"; | ||
| 764 | |||
| 765 | status = "disabled"; | ||
| 766 | |||
| 767 | reg = <0x48058000 0x1000>, | ||
| 768 | <0x48059000 0x1000>; | ||
| 769 | reg-names = "sys", | ||
| 770 | "gdd"; | ||
| 771 | |||
| 772 | interrupts = <71>; | ||
| 773 | interrupt-names = "gdd_mpu"; | ||
| 774 | |||
| 775 | #address-cells = <1>; | ||
| 776 | #size-cells = <1>; | ||
| 777 | ranges; | ||
| 778 | |||
| 779 | ssi_port1: ssi-port@4805a000 { | ||
| 780 | compatible = "ti,omap3-ssi-port"; | ||
| 781 | |||
| 782 | reg = <0x4805a000 0x800>, | ||
| 783 | <0x4805a800 0x800>; | ||
| 784 | reg-names = "tx", | ||
| 785 | "rx"; | ||
| 786 | |||
| 787 | interrupt-parent = <&intc>; | ||
| 788 | interrupts = <67>, | ||
| 789 | <68>; | ||
| 790 | }; | ||
| 791 | |||
| 792 | ssi_port2: ssi-port@4805b000 { | ||
| 793 | compatible = "ti,omap3-ssi-port"; | ||
| 794 | |||
| 795 | reg = <0x4805b000 0x800>, | ||
| 796 | <0x4805b800 0x800>; | ||
| 797 | reg-names = "tx", | ||
| 798 | "rx"; | ||
| 799 | |||
| 800 | interrupt-parent = <&intc>; | ||
| 801 | interrupts = <69>, | ||
| 802 | <70>; | ||
| 803 | }; | ||
| 804 | }; | ||
| 760 | }; | 805 | }; |
| 761 | }; | 806 | }; |
| 762 | 807 | ||
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index 2e92360da1f3..3819c1e91591 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi | |||
| @@ -40,6 +40,17 @@ | |||
| 40 | }; | 40 | }; |
| 41 | }; | 41 | }; |
| 42 | 42 | ||
| 43 | &ssi { | ||
| 44 | status = "ok"; | ||
| 45 | |||
| 46 | clocks = <&ssi_ssr_fck>, | ||
| 47 | <&ssi_sst_fck>, | ||
| 48 | <&ssi_ick>; | ||
| 49 | clock-names = "ssi_ssr_fck", | ||
| 50 | "ssi_sst_fck", | ||
| 51 | "ssi_ick"; | ||
| 52 | }; | ||
| 53 | |||
| 43 | /include/ "omap34xx-omap36xx-clocks.dtsi" | 54 | /include/ "omap34xx-omap36xx-clocks.dtsi" |
| 44 | /include/ "omap36xx-omap3430es2plus-clocks.dtsi" | 55 | /include/ "omap36xx-omap3430es2plus-clocks.dtsi" |
| 45 | /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" | 56 | /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" |
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi index 6b5280d04a0e..200ae3a5cbbb 100644 --- a/arch/arm/boot/dts/omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi | |||
| @@ -83,7 +83,7 @@ | |||
| 83 | }; | 83 | }; |
| 84 | 84 | ||
| 85 | &dpll4_m5x2_mul_ck { | 85 | &dpll4_m5x2_mul_ck { |
| 86 | clock-mult = <1>; | 86 | ti,clock-mult = <1>; |
| 87 | }; | 87 | }; |
| 88 | 88 | ||
| 89 | &dpll4_m6x2_mul_ck { | 89 | &dpll4_m6x2_mul_ck { |
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 22cf4647087e..541704a59a5a 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi | |||
| @@ -78,6 +78,17 @@ | |||
| 78 | clock-names = "fck", "tv_dac_clk"; | 78 | clock-names = "fck", "tv_dac_clk"; |
| 79 | }; | 79 | }; |
| 80 | 80 | ||
| 81 | &ssi { | ||
| 82 | status = "ok"; | ||
| 83 | |||
| 84 | clocks = <&ssi_ssr_fck>, | ||
| 85 | <&ssi_sst_fck>, | ||
| 86 | <&ssi_ick>; | ||
| 87 | clock-names = "ssi_ssr_fck", | ||
| 88 | "ssi_sst_fck", | ||
| 89 | "ssi_ick"; | ||
| 90 | }; | ||
| 91 | |||
| 81 | /include/ "omap34xx-omap36xx-clocks.dtsi" | 92 | /include/ "omap34xx-omap36xx-clocks.dtsi" |
| 82 | /include/ "omap36xx-omap3430es2plus-clocks.dtsi" | 93 | /include/ "omap36xx-omap3430es2plus-clocks.dtsi" |
| 83 | /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" | 94 | /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" |
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 12be2b35dae9..e47ff69dcf70 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi | |||
| @@ -453,10 +453,11 @@ | |||
| 453 | 453 | ||
| 454 | dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { | 454 | dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { |
| 455 | #clock-cells = <0>; | 455 | #clock-cells = <0>; |
| 456 | compatible = "fixed-factor-clock"; | 456 | compatible = "ti,fixed-factor-clock"; |
| 457 | clocks = <&dpll4_m5_ck>; | 457 | clocks = <&dpll4_m5_ck>; |
| 458 | clock-mult = <2>; | 458 | ti,clock-mult = <2>; |
| 459 | clock-div = <1>; | 459 | ti,clock-div = <1>; |
| 460 | ti,set-rate-parent; | ||
| 460 | }; | 461 | }; |
| 461 | 462 | ||
| 462 | dpll4_m5x2_ck: dpll4_m5x2_ck { | 463 | dpll4_m5x2_ck: dpll4_m5x2_ck { |
diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts index 96f51d870812..cd53a64d8f2e 100644 --- a/arch/arm/boot/dts/omap4-duovero-parlor.dts +++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts | |||
| @@ -46,35 +46,35 @@ | |||
| 46 | 46 | ||
| 47 | led_pins: pinmux_led_pins { | 47 | led_pins: pinmux_led_pins { |
| 48 | pinctrl-single,pins = < | 48 | pinctrl-single,pins = < |
| 49 | 0xd6 (PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ | 49 | OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ |
| 50 | >; | 50 | >; |
| 51 | }; | 51 | }; |
| 52 | 52 | ||
| 53 | button_pins: pinmux_button_pins { | 53 | button_pins: pinmux_button_pins { |
| 54 | pinctrl-single,pins = < | 54 | pinctrl-single,pins = < |
| 55 | 0xd4 (PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */ | 55 | OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */ |
| 56 | >; | 56 | >; |
| 57 | }; | 57 | }; |
| 58 | 58 | ||
| 59 | i2c2_pins: pinmux_i2c2_pins { | 59 | i2c2_pins: pinmux_i2c2_pins { |
| 60 | pinctrl-single,pins = < | 60 | pinctrl-single,pins = < |
| 61 | 0xe6 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ | 61 | OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ |
| 62 | 0xe8 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ | 62 | OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ |
| 63 | >; | 63 | >; |
| 64 | }; | 64 | }; |
| 65 | 65 | ||
| 66 | i2c3_pins: pinmux_i2c3_pins { | 66 | i2c3_pins: pinmux_i2c3_pins { |
| 67 | pinctrl-single,pins = < | 67 | pinctrl-single,pins = < |
| 68 | 0xea (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ | 68 | OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ |
| 69 | 0xec (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ | 69 | OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ |
| 70 | >; | 70 | >; |
| 71 | }; | 71 | }; |
| 72 | 72 | ||
| 73 | smsc_pins: pinmux_smsc_pins { | 73 | smsc_pins: pinmux_smsc_pins { |
| 74 | pinctrl-single,pins = < | 74 | pinctrl-single,pins = < |
| 75 | 0x28 (PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */ | 75 | OMAP4_IOPAD(0x068, PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */ |
| 76 | 0x2a (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */ | 76 | OMAP4_IOPAD(0x06a, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */ |
| 77 | 0x30 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48: amdix enabled */ | 77 | OMAP4_IOPAD(0x070, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48: amdix enabled */ |
| 78 | >; | 78 | >; |
| 79 | }; | 79 | }; |
| 80 | }; | 80 | }; |
diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi index a514791154eb..e860ccd9d09c 100644 --- a/arch/arm/boot/dts/omap4-duovero.dtsi +++ b/arch/arm/boot/dts/omap4-duovero.dtsi | |||
| @@ -67,100 +67,98 @@ | |||
| 67 | pinctrl-names = "default"; | 67 | pinctrl-names = "default"; |
| 68 | pinctrl-0 = < | 68 | pinctrl-0 = < |
| 69 | &twl6040_pins | 69 | &twl6040_pins |
| 70 | &mcpdm_pins | ||
| 71 | &mcbsp1_pins | ||
| 72 | &hsusbb1_pins | 70 | &hsusbb1_pins |
| 73 | >; | 71 | >; |
| 74 | 72 | ||
| 75 | twl6040_pins: pinmux_twl6040_pins { | 73 | twl6040_pins: pinmux_twl6040_pins { |
| 76 | pinctrl-single,pins = < | 74 | pinctrl-single,pins = < |
| 77 | 0x126 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_nxt.gpio_160 */ | 75 | OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_nxt.gpio_160 */ |
| 78 | 0x160 (PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ | 76 | OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ |
| 79 | >; | 77 | >; |
| 80 | }; | 78 | }; |
| 81 | 79 | ||
| 82 | mcpdm_pins: pinmux_mcpdm_pins { | 80 | mcpdm_pins: pinmux_mcpdm_pins { |
| 83 | pinctrl-single,pins = < | 81 | pinctrl-single,pins = < |
| 84 | 0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ | 82 | OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ |
| 85 | 0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ | 83 | OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ |
| 86 | 0xca (PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ | 84 | OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ |
| 87 | 0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ | 85 | OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ |
| 88 | 0xce (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ | 86 | OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ |
| 89 | >; | 87 | >; |
| 90 | }; | 88 | }; |
| 91 | 89 | ||
| 92 | mcbsp1_pins: pinmux_mcbsp1_pins { | 90 | mcbsp1_pins: pinmux_mcbsp1_pins { |
| 93 | pinctrl-single,pins = < | 91 | pinctrl-single,pins = < |
| 94 | 0xbe (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ | 92 | OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ |
| 95 | 0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ | 93 | OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ |
| 96 | 0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ | 94 | OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ |
| 97 | 0xc4 (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ | 95 | OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ |
| 98 | >; | 96 | >; |
| 99 | }; | 97 | }; |
| 100 | 98 | ||
| 101 | hsusbb1_pins: pinmux_hsusbb1_pins { | 99 | hsusbb1_pins: pinmux_hsusbb1_pins { |
| 102 | pinctrl-single,pins = < | 100 | pinctrl-single,pins = < |
| 103 | 0x82 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ | 101 | OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ |
| 104 | 0x84 (PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ | 102 | OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ |
| 105 | 0x86 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ | 103 | OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ |
| 106 | 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ | 104 | OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ |
| 107 | 0x8a (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ | 105 | OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ |
| 108 | 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ | 106 | OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ |
| 109 | 0x8e (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ | 107 | OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ |
| 110 | 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ | 108 | OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ |
| 111 | 0x92 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ | 109 | OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ |
| 112 | 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ | 110 | OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ |
| 113 | 0x96 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ | 111 | OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ |
| 114 | 0x98 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ | 112 | OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ |
| 115 | >; | 113 | >; |
| 116 | }; | 114 | }; |
| 117 | 115 | ||
| 118 | hsusb1phy_pins: pinmux_hsusb1phy_pins { | 116 | hsusb1phy_pins: pinmux_hsusb1phy_pins { |
| 119 | pinctrl-single,pins = < | 117 | pinctrl-single,pins = < |
| 120 | 0x4c (PIN_OUTPUT | MUX_MODE3) /* gpmc_wait1.gpio_62 */ | 118 | OMAP4_IOPAD(0x08c, PIN_OUTPUT | MUX_MODE3) /* gpmc_wait1.gpio_62 */ |
| 121 | >; | 119 | >; |
| 122 | }; | 120 | }; |
| 123 | 121 | ||
| 124 | w2cbw0015_pins: pinmux_w2cbw0015_pins { | 122 | w2cbw0015_pins: pinmux_w2cbw0015_pins { |
| 125 | pinctrl-single,pins = < | 123 | pinctrl-single,pins = < |
| 126 | 0x26 (PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ | 124 | OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ |
| 127 | 0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ | 125 | OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ |
| 128 | >; | 126 | >; |
| 129 | }; | 127 | }; |
| 130 | 128 | ||
| 131 | i2c1_pins: pinmux_i2c1_pins { | 129 | i2c1_pins: pinmux_i2c1_pins { |
| 132 | pinctrl-single,pins = < | 130 | pinctrl-single,pins = < |
| 133 | 0xe2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ | 131 | OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ |
| 134 | 0xe4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ | 132 | OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ |
| 135 | >; | 133 | >; |
| 136 | }; | 134 | }; |
| 137 | 135 | ||
| 138 | i2c4_pins: pinmux_i2c4_pins { | 136 | i2c4_pins: pinmux_i2c4_pins { |
| 139 | pinctrl-single,pins = < | 137 | pinctrl-single,pins = < |
| 140 | 0xee (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ | 138 | OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ |
| 141 | 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ | 139 | OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ |
| 142 | >; | 140 | >; |
| 143 | }; | 141 | }; |
| 144 | 142 | ||
| 145 | mmc1_pins: pinmux_mmc1_pins { | 143 | mmc1_pins: pinmux_mmc1_pins { |
| 146 | pinctrl-single,pins = < | 144 | pinctrl-single,pins = < |
| 147 | 0xa2 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ | 145 | OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ |
| 148 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_cmd */ | 146 | OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_cmd */ |
| 149 | 0xa6 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_dat0 */ | 147 | OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_dat0 */ |
| 150 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ | 148 | OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ |
| 151 | 0xaa (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ | 149 | OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ |
| 152 | 0xac (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ | 150 | OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ |
| 153 | >; | 151 | >; |
| 154 | }; | 152 | }; |
| 155 | 153 | ||
| 156 | mmc5_pins: pinmux_mmc5_pins { | 154 | mmc5_pins: pinmux_mmc5_pins { |
| 157 | pinctrl-single,pins = < | 155 | pinctrl-single,pins = < |
| 158 | 0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk */ | 156 | OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk */ |
| 159 | 0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_cmd */ | 157 | OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_cmd */ |
| 160 | 0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_dat0 */ | 158 | OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_dat0 */ |
| 161 | 0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1 */ | 159 | OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1 */ |
| 162 | 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2 */ | 160 | OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2 */ |
| 163 | 0x112 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3 */ | 161 | OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3 */ |
| 164 | >; | 162 | >; |
| 165 | }; | 163 | }; |
| 166 | }; | 164 | }; |
| @@ -202,6 +200,18 @@ | |||
| 202 | clock-frequency = <400000>; | 200 | clock-frequency = <400000>; |
| 203 | }; | 201 | }; |
| 204 | 202 | ||
| 203 | &mcbsp1 { | ||
| 204 | pinctrl-names = "default"; | ||
| 205 | pinctrl-0 = <&mcbsp1_pins>; | ||
| 206 | status = "okay"; | ||
| 207 | }; | ||
| 208 | |||
| 209 | &mcpdm { | ||
| 210 | pinctrl-names = "default"; | ||
| 211 | pinctrl-0 = <&mcpdm_pins>; | ||
| 212 | status = "okay"; | ||
| 213 | }; | ||
| 214 | |||
| 205 | &mmc1 { | 215 | &mmc1 { |
| 206 | pinctrl-names = "default"; | 216 | pinctrl-names = "default"; |
| 207 | pinctrl-0 = <&mmc1_pins>; | 217 | pinctrl-0 = <&mmc1_pins>; |
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index d2c45bfaaa2c..8cfa3c8a72b0 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi | |||
| @@ -481,6 +481,21 @@ | |||
| 481 | usb-supply = <&vusb>; | 481 | usb-supply = <&vusb>; |
| 482 | }; | 482 | }; |
| 483 | 483 | ||
| 484 | &uart2 { | ||
| 485 | interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH | ||
| 486 | &omap4_pmx_core OMAP4_UART2_RX>; | ||
| 487 | }; | ||
| 488 | |||
| 489 | &uart3 { | ||
| 490 | interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH | ||
| 491 | &omap4_pmx_core OMAP4_UART3_RX>; | ||
| 492 | }; | ||
| 493 | |||
| 494 | &uart4 { | ||
| 495 | interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH | ||
| 496 | &omap4_pmx_core OMAP4_UART4_RX>; | ||
| 497 | }; | ||
| 498 | |||
| 484 | &usb_otg_hs { | 499 | &usb_otg_hs { |
| 485 | interface-type = <1>; | 500 | interface-type = <1>; |
| 486 | mode = <3>; | 501 | mode = <3>; |
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 48983c8d56c2..3e1da43068f6 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts | |||
| @@ -570,16 +570,22 @@ | |||
| 570 | }; | 570 | }; |
| 571 | 571 | ||
| 572 | &uart2 { | 572 | &uart2 { |
| 573 | interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH | ||
| 574 | &omap4_pmx_core OMAP4_UART2_RX>; | ||
| 573 | pinctrl-names = "default"; | 575 | pinctrl-names = "default"; |
| 574 | pinctrl-0 = <&uart2_pins>; | 576 | pinctrl-0 = <&uart2_pins>; |
| 575 | }; | 577 | }; |
| 576 | 578 | ||
| 577 | &uart3 { | 579 | &uart3 { |
| 580 | interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH | ||
| 581 | &omap4_pmx_core OMAP4_UART3_RX>; | ||
| 578 | pinctrl-names = "default"; | 582 | pinctrl-names = "default"; |
| 579 | pinctrl-0 = <&uart3_pins>; | 583 | pinctrl-0 = <&uart3_pins>; |
| 580 | }; | 584 | }; |
| 581 | 585 | ||
| 582 | &uart4 { | 586 | &uart4 { |
| 587 | interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH | ||
| 588 | &omap4_pmx_core OMAP4_UART4_RX>; | ||
| 583 | pinctrl-names = "default"; | 589 | pinctrl-names = "default"; |
| 584 | pinctrl-0 = <&uart4_pins>; | 590 | pinctrl-0 = <&uart4_pins>; |
| 585 | }; | 591 | }; |
diff --git a/arch/arm/boot/dts/omap4-var-dvk-om44.dts b/arch/arm/boot/dts/omap4-var-dvk-om44.dts new file mode 100644 index 000000000000..458d79fa378b --- /dev/null +++ b/arch/arm/boot/dts/omap4-var-dvk-om44.dts | |||
| @@ -0,0 +1,71 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | /dts-v1/; | ||
| 9 | |||
| 10 | #include "omap4-var-som-om44.dtsi" | ||
| 11 | #include "omap4-var-som-om44-wlan.dtsi" | ||
| 12 | #include "omap4-var-om44customboard.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "Variscite VAR-DVK-OM44"; | ||
| 16 | compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; | ||
| 17 | |||
| 18 | aliases { | ||
| 19 | display0 = &lcd0; | ||
| 20 | display1 = &hdmi0; | ||
| 21 | }; | ||
| 22 | |||
| 23 | lcd0: display { | ||
| 24 | compatible = "innolux,at070tn83", "panel-dpi"; | ||
| 25 | label = "lcd"; | ||
| 26 | panel-timing { | ||
| 27 | clock-frequency = <33333333>; | ||
| 28 | |||
| 29 | hback-porch = <40>; | ||
| 30 | hactive = <800>; | ||
| 31 | hfront-porch = <40>; | ||
| 32 | hsync-len = <48>; | ||
| 33 | |||
| 34 | vback-porch = <29>; | ||
| 35 | vactive = <480>; | ||
| 36 | vfront-porch = <13>; | ||
| 37 | vsync-len = <3>; | ||
| 38 | }; | ||
| 39 | |||
| 40 | port { | ||
| 41 | lcd_in: endpoint { | ||
| 42 | remote-endpoint = <&dpi_out>; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | |||
| 47 | backlight { | ||
| 48 | compatible = "gpio-backlight"; | ||
| 49 | pinctrl-names = "default"; | ||
| 50 | pinctrl-0 = <&backlight_pins>; | ||
| 51 | |||
| 52 | gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio 122 */ | ||
| 53 | }; | ||
| 54 | }; | ||
| 55 | |||
| 56 | &dss { | ||
| 57 | pinctrl-names = "default"; | ||
| 58 | pinctrl-0 = <&dss_dpi_pins>; | ||
| 59 | |||
| 60 | port { | ||
| 61 | dpi_out: endpoint { | ||
| 62 | remote-endpoint = <&lcd_in>; | ||
| 63 | data-lines = <24>; | ||
| 64 | }; | ||
| 65 | }; | ||
| 66 | }; | ||
| 67 | |||
| 68 | &dsi2 { | ||
| 69 | status = "okay"; | ||
| 70 | vdd-supply = <&vcxio>; | ||
| 71 | }; | ||
diff --git a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi new file mode 100644 index 000000000000..f2d2fdb75628 --- /dev/null +++ b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi | |||
| @@ -0,0 +1,235 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <dt-bindings/input/input.h> | ||
| 10 | |||
| 11 | / { | ||
| 12 | aliases { | ||
| 13 | display0 = &hdmi0; | ||
| 14 | }; | ||
| 15 | |||
| 16 | leds { | ||
| 17 | compatible = "gpio-leds"; | ||
| 18 | pinctrl-names = "default"; | ||
| 19 | pinctrl-0 = <&gpio_led_pins>; | ||
| 20 | |||
| 21 | led0 { | ||
| 22 | label = "var:green:led0"; | ||
| 23 | gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio 173 */ | ||
| 24 | linux,default-trigger = "heartbeat"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | led1 { | ||
| 28 | label = "var:green:led1"; | ||
| 29 | gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; /* gpio 172 */ | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | |||
| 33 | gpio-keys { | ||
| 34 | compatible = "gpio-keys"; | ||
| 35 | pinctrl-names = "default"; | ||
| 36 | pinctrl-0 = <&gpio_key_pins>; | ||
| 37 | #address-cells = <1>; | ||
| 38 | #size-cells = <0>; | ||
| 39 | |||
| 40 | user-key@184 { | ||
| 41 | label = "user"; | ||
| 42 | gpios = <&gpio6 24 GPIO_ACTIVE_HIGH>; /* gpio 184 */ | ||
| 43 | linux,code = <BTN_EXTRA>; | ||
| 44 | gpio-key,wakeup; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | |||
| 48 | hdmi0: connector@0 { | ||
| 49 | compatible = "hdmi-connector"; | ||
| 50 | pinctrl-names = "default"; | ||
| 51 | pinctrl-0 = <&hdmi_hpd_pins>; | ||
| 52 | label = "hdmi"; | ||
| 53 | type = "a"; | ||
| 54 | |||
| 55 | hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio_63 */ | ||
| 56 | |||
| 57 | port { | ||
| 58 | hdmi_connector_in: endpoint { | ||
| 59 | remote-endpoint = <&hdmi_out>; | ||
| 60 | }; | ||
| 61 | }; | ||
| 62 | }; | ||
| 63 | }; | ||
| 64 | |||
| 65 | &omap4_pmx_core { | ||
| 66 | uart1_pins: pinmux_uart1_pins { | ||
| 67 | pinctrl-single,pins = < | ||
| 68 | OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi1_cs2.uart1_cts */ | ||
| 69 | OMAP4_IOPAD(0x13e, PIN_OUTPUT | MUX_MODE1) /* mcspi1_cs3.uart1_rts */ | ||
| 70 | OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE1) /* i2c2_scl.uart1_rx */ | ||
| 71 | OMAP4_IOPAD(0x128, PIN_OUTPUT | MUX_MODE1) /* i2c2_sda.uart1_tx */ | ||
| 72 | >; | ||
| 73 | }; | ||
| 74 | |||
| 75 | mcspi1_pins: pinmux_mcspi1_pins { | ||
| 76 | pinctrl-single,pins = < | ||
| 77 | OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ | ||
| 78 | OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ | ||
| 79 | OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ | ||
| 80 | OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ | ||
| 81 | >; | ||
| 82 | }; | ||
| 83 | |||
| 84 | mcasp_pins: pinmux_mcsasp_pins { | ||
| 85 | pinctrl-single,pins = < | ||
| 86 | OMAP4_IOPAD(0x0f8, PIN_OUTPUT | MUX_MODE2) /* mcbsp2_dr.abe_mcasp_axr */ | ||
| 87 | >; | ||
| 88 | }; | ||
| 89 | |||
| 90 | dss_dpi_pins: pinmux_dss_dpi_pins { | ||
| 91 | pinctrl-single,pins = < | ||
| 92 | OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ | ||
| 93 | OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ | ||
| 94 | OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */ | ||
| 95 | OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */ | ||
| 96 | OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */ | ||
| 97 | OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */ | ||
| 98 | OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */ | ||
| 99 | OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */ | ||
| 100 | OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */ | ||
| 101 | OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */ | ||
| 102 | OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */ | ||
| 103 | OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */ | ||
| 104 | OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */ | ||
| 105 | OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */ | ||
| 106 | OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */ | ||
| 107 | OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */ | ||
| 108 | OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */ | ||
| 109 | OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */ | ||
| 110 | OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5) /* dispc2_de */ | ||
| 111 | OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */ | ||
| 112 | OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */ | ||
| 113 | OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */ | ||
| 114 | OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */ | ||
| 115 | OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */ | ||
| 116 | OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */ | ||
| 117 | OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */ | ||
| 118 | OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */ | ||
| 119 | OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ | ||
| 120 | >; | ||
| 121 | }; | ||
| 122 | |||
| 123 | dss_hdmi_pins: pinmux_dss_hdmi_pins { | ||
| 124 | pinctrl-single,pins = < | ||
| 125 | OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ | ||
| 126 | OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ | ||
| 127 | OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ | ||
| 128 | >; | ||
| 129 | }; | ||
| 130 | |||
| 131 | i2c4_pins: pinmux_i2c4_pins { | ||
| 132 | pinctrl-single,pins = < | ||
| 133 | OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ | ||
| 134 | OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ | ||
| 135 | >; | ||
| 136 | }; | ||
| 137 | |||
| 138 | mmc5_pins: pinmux_mmc5_pins { | ||
| 139 | pinctrl-single,pins = < | ||
| 140 | OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE3) /* abe_mcbsp2_clkx.gpio_110 */ | ||
| 141 | OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ | ||
| 142 | OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ | ||
| 143 | OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ | ||
| 144 | OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ | ||
| 145 | OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ | ||
| 146 | OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ | ||
| 147 | >; | ||
| 148 | }; | ||
| 149 | |||
| 150 | gpio_led_pins: pinmux_gpio_led_pins { | ||
| 151 | pinctrl-single,pins = < | ||
| 152 | OMAP4_IOPAD(0x17e, PIN_OUTPUT | MUX_MODE3) /* kpd_col4.gpio_172 */ | ||
| 153 | OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) /* kpd_col5.gpio_173 */ | ||
| 154 | >; | ||
| 155 | }; | ||
| 156 | |||
| 157 | gpio_key_pins: pinmux_gpio_key_pins { | ||
| 158 | pinctrl-single,pins = < | ||
| 159 | OMAP4_IOPAD(0x1a2, PIN_INPUT | MUX_MODE3) /* sys_boot0.gpio_184 */ | ||
| 160 | >; | ||
| 161 | }; | ||
| 162 | |||
| 163 | ks8851_irq_pins: pinmux_ks8851_irq_pins { | ||
| 164 | pinctrl-single,pins = < | ||
| 165 | OMAP4_IOPAD(0x17c, PIN_INPUT_PULLUP | MUX_MODE3) /* kpd_col3.gpio_171 */ | ||
| 166 | >; | ||
| 167 | }; | ||
| 168 | |||
| 169 | hdmi_hpd_pins: pinmux_hdmi_hpd_pins { | ||
| 170 | pinctrl-single,pins = < | ||
| 171 | OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ | ||
| 172 | >; | ||
| 173 | }; | ||
| 174 | |||
| 175 | backlight_pins: pinmux_backlight_pins { | ||
| 176 | pinctrl-single,pins = < | ||
| 177 | OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ | ||
| 178 | >; | ||
| 179 | }; | ||
| 180 | }; | ||
| 181 | |||
| 182 | &i2c4 { | ||
| 183 | pinctrl-names = "default"; | ||
| 184 | pinctrl-0 = <&i2c4_pins>; | ||
| 185 | clock-frequency = <400000>; | ||
| 186 | status = "okay"; | ||
| 187 | }; | ||
| 188 | |||
| 189 | &uart1 { | ||
| 190 | pinctrl-names = "default"; | ||
| 191 | pinctrl-0 = <&uart1_pins>; | ||
| 192 | status = "okay"; | ||
| 193 | }; | ||
| 194 | |||
| 195 | &mcspi1 { | ||
| 196 | pinctrl-names = "default"; | ||
| 197 | pinctrl-0 = <&mcspi1_pins>; | ||
| 198 | status = "okay"; | ||
| 199 | |||
| 200 | eth@0 { | ||
| 201 | compatible = "ks8851"; | ||
| 202 | pinctrl-names = "default"; | ||
| 203 | pinctrl-0 = <&ks8851_irq_pins>; | ||
| 204 | spi-max-frequency = <24000000>; | ||
| 205 | reg = <0>; | ||
| 206 | interrupt-parent = <&gpio6>; | ||
| 207 | interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio 171 */ | ||
| 208 | }; | ||
| 209 | }; | ||
| 210 | |||
| 211 | &mmc5 { | ||
| 212 | pinctrl-names = "default"; | ||
| 213 | pinctrl-0 = <&mmc5_pins>; | ||
| 214 | vmmc-supply = <&vbat>; | ||
| 215 | bus-width = <4>; | ||
| 216 | cd-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; /* gpio 110 */ | ||
| 217 | status = "okay"; | ||
| 218 | }; | ||
| 219 | |||
| 220 | &dss { | ||
| 221 | status = "okay"; | ||
| 222 | }; | ||
| 223 | |||
| 224 | &hdmi { | ||
| 225 | status = "okay"; | ||
| 226 | pinctrl-names = "default"; | ||
| 227 | pinctrl-0 = <&dss_hdmi_pins>; | ||
| 228 | vdda-supply = <&vdac>; | ||
| 229 | |||
| 230 | port { | ||
| 231 | hdmi_out: endpoint { | ||
| 232 | remote-endpoint = <&hdmi_connector_in>; | ||
| 233 | }; | ||
| 234 | }; | ||
| 235 | }; | ||
diff --git a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi new file mode 100644 index 000000000000..cc66af419236 --- /dev/null +++ b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | / { | ||
| 10 | /* regulator for wl12xx on sdio4 */ | ||
| 11 | wl12xx_vmmc: wl12xx_vmmc { | ||
| 12 | pinctrl-names = "default"; | ||
| 13 | pinctrl-0 = <&wl12xx_ctrl_pins>; | ||
| 14 | compatible = "regulator-fixed"; | ||
| 15 | regulator-name = "vwl1271"; | ||
| 16 | regulator-min-microvolt = <1800000>; | ||
| 17 | regulator-max-microvolt = <1800000>; | ||
| 18 | gpio = <&gpio2 11 0>; /* gpio 43 */ | ||
| 19 | startup-delay-us = <70000>; | ||
| 20 | enable-active-high; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | |||
| 24 | &omap4_pmx_core { | ||
| 25 | uart2_pins: pinmux_uart2_pins { | ||
| 26 | pinctrl-single,pins = < | ||
| 27 | OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ | ||
| 28 | OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ | ||
| 29 | OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ | ||
| 30 | OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ | ||
| 31 | >; | ||
| 32 | }; | ||
| 33 | |||
| 34 | wl12xx_ctrl_pins: pinmux_wl12xx_ctrl_pins { | ||
| 35 | pinctrl-single,pins = < | ||
| 36 | OMAP4_IOPAD(0x062, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a17.gpio_41 (WLAN_IRQ) */ | ||
| 37 | OMAP4_IOPAD(0x064, PIN_OUTPUT | MUX_MODE3) /* gpmc_a18.gpio_42 (BT_EN) */ | ||
| 38 | OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 (WLAN_EN) */ | ||
| 39 | >; | ||
| 40 | }; | ||
| 41 | |||
| 42 | mmc4_pins: pinmux_mmc4_pins { | ||
| 43 | pinctrl-single,pins = < | ||
| 44 | OMAP4_IOPAD(0x154, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_clk.sdmmc4_clk */ | ||
| 45 | OMAP4_IOPAD(0x156, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_simo.sdmmc4_cmd */ | ||
| 46 | OMAP4_IOPAD(0x158, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_somi.sdmmc4_dat0 */ | ||
| 47 | OMAP4_IOPAD(0x15e, PIN_INPUT_PULLUP | MUX_MODE1) /* uart4_tx.sdmmc4_dat1 */ | ||
| 48 | OMAP4_IOPAD(0x15c, PIN_INPUT_PULLUP | MUX_MODE1) /* uart4_rx.sdmmc4_dat2 */ | ||
| 49 | OMAP4_IOPAD(0x15a, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_cs0.sdmmc4_dat3 */ | ||
| 50 | >; | ||
| 51 | }; | ||
| 52 | }; | ||
| 53 | |||
| 54 | &uart2 { | ||
| 55 | pinctrl-names = "default"; | ||
| 56 | pinctrl-0 = <&uart2_pins>; | ||
| 57 | status = "okay"; | ||
| 58 | }; | ||
| 59 | |||
| 60 | &mmc4 { | ||
| 61 | pinctrl-names = "default"; | ||
| 62 | pinctrl-0 = <&mmc4_pins>; | ||
| 63 | vmmc-supply = <&wl12xx_vmmc>; | ||
| 64 | non-removable; | ||
| 65 | bus-width = <4>; | ||
| 66 | cap-power-off-card; | ||
| 67 | status = "okay"; | ||
| 68 | }; | ||
diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi new file mode 100644 index 000000000000..062701e1a898 --- /dev/null +++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi | |||
| @@ -0,0 +1,343 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com> | ||
| 3 | * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include "omap4460.dtsi" | ||
| 10 | |||
| 11 | / { | ||
| 12 | model = "Variscite VAR-SOM-OM44"; | ||
| 13 | compatible = "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; | ||
| 14 | |||
| 15 | memory { | ||
| 16 | device_type = "memory"; | ||
| 17 | reg = <0x80000000 0x40000000>; /* 1 GB */ | ||
| 18 | }; | ||
| 19 | |||
| 20 | sound: sound@0 { | ||
| 21 | compatible = "ti,abe-twl6040"; | ||
| 22 | ti,model = "VAR-SOM-OM44"; | ||
| 23 | |||
| 24 | ti,mclk-freq = <38400000>; | ||
| 25 | ti,mcpdm = <&mcpdm>; | ||
| 26 | ti,twl6040 = <&twl6040>; | ||
| 27 | |||
| 28 | /* Audio routing */ | ||
| 29 | ti,audio-routing = | ||
| 30 | "Headset Stereophone", "HSOL", | ||
| 31 | "Headset Stereophone", "HSOR", | ||
| 32 | "AFML", "Line In", | ||
| 33 | "AFMR", "Line In"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | /* HS USB Host PHY on PORT 1 */ | ||
| 37 | hsusb1_phy: hsusb1_phy { | ||
| 38 | compatible = "usb-nop-xceiv"; | ||
| 39 | pinctrl-names = "default"; | ||
| 40 | pinctrl-0 = < | ||
| 41 | &hsusbb1_phy_clk_pins | ||
| 42 | &hsusbb1_phy_rst_pins | ||
| 43 | >; | ||
| 44 | |||
| 45 | reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; /* gpio 177 */ | ||
| 46 | vcc-supply = <&vbat>; | ||
| 47 | |||
| 48 | clocks = <&auxclk3_ck>; | ||
| 49 | clock-names = "main_clk"; | ||
| 50 | clock-frequency = <19200000>; | ||
| 51 | }; | ||
| 52 | |||
| 53 | vbat: fixedregulator-vbat { | ||
| 54 | compatible = "regulator-fixed"; | ||
| 55 | regulator-name = "VBAT"; | ||
| 56 | regulator-min-microvolt = <3300000>; | ||
| 57 | regulator-max-microvolt = <3300000>; | ||
| 58 | regulator-always-on; | ||
| 59 | regulator-boot-on; | ||
| 60 | }; | ||
| 61 | }; | ||
| 62 | |||
| 63 | &omap4_pmx_core { | ||
| 64 | pinctrl-names = "default"; | ||
| 65 | pinctrl-0 = < | ||
| 66 | &hsusbb1_pins | ||
| 67 | >; | ||
| 68 | |||
| 69 | twl6040_pins: pinmux_twl6040_pins { | ||
| 70 | pinctrl-single,pins = < | ||
| 71 | OMAP4_IOPAD(0x19c, PIN_OUTPUT | MUX_MODE3) /* fref_clk2_out.gpio_182 */ | ||
| 72 | OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ | ||
| 73 | >; | ||
| 74 | }; | ||
| 75 | |||
| 76 | mcpdm_pins: pinmux_mcpdm_pins { | ||
| 77 | pinctrl-single,pins = < | ||
| 78 | OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ | ||
| 79 | OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ | ||
| 80 | OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ | ||
| 81 | OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ | ||
| 82 | OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ | ||
| 83 | >; | ||
| 84 | }; | ||
| 85 | |||
| 86 | tsc2004_pins: pinmux_tsc2004_pins { | ||
| 87 | pinctrl-single,pins = < | ||
| 88 | OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3) /* gpmc_ncs4.gpio_101 (irq) */ | ||
| 89 | OMAP4_IOPAD(0x092, PIN_OUTPUT | MUX_MODE3) /* gpmc_ncs5.gpio_102 (rst) */ | ||
| 90 | >; | ||
| 91 | }; | ||
| 92 | |||
| 93 | uart3_pins: pinmux_uart3_pins { | ||
| 94 | pinctrl-single,pins = < | ||
| 95 | OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ | ||
| 96 | OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ | ||
| 97 | OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ | ||
| 98 | OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ | ||
| 99 | >; | ||
| 100 | }; | ||
| 101 | |||
| 102 | hsusbb1_pins: pinmux_hsusbb1_pins { | ||
| 103 | pinctrl-single,pins = < | ||
| 104 | OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ | ||
| 105 | OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ | ||
| 106 | OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ | ||
| 107 | OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ | ||
| 108 | OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ | ||
| 109 | OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ | ||
| 110 | OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ | ||
| 111 | OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ | ||
| 112 | OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ | ||
| 113 | OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ | ||
| 114 | OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ | ||
| 115 | OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ | ||
| 116 | >; | ||
| 117 | }; | ||
| 118 | |||
| 119 | hsusbb1_phy_rst_pins: pinmux_hsusbb1_phy_rst_pins { | ||
| 120 | pinctrl-single,pins = < | ||
| 121 | OMAP4_IOPAD(0x18c, PIN_OUTPUT | MUX_MODE3) /* kpd_row2.gpio_177 */ | ||
| 122 | >; | ||
| 123 | }; | ||
| 124 | |||
| 125 | i2c1_pins: pinmux_i2c1_pins { | ||
| 126 | pinctrl-single,pins = < | ||
| 127 | OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ | ||
| 128 | OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ | ||
| 129 | >; | ||
| 130 | }; | ||
| 131 | |||
| 132 | i2c3_pins: pinmux_i2c3_pins { | ||
| 133 | pinctrl-single,pins = < | ||
| 134 | OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ | ||
| 135 | OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ | ||
| 136 | >; | ||
| 137 | }; | ||
| 138 | |||
| 139 | mmc1_pins: pinmux_mmc1_pins { | ||
| 140 | pinctrl-single,pins = < | ||
| 141 | OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ | ||
| 142 | OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ | ||
| 143 | OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ | ||
| 144 | OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ | ||
| 145 | OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ | ||
| 146 | OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ | ||
| 147 | >; | ||
| 148 | }; | ||
| 149 | }; | ||
| 150 | |||
| 151 | &omap4_pmx_wkup { | ||
| 152 | pinctrl-names = "default"; | ||
| 153 | pinctrl-0 = < | ||
| 154 | &hsusbb1_hub_rst_pins | ||
| 155 | &lan7500_rst_pins | ||
| 156 | >; | ||
| 157 | |||
| 158 | hsusbb1_phy_clk_pins: pinmux_hsusbb1_phy_clk_pins { | ||
| 159 | pinctrl-single,pins = < | ||
| 160 | OMAP4_IOPAD(0x058, PIN_OUTPUT | MUX_MODE0) /* fref_clk3_out */ | ||
| 161 | >; | ||
| 162 | }; | ||
| 163 | |||
| 164 | hsusbb1_hub_rst_pins: pinmux_hsusbb1_hub_rst_pins { | ||
| 165 | pinctrl-single,pins = < | ||
| 166 | OMAP4_IOPAD(0x042, PIN_OUTPUT | MUX_MODE3) /* gpio_wk1 */ | ||
| 167 | >; | ||
| 168 | }; | ||
| 169 | |||
| 170 | lan7500_rst_pins: pinmux_lan7500_rst_pins { | ||
| 171 | pinctrl-single,pins = < | ||
| 172 | OMAP4_IOPAD(0x040, PIN_OUTPUT | MUX_MODE3) /* gpio_wk0 */ | ||
| 173 | >; | ||
| 174 | }; | ||
| 175 | }; | ||
| 176 | |||
| 177 | &i2c1 { | ||
| 178 | pinctrl-names = "default"; | ||
| 179 | pinctrl-0 = <&i2c1_pins>; | ||
| 180 | status = "okay"; | ||
| 181 | |||
| 182 | clock-frequency = <400000>; | ||
| 183 | |||
| 184 | twl: twl@48 { | ||
| 185 | reg = <0x48>; | ||
| 186 | /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ | ||
| 187 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ | ||
| 188 | interrupt-parent = <&gic>; | ||
| 189 | }; | ||
| 190 | |||
| 191 | twl6040: twl@4b { | ||
| 192 | compatible = "ti,twl6040"; | ||
| 193 | reg = <0x4b>; | ||
| 194 | |||
| 195 | pinctrl-names = "default"; | ||
| 196 | pinctrl-0 = <&twl6040_pins>; | ||
| 197 | |||
| 198 | /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ | ||
| 199 | interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ | ||
| 200 | interrupt-parent = <&gic>; | ||
| 201 | ti,audpwron-gpio = <&gpio6 22 0>; /* gpio 182 */ | ||
| 202 | |||
| 203 | vio-supply = <&v1v8>; | ||
| 204 | v2v1-supply = <&v2v1>; | ||
| 205 | enable-active-high; | ||
| 206 | }; | ||
| 207 | }; | ||
| 208 | |||
| 209 | #include "twl6030.dtsi" | ||
| 210 | #include "twl6030_omap4.dtsi" | ||
| 211 | |||
| 212 | &vusim { | ||
| 213 | regulator-min-microvolt = <3000000>; | ||
| 214 | regulator-max-microvolt = <3000000>; | ||
| 215 | regulator-always-on; | ||
| 216 | }; | ||
| 217 | |||
| 218 | &i2c2 { | ||
| 219 | status = "disabled"; | ||
| 220 | }; | ||
| 221 | |||
| 222 | &i2c3 { | ||
| 223 | pinctrl-names = "default"; | ||
| 224 | pinctrl-0 = <&i2c3_pins>; | ||
| 225 | status = "okay"; | ||
| 226 | |||
| 227 | clock-frequency = <400000>; | ||
| 228 | |||
| 229 | touchscreen: tsc2004@48 { | ||
| 230 | compatible = "ti,tsc2004"; | ||
| 231 | reg = <0x48>; | ||
| 232 | pinctrl-names = "default"; | ||
| 233 | pinctrl-0 = <&tsc2004_pins>; | ||
| 234 | interrupt-parent = <&gpio4>; | ||
| 235 | interrupts = <5 IRQ_TYPE_LEVEL_LOW>; /* gpio 101 */ | ||
| 236 | status = "disabled"; | ||
| 237 | }; | ||
| 238 | |||
| 239 | tmp105@49 { | ||
| 240 | compatible = "ti,tmp105"; | ||
| 241 | reg = <0x49>; | ||
| 242 | }; | ||
| 243 | |||
| 244 | eeprom@50 { | ||
| 245 | compatible = "microchip,24c32"; | ||
| 246 | reg = <0x50>; | ||
| 247 | }; | ||
| 248 | }; | ||
| 249 | |||
| 250 | &i2c4 { | ||
| 251 | status = "disabled"; | ||
| 252 | }; | ||
| 253 | |||
| 254 | &mcpdm { | ||
| 255 | pinctrl-names = "default"; | ||
| 256 | pinctrl-0 = <&mcpdm_pins>; | ||
| 257 | status = "okay"; | ||
| 258 | }; | ||
| 259 | |||
| 260 | &gpmc { | ||
| 261 | status = "disabled"; | ||
| 262 | }; | ||
| 263 | |||
| 264 | &mcspi1 { | ||
| 265 | status = "disabled"; | ||
| 266 | }; | ||
| 267 | |||
| 268 | &mcspi2 { | ||
| 269 | status = "disabled"; | ||
| 270 | }; | ||
| 271 | |||
| 272 | &mcspi3 { | ||
| 273 | status = "disabled"; | ||
| 274 | }; | ||
| 275 | |||
| 276 | &mcspi4 { | ||
| 277 | status = "disabled"; | ||
| 278 | }; | ||
| 279 | |||
| 280 | &mmc1 { | ||
| 281 | pinctrl-names = "default"; | ||
| 282 | pinctrl-0 = <&mmc1_pins>; | ||
| 283 | vmmc-supply = <&vmmc>; | ||
| 284 | bus-width = <4>; | ||
| 285 | ti,non-removable; | ||
| 286 | status = "okay"; | ||
| 287 | }; | ||
| 288 | |||
| 289 | &mmc2 { | ||
| 290 | status = "disabled"; | ||
| 291 | }; | ||
| 292 | |||
| 293 | &mmc3 { | ||
| 294 | status = "disabled"; | ||
| 295 | }; | ||
| 296 | |||
| 297 | &mmc4 { | ||
| 298 | status = "disabled"; | ||
| 299 | }; | ||
| 300 | |||
| 301 | &mmc5 { | ||
| 302 | status = "disabled"; | ||
| 303 | }; | ||
| 304 | |||
| 305 | &uart1 { | ||
| 306 | status = "disabled"; | ||
| 307 | }; | ||
| 308 | |||
| 309 | &uart2 { | ||
| 310 | status = "disabled"; | ||
| 311 | }; | ||
| 312 | |||
| 313 | &uart3 { | ||
| 314 | pinctrl-names = "default"; | ||
| 315 | pinctrl-0 = <&uart3_pins>; | ||
| 316 | status = "okay"; | ||
| 317 | }; | ||
| 318 | |||
| 319 | &uart4 { | ||
| 320 | status = "disabled"; | ||
| 321 | }; | ||
| 322 | |||
| 323 | &keypad { | ||
| 324 | status = "disabled"; | ||
| 325 | }; | ||
| 326 | |||
| 327 | &twl_usb_comparator { | ||
| 328 | usb-supply = <&vusb>; | ||
| 329 | }; | ||
| 330 | |||
| 331 | &usb_otg_hs { | ||
| 332 | interface-type = <1>; | ||
| 333 | mode = <3>; | ||
| 334 | power = <50>; | ||
| 335 | }; | ||
| 336 | |||
| 337 | &usbhshost { | ||
| 338 | port1-mode = "ehci-phy"; | ||
| 339 | }; | ||
| 340 | |||
| 341 | &usbhsehci { | ||
| 342 | phys = <&hsusb1_phy>; | ||
| 343 | }; | ||
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts deleted file mode 100644 index b41269e871dd..000000000000 --- a/arch/arm/boot/dts/omap4-var-som.dts +++ /dev/null | |||
| @@ -1,96 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | /dts-v1/; | ||
| 9 | |||
| 10 | #include "omap443x.dtsi" | ||
| 11 | |||
| 12 | / { | ||
| 13 | model = "Variscite OMAP4 SOM"; | ||
| 14 | compatible = "var,omap4-var_som", "ti,omap4430", "ti,omap4"; | ||
| 15 | |||
| 16 | memory { | ||
| 17 | device_type = "memory"; | ||
| 18 | reg = <0x80000000 0x40000000>; /* 1 GB */ | ||
| 19 | }; | ||
| 20 | |||
| 21 | vdd_eth: fixedregulator@0 { | ||
| 22 | compatible = "regulator-fixed"; | ||
| 23 | regulator-name = "VDD_ETH"; | ||
| 24 | regulator-min-microvolt = <3300000>; | ||
| 25 | regulator-max-microvolt = <3300000>; | ||
| 26 | enable-active-high; | ||
| 27 | regulator-boot-on; | ||
| 28 | }; | ||
| 29 | }; | ||
| 30 | |||
| 31 | &i2c1 { | ||
| 32 | clock-frequency = <400000>; | ||
| 33 | |||
| 34 | twl: twl@48 { | ||
| 35 | reg = <0x48>; | ||
| 36 | /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ | ||
| 37 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ | ||
| 38 | interrupt-parent = <&gic>; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | |||
| 42 | #include "twl6030.dtsi" | ||
| 43 | |||
| 44 | &i2c2 { | ||
| 45 | clock-frequency = <400000>; | ||
| 46 | }; | ||
| 47 | |||
| 48 | &i2c3 { | ||
| 49 | clock-frequency = <400000>; | ||
| 50 | |||
| 51 | /* | ||
| 52 | * Temperature Sensor | ||
| 53 | * http://www.ti.com/lit/ds/symlink/tmp105.pdf | ||
| 54 | */ | ||
| 55 | tmp105@49 { | ||
| 56 | compatible = "ti,tmp105"; | ||
| 57 | reg = <0x49>; | ||
| 58 | }; | ||
| 59 | }; | ||
| 60 | |||
| 61 | &i2c4 { | ||
| 62 | clock-frequency = <400000>; | ||
| 63 | }; | ||
| 64 | |||
| 65 | &mcspi1 { | ||
| 66 | eth@0 { | ||
| 67 | compatible = "ks8851"; | ||
| 68 | spi-max-frequency = <24000000>; | ||
| 69 | reg = <0>; | ||
| 70 | interrupt-parent = <&gpio6>; | ||
| 71 | interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio line 171 */ | ||
| 72 | vdd-supply = <&vdd_eth>; | ||
| 73 | }; | ||
| 74 | }; | ||
| 75 | |||
| 76 | &mmc1 { | ||
| 77 | vmmc-supply = <&vmmc>; | ||
| 78 | ti,bus-width = <8>; | ||
| 79 | ti,non-removable; | ||
| 80 | }; | ||
| 81 | |||
| 82 | &mmc2 { | ||
| 83 | status = "disabled"; | ||
| 84 | }; | ||
| 85 | |||
| 86 | &mmc3 { | ||
| 87 | status = "disabled"; | ||
| 88 | }; | ||
| 89 | |||
| 90 | &mmc4 { | ||
| 91 | status = "disabled"; | ||
| 92 | }; | ||
| 93 | |||
| 94 | &mmc5 { | ||
| 95 | ti,bus-width = <4>; | ||
| 96 | }; | ||
diff --git a/arch/arm/boot/dts/omap4-var-stk-om44.dts b/arch/arm/boot/dts/omap4-var-stk-om44.dts new file mode 100644 index 000000000000..56b64e618608 --- /dev/null +++ b/arch/arm/boot/dts/omap4-var-stk-om44.dts | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | /dts-v1/; | ||
| 9 | |||
| 10 | #include "omap4-var-som-om44.dtsi" | ||
| 11 | #include "omap4-var-som-om44-wlan.dtsi" | ||
| 12 | #include "omap4-var-om44customboard.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "Variscite VAR-STK-OM44"; | ||
| 16 | compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; | ||
| 17 | }; | ||
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 649b5cd38b40..43a587e097d4 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi | |||
| @@ -67,6 +67,7 @@ | |||
| 67 | 67 | ||
| 68 | local-timer@48240600 { | 68 | local-timer@48240600 { |
| 69 | compatible = "arm,cortex-a9-twd-timer"; | 69 | compatible = "arm,cortex-a9-twd-timer"; |
| 70 | clocks = <&mpu_periphclk>; | ||
| 70 | reg = <0x48240600 0x20>; | 71 | reg = <0x48240600 0x20>; |
| 71 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; | 72 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; |
| 72 | }; | 73 | }; |
| @@ -311,7 +312,7 @@ | |||
| 311 | uart2: serial@4806c000 { | 312 | uart2: serial@4806c000 { |
| 312 | compatible = "ti,omap4-uart"; | 313 | compatible = "ti,omap4-uart"; |
| 313 | reg = <0x4806c000 0x100>; | 314 | reg = <0x4806c000 0x100>; |
| 314 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | 315 | interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 315 | ti,hwmods = "uart2"; | 316 | ti,hwmods = "uart2"; |
| 316 | clock-frequency = <48000000>; | 317 | clock-frequency = <48000000>; |
| 317 | }; | 318 | }; |
| @@ -319,7 +320,7 @@ | |||
| 319 | uart3: serial@48020000 { | 320 | uart3: serial@48020000 { |
| 320 | compatible = "ti,omap4-uart"; | 321 | compatible = "ti,omap4-uart"; |
| 321 | reg = <0x48020000 0x100>; | 322 | reg = <0x48020000 0x100>; |
| 322 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | 323 | interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 323 | ti,hwmods = "uart3"; | 324 | ti,hwmods = "uart3"; |
| 324 | clock-frequency = <48000000>; | 325 | clock-frequency = <48000000>; |
| 325 | }; | 326 | }; |
| @@ -327,7 +328,7 @@ | |||
| 327 | uart4: serial@4806e000 { | 328 | uart4: serial@4806e000 { |
| 328 | compatible = "ti,omap4-uart"; | 329 | compatible = "ti,omap4-uart"; |
| 329 | reg = <0x4806e000 0x100>; | 330 | reg = <0x4806e000 0x100>; |
| 330 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | 331 | interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
| 331 | ti,hwmods = "uart4"; | 332 | ti,hwmods = "uart4"; |
| 332 | clock-frequency = <48000000>; | 333 | clock-frequency = <48000000>; |
| 333 | }; | 334 | }; |
| @@ -642,6 +643,8 @@ | |||
| 642 | compatible = "ti,omap-usb2"; | 643 | compatible = "ti,omap-usb2"; |
| 643 | reg = <0x4a0ad080 0x58>; | 644 | reg = <0x4a0ad080 0x58>; |
| 644 | ctrl-module = <&omap_control_usb2phy>; | 645 | ctrl-module = <&omap_control_usb2phy>; |
| 646 | clocks = <&usb_phy_cm_clk32k>; | ||
| 647 | clock-names = "wkupclk"; | ||
| 645 | #phy-cells = <0>; | 648 | #phy-cells = <0>; |
| 646 | }; | 649 | }; |
| 647 | }; | 650 | }; |
diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts new file mode 100644 index 000000000000..b8698ca68647 --- /dev/null +++ b/arch/arm/boot/dts/omap5-cm-t54.dts | |||
| @@ -0,0 +1,413 @@ | |||
| 1 | /* | ||
| 2 | * Support for CompuLab CM-T54 | ||
| 3 | */ | ||
| 4 | /dts-v1/; | ||
| 5 | |||
| 6 | #include "omap5.dtsi" | ||
| 7 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 8 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 9 | |||
| 10 | / { | ||
| 11 | model = "CompuLab CM-T54"; | ||
| 12 | compatible = "compulab,omap5-cm-t54", "ti,omap5"; | ||
| 13 | |||
| 14 | memory { | ||
| 15 | device_type = "memory"; | ||
| 16 | reg = <0x80000000 0x7F000000>; /* 2048 MB */ | ||
| 17 | }; | ||
| 18 | |||
| 19 | vmmcsd_fixed: fixed-regulator-mmcsd { | ||
| 20 | compatible = "regulator-fixed"; | ||
| 21 | regulator-name = "vmmcsd_fixed"; | ||
| 22 | regulator-min-microvolt = <3300000>; | ||
| 23 | regulator-max-microvolt = <3300000>; | ||
| 24 | }; | ||
| 25 | |||
| 26 | vwlan_pdn_fixed: fixed-regulator-vwlan-pdn { | ||
| 27 | compatible = "regulator-fixed"; | ||
| 28 | regulator-name = "vwlan_pdn_fixed"; | ||
| 29 | regulator-min-microvolt = <3300000>; | ||
| 30 | regulator-max-microvolt = <3300000>; | ||
| 31 | vin-supply = <&ldo2_reg>; | ||
| 32 | gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* gpio4_109 */ | ||
| 33 | startup-delay-us = <1000>; | ||
| 34 | enable-active-high; | ||
| 35 | }; | ||
| 36 | |||
| 37 | vwlan_fixed: fixed-regulator-vwlan { | ||
| 38 | compatible = "regulator-fixed"; | ||
| 39 | regulator-name = "vwlan_fixed"; | ||
| 40 | regulator-min-microvolt = <3300000>; | ||
| 41 | regulator-max-microvolt = <3300000>; | ||
| 42 | vin-supply = <&vwlan_pdn_fixed>; | ||
| 43 | gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; /* gpio4_110 */ | ||
| 44 | startup-delay-us = <1000>; | ||
| 45 | enable-active-high; | ||
| 46 | }; | ||
| 47 | |||
| 48 | /* HS USB Host PHY on PORT 2 */ | ||
| 49 | hsusb2_phy: hsusb2_phy { | ||
| 50 | compatible = "usb-nop-xceiv"; | ||
| 51 | reset-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; /* gpio3_76 HUB_RESET */ | ||
| 52 | }; | ||
| 53 | |||
| 54 | /* HS USB Host PHY on PORT 3 */ | ||
| 55 | hsusb3_phy: hsusb3_phy { | ||
| 56 | compatible = "usb-nop-xceiv"; | ||
| 57 | reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 ETH_RESET */ | ||
| 58 | }; | ||
| 59 | |||
| 60 | leds { | ||
| 61 | compatible = "gpio-leds"; | ||
| 62 | led@1 { | ||
| 63 | label = "Heartbeat"; | ||
| 64 | gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 ACT_LED */ | ||
| 65 | linux,default-trigger = "heartbeat"; | ||
| 66 | default-state = "off"; | ||
| 67 | }; | ||
| 68 | }; | ||
| 69 | }; | ||
| 70 | |||
| 71 | &omap5_pmx_core { | ||
| 72 | pinctrl-names = "default"; | ||
| 73 | pinctrl-0 = < | ||
| 74 | &led_gpio_pins | ||
| 75 | &usbhost_pins | ||
| 76 | >; | ||
| 77 | |||
| 78 | led_gpio_pins: pinmux_led_gpio_pins { | ||
| 79 | pinctrl-single,pins = < | ||
| 80 | OMAP5_IOPAD(0x00b0, PIN_OUTPUT | MUX_MODE6) /* hsi2_caflag.gpio3_80 */ | ||
| 81 | >; | ||
| 82 | }; | ||
| 83 | |||
| 84 | i2c1_pins: pinmux_i2c1_pins { | ||
| 85 | pinctrl-single,pins = < | ||
| 86 | OMAP5_IOPAD(0x01f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_scl */ | ||
| 87 | OMAP5_IOPAD(0x01f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_sda */ | ||
| 88 | >; | ||
| 89 | }; | ||
| 90 | |||
| 91 | mmc1_pins: pinmux_mmc1_pins { | ||
| 92 | pinctrl-single,pins = < | ||
| 93 | OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */ | ||
| 94 | OMAP5_IOPAD(0x01e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_cmd */ | ||
| 95 | OMAP5_IOPAD(0x01e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data2 */ | ||
| 96 | OMAP5_IOPAD(0x01e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data3 */ | ||
| 97 | OMAP5_IOPAD(0x01ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data0 */ | ||
| 98 | OMAP5_IOPAD(0x01ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data1 */ | ||
| 99 | >; | ||
| 100 | }; | ||
| 101 | |||
| 102 | mmc2_pins: pinmux_mmc2_pins { | ||
| 103 | pinctrl-single,pins = < | ||
| 104 | OMAP5_IOPAD(0x0040, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_clk */ | ||
| 105 | OMAP5_IOPAD(0x0042, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_cmd */ | ||
| 106 | OMAP5_IOPAD(0x0044, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data0 */ | ||
| 107 | OMAP5_IOPAD(0x0046, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data1 */ | ||
| 108 | OMAP5_IOPAD(0x0048, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data2 */ | ||
| 109 | OMAP5_IOPAD(0x004a, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data3 */ | ||
| 110 | OMAP5_IOPAD(0x004c, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data4 */ | ||
| 111 | OMAP5_IOPAD(0x004e, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data5 */ | ||
| 112 | OMAP5_IOPAD(0x0050, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data6 */ | ||
| 113 | OMAP5_IOPAD(0x0052, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data7 */ | ||
| 114 | >; | ||
| 115 | }; | ||
| 116 | |||
| 117 | mmc3_pins: pinmux_mmc3_pins { | ||
| 118 | pinctrl-single,pins = < | ||
| 119 | OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ | ||
| 120 | OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ | ||
| 121 | OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */ | ||
| 122 | OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */ | ||
| 123 | OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */ | ||
| 124 | OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ | ||
| 125 | >; | ||
| 126 | }; | ||
| 127 | |||
| 128 | wlan_gpios_pins: pinmux_wlan_gpios_pins { | ||
| 129 | pinctrl-single,pins = < | ||
| 130 | OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_109 */ | ||
| 131 | OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_110 */ | ||
| 132 | >; | ||
| 133 | }; | ||
| 134 | |||
| 135 | usbhost_pins: pinmux_usbhost_pins { | ||
| 136 | pinctrl-single,pins = < | ||
| 137 | OMAP5_IOPAD(0x00c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ | ||
| 138 | OMAP5_IOPAD(0x00c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ | ||
| 139 | |||
| 140 | OMAP5_IOPAD(0x01dc, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ | ||
| 141 | OMAP5_IOPAD(0x01de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ | ||
| 142 | |||
| 143 | OMAP5_IOPAD(0x00a8, PIN_OUTPUT | MUX_MODE6) /* hsi2_caready.gpio3_76 */ | ||
| 144 | OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */ | ||
| 145 | >; | ||
| 146 | }; | ||
| 147 | }; | ||
| 148 | |||
| 149 | &mmc1 { | ||
| 150 | pinctrl-names = "default"; | ||
| 151 | pinctrl-0 = <&mmc1_pins>; | ||
| 152 | vmmc-supply = <&ldo9_reg>; | ||
| 153 | bus-width = <4>; | ||
| 154 | }; | ||
| 155 | |||
| 156 | &mmc2 { | ||
| 157 | pinctrl-names = "default"; | ||
| 158 | pinctrl-0 = <&mmc2_pins>; | ||
| 159 | vmmc-supply = <&vmmcsd_fixed>; | ||
| 160 | bus-width = <8>; | ||
| 161 | ti,non-removable; | ||
| 162 | }; | ||
| 163 | |||
| 164 | &mmc3 { | ||
| 165 | pinctrl-names = "default"; | ||
| 166 | pinctrl-0 = < | ||
| 167 | &mmc3_pins | ||
| 168 | &wlan_gpios_pins | ||
| 169 | >; | ||
| 170 | vmmc-supply = <&vwlan_fixed>; | ||
| 171 | bus-width = <4>; | ||
| 172 | ti,non-removable; | ||
| 173 | }; | ||
| 174 | |||
| 175 | &mmc4 { | ||
| 176 | status = "disabled"; | ||
| 177 | }; | ||
| 178 | |||
| 179 | &mmc5 { | ||
| 180 | status = "disabled"; | ||
| 181 | }; | ||
| 182 | |||
| 183 | &i2c1 { | ||
| 184 | pinctrl-names = "default"; | ||
| 185 | pinctrl-0 = <&i2c1_pins>; | ||
| 186 | |||
| 187 | clock-frequency = <400000>; | ||
| 188 | |||
| 189 | at24@50 { | ||
| 190 | compatible = "at24,24c02"; | ||
| 191 | pagesize = <16>; | ||
| 192 | reg = <0x50>; | ||
| 193 | }; | ||
| 194 | |||
| 195 | palmas: palmas@48 { | ||
| 196 | compatible = "ti,palmas"; | ||
| 197 | interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ | ||
| 198 | interrupt-parent = <&gic>; | ||
| 199 | reg = <0x48>; | ||
| 200 | interrupt-controller; | ||
| 201 | #interrupt-cells = <2>; | ||
| 202 | ti,system-power-controller; | ||
| 203 | |||
| 204 | extcon_usb3: palmas_usb { | ||
| 205 | compatible = "ti,palmas-usb-vid"; | ||
| 206 | ti,enable-vbus-detection; | ||
| 207 | ti,enable-id-detection; | ||
| 208 | ti,wakeup; | ||
| 209 | }; | ||
| 210 | |||
| 211 | rtc { | ||
| 212 | compatible = "ti,palmas-rtc"; | ||
| 213 | interrupt-parent = <&palmas>; | ||
| 214 | interrupts = <8 IRQ_TYPE_NONE>; | ||
| 215 | }; | ||
| 216 | |||
| 217 | palmas_pmic { | ||
| 218 | compatible = "ti,palmas-pmic"; | ||
| 219 | interrupt-parent = <&palmas>; | ||
| 220 | interrupts = <14 IRQ_TYPE_NONE>; | ||
| 221 | interrupt-name = "short-irq"; | ||
| 222 | |||
| 223 | ti,ldo6-vibrator; | ||
| 224 | |||
| 225 | regulators { | ||
| 226 | smps123_reg: smps123 { | ||
| 227 | /* VDD_OPP_MPU */ | ||
| 228 | regulator-name = "smps123"; | ||
| 229 | regulator-min-microvolt = < 600000>; | ||
| 230 | regulator-max-microvolt = <1500000>; | ||
| 231 | regulator-always-on; | ||
| 232 | regulator-boot-on; | ||
| 233 | }; | ||
| 234 | |||
| 235 | smps45_reg: smps45 { | ||
| 236 | /* VDD_OPP_MM */ | ||
| 237 | regulator-name = "smps45"; | ||
| 238 | regulator-min-microvolt = < 600000>; | ||
| 239 | regulator-max-microvolt = <1310000>; | ||
| 240 | regulator-always-on; | ||
| 241 | regulator-boot-on; | ||
| 242 | }; | ||
| 243 | |||
| 244 | smps6_reg: smps6 { | ||
| 245 | /* VDD_DDR3 - over VDD_SMPS6 */ | ||
| 246 | regulator-name = "smps6"; | ||
| 247 | regulator-min-microvolt = <1500000>; | ||
| 248 | regulator-max-microvolt = <1500000>; | ||
| 249 | regulator-always-on; | ||
| 250 | regulator-boot-on; | ||
| 251 | }; | ||
| 252 | |||
| 253 | smps7_reg: smps7 { | ||
| 254 | /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ | ||
| 255 | regulator-name = "smps7"; | ||
| 256 | regulator-min-microvolt = <1800000>; | ||
| 257 | regulator-max-microvolt = <1800000>; | ||
| 258 | regulator-always-on; | ||
| 259 | regulator-boot-on; | ||
| 260 | }; | ||
| 261 | |||
| 262 | smps8_reg: smps8 { | ||
| 263 | /* VDD_OPP_CORE */ | ||
| 264 | regulator-name = "smps8"; | ||
| 265 | regulator-min-microvolt = < 600000>; | ||
| 266 | regulator-max-microvolt = <1310000>; | ||
| 267 | regulator-always-on; | ||
| 268 | regulator-boot-on; | ||
| 269 | }; | ||
| 270 | |||
| 271 | smps9_reg: smps9 { | ||
| 272 | /* VDDA_2v1_AUD over VDD_2v1 */ | ||
| 273 | regulator-name = "smps9"; | ||
| 274 | regulator-min-microvolt = <3300000>; | ||
| 275 | regulator-max-microvolt = <3300000>; | ||
| 276 | ti,smps-range = <0x80>; | ||
| 277 | regulator-always-on; | ||
| 278 | regulator-boot-on; | ||
| 279 | }; | ||
| 280 | |||
| 281 | smps10_out2_reg: smps10_out2 { | ||
| 282 | /* VBUS_5V_OTG */ | ||
| 283 | regulator-name = "smps10_out2"; | ||
| 284 | regulator-min-microvolt = <5000000>; | ||
| 285 | regulator-max-microvolt = <5000000>; | ||
| 286 | regulator-always-on; | ||
| 287 | regulator-boot-on; | ||
| 288 | }; | ||
| 289 | |||
| 290 | smps10_out1_reg: smps10_out1 { | ||
| 291 | /* VBUS_5V_OTG */ | ||
| 292 | regulator-name = "smps10_out1"; | ||
| 293 | regulator-min-microvolt = <5000000>; | ||
| 294 | regulator-max-microvolt = <5000000>; | ||
| 295 | }; | ||
| 296 | |||
| 297 | ldo1_reg: ldo1 { | ||
| 298 | /* VDDAPHY_CAM: vdda_csiport */ | ||
| 299 | regulator-name = "ldo1"; | ||
| 300 | regulator-min-microvolt = <1500000>; | ||
| 301 | regulator-max-microvolt = <1800000>; | ||
| 302 | }; | ||
| 303 | |||
| 304 | ldo2_reg: ldo2 { | ||
| 305 | /* VDD_3V3_WLAN */ | ||
| 306 | regulator-name = "ldo2"; | ||
| 307 | regulator-min-microvolt = <3300000>; | ||
| 308 | regulator-max-microvolt = <3300000>; | ||
| 309 | startup-delay-us = <1000>; | ||
| 310 | }; | ||
| 311 | |||
| 312 | ldo3_reg: ldo3 { | ||
| 313 | /* VCC_1V5_AUD */ | ||
| 314 | regulator-name = "ldo3"; | ||
| 315 | regulator-min-microvolt = <1500000>; | ||
| 316 | regulator-max-microvolt = <1500000>; | ||
| 317 | regulator-always-on; | ||
| 318 | regulator-boot-on; | ||
| 319 | }; | ||
| 320 | |||
| 321 | ldo4_reg: ldo4 { | ||
| 322 | /* VDDAPHY_DISP: vdda_dsiport/hdmi */ | ||
| 323 | regulator-name = "ldo4"; | ||
| 324 | regulator-min-microvolt = <1500000>; | ||
| 325 | regulator-max-microvolt = <1800000>; | ||
| 326 | }; | ||
| 327 | |||
| 328 | ldo5_reg: ldo5 { | ||
| 329 | /* VDDA_1V8_PHY: usb/sata/hdmi.. */ | ||
| 330 | regulator-name = "ldo5"; | ||
| 331 | regulator-min-microvolt = <1800000>; | ||
| 332 | regulator-max-microvolt = <1800000>; | ||
| 333 | regulator-always-on; | ||
| 334 | regulator-boot-on; | ||
| 335 | }; | ||
| 336 | |||
| 337 | ldo6_reg: ldo6 { | ||
| 338 | /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ | ||
| 339 | regulator-name = "ldo6"; | ||
| 340 | regulator-min-microvolt = <1200000>; | ||
| 341 | regulator-max-microvolt = <1200000>; | ||
| 342 | regulator-always-on; | ||
| 343 | regulator-boot-on; | ||
| 344 | }; | ||
| 345 | |||
| 346 | ldo7_reg: ldo7 { | ||
| 347 | /* VDD_VPP: vpp1 */ | ||
| 348 | regulator-name = "ldo7"; | ||
| 349 | regulator-min-microvolt = <2000000>; | ||
| 350 | regulator-max-microvolt = <2000000>; | ||
| 351 | /* Only for efuse reprograming! */ | ||
| 352 | status = "disabled"; | ||
| 353 | }; | ||
| 354 | |||
| 355 | ldo8_reg: ldo8 { | ||
| 356 | /* VDD_3v0: Does not go anywhere */ | ||
| 357 | regulator-name = "ldo8"; | ||
| 358 | regulator-min-microvolt = <3000000>; | ||
| 359 | regulator-max-microvolt = <3000000>; | ||
| 360 | regulator-boot-on; | ||
| 361 | /* Unused */ | ||
| 362 | status = "disabled"; | ||
| 363 | }; | ||
| 364 | |||
| 365 | ldo9_reg: ldo9 { | ||
| 366 | /* VCC_DV_SDIO: vdds_sdcard */ | ||
| 367 | regulator-name = "ldo9"; | ||
| 368 | regulator-min-microvolt = <1800000>; | ||
| 369 | regulator-max-microvolt = <3000000>; | ||
| 370 | regulator-boot-on; | ||
| 371 | }; | ||
| 372 | |||
| 373 | ldoln_reg: ldoln { | ||
| 374 | /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ | ||
| 375 | regulator-name = "ldoln"; | ||
| 376 | regulator-min-microvolt = <1800000>; | ||
| 377 | regulator-max-microvolt = <1800000>; | ||
| 378 | regulator-always-on; | ||
| 379 | regulator-boot-on; | ||
| 380 | }; | ||
| 381 | |||
| 382 | ldousb_reg: ldousb { | ||
| 383 | /* VDDA_3V_USB: VDDA_USBHS33 */ | ||
| 384 | regulator-name = "ldousb"; | ||
| 385 | regulator-min-microvolt = <3250000>; | ||
| 386 | regulator-max-microvolt = <3250000>; | ||
| 387 | regulator-always-on; | ||
| 388 | regulator-boot-on; | ||
| 389 | }; | ||
| 390 | |||
| 391 | regen3_reg: regen3 { | ||
| 392 | /* REGEN3 controls LDO9 supply to card */ | ||
| 393 | regulator-name = "regen3"; | ||
| 394 | regulator-always-on; | ||
| 395 | regulator-boot-on; | ||
| 396 | }; | ||
| 397 | }; | ||
| 398 | }; | ||
| 399 | }; | ||
| 400 | }; | ||
| 401 | |||
| 402 | &usbhshost { | ||
| 403 | port2-mode = "ehci-hsic"; | ||
| 404 | port3-mode = "ehci-hsic"; | ||
| 405 | }; | ||
| 406 | |||
| 407 | &usbhsehci { | ||
| 408 | phys = <0 &hsusb2_phy &hsusb3_phy>; | ||
| 409 | }; | ||
| 410 | |||
| 411 | &cpu0 { | ||
| 412 | cpu0-supply = <&smps123_reg>; | ||
| 413 | }; | ||
diff --git a/arch/arm/boot/dts/omap5-sbc-t54.dts b/arch/arm/boot/dts/omap5-sbc-t54.dts new file mode 100644 index 000000000000..aa98fea3f2b3 --- /dev/null +++ b/arch/arm/boot/dts/omap5-sbc-t54.dts | |||
| @@ -0,0 +1,51 @@ | |||
| 1 | /* | ||
| 2 | * Suppport for CompuLab SBC-T54 with CM-T54 | ||
| 3 | */ | ||
| 4 | |||
| 5 | #include "omap5-cm-t54.dts" | ||
| 6 | |||
| 7 | / { | ||
| 8 | model = "CompuLab SBC-T54 with CM-T54"; | ||
| 9 | compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5"; | ||
| 10 | }; | ||
| 11 | |||
| 12 | &omap5_pmx_core { | ||
| 13 | i2c4_pins: pinmux_i2c4_pins { | ||
| 14 | pinctrl-single,pins = < | ||
| 15 | OMAP5_IOPAD(0x00f8, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ | ||
| 16 | OMAP5_IOPAD(0x00fa, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ | ||
| 17 | >; | ||
| 18 | }; | ||
| 19 | |||
| 20 | mmc1_aux_pins: pinmux_mmc1_aux_pins { | ||
| 21 | pinctrl-single,pins = < | ||
| 22 | OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_228 */ | ||
| 23 | OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_229 */ | ||
| 24 | >; | ||
| 25 | }; | ||
| 26 | }; | ||
| 27 | |||
| 28 | &mmc1 { | ||
| 29 | pinctrl-names = "default"; | ||
| 30 | pinctrl-0 = < | ||
| 31 | &mmc1_pins | ||
| 32 | &mmc1_aux_pins | ||
| 33 | >; | ||
| 34 | cd-inverted; | ||
| 35 | wp-inverted; | ||
| 36 | cd-gpios = <&gpio8 4 GPIO_ACTIVE_LOW>; /* gpio8_228 */ | ||
| 37 | wp-gpios = <&gpio8 5 GPIO_ACTIVE_LOW>; /* gpio8_229 */ | ||
| 38 | }; | ||
| 39 | |||
| 40 | &i2c4 { | ||
| 41 | pinctrl-names = "default"; | ||
| 42 | pinctrl-0 = <&i2c4_pins>; | ||
| 43 | |||
| 44 | clock-frequency = <400000>; | ||
| 45 | |||
| 46 | at24@50 { | ||
| 47 | compatible = "at24,24c02"; | ||
| 48 | pagesize = <16>; | ||
| 49 | reg = <0x50>; | ||
| 50 | }; | ||
| 51 | }; | ||
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 36b4312a5e0d..e58be57984ab 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi | |||
| @@ -82,6 +82,12 @@ | |||
| 82 | <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; | 82 | <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; |
| 83 | }; | 83 | }; |
| 84 | 84 | ||
| 85 | pmu { | ||
| 86 | compatible = "arm,cortex-a15-pmu"; | ||
| 87 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | ||
| 88 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; | ||
| 89 | }; | ||
| 90 | |||
| 85 | gic: interrupt-controller@48211000 { | 91 | gic: interrupt-controller@48211000 { |
| 86 | compatible = "arm,cortex-a15-gic"; | 92 | compatible = "arm,cortex-a15-gic"; |
| 87 | interrupt-controller; | 93 | interrupt-controller; |
| @@ -810,6 +816,8 @@ | |||
| 810 | compatible = "ti,omap-usb2"; | 816 | compatible = "ti,omap-usb2"; |
| 811 | reg = <0x4a084000 0x7c>; | 817 | reg = <0x4a084000 0x7c>; |
| 812 | ctrl-module = <&omap_control_usb2phy>; | 818 | ctrl-module = <&omap_control_usb2phy>; |
| 819 | clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; | ||
| 820 | clock-names = "wkupclk", "refclk"; | ||
| 813 | #phy-cells = <0>; | 821 | #phy-cells = <0>; |
| 814 | }; | 822 | }; |
| 815 | 823 | ||
| @@ -876,6 +884,46 @@ | |||
| 876 | 884 | ||
| 877 | #thermal-sensor-cells = <1>; | 885 | #thermal-sensor-cells = <1>; |
| 878 | }; | 886 | }; |
| 887 | |||
| 888 | omap_control_sata: control-phy@4a002374 { | ||
| 889 | compatible = "ti,control-phy-pipe3"; | ||
| 890 | reg = <0x4a002374 0x4>; | ||
| 891 | reg-names = "power"; | ||
| 892 | clocks = <&sys_clkin>; | ||
| 893 | clock-names = "sysclk"; | ||
| 894 | }; | ||
| 895 | |||
| 896 | /* OCP2SCP3 */ | ||
| 897 | ocp2scp@4a090000 { | ||
| 898 | compatible = "ti,omap-ocp2scp"; | ||
| 899 | #address-cells = <1>; | ||
| 900 | #size-cells = <1>; | ||
| 901 | reg = <0x4a090000 0x20>; | ||
| 902 | ranges; | ||
| 903 | ti,hwmods = "ocp2scp3"; | ||
| 904 | sata_phy: phy@4a096000 { | ||
| 905 | compatible = "ti,phy-pipe3-sata"; | ||
| 906 | reg = <0x4A096000 0x80>, /* phy_rx */ | ||
| 907 | <0x4A096400 0x64>, /* phy_tx */ | ||
| 908 | <0x4A096800 0x40>; /* pll_ctrl */ | ||
| 909 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | ||
| 910 | ctrl-module = <&omap_control_sata>; | ||
| 911 | clocks = <&sys_clkin>; | ||
| 912 | clock-names = "sysclk"; | ||
| 913 | #phy-cells = <0>; | ||
| 914 | }; | ||
| 915 | }; | ||
| 916 | |||
| 917 | sata: sata@4a141100 { | ||
| 918 | compatible = "snps,dwc-ahci"; | ||
| 919 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; | ||
| 920 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | ||
| 921 | phys = <&sata_phy>; | ||
| 922 | phy-names = "sata-phy"; | ||
| 923 | clocks = <&sata_ref_clk>; | ||
| 924 | ti,hwmods = "sata"; | ||
| 925 | }; | ||
| 926 | |||
| 879 | }; | 927 | }; |
| 880 | }; | 928 | }; |
| 881 | 929 | ||
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index d487fdab3921..aeb142ce8e9d 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi | |||
| @@ -120,10 +120,8 @@ | |||
| 120 | compatible = "ti,divider-clock"; | 120 | compatible = "ti,divider-clock"; |
| 121 | clocks = <&dpll_abe_x2_ck>; | 121 | clocks = <&dpll_abe_x2_ck>; |
| 122 | ti,max-div = <31>; | 122 | ti,max-div = <31>; |
| 123 | ti,autoidle-shift = <8>; | ||
| 124 | reg = <0x01f0>; | 123 | reg = <0x01f0>; |
| 125 | ti,index-starts-at-one; | 124 | ti,index-starts-at-one; |
| 126 | ti,invert-autoidle-bit; | ||
| 127 | }; | 125 | }; |
| 128 | 126 | ||
| 129 | abe_24m_fclk: abe_24m_fclk { | 127 | abe_24m_fclk: abe_24m_fclk { |
| @@ -145,10 +143,11 @@ | |||
| 145 | 143 | ||
| 146 | abe_iclk: abe_iclk { | 144 | abe_iclk: abe_iclk { |
| 147 | #clock-cells = <0>; | 145 | #clock-cells = <0>; |
| 148 | compatible = "fixed-factor-clock"; | 146 | compatible = "ti,divider-clock"; |
| 149 | clocks = <&abe_clk>; | 147 | clocks = <&aess_fclk>; |
| 150 | clock-mult = <1>; | 148 | ti,bit-shift = <24>; |
| 151 | clock-div = <2>; | 149 | reg = <0x0528>; |
| 150 | ti,dividers = <2>, <1>; | ||
| 152 | }; | 151 | }; |
| 153 | 152 | ||
| 154 | abe_lp_clk_div: abe_lp_clk_div { | 153 | abe_lp_clk_div: abe_lp_clk_div { |
| @@ -164,10 +163,8 @@ | |||
| 164 | compatible = "ti,divider-clock"; | 163 | compatible = "ti,divider-clock"; |
| 165 | clocks = <&dpll_abe_x2_ck>; | 164 | clocks = <&dpll_abe_x2_ck>; |
| 166 | ti,max-div = <31>; | 165 | ti,max-div = <31>; |
| 167 | ti,autoidle-shift = <8>; | ||
| 168 | reg = <0x01f4>; | 166 | reg = <0x01f4>; |
| 169 | ti,index-starts-at-one; | 167 | ti,index-starts-at-one; |
| 170 | ti,invert-autoidle-bit; | ||
| 171 | }; | 168 | }; |
| 172 | 169 | ||
| 173 | dpll_core_ck: dpll_core_ck { | 170 | dpll_core_ck: dpll_core_ck { |
| @@ -188,10 +185,8 @@ | |||
| 188 | compatible = "ti,divider-clock"; | 185 | compatible = "ti,divider-clock"; |
| 189 | clocks = <&dpll_core_x2_ck>; | 186 | clocks = <&dpll_core_x2_ck>; |
| 190 | ti,max-div = <63>; | 187 | ti,max-div = <63>; |
| 191 | ti,autoidle-shift = <8>; | ||
| 192 | reg = <0x0150>; | 188 | reg = <0x0150>; |
| 193 | ti,index-starts-at-one; | 189 | ti,index-starts-at-one; |
| 194 | ti,invert-autoidle-bit; | ||
| 195 | }; | 190 | }; |
| 196 | 191 | ||
| 197 | c2c_fclk: c2c_fclk { | 192 | c2c_fclk: c2c_fclk { |
| @@ -215,10 +210,8 @@ | |||
| 215 | compatible = "ti,divider-clock"; | 210 | compatible = "ti,divider-clock"; |
| 216 | clocks = <&dpll_core_x2_ck>; | 211 | clocks = <&dpll_core_x2_ck>; |
| 217 | ti,max-div = <63>; | 212 | ti,max-div = <63>; |
| 218 | ti,autoidle-shift = <8>; | ||
| 219 | reg = <0x0138>; | 213 | reg = <0x0138>; |
| 220 | ti,index-starts-at-one; | 214 | ti,index-starts-at-one; |
| 221 | ti,invert-autoidle-bit; | ||
| 222 | }; | 215 | }; |
| 223 | 216 | ||
| 224 | dpll_core_h12x2_ck: dpll_core_h12x2_ck { | 217 | dpll_core_h12x2_ck: dpll_core_h12x2_ck { |
| @@ -226,10 +219,8 @@ | |||
| 226 | compatible = "ti,divider-clock"; | 219 | compatible = "ti,divider-clock"; |
| 227 | clocks = <&dpll_core_x2_ck>; | 220 | clocks = <&dpll_core_x2_ck>; |
| 228 | ti,max-div = <63>; | 221 | ti,max-div = <63>; |
| 229 | ti,autoidle-shift = <8>; | ||
| 230 | reg = <0x013c>; | 222 | reg = <0x013c>; |
| 231 | ti,index-starts-at-one; | 223 | ti,index-starts-at-one; |
| 232 | ti,invert-autoidle-bit; | ||
| 233 | }; | 224 | }; |
| 234 | 225 | ||
| 235 | dpll_core_h13x2_ck: dpll_core_h13x2_ck { | 226 | dpll_core_h13x2_ck: dpll_core_h13x2_ck { |
| @@ -237,10 +228,8 @@ | |||
| 237 | compatible = "ti,divider-clock"; | 228 | compatible = "ti,divider-clock"; |
| 238 | clocks = <&dpll_core_x2_ck>; | 229 | clocks = <&dpll_core_x2_ck>; |
| 239 | ti,max-div = <63>; | 230 | ti,max-div = <63>; |
| 240 | ti,autoidle-shift = <8>; | ||
| 241 | reg = <0x0140>; | 231 | reg = <0x0140>; |
| 242 | ti,index-starts-at-one; | 232 | ti,index-starts-at-one; |
| 243 | ti,invert-autoidle-bit; | ||
| 244 | }; | 233 | }; |
| 245 | 234 | ||
| 246 | dpll_core_h14x2_ck: dpll_core_h14x2_ck { | 235 | dpll_core_h14x2_ck: dpll_core_h14x2_ck { |
| @@ -248,10 +237,8 @@ | |||
| 248 | compatible = "ti,divider-clock"; | 237 | compatible = "ti,divider-clock"; |
| 249 | clocks = <&dpll_core_x2_ck>; | 238 | clocks = <&dpll_core_x2_ck>; |
| 250 | ti,max-div = <63>; | 239 | ti,max-div = <63>; |
| 251 | ti,autoidle-shift = <8>; | ||
| 252 | reg = <0x0144>; | 240 | reg = <0x0144>; |
| 253 | ti,index-starts-at-one; | 241 | ti,index-starts-at-one; |
| 254 | ti,invert-autoidle-bit; | ||
| 255 | }; | 242 | }; |
| 256 | 243 | ||
| 257 | dpll_core_h22x2_ck: dpll_core_h22x2_ck { | 244 | dpll_core_h22x2_ck: dpll_core_h22x2_ck { |
| @@ -259,10 +246,8 @@ | |||
| 259 | compatible = "ti,divider-clock"; | 246 | compatible = "ti,divider-clock"; |
| 260 | clocks = <&dpll_core_x2_ck>; | 247 | clocks = <&dpll_core_x2_ck>; |
| 261 | ti,max-div = <63>; | 248 | ti,max-div = <63>; |
| 262 | ti,autoidle-shift = <8>; | ||
| 263 | reg = <0x0154>; | 249 | reg = <0x0154>; |
| 264 | ti,index-starts-at-one; | 250 | ti,index-starts-at-one; |
| 265 | ti,invert-autoidle-bit; | ||
| 266 | }; | 251 | }; |
| 267 | 252 | ||
| 268 | dpll_core_h23x2_ck: dpll_core_h23x2_ck { | 253 | dpll_core_h23x2_ck: dpll_core_h23x2_ck { |
| @@ -270,10 +255,8 @@ | |||
| 270 | compatible = "ti,divider-clock"; | 255 | compatible = "ti,divider-clock"; |
| 271 | clocks = <&dpll_core_x2_ck>; | 256 | clocks = <&dpll_core_x2_ck>; |
| 272 | ti,max-div = <63>; | 257 | ti,max-div = <63>; |
| 273 | ti,autoidle-shift = <8>; | ||
| 274 | reg = <0x0158>; | 258 | reg = <0x0158>; |
| 275 | ti,index-starts-at-one; | 259 | ti,index-starts-at-one; |
| 276 | ti,invert-autoidle-bit; | ||
| 277 | }; | 260 | }; |
| 278 | 261 | ||
| 279 | dpll_core_h24x2_ck: dpll_core_h24x2_ck { | 262 | dpll_core_h24x2_ck: dpll_core_h24x2_ck { |
| @@ -281,10 +264,8 @@ | |||
| 281 | compatible = "ti,divider-clock"; | 264 | compatible = "ti,divider-clock"; |
| 282 | clocks = <&dpll_core_x2_ck>; | 265 | clocks = <&dpll_core_x2_ck>; |
| 283 | ti,max-div = <63>; | 266 | ti,max-div = <63>; |
| 284 | ti,autoidle-shift = <8>; | ||
| 285 | reg = <0x015c>; | 267 | reg = <0x015c>; |
| 286 | ti,index-starts-at-one; | 268 | ti,index-starts-at-one; |
| 287 | ti,invert-autoidle-bit; | ||
| 288 | }; | 269 | }; |
| 289 | 270 | ||
| 290 | dpll_core_m2_ck: dpll_core_m2_ck { | 271 | dpll_core_m2_ck: dpll_core_m2_ck { |
| @@ -292,10 +273,8 @@ | |||
| 292 | compatible = "ti,divider-clock"; | 273 | compatible = "ti,divider-clock"; |
| 293 | clocks = <&dpll_core_ck>; | 274 | clocks = <&dpll_core_ck>; |
| 294 | ti,max-div = <31>; | 275 | ti,max-div = <31>; |
| 295 | ti,autoidle-shift = <8>; | ||
| 296 | reg = <0x0130>; | 276 | reg = <0x0130>; |
| 297 | ti,index-starts-at-one; | 277 | ti,index-starts-at-one; |
| 298 | ti,invert-autoidle-bit; | ||
| 299 | }; | 278 | }; |
| 300 | 279 | ||
| 301 | dpll_core_m3x2_ck: dpll_core_m3x2_ck { | 280 | dpll_core_m3x2_ck: dpll_core_m3x2_ck { |
| @@ -303,10 +282,8 @@ | |||
| 303 | compatible = "ti,divider-clock"; | 282 | compatible = "ti,divider-clock"; |
| 304 | clocks = <&dpll_core_x2_ck>; | 283 | clocks = <&dpll_core_x2_ck>; |
| 305 | ti,max-div = <31>; | 284 | ti,max-div = <31>; |
| 306 | ti,autoidle-shift = <8>; | ||
| 307 | reg = <0x0134>; | 285 | reg = <0x0134>; |
| 308 | ti,index-starts-at-one; | 286 | ti,index-starts-at-one; |
| 309 | ti,invert-autoidle-bit; | ||
| 310 | }; | 287 | }; |
| 311 | 288 | ||
| 312 | iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { | 289 | iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { |
| @@ -335,10 +312,8 @@ | |||
| 335 | compatible = "ti,divider-clock"; | 312 | compatible = "ti,divider-clock"; |
| 336 | clocks = <&dpll_iva_x2_ck>; | 313 | clocks = <&dpll_iva_x2_ck>; |
| 337 | ti,max-div = <63>; | 314 | ti,max-div = <63>; |
| 338 | ti,autoidle-shift = <8>; | ||
| 339 | reg = <0x01b8>; | 315 | reg = <0x01b8>; |
| 340 | ti,index-starts-at-one; | 316 | ti,index-starts-at-one; |
| 341 | ti,invert-autoidle-bit; | ||
| 342 | }; | 317 | }; |
| 343 | 318 | ||
| 344 | dpll_iva_h12x2_ck: dpll_iva_h12x2_ck { | 319 | dpll_iva_h12x2_ck: dpll_iva_h12x2_ck { |
| @@ -346,10 +321,8 @@ | |||
| 346 | compatible = "ti,divider-clock"; | 321 | compatible = "ti,divider-clock"; |
| 347 | clocks = <&dpll_iva_x2_ck>; | 322 | clocks = <&dpll_iva_x2_ck>; |
| 348 | ti,max-div = <63>; | 323 | ti,max-div = <63>; |
| 349 | ti,autoidle-shift = <8>; | ||
| 350 | reg = <0x01bc>; | 324 | reg = <0x01bc>; |
| 351 | ti,index-starts-at-one; | 325 | ti,index-starts-at-one; |
| 352 | ti,invert-autoidle-bit; | ||
| 353 | }; | 326 | }; |
| 354 | 327 | ||
| 355 | mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { | 328 | mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { |
| @@ -372,10 +345,8 @@ | |||
| 372 | compatible = "ti,divider-clock"; | 345 | compatible = "ti,divider-clock"; |
| 373 | clocks = <&dpll_mpu_ck>; | 346 | clocks = <&dpll_mpu_ck>; |
| 374 | ti,max-div = <31>; | 347 | ti,max-div = <31>; |
| 375 | ti,autoidle-shift = <8>; | ||
| 376 | reg = <0x0170>; | 348 | reg = <0x0170>; |
| 377 | ti,index-starts-at-one; | 349 | ti,index-starts-at-one; |
| 378 | ti,invert-autoidle-bit; | ||
| 379 | }; | 350 | }; |
| 380 | 351 | ||
| 381 | per_dpll_hs_clk_div: per_dpll_hs_clk_div { | 352 | per_dpll_hs_clk_div: per_dpll_hs_clk_div { |
| @@ -642,10 +613,8 @@ | |||
| 642 | compatible = "ti,divider-clock"; | 613 | compatible = "ti,divider-clock"; |
| 643 | clocks = <&dpll_per_x2_ck>; | 614 | clocks = <&dpll_per_x2_ck>; |
| 644 | ti,max-div = <63>; | 615 | ti,max-div = <63>; |
| 645 | ti,autoidle-shift = <8>; | ||
| 646 | reg = <0x0158>; | 616 | reg = <0x0158>; |
| 647 | ti,index-starts-at-one; | 617 | ti,index-starts-at-one; |
| 648 | ti,invert-autoidle-bit; | ||
| 649 | }; | 618 | }; |
| 650 | 619 | ||
| 651 | dpll_per_h12x2_ck: dpll_per_h12x2_ck { | 620 | dpll_per_h12x2_ck: dpll_per_h12x2_ck { |
| @@ -653,10 +622,8 @@ | |||
| 653 | compatible = "ti,divider-clock"; | 622 | compatible = "ti,divider-clock"; |
| 654 | clocks = <&dpll_per_x2_ck>; | 623 | clocks = <&dpll_per_x2_ck>; |
| 655 | ti,max-div = <63>; | 624 | ti,max-div = <63>; |
| 656 | ti,autoidle-shift = <8>; | ||
| 657 | reg = <0x015c>; | 625 | reg = <0x015c>; |
| 658 | ti,index-starts-at-one; | 626 | ti,index-starts-at-one; |
| 659 | ti,invert-autoidle-bit; | ||
| 660 | }; | 627 | }; |
| 661 | 628 | ||
| 662 | dpll_per_h14x2_ck: dpll_per_h14x2_ck { | 629 | dpll_per_h14x2_ck: dpll_per_h14x2_ck { |
| @@ -664,10 +631,8 @@ | |||
| 664 | compatible = "ti,divider-clock"; | 631 | compatible = "ti,divider-clock"; |
| 665 | clocks = <&dpll_per_x2_ck>; | 632 | clocks = <&dpll_per_x2_ck>; |
| 666 | ti,max-div = <63>; | 633 | ti,max-div = <63>; |
| 667 | ti,autoidle-shift = <8>; | ||
| 668 | reg = <0x0164>; | 634 | reg = <0x0164>; |
| 669 | ti,index-starts-at-one; | 635 | ti,index-starts-at-one; |
| 670 | ti,invert-autoidle-bit; | ||
| 671 | }; | 636 | }; |
| 672 | 637 | ||
| 673 | dpll_per_m2_ck: dpll_per_m2_ck { | 638 | dpll_per_m2_ck: dpll_per_m2_ck { |
| @@ -675,10 +640,8 @@ | |||
| 675 | compatible = "ti,divider-clock"; | 640 | compatible = "ti,divider-clock"; |
| 676 | clocks = <&dpll_per_ck>; | 641 | clocks = <&dpll_per_ck>; |
| 677 | ti,max-div = <31>; | 642 | ti,max-div = <31>; |
| 678 | ti,autoidle-shift = <8>; | ||
| 679 | reg = <0x0150>; | 643 | reg = <0x0150>; |
| 680 | ti,index-starts-at-one; | 644 | ti,index-starts-at-one; |
| 681 | ti,invert-autoidle-bit; | ||
| 682 | }; | 645 | }; |
| 683 | 646 | ||
| 684 | dpll_per_m2x2_ck: dpll_per_m2x2_ck { | 647 | dpll_per_m2x2_ck: dpll_per_m2x2_ck { |
| @@ -686,10 +649,8 @@ | |||
| 686 | compatible = "ti,divider-clock"; | 649 | compatible = "ti,divider-clock"; |
| 687 | clocks = <&dpll_per_x2_ck>; | 650 | clocks = <&dpll_per_x2_ck>; |
| 688 | ti,max-div = <31>; | 651 | ti,max-div = <31>; |
| 689 | ti,autoidle-shift = <8>; | ||
| 690 | reg = <0x0150>; | 652 | reg = <0x0150>; |
| 691 | ti,index-starts-at-one; | 653 | ti,index-starts-at-one; |
| 692 | ti,invert-autoidle-bit; | ||
| 693 | }; | 654 | }; |
| 694 | 655 | ||
| 695 | dpll_per_m3x2_ck: dpll_per_m3x2_ck { | 656 | dpll_per_m3x2_ck: dpll_per_m3x2_ck { |
| @@ -697,10 +658,8 @@ | |||
| 697 | compatible = "ti,divider-clock"; | 658 | compatible = "ti,divider-clock"; |
| 698 | clocks = <&dpll_per_x2_ck>; | 659 | clocks = <&dpll_per_x2_ck>; |
| 699 | ti,max-div = <31>; | 660 | ti,max-div = <31>; |
| 700 | ti,autoidle-shift = <8>; | ||
| 701 | reg = <0x0154>; | 661 | reg = <0x0154>; |
| 702 | ti,index-starts-at-one; | 662 | ti,index-starts-at-one; |
| 703 | ti,invert-autoidle-bit; | ||
| 704 | }; | 663 | }; |
| 705 | 664 | ||
| 706 | dpll_unipro1_ck: dpll_unipro1_ck { | 665 | dpll_unipro1_ck: dpll_unipro1_ck { |
| @@ -723,10 +682,8 @@ | |||
| 723 | compatible = "ti,divider-clock"; | 682 | compatible = "ti,divider-clock"; |
| 724 | clocks = <&dpll_unipro1_ck>; | 683 | clocks = <&dpll_unipro1_ck>; |
| 725 | ti,max-div = <127>; | 684 | ti,max-div = <127>; |
| 726 | ti,autoidle-shift = <8>; | ||
| 727 | reg = <0x0210>; | 685 | reg = <0x0210>; |
| 728 | ti,index-starts-at-one; | 686 | ti,index-starts-at-one; |
| 729 | ti,invert-autoidle-bit; | ||
| 730 | }; | 687 | }; |
| 731 | 688 | ||
| 732 | dpll_unipro2_ck: dpll_unipro2_ck { | 689 | dpll_unipro2_ck: dpll_unipro2_ck { |
| @@ -749,10 +706,8 @@ | |||
| 749 | compatible = "ti,divider-clock"; | 706 | compatible = "ti,divider-clock"; |
| 750 | clocks = <&dpll_unipro2_ck>; | 707 | clocks = <&dpll_unipro2_ck>; |
| 751 | ti,max-div = <127>; | 708 | ti,max-div = <127>; |
| 752 | ti,autoidle-shift = <8>; | ||
| 753 | reg = <0x01d0>; | 709 | reg = <0x01d0>; |
| 754 | ti,index-starts-at-one; | 710 | ti,index-starts-at-one; |
| 755 | ti,invert-autoidle-bit; | ||
| 756 | }; | 711 | }; |
| 757 | 712 | ||
| 758 | dpll_usb_ck: dpll_usb_ck { | 713 | dpll_usb_ck: dpll_usb_ck { |
| @@ -775,10 +730,8 @@ | |||
| 775 | compatible = "ti,divider-clock"; | 730 | compatible = "ti,divider-clock"; |
| 776 | clocks = <&dpll_usb_ck>; | 731 | clocks = <&dpll_usb_ck>; |
| 777 | ti,max-div = <127>; | 732 | ti,max-div = <127>; |
| 778 | ti,autoidle-shift = <8>; | ||
| 779 | reg = <0x0190>; | 733 | reg = <0x0190>; |
| 780 | ti,index-starts-at-one; | 734 | ti,index-starts-at-one; |
| 781 | ti,invert-autoidle-bit; | ||
| 782 | }; | 735 | }; |
| 783 | 736 | ||
| 784 | func_128m_clk: func_128m_clk { | 737 | func_128m_clk: func_128m_clk { |
| @@ -851,6 +804,7 @@ | |||
| 851 | clocks = <&dpll_per_h12x2_ck>; | 804 | clocks = <&dpll_per_h12x2_ck>; |
| 852 | ti,bit-shift = <8>; | 805 | ti,bit-shift = <8>; |
| 853 | reg = <0x1420>; | 806 | reg = <0x1420>; |
| 807 | ti,set-rate-parent; | ||
| 854 | }; | 808 | }; |
| 855 | 809 | ||
| 856 | dss_sys_clk: dss_sys_clk { | 810 | dss_sys_clk: dss_sys_clk { |
diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts new file mode 100644 index 000000000000..c701e8d16bbb --- /dev/null +++ b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts | |||
| @@ -0,0 +1,236 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
| 3 | * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include <dt-bindings/gpio/gpio.h> | ||
| 13 | #include <dt-bindings/input/input.h> | ||
| 14 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 15 | #include "orion5x-mv88f5182.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | model = "LaCie d2 Network"; | ||
| 19 | compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x"; | ||
| 20 | |||
| 21 | memory { | ||
| 22 | reg = <0x00000000 0x4000000>; /* 64 MB */ | ||
| 23 | }; | ||
| 24 | |||
| 25 | chosen { | ||
| 26 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | ||
| 27 | linux,stdout-path = &uart0; | ||
| 28 | }; | ||
| 29 | |||
| 30 | soc { | ||
| 31 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, | ||
| 32 | <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, | ||
| 33 | <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>; | ||
| 34 | }; | ||
| 35 | |||
| 36 | gpio-keys { | ||
| 37 | compatible = "gpio-keys"; | ||
| 38 | pinctrl-0 = <&pmx_buttons>; | ||
| 39 | pinctrl-names = "default"; | ||
| 40 | #address-cells = <1>; | ||
| 41 | #size-cells = <0>; | ||
| 42 | front_button { | ||
| 43 | label = "Front Push Button"; | ||
| 44 | linux,code = <KEY_POWER>; | ||
| 45 | gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; | ||
| 46 | }; | ||
| 47 | |||
| 48 | power_rocker_sw_on { | ||
| 49 | label = "Power rocker switch (on|auto)"; | ||
| 50 | linux,input-type = <5>; /* EV_SW */ | ||
| 51 | linux,code = <1>; /* D2NET_SWITCH_POWER_ON */ | ||
| 52 | gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; | ||
| 53 | }; | ||
| 54 | |||
| 55 | power_rocker_sw_off { | ||
| 56 | label = "Power rocker switch (auto|off)"; | ||
| 57 | linux,input-type = <5>; /* EV_SW */ | ||
| 58 | linux,code = <2>; /* D2NET_SWITCH_POWER_OFF */ | ||
| 59 | gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; | ||
| 60 | }; | ||
| 61 | }; | ||
| 62 | |||
| 63 | regulators { | ||
| 64 | compatible = "simple-bus"; | ||
| 65 | #address-cells = <1>; | ||
| 66 | #size-cells = <0>; | ||
| 67 | pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power>; | ||
| 68 | pinctrl-names = "default"; | ||
| 69 | |||
| 70 | sata0_power: regulator@0 { | ||
| 71 | compatible = "regulator-fixed"; | ||
| 72 | reg = <0>; | ||
| 73 | regulator-name = "SATA0 Power"; | ||
| 74 | regulator-min-microvolt = <5000000>; | ||
| 75 | regulator-max-microvolt = <5000000>; | ||
| 76 | enable-active-high; | ||
| 77 | regulator-always-on; | ||
| 78 | regulator-boot-on; | ||
| 79 | gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; | ||
| 80 | }; | ||
| 81 | |||
| 82 | sata1_power: regulator@1 { | ||
| 83 | compatible = "regulator-fixed"; | ||
| 84 | reg = <1>; | ||
| 85 | regulator-name = "SATA1 Power"; | ||
| 86 | regulator-min-microvolt = <5000000>; | ||
| 87 | regulator-max-microvolt = <5000000>; | ||
| 88 | enable-active-high; | ||
| 89 | regulator-always-on; | ||
| 90 | regulator-boot-on; | ||
| 91 | gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; | ||
| 92 | }; | ||
| 93 | }; | ||
| 94 | }; | ||
| 95 | |||
| 96 | &devbus_bootcs { | ||
| 97 | status = "okay"; | ||
| 98 | |||
| 99 | devbus,keep-config; | ||
| 100 | |||
| 101 | /* | ||
| 102 | * Currently the MTD code does not recognize the MX29LV400CBCT | ||
| 103 | * as a bottom-type device. This could cause risks of | ||
| 104 | * accidentally erasing critical flash sectors. We thus define | ||
| 105 | * a single, write-protected partition covering the whole | ||
| 106 | * flash. TODO: once the flash part TOP/BOTTOM detection | ||
| 107 | * issue is sorted out in the MTD code, break this into at | ||
| 108 | * least three partitions: 'u-boot code', 'u-boot environment' | ||
| 109 | * and 'whatever is left'. | ||
| 110 | */ | ||
| 111 | flash@0 { | ||
| 112 | compatible = "cfi-flash"; | ||
| 113 | reg = <0 0x80000>; | ||
| 114 | bank-width = <1>; | ||
| 115 | #address-cells = <1>; | ||
| 116 | #size-cells = <1>; | ||
| 117 | |||
| 118 | partition@0 { | ||
| 119 | label = "Full512Kb"; | ||
| 120 | reg = <0 0x80000>; | ||
| 121 | read-only; | ||
| 122 | }; | ||
| 123 | }; | ||
| 124 | }; | ||
| 125 | |||
| 126 | &mdio { | ||
| 127 | status = "okay"; | ||
| 128 | |||
| 129 | ethphy: ethernet-phy { | ||
| 130 | reg = <8>; | ||
| 131 | }; | ||
| 132 | }; | ||
| 133 | |||
| 134 | &ehci0 { | ||
| 135 | status = "okay"; | ||
| 136 | }; | ||
| 137 | |||
| 138 | ð { | ||
| 139 | status = "okay"; | ||
| 140 | |||
| 141 | ethernet-port@0 { | ||
| 142 | phy-handle = <ðphy>; | ||
| 143 | }; | ||
| 144 | }; | ||
| 145 | |||
| 146 | &i2c { | ||
| 147 | status = "okay"; | ||
| 148 | clock-frequency = <100000>; | ||
| 149 | #address-cells = <1>; | ||
| 150 | |||
| 151 | rtc@32 { | ||
| 152 | compatible = "ricoh,rs5c372b"; | ||
| 153 | reg = <0x32>; | ||
| 154 | }; | ||
| 155 | |||
| 156 | fan@3e { | ||
| 157 | compatible = "gmt,g762"; | ||
| 158 | reg = <0x3e>; | ||
| 159 | |||
| 160 | /* Not enough HW info */ | ||
| 161 | status = "disabled"; | ||
| 162 | }; | ||
| 163 | |||
| 164 | eeprom@50 { | ||
| 165 | compatible = "atmel,24c08"; | ||
| 166 | reg = <0x50>; | ||
| 167 | }; | ||
| 168 | }; | ||
| 169 | |||
| 170 | &pinctrl { | ||
| 171 | pinctrl-0 = <&pmx_leds &pmx_board_id &pmx_fan_fail>; | ||
| 172 | pinctrl-names = "default"; | ||
| 173 | |||
| 174 | pmx_board_id: pmx-board-id { | ||
| 175 | marvell,pins = "mpp0", "mpp1", "mpp2"; | ||
| 176 | marvell,function = "gpio"; | ||
| 177 | }; | ||
| 178 | |||
| 179 | pmx_buttons: pmx-buttons { | ||
| 180 | marvell,pins = "mpp8", "mpp9", "mpp18"; | ||
| 181 | marvell,function = "gpio"; | ||
| 182 | }; | ||
| 183 | |||
| 184 | pmx_fan_fail: pmx-fan-fail { | ||
| 185 | marvell,pins = "mpp5"; | ||
| 186 | marvell,function = "gpio"; | ||
| 187 | }; | ||
| 188 | |||
| 189 | /* | ||
| 190 | * MPP6: Red front LED | ||
| 191 | * MPP16: Blue front LED blink control | ||
| 192 | */ | ||
| 193 | pmx_leds: pmx-leds { | ||
| 194 | marvell,pins = "mpp6", "mpp16"; | ||
| 195 | marvell,function = "gpio"; | ||
| 196 | }; | ||
| 197 | |||
| 198 | pmx_sata0_led_active: pmx-sata0-led-active { | ||
| 199 | marvell,pins = "mpp14"; | ||
| 200 | marvell,function = "sata0"; | ||
| 201 | }; | ||
| 202 | |||
| 203 | pmx_sata0_power: pmx-sata0-power { | ||
| 204 | marvell,pins = "mpp3"; | ||
| 205 | marvell,function = "gpio"; | ||
| 206 | }; | ||
| 207 | |||
| 208 | pmx_sata1_led_active: pmx-sata1-led-active { | ||
| 209 | marvell,pins = "mpp15"; | ||
| 210 | marvell,function = "sata1"; | ||
| 211 | }; | ||
| 212 | |||
| 213 | pmx_sata1_power: pmx-sata1-power { | ||
| 214 | marvell,pins = "mpp12"; | ||
| 215 | marvell,function = "gpio"; | ||
| 216 | }; | ||
| 217 | |||
| 218 | /* | ||
| 219 | * Non MPP GPIOs: | ||
| 220 | * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok) | ||
| 221 | * GPIO 23: Blue front LED off | ||
| 222 | * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled) | ||
| 223 | */ | ||
| 224 | }; | ||
| 225 | |||
| 226 | &sata { | ||
| 227 | pinctrl-0 = <&pmx_sata0_led_active | ||
| 228 | &pmx_sata1_led_active>; | ||
| 229 | pinctrl-names = "default"; | ||
| 230 | status = "okay"; | ||
| 231 | nr-ports = <2>; | ||
| 232 | }; | ||
| 233 | |||
| 234 | &uart0 { | ||
| 235 | status = "okay"; | ||
| 236 | }; | ||
diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index 5ed6c1376901..89ff404a528c 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | |||
| @@ -6,8 +6,19 @@ | |||
| 6 | * warranty of any kind, whether express or implied. | 6 | * warranty of any kind, whether express or implied. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* | ||
| 10 | * TODO: add Orion USB device port init when kernel.org support is added. | ||
| 11 | * TODO: add flash write support: see below. | ||
| 12 | * TODO: add power-off support. | ||
| 13 | * TODO: add I2C EEPROM support. | ||
| 14 | */ | ||
| 15 | |||
| 9 | /dts-v1/; | 16 | /dts-v1/; |
| 10 | /include/ "orion5x.dtsi" | 17 | |
| 18 | #include <dt-bindings/gpio/gpio.h> | ||
| 19 | #include <dt-bindings/input/input.h> | ||
| 20 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 21 | #include "orion5x-mv88f5182.dtsi" | ||
| 11 | 22 | ||
| 12 | / { | 23 | / { |
| 13 | model = "LaCie Ethernet Disk mini V2"; | 24 | model = "LaCie Ethernet Disk mini V2"; |
| @@ -19,49 +30,84 @@ | |||
| 19 | 30 | ||
| 20 | chosen { | 31 | chosen { |
| 21 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 32 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 33 | linux,stdout-path = &uart0; | ||
| 22 | }; | 34 | }; |
| 23 | 35 | ||
| 24 | ocp@f1000000 { | 36 | soc { |
| 25 | serial@12000 { | 37 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, |
| 26 | clock-frequency = <166666667>; | 38 | <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, |
| 27 | status = "okay"; | 39 | <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>; |
| 28 | }; | ||
| 29 | |||
| 30 | sata@80000 { | ||
| 31 | status = "okay"; | ||
| 32 | nr-ports = <2>; | ||
| 33 | }; | ||
| 34 | }; | 40 | }; |
| 35 | 41 | ||
| 36 | gpio_keys { | 42 | gpio-keys { |
| 37 | compatible = "gpio-keys"; | 43 | compatible = "gpio-keys"; |
| 44 | pinctrl-0 = <&pmx_power_button>; | ||
| 45 | pinctrl-names = "default"; | ||
| 38 | #address-cells = <1>; | 46 | #address-cells = <1>; |
| 39 | #size-cells = <0>; | 47 | #size-cells = <0>; |
| 40 | button@1 { | 48 | button@1 { |
| 41 | label = "Power-on Switch"; | 49 | label = "Power-on Switch"; |
| 42 | linux,code = <116>; /* KEY_POWER */ | 50 | linux,code = <KEY_POWER>; |
| 43 | gpios = <&gpio0 18 0>; | 51 | gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; |
| 44 | }; | 52 | }; |
| 45 | }; | 53 | }; |
| 46 | 54 | ||
| 47 | gpio_leds { | 55 | gpio-leds { |
| 48 | compatible = "gpio-leds"; | 56 | compatible = "gpio-leds"; |
| 57 | pinctrl-0 = <&pmx_power_led>; | ||
| 58 | pinctrl-names = "default"; | ||
| 49 | 59 | ||
| 50 | led@1 { | 60 | led@1 { |
| 51 | label = "power:blue"; | 61 | label = "power:blue"; |
| 52 | gpios = <&gpio0 16 1>; | 62 | gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; |
| 53 | }; | 63 | }; |
| 54 | }; | 64 | }; |
| 55 | }; | 65 | }; |
| 56 | 66 | ||
| 57 | &mdio { | 67 | &devbus_bootcs { |
| 58 | status = "okay"; | 68 | status = "okay"; |
| 59 | 69 | ||
| 60 | ethphy: ethernet-phy { | 70 | /* Read parameters */ |
| 61 | reg = <8>; | 71 | devbus,bus-width = <8>; |
| 72 | devbus,turn-off-ps = <90000>; | ||
| 73 | devbus,badr-skew-ps = <0>; | ||
| 74 | devbus,acc-first-ps = <186000>; | ||
| 75 | devbus,acc-next-ps = <186000>; | ||
| 76 | |||
| 77 | /* Write parameters */ | ||
| 78 | devbus,wr-high-ps = <90000>; | ||
| 79 | devbus,wr-low-ps = <90000>; | ||
| 80 | devbus,ale-wr-ps = <90000>; | ||
| 81 | |||
| 82 | /* | ||
| 83 | * Currently the MTD code does not recognize the MX29LV400CBCT | ||
| 84 | * as a bottom-type device. This could cause risks of | ||
| 85 | * accidentally erasing critical flash sectors. We thus define | ||
| 86 | * a single, write-protected partition covering the whole | ||
| 87 | * flash. TODO: once the flash part TOP/BOTTOM detection | ||
| 88 | * issue is sorted out in the MTD code, break this into at | ||
| 89 | * least three partitions: 'u-boot code', 'u-boot environment' | ||
| 90 | * and 'whatever is left'. | ||
| 91 | */ | ||
| 92 | flash@0 { | ||
| 93 | compatible = "cfi-flash"; | ||
| 94 | reg = <0 0x80000>; | ||
| 95 | bank-width = <1>; | ||
| 96 | #address-cells = <1>; | ||
| 97 | #size-cells = <1>; | ||
| 98 | |||
| 99 | partition@0 { | ||
| 100 | label = "Full512Kb"; | ||
| 101 | reg = <0 0x80000>; | ||
| 102 | read-only; | ||
| 103 | }; | ||
| 62 | }; | 104 | }; |
| 63 | }; | 105 | }; |
| 64 | 106 | ||
| 107 | &ehci0 { | ||
| 108 | status = "okay"; | ||
| 109 | }; | ||
| 110 | |||
| 65 | ð { | 111 | ð { |
| 66 | status = "okay"; | 112 | status = "okay"; |
| 67 | 113 | ||
| @@ -69,3 +115,60 @@ | |||
| 69 | phy-handle = <ðphy>; | 115 | phy-handle = <ðphy>; |
| 70 | }; | 116 | }; |
| 71 | }; | 117 | }; |
| 118 | |||
| 119 | &i2c { | ||
| 120 | status = "okay"; | ||
| 121 | clock-frequency = <100000>; | ||
| 122 | #address-cells = <1>; | ||
| 123 | |||
| 124 | rtc@32 { | ||
| 125 | compatible = "ricoh,rs5c372a"; | ||
| 126 | reg = <0x32>; | ||
| 127 | interrupt-parent = <&gpio0>; | ||
| 128 | interrupts = <3 IRQ_TYPE_LEVEL_LOW>; | ||
| 129 | }; | ||
| 130 | }; | ||
| 131 | |||
| 132 | &mdio { | ||
| 133 | status = "okay"; | ||
| 134 | |||
| 135 | ethphy: ethernet-phy { | ||
| 136 | reg = <8>; | ||
| 137 | }; | ||
| 138 | }; | ||
| 139 | |||
| 140 | &pinctrl { | ||
| 141 | pinctrl-0 = <&pmx_rtc &pmx_power_led_ctrl>; | ||
| 142 | pinctrl-names = "default"; | ||
| 143 | |||
| 144 | pmx_power_button: pmx-power-button { | ||
| 145 | marvell,pins = "mpp18"; | ||
| 146 | marvell,function = "gpio"; | ||
| 147 | }; | ||
| 148 | |||
| 149 | pmx_power_led: pmx-power-led { | ||
| 150 | marvell,pins = "mpp16"; | ||
| 151 | marvell,function = "gpio"; | ||
| 152 | }; | ||
| 153 | |||
| 154 | pmx_power_led_ctrl: pmx-power-led-ctrl { | ||
| 155 | marvell,pins = "mpp17"; | ||
| 156 | marvell,function = "gpio"; | ||
| 157 | }; | ||
| 158 | |||
| 159 | pmx_rtc: pmx-rtc { | ||
| 160 | marvell,pins = "mpp3"; | ||
| 161 | marvell,function = "gpio"; | ||
| 162 | }; | ||
| 163 | }; | ||
| 164 | |||
| 165 | &sata { | ||
| 166 | pinctrl-0 = <&pmx_sata0 &pmx_sata1>; | ||
| 167 | pinctrl-names = "default"; | ||
| 168 | status = "okay"; | ||
| 169 | nr-ports = <2>; | ||
| 170 | }; | ||
| 171 | |||
| 172 | &uart0 { | ||
| 173 | status = "okay"; | ||
| 174 | }; | ||
diff --git a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts new file mode 100644 index 000000000000..ff3484904294 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts | |||
| @@ -0,0 +1,178 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
| 3 | * Copyright (C) Sylver Bruneau <sylver.bruneau@googlemail.com> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include <dt-bindings/gpio/gpio.h> | ||
| 13 | #include <dt-bindings/input/input.h> | ||
| 14 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 15 | #include "orion5x-mv88f5182.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | model = "Maxtor Shared Storage II"; | ||
| 19 | compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x"; | ||
| 20 | |||
| 21 | memory { | ||
| 22 | reg = <0x00000000 0x4000000>; /* 64 MB */ | ||
| 23 | }; | ||
| 24 | |||
| 25 | chosen { | ||
| 26 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | ||
| 27 | linux,stdout-path = &uart0; | ||
| 28 | }; | ||
| 29 | |||
| 30 | soc { | ||
| 31 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, | ||
| 32 | <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, | ||
| 33 | <MBUS_ID(0x01, 0x0f) 0 0xff800000 0x40000>; | ||
| 34 | }; | ||
| 35 | |||
| 36 | gpio-keys { | ||
| 37 | compatible = "gpio-keys"; | ||
| 38 | pinctrl-0 = <&pmx_buttons>; | ||
| 39 | pinctrl-names = "default"; | ||
| 40 | #address-cells = <1>; | ||
| 41 | #size-cells = <0>; | ||
| 42 | power { | ||
| 43 | label = "Power"; | ||
| 44 | linux,code = <KEY_POWER>; | ||
| 45 | gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; | ||
| 46 | }; | ||
| 47 | |||
| 48 | reset { | ||
| 49 | label = "Reset"; | ||
| 50 | linux,code = <KEY_RESTART>; | ||
| 51 | gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; | ||
| 52 | }; | ||
| 53 | }; | ||
| 54 | }; | ||
| 55 | |||
| 56 | &devbus_bootcs { | ||
| 57 | status = "okay"; | ||
| 58 | |||
| 59 | devbus,keep-config; | ||
| 60 | |||
| 61 | /* | ||
| 62 | * Currently the MTD code does not recognize the MX29LV400CBCT | ||
| 63 | * as a bottom-type device. This could cause risks of | ||
| 64 | * accidentally erasing critical flash sectors. We thus define | ||
| 65 | * a single, write-protected partition covering the whole | ||
| 66 | * flash. TODO: once the flash part TOP/BOTTOM detection | ||
| 67 | * issue is sorted out in the MTD code, break this into at | ||
| 68 | * least three partitions: 'u-boot code', 'u-boot environment' | ||
| 69 | * and 'whatever is left'. | ||
| 70 | */ | ||
| 71 | flash@0 { | ||
| 72 | compatible = "cfi-flash"; | ||
| 73 | reg = <0 0x40000>; | ||
| 74 | bank-width = <1>; | ||
| 75 | #address-cells = <1>; | ||
| 76 | #size-cells = <1>; | ||
| 77 | }; | ||
| 78 | }; | ||
| 79 | |||
| 80 | &mdio { | ||
| 81 | status = "okay"; | ||
| 82 | |||
| 83 | ethphy: ethernet-phy { | ||
| 84 | reg = <8>; | ||
| 85 | }; | ||
| 86 | }; | ||
| 87 | |||
| 88 | &ehci0 { | ||
| 89 | status = "okay"; | ||
| 90 | }; | ||
| 91 | |||
| 92 | ð { | ||
| 93 | status = "okay"; | ||
| 94 | |||
| 95 | ethernet-port@0 { | ||
| 96 | phy-handle = <ðphy>; | ||
| 97 | }; | ||
| 98 | }; | ||
| 99 | |||
| 100 | &i2c { | ||
| 101 | status = "okay"; | ||
| 102 | clock-frequency = <100000>; | ||
| 103 | #address-cells = <1>; | ||
| 104 | |||
| 105 | rtc@68 { | ||
| 106 | compatible = "st,m41t81"; | ||
| 107 | reg = <0x68>; | ||
| 108 | pinctrl-0 = <&pmx_rtc>; | ||
| 109 | pinctrl-names = "default"; | ||
| 110 | interrupt-parent = <&gpio0>; | ||
| 111 | interrupts = <3 IRQ_TYPE_LEVEL_LOW>; | ||
| 112 | }; | ||
| 113 | }; | ||
| 114 | |||
| 115 | &pinctrl { | ||
| 116 | pinctrl-0 = <&pmx_leds &pmx_misc>; | ||
| 117 | pinctrl-names = "default"; | ||
| 118 | |||
| 119 | pmx_buttons: pmx-buttons { | ||
| 120 | marvell,pins = "mpp11", "mpp12"; | ||
| 121 | marvell,function = "gpio"; | ||
| 122 | }; | ||
| 123 | |||
| 124 | /* | ||
| 125 | * MPP0: Power LED | ||
| 126 | * MPP1: Error LED | ||
| 127 | */ | ||
| 128 | pmx_leds: pmx-leds { | ||
| 129 | marvell,pins = "mpp0", "mpp1"; | ||
| 130 | marvell,function = "gpio"; | ||
| 131 | }; | ||
| 132 | |||
| 133 | /* | ||
| 134 | * MPP4: HDD ind. (Single/Dual) | ||
| 135 | * MPP5: HD0 5V control | ||
| 136 | * MPP6: HD0 12V control | ||
| 137 | * MPP7: HD1 5V control | ||
| 138 | * MPP8: HD1 12V control | ||
| 139 | */ | ||
| 140 | pmx_misc: pmx-misc { | ||
| 141 | marvell,pins = "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp10"; | ||
| 142 | marvell,function = "gpio"; | ||
| 143 | }; | ||
| 144 | |||
| 145 | pmx_rtc: pmx-rtc { | ||
| 146 | marvell,pins = "mpp3"; | ||
| 147 | marvell,function = "gpio"; | ||
| 148 | }; | ||
| 149 | |||
| 150 | pmx_sata0_led_active: pmx-sata0-led-active { | ||
| 151 | marvell,pins = "mpp14"; | ||
| 152 | marvell,function = "sata0"; | ||
| 153 | }; | ||
| 154 | |||
| 155 | pmx_sata1_led_active: pmx-sata1-led-active { | ||
| 156 | marvell,pins = "mpp15"; | ||
| 157 | marvell,function = "sata1"; | ||
| 158 | }; | ||
| 159 | |||
| 160 | /* | ||
| 161 | * Non MPP GPIOs: | ||
| 162 | * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok) | ||
| 163 | * GPIO 23: Blue front LED off | ||
| 164 | * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled) | ||
| 165 | */ | ||
| 166 | }; | ||
| 167 | |||
| 168 | &sata { | ||
| 169 | pinctrl-0 = <&pmx_sata0_led_active | ||
| 170 | &pmx_sata1_led_active>; | ||
| 171 | pinctrl-names = "default"; | ||
| 172 | status = "okay"; | ||
| 173 | nr-ports = <2>; | ||
| 174 | }; | ||
| 175 | |||
| 176 | &uart0 { | ||
| 177 | status = "okay"; | ||
| 178 | }; | ||
diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi new file mode 100644 index 000000000000..d1ed71c60209 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include "orion5x.dtsi" | ||
| 10 | |||
| 11 | / { | ||
| 12 | compatible = "marvell,orion5x-88f5182", "marvell,orion5x"; | ||
| 13 | |||
| 14 | soc { | ||
| 15 | compatible = "marvell,orion5x-88f5182-mbus", "simple-bus"; | ||
| 16 | |||
| 17 | internal-regs { | ||
| 18 | pinctrl: pinctrl@10000 { | ||
| 19 | compatible = "marvell,88f5182-pinctrl"; | ||
| 20 | reg = <0x10000 0x8>, <0x10050 0x4>; | ||
| 21 | |||
| 22 | pmx_sata0: pmx-sata0 { | ||
| 23 | marvell,pins = "mpp12", "mpp14"; | ||
| 24 | marvell,function = "sata0"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | pmx_sata1: pmx-sata1 { | ||
| 28 | marvell,pins = "mpp13", "mpp15"; | ||
| 29 | marvell,function = "sata1"; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | |||
| 33 | core_clk: core-clocks@10030 { | ||
| 34 | compatible = "marvell,mv88f5182-core-clock"; | ||
| 35 | reg = <0x10010 0x4>; | ||
| 36 | #clock-cells = <1>; | ||
| 37 | }; | ||
| 38 | |||
| 39 | mbusc: mbus-controller@20000 { | ||
| 40 | compatible = "marvell,mbus-controller"; | ||
| 41 | reg = <0x20000 0x100>, <0x1500 0x20>; | ||
| 42 | }; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | }; | ||
diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts new file mode 100644 index 000000000000..6fb052507b36 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts | |||
| @@ -0,0 +1,177 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /dts-v1/; | ||
| 10 | |||
| 11 | #include <dt-bindings/gpio/gpio.h> | ||
| 12 | #include "orion5x-mv88f5182.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "Marvell Reference Design 88F5182 NAS"; | ||
| 16 | compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x"; | ||
| 17 | |||
| 18 | memory { | ||
| 19 | reg = <0x00000000 0x4000000>; /* 64 MB */ | ||
| 20 | }; | ||
| 21 | |||
| 22 | chosen { | ||
| 23 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | ||
| 24 | linux,stdout-path = &uart0; | ||
| 25 | }; | ||
| 26 | |||
| 27 | soc { | ||
| 28 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, | ||
| 29 | <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, | ||
| 30 | <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x80000>, | ||
| 31 | <MBUS_ID(0x01, 0x1d) 0 0xfc000000 0x1000000>; | ||
| 32 | }; | ||
| 33 | |||
| 34 | gpio-leds { | ||
| 35 | compatible = "gpio-leds"; | ||
| 36 | pinctrl-0 = <&pmx_debug_led>; | ||
| 37 | pinctrl-names = "default"; | ||
| 38 | |||
| 39 | led@0 { | ||
| 40 | label = "rd88f5182:cpu"; | ||
| 41 | linux,default-trigger = "heartbeat"; | ||
| 42 | gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | |||
| 47 | &devbus_bootcs { | ||
| 48 | status = "okay"; | ||
| 49 | |||
| 50 | /* Read parameters */ | ||
| 51 | devbus,bus-width = <8>; | ||
| 52 | devbus,turn-off-ps = <90000>; | ||
| 53 | devbus,badr-skew-ps = <0>; | ||
| 54 | devbus,acc-first-ps = <186000>; | ||
| 55 | devbus,acc-next-ps = <186000>; | ||
| 56 | |||
| 57 | /* Write parameters */ | ||
| 58 | devbus,wr-high-ps = <90000>; | ||
| 59 | devbus,wr-low-ps = <90000>; | ||
| 60 | devbus,ale-wr-ps = <90000>; | ||
| 61 | |||
| 62 | flash@0 { | ||
| 63 | compatible = "cfi-flash"; | ||
| 64 | reg = <0 0x80000>; | ||
| 65 | bank-width = <1>; | ||
| 66 | }; | ||
| 67 | }; | ||
| 68 | |||
| 69 | &devbus_cs1 { | ||
| 70 | status = "okay"; | ||
| 71 | |||
| 72 | /* Read parameters */ | ||
| 73 | devbus,bus-width = <8>; | ||
| 74 | devbus,turn-off-ps = <90000>; | ||
| 75 | devbus,badr-skew-ps = <0>; | ||
| 76 | devbus,acc-first-ps = <186000>; | ||
| 77 | devbus,acc-next-ps = <186000>; | ||
| 78 | |||
| 79 | /* Write parameters */ | ||
| 80 | devbus,wr-high-ps = <90000>; | ||
| 81 | devbus,wr-low-ps = <90000>; | ||
| 82 | devbus,ale-wr-ps = <90000>; | ||
| 83 | |||
| 84 | flash@0 { | ||
| 85 | compatible = "cfi-flash"; | ||
| 86 | reg = <0 0x1000000>; | ||
| 87 | bank-width = <1>; | ||
| 88 | }; | ||
| 89 | }; | ||
| 90 | |||
| 91 | &ehci0 { | ||
| 92 | status = "okay"; | ||
| 93 | }; | ||
| 94 | |||
| 95 | &ehci1 { | ||
| 96 | status = "okay"; | ||
| 97 | }; | ||
| 98 | |||
| 99 | ð { | ||
| 100 | status = "okay"; | ||
| 101 | |||
| 102 | ethernet-port@0 { | ||
| 103 | phy-handle = <ðphy>; | ||
| 104 | }; | ||
| 105 | }; | ||
| 106 | |||
| 107 | &i2c { | ||
| 108 | status = "okay"; | ||
| 109 | clock-frequency = <100000>; | ||
| 110 | #address-cells = <1>; | ||
| 111 | |||
| 112 | rtc@68 { | ||
| 113 | pinctrl-0 = <&pmx_rtc>; | ||
| 114 | pinctrl-names = "default"; | ||
| 115 | compatible = "dallas,ds1338"; | ||
| 116 | reg = <0x68>; | ||
| 117 | }; | ||
| 118 | }; | ||
| 119 | |||
| 120 | &mdio { | ||
| 121 | status = "okay"; | ||
| 122 | |||
| 123 | ethphy: ethernet-phy { | ||
| 124 | reg = <8>; | ||
| 125 | }; | ||
| 126 | }; | ||
| 127 | |||
| 128 | &pinctrl { | ||
| 129 | pinctrl-0 = <&pmx_reset_switch &pmx_misc_gpios | ||
| 130 | &pmx_pci_gpios>; | ||
| 131 | pinctrl-names = "default"; | ||
| 132 | |||
| 133 | /* | ||
| 134 | * MPP[20] PCI Clock to MV88F5182 | ||
| 135 | * MPP[21] PCI Clock to mini PCI CON11 | ||
| 136 | * MPP[22] USB 0 over current indication | ||
| 137 | * MPP[23] USB 1 over current indication | ||
| 138 | * MPP[24] USB 1 over current enable | ||
| 139 | * MPP[25] USB 0 over current enable | ||
| 140 | */ | ||
| 141 | |||
| 142 | pmx_debug_led: pmx-debug_led { | ||
| 143 | marvell,pins = "mpp0"; | ||
| 144 | marvell,function = "gpio"; | ||
| 145 | }; | ||
| 146 | |||
| 147 | pmx_reset_switch: pmx-reset-switch { | ||
| 148 | marvell,pins = "mpp1"; | ||
| 149 | marvell,function = "gpio"; | ||
| 150 | }; | ||
| 151 | |||
| 152 | pmx_rtc: pmx-rtc { | ||
| 153 | marvell,pins = "mpp3"; | ||
| 154 | marvell,function = "gpio"; | ||
| 155 | }; | ||
| 156 | |||
| 157 | pmx_misc_gpios: pmx-misc-gpios { | ||
| 158 | marvell,pins = "mpp4", "mpp5"; | ||
| 159 | marvell,function = "gpio"; | ||
| 160 | }; | ||
| 161 | |||
| 162 | pmx_pci_gpios: pmx-pci-gpios { | ||
| 163 | marvell,pins = "mpp6", "mpp7"; | ||
| 164 | marvell,function = "gpio"; | ||
| 165 | }; | ||
| 166 | }; | ||
| 167 | |||
| 168 | &sata { | ||
| 169 | pinctrl-0 = <&pmx_sata0 &pmx_sata1>; | ||
| 170 | pinctrl-names = "default"; | ||
| 171 | status = "okay"; | ||
| 172 | nr-ports = <2>; | ||
| 173 | }; | ||
| 174 | |||
| 175 | &uart0 { | ||
| 176 | status = "okay"; | ||
| 177 | }; | ||
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index 174d89241f70..75cd01bd6024 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi | |||
| @@ -6,7 +6,9 @@ | |||
| 6 | * warranty of any kind, whether express or implied. | 6 | * warranty of any kind, whether express or implied. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /include/ "skeleton.dtsi" | 9 | #include "skeleton.dtsi" |
| 10 | |||
| 11 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) | ||
| 10 | 12 | ||
| 11 | / { | 13 | / { |
| 12 | model = "Marvell Orion5x SoC"; | 14 | model = "Marvell Orion5x SoC"; |
| @@ -17,149 +19,214 @@ | |||
| 17 | gpio0 = &gpio0; | 19 | gpio0 = &gpio0; |
| 18 | }; | 20 | }; |
| 19 | 21 | ||
| 20 | intc: interrupt-controller { | 22 | soc { |
| 21 | compatible = "marvell,orion-intc"; | 23 | #address-cells = <2>; |
| 22 | interrupt-controller; | ||
| 23 | #interrupt-cells = <1>; | ||
| 24 | reg = <0xf1020200 0x08>; | ||
| 25 | }; | ||
| 26 | |||
| 27 | ocp@f1000000 { | ||
| 28 | compatible = "simple-bus"; | ||
| 29 | ranges = <0x00000000 0xf1000000 0x4000000 | ||
| 30 | 0xf2200000 0xf2200000 0x0000800>; | ||
| 31 | #address-cells = <1>; | ||
| 32 | #size-cells = <1>; | 24 | #size-cells = <1>; |
| 25 | controller = <&mbusc>; | ||
| 33 | 26 | ||
| 34 | gpio0: gpio@10100 { | 27 | devbus_bootcs: devbus-bootcs { |
| 35 | compatible = "marvell,orion-gpio"; | 28 | compatible = "marvell,orion-devbus"; |
| 36 | #gpio-cells = <2>; | 29 | reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>; |
| 37 | gpio-controller; | 30 | ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>; |
| 38 | reg = <0x10100 0x40>; | ||
| 39 | ngpios = <32>; | ||
| 40 | interrupt-controller; | ||
| 41 | #interrupt-cells = <2>; | ||
| 42 | interrupts = <6>, <7>, <8>, <9>; | ||
| 43 | }; | ||
| 44 | |||
| 45 | spi@10600 { | ||
| 46 | compatible = "marvell,orion-spi"; | ||
| 47 | #address-cells = <1>; | 31 | #address-cells = <1>; |
| 48 | #size-cells = <0>; | 32 | #size-cells = <1>; |
| 49 | cell-index = <0>; | 33 | clocks = <&core_clk 0>; |
| 50 | reg = <0x10600 0x28>; | ||
| 51 | status = "disabled"; | 34 | status = "disabled"; |
| 52 | }; | 35 | }; |
| 53 | 36 | ||
| 54 | i2c@11000 { | 37 | devbus_cs0: devbus-cs0 { |
| 55 | compatible = "marvell,mv64xxx-i2c"; | 38 | compatible = "marvell,orion-devbus"; |
| 56 | reg = <0x11000 0x20>; | 39 | reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>; |
| 40 | ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>; | ||
| 57 | #address-cells = <1>; | 41 | #address-cells = <1>; |
| 58 | #size-cells = <0>; | 42 | #size-cells = <1>; |
| 59 | interrupts = <5>; | 43 | clocks = <&core_clk 0>; |
| 60 | clock-frequency = <100000>; | ||
| 61 | status = "disabled"; | 44 | status = "disabled"; |
| 62 | }; | 45 | }; |
| 63 | 46 | ||
| 64 | serial@12000 { | 47 | devbus_cs1: devbus-cs1 { |
| 65 | compatible = "ns16550a"; | 48 | compatible = "marvell,orion-devbus"; |
| 66 | reg = <0x12000 0x100>; | 49 | reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>; |
| 67 | reg-shift = <2>; | 50 | ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>; |
| 68 | interrupts = <3>; | 51 | #address-cells = <1>; |
| 69 | /* set clock-frequency in board dts */ | 52 | #size-cells = <1>; |
| 53 | clocks = <&core_clk 0>; | ||
| 70 | status = "disabled"; | 54 | status = "disabled"; |
| 71 | }; | 55 | }; |
| 72 | 56 | ||
| 73 | serial@12100 { | 57 | devbus_cs2: devbus-cs2 { |
| 74 | compatible = "ns16550a"; | 58 | compatible = "marvell,orion-devbus"; |
| 75 | reg = <0x12100 0x100>; | 59 | reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>; |
| 76 | reg-shift = <2>; | 60 | ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>; |
| 77 | interrupts = <4>; | 61 | #address-cells = <1>; |
| 78 | /* set clock-frequency in board dts */ | 62 | #size-cells = <1>; |
| 63 | clocks = <&core_clk 0>; | ||
| 79 | status = "disabled"; | 64 | status = "disabled"; |
| 80 | }; | 65 | }; |
| 81 | 66 | ||
| 82 | wdt@20300 { | 67 | internal-regs { |
| 83 | compatible = "marvell,orion-wdt"; | 68 | compatible = "simple-bus"; |
| 84 | reg = <0x20300 0x28>; | 69 | #address-cells = <1>; |
| 85 | status = "okay"; | 70 | #size-cells = <1>; |
| 86 | }; | 71 | ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; |
| 72 | |||
| 73 | gpio0: gpio@10100 { | ||
| 74 | compatible = "marvell,orion-gpio"; | ||
| 75 | #gpio-cells = <2>; | ||
| 76 | gpio-controller; | ||
| 77 | reg = <0x10100 0x40>; | ||
| 78 | ngpios = <32>; | ||
| 79 | interrupt-controller; | ||
| 80 | #interrupt-cells = <2>; | ||
| 81 | interrupts = <6>, <7>, <8>, <9>; | ||
| 82 | }; | ||
| 87 | 83 | ||
| 88 | ehci@50000 { | 84 | spi: spi@10600 { |
| 89 | compatible = "marvell,orion-ehci"; | 85 | compatible = "marvell,orion-spi"; |
| 90 | reg = <0x50000 0x1000>; | 86 | #address-cells = <1>; |
| 91 | interrupts = <17>; | 87 | #size-cells = <0>; |
| 92 | status = "disabled"; | 88 | cell-index = <0>; |
| 93 | }; | 89 | reg = <0x10600 0x28>; |
| 90 | status = "disabled"; | ||
| 91 | }; | ||
| 94 | 92 | ||
| 95 | xor@60900 { | 93 | i2c: i2c@11000 { |
| 96 | compatible = "marvell,orion-xor"; | 94 | compatible = "marvell,mv64xxx-i2c"; |
| 97 | reg = <0x60900 0x100 | 95 | reg = <0x11000 0x20>; |
| 98 | 0x60b00 0x100>; | 96 | #address-cells = <1>; |
| 99 | status = "okay"; | 97 | #size-cells = <0>; |
| 98 | interrupts = <5>; | ||
| 99 | clocks = <&core_clk 0>; | ||
| 100 | status = "disabled"; | ||
| 101 | }; | ||
| 100 | 102 | ||
| 101 | xor00 { | 103 | uart0: serial@12000 { |
| 102 | interrupts = <30>; | 104 | compatible = "ns16550a"; |
| 103 | dmacap,memcpy; | 105 | reg = <0x12000 0x100>; |
| 104 | dmacap,xor; | 106 | reg-shift = <2>; |
| 107 | interrupts = <3>; | ||
| 108 | clocks = <&core_clk 0>; | ||
| 109 | status = "disabled"; | ||
| 105 | }; | 110 | }; |
| 106 | xor01 { | 111 | |
| 107 | interrupts = <31>; | 112 | uart1: serial@12100 { |
| 108 | dmacap,memcpy; | 113 | compatible = "ns16550a"; |
| 109 | dmacap,xor; | 114 | reg = <0x12100 0x100>; |
| 110 | dmacap,memset; | 115 | reg-shift = <2>; |
| 116 | interrupts = <4>; | ||
| 117 | clocks = <&core_clk 0>; | ||
| 118 | status = "disabled"; | ||
| 111 | }; | 119 | }; |
| 112 | }; | ||
| 113 | 120 | ||
| 114 | eth: ethernet-controller@72000 { | 121 | bridge_intc: bridge-interrupt-ctrl@20110 { |
| 115 | compatible = "marvell,orion-eth"; | 122 | compatible = "marvell,orion-bridge-intc"; |
| 116 | #address-cells = <1>; | 123 | interrupt-controller; |
| 117 | #size-cells = <0>; | 124 | #interrupt-cells = <1>; |
| 118 | reg = <0x72000 0x4000>; | 125 | reg = <0x20110 0x8>; |
| 119 | marvell,tx-checksum-limit = <1600>; | 126 | interrupts = <0>; |
| 120 | status = "disabled"; | 127 | marvell,#interrupts = <4>; |
| 128 | }; | ||
| 121 | 129 | ||
| 122 | ethernet-port@0 { | 130 | intc: interrupt-controller@20200 { |
| 123 | compatible = "marvell,orion-eth-port"; | 131 | compatible = "marvell,orion-intc"; |
| 124 | reg = <0>; | 132 | interrupt-controller; |
| 125 | /* overwrite MAC address in bootloader */ | 133 | #interrupt-cells = <1>; |
| 126 | local-mac-address = [00 00 00 00 00 00]; | 134 | reg = <0x20200 0x08>; |
| 127 | /* set phy-handle property in board file */ | ||
| 128 | }; | 135 | }; |
| 129 | }; | ||
| 130 | 136 | ||
| 131 | mdio: mdio-bus@72004 { | 137 | timer: timer@20300 { |
| 132 | compatible = "marvell,orion-mdio"; | 138 | compatible = "marvell,orion-timer"; |
| 133 | #address-cells = <1>; | 139 | reg = <0x20300 0x20>; |
| 134 | #size-cells = <0>; | 140 | interrupt-parent = <&bridge_intc>; |
| 135 | reg = <0x72004 0x84>; | 141 | interrupts = <1>, <2>; |
| 136 | interrupts = <22>; | 142 | clocks = <&core_clk 0>; |
| 137 | status = "disabled"; | 143 | }; |
| 138 | 144 | ||
| 139 | /* add phy nodes in board file */ | 145 | wdt: wdt@20300 { |
| 140 | }; | 146 | compatible = "marvell,orion-wdt"; |
| 147 | reg = <0x20300 0x28>; | ||
| 148 | interrupt-parent = <&bridge_intc>; | ||
| 149 | interrupts = <3>; | ||
| 150 | status = "okay"; | ||
| 151 | }; | ||
| 141 | 152 | ||
| 142 | sata@80000 { | 153 | ehci0: ehci@50000 { |
| 143 | compatible = "marvell,orion-sata"; | 154 | compatible = "marvell,orion-ehci"; |
| 144 | reg = <0x80000 0x5000>; | 155 | reg = <0x50000 0x1000>; |
| 145 | interrupts = <29>; | 156 | interrupts = <17>; |
| 146 | status = "disabled"; | 157 | status = "disabled"; |
| 158 | }; | ||
| 159 | |||
| 160 | xor: dma-controller@60900 { | ||
| 161 | compatible = "marvell,orion-xor"; | ||
| 162 | reg = <0x60900 0x100 | ||
| 163 | 0x60b00 0x100>; | ||
| 164 | status = "okay"; | ||
| 165 | |||
| 166 | xor00 { | ||
| 167 | interrupts = <30>; | ||
| 168 | dmacap,memcpy; | ||
| 169 | dmacap,xor; | ||
| 170 | }; | ||
| 171 | xor01 { | ||
| 172 | interrupts = <31>; | ||
| 173 | dmacap,memcpy; | ||
| 174 | dmacap,xor; | ||
| 175 | dmacap,memset; | ||
| 176 | }; | ||
| 177 | }; | ||
| 178 | |||
| 179 | eth: ethernet-controller@72000 { | ||
| 180 | compatible = "marvell,orion-eth"; | ||
| 181 | #address-cells = <1>; | ||
| 182 | #size-cells = <0>; | ||
| 183 | reg = <0x72000 0x4000>; | ||
| 184 | marvell,tx-checksum-limit = <1600>; | ||
| 185 | status = "disabled"; | ||
| 186 | |||
| 187 | ethport: ethernet-port@0 { | ||
| 188 | compatible = "marvell,orion-eth-port"; | ||
| 189 | reg = <0>; | ||
| 190 | interrupts = <21>; | ||
| 191 | /* overwrite MAC address in bootloader */ | ||
| 192 | local-mac-address = [00 00 00 00 00 00]; | ||
| 193 | /* set phy-handle property in board file */ | ||
| 194 | }; | ||
| 195 | }; | ||
| 196 | |||
| 197 | mdio: mdio-bus@72004 { | ||
| 198 | compatible = "marvell,orion-mdio"; | ||
| 199 | #address-cells = <1>; | ||
| 200 | #size-cells = <0>; | ||
| 201 | reg = <0x72004 0x84>; | ||
| 202 | interrupts = <22>; | ||
| 203 | status = "disabled"; | ||
| 204 | |||
| 205 | /* add phy nodes in board file */ | ||
| 206 | }; | ||
| 207 | |||
| 208 | sata: sata@80000 { | ||
| 209 | compatible = "marvell,orion-sata"; | ||
| 210 | reg = <0x80000 0x5000>; | ||
| 211 | interrupts = <29>; | ||
| 212 | status = "disabled"; | ||
| 213 | }; | ||
| 214 | |||
| 215 | ehci1: ehci@a0000 { | ||
| 216 | compatible = "marvell,orion-ehci"; | ||
| 217 | reg = <0xa0000 0x1000>; | ||
| 218 | interrupts = <12>; | ||
| 219 | status = "disabled"; | ||
| 220 | }; | ||
| 147 | }; | 221 | }; |
| 148 | 222 | ||
| 149 | crypto@90000 { | 223 | cesa: crypto@90000 { |
| 150 | compatible = "marvell,orion-crypto"; | 224 | compatible = "marvell,orion-crypto"; |
| 151 | reg = <0x90000 0x10000>, | 225 | reg = <MBUS_ID(0xf0, 0x01) 0x90000 0x10000>, |
| 152 | <0xf2200000 0x800>; | 226 | <MBUS_ID(0x09, 0x00) 0x0 0x800>; |
| 153 | reg-names = "regs", "sram"; | 227 | reg-names = "regs", "sram"; |
| 154 | interrupts = <28>; | 228 | interrupts = <28>; |
| 155 | status = "okay"; | 229 | status = "okay"; |
| 156 | }; | 230 | }; |
| 157 | |||
| 158 | ehci@a0000 { | ||
| 159 | compatible = "marvell,orion-ehci"; | ||
| 160 | reg = <0xa0000 0x1000>; | ||
| 161 | interrupts = <12>; | ||
| 162 | status = "disabled"; | ||
| 163 | }; | ||
| 164 | }; | 231 | }; |
| 165 | }; | 232 | }; |
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 1e82571d6823..963b7e54ab15 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi | |||
| @@ -48,7 +48,7 @@ | |||
| 48 | ranges = <0x40000000 0x40000000 0x80000000>; | 48 | ranges = <0x40000000 0x40000000 0x80000000>; |
| 49 | 49 | ||
| 50 | l2-cache-controller@80040000 { | 50 | l2-cache-controller@80040000 { |
| 51 | compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; | 51 | compatible = "arm,pl310-cache"; |
| 52 | reg = <0x80040000 0x1000>; | 52 | reg = <0x80040000 0x1000>; |
| 53 | interrupts = <59>; | 53 | interrupts = <59>; |
| 54 | arm,tag-latency = <1 1 1>; | 54 | arm,tag-latency = <1 1 1>; |
| @@ -201,6 +201,7 @@ | |||
| 201 | compatible = "sirf,prima2-tick"; | 201 | compatible = "sirf,prima2-tick"; |
| 202 | reg = <0xb0020000 0x1000>; | 202 | reg = <0xb0020000 0x1000>; |
| 203 | interrupts = <0>; | 203 | interrupts = <0>; |
| 204 | clocks = <&clks 11>; | ||
| 204 | }; | 205 | }; |
| 205 | 206 | ||
| 206 | nand@b0030000 { | 207 | nand@b0030000 { |
| @@ -313,8 +314,9 @@ | |||
| 313 | reg = <0xb00d0000 0x10000>; | 314 | reg = <0xb00d0000 0x10000>; |
| 314 | interrupts = <15>; | 315 | interrupts = <15>; |
| 315 | sirf,spi-num-chipselects = <1>; | 316 | sirf,spi-num-chipselects = <1>; |
| 316 | sirf,spi-dma-rx-channel = <25>; | 317 | dmas = <&dmac1 9>, |
| 317 | sirf,spi-dma-tx-channel = <20>; | 318 | <&dmac1 4>; |
| 319 | dma-names = "rx", "tx"; | ||
| 318 | #address-cells = <1>; | 320 | #address-cells = <1>; |
| 319 | #size-cells = <0>; | 321 | #size-cells = <0>; |
| 320 | clocks = <&clks 19>; | 322 | clocks = <&clks 19>; |
| @@ -327,8 +329,9 @@ | |||
| 327 | reg = <0xb0170000 0x10000>; | 329 | reg = <0xb0170000 0x10000>; |
| 328 | interrupts = <16>; | 330 | interrupts = <16>; |
| 329 | sirf,spi-num-chipselects = <1>; | 331 | sirf,spi-num-chipselects = <1>; |
| 330 | sirf,spi-dma-rx-channel = <12>; | 332 | dmas = <&dmac0 12>, |
| 331 | sirf,spi-dma-tx-channel = <13>; | 333 | <&dmac0 13>; |
| 334 | dma-names = "rx", "tx"; | ||
| 332 | #address-cells = <1>; | 335 | #address-cells = <1>; |
| 333 | #size-cells = <0>; | 336 | #size-cells = <0>; |
| 334 | clocks = <&clks 20>; | 337 | clocks = <&clks 20>; |
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts new file mode 100644 index 000000000000..7c2441d526bc --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | #include "qcom-apq8064-v2.0.dtsi" | ||
| 2 | |||
| 3 | / { | ||
| 4 | model = "Qualcomm APQ8064/IFC6410"; | ||
| 5 | compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; | ||
| 6 | |||
| 7 | soc { | ||
| 8 | gsbi@16600000 { | ||
| 9 | status = "ok"; | ||
| 10 | qcom,mode = <GSBI_PROT_I2C_UART>; | ||
| 11 | serial@16640000 { | ||
| 12 | status = "ok"; | ||
| 13 | }; | ||
| 14 | }; | ||
| 15 | }; | ||
| 16 | }; | ||
diff --git a/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi new file mode 100644 index 000000000000..935c3945fc5e --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi | |||
| @@ -0,0 +1 @@ | |||
| #include "qcom-apq8064.dtsi" | |||
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi new file mode 100644 index 000000000000..92bf793622c3 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi | |||
| @@ -0,0 +1,170 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | #include "skeleton.dtsi" | ||
| 4 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> | ||
| 5 | #include <dt-bindings/soc/qcom,gsbi.h> | ||
| 6 | |||
| 7 | / { | ||
| 8 | model = "Qualcomm APQ8064"; | ||
| 9 | compatible = "qcom,apq8064"; | ||
| 10 | interrupt-parent = <&intc>; | ||
| 11 | |||
| 12 | cpus { | ||
| 13 | #address-cells = <1>; | ||
| 14 | #size-cells = <0>; | ||
| 15 | |||
| 16 | cpu@0 { | ||
| 17 | compatible = "qcom,krait"; | ||
| 18 | enable-method = "qcom,kpss-acc-v1"; | ||
| 19 | device_type = "cpu"; | ||
| 20 | reg = <0>; | ||
| 21 | next-level-cache = <&L2>; | ||
| 22 | qcom,acc = <&acc0>; | ||
| 23 | qcom,saw = <&saw0>; | ||
| 24 | }; | ||
| 25 | |||
| 26 | cpu@1 { | ||
| 27 | compatible = "qcom,krait"; | ||
| 28 | enable-method = "qcom,kpss-acc-v1"; | ||
| 29 | device_type = "cpu"; | ||
| 30 | reg = <1>; | ||
| 31 | next-level-cache = <&L2>; | ||
| 32 | qcom,acc = <&acc1>; | ||
| 33 | qcom,saw = <&saw1>; | ||
| 34 | }; | ||
| 35 | |||
| 36 | cpu@2 { | ||
| 37 | compatible = "qcom,krait"; | ||
| 38 | enable-method = "qcom,kpss-acc-v1"; | ||
| 39 | device_type = "cpu"; | ||
| 40 | reg = <2>; | ||
| 41 | next-level-cache = <&L2>; | ||
| 42 | qcom,acc = <&acc2>; | ||
| 43 | qcom,saw = <&saw2>; | ||
| 44 | }; | ||
| 45 | |||
| 46 | cpu@3 { | ||
| 47 | compatible = "qcom,krait"; | ||
| 48 | enable-method = "qcom,kpss-acc-v1"; | ||
| 49 | device_type = "cpu"; | ||
| 50 | reg = <3>; | ||
| 51 | next-level-cache = <&L2>; | ||
| 52 | qcom,acc = <&acc3>; | ||
| 53 | qcom,saw = <&saw3>; | ||
| 54 | }; | ||
| 55 | |||
| 56 | L2: l2-cache { | ||
| 57 | compatible = "cache"; | ||
| 58 | cache-level = <2>; | ||
| 59 | }; | ||
| 60 | }; | ||
| 61 | |||
| 62 | cpu-pmu { | ||
| 63 | compatible = "qcom,krait-pmu"; | ||
| 64 | interrupts = <1 10 0x304>; | ||
| 65 | }; | ||
| 66 | |||
| 67 | soc: soc { | ||
| 68 | #address-cells = <1>; | ||
| 69 | #size-cells = <1>; | ||
| 70 | ranges; | ||
| 71 | compatible = "simple-bus"; | ||
| 72 | |||
| 73 | intc: interrupt-controller@2000000 { | ||
| 74 | compatible = "qcom,msm-qgic2"; | ||
| 75 | interrupt-controller; | ||
| 76 | #interrupt-cells = <3>; | ||
| 77 | reg = <0x02000000 0x1000>, | ||
| 78 | <0x02002000 0x1000>; | ||
| 79 | }; | ||
| 80 | |||
| 81 | timer@200a000 { | ||
| 82 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; | ||
| 83 | interrupts = <1 1 0x301>, | ||
| 84 | <1 2 0x301>, | ||
| 85 | <1 3 0x301>; | ||
| 86 | reg = <0x0200a000 0x100>; | ||
| 87 | clock-frequency = <27000000>, | ||
| 88 | <32768>; | ||
| 89 | cpu-offset = <0x80000>; | ||
| 90 | }; | ||
| 91 | |||
| 92 | acc0: clock-controller@2088000 { | ||
| 93 | compatible = "qcom,kpss-acc-v1"; | ||
| 94 | reg = <0x02088000 0x1000>, <0x02008000 0x1000>; | ||
| 95 | }; | ||
| 96 | |||
| 97 | acc1: clock-controller@2098000 { | ||
| 98 | compatible = "qcom,kpss-acc-v1"; | ||
| 99 | reg = <0x02098000 0x1000>, <0x02008000 0x1000>; | ||
| 100 | }; | ||
| 101 | |||
| 102 | acc2: clock-controller@20a8000 { | ||
| 103 | compatible = "qcom,kpss-acc-v1"; | ||
| 104 | reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; | ||
| 105 | }; | ||
| 106 | |||
| 107 | acc3: clock-controller@20b8000 { | ||
| 108 | compatible = "qcom,kpss-acc-v1"; | ||
| 109 | reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; | ||
| 110 | }; | ||
| 111 | |||
| 112 | saw0: regulator@2089000 { | ||
| 113 | compatible = "qcom,saw2"; | ||
| 114 | reg = <0x02089000 0x1000>, <0x02009000 0x1000>; | ||
| 115 | regulator; | ||
| 116 | }; | ||
| 117 | |||
| 118 | saw1: regulator@2099000 { | ||
| 119 | compatible = "qcom,saw2"; | ||
| 120 | reg = <0x02099000 0x1000>, <0x02009000 0x1000>; | ||
| 121 | regulator; | ||
| 122 | }; | ||
| 123 | |||
| 124 | saw2: regulator@20a9000 { | ||
| 125 | compatible = "qcom,saw2"; | ||
| 126 | reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; | ||
| 127 | regulator; | ||
| 128 | }; | ||
| 129 | |||
| 130 | saw3: regulator@20b9000 { | ||
| 131 | compatible = "qcom,saw2"; | ||
| 132 | reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; | ||
| 133 | regulator; | ||
| 134 | }; | ||
| 135 | |||
| 136 | gsbi7: gsbi@16600000 { | ||
| 137 | status = "disabled"; | ||
| 138 | compatible = "qcom,gsbi-v1.0.0"; | ||
| 139 | reg = <0x16600000 0x100>; | ||
| 140 | clocks = <&gcc GSBI7_H_CLK>; | ||
| 141 | clock-names = "iface"; | ||
| 142 | #address-cells = <1>; | ||
| 143 | #size-cells = <1>; | ||
| 144 | ranges; | ||
| 145 | |||
| 146 | serial@16640000 { | ||
| 147 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | ||
| 148 | reg = <0x16640000 0x1000>, | ||
| 149 | <0x16600000 0x1000>; | ||
| 150 | interrupts = <0 158 0x0>; | ||
| 151 | clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; | ||
| 152 | clock-names = "core", "iface"; | ||
| 153 | status = "disabled"; | ||
| 154 | }; | ||
| 155 | }; | ||
| 156 | |||
| 157 | qcom,ssbi@500000 { | ||
| 158 | compatible = "qcom,ssbi"; | ||
| 159 | reg = <0x00500000 0x1000>; | ||
| 160 | qcom,controller-type = "pmic-arbiter"; | ||
| 161 | }; | ||
| 162 | |||
| 163 | gcc: clock-controller@900000 { | ||
| 164 | compatible = "qcom,gcc-apq8064"; | ||
| 165 | reg = <0x00900000 0x4000>; | ||
| 166 | #clock-cells = <1>; | ||
| 167 | #reset-cells = <1>; | ||
| 168 | }; | ||
| 169 | }; | ||
| 170 | }; | ||
diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index 13ac3e222495..b4dfb01fe6fb 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | |||
| @@ -3,4 +3,43 @@ | |||
| 3 | / { | 3 | / { |
| 4 | model = "Qualcomm APQ8074 Dragonboard"; | 4 | model = "Qualcomm APQ8074 Dragonboard"; |
| 5 | compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; | 5 | compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; |
| 6 | |||
| 7 | soc { | ||
| 8 | serial@f991e000 { | ||
| 9 | status = "ok"; | ||
| 10 | }; | ||
| 11 | |||
| 12 | sdhci@f9824900 { | ||
| 13 | bus-width = <8>; | ||
| 14 | non-removable; | ||
| 15 | status = "ok"; | ||
| 16 | }; | ||
| 17 | |||
| 18 | sdhci@f98a4900 { | ||
| 19 | cd-gpios = <&msmgpio 62 0x1>; | ||
| 20 | bus-width = <4>; | ||
| 21 | }; | ||
| 22 | |||
| 23 | |||
| 24 | pinctrl@fd510000 { | ||
| 25 | spi8_default: spi8_default { | ||
| 26 | mosi { | ||
| 27 | pins = "gpio45"; | ||
| 28 | function = "blsp_spi8"; | ||
| 29 | }; | ||
| 30 | miso { | ||
| 31 | pins = "gpio46"; | ||
| 32 | function = "blsp_spi8"; | ||
| 33 | }; | ||
| 34 | cs { | ||
| 35 | pins = "gpio47"; | ||
| 36 | function = "blsp_spi8"; | ||
| 37 | }; | ||
| 38 | clk { | ||
| 39 | pins = "gpio48"; | ||
| 40 | function = "blsp_spi8"; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | }; | ||
| 44 | }; | ||
| 6 | }; | 45 | }; |
diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts new file mode 100644 index 000000000000..9dae3878b71d --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #include "qcom-apq8084.dtsi" | ||
| 2 | |||
| 3 | / { | ||
| 4 | model = "Qualcomm APQ 8084-MTP"; | ||
| 5 | compatible = "qcom,apq8084-mtp", "qcom,apq8084"; | ||
| 6 | }; | ||
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi new file mode 100644 index 000000000000..e3e009a5912b --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi | |||
| @@ -0,0 +1,179 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | #include "skeleton.dtsi" | ||
| 4 | |||
| 5 | / { | ||
| 6 | model = "Qualcomm APQ 8084"; | ||
| 7 | compatible = "qcom,apq8084"; | ||
| 8 | interrupt-parent = <&intc>; | ||
| 9 | |||
| 10 | cpus { | ||
| 11 | #address-cells = <1>; | ||
| 12 | #size-cells = <0>; | ||
| 13 | |||
| 14 | cpu@0 { | ||
| 15 | device_type = "cpu"; | ||
| 16 | compatible = "qcom,krait"; | ||
| 17 | reg = <0>; | ||
| 18 | enable-method = "qcom,kpss-acc-v2"; | ||
| 19 | next-level-cache = <&L2>; | ||
| 20 | qcom,acc = <&acc0>; | ||
| 21 | }; | ||
| 22 | |||
| 23 | cpu@1 { | ||
| 24 | device_type = "cpu"; | ||
| 25 | compatible = "qcom,krait"; | ||
| 26 | reg = <1>; | ||
| 27 | enable-method = "qcom,kpss-acc-v2"; | ||
| 28 | next-level-cache = <&L2>; | ||
| 29 | qcom,acc = <&acc1>; | ||
| 30 | }; | ||
| 31 | |||
| 32 | cpu@2 { | ||
| 33 | device_type = "cpu"; | ||
| 34 | compatible = "qcom,krait"; | ||
| 35 | reg = <2>; | ||
| 36 | enable-method = "qcom,kpss-acc-v2"; | ||
| 37 | next-level-cache = <&L2>; | ||
| 38 | qcom,acc = <&acc2>; | ||
| 39 | }; | ||
| 40 | |||
| 41 | cpu@3 { | ||
| 42 | device_type = "cpu"; | ||
| 43 | compatible = "qcom,krait"; | ||
| 44 | reg = <3>; | ||
| 45 | enable-method = "qcom,kpss-acc-v2"; | ||
| 46 | next-level-cache = <&L2>; | ||
| 47 | qcom,acc = <&acc3>; | ||
| 48 | }; | ||
| 49 | |||
| 50 | L2: l2-cache { | ||
| 51 | compatible = "qcom,arch-cache"; | ||
| 52 | cache-level = <2>; | ||
| 53 | qcom,saw = <&saw_l2>; | ||
| 54 | }; | ||
| 55 | }; | ||
| 56 | |||
| 57 | cpu-pmu { | ||
| 58 | compatible = "qcom,krait-pmu"; | ||
| 59 | interrupts = <1 7 0xf04>; | ||
| 60 | }; | ||
| 61 | |||
| 62 | timer { | ||
| 63 | compatible = "arm,armv7-timer"; | ||
| 64 | interrupts = <1 2 0xf08>, | ||
| 65 | <1 3 0xf08>, | ||
| 66 | <1 4 0xf08>, | ||
| 67 | <1 1 0xf08>; | ||
| 68 | clock-frequency = <19200000>; | ||
| 69 | }; | ||
| 70 | |||
| 71 | soc: soc { | ||
| 72 | #address-cells = <1>; | ||
| 73 | #size-cells = <1>; | ||
| 74 | ranges; | ||
| 75 | compatible = "simple-bus"; | ||
| 76 | |||
| 77 | intc: interrupt-controller@f9000000 { | ||
| 78 | compatible = "qcom,msm-qgic2"; | ||
| 79 | interrupt-controller; | ||
| 80 | #interrupt-cells = <3>; | ||
| 81 | reg = <0xf9000000 0x1000>, | ||
| 82 | <0xf9002000 0x1000>; | ||
| 83 | }; | ||
| 84 | |||
| 85 | timer@f9020000 { | ||
| 86 | #address-cells = <1>; | ||
| 87 | #size-cells = <1>; | ||
| 88 | ranges; | ||
| 89 | compatible = "arm,armv7-timer-mem"; | ||
| 90 | reg = <0xf9020000 0x1000>; | ||
| 91 | clock-frequency = <19200000>; | ||
| 92 | |||
| 93 | frame@f9021000 { | ||
| 94 | frame-number = <0>; | ||
| 95 | interrupts = <0 8 0x4>, | ||
| 96 | <0 7 0x4>; | ||
| 97 | reg = <0xf9021000 0x1000>, | ||
| 98 | <0xf9022000 0x1000>; | ||
| 99 | }; | ||
| 100 | |||
| 101 | frame@f9023000 { | ||
| 102 | frame-number = <1>; | ||
| 103 | interrupts = <0 9 0x4>; | ||
| 104 | reg = <0xf9023000 0x1000>; | ||
| 105 | status = "disabled"; | ||
| 106 | }; | ||
| 107 | |||
| 108 | frame@f9024000 { | ||
| 109 | frame-number = <2>; | ||
| 110 | interrupts = <0 10 0x4>; | ||
| 111 | reg = <0xf9024000 0x1000>; | ||
| 112 | status = "disabled"; | ||
| 113 | }; | ||
| 114 | |||
| 115 | frame@f9025000 { | ||
| 116 | frame-number = <3>; | ||
| 117 | interrupts = <0 11 0x4>; | ||
| 118 | reg = <0xf9025000 0x1000>; | ||
| 119 | status = "disabled"; | ||
| 120 | }; | ||
| 121 | |||
| 122 | frame@f9026000 { | ||
| 123 | frame-number = <4>; | ||
| 124 | interrupts = <0 12 0x4>; | ||
| 125 | reg = <0xf9026000 0x1000>; | ||
| 126 | status = "disabled"; | ||
| 127 | }; | ||
| 128 | |||
| 129 | frame@f9027000 { | ||
| 130 | frame-number = <5>; | ||
| 131 | interrupts = <0 13 0x4>; | ||
| 132 | reg = <0xf9027000 0x1000>; | ||
| 133 | status = "disabled"; | ||
| 134 | }; | ||
| 135 | |||
| 136 | frame@f9028000 { | ||
| 137 | frame-number = <6>; | ||
| 138 | interrupts = <0 14 0x4>; | ||
| 139 | reg = <0xf9028000 0x1000>; | ||
| 140 | status = "disabled"; | ||
| 141 | }; | ||
| 142 | }; | ||
| 143 | |||
| 144 | saw_l2: regulator@f9012000 { | ||
| 145 | compatible = "qcom,saw2"; | ||
| 146 | reg = <0xf9012000 0x1000>; | ||
| 147 | regulator; | ||
| 148 | }; | ||
| 149 | |||
| 150 | acc0: clock-controller@f9088000 { | ||
| 151 | compatible = "qcom,kpss-acc-v2"; | ||
| 152 | reg = <0xf9088000 0x1000>, | ||
| 153 | <0xf9008000 0x1000>; | ||
| 154 | }; | ||
| 155 | |||
| 156 | acc1: clock-controller@f9098000 { | ||
| 157 | compatible = "qcom,kpss-acc-v2"; | ||
| 158 | reg = <0xf9098000 0x1000>, | ||
| 159 | <0xf9008000 0x1000>; | ||
| 160 | }; | ||
| 161 | |||
| 162 | acc2: clock-controller@f90a8000 { | ||
| 163 | compatible = "qcom,kpss-acc-v2"; | ||
| 164 | reg = <0xf90a8000 0x1000>, | ||
| 165 | <0xf9008000 0x1000>; | ||
| 166 | }; | ||
| 167 | |||
| 168 | acc3: clock-controller@f90b8000 { | ||
| 169 | compatible = "qcom,kpss-acc-v2"; | ||
| 170 | reg = <0xf90b8000 0x1000>, | ||
| 171 | <0xf9008000 0x1000>; | ||
| 172 | }; | ||
| 173 | |||
| 174 | restart@fc4ab000 { | ||
| 175 | compatible = "qcom,pshold"; | ||
| 176 | reg = <0xfc4ab000 0x4>; | ||
| 177 | }; | ||
| 178 | }; | ||
| 179 | }; | ||
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts index 169bad90dac9..45180adfadf1 100644 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts | |||
| @@ -3,4 +3,14 @@ | |||
| 3 | / { | 3 | / { |
| 4 | model = "Qualcomm MSM8660 SURF"; | 4 | model = "Qualcomm MSM8660 SURF"; |
| 5 | compatible = "qcom,msm8660-surf", "qcom,msm8660"; | 5 | compatible = "qcom,msm8660-surf", "qcom,msm8660"; |
| 6 | |||
| 7 | soc { | ||
| 8 | gsbi@19c00000 { | ||
| 9 | status = "ok"; | ||
| 10 | qcom,mode = <GSBI_PROT_I2C_UART>; | ||
| 11 | serial@19c40000 { | ||
| 12 | status = "ok"; | ||
| 13 | }; | ||
| 14 | }; | ||
| 15 | }; | ||
| 6 | }; | 16 | }; |
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index c52a9e964a44..53837aaa2f72 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi | |||
| @@ -3,6 +3,7 @@ | |||
| 3 | /include/ "skeleton.dtsi" | 3 | /include/ "skeleton.dtsi" |
| 4 | 4 | ||
| 5 | #include <dt-bindings/clock/qcom,gcc-msm8660.h> | 5 | #include <dt-bindings/clock/qcom,gcc-msm8660.h> |
| 6 | #include <dt-bindings/soc/qcom,gsbi.h> | ||
| 6 | 7 | ||
| 7 | / { | 8 | / { |
| 8 | model = "Qualcomm MSM8660"; | 9 | model = "Qualcomm MSM8660"; |
| @@ -12,16 +13,18 @@ | |||
| 12 | cpus { | 13 | cpus { |
| 13 | #address-cells = <1>; | 14 | #address-cells = <1>; |
| 14 | #size-cells = <0>; | 15 | #size-cells = <0>; |
| 15 | compatible = "qcom,scorpion"; | ||
| 16 | enable-method = "qcom,gcc-msm8660"; | ||
| 17 | 16 | ||
| 18 | cpu@0 { | 17 | cpu@0 { |
| 18 | compatible = "qcom,scorpion"; | ||
| 19 | enable-method = "qcom,gcc-msm8660"; | ||
| 19 | device_type = "cpu"; | 20 | device_type = "cpu"; |
| 20 | reg = <0>; | 21 | reg = <0>; |
| 21 | next-level-cache = <&L2>; | 22 | next-level-cache = <&L2>; |
| 22 | }; | 23 | }; |
| 23 | 24 | ||
| 24 | cpu@1 { | 25 | cpu@1 { |
| 26 | compatible = "qcom,scorpion"; | ||
| 27 | enable-method = "qcom,gcc-msm8660"; | ||
| 25 | device_type = "cpu"; | 28 | device_type = "cpu"; |
| 26 | reg = <1>; | 29 | reg = <1>; |
| 27 | next-level-cache = <&L2>; | 30 | next-level-cache = <&L2>; |
| @@ -33,55 +36,73 @@ | |||
| 33 | }; | 36 | }; |
| 34 | }; | 37 | }; |
| 35 | 38 | ||
| 36 | intc: interrupt-controller@2080000 { | 39 | soc: soc { |
| 37 | compatible = "qcom,msm-8660-qgic"; | 40 | #address-cells = <1>; |
| 38 | interrupt-controller; | 41 | #size-cells = <1>; |
| 39 | #interrupt-cells = <3>; | 42 | ranges; |
| 40 | reg = < 0x02080000 0x1000 >, | 43 | compatible = "simple-bus"; |
| 41 | < 0x02081000 0x1000 >; | ||
| 42 | }; | ||
| 43 | 44 | ||
| 44 | timer@2000000 { | 45 | intc: interrupt-controller@2080000 { |
| 45 | compatible = "qcom,scss-timer", "qcom,msm-timer"; | 46 | compatible = "qcom,msm-8660-qgic"; |
| 46 | interrupts = <1 0 0x301>, | 47 | interrupt-controller; |
| 47 | <1 1 0x301>, | 48 | #interrupt-cells = <3>; |
| 48 | <1 2 0x301>; | 49 | reg = < 0x02080000 0x1000 >, |
| 49 | reg = <0x02000000 0x100>; | 50 | < 0x02081000 0x1000 >; |
| 50 | clock-frequency = <27000000>, | 51 | }; |
| 51 | <32768>; | ||
| 52 | cpu-offset = <0x40000>; | ||
| 53 | }; | ||
| 54 | 52 | ||
| 55 | msmgpio: gpio@800000 { | 53 | timer@2000000 { |
| 56 | compatible = "qcom,msm-gpio"; | 54 | compatible = "qcom,scss-timer", "qcom,msm-timer"; |
| 57 | reg = <0x00800000 0x4000>; | 55 | interrupts = <1 0 0x301>, |
| 58 | gpio-controller; | 56 | <1 1 0x301>, |
| 59 | #gpio-cells = <2>; | 57 | <1 2 0x301>; |
| 60 | ngpio = <173>; | 58 | reg = <0x02000000 0x100>; |
| 61 | interrupts = <0 16 0x4>; | 59 | clock-frequency = <27000000>, |
| 62 | interrupt-controller; | 60 | <32768>; |
| 63 | #interrupt-cells = <2>; | 61 | cpu-offset = <0x40000>; |
| 64 | }; | 62 | }; |
| 65 | 63 | ||
| 66 | gcc: clock-controller@900000 { | 64 | msmgpio: gpio@800000 { |
| 67 | compatible = "qcom,gcc-msm8660"; | 65 | compatible = "qcom,msm-gpio"; |
| 68 | #clock-cells = <1>; | 66 | reg = <0x00800000 0x4000>; |
| 69 | #reset-cells = <1>; | 67 | gpio-controller; |
| 70 | reg = <0x900000 0x4000>; | 68 | #gpio-cells = <2>; |
| 71 | }; | 69 | ngpio = <173>; |
| 70 | interrupts = <0 16 0x4>; | ||
| 71 | interrupt-controller; | ||
| 72 | #interrupt-cells = <2>; | ||
| 73 | }; | ||
| 72 | 74 | ||
| 73 | serial@19c40000 { | 75 | gcc: clock-controller@900000 { |
| 74 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | 76 | compatible = "qcom,gcc-msm8660"; |
| 75 | reg = <0x19c40000 0x1000>, | 77 | #clock-cells = <1>; |
| 76 | <0x19c00000 0x1000>; | 78 | #reset-cells = <1>; |
| 77 | interrupts = <0 195 0x0>; | 79 | reg = <0x900000 0x4000>; |
| 78 | clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; | 80 | }; |
| 79 | clock-names = "core", "iface"; | 81 | |
| 80 | }; | 82 | gsbi12: gsbi@19c00000 { |
| 83 | compatible = "qcom,gsbi-v1.0.0"; | ||
| 84 | reg = <0x19c00000 0x100>; | ||
| 85 | clocks = <&gcc GSBI12_H_CLK>; | ||
| 86 | clock-names = "iface"; | ||
| 87 | #address-cells = <1>; | ||
| 88 | #size-cells = <1>; | ||
| 89 | ranges; | ||
| 81 | 90 | ||
| 82 | qcom,ssbi@500000 { | 91 | serial@19c40000 { |
| 83 | compatible = "qcom,ssbi"; | 92 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
| 84 | reg = <0x500000 0x1000>; | 93 | reg = <0x19c40000 0x1000>, |
| 85 | qcom,controller-type = "pmic-arbiter"; | 94 | <0x19c00000 0x1000>; |
| 95 | interrupts = <0 195 0x0>; | ||
| 96 | clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; | ||
| 97 | clock-names = "core", "iface"; | ||
| 98 | status = "disabled"; | ||
| 99 | }; | ||
| 100 | }; | ||
| 101 | |||
| 102 | qcom,ssbi@500000 { | ||
| 103 | compatible = "qcom,ssbi"; | ||
| 104 | reg = <0x500000 0x1000>; | ||
| 105 | qcom,controller-type = "pmic-arbiter"; | ||
| 106 | }; | ||
| 86 | }; | 107 | }; |
| 87 | }; | 108 | }; |
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index a58fb88315f6..8f75cc4c8340 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts | |||
| @@ -3,4 +3,14 @@ | |||
| 3 | / { | 3 | / { |
| 4 | model = "Qualcomm MSM8960 CDP"; | 4 | model = "Qualcomm MSM8960 CDP"; |
| 5 | compatible = "qcom,msm8960-cdp", "qcom,msm8960"; | 5 | compatible = "qcom,msm8960-cdp", "qcom,msm8960"; |
| 6 | |||
| 7 | soc { | ||
| 8 | gsbi@16400000 { | ||
| 9 | status = "ok"; | ||
| 10 | qcom,mode = <GSBI_PROT_I2C_UART>; | ||
| 11 | serial@16440000 { | ||
| 12 | status = "ok"; | ||
| 13 | }; | ||
| 14 | }; | ||
| 15 | }; | ||
| 6 | }; | 16 | }; |
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 997b7b94e117..5303e53e34dc 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi | |||
| @@ -3,6 +3,7 @@ | |||
| 3 | /include/ "skeleton.dtsi" | 3 | /include/ "skeleton.dtsi" |
| 4 | 4 | ||
| 5 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> | 5 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> |
| 6 | #include <dt-bindings/soc/qcom,gsbi.h> | ||
| 6 | 7 | ||
| 7 | / { | 8 | / { |
| 8 | model = "Qualcomm MSM8960"; | 9 | model = "Qualcomm MSM8960"; |
| @@ -13,10 +14,10 @@ | |||
| 13 | #address-cells = <1>; | 14 | #address-cells = <1>; |
| 14 | #size-cells = <0>; | 15 | #size-cells = <0>; |
| 15 | interrupts = <1 14 0x304>; | 16 | interrupts = <1 14 0x304>; |
| 16 | compatible = "qcom,krait"; | ||
| 17 | enable-method = "qcom,kpss-acc-v1"; | ||
| 18 | 17 | ||
| 19 | cpu@0 { | 18 | cpu@0 { |
| 19 | compatible = "qcom,krait"; | ||
| 20 | enable-method = "qcom,kpss-acc-v1"; | ||
| 20 | device_type = "cpu"; | 21 | device_type = "cpu"; |
| 21 | reg = <0>; | 22 | reg = <0>; |
| 22 | next-level-cache = <&L2>; | 23 | next-level-cache = <&L2>; |
| @@ -25,6 +26,8 @@ | |||
| 25 | }; | 26 | }; |
| 26 | 27 | ||
| 27 | cpu@1 { | 28 | cpu@1 { |
| 29 | compatible = "qcom,krait"; | ||
| 30 | enable-method = "qcom,kpss-acc-v1"; | ||
| 28 | device_type = "cpu"; | 31 | device_type = "cpu"; |
| 29 | reg = <1>; | 32 | reg = <1>; |
| 30 | next-level-cache = <&L2>; | 33 | next-level-cache = <&L2>; |
| @@ -35,7 +38,6 @@ | |||
| 35 | L2: l2-cache { | 38 | L2: l2-cache { |
| 36 | compatible = "cache"; | 39 | compatible = "cache"; |
| 37 | cache-level = <2>; | 40 | cache-level = <2>; |
| 38 | interrupts = <0 2 0x4>; | ||
| 39 | }; | 41 | }; |
| 40 | }; | 42 | }; |
| 41 | 43 | ||
| @@ -45,91 +47,109 @@ | |||
| 45 | qcom,no-pc-write; | 47 | qcom,no-pc-write; |
| 46 | }; | 48 | }; |
| 47 | 49 | ||
| 48 | intc: interrupt-controller@2000000 { | 50 | soc: soc { |
| 49 | compatible = "qcom,msm-qgic2"; | 51 | #address-cells = <1>; |
| 50 | interrupt-controller; | 52 | #size-cells = <1>; |
| 51 | #interrupt-cells = <3>; | 53 | ranges; |
| 52 | reg = < 0x02000000 0x1000 >, | 54 | compatible = "simple-bus"; |
| 53 | < 0x02002000 0x1000 >; | 55 | |
| 54 | }; | 56 | intc: interrupt-controller@2000000 { |
| 57 | compatible = "qcom,msm-qgic2"; | ||
| 58 | interrupt-controller; | ||
| 59 | #interrupt-cells = <3>; | ||
| 60 | reg = <0x02000000 0x1000>, | ||
| 61 | <0x02002000 0x1000>; | ||
| 62 | }; | ||
| 55 | 63 | ||
| 56 | timer@200a000 { | 64 | timer@200a000 { |
| 57 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; | 65 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; |
| 58 | interrupts = <1 1 0x301>, | 66 | interrupts = <1 1 0x301>, |
| 59 | <1 2 0x301>, | 67 | <1 2 0x301>, |
| 60 | <1 3 0x301>; | 68 | <1 3 0x301>; |
| 61 | reg = <0x0200a000 0x100>; | 69 | reg = <0x0200a000 0x100>; |
| 62 | clock-frequency = <27000000>, | 70 | clock-frequency = <27000000>, |
| 63 | <32768>; | 71 | <32768>; |
| 64 | cpu-offset = <0x80000>; | 72 | cpu-offset = <0x80000>; |
| 65 | }; | 73 | }; |
| 66 | 74 | ||
| 67 | msmgpio: gpio@800000 { | 75 | msmgpio: gpio@800000 { |
| 68 | compatible = "qcom,msm-gpio"; | 76 | compatible = "qcom,msm-gpio"; |
| 69 | gpio-controller; | 77 | gpio-controller; |
| 70 | #gpio-cells = <2>; | 78 | #gpio-cells = <2>; |
| 71 | ngpio = <150>; | 79 | ngpio = <150>; |
| 72 | interrupts = <0 16 0x4>; | 80 | interrupts = <0 16 0x4>; |
| 73 | interrupt-controller; | 81 | interrupt-controller; |
| 74 | #interrupt-cells = <2>; | 82 | #interrupt-cells = <2>; |
| 75 | reg = <0x800000 0x4000>; | 83 | reg = <0x800000 0x4000>; |
| 76 | }; | 84 | }; |
| 77 | 85 | ||
| 78 | gcc: clock-controller@900000 { | 86 | gcc: clock-controller@900000 { |
| 79 | compatible = "qcom,gcc-msm8960"; | 87 | compatible = "qcom,gcc-msm8960"; |
| 80 | #clock-cells = <1>; | 88 | #clock-cells = <1>; |
| 81 | #reset-cells = <1>; | 89 | #reset-cells = <1>; |
| 82 | reg = <0x900000 0x4000>; | 90 | reg = <0x900000 0x4000>; |
| 83 | }; | 91 | }; |
| 84 | 92 | ||
| 85 | clock-controller@4000000 { | 93 | clock-controller@4000000 { |
| 86 | compatible = "qcom,mmcc-msm8960"; | 94 | compatible = "qcom,mmcc-msm8960"; |
| 87 | reg = <0x4000000 0x1000>; | 95 | reg = <0x4000000 0x1000>; |
| 88 | #clock-cells = <1>; | 96 | #clock-cells = <1>; |
| 89 | #reset-cells = <1>; | 97 | #reset-cells = <1>; |
| 90 | }; | 98 | }; |
| 91 | 99 | ||
| 92 | acc0: clock-controller@2088000 { | 100 | acc0: clock-controller@2088000 { |
| 93 | compatible = "qcom,kpss-acc-v1"; | 101 | compatible = "qcom,kpss-acc-v1"; |
| 94 | reg = <0x02088000 0x1000>, <0x02008000 0x1000>; | 102 | reg = <0x02088000 0x1000>, <0x02008000 0x1000>; |
| 95 | }; | 103 | }; |
| 96 | 104 | ||
| 97 | acc1: clock-controller@2098000 { | 105 | acc1: clock-controller@2098000 { |
| 98 | compatible = "qcom,kpss-acc-v1"; | 106 | compatible = "qcom,kpss-acc-v1"; |
| 99 | reg = <0x02098000 0x1000>, <0x02008000 0x1000>; | 107 | reg = <0x02098000 0x1000>, <0x02008000 0x1000>; |
| 100 | }; | 108 | }; |
| 101 | 109 | ||
| 102 | saw0: regulator@2089000 { | 110 | saw0: regulator@2089000 { |
| 103 | compatible = "qcom,saw2"; | 111 | compatible = "qcom,saw2"; |
| 104 | reg = <0x02089000 0x1000>, <0x02009000 0x1000>; | 112 | reg = <0x02089000 0x1000>, <0x02009000 0x1000>; |
| 105 | regulator; | 113 | regulator; |
| 106 | }; | 114 | }; |
| 107 | 115 | ||
| 108 | saw1: regulator@2099000 { | 116 | saw1: regulator@2099000 { |
| 109 | compatible = "qcom,saw2"; | 117 | compatible = "qcom,saw2"; |
| 110 | reg = <0x02099000 0x1000>, <0x02009000 0x1000>; | 118 | reg = <0x02099000 0x1000>, <0x02009000 0x1000>; |
| 111 | regulator; | 119 | regulator; |
| 112 | }; | 120 | }; |
| 113 | 121 | ||
| 114 | serial@16440000 { | 122 | gsbi5: gsbi@16400000 { |
| 115 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | 123 | compatible = "qcom,gsbi-v1.0.0"; |
| 116 | reg = <0x16440000 0x1000>, | 124 | reg = <0x16400000 0x100>; |
| 117 | <0x16400000 0x1000>; | 125 | clocks = <&gcc GSBI5_H_CLK>; |
| 118 | interrupts = <0 154 0x0>; | 126 | clock-names = "iface"; |
| 119 | clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; | 127 | #address-cells = <1>; |
| 120 | clock-names = "core", "iface"; | 128 | #size-cells = <1>; |
| 121 | }; | 129 | ranges; |
| 130 | |||
| 131 | serial@16440000 { | ||
| 132 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | ||
| 133 | reg = <0x16440000 0x1000>, | ||
| 134 | <0x16400000 0x1000>; | ||
| 135 | interrupts = <0 154 0x0>; | ||
| 136 | clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; | ||
| 137 | clock-names = "core", "iface"; | ||
| 138 | status = "disabled"; | ||
| 139 | }; | ||
| 140 | }; | ||
| 122 | 141 | ||
| 123 | qcom,ssbi@500000 { | 142 | qcom,ssbi@500000 { |
| 124 | compatible = "qcom,ssbi"; | 143 | compatible = "qcom,ssbi"; |
| 125 | reg = <0x500000 0x1000>; | 144 | reg = <0x500000 0x1000>; |
| 126 | qcom,controller-type = "pmic-arbiter"; | 145 | qcom,controller-type = "pmic-arbiter"; |
| 127 | }; | 146 | }; |
| 128 | 147 | ||
| 129 | rng@1a500000 { | 148 | rng@1a500000 { |
| 130 | compatible = "qcom,prng"; | 149 | compatible = "qcom,prng"; |
| 131 | reg = <0x1a500000 0x200>; | 150 | reg = <0x1a500000 0x200>; |
| 132 | clocks = <&gcc PRNG_CLK>; | 151 | clocks = <&gcc PRNG_CLK>; |
| 133 | clock-names = "core"; | 152 | clock-names = "core"; |
| 153 | }; | ||
| 134 | }; | 154 | }; |
| 135 | }; | 155 | }; |
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index f68723918b3f..69dca2aca25a 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi | |||
| @@ -13,10 +13,10 @@ | |||
| 13 | #address-cells = <1>; | 13 | #address-cells = <1>; |
| 14 | #size-cells = <0>; | 14 | #size-cells = <0>; |
| 15 | interrupts = <1 9 0xf04>; | 15 | interrupts = <1 9 0xf04>; |
| 16 | compatible = "qcom,krait"; | ||
| 17 | enable-method = "qcom,kpss-acc-v2"; | ||
| 18 | 16 | ||
| 19 | cpu@0 { | 17 | cpu@0 { |
| 18 | compatible = "qcom,krait"; | ||
| 19 | enable-method = "qcom,kpss-acc-v2"; | ||
| 20 | device_type = "cpu"; | 20 | device_type = "cpu"; |
| 21 | reg = <0>; | 21 | reg = <0>; |
| 22 | next-level-cache = <&L2>; | 22 | next-level-cache = <&L2>; |
| @@ -24,6 +24,8 @@ | |||
| 24 | }; | 24 | }; |
| 25 | 25 | ||
| 26 | cpu@1 { | 26 | cpu@1 { |
| 27 | compatible = "qcom,krait"; | ||
| 28 | enable-method = "qcom,kpss-acc-v2"; | ||
| 27 | device_type = "cpu"; | 29 | device_type = "cpu"; |
| 28 | reg = <1>; | 30 | reg = <1>; |
| 29 | next-level-cache = <&L2>; | 31 | next-level-cache = <&L2>; |
| @@ -31,6 +33,8 @@ | |||
| 31 | }; | 33 | }; |
| 32 | 34 | ||
| 33 | cpu@2 { | 35 | cpu@2 { |
| 36 | compatible = "qcom,krait"; | ||
| 37 | enable-method = "qcom,kpss-acc-v2"; | ||
| 34 | device_type = "cpu"; | 38 | device_type = "cpu"; |
| 35 | reg = <2>; | 39 | reg = <2>; |
| 36 | next-level-cache = <&L2>; | 40 | next-level-cache = <&L2>; |
| @@ -38,6 +42,8 @@ | |||
| 38 | }; | 42 | }; |
| 39 | 43 | ||
| 40 | cpu@3 { | 44 | cpu@3 { |
| 45 | compatible = "qcom,krait"; | ||
| 46 | enable-method = "qcom,kpss-acc-v2"; | ||
| 41 | device_type = "cpu"; | 47 | device_type = "cpu"; |
| 42 | reg = <3>; | 48 | reg = <3>; |
| 43 | next-level-cache = <&L2>; | 49 | next-level-cache = <&L2>; |
| @@ -47,7 +53,6 @@ | |||
| 47 | L2: l2-cache { | 53 | L2: l2-cache { |
| 48 | compatible = "cache"; | 54 | compatible = "cache"; |
| 49 | cache-level = <2>; | 55 | cache-level = <2>; |
| 50 | interrupts = <0 2 0x4>; | ||
| 51 | qcom,saw = <&saw_l2>; | 56 | qcom,saw = <&saw_l2>; |
| 52 | }; | 57 | }; |
| 53 | }; | 58 | }; |
| @@ -57,6 +62,15 @@ | |||
| 57 | interrupts = <1 7 0xf04>; | 62 | interrupts = <1 7 0xf04>; |
| 58 | }; | 63 | }; |
| 59 | 64 | ||
| 65 | timer { | ||
| 66 | compatible = "arm,armv7-timer"; | ||
| 67 | interrupts = <1 2 0xf08>, | ||
| 68 | <1 3 0xf08>, | ||
| 69 | <1 4 0xf08>, | ||
| 70 | <1 1 0xf08>; | ||
| 71 | clock-frequency = <19200000>; | ||
| 72 | }; | ||
| 73 | |||
| 60 | soc: soc { | 74 | soc: soc { |
| 61 | #address-cells = <1>; | 75 | #address-cells = <1>; |
| 62 | #size-cells = <1>; | 76 | #size-cells = <1>; |
| @@ -71,15 +85,6 @@ | |||
| 71 | <0xf9002000 0x1000>; | 85 | <0xf9002000 0x1000>; |
| 72 | }; | 86 | }; |
| 73 | 87 | ||
| 74 | timer { | ||
| 75 | compatible = "arm,armv7-timer"; | ||
| 76 | interrupts = <1 2 0xf08>, | ||
| 77 | <1 3 0xf08>, | ||
| 78 | <1 4 0xf08>, | ||
| 79 | <1 1 0xf08>; | ||
| 80 | clock-frequency = <19200000>; | ||
| 81 | }; | ||
| 82 | |||
| 83 | timer@f9020000 { | 88 | timer@f9020000 { |
| 84 | #address-cells = <1>; | 89 | #address-cells = <1>; |
| 85 | #size-cells = <1>; | 90 | #size-cells = <1>; |
| @@ -190,6 +195,29 @@ | |||
| 190 | interrupts = <0 108 0x0>; | 195 | interrupts = <0 108 0x0>; |
| 191 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; | 196 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; |
| 192 | clock-names = "core", "iface"; | 197 | clock-names = "core", "iface"; |
| 198 | status = "disabled"; | ||
| 199 | }; | ||
| 200 | |||
| 201 | sdhci@f9824900 { | ||
| 202 | compatible = "qcom,sdhci-msm-v4"; | ||
| 203 | reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; | ||
| 204 | reg-names = "hc_mem", "core_mem"; | ||
| 205 | interrupts = <0 123 0>, <0 138 0>; | ||
| 206 | interrupt-names = "hc_irq", "pwr_irq"; | ||
| 207 | clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; | ||
| 208 | clock-names = "core", "iface"; | ||
| 209 | status = "disabled"; | ||
| 210 | }; | ||
| 211 | |||
| 212 | sdhci@f98a4900 { | ||
| 213 | compatible = "qcom,sdhci-msm-v4"; | ||
| 214 | reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; | ||
| 215 | reg-names = "hc_mem", "core_mem"; | ||
| 216 | interrupts = <0 125 0>, <0 221 0>; | ||
| 217 | interrupt-names = "hc_irq", "pwr_irq"; | ||
| 218 | clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; | ||
| 219 | clock-names = "core", "iface"; | ||
| 220 | status = "disabled"; | ||
| 193 | }; | 221 | }; |
| 194 | 222 | ||
| 195 | rng@f9bff000 { | 223 | rng@f9bff000 { |
| @@ -198,5 +226,15 @@ | |||
| 198 | clocks = <&gcc GCC_PRNG_AHB_CLK>; | 226 | clocks = <&gcc GCC_PRNG_AHB_CLK>; |
| 199 | clock-names = "core"; | 227 | clock-names = "core"; |
| 200 | }; | 228 | }; |
| 229 | |||
| 230 | msmgpio: pinctrl@fd510000 { | ||
| 231 | compatible = "qcom,msm8974-pinctrl"; | ||
| 232 | reg = <0xfd510000 0x4000>; | ||
| 233 | gpio-controller; | ||
| 234 | #gpio-cells = <2>; | ||
| 235 | interrupt-controller; | ||
| 236 | #interrupt-cells = <2>; | ||
| 237 | interrupts = <0 208 0>; | ||
| 238 | }; | ||
| 201 | }; | 239 | }; |
| 202 | }; | 240 | }; |
diff --git a/arch/arm/boot/dts/r7s72100-genmai-reference.dts b/arch/arm/boot/dts/r7s72100-genmai-reference.dts deleted file mode 100644 index e664611a47c8..000000000000 --- a/arch/arm/boot/dts/r7s72100-genmai-reference.dts +++ /dev/null | |||
| @@ -1,42 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree Source for the Genmai board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Renesas Solutions Corp. | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public License | ||
| 7 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 8 | * kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /dts-v1/; | ||
| 12 | #include "r7s72100.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "Genmai"; | ||
| 16 | compatible = "renesas,genmai-reference", "renesas,r7s72100"; | ||
| 17 | |||
| 18 | chosen { | ||
| 19 | bootargs = "console=ttySC2,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; | ||
| 20 | }; | ||
| 21 | |||
| 22 | memory { | ||
| 23 | device_type = "memory"; | ||
| 24 | reg = <0x08000000 0x08000000>; | ||
| 25 | }; | ||
| 26 | |||
| 27 | lbsc { | ||
| 28 | #address-cells = <1>; | ||
| 29 | #size-cells = <1>; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | |||
| 33 | &i2c2 { | ||
| 34 | status = "okay"; | ||
| 35 | clock-frequency = <400000>; | ||
| 36 | |||
| 37 | eeprom@50 { | ||
| 38 | compatible = "renesas,24c128"; | ||
| 39 | reg = <0x50>; | ||
| 40 | pagesize = <64>; | ||
| 41 | }; | ||
| 42 | }; | ||
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index b1deaf7e2e06..56849b55e1c2 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts | |||
| @@ -1,7 +1,8 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Device Tree Source for the Genmai board | 2 | * Device Tree Source for the Genmai board |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2013 Renesas Solutions Corp. | 4 | * Copyright (C) 2013-14 Renesas Solutions Corp. |
| 5 | * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> | ||
| 5 | * | 6 | * |
| 6 | * This file is licensed under the terms of the GNU General Public License | 7 | * This file is licensed under the terms of the GNU General Public License |
| 7 | * version 2. This program is licensed "as is" without any warranty of any | 8 | * version 2. This program is licensed "as is" without any warranty of any |
| @@ -15,6 +16,10 @@ | |||
| 15 | model = "Genmai"; | 16 | model = "Genmai"; |
| 16 | compatible = "renesas,genmai", "renesas,r7s72100"; | 17 | compatible = "renesas,genmai", "renesas,r7s72100"; |
| 17 | 18 | ||
| 19 | aliases { | ||
| 20 | serial2 = &scif2; | ||
| 21 | }; | ||
| 22 | |||
| 18 | chosen { | 23 | chosen { |
| 19 | bootargs = "console=ttySC2,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; | 24 | bootargs = "console=ttySC2,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; |
| 20 | }; | 25 | }; |
| @@ -29,3 +34,26 @@ | |||
| 29 | #size-cells = <1>; | 34 | #size-cells = <1>; |
| 30 | }; | 35 | }; |
| 31 | }; | 36 | }; |
| 37 | |||
| 38 | &extal_clk { | ||
| 39 | clock-frequency = <13330000>; | ||
| 40 | }; | ||
| 41 | |||
| 42 | &usb_x1_clk { | ||
| 43 | clock-frequency = <48000000>; | ||
| 44 | }; | ||
| 45 | |||
| 46 | &i2c2 { | ||
| 47 | status = "okay"; | ||
| 48 | clock-frequency = <400000>; | ||
| 49 | |||
| 50 | eeprom@50 { | ||
| 51 | compatible = "renesas,24c128"; | ||
| 52 | reg = <0x50>; | ||
| 53 | pagesize = <64>; | ||
| 54 | }; | ||
| 55 | }; | ||
| 56 | |||
| 57 | &scif2 { | ||
| 58 | status = "okay"; | ||
| 59 | }; | ||
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index ee700717a34b..f50fbc8f3bd9 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi | |||
| @@ -1,13 +1,15 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Device Tree Source for the r7s72100 SoC | 2 | * Device Tree Source for the r7s72100 SoC |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2013 Renesas Solutions Corp. | 4 | * Copyright (C) 2013-14 Renesas Solutions Corp. |
| 5 | * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> | ||
| 5 | * | 6 | * |
| 6 | * This file is licensed under the terms of the GNU General Public License | 7 | * This file is licensed under the terms of the GNU General Public License |
| 7 | * version 2. This program is licensed "as is" without any warranty of any | 8 | * version 2. This program is licensed "as is" without any warranty of any |
| 8 | * kind, whether express or implied. | 9 | * kind, whether express or implied. |
| 9 | */ | 10 | */ |
| 10 | 11 | ||
| 12 | #include <dt-bindings/clock/r7s72100-clock.h> | ||
| 11 | #include <dt-bindings/interrupt-controller/irq.h> | 13 | #include <dt-bindings/interrupt-controller/irq.h> |
| 12 | 14 | ||
| 13 | / { | 15 | / { |
| @@ -28,6 +30,112 @@ | |||
| 28 | spi4 = &spi4; | 30 | spi4 = &spi4; |
| 29 | }; | 31 | }; |
| 30 | 32 | ||
| 33 | clocks { | ||
| 34 | ranges; | ||
| 35 | #address-cells = <1>; | ||
| 36 | #size-cells = <1>; | ||
| 37 | |||
| 38 | /* External clocks */ | ||
| 39 | extal_clk: extal_clk { | ||
| 40 | #clock-cells = <0>; | ||
| 41 | compatible = "fixed-clock"; | ||
| 42 | /* If clk present, value must be set by board */ | ||
| 43 | clock-frequency = <0>; | ||
| 44 | clock-output-names = "extal"; | ||
| 45 | }; | ||
| 46 | |||
| 47 | usb_x1_clk: usb_x1_clk { | ||
| 48 | #clock-cells = <0>; | ||
| 49 | compatible = "fixed-clock"; | ||
| 50 | /* If clk present, value must be set by board */ | ||
| 51 | clock-frequency = <0>; | ||
| 52 | clock-output-names = "usb_x1"; | ||
| 53 | }; | ||
| 54 | |||
| 55 | /* Special CPG clocks */ | ||
| 56 | cpg_clocks: cpg_clocks@fcfe0000 { | ||
| 57 | #clock-cells = <1>; | ||
| 58 | compatible = "renesas,r7s72100-cpg-clocks", | ||
| 59 | "renesas,rz-cpg-clocks"; | ||
| 60 | reg = <0xfcfe0000 0x18>; | ||
| 61 | clocks = <&extal_clk>, <&usb_x1_clk>; | ||
| 62 | clock-output-names = "pll", "i", "g"; | ||
| 63 | }; | ||
| 64 | |||
| 65 | /* Fixed factor clocks */ | ||
| 66 | b_clk: b_clk { | ||
| 67 | #clock-cells = <0>; | ||
| 68 | compatible = "fixed-factor-clock"; | ||
| 69 | clocks = <&cpg_clocks R7S72100_CLK_PLL>; | ||
| 70 | clock-mult = <1>; | ||
| 71 | clock-div = <3>; | ||
| 72 | clock-output-names = "b"; | ||
| 73 | }; | ||
| 74 | p1_clk: p1_clk { | ||
| 75 | #clock-cells = <0>; | ||
| 76 | compatible = "fixed-factor-clock"; | ||
| 77 | clocks = <&cpg_clocks R7S72100_CLK_PLL>; | ||
| 78 | clock-mult = <1>; | ||
| 79 | clock-div = <6>; | ||
| 80 | clock-output-names = "p1"; | ||
| 81 | }; | ||
| 82 | p0_clk: p0_clk { | ||
| 83 | #clock-cells = <0>; | ||
| 84 | compatible = "fixed-factor-clock"; | ||
| 85 | clocks = <&cpg_clocks R7S72100_CLK_PLL>; | ||
| 86 | clock-mult = <1>; | ||
| 87 | clock-div = <12>; | ||
| 88 | clock-output-names = "p0"; | ||
| 89 | }; | ||
| 90 | |||
| 91 | /* MSTP clocks */ | ||
| 92 | mstp3_clks: mstp3_clks@fcfe0420 { | ||
| 93 | #clock-cells = <1>; | ||
| 94 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | ||
| 95 | reg = <0xfcfe0420 4>; | ||
| 96 | clocks = <&p0_clk>; | ||
| 97 | clock-indices = <R7S72100_CLK_MTU2>; | ||
| 98 | clock-output-names = "mtu2"; | ||
| 99 | }; | ||
| 100 | |||
| 101 | mstp4_clks: mstp4_clks@fcfe0424 { | ||
| 102 | #clock-cells = <1>; | ||
| 103 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | ||
| 104 | reg = <0xfcfe0424 4>; | ||
| 105 | clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, | ||
| 106 | <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; | ||
| 107 | clock-indices = < | ||
| 108 | R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 | ||
| 109 | R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 | ||
| 110 | >; | ||
| 111 | clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; | ||
| 112 | }; | ||
| 113 | |||
| 114 | mstp9_clks: mstp9_clks@fcfe0438 { | ||
| 115 | #clock-cells = <1>; | ||
| 116 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | ||
| 117 | reg = <0xfcfe0438 4>; | ||
| 118 | clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>; | ||
| 119 | clock-indices = < | ||
| 120 | R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 | ||
| 121 | >; | ||
| 122 | clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3"; | ||
| 123 | }; | ||
| 124 | |||
| 125 | mstp10_clks: mstp10_clks@fcfe043c { | ||
| 126 | #clock-cells = <1>; | ||
| 127 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | ||
| 128 | reg = <0xfcfe043c 4>; | ||
| 129 | clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, | ||
| 130 | <&p1_clk>; | ||
| 131 | clock-indices = < | ||
| 132 | R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 | ||
| 133 | R7S72100_CLK_SPI4 | ||
| 134 | >; | ||
| 135 | clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; | ||
| 136 | }; | ||
| 137 | }; | ||
| 138 | |||
| 31 | cpus { | 139 | cpus { |
| 32 | #address-cells = <1>; | 140 | #address-cells = <1>; |
| 33 | #size-cells = <0>; | 141 | #size-cells = <0>; |
| @@ -61,6 +169,7 @@ | |||
| 61 | <0 162 IRQ_TYPE_LEVEL_HIGH>, | 169 | <0 162 IRQ_TYPE_LEVEL_HIGH>, |
| 62 | <0 163 IRQ_TYPE_LEVEL_HIGH>, | 170 | <0 163 IRQ_TYPE_LEVEL_HIGH>, |
| 63 | <0 164 IRQ_TYPE_LEVEL_HIGH>; | 171 | <0 164 IRQ_TYPE_LEVEL_HIGH>; |
| 172 | clocks = <&mstp9_clks R7S72100_CLK_I2C0>; | ||
| 64 | clock-frequency = <100000>; | 173 | clock-frequency = <100000>; |
| 65 | status = "disabled"; | 174 | status = "disabled"; |
| 66 | }; | 175 | }; |
| @@ -78,6 +187,7 @@ | |||
| 78 | <0 170 IRQ_TYPE_LEVEL_HIGH>, | 187 | <0 170 IRQ_TYPE_LEVEL_HIGH>, |
| 79 | <0 171 IRQ_TYPE_LEVEL_HIGH>, | 188 | <0 171 IRQ_TYPE_LEVEL_HIGH>, |
| 80 | <0 172 IRQ_TYPE_LEVEL_HIGH>; | 189 | <0 172 IRQ_TYPE_LEVEL_HIGH>; |
| 190 | clocks = <&mstp9_clks R7S72100_CLK_I2C1>; | ||
| 81 | clock-frequency = <100000>; | 191 | clock-frequency = <100000>; |
| 82 | status = "disabled"; | 192 | status = "disabled"; |
| 83 | }; | 193 | }; |
| @@ -95,6 +205,7 @@ | |||
| 95 | <0 178 IRQ_TYPE_LEVEL_HIGH>, | 205 | <0 178 IRQ_TYPE_LEVEL_HIGH>, |
| 96 | <0 179 IRQ_TYPE_LEVEL_HIGH>, | 206 | <0 179 IRQ_TYPE_LEVEL_HIGH>, |
| 97 | <0 180 IRQ_TYPE_LEVEL_HIGH>; | 207 | <0 180 IRQ_TYPE_LEVEL_HIGH>; |
| 208 | clocks = <&mstp9_clks R7S72100_CLK_I2C2>; | ||
| 98 | clock-frequency = <100000>; | 209 | clock-frequency = <100000>; |
| 99 | status = "disabled"; | 210 | status = "disabled"; |
| 100 | }; | 211 | }; |
| @@ -112,10 +223,107 @@ | |||
| 112 | <0 186 IRQ_TYPE_LEVEL_HIGH>, | 223 | <0 186 IRQ_TYPE_LEVEL_HIGH>, |
| 113 | <0 187 IRQ_TYPE_LEVEL_HIGH>, | 224 | <0 187 IRQ_TYPE_LEVEL_HIGH>, |
| 114 | <0 188 IRQ_TYPE_LEVEL_HIGH>; | 225 | <0 188 IRQ_TYPE_LEVEL_HIGH>; |
| 226 | clocks = <&mstp9_clks R7S72100_CLK_I2C3>; | ||
| 115 | clock-frequency = <100000>; | 227 | clock-frequency = <100000>; |
| 116 | status = "disabled"; | 228 | status = "disabled"; |
| 117 | }; | 229 | }; |
| 118 | 230 | ||
| 231 | scif0: serial@e8007000 { | ||
| 232 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | ||
| 233 | reg = <0xe8007000 64>; | ||
| 234 | interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>, | ||
| 235 | <0 191 IRQ_TYPE_LEVEL_HIGH>, | ||
| 236 | <0 192 IRQ_TYPE_LEVEL_HIGH>, | ||
| 237 | <0 189 IRQ_TYPE_LEVEL_HIGH>; | ||
| 238 | clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; | ||
| 239 | clock-names = "sci_ick"; | ||
| 240 | status = "disabled"; | ||
| 241 | }; | ||
| 242 | |||
| 243 | scif1: serial@e8007800 { | ||
| 244 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | ||
| 245 | reg = <0xe8007800 64>; | ||
| 246 | interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>, | ||
| 247 | <0 195 IRQ_TYPE_LEVEL_HIGH>, | ||
| 248 | <0 196 IRQ_TYPE_LEVEL_HIGH>, | ||
| 249 | <0 193 IRQ_TYPE_LEVEL_HIGH>; | ||
| 250 | clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; | ||
| 251 | clock-names = "sci_ick"; | ||
| 252 | status = "disabled"; | ||
| 253 | }; | ||
| 254 | |||
| 255 | scif2: serial@e8008000 { | ||
| 256 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | ||
| 257 | reg = <0xe8008000 64>; | ||
| 258 | interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, | ||
| 259 | <0 199 IRQ_TYPE_LEVEL_HIGH>, | ||
| 260 | <0 200 IRQ_TYPE_LEVEL_HIGH>, | ||
| 261 | <0 197 IRQ_TYPE_LEVEL_HIGH>; | ||
| 262 | clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; | ||
| 263 | clock-names = "sci_ick"; | ||
| 264 | status = "disabled"; | ||
| 265 | }; | ||
| 266 | |||
| 267 | scif3: serial@e8008800 { | ||
| 268 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | ||
| 269 | reg = <0xe8008800 64>; | ||
| 270 | interrupts = <0 202 IRQ_TYPE_LEVEL_HIGH>, | ||
| 271 | <0 203 IRQ_TYPE_LEVEL_HIGH>, | ||
| 272 | <0 204 IRQ_TYPE_LEVEL_HIGH>, | ||
| 273 | <0 201 IRQ_TYPE_LEVEL_HIGH>; | ||
| 274 | clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; | ||
| 275 | clock-names = "sci_ick"; | ||
| 276 | status = "disabled"; | ||
| 277 | }; | ||
| 278 | |||
| 279 | scif4: serial@e8009000 { | ||
| 280 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | ||
| 281 | reg = <0xe8009000 64>; | ||
| 282 | interrupts = <0 206 IRQ_TYPE_LEVEL_HIGH>, | ||
| 283 | <0 207 IRQ_TYPE_LEVEL_HIGH>, | ||
| 284 | <0 208 IRQ_TYPE_LEVEL_HIGH>, | ||
| 285 | <0 205 IRQ_TYPE_LEVEL_HIGH>; | ||
| 286 | clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; | ||
| 287 | clock-names = "sci_ick"; | ||
| 288 | status = "disabled"; | ||
| 289 | }; | ||
| 290 | |||
| 291 | scif5: serial@e8009800 { | ||
| 292 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | ||
| 293 | reg = <0xe8009800 64>; | ||
| 294 | interrupts = <0 210 IRQ_TYPE_LEVEL_HIGH>, | ||
| 295 | <0 211 IRQ_TYPE_LEVEL_HIGH>, | ||
| 296 | <0 212 IRQ_TYPE_LEVEL_HIGH>, | ||
| 297 | <0 209 IRQ_TYPE_LEVEL_HIGH>; | ||
| 298 | clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; | ||
| 299 | clock-names = "sci_ick"; | ||
| 300 | status = "disabled"; | ||
| 301 | }; | ||
| 302 | |||
| 303 | scif6: serial@e800a000 { | ||
| 304 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | ||
| 305 | reg = <0xe800a000 64>; | ||
| 306 | interrupts = <0 214 IRQ_TYPE_LEVEL_HIGH>, | ||
| 307 | <0 215 IRQ_TYPE_LEVEL_HIGH>, | ||
| 308 | <0 216 IRQ_TYPE_LEVEL_HIGH>, | ||
| 309 | <0 213 IRQ_TYPE_LEVEL_HIGH>; | ||
| 310 | clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; | ||
| 311 | clock-names = "sci_ick"; | ||
| 312 | status = "disabled"; | ||
| 313 | }; | ||
| 314 | |||
| 315 | scif7: serial@e800a800 { | ||
| 316 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | ||
| 317 | reg = <0xe800a800 64>; | ||
| 318 | interrupts = <0 218 IRQ_TYPE_LEVEL_HIGH>, | ||
| 319 | <0 219 IRQ_TYPE_LEVEL_HIGH>, | ||
| 320 | <0 220 IRQ_TYPE_LEVEL_HIGH>, | ||
| 321 | <0 217 IRQ_TYPE_LEVEL_HIGH>; | ||
| 322 | clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; | ||
| 323 | clock-names = "sci_ick"; | ||
| 324 | status = "disabled"; | ||
| 325 | }; | ||
| 326 | |||
| 119 | spi0: spi@e800c800 { | 327 | spi0: spi@e800c800 { |
| 120 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; | 328 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; |
| 121 | reg = <0xe800c800 0x24>; | 329 | reg = <0xe800c800 0x24>; |
| @@ -123,6 +331,7 @@ | |||
| 123 | <0 239 IRQ_TYPE_LEVEL_HIGH>, | 331 | <0 239 IRQ_TYPE_LEVEL_HIGH>, |
| 124 | <0 240 IRQ_TYPE_LEVEL_HIGH>; | 332 | <0 240 IRQ_TYPE_LEVEL_HIGH>; |
| 125 | interrupt-names = "error", "rx", "tx"; | 333 | interrupt-names = "error", "rx", "tx"; |
| 334 | clocks = <&mstp10_clks R7S72100_CLK_SPI0>; | ||
| 126 | num-cs = <1>; | 335 | num-cs = <1>; |
| 127 | #address-cells = <1>; | 336 | #address-cells = <1>; |
| 128 | #size-cells = <0>; | 337 | #size-cells = <0>; |
| @@ -136,6 +345,7 @@ | |||
| 136 | <0 242 IRQ_TYPE_LEVEL_HIGH>, | 345 | <0 242 IRQ_TYPE_LEVEL_HIGH>, |
| 137 | <0 243 IRQ_TYPE_LEVEL_HIGH>; | 346 | <0 243 IRQ_TYPE_LEVEL_HIGH>; |
| 138 | interrupt-names = "error", "rx", "tx"; | 347 | interrupt-names = "error", "rx", "tx"; |
| 348 | clocks = <&mstp10_clks R7S72100_CLK_SPI1>; | ||
| 139 | num-cs = <1>; | 349 | num-cs = <1>; |
| 140 | #address-cells = <1>; | 350 | #address-cells = <1>; |
| 141 | #size-cells = <0>; | 351 | #size-cells = <0>; |
| @@ -149,6 +359,7 @@ | |||
| 149 | <0 245 IRQ_TYPE_LEVEL_HIGH>, | 359 | <0 245 IRQ_TYPE_LEVEL_HIGH>, |
| 150 | <0 246 IRQ_TYPE_LEVEL_HIGH>; | 360 | <0 246 IRQ_TYPE_LEVEL_HIGH>; |
| 151 | interrupt-names = "error", "rx", "tx"; | 361 | interrupt-names = "error", "rx", "tx"; |
| 362 | clocks = <&mstp10_clks R7S72100_CLK_SPI2>; | ||
| 152 | num-cs = <1>; | 363 | num-cs = <1>; |
| 153 | #address-cells = <1>; | 364 | #address-cells = <1>; |
| 154 | #size-cells = <0>; | 365 | #size-cells = <0>; |
| @@ -162,6 +373,7 @@ | |||
| 162 | <0 248 IRQ_TYPE_LEVEL_HIGH>, | 373 | <0 248 IRQ_TYPE_LEVEL_HIGH>, |
| 163 | <0 249 IRQ_TYPE_LEVEL_HIGH>; | 374 | <0 249 IRQ_TYPE_LEVEL_HIGH>; |
| 164 | interrupt-names = "error", "rx", "tx"; | 375 | interrupt-names = "error", "rx", "tx"; |
| 376 | clocks = <&mstp10_clks R7S72100_CLK_SPI3>; | ||
| 165 | num-cs = <1>; | 377 | num-cs = <1>; |
| 166 | #address-cells = <1>; | 378 | #address-cells = <1>; |
| 167 | #size-cells = <0>; | 379 | #size-cells = <0>; |
| @@ -175,6 +387,7 @@ | |||
| 175 | <0 251 IRQ_TYPE_LEVEL_HIGH>, | 387 | <0 251 IRQ_TYPE_LEVEL_HIGH>, |
| 176 | <0 252 IRQ_TYPE_LEVEL_HIGH>; | 388 | <0 252 IRQ_TYPE_LEVEL_HIGH>; |
| 177 | interrupt-names = "error", "rx", "tx"; | 389 | interrupt-names = "error", "rx", "tx"; |
| 390 | clocks = <&mstp10_clks R7S72100_CLK_SPI4>; | ||
| 178 | num-cs = <1>; | 391 | num-cs = <1>; |
| 179 | #address-cells = <1>; | 392 | #address-cells = <1>; |
| 180 | #size-cells = <0>; | 393 | #size-cells = <0>; |
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 62d0211bd192..82c5ac825386 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi | |||
| @@ -55,7 +55,6 @@ | |||
| 55 | #interrupt-cells = <2>; | 55 | #interrupt-cells = <2>; |
| 56 | interrupt-controller; | 56 | interrupt-controller; |
| 57 | reg = <0 0xe61c0000 0 0x200>; | 57 | reg = <0 0xe61c0000 0 0x200>; |
| 58 | interrupt-parent = <&gic>; | ||
| 59 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, | 58 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
| 60 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | 59 | <0 1 IRQ_TYPE_LEVEL_HIGH>, |
| 61 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | 60 | <0 2 IRQ_TYPE_LEVEL_HIGH>, |
| @@ -95,7 +94,6 @@ | |||
| 95 | #interrupt-cells = <2>; | 94 | #interrupt-cells = <2>; |
| 96 | interrupt-controller; | 95 | interrupt-controller; |
| 97 | reg = <0 0xe61c0200 0 0x200>; | 96 | reg = <0 0xe61c0200 0 0x200>; |
| 98 | interrupt-parent = <&gic>; | ||
| 99 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, | 97 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, |
| 100 | <0 33 IRQ_TYPE_LEVEL_HIGH>, | 98 | <0 33 IRQ_TYPE_LEVEL_HIGH>, |
| 101 | <0 34 IRQ_TYPE_LEVEL_HIGH>, | 99 | <0 34 IRQ_TYPE_LEVEL_HIGH>, |
| @@ -136,7 +134,6 @@ | |||
| 136 | dma0: dma-controller@e6700020 { | 134 | dma0: dma-controller@e6700020 { |
| 137 | compatible = "renesas,shdma-r8a73a4"; | 135 | compatible = "renesas,shdma-r8a73a4"; |
| 138 | reg = <0 0xe6700020 0 0x89e0>; | 136 | reg = <0 0xe6700020 0 0x89e0>; |
| 139 | interrupt-parent = <&gic>; | ||
| 140 | interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH | 137 | interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH |
| 141 | 0 200 IRQ_TYPE_LEVEL_HIGH | 138 | 0 200 IRQ_TYPE_LEVEL_HIGH |
| 142 | 0 201 IRQ_TYPE_LEVEL_HIGH | 139 | 0 201 IRQ_TYPE_LEVEL_HIGH |
| @@ -171,7 +168,6 @@ | |||
| 171 | compatible = "renesas,rcar-thermal"; | 168 | compatible = "renesas,rcar-thermal"; |
| 172 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, | 169 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, |
| 173 | <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; | 170 | <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; |
| 174 | interrupt-parent = <&gic>; | ||
| 175 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; | 171 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
| 176 | }; | 172 | }; |
| 177 | 173 | ||
| @@ -180,7 +176,6 @@ | |||
| 180 | #size-cells = <0>; | 176 | #size-cells = <0>; |
| 181 | compatible = "renesas,rmobile-iic"; | 177 | compatible = "renesas,rmobile-iic"; |
| 182 | reg = <0 0xe6500000 0 0x428>; | 178 | reg = <0 0xe6500000 0 0x428>; |
| 183 | interrupt-parent = <&gic>; | ||
| 184 | interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; | 179 | interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; |
| 185 | status = "disabled"; | 180 | status = "disabled"; |
| 186 | }; | 181 | }; |
| @@ -190,7 +185,6 @@ | |||
| 190 | #size-cells = <0>; | 185 | #size-cells = <0>; |
| 191 | compatible = "renesas,rmobile-iic"; | 186 | compatible = "renesas,rmobile-iic"; |
| 192 | reg = <0 0xe6510000 0 0x428>; | 187 | reg = <0 0xe6510000 0 0x428>; |
| 193 | interrupt-parent = <&gic>; | ||
| 194 | interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; | 188 | interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; |
| 195 | status = "disabled"; | 189 | status = "disabled"; |
| 196 | }; | 190 | }; |
| @@ -200,7 +194,6 @@ | |||
| 200 | #size-cells = <0>; | 194 | #size-cells = <0>; |
| 201 | compatible = "renesas,rmobile-iic"; | 195 | compatible = "renesas,rmobile-iic"; |
| 202 | reg = <0 0xe6520000 0 0x428>; | 196 | reg = <0 0xe6520000 0 0x428>; |
| 203 | interrupt-parent = <&gic>; | ||
| 204 | interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; | 197 | interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; |
| 205 | status = "disabled"; | 198 | status = "disabled"; |
| 206 | }; | 199 | }; |
| @@ -210,7 +203,6 @@ | |||
| 210 | #size-cells = <0>; | 203 | #size-cells = <0>; |
| 211 | compatible = "renesas,rmobile-iic"; | 204 | compatible = "renesas,rmobile-iic"; |
| 212 | reg = <0 0xe6530000 0 0x428>; | 205 | reg = <0 0xe6530000 0 0x428>; |
| 213 | interrupt-parent = <&gic>; | ||
| 214 | interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; | 206 | interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; |
| 215 | status = "disabled"; | 207 | status = "disabled"; |
| 216 | }; | 208 | }; |
| @@ -220,7 +212,6 @@ | |||
| 220 | #size-cells = <0>; | 212 | #size-cells = <0>; |
| 221 | compatible = "renesas,rmobile-iic"; | 213 | compatible = "renesas,rmobile-iic"; |
| 222 | reg = <0 0xe6540000 0 0x428>; | 214 | reg = <0 0xe6540000 0 0x428>; |
| 223 | interrupt-parent = <&gic>; | ||
| 224 | interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; | 215 | interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; |
| 225 | status = "disabled"; | 216 | status = "disabled"; |
| 226 | }; | 217 | }; |
| @@ -230,7 +221,6 @@ | |||
| 230 | #size-cells = <0>; | 221 | #size-cells = <0>; |
| 231 | compatible = "renesas,rmobile-iic"; | 222 | compatible = "renesas,rmobile-iic"; |
| 232 | reg = <0 0xe60b0000 0 0x428>; | 223 | reg = <0 0xe60b0000 0 0x428>; |
| 233 | interrupt-parent = <&gic>; | ||
| 234 | interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; | 224 | interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; |
| 235 | status = "disabled"; | 225 | status = "disabled"; |
| 236 | }; | 226 | }; |
| @@ -240,7 +230,6 @@ | |||
| 240 | #size-cells = <0>; | 230 | #size-cells = <0>; |
| 241 | compatible = "renesas,rmobile-iic"; | 231 | compatible = "renesas,rmobile-iic"; |
| 242 | reg = <0 0xe6550000 0 0x428>; | 232 | reg = <0 0xe6550000 0 0x428>; |
| 243 | interrupt-parent = <&gic>; | ||
| 244 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; | 233 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; |
| 245 | status = "disabled"; | 234 | status = "disabled"; |
| 246 | }; | 235 | }; |
| @@ -250,7 +239,6 @@ | |||
| 250 | #size-cells = <0>; | 239 | #size-cells = <0>; |
| 251 | compatible = "renesas,rmobile-iic"; | 240 | compatible = "renesas,rmobile-iic"; |
| 252 | reg = <0 0xe6560000 0 0x428>; | 241 | reg = <0 0xe6560000 0 0x428>; |
| 253 | interrupt-parent = <&gic>; | ||
| 254 | interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; | 242 | interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; |
| 255 | status = "disabled"; | 243 | status = "disabled"; |
| 256 | }; | 244 | }; |
| @@ -260,7 +248,6 @@ | |||
| 260 | #size-cells = <0>; | 248 | #size-cells = <0>; |
| 261 | compatible = "renesas,rmobile-iic"; | 249 | compatible = "renesas,rmobile-iic"; |
| 262 | reg = <0 0xe6570000 0 0x428>; | 250 | reg = <0 0xe6570000 0 0x428>; |
| 263 | interrupt-parent = <&gic>; | ||
| 264 | interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; | 251 | interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; |
| 265 | status = "disabled"; | 252 | status = "disabled"; |
| 266 | }; | 253 | }; |
| @@ -268,7 +255,6 @@ | |||
| 268 | mmcif0: mmc@ee200000 { | 255 | mmcif0: mmc@ee200000 { |
| 269 | compatible = "renesas,sh-mmcif"; | 256 | compatible = "renesas,sh-mmcif"; |
| 270 | reg = <0 0xee200000 0 0x80>; | 257 | reg = <0 0xee200000 0 0x80>; |
| 271 | interrupt-parent = <&gic>; | ||
| 272 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; | 258 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; |
| 273 | reg-io-width = <4>; | 259 | reg-io-width = <4>; |
| 274 | status = "disabled"; | 260 | status = "disabled"; |
| @@ -277,7 +263,6 @@ | |||
| 277 | mmcif1: mmc@ee220000 { | 263 | mmcif1: mmc@ee220000 { |
| 278 | compatible = "renesas,sh-mmcif"; | 264 | compatible = "renesas,sh-mmcif"; |
| 279 | reg = <0 0xee220000 0 0x80>; | 265 | reg = <0 0xee220000 0 0x80>; |
| 280 | interrupt-parent = <&gic>; | ||
| 281 | interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; | 266 | interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; |
| 282 | reg-io-width = <4>; | 267 | reg-io-width = <4>; |
| 283 | status = "disabled"; | 268 | status = "disabled"; |
| @@ -309,7 +294,6 @@ | |||
| 309 | sdhi0: sd@ee100000 { | 294 | sdhi0: sd@ee100000 { |
| 310 | compatible = "renesas,sdhi-r8a73a4"; | 295 | compatible = "renesas,sdhi-r8a73a4"; |
| 311 | reg = <0 0xee100000 0 0x100>; | 296 | reg = <0 0xee100000 0 0x100>; |
| 312 | interrupt-parent = <&gic>; | ||
| 313 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; | 297 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
| 314 | cap-sd-highspeed; | 298 | cap-sd-highspeed; |
| 315 | status = "disabled"; | 299 | status = "disabled"; |
| @@ -318,7 +302,6 @@ | |||
| 318 | sdhi1: sd@ee120000 { | 302 | sdhi1: sd@ee120000 { |
| 319 | compatible = "renesas,sdhi-r8a73a4"; | 303 | compatible = "renesas,sdhi-r8a73a4"; |
| 320 | reg = <0 0xee120000 0 0x100>; | 304 | reg = <0 0xee120000 0 0x100>; |
| 321 | interrupt-parent = <&gic>; | ||
| 322 | interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; | 305 | interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; |
| 323 | cap-sd-highspeed; | 306 | cap-sd-highspeed; |
| 324 | status = "disabled"; | 307 | status = "disabled"; |
| @@ -327,7 +310,6 @@ | |||
| 327 | sdhi2: sd@ee140000 { | 310 | sdhi2: sd@ee140000 { |
| 328 | compatible = "renesas,sdhi-r8a73a4"; | 311 | compatible = "renesas,sdhi-r8a73a4"; |
| 329 | reg = <0 0xee140000 0 0x100>; | 312 | reg = <0 0xee140000 0 0x100>; |
| 330 | interrupt-parent = <&gic>; | ||
| 331 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; | 313 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
| 332 | cap-sd-highspeed; | 314 | cap-sd-highspeed; |
| 333 | status = "disabled"; | 315 | status = "disabled"; |
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index 95a849bf921f..486007d7ffe4 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | /dts-v1/; | 11 | /dts-v1/; |
| 12 | #include "r8a7740.dtsi" | 12 | #include "r8a7740.dtsi" |
| 13 | #include <dt-bindings/gpio/gpio.h> | 13 | #include <dt-bindings/gpio/gpio.h> |
| 14 | #include <dt-bindings/input/input.h> | ||
| 14 | #include <dt-bindings/interrupt-controller/irq.h> | 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | #include <dt-bindings/pwm/pwm.h> | 16 | #include <dt-bindings/pwm/pwm.h> |
| 16 | 17 | ||
| @@ -77,26 +78,26 @@ | |||
| 77 | 78 | ||
| 78 | power-key { | 79 | power-key { |
| 79 | gpios = <&pfc 99 GPIO_ACTIVE_LOW>; | 80 | gpios = <&pfc 99 GPIO_ACTIVE_LOW>; |
| 80 | linux,code = <116>; | 81 | linux,code = <KEY_POWER>; |
| 81 | label = "SW3"; | 82 | label = "SW3"; |
| 82 | gpio-key,wakeup; | 83 | gpio-key,wakeup; |
| 83 | }; | 84 | }; |
| 84 | 85 | ||
| 85 | back-key { | 86 | back-key { |
| 86 | gpios = <&pfc 100 GPIO_ACTIVE_LOW>; | 87 | gpios = <&pfc 100 GPIO_ACTIVE_LOW>; |
| 87 | linux,code = <158>; | 88 | linux,code = <KEY_BACK>; |
| 88 | label = "SW4"; | 89 | label = "SW4"; |
| 89 | }; | 90 | }; |
| 90 | 91 | ||
| 91 | menu-key { | 92 | menu-key { |
| 92 | gpios = <&pfc 97 GPIO_ACTIVE_LOW>; | 93 | gpios = <&pfc 97 GPIO_ACTIVE_LOW>; |
| 93 | linux,code = <139>; | 94 | linux,code = <KEY_MENU>; |
| 94 | label = "SW5"; | 95 | label = "SW5"; |
| 95 | }; | 96 | }; |
| 96 | 97 | ||
| 97 | home-key { | 98 | home-key { |
| 98 | gpios = <&pfc 98 GPIO_ACTIVE_LOW>; | 99 | gpios = <&pfc 98 GPIO_ACTIVE_LOW>; |
| 99 | linux,code = <102>; | 100 | linux,code = <KEY_HOME>; |
| 100 | label = "SW6"; | 101 | label = "SW6"; |
| 101 | }; | 102 | }; |
| 102 | }; | 103 | }; |
| @@ -117,6 +118,16 @@ | |||
| 117 | }; | 118 | }; |
| 118 | }; | 119 | }; |
| 119 | 120 | ||
| 121 | i2c2: i2c@2 { | ||
| 122 | #address-cells = <1>; | ||
| 123 | #size-cells = <0>; | ||
| 124 | compatible = "i2c-gpio"; | ||
| 125 | gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */ | ||
| 126 | &pfc 91 GPIO_ACTIVE_HIGH /* scl */ | ||
| 127 | >; | ||
| 128 | i2c-gpio,delay-us = <5>; | ||
| 129 | }; | ||
| 130 | |||
| 120 | backlight { | 131 | backlight { |
| 121 | compatible = "pwm-backlight"; | 132 | compatible = "pwm-backlight"; |
| 122 | pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>; | 133 | pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>; |
| @@ -147,6 +158,18 @@ | |||
| 147 | }; | 158 | }; |
| 148 | }; | 159 | }; |
| 149 | 160 | ||
| 161 | ðer { | ||
| 162 | pinctrl-0 = <ðer_pins>; | ||
| 163 | pinctrl-names = "default"; | ||
| 164 | |||
| 165 | phy-handle = <&phy0>; | ||
| 166 | status = "ok"; | ||
| 167 | |||
| 168 | phy0: ethernet-phy@0 { | ||
| 169 | reg = <0>; | ||
| 170 | }; | ||
| 171 | }; | ||
| 172 | |||
| 150 | &i2c0 { | 173 | &i2c0 { |
| 151 | status = "okay"; | 174 | status = "okay"; |
| 152 | touchscreen@55 { | 175 | touchscreen@55 { |
| @@ -166,10 +189,23 @@ | |||
| 166 | }; | 189 | }; |
| 167 | }; | 190 | }; |
| 168 | 191 | ||
| 192 | &i2c2 { | ||
| 193 | status = "okay"; | ||
| 194 | rtc@30 { | ||
| 195 | compatible = "sii,s35390a"; | ||
| 196 | reg = <0x30>; | ||
| 197 | }; | ||
| 198 | }; | ||
| 199 | |||
| 169 | &pfc { | 200 | &pfc { |
| 170 | pinctrl-0 = <&scifa1_pins>; | 201 | pinctrl-0 = <&scifa1_pins>; |
| 171 | pinctrl-names = "default"; | 202 | pinctrl-names = "default"; |
| 172 | 203 | ||
| 204 | ether_pins: ether { | ||
| 205 | renesas,groups = "gether_mii", "gether_int"; | ||
| 206 | renesas,function = "gether"; | ||
| 207 | }; | ||
| 208 | |||
| 173 | scifa1_pins: serial1 { | 209 | scifa1_pins: serial1 { |
| 174 | renesas,groups = "scifa1_data"; | 210 | renesas,groups = "scifa1_data"; |
| 175 | renesas,function = "scifa1"; | 211 | renesas,function = "scifa1"; |
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 2551e9438d35..55d29f4d2ed6 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | compatible = "renesas,r8a7740"; | 16 | compatible = "renesas,r8a7740"; |
| 17 | interrupt-parent = <&gic>; | ||
| 17 | 18 | ||
| 18 | cpus { | 19 | cpus { |
| 19 | #address-cells = <1>; | 20 | #address-cells = <1>; |
| @@ -22,6 +23,7 @@ | |||
| 22 | compatible = "arm,cortex-a9"; | 23 | compatible = "arm,cortex-a9"; |
| 23 | device_type = "cpu"; | 24 | device_type = "cpu"; |
| 24 | reg = <0x0>; | 25 | reg = <0x0>; |
| 26 | clock-frequency = <800000000>; | ||
| 25 | }; | 27 | }; |
| 26 | }; | 28 | }; |
| 27 | 29 | ||
| @@ -48,7 +50,6 @@ | |||
| 48 | <0xe6900020 1>, | 50 | <0xe6900020 1>, |
| 49 | <0xe6900040 1>, | 51 | <0xe6900040 1>, |
| 50 | <0xe6900060 1>; | 52 | <0xe6900060 1>; |
| 51 | interrupt-parent = <&gic>; | ||
| 52 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH | 53 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH |
| 53 | 0 149 IRQ_TYPE_LEVEL_HIGH | 54 | 0 149 IRQ_TYPE_LEVEL_HIGH |
| 54 | 0 149 IRQ_TYPE_LEVEL_HIGH | 55 | 0 149 IRQ_TYPE_LEVEL_HIGH |
| @@ -69,7 +70,6 @@ | |||
| 69 | <0xe6900024 1>, | 70 | <0xe6900024 1>, |
| 70 | <0xe6900044 1>, | 71 | <0xe6900044 1>, |
| 71 | <0xe6900064 1>; | 72 | <0xe6900064 1>; |
| 72 | interrupt-parent = <&gic>; | ||
| 73 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH | 73 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH |
| 74 | 0 149 IRQ_TYPE_LEVEL_HIGH | 74 | 0 149 IRQ_TYPE_LEVEL_HIGH |
| 75 | 0 149 IRQ_TYPE_LEVEL_HIGH | 75 | 0 149 IRQ_TYPE_LEVEL_HIGH |
| @@ -90,7 +90,6 @@ | |||
| 90 | <0xe6900028 1>, | 90 | <0xe6900028 1>, |
| 91 | <0xe6900048 1>, | 91 | <0xe6900048 1>, |
| 92 | <0xe6900068 1>; | 92 | <0xe6900068 1>; |
| 93 | interrupt-parent = <&gic>; | ||
| 94 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH | 93 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH |
| 95 | 0 149 IRQ_TYPE_LEVEL_HIGH | 94 | 0 149 IRQ_TYPE_LEVEL_HIGH |
| 96 | 0 149 IRQ_TYPE_LEVEL_HIGH | 95 | 0 149 IRQ_TYPE_LEVEL_HIGH |
| @@ -111,7 +110,6 @@ | |||
| 111 | <0xe690002c 1>, | 110 | <0xe690002c 1>, |
| 112 | <0xe690004c 1>, | 111 | <0xe690004c 1>, |
| 113 | <0xe690006c 1>; | 112 | <0xe690006c 1>; |
| 114 | interrupt-parent = <&gic>; | ||
| 115 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH | 113 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH |
| 116 | 0 149 IRQ_TYPE_LEVEL_HIGH | 114 | 0 149 IRQ_TYPE_LEVEL_HIGH |
| 117 | 0 149 IRQ_TYPE_LEVEL_HIGH | 115 | 0 149 IRQ_TYPE_LEVEL_HIGH |
| @@ -122,12 +120,23 @@ | |||
| 122 | 0 149 IRQ_TYPE_LEVEL_HIGH>; | 120 | 0 149 IRQ_TYPE_LEVEL_HIGH>; |
| 123 | }; | 121 | }; |
| 124 | 122 | ||
| 123 | ether: ethernet@e9a00000 { | ||
| 124 | compatible = "renesas,gether-r8a7740"; | ||
| 125 | reg = <0xe9a00000 0x800>, | ||
| 126 | <0xe9a01800 0x800>; | ||
| 127 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; | ||
| 128 | /* clocks = <&mstp3_clks R8A7740_CLK_GETHER>; */ | ||
| 129 | phy-mode = "mii"; | ||
| 130 | #address-cells = <1>; | ||
| 131 | #size-cells = <0>; | ||
| 132 | status = "disabled"; | ||
| 133 | }; | ||
| 134 | |||
| 125 | i2c0: i2c@fff20000 { | 135 | i2c0: i2c@fff20000 { |
| 126 | #address-cells = <1>; | 136 | #address-cells = <1>; |
| 127 | #size-cells = <0>; | 137 | #size-cells = <0>; |
| 128 | compatible = "renesas,rmobile-iic"; | 138 | compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; |
| 129 | reg = <0xfff20000 0x425>; | 139 | reg = <0xfff20000 0x425>; |
| 130 | interrupt-parent = <&gic>; | ||
| 131 | interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH | 140 | interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH |
| 132 | 0 202 IRQ_TYPE_LEVEL_HIGH | 141 | 0 202 IRQ_TYPE_LEVEL_HIGH |
| 133 | 0 203 IRQ_TYPE_LEVEL_HIGH | 142 | 0 203 IRQ_TYPE_LEVEL_HIGH |
| @@ -138,9 +147,8 @@ | |||
| 138 | i2c1: i2c@e6c20000 { | 147 | i2c1: i2c@e6c20000 { |
| 139 | #address-cells = <1>; | 148 | #address-cells = <1>; |
| 140 | #size-cells = <0>; | 149 | #size-cells = <0>; |
| 141 | compatible = "renesas,rmobile-iic"; | 150 | compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; |
| 142 | reg = <0xe6c20000 0x425>; | 151 | reg = <0xe6c20000 0x425>; |
| 143 | interrupt-parent = <&gic>; | ||
| 144 | interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH | 152 | interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH |
| 145 | 0 71 IRQ_TYPE_LEVEL_HIGH | 153 | 0 71 IRQ_TYPE_LEVEL_HIGH |
| 146 | 0 72 IRQ_TYPE_LEVEL_HIGH | 154 | 0 72 IRQ_TYPE_LEVEL_HIGH |
| @@ -173,9 +181,8 @@ | |||
| 173 | }; | 181 | }; |
| 174 | 182 | ||
| 175 | mmcif0: mmc@e6bd0000 { | 183 | mmcif0: mmc@e6bd0000 { |
| 176 | compatible = "renesas,sh-mmcif"; | 184 | compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif"; |
| 177 | reg = <0xe6bd0000 0x100>; | 185 | reg = <0xe6bd0000 0x100>; |
| 178 | interrupt-parent = <&gic>; | ||
| 179 | interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH | 186 | interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH |
| 180 | 0 57 IRQ_TYPE_LEVEL_HIGH>; | 187 | 0 57 IRQ_TYPE_LEVEL_HIGH>; |
| 181 | status = "disabled"; | 188 | status = "disabled"; |
| @@ -184,7 +191,6 @@ | |||
| 184 | sdhi0: sd@e6850000 { | 191 | sdhi0: sd@e6850000 { |
| 185 | compatible = "renesas,sdhi-r8a7740"; | 192 | compatible = "renesas,sdhi-r8a7740"; |
| 186 | reg = <0xe6850000 0x100>; | 193 | reg = <0xe6850000 0x100>; |
| 187 | interrupt-parent = <&gic>; | ||
| 188 | interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH | 194 | interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH |
| 189 | 0 118 IRQ_TYPE_LEVEL_HIGH | 195 | 0 118 IRQ_TYPE_LEVEL_HIGH |
| 190 | 0 119 IRQ_TYPE_LEVEL_HIGH>; | 196 | 0 119 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -196,7 +202,6 @@ | |||
| 196 | sdhi1: sd@e6860000 { | 202 | sdhi1: sd@e6860000 { |
| 197 | compatible = "renesas,sdhi-r8a7740"; | 203 | compatible = "renesas,sdhi-r8a7740"; |
| 198 | reg = <0xe6860000 0x100>; | 204 | reg = <0xe6860000 0x100>; |
| 199 | interrupt-parent = <&gic>; | ||
| 200 | interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH | 205 | interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH |
| 201 | 0 122 IRQ_TYPE_LEVEL_HIGH | 206 | 0 122 IRQ_TYPE_LEVEL_HIGH |
| 202 | 0 123 IRQ_TYPE_LEVEL_HIGH>; | 207 | 0 123 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -208,7 +213,6 @@ | |||
| 208 | sdhi2: sd@e6870000 { | 213 | sdhi2: sd@e6870000 { |
| 209 | compatible = "renesas,sdhi-r8a7740"; | 214 | compatible = "renesas,sdhi-r8a7740"; |
| 210 | reg = <0xe6870000 0x100>; | 215 | reg = <0xe6870000 0x100>; |
| 211 | interrupt-parent = <&gic>; | ||
| 212 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH | 216 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH |
| 213 | 0 126 IRQ_TYPE_LEVEL_HIGH | 217 | 0 126 IRQ_TYPE_LEVEL_HIGH |
| 214 | 0 127 IRQ_TYPE_LEVEL_HIGH>; | 218 | 0 127 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -219,9 +223,8 @@ | |||
| 219 | 223 | ||
| 220 | sh_fsi2: sound@fe1f0000 { | 224 | sh_fsi2: sound@fe1f0000 { |
| 221 | #sound-dai-cells = <1>; | 225 | #sound-dai-cells = <1>; |
| 222 | compatible = "renesas,sh_fsi2"; | 226 | compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; |
| 223 | reg = <0xfe1f0000 0x400>; | 227 | reg = <0xfe1f0000 0x400>; |
| 224 | interrupt-parent = <&gic>; | ||
| 225 | interrupts = <0 9 0x4>; | 228 | interrupts = <0 9 0x4>; |
| 226 | status = "disabled"; | 229 | status = "disabled"; |
| 227 | }; | 230 | }; |
diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index 06cda19dac6a..f76f6ec01e19 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts | |||
| @@ -109,4 +109,18 @@ | |||
| 109 | pinctrl-0 = <&hspi0_pins>; | 109 | pinctrl-0 = <&hspi0_pins>; |
| 110 | pinctrl-names = "default"; | 110 | pinctrl-names = "default"; |
| 111 | status = "okay"; | 111 | status = "okay"; |
| 112 | |||
| 113 | flash: flash@0 { | ||
| 114 | #address-cells = <1>; | ||
| 115 | #size-cells = <1>; | ||
| 116 | compatible = "spansion,s25fl008k"; | ||
| 117 | reg = <0>; | ||
| 118 | spi-max-frequency = <104000000>; | ||
| 119 | m25p,fast-read; | ||
| 120 | |||
| 121 | partition@0 { | ||
| 122 | label = "data(spi)"; | ||
| 123 | reg = <0x00000000 0x00100000>; | ||
| 124 | }; | ||
| 125 | }; | ||
| 112 | }; | 126 | }; |
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 85c5b3b99f5e..3af0a2187493 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | 20 | ||
| 21 | / { | 21 | / { |
| 22 | compatible = "renesas,r8a7778"; | 22 | compatible = "renesas,r8a7778"; |
| 23 | interrupt-parent = <&gic>; | ||
| 23 | 24 | ||
| 24 | cpus { | 25 | cpus { |
| 25 | cpu@0 { | 26 | cpu@0 { |
| @@ -52,7 +53,6 @@ | |||
| 52 | <0xfe780024 4>, | 53 | <0xfe780024 4>, |
| 53 | <0xfe780044 4>, | 54 | <0xfe780044 4>, |
| 54 | <0xfe780064 4>; | 55 | <0xfe780064 4>; |
| 55 | interrupt-parent = <&gic>; | ||
| 56 | interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH | 56 | interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH |
| 57 | 0 28 IRQ_TYPE_LEVEL_HIGH | 57 | 0 28 IRQ_TYPE_LEVEL_HIGH |
| 58 | 0 29 IRQ_TYPE_LEVEL_HIGH | 58 | 0 29 IRQ_TYPE_LEVEL_HIGH |
| @@ -63,7 +63,6 @@ | |||
| 63 | gpio0: gpio@ffc40000 { | 63 | gpio0: gpio@ffc40000 { |
| 64 | compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; | 64 | compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; |
| 65 | reg = <0xffc40000 0x2c>; | 65 | reg = <0xffc40000 0x2c>; |
| 66 | interrupt-parent = <&gic>; | ||
| 67 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; | 66 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; |
| 68 | #gpio-cells = <2>; | 67 | #gpio-cells = <2>; |
| 69 | gpio-controller; | 68 | gpio-controller; |
| @@ -75,7 +74,6 @@ | |||
| 75 | gpio1: gpio@ffc41000 { | 74 | gpio1: gpio@ffc41000 { |
| 76 | compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; | 75 | compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; |
| 77 | reg = <0xffc41000 0x2c>; | 76 | reg = <0xffc41000 0x2c>; |
| 78 | interrupt-parent = <&gic>; | ||
| 79 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; | 77 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; |
| 80 | #gpio-cells = <2>; | 78 | #gpio-cells = <2>; |
| 81 | gpio-controller; | 79 | gpio-controller; |
| @@ -87,7 +85,6 @@ | |||
| 87 | gpio2: gpio@ffc42000 { | 85 | gpio2: gpio@ffc42000 { |
| 88 | compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; | 86 | compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; |
| 89 | reg = <0xffc42000 0x2c>; | 87 | reg = <0xffc42000 0x2c>; |
| 90 | interrupt-parent = <&gic>; | ||
| 91 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; | 88 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; |
| 92 | #gpio-cells = <2>; | 89 | #gpio-cells = <2>; |
| 93 | gpio-controller; | 90 | gpio-controller; |
| @@ -99,7 +96,6 @@ | |||
| 99 | gpio3: gpio@ffc43000 { | 96 | gpio3: gpio@ffc43000 { |
| 100 | compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; | 97 | compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; |
| 101 | reg = <0xffc43000 0x2c>; | 98 | reg = <0xffc43000 0x2c>; |
| 102 | interrupt-parent = <&gic>; | ||
| 103 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; | 99 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; |
| 104 | #gpio-cells = <2>; | 100 | #gpio-cells = <2>; |
| 105 | gpio-controller; | 101 | gpio-controller; |
| @@ -111,7 +107,6 @@ | |||
| 111 | gpio4: gpio@ffc44000 { | 107 | gpio4: gpio@ffc44000 { |
| 112 | compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; | 108 | compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; |
| 113 | reg = <0xffc44000 0x2c>; | 109 | reg = <0xffc44000 0x2c>; |
| 114 | interrupt-parent = <&gic>; | ||
| 115 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; | 110 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; |
| 116 | #gpio-cells = <2>; | 111 | #gpio-cells = <2>; |
| 117 | gpio-controller; | 112 | gpio-controller; |
| @@ -130,7 +125,6 @@ | |||
| 130 | #size-cells = <0>; | 125 | #size-cells = <0>; |
| 131 | compatible = "renesas,i2c-r8a7778"; | 126 | compatible = "renesas,i2c-r8a7778"; |
| 132 | reg = <0xffc70000 0x1000>; | 127 | reg = <0xffc70000 0x1000>; |
| 133 | interrupt-parent = <&gic>; | ||
| 134 | interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; | 128 | interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; |
| 135 | status = "disabled"; | 129 | status = "disabled"; |
| 136 | }; | 130 | }; |
| @@ -140,7 +134,6 @@ | |||
| 140 | #size-cells = <0>; | 134 | #size-cells = <0>; |
| 141 | compatible = "renesas,i2c-r8a7778"; | 135 | compatible = "renesas,i2c-r8a7778"; |
| 142 | reg = <0xffc71000 0x1000>; | 136 | reg = <0xffc71000 0x1000>; |
| 143 | interrupt-parent = <&gic>; | ||
| 144 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; | 137 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; |
| 145 | status = "disabled"; | 138 | status = "disabled"; |
| 146 | }; | 139 | }; |
| @@ -150,7 +143,6 @@ | |||
| 150 | #size-cells = <0>; | 143 | #size-cells = <0>; |
| 151 | compatible = "renesas,i2c-r8a7778"; | 144 | compatible = "renesas,i2c-r8a7778"; |
| 152 | reg = <0xffc72000 0x1000>; | 145 | reg = <0xffc72000 0x1000>; |
| 153 | interrupt-parent = <&gic>; | ||
| 154 | interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; | 146 | interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; |
| 155 | status = "disabled"; | 147 | status = "disabled"; |
| 156 | }; | 148 | }; |
| @@ -160,7 +152,6 @@ | |||
| 160 | #size-cells = <0>; | 152 | #size-cells = <0>; |
| 161 | compatible = "renesas,i2c-r8a7778"; | 153 | compatible = "renesas,i2c-r8a7778"; |
| 162 | reg = <0xffc73000 0x1000>; | 154 | reg = <0xffc73000 0x1000>; |
| 163 | interrupt-parent = <&gic>; | ||
| 164 | interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; | 155 | interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; |
| 165 | status = "disabled"; | 156 | status = "disabled"; |
| 166 | }; | 157 | }; |
| @@ -168,7 +159,6 @@ | |||
| 168 | mmcif: mmc@ffe4e000 { | 159 | mmcif: mmc@ffe4e000 { |
| 169 | compatible = "renesas,sh-mmcif"; | 160 | compatible = "renesas,sh-mmcif"; |
| 170 | reg = <0xffe4e000 0x100>; | 161 | reg = <0xffe4e000 0x100>; |
| 171 | interrupt-parent = <&gic>; | ||
| 172 | interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; | 162 | interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; |
| 173 | status = "disabled"; | 163 | status = "disabled"; |
| 174 | }; | 164 | }; |
| @@ -176,7 +166,6 @@ | |||
| 176 | sdhi0: sd@ffe4c000 { | 166 | sdhi0: sd@ffe4c000 { |
| 177 | compatible = "renesas,sdhi-r8a7778"; | 167 | compatible = "renesas,sdhi-r8a7778"; |
| 178 | reg = <0xffe4c000 0x100>; | 168 | reg = <0xffe4c000 0x100>; |
| 179 | interrupt-parent = <&gic>; | ||
| 180 | interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; | 169 | interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; |
| 181 | cap-sd-highspeed; | 170 | cap-sd-highspeed; |
| 182 | cap-sdio-irq; | 171 | cap-sdio-irq; |
| @@ -186,7 +175,6 @@ | |||
| 186 | sdhi1: sd@ffe4d000 { | 175 | sdhi1: sd@ffe4d000 { |
| 187 | compatible = "renesas,sdhi-r8a7778"; | 176 | compatible = "renesas,sdhi-r8a7778"; |
| 188 | reg = <0xffe4d000 0x100>; | 177 | reg = <0xffe4d000 0x100>; |
| 189 | interrupt-parent = <&gic>; | ||
| 190 | interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; | 178 | interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; |
| 191 | cap-sd-highspeed; | 179 | cap-sd-highspeed; |
| 192 | cap-sdio-irq; | 180 | cap-sdio-irq; |
| @@ -196,7 +184,6 @@ | |||
| 196 | sdhi2: sd@ffe4f000 { | 184 | sdhi2: sd@ffe4f000 { |
| 197 | compatible = "renesas,sdhi-r8a7778"; | 185 | compatible = "renesas,sdhi-r8a7778"; |
| 198 | reg = <0xffe4f000 0x100>; | 186 | reg = <0xffe4f000 0x100>; |
| 199 | interrupt-parent = <&gic>; | ||
| 200 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; | 187 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
| 201 | cap-sd-highspeed; | 188 | cap-sd-highspeed; |
| 202 | cap-sdio-irq; | 189 | cap-sdio-irq; |
| @@ -204,26 +191,29 @@ | |||
| 204 | }; | 191 | }; |
| 205 | 192 | ||
| 206 | hspi0: spi@fffc7000 { | 193 | hspi0: spi@fffc7000 { |
| 207 | compatible = "renesas,hspi"; | 194 | compatible = "renesas,hspi-r8a7778", "renesas,hspi"; |
| 208 | reg = <0xfffc7000 0x18>; | 195 | reg = <0xfffc7000 0x18>; |
| 209 | interrupt-controller = <&gic>; | ||
| 210 | interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; | 196 | interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; |
| 197 | #address-cells = <1>; | ||
| 198 | #size-cells = <0>; | ||
| 211 | status = "disabled"; | 199 | status = "disabled"; |
| 212 | }; | 200 | }; |
| 213 | 201 | ||
| 214 | hspi1: spi@fffc8000 { | 202 | hspi1: spi@fffc8000 { |
| 215 | compatible = "renesas,hspi"; | 203 | compatible = "renesas,hspi-r8a7778", "renesas,hspi"; |
| 216 | reg = <0xfffc8000 0x18>; | 204 | reg = <0xfffc8000 0x18>; |
| 217 | interrupt-controller = <&gic>; | ||
| 218 | interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; | 205 | interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; |
| 206 | #address-cells = <1>; | ||
| 207 | #size-cells = <0>; | ||
| 219 | status = "disabled"; | 208 | status = "disabled"; |
| 220 | }; | 209 | }; |
| 221 | 210 | ||
| 222 | hspi2: spi@fffc6000 { | 211 | hspi2: spi@fffc6000 { |
| 223 | compatible = "renesas,hspi"; | 212 | compatible = "renesas,hspi-r8a7778", "renesas,hspi"; |
| 224 | reg = <0xfffc6000 0x18>; | 213 | reg = <0xfffc6000 0x18>; |
| 225 | interrupt-controller = <&gic>; | ||
| 226 | interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; | 214 | interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; |
| 215 | #address-cells = <1>; | ||
| 216 | #size-cells = <0>; | ||
| 227 | status = "disabled"; | 217 | status = "disabled"; |
| 228 | }; | 218 | }; |
| 229 | }; | 219 | }; |
diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts index 76f5eef7d1cc..b27c6373ff4d 100644 --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts | |||
| @@ -45,6 +45,7 @@ | |||
| 45 | phy-mode = "mii"; | 45 | phy-mode = "mii"; |
| 46 | interrupt-parent = <&irqpin0>; | 46 | interrupt-parent = <&irqpin0>; |
| 47 | interrupts = <1 IRQ_TYPE_EDGE_FALLING>; | 47 | interrupts = <1 IRQ_TYPE_EDGE_FALLING>; |
| 48 | smsc,irq-push-pull; | ||
| 48 | reg-io-width = <4>; | 49 | reg-io-width = <4>; |
| 49 | vddvario-supply = <&fixedregulator3v3>; | 50 | vddvario-supply = <&fixedregulator3v3>; |
| 50 | vdd33a-supply = <&fixedregulator3v3>; | 51 | vdd33a-supply = <&fixedregulator3v3>; |
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index d0561d4c7c46..b517c8e6b420 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi | |||
| @@ -15,6 +15,7 @@ | |||
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | compatible = "renesas,r8a7779"; | 17 | compatible = "renesas,r8a7779"; |
| 18 | interrupt-parent = <&gic>; | ||
| 18 | 19 | ||
| 19 | cpus { | 20 | cpus { |
| 20 | #address-cells = <1>; | 21 | #address-cells = <1>; |
| @@ -59,7 +60,6 @@ | |||
| 59 | gpio0: gpio@ffc40000 { | 60 | gpio0: gpio@ffc40000 { |
| 60 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; | 61 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; |
| 61 | reg = <0xffc40000 0x2c>; | 62 | reg = <0xffc40000 0x2c>; |
| 62 | interrupt-parent = <&gic>; | ||
| 63 | interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>; | 63 | interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>; |
| 64 | #gpio-cells = <2>; | 64 | #gpio-cells = <2>; |
| 65 | gpio-controller; | 65 | gpio-controller; |
| @@ -71,7 +71,6 @@ | |||
| 71 | gpio1: gpio@ffc41000 { | 71 | gpio1: gpio@ffc41000 { |
| 72 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; | 72 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; |
| 73 | reg = <0xffc41000 0x2c>; | 73 | reg = <0xffc41000 0x2c>; |
| 74 | interrupt-parent = <&gic>; | ||
| 75 | interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>; | 74 | interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>; |
| 76 | #gpio-cells = <2>; | 75 | #gpio-cells = <2>; |
| 77 | gpio-controller; | 76 | gpio-controller; |
| @@ -83,7 +82,6 @@ | |||
| 83 | gpio2: gpio@ffc42000 { | 82 | gpio2: gpio@ffc42000 { |
| 84 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; | 83 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; |
| 85 | reg = <0xffc42000 0x2c>; | 84 | reg = <0xffc42000 0x2c>; |
| 86 | interrupt-parent = <&gic>; | ||
| 87 | interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; | 85 | interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; |
| 88 | #gpio-cells = <2>; | 86 | #gpio-cells = <2>; |
| 89 | gpio-controller; | 87 | gpio-controller; |
| @@ -95,7 +93,6 @@ | |||
| 95 | gpio3: gpio@ffc43000 { | 93 | gpio3: gpio@ffc43000 { |
| 96 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; | 94 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; |
| 97 | reg = <0xffc43000 0x2c>; | 95 | reg = <0xffc43000 0x2c>; |
| 98 | interrupt-parent = <&gic>; | ||
| 99 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; | 96 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; |
| 100 | #gpio-cells = <2>; | 97 | #gpio-cells = <2>; |
| 101 | gpio-controller; | 98 | gpio-controller; |
| @@ -107,7 +104,6 @@ | |||
| 107 | gpio4: gpio@ffc44000 { | 104 | gpio4: gpio@ffc44000 { |
| 108 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; | 105 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; |
| 109 | reg = <0xffc44000 0x2c>; | 106 | reg = <0xffc44000 0x2c>; |
| 110 | interrupt-parent = <&gic>; | ||
| 111 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; | 107 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; |
| 112 | #gpio-cells = <2>; | 108 | #gpio-cells = <2>; |
| 113 | gpio-controller; | 109 | gpio-controller; |
| @@ -119,7 +115,6 @@ | |||
| 119 | gpio5: gpio@ffc45000 { | 115 | gpio5: gpio@ffc45000 { |
| 120 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; | 116 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; |
| 121 | reg = <0xffc45000 0x2c>; | 117 | reg = <0xffc45000 0x2c>; |
| 122 | interrupt-parent = <&gic>; | ||
| 123 | interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>; | 118 | interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>; |
| 124 | #gpio-cells = <2>; | 119 | #gpio-cells = <2>; |
| 125 | gpio-controller; | 120 | gpio-controller; |
| @@ -131,7 +126,6 @@ | |||
| 131 | gpio6: gpio@ffc46000 { | 126 | gpio6: gpio@ffc46000 { |
| 132 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; | 127 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; |
| 133 | reg = <0xffc46000 0x2c>; | 128 | reg = <0xffc46000 0x2c>; |
| 134 | interrupt-parent = <&gic>; | ||
| 135 | interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>; | 129 | interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>; |
| 136 | #gpio-cells = <2>; | 130 | #gpio-cells = <2>; |
| 137 | gpio-controller; | 131 | gpio-controller; |
| @@ -150,7 +144,6 @@ | |||
| 150 | <0xfe780024 4>, | 144 | <0xfe780024 4>, |
| 151 | <0xfe780044 4>, | 145 | <0xfe780044 4>, |
| 152 | <0xfe780064 4>; | 146 | <0xfe780064 4>; |
| 153 | interrupt-parent = <&gic>; | ||
| 154 | interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH | 147 | interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH |
| 155 | 0 28 IRQ_TYPE_LEVEL_HIGH | 148 | 0 28 IRQ_TYPE_LEVEL_HIGH |
| 156 | 0 29 IRQ_TYPE_LEVEL_HIGH | 149 | 0 29 IRQ_TYPE_LEVEL_HIGH |
| @@ -163,7 +156,6 @@ | |||
| 163 | #size-cells = <0>; | 156 | #size-cells = <0>; |
| 164 | compatible = "renesas,i2c-r8a7779"; | 157 | compatible = "renesas,i2c-r8a7779"; |
| 165 | reg = <0xffc70000 0x1000>; | 158 | reg = <0xffc70000 0x1000>; |
| 166 | interrupt-parent = <&gic>; | ||
| 167 | interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; | 159 | interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; |
| 168 | status = "disabled"; | 160 | status = "disabled"; |
| 169 | }; | 161 | }; |
| @@ -173,7 +165,6 @@ | |||
| 173 | #size-cells = <0>; | 165 | #size-cells = <0>; |
| 174 | compatible = "renesas,i2c-r8a7779"; | 166 | compatible = "renesas,i2c-r8a7779"; |
| 175 | reg = <0xffc71000 0x1000>; | 167 | reg = <0xffc71000 0x1000>; |
| 176 | interrupt-parent = <&gic>; | ||
| 177 | interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; | 168 | interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; |
| 178 | status = "disabled"; | 169 | status = "disabled"; |
| 179 | }; | 170 | }; |
| @@ -183,7 +174,6 @@ | |||
| 183 | #size-cells = <0>; | 174 | #size-cells = <0>; |
| 184 | compatible = "renesas,i2c-r8a7779"; | 175 | compatible = "renesas,i2c-r8a7779"; |
| 185 | reg = <0xffc72000 0x1000>; | 176 | reg = <0xffc72000 0x1000>; |
| 186 | interrupt-parent = <&gic>; | ||
| 187 | interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; | 177 | interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
| 188 | status = "disabled"; | 178 | status = "disabled"; |
| 189 | }; | 179 | }; |
| @@ -193,7 +183,6 @@ | |||
| 193 | #size-cells = <0>; | 183 | #size-cells = <0>; |
| 194 | compatible = "renesas,i2c-r8a7779"; | 184 | compatible = "renesas,i2c-r8a7779"; |
| 195 | reg = <0xffc73000 0x1000>; | 185 | reg = <0xffc73000 0x1000>; |
| 196 | interrupt-parent = <&gic>; | ||
| 197 | interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; | 186 | interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; |
| 198 | status = "disabled"; | 187 | status = "disabled"; |
| 199 | }; | 188 | }; |
| @@ -211,14 +200,12 @@ | |||
| 211 | sata: sata@fc600000 { | 200 | sata: sata@fc600000 { |
| 212 | compatible = "renesas,rcar-sata"; | 201 | compatible = "renesas,rcar-sata"; |
| 213 | reg = <0xfc600000 0x2000>; | 202 | reg = <0xfc600000 0x2000>; |
| 214 | interrupt-parent = <&gic>; | ||
| 215 | interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; | 203 | interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; |
| 216 | }; | 204 | }; |
| 217 | 205 | ||
| 218 | sdhi0: sd@ffe4c000 { | 206 | sdhi0: sd@ffe4c000 { |
| 219 | compatible = "renesas,sdhi-r8a7779"; | 207 | compatible = "renesas,sdhi-r8a7779"; |
| 220 | reg = <0xffe4c000 0x100>; | 208 | reg = <0xffe4c000 0x100>; |
| 221 | interrupt-parent = <&gic>; | ||
| 222 | interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; | 209 | interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; |
| 223 | cap-sd-highspeed; | 210 | cap-sd-highspeed; |
| 224 | cap-sdio-irq; | 211 | cap-sdio-irq; |
| @@ -228,7 +215,6 @@ | |||
| 228 | sdhi1: sd@ffe4d000 { | 215 | sdhi1: sd@ffe4d000 { |
| 229 | compatible = "renesas,sdhi-r8a7779"; | 216 | compatible = "renesas,sdhi-r8a7779"; |
| 230 | reg = <0xffe4d000 0x100>; | 217 | reg = <0xffe4d000 0x100>; |
| 231 | interrupt-parent = <&gic>; | ||
| 232 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; | 218 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; |
| 233 | cap-sd-highspeed; | 219 | cap-sd-highspeed; |
| 234 | cap-sdio-irq; | 220 | cap-sdio-irq; |
| @@ -238,7 +224,6 @@ | |||
| 238 | sdhi2: sd@ffe4e000 { | 224 | sdhi2: sd@ffe4e000 { |
| 239 | compatible = "renesas,sdhi-r8a7779"; | 225 | compatible = "renesas,sdhi-r8a7779"; |
| 240 | reg = <0xffe4e000 0x100>; | 226 | reg = <0xffe4e000 0x100>; |
| 241 | interrupt-parent = <&gic>; | ||
| 242 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; | 227 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; |
| 243 | cap-sd-highspeed; | 228 | cap-sd-highspeed; |
| 244 | cap-sdio-irq; | 229 | cap-sdio-irq; |
| @@ -248,7 +233,6 @@ | |||
| 248 | sdhi3: sd@ffe4f000 { | 233 | sdhi3: sd@ffe4f000 { |
| 249 | compatible = "renesas,sdhi-r8a7779"; | 234 | compatible = "renesas,sdhi-r8a7779"; |
| 250 | reg = <0xffe4f000 0x100>; | 235 | reg = <0xffe4f000 0x100>; |
| 251 | interrupt-parent = <&gic>; | ||
| 252 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; | 236 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; |
| 253 | cap-sd-highspeed; | 237 | cap-sd-highspeed; |
| 254 | cap-sdio-irq; | 238 | cap-sdio-irq; |
| @@ -256,26 +240,29 @@ | |||
| 256 | }; | 240 | }; |
| 257 | 241 | ||
| 258 | hspi0: spi@fffc7000 { | 242 | hspi0: spi@fffc7000 { |
| 259 | compatible = "renesas,hspi"; | 243 | compatible = "renesas,hspi-r8a7779", "renesas,hspi"; |
| 260 | reg = <0xfffc7000 0x18>; | 244 | reg = <0xfffc7000 0x18>; |
| 261 | interrupt-controller = <&gic>; | ||
| 262 | interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; | 245 | interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; |
| 246 | #address-cells = <1>; | ||
| 247 | #size-cells = <0>; | ||
| 263 | status = "disabled"; | 248 | status = "disabled"; |
| 264 | }; | 249 | }; |
| 265 | 250 | ||
| 266 | hspi1: spi@fffc8000 { | 251 | hspi1: spi@fffc8000 { |
| 267 | compatible = "renesas,hspi"; | 252 | compatible = "renesas,hspi-r8a7779", "renesas,hspi"; |
| 268 | reg = <0xfffc8000 0x18>; | 253 | reg = <0xfffc8000 0x18>; |
| 269 | interrupt-controller = <&gic>; | ||
| 270 | interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; | 254 | interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; |
| 255 | #address-cells = <1>; | ||
| 256 | #size-cells = <0>; | ||
| 271 | status = "disabled"; | 257 | status = "disabled"; |
| 272 | }; | 258 | }; |
| 273 | 259 | ||
| 274 | hspi2: spi@fffc6000 { | 260 | hspi2: spi@fffc6000 { |
| 275 | compatible = "renesas,hspi"; | 261 | compatible = "renesas,hspi-r8a7779", "renesas,hspi"; |
| 276 | reg = <0xfffc6000 0x18>; | 262 | reg = <0xfffc6000 0x18>; |
| 277 | interrupt-controller = <&gic>; | ||
| 278 | interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; | 263 | interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; |
| 264 | #address-cells = <1>; | ||
| 265 | #size-cells = <0>; | ||
| 279 | status = "disabled"; | 266 | status = "disabled"; |
| 280 | }; | 267 | }; |
| 281 | }; | 268 | }; |
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index d01048ab3e77..dd2fe46073f2 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts | |||
| @@ -12,11 +12,17 @@ | |||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | #include "r8a7790.dtsi" | 13 | #include "r8a7790.dtsi" |
| 14 | #include <dt-bindings/gpio/gpio.h> | 14 | #include <dt-bindings/gpio/gpio.h> |
| 15 | #include <dt-bindings/input/input.h> | ||
| 15 | 16 | ||
| 16 | / { | 17 | / { |
| 17 | model = "Lager"; | 18 | model = "Lager"; |
| 18 | compatible = "renesas,lager", "renesas,r8a7790"; | 19 | compatible = "renesas,lager", "renesas,r8a7790"; |
| 19 | 20 | ||
| 21 | aliases { | ||
| 22 | serial6 = &scif0; | ||
| 23 | serial7 = &scif1; | ||
| 24 | }; | ||
| 25 | |||
| 20 | chosen { | 26 | chosen { |
| 21 | bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; | 27 | bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; |
| 22 | }; | 28 | }; |
| @@ -36,6 +42,39 @@ | |||
| 36 | #size-cells = <1>; | 42 | #size-cells = <1>; |
| 37 | }; | 43 | }; |
| 38 | 44 | ||
| 45 | gpio_keys { | ||
| 46 | compatible = "gpio-keys"; | ||
| 47 | |||
| 48 | button@1 { | ||
| 49 | linux,code = <KEY_1>; | ||
| 50 | label = "SW2-1"; | ||
| 51 | gpio-key,wakeup; | ||
| 52 | debounce-interval = <20>; | ||
| 53 | gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; | ||
| 54 | }; | ||
| 55 | button@2 { | ||
| 56 | linux,code = <KEY_2>; | ||
| 57 | label = "SW2-2"; | ||
| 58 | gpio-key,wakeup; | ||
| 59 | debounce-interval = <20>; | ||
| 60 | gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; | ||
| 61 | }; | ||
| 62 | button@3 { | ||
| 63 | linux,code = <KEY_3>; | ||
| 64 | label = "SW2-3"; | ||
| 65 | gpio-key,wakeup; | ||
| 66 | debounce-interval = <20>; | ||
| 67 | gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; | ||
| 68 | }; | ||
| 69 | button@4 { | ||
| 70 | linux,code = <KEY_4>; | ||
| 71 | label = "SW2-4"; | ||
| 72 | gpio-key,wakeup; | ||
| 73 | debounce-interval = <20>; | ||
| 74 | gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; | ||
| 75 | }; | ||
| 76 | }; | ||
| 77 | |||
| 39 | leds { | 78 | leds { |
| 40 | compatible = "gpio-leds"; | 79 | compatible = "gpio-leds"; |
| 41 | led6 { | 80 | led6 { |
| @@ -112,7 +151,7 @@ | |||
| 112 | }; | 151 | }; |
| 113 | 152 | ||
| 114 | &pfc { | 153 | &pfc { |
| 115 | pinctrl-0 = <&du_pins &scif0_pins &scif1_pins>; | 154 | pinctrl-0 = <&du_pins>; |
| 116 | pinctrl-names = "default"; | 155 | pinctrl-names = "default"; |
| 117 | 156 | ||
| 118 | du_pins: du { | 157 | du_pins: du { |
| @@ -155,10 +194,16 @@ | |||
| 155 | renesas,function = "mmc1"; | 194 | renesas,function = "mmc1"; |
| 156 | }; | 195 | }; |
| 157 | 196 | ||
| 158 | qspi_pins: spi { | 197 | qspi_pins: spi0 { |
| 159 | renesas,groups = "qspi_ctrl", "qspi_data4"; | 198 | renesas,groups = "qspi_ctrl", "qspi_data4"; |
| 160 | renesas,function = "qspi"; | 199 | renesas,function = "qspi"; |
| 161 | }; | 200 | }; |
| 201 | |||
| 202 | msiof1_pins: spi2 { | ||
| 203 | renesas,groups = "msiof1_clk", "msiof1_sync", "msiof1_rx", | ||
| 204 | "msiof1_tx"; | ||
| 205 | renesas,function = "msiof1"; | ||
| 206 | }; | ||
| 162 | }; | 207 | }; |
| 163 | 208 | ||
| 164 | ðer { | 209 | ðer { |
| @@ -173,6 +218,7 @@ | |||
| 173 | reg = <1>; | 218 | reg = <1>; |
| 174 | interrupt-parent = <&irqc0>; | 219 | interrupt-parent = <&irqc0>; |
| 175 | interrupts = <0 IRQ_TYPE_LEVEL_LOW>; | 220 | interrupts = <0 IRQ_TYPE_LEVEL_LOW>; |
| 221 | micrel,led-mode = <1>; | ||
| 176 | }; | 222 | }; |
| 177 | }; | 223 | }; |
| 178 | 224 | ||
| @@ -190,7 +236,7 @@ | |||
| 190 | status = "okay"; | 236 | status = "okay"; |
| 191 | }; | 237 | }; |
| 192 | 238 | ||
| 193 | &spi { | 239 | &qspi { |
| 194 | pinctrl-0 = <&qspi_pins>; | 240 | pinctrl-0 = <&qspi_pins>; |
| 195 | pinctrl-names = "default"; | 241 | pinctrl-names = "default"; |
| 196 | 242 | ||
| @@ -202,6 +248,8 @@ | |||
| 202 | compatible = "spansion,s25fl512s"; | 248 | compatible = "spansion,s25fl512s"; |
| 203 | reg = <0>; | 249 | reg = <0>; |
| 204 | spi-max-frequency = <30000000>; | 250 | spi-max-frequency = <30000000>; |
| 251 | spi-tx-bus-width = <4>; | ||
| 252 | spi-rx-bus-width = <4>; | ||
| 205 | m25p,fast-read; | 253 | m25p,fast-read; |
| 206 | 254 | ||
| 207 | partition@0 { | 255 | partition@0 { |
| @@ -221,6 +269,35 @@ | |||
| 221 | }; | 269 | }; |
| 222 | }; | 270 | }; |
| 223 | 271 | ||
| 272 | &scif0 { | ||
| 273 | pinctrl-0 = <&scif0_pins>; | ||
| 274 | pinctrl-names = "default"; | ||
| 275 | |||
| 276 | status = "okay"; | ||
| 277 | }; | ||
| 278 | |||
| 279 | &scif1 { | ||
| 280 | pinctrl-0 = <&scif1_pins>; | ||
| 281 | pinctrl-names = "default"; | ||
| 282 | |||
| 283 | status = "okay"; | ||
| 284 | }; | ||
| 285 | |||
| 286 | &msiof1 { | ||
| 287 | pinctrl-0 = <&msiof1_pins>; | ||
| 288 | pinctrl-names = "default"; | ||
| 289 | |||
| 290 | status = "okay"; | ||
| 291 | |||
| 292 | pmic: pmic@0 { | ||
| 293 | compatible = "renesas,r2a11302ft"; | ||
| 294 | reg = <0>; | ||
| 295 | spi-max-frequency = <6000000>; | ||
| 296 | spi-cpol; | ||
| 297 | spi-cpha; | ||
| 298 | }; | ||
| 299 | }; | ||
| 300 | |||
| 224 | &sdhi0 { | 301 | &sdhi0 { |
| 225 | pinctrl-0 = <&sdhi0_pins>; | 302 | pinctrl-0 = <&sdhi0_pins>; |
| 226 | pinctrl-names = "default"; | 303 | pinctrl-names = "default"; |
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 618e5b537eaf..7ff29601f962 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi | |||
| @@ -24,6 +24,15 @@ | |||
| 24 | i2c1 = &i2c1; | 24 | i2c1 = &i2c1; |
| 25 | i2c2 = &i2c2; | 25 | i2c2 = &i2c2; |
| 26 | i2c3 = &i2c3; | 26 | i2c3 = &i2c3; |
| 27 | i2c4 = &iic0; | ||
| 28 | i2c5 = &iic1; | ||
| 29 | i2c6 = &iic2; | ||
| 30 | i2c7 = &iic3; | ||
| 31 | spi0 = &qspi; | ||
| 32 | spi1 = &msiof0; | ||
| 33 | spi2 = &msiof1; | ||
| 34 | spi3 = &msiof2; | ||
| 35 | spi4 = &msiof3; | ||
| 27 | }; | 36 | }; |
| 28 | 37 | ||
| 29 | cpus { | 38 | cpus { |
| @@ -108,6 +117,7 @@ | |||
| 108 | gpio-ranges = <&pfc 0 0 32>; | 117 | gpio-ranges = <&pfc 0 0 32>; |
| 109 | #interrupt-cells = <2>; | 118 | #interrupt-cells = <2>; |
| 110 | interrupt-controller; | 119 | interrupt-controller; |
| 120 | clocks = <&mstp9_clks R8A7790_CLK_GPIO0>; | ||
| 111 | }; | 121 | }; |
| 112 | 122 | ||
| 113 | gpio1: gpio@e6051000 { | 123 | gpio1: gpio@e6051000 { |
| @@ -119,6 +129,7 @@ | |||
| 119 | gpio-ranges = <&pfc 0 32 32>; | 129 | gpio-ranges = <&pfc 0 32 32>; |
| 120 | #interrupt-cells = <2>; | 130 | #interrupt-cells = <2>; |
| 121 | interrupt-controller; | 131 | interrupt-controller; |
| 132 | clocks = <&mstp9_clks R8A7790_CLK_GPIO1>; | ||
| 122 | }; | 133 | }; |
| 123 | 134 | ||
| 124 | gpio2: gpio@e6052000 { | 135 | gpio2: gpio@e6052000 { |
| @@ -130,6 +141,7 @@ | |||
| 130 | gpio-ranges = <&pfc 0 64 32>; | 141 | gpio-ranges = <&pfc 0 64 32>; |
| 131 | #interrupt-cells = <2>; | 142 | #interrupt-cells = <2>; |
| 132 | interrupt-controller; | 143 | interrupt-controller; |
| 144 | clocks = <&mstp9_clks R8A7790_CLK_GPIO2>; | ||
| 133 | }; | 145 | }; |
| 134 | 146 | ||
| 135 | gpio3: gpio@e6053000 { | 147 | gpio3: gpio@e6053000 { |
| @@ -141,6 +153,7 @@ | |||
| 141 | gpio-ranges = <&pfc 0 96 32>; | 153 | gpio-ranges = <&pfc 0 96 32>; |
| 142 | #interrupt-cells = <2>; | 154 | #interrupt-cells = <2>; |
| 143 | interrupt-controller; | 155 | interrupt-controller; |
| 156 | clocks = <&mstp9_clks R8A7790_CLK_GPIO3>; | ||
| 144 | }; | 157 | }; |
| 145 | 158 | ||
| 146 | gpio4: gpio@e6054000 { | 159 | gpio4: gpio@e6054000 { |
| @@ -152,6 +165,7 @@ | |||
| 152 | gpio-ranges = <&pfc 0 128 32>; | 165 | gpio-ranges = <&pfc 0 128 32>; |
| 153 | #interrupt-cells = <2>; | 166 | #interrupt-cells = <2>; |
| 154 | interrupt-controller; | 167 | interrupt-controller; |
| 168 | clocks = <&mstp9_clks R8A7790_CLK_GPIO4>; | ||
| 155 | }; | 169 | }; |
| 156 | 170 | ||
| 157 | gpio5: gpio@e6055000 { | 171 | gpio5: gpio@e6055000 { |
| @@ -163,6 +177,7 @@ | |||
| 163 | gpio-ranges = <&pfc 0 160 32>; | 177 | gpio-ranges = <&pfc 0 160 32>; |
| 164 | #interrupt-cells = <2>; | 178 | #interrupt-cells = <2>; |
| 165 | interrupt-controller; | 179 | interrupt-controller; |
| 180 | clocks = <&mstp9_clks R8A7790_CLK_GPIO5>; | ||
| 166 | }; | 181 | }; |
| 167 | 182 | ||
| 168 | thermal@e61f0000 { | 183 | thermal@e61f0000 { |
| @@ -231,6 +246,46 @@ | |||
| 231 | status = "disabled"; | 246 | status = "disabled"; |
| 232 | }; | 247 | }; |
| 233 | 248 | ||
| 249 | iic0: i2c@e6500000 { | ||
| 250 | #address-cells = <1>; | ||
| 251 | #size-cells = <0>; | ||
| 252 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; | ||
| 253 | reg = <0 0xe6500000 0 0x425>; | ||
| 254 | interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; | ||
| 255 | clocks = <&mstp3_clks R8A7790_CLK_IIC0>; | ||
| 256 | status = "disabled"; | ||
| 257 | }; | ||
| 258 | |||
| 259 | iic1: i2c@e6510000 { | ||
| 260 | #address-cells = <1>; | ||
| 261 | #size-cells = <0>; | ||
| 262 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; | ||
| 263 | reg = <0 0xe6510000 0 0x425>; | ||
| 264 | interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; | ||
| 265 | clocks = <&mstp3_clks R8A7790_CLK_IIC1>; | ||
| 266 | status = "disabled"; | ||
| 267 | }; | ||
| 268 | |||
| 269 | iic2: i2c@e6520000 { | ||
| 270 | #address-cells = <1>; | ||
| 271 | #size-cells = <0>; | ||
| 272 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; | ||
| 273 | reg = <0 0xe6520000 0 0x425>; | ||
| 274 | interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; | ||
| 275 | clocks = <&mstp3_clks R8A7790_CLK_IIC2>; | ||
| 276 | status = "disabled"; | ||
| 277 | }; | ||
| 278 | |||
| 279 | iic3: i2c@e60b0000 { | ||
| 280 | #address-cells = <1>; | ||
| 281 | #size-cells = <0>; | ||
| 282 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; | ||
| 283 | reg = <0 0xe60b0000 0 0x425>; | ||
| 284 | interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; | ||
| 285 | clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; | ||
| 286 | status = "disabled"; | ||
| 287 | }; | ||
| 288 | |||
| 234 | mmcif0: mmcif@ee200000 { | 289 | mmcif0: mmcif@ee200000 { |
| 235 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; | 290 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
| 236 | reg = <0 0xee200000 0 0x80>; | 291 | reg = <0 0xee200000 0 0x80>; |
| @@ -673,7 +728,7 @@ | |||
| 673 | renesas,clock-indices = < | 728 | renesas,clock-indices = < |
| 674 | R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 | 729 | R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 |
| 675 | R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 | 730 | R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 |
| 676 | R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY | 731 | R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S |
| 677 | >; | 732 | >; |
| 678 | clock-output-names = | 733 | clock-output-names = |
| 679 | "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", | 734 | "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", |
| @@ -697,18 +752,19 @@ | |||
| 697 | mstp3_clks: mstp3_clks@e615013c { | 752 | mstp3_clks: mstp3_clks@e615013c { |
| 698 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | 753 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 699 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | 754 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; |
| 700 | clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, | 755 | clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, |
| 701 | <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, | 756 | <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, |
| 702 | <&mmc0_clk>, <&rclk_clk>; | 757 | <&hp_clk>, <&hp_clk>, <&rclk_clk>; |
| 703 | #clock-cells = <1>; | 758 | #clock-cells = <1>; |
| 704 | renesas,clock-indices = < | 759 | renesas,clock-indices = < |
| 705 | R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 | 760 | R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 |
| 706 | R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 | 761 | R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 |
| 707 | R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1 | 762 | R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_CMT1 |
| 708 | >; | 763 | >; |
| 709 | clock-output-names = | 764 | clock-output-names = |
| 710 | "tpu0", "mmcif1", "sdhi3", "sdhi2", | 765 | "iic2", "tpu0", "mmcif1", "sdhi3", |
| 711 | "sdhi1", "sdhi0", "mmcif0", "cmt1"; | 766 | "sdhi2", "sdhi1", "sdhi0", "mmcif0", |
| 767 | "iic0", "iic1", "cmt1"; | ||
| 712 | }; | 768 | }; |
| 713 | mstp5_clks: mstp5_clks@e6150144 { | 769 | mstp5_clks: mstp5_clks@e6150144 { |
| 714 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | 770 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| @@ -752,20 +808,25 @@ | |||
| 752 | mstp9_clks: mstp9_clks@e6150994 { | 808 | mstp9_clks: mstp9_clks@e6150994 { |
| 753 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | 809 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 754 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | 810 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; |
| 755 | clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, | 811 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, |
| 756 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; | 812 | <&cp_clk>, <&cp_clk>, <&cp_clk>, |
| 813 | <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, | ||
| 814 | <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; | ||
| 757 | #clock-cells = <1>; | 815 | #clock-cells = <1>; |
| 758 | renesas,clock-indices = < | 816 | renesas,clock-indices = < |
| 759 | R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD | 817 | R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 |
| 760 | R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 | 818 | R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 |
| 761 | R8A7790_CLK_I2C0 | 819 | R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS |
| 820 | R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 | ||
| 762 | >; | 821 | >; |
| 763 | clock-output-names = | 822 | clock-output-names = |
| 764 | "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0"; | 823 | "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", |
| 824 | "rcan1", "rcan0", "qspi_mod", "iic3", | ||
| 825 | "i2c3", "i2c2", "i2c1", "i2c0"; | ||
| 765 | }; | 826 | }; |
| 766 | }; | 827 | }; |
| 767 | 828 | ||
| 768 | spi: spi@e6b10000 { | 829 | qspi: spi@e6b10000 { |
| 769 | compatible = "renesas,qspi-r8a7790", "renesas,qspi"; | 830 | compatible = "renesas,qspi-r8a7790", "renesas,qspi"; |
| 770 | reg = <0 0xe6b10000 0 0x2c>; | 831 | reg = <0 0xe6b10000 0 0x2c>; |
| 771 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; | 832 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -775,4 +836,44 @@ | |||
| 775 | #size-cells = <0>; | 836 | #size-cells = <0>; |
| 776 | status = "disabled"; | 837 | status = "disabled"; |
| 777 | }; | 838 | }; |
| 839 | |||
| 840 | msiof0: spi@e6e20000 { | ||
| 841 | compatible = "renesas,msiof-r8a7790"; | ||
| 842 | reg = <0 0xe6e20000 0 0x0064>; | ||
| 843 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; | ||
| 844 | clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; | ||
| 845 | #address-cells = <1>; | ||
| 846 | #size-cells = <0>; | ||
| 847 | status = "disabled"; | ||
| 848 | }; | ||
| 849 | |||
| 850 | msiof1: spi@e6e10000 { | ||
| 851 | compatible = "renesas,msiof-r8a7790"; | ||
| 852 | reg = <0 0xe6e10000 0 0x0064>; | ||
| 853 | interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; | ||
| 854 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; | ||
| 855 | #address-cells = <1>; | ||
| 856 | #size-cells = <0>; | ||
| 857 | status = "disabled"; | ||
| 858 | }; | ||
| 859 | |||
| 860 | msiof2: spi@e6e00000 { | ||
| 861 | compatible = "renesas,msiof-r8a7790"; | ||
| 862 | reg = <0 0xe6e00000 0 0x0064>; | ||
| 863 | interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; | ||
| 864 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; | ||
| 865 | #address-cells = <1>; | ||
| 866 | #size-cells = <0>; | ||
| 867 | status = "disabled"; | ||
| 868 | }; | ||
| 869 | |||
| 870 | msiof3: spi@e6c90000 { | ||
| 871 | compatible = "renesas,msiof-r8a7790"; | ||
| 872 | reg = <0 0xe6c90000 0 0x0064>; | ||
| 873 | interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>; | ||
| 874 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; | ||
| 875 | #address-cells = <1>; | ||
| 876 | #size-cells = <0>; | ||
| 877 | status = "disabled"; | ||
| 878 | }; | ||
| 778 | }; | 879 | }; |
diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts new file mode 100644 index 000000000000..cc6d992e8db2 --- /dev/null +++ b/arch/arm/boot/dts/r8a7791-henninger.dts | |||
| @@ -0,0 +1,219 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree Source for the Henninger board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2014 Renesas Solutions Corp. | ||
| 5 | * Copyright (C) 2014 Cogent Embedded, Inc. | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public License | ||
| 8 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 9 | * kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "r8a7791.dtsi" | ||
| 14 | #include <dt-bindings/gpio/gpio.h> | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Henninger"; | ||
| 18 | compatible = "renesas,henninger", "renesas,r8a7791"; | ||
| 19 | |||
| 20 | aliases { | ||
| 21 | serial0 = &scif0; | ||
| 22 | }; | ||
| 23 | |||
| 24 | chosen { | ||
| 25 | bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp"; | ||
| 26 | }; | ||
| 27 | |||
| 28 | memory@40000000 { | ||
| 29 | device_type = "memory"; | ||
| 30 | reg = <0 0x40000000 0 0x40000000>; | ||
| 31 | }; | ||
| 32 | |||
| 33 | memory@200000000 { | ||
| 34 | device_type = "memory"; | ||
| 35 | reg = <2 0x00000000 0 0x40000000>; | ||
| 36 | }; | ||
| 37 | |||
| 38 | vcc_sdhi0: regulator@0 { | ||
| 39 | compatible = "regulator-fixed"; | ||
| 40 | |||
| 41 | regulator-name = "SDHI0 Vcc"; | ||
| 42 | regulator-min-microvolt = <3300000>; | ||
| 43 | regulator-max-microvolt = <3300000>; | ||
| 44 | regulator-always-on; | ||
| 45 | }; | ||
| 46 | |||
| 47 | vccq_sdhi0: regulator@1 { | ||
| 48 | compatible = "regulator-gpio"; | ||
| 49 | |||
| 50 | regulator-name = "SDHI0 VccQ"; | ||
| 51 | regulator-min-microvolt = <1800000>; | ||
| 52 | regulator-max-microvolt = <3300000>; | ||
| 53 | |||
| 54 | gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; | ||
| 55 | gpios-states = <1>; | ||
| 56 | states = <3300000 1 | ||
| 57 | 1800000 0>; | ||
| 58 | }; | ||
| 59 | |||
| 60 | vcc_sdhi2: regulator@2 { | ||
| 61 | compatible = "regulator-fixed"; | ||
| 62 | |||
| 63 | regulator-name = "SDHI2 Vcc"; | ||
| 64 | regulator-min-microvolt = <3300000>; | ||
| 65 | regulator-max-microvolt = <3300000>; | ||
| 66 | regulator-always-on; | ||
| 67 | }; | ||
| 68 | |||
| 69 | vccq_sdhi2: regulator@3 { | ||
| 70 | compatible = "regulator-gpio"; | ||
| 71 | |||
| 72 | regulator-name = "SDHI2 VccQ"; | ||
| 73 | regulator-min-microvolt = <1800000>; | ||
| 74 | regulator-max-microvolt = <3300000>; | ||
| 75 | |||
| 76 | gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; | ||
| 77 | gpios-states = <1>; | ||
| 78 | states = <3300000 1 | ||
| 79 | 1800000 0>; | ||
| 80 | }; | ||
| 81 | }; | ||
| 82 | |||
| 83 | &extal_clk { | ||
| 84 | clock-frequency = <20000000>; | ||
| 85 | }; | ||
| 86 | |||
| 87 | &pfc { | ||
| 88 | scif0_pins: serial0 { | ||
| 89 | renesas,groups = "scif0_data_d"; | ||
| 90 | renesas,function = "scif0"; | ||
| 91 | }; | ||
| 92 | |||
| 93 | ether_pins: ether { | ||
| 94 | renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; | ||
| 95 | renesas,function = "eth"; | ||
| 96 | }; | ||
| 97 | |||
| 98 | phy1_pins: phy1 { | ||
| 99 | renesas,groups = "intc_irq0"; | ||
| 100 | renesas,function = "intc"; | ||
| 101 | }; | ||
| 102 | |||
| 103 | sdhi0_pins: sd0 { | ||
| 104 | renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; | ||
| 105 | renesas,function = "sdhi0"; | ||
| 106 | }; | ||
| 107 | |||
| 108 | sdhi2_pins: sd2 { | ||
| 109 | renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; | ||
| 110 | renesas,function = "sdhi2"; | ||
| 111 | }; | ||
| 112 | |||
| 113 | qspi_pins: spi0 { | ||
| 114 | renesas,groups = "qspi_ctrl", "qspi_data4"; | ||
| 115 | renesas,function = "qspi"; | ||
| 116 | }; | ||
| 117 | |||
| 118 | msiof0_pins: spi1 { | ||
| 119 | renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", | ||
| 120 | "msiof0_tx"; | ||
| 121 | renesas,function = "msiof0"; | ||
| 122 | }; | ||
| 123 | }; | ||
| 124 | |||
| 125 | &scif0 { | ||
| 126 | pinctrl-0 = <&scif0_pins>; | ||
| 127 | pinctrl-names = "default"; | ||
| 128 | |||
| 129 | status = "okay"; | ||
| 130 | }; | ||
| 131 | |||
| 132 | ðer { | ||
| 133 | pinctrl-0 = <ðer_pins &phy1_pins>; | ||
| 134 | pinctrl-names = "default"; | ||
| 135 | |||
| 136 | phy-handle = <&phy1>; | ||
| 137 | renesas,ether-link-active-low; | ||
| 138 | status = "ok"; | ||
| 139 | |||
| 140 | phy1: ethernet-phy@1 { | ||
| 141 | reg = <1>; | ||
| 142 | interrupt-parent = <&irqc0>; | ||
| 143 | interrupts = <0 IRQ_TYPE_LEVEL_LOW>; | ||
| 144 | micrel,led-mode = <1>; | ||
| 145 | }; | ||
| 146 | }; | ||
| 147 | |||
| 148 | &sata0 { | ||
| 149 | status = "okay"; | ||
| 150 | }; | ||
| 151 | |||
| 152 | &sdhi0 { | ||
| 153 | pinctrl-0 = <&sdhi0_pins>; | ||
| 154 | pinctrl-names = "default"; | ||
| 155 | |||
| 156 | vmmc-supply = <&vcc_sdhi0>; | ||
| 157 | vqmmc-supply = <&vccq_sdhi0>; | ||
| 158 | cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; | ||
| 159 | wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; | ||
| 160 | status = "okay"; | ||
| 161 | }; | ||
| 162 | |||
| 163 | &sdhi2 { | ||
| 164 | pinctrl-0 = <&sdhi2_pins>; | ||
| 165 | pinctrl-names = "default"; | ||
| 166 | |||
| 167 | vmmc-supply = <&vcc_sdhi2>; | ||
| 168 | vqmmc-supply = <&vccq_sdhi2>; | ||
| 169 | cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; | ||
| 170 | status = "okay"; | ||
| 171 | }; | ||
| 172 | |||
| 173 | &qspi { | ||
| 174 | pinctrl-0 = <&qspi_pins>; | ||
| 175 | pinctrl-names = "default"; | ||
| 176 | |||
| 177 | status = "okay"; | ||
| 178 | |||
| 179 | flash@0 { | ||
| 180 | #address-cells = <1>; | ||
| 181 | #size-cells = <1>; | ||
| 182 | compatible = "spansion,s25fl512s"; | ||
| 183 | reg = <0>; | ||
| 184 | spi-max-frequency = <30000000>; | ||
| 185 | spi-tx-bus-width = <4>; | ||
| 186 | spi-rx-bus-width = <4>; | ||
| 187 | m25p,fast-read; | ||
| 188 | |||
| 189 | partition@0 { | ||
| 190 | label = "loader_prg"; | ||
| 191 | reg = <0x00000000 0x00040000>; | ||
| 192 | read-only; | ||
| 193 | }; | ||
| 194 | partition@40000 { | ||
| 195 | label = "user_prg"; | ||
| 196 | reg = <0x00040000 0x00400000>; | ||
| 197 | read-only; | ||
| 198 | }; | ||
| 199 | partition@440000 { | ||
| 200 | label = "flash_fs"; | ||
| 201 | reg = <0x00440000 0x03bc0000>; | ||
| 202 | }; | ||
| 203 | }; | ||
| 204 | }; | ||
| 205 | |||
| 206 | &msiof0 { | ||
| 207 | pinctrl-0 = <&msiof0_pins>; | ||
| 208 | pinctrl-names = "default"; | ||
| 209 | |||
| 210 | status = "okay"; | ||
| 211 | |||
| 212 | pmic@0 { | ||
| 213 | compatible = "renesas,r2a11302ft"; | ||
| 214 | reg = <0>; | ||
| 215 | spi-max-frequency = <6000000>; | ||
| 216 | spi-cpol; | ||
| 217 | spi-cpha; | ||
| 218 | }; | ||
| 219 | }; | ||
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index de1b6977c69a..05d44f9b202f 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts | |||
| @@ -13,11 +13,17 @@ | |||
| 13 | /dts-v1/; | 13 | /dts-v1/; |
| 14 | #include "r8a7791.dtsi" | 14 | #include "r8a7791.dtsi" |
| 15 | #include <dt-bindings/gpio/gpio.h> | 15 | #include <dt-bindings/gpio/gpio.h> |
| 16 | #include <dt-bindings/input/input.h> | ||
| 16 | 17 | ||
| 17 | / { | 18 | / { |
| 18 | model = "Koelsch"; | 19 | model = "Koelsch"; |
| 19 | compatible = "renesas,koelsch", "renesas,r8a7791"; | 20 | compatible = "renesas,koelsch", "renesas,r8a7791"; |
| 20 | 21 | ||
| 22 | aliases { | ||
| 23 | serial6 = &scif0; | ||
| 24 | serial7 = &scif1; | ||
| 25 | }; | ||
| 26 | |||
| 21 | chosen { | 27 | chosen { |
| 22 | bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; | 28 | bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; |
| 23 | }; | 29 | }; |
| @@ -40,51 +46,79 @@ | |||
| 40 | gpio-keys { | 46 | gpio-keys { |
| 41 | compatible = "gpio-keys"; | 47 | compatible = "gpio-keys"; |
| 42 | 48 | ||
| 49 | key-1 { | ||
| 50 | gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; | ||
| 51 | linux,code = <KEY_1>; | ||
| 52 | label = "SW2-1"; | ||
| 53 | gpio-key,wakeup; | ||
| 54 | debounce-interval = <20>; | ||
| 55 | }; | ||
| 56 | key-2 { | ||
| 57 | gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; | ||
| 58 | linux,code = <KEY_2>; | ||
| 59 | label = "SW2-2"; | ||
| 60 | gpio-key,wakeup; | ||
| 61 | debounce-interval = <20>; | ||
| 62 | }; | ||
| 63 | key-3 { | ||
| 64 | gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; | ||
| 65 | linux,code = <KEY_3>; | ||
| 66 | label = "SW2-3"; | ||
| 67 | gpio-key,wakeup; | ||
| 68 | debounce-interval = <20>; | ||
| 69 | }; | ||
| 70 | key-4 { | ||
| 71 | gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; | ||
| 72 | linux,code = <KEY_4>; | ||
| 73 | label = "SW2-4"; | ||
| 74 | gpio-key,wakeup; | ||
| 75 | debounce-interval = <20>; | ||
| 76 | }; | ||
| 43 | key-a { | 77 | key-a { |
| 44 | gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; | 78 | gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; |
| 45 | linux,code = <30>; | 79 | linux,code = <KEY_A>; |
| 46 | label = "SW30"; | 80 | label = "SW30"; |
| 47 | gpio-key,wakeup; | 81 | gpio-key,wakeup; |
| 48 | debounce-interval = <20>; | 82 | debounce-interval = <20>; |
| 49 | }; | 83 | }; |
| 50 | key-b { | 84 | key-b { |
| 51 | gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; | 85 | gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; |
| 52 | linux,code = <48>; | 86 | linux,code = <KEY_B>; |
| 53 | label = "SW31"; | 87 | label = "SW31"; |
| 54 | gpio-key,wakeup; | 88 | gpio-key,wakeup; |
| 55 | debounce-interval = <20>; | 89 | debounce-interval = <20>; |
| 56 | }; | 90 | }; |
| 57 | key-c { | 91 | key-c { |
| 58 | gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; | 92 | gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; |
| 59 | linux,code = <46>; | 93 | linux,code = <KEY_C>; |
| 60 | label = "SW32"; | 94 | label = "SW32"; |
| 61 | gpio-key,wakeup; | 95 | gpio-key,wakeup; |
| 62 | debounce-interval = <20>; | 96 | debounce-interval = <20>; |
| 63 | }; | 97 | }; |
| 64 | key-d { | 98 | key-d { |
| 65 | gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; | 99 | gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; |
| 66 | linux,code = <32>; | 100 | linux,code = <KEY_D>; |
| 67 | label = "SW33"; | 101 | label = "SW33"; |
| 68 | gpio-key,wakeup; | 102 | gpio-key,wakeup; |
| 69 | debounce-interval = <20>; | 103 | debounce-interval = <20>; |
| 70 | }; | 104 | }; |
| 71 | key-e { | 105 | key-e { |
| 72 | gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; | 106 | gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; |
| 73 | linux,code = <18>; | 107 | linux,code = <KEY_E>; |
| 74 | label = "SW34"; | 108 | label = "SW34"; |
| 75 | gpio-key,wakeup; | 109 | gpio-key,wakeup; |
| 76 | debounce-interval = <20>; | 110 | debounce-interval = <20>; |
| 77 | }; | 111 | }; |
| 78 | key-f { | 112 | key-f { |
| 79 | gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; | 113 | gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; |
| 80 | linux,code = <33>; | 114 | linux,code = <KEY_F>; |
| 81 | label = "SW35"; | 115 | label = "SW35"; |
| 82 | gpio-key,wakeup; | 116 | gpio-key,wakeup; |
| 83 | debounce-interval = <20>; | 117 | debounce-interval = <20>; |
| 84 | }; | 118 | }; |
| 85 | key-g { | 119 | key-g { |
| 86 | gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; | 120 | gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; |
| 87 | linux,code = <34>; | 121 | linux,code = <KEY_G>; |
| 88 | label = "SW36"; | 122 | label = "SW36"; |
| 89 | gpio-key,wakeup; | 123 | gpio-key,wakeup; |
| 90 | debounce-interval = <20>; | 124 | debounce-interval = <20>; |
| @@ -195,11 +229,16 @@ | |||
| 195 | }; | 229 | }; |
| 196 | }; | 230 | }; |
| 197 | 231 | ||
| 232 | &i2c6 { | ||
| 233 | status = "okay"; | ||
| 234 | clock-frequency = <100000>; | ||
| 235 | }; | ||
| 236 | |||
| 198 | &pfc { | 237 | &pfc { |
| 199 | pinctrl-0 = <&du_pins &scif0_pins &scif1_pins>; | 238 | pinctrl-0 = <&du_pins>; |
| 200 | pinctrl-names = "default"; | 239 | pinctrl-names = "default"; |
| 201 | 240 | ||
| 202 | i2c2_pins: i2c { | 241 | i2c2_pins: i2c2 { |
| 203 | renesas,groups = "i2c2"; | 242 | renesas,groups = "i2c2"; |
| 204 | renesas,function = "i2c2"; | 243 | renesas,function = "i2c2"; |
| 205 | }; | 244 | }; |
| @@ -244,10 +283,16 @@ | |||
| 244 | renesas,function = "sdhi2"; | 283 | renesas,function = "sdhi2"; |
| 245 | }; | 284 | }; |
| 246 | 285 | ||
| 247 | qspi_pins: spi { | 286 | qspi_pins: spi0 { |
| 248 | renesas,groups = "qspi_ctrl", "qspi_data4"; | 287 | renesas,groups = "qspi_ctrl", "qspi_data4"; |
| 249 | renesas,function = "qspi"; | 288 | renesas,function = "qspi"; |
| 250 | }; | 289 | }; |
| 290 | |||
| 291 | msiof0_pins: spi1 { | ||
| 292 | renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", | ||
| 293 | "msiof0_tx"; | ||
| 294 | renesas,function = "msiof0"; | ||
| 295 | }; | ||
| 251 | }; | 296 | }; |
| 252 | 297 | ||
| 253 | ðer { | 298 | ðer { |
| @@ -262,6 +307,7 @@ | |||
| 262 | reg = <1>; | 307 | reg = <1>; |
| 263 | interrupt-parent = <&irqc0>; | 308 | interrupt-parent = <&irqc0>; |
| 264 | interrupts = <0 IRQ_TYPE_LEVEL_LOW>; | 309 | interrupts = <0 IRQ_TYPE_LEVEL_LOW>; |
| 310 | micrel,led-mode = <1>; | ||
| 265 | }; | 311 | }; |
| 266 | }; | 312 | }; |
| 267 | 313 | ||
| @@ -269,6 +315,20 @@ | |||
| 269 | status = "okay"; | 315 | status = "okay"; |
| 270 | }; | 316 | }; |
| 271 | 317 | ||
| 318 | &scif0 { | ||
| 319 | pinctrl-0 = <&scif0_pins>; | ||
| 320 | pinctrl-names = "default"; | ||
| 321 | |||
| 322 | status = "okay"; | ||
| 323 | }; | ||
| 324 | |||
| 325 | &scif1 { | ||
| 326 | pinctrl-0 = <&scif1_pins>; | ||
| 327 | pinctrl-names = "default"; | ||
| 328 | |||
| 329 | status = "okay"; | ||
| 330 | }; | ||
| 331 | |||
| 272 | &sdhi0 { | 332 | &sdhi0 { |
| 273 | pinctrl-0 = <&sdhi0_pins>; | 333 | pinctrl-0 = <&sdhi0_pins>; |
| 274 | pinctrl-names = "default"; | 334 | pinctrl-names = "default"; |
| @@ -301,7 +361,7 @@ | |||
| 301 | status = "okay"; | 361 | status = "okay"; |
| 302 | }; | 362 | }; |
| 303 | 363 | ||
| 304 | &spi { | 364 | &qspi { |
| 305 | pinctrl-0 = <&qspi_pins>; | 365 | pinctrl-0 = <&qspi_pins>; |
| 306 | pinctrl-names = "default"; | 366 | pinctrl-names = "default"; |
| 307 | 367 | ||
| @@ -313,6 +373,8 @@ | |||
| 313 | compatible = "spansion,s25fl512s"; | 373 | compatible = "spansion,s25fl512s"; |
| 314 | reg = <0>; | 374 | reg = <0>; |
| 315 | spi-max-frequency = <30000000>; | 375 | spi-max-frequency = <30000000>; |
| 376 | spi-tx-bus-width = <4>; | ||
| 377 | spi-rx-bus-width = <4>; | ||
| 316 | m25p,fast-read; | 378 | m25p,fast-read; |
| 317 | 379 | ||
| 318 | partition@0 { | 380 | partition@0 { |
| @@ -331,3 +393,18 @@ | |||
| 331 | }; | 393 | }; |
| 332 | }; | 394 | }; |
| 333 | }; | 395 | }; |
| 396 | |||
| 397 | &msiof0 { | ||
| 398 | pinctrl-0 = <&msiof0_pins>; | ||
| 399 | pinctrl-names = "default"; | ||
| 400 | |||
| 401 | status = "okay"; | ||
| 402 | |||
| 403 | pmic: pmic@0 { | ||
| 404 | compatible = "renesas,r2a11302ft"; | ||
| 405 | reg = <0>; | ||
| 406 | spi-max-frequency = <6000000>; | ||
| 407 | spi-cpol; | ||
| 408 | spi-cpha; | ||
| 409 | }; | ||
| 410 | }; | ||
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 46181708e59c..8d7ffaeff6e0 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi | |||
| @@ -27,6 +27,13 @@ | |||
| 27 | i2c3 = &i2c3; | 27 | i2c3 = &i2c3; |
| 28 | i2c4 = &i2c4; | 28 | i2c4 = &i2c4; |
| 29 | i2c5 = &i2c5; | 29 | i2c5 = &i2c5; |
| 30 | i2c6 = &i2c6; | ||
| 31 | i2c7 = &i2c7; | ||
| 32 | i2c8 = &i2c8; | ||
| 33 | spi0 = &qspi; | ||
| 34 | spi1 = &msiof0; | ||
| 35 | spi2 = &msiof1; | ||
| 36 | spi3 = &msiof2; | ||
| 30 | }; | 37 | }; |
| 31 | 38 | ||
| 32 | cpus { | 39 | cpus { |
| @@ -37,14 +44,14 @@ | |||
| 37 | device_type = "cpu"; | 44 | device_type = "cpu"; |
| 38 | compatible = "arm,cortex-a15"; | 45 | compatible = "arm,cortex-a15"; |
| 39 | reg = <0>; | 46 | reg = <0>; |
| 40 | clock-frequency = <1300000000>; | 47 | clock-frequency = <1500000000>; |
| 41 | }; | 48 | }; |
| 42 | 49 | ||
| 43 | cpu1: cpu@1 { | 50 | cpu1: cpu@1 { |
| 44 | device_type = "cpu"; | 51 | device_type = "cpu"; |
| 45 | compatible = "arm,cortex-a15"; | 52 | compatible = "arm,cortex-a15"; |
| 46 | reg = <1>; | 53 | reg = <1>; |
| 47 | clock-frequency = <1300000000>; | 54 | clock-frequency = <1500000000>; |
| 48 | }; | 55 | }; |
| 49 | }; | 56 | }; |
| 50 | 57 | ||
| @@ -69,6 +76,7 @@ | |||
| 69 | gpio-ranges = <&pfc 0 0 32>; | 76 | gpio-ranges = <&pfc 0 0 32>; |
| 70 | #interrupt-cells = <2>; | 77 | #interrupt-cells = <2>; |
| 71 | interrupt-controller; | 78 | interrupt-controller; |
| 79 | clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; | ||
| 72 | }; | 80 | }; |
| 73 | 81 | ||
| 74 | gpio1: gpio@e6051000 { | 82 | gpio1: gpio@e6051000 { |
| @@ -80,6 +88,7 @@ | |||
| 80 | gpio-ranges = <&pfc 0 32 32>; | 88 | gpio-ranges = <&pfc 0 32 32>; |
| 81 | #interrupt-cells = <2>; | 89 | #interrupt-cells = <2>; |
| 82 | interrupt-controller; | 90 | interrupt-controller; |
| 91 | clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; | ||
| 83 | }; | 92 | }; |
| 84 | 93 | ||
| 85 | gpio2: gpio@e6052000 { | 94 | gpio2: gpio@e6052000 { |
| @@ -91,6 +100,7 @@ | |||
| 91 | gpio-ranges = <&pfc 0 64 32>; | 100 | gpio-ranges = <&pfc 0 64 32>; |
| 92 | #interrupt-cells = <2>; | 101 | #interrupt-cells = <2>; |
| 93 | interrupt-controller; | 102 | interrupt-controller; |
| 103 | clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; | ||
| 94 | }; | 104 | }; |
| 95 | 105 | ||
| 96 | gpio3: gpio@e6053000 { | 106 | gpio3: gpio@e6053000 { |
| @@ -102,6 +112,7 @@ | |||
| 102 | gpio-ranges = <&pfc 0 96 32>; | 112 | gpio-ranges = <&pfc 0 96 32>; |
| 103 | #interrupt-cells = <2>; | 113 | #interrupt-cells = <2>; |
| 104 | interrupt-controller; | 114 | interrupt-controller; |
| 115 | clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; | ||
| 105 | }; | 116 | }; |
| 106 | 117 | ||
| 107 | gpio4: gpio@e6054000 { | 118 | gpio4: gpio@e6054000 { |
| @@ -113,6 +124,7 @@ | |||
| 113 | gpio-ranges = <&pfc 0 128 32>; | 124 | gpio-ranges = <&pfc 0 128 32>; |
| 114 | #interrupt-cells = <2>; | 125 | #interrupt-cells = <2>; |
| 115 | interrupt-controller; | 126 | interrupt-controller; |
| 127 | clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; | ||
| 116 | }; | 128 | }; |
| 117 | 129 | ||
| 118 | gpio5: gpio@e6055000 { | 130 | gpio5: gpio@e6055000 { |
| @@ -124,6 +136,7 @@ | |||
| 124 | gpio-ranges = <&pfc 0 160 32>; | 136 | gpio-ranges = <&pfc 0 160 32>; |
| 125 | #interrupt-cells = <2>; | 137 | #interrupt-cells = <2>; |
| 126 | interrupt-controller; | 138 | interrupt-controller; |
| 139 | clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; | ||
| 127 | }; | 140 | }; |
| 128 | 141 | ||
| 129 | gpio6: gpio@e6055400 { | 142 | gpio6: gpio@e6055400 { |
| @@ -135,6 +148,7 @@ | |||
| 135 | gpio-ranges = <&pfc 0 192 32>; | 148 | gpio-ranges = <&pfc 0 192 32>; |
| 136 | #interrupt-cells = <2>; | 149 | #interrupt-cells = <2>; |
| 137 | interrupt-controller; | 150 | interrupt-controller; |
| 151 | clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; | ||
| 138 | }; | 152 | }; |
| 139 | 153 | ||
| 140 | gpio7: gpio@e6055800 { | 154 | gpio7: gpio@e6055800 { |
| @@ -146,6 +160,7 @@ | |||
| 146 | gpio-ranges = <&pfc 0 224 26>; | 160 | gpio-ranges = <&pfc 0 224 26>; |
| 147 | #interrupt-cells = <2>; | 161 | #interrupt-cells = <2>; |
| 148 | interrupt-controller; | 162 | interrupt-controller; |
| 163 | clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; | ||
| 149 | }; | 164 | }; |
| 150 | 165 | ||
| 151 | thermal@e61f0000 { | 166 | thermal@e61f0000 { |
| @@ -180,6 +195,7 @@ | |||
| 180 | <0 17 IRQ_TYPE_LEVEL_HIGH>; | 195 | <0 17 IRQ_TYPE_LEVEL_HIGH>; |
| 181 | }; | 196 | }; |
| 182 | 197 | ||
| 198 | /* The memory map in the User's Manual maps the cores to bus numbers */ | ||
| 183 | i2c0: i2c@e6508000 { | 199 | i2c0: i2c@e6508000 { |
| 184 | #address-cells = <1>; | 200 | #address-cells = <1>; |
| 185 | #size-cells = <0>; | 201 | #size-cells = <0>; |
| @@ -231,6 +247,7 @@ | |||
| 231 | }; | 247 | }; |
| 232 | 248 | ||
| 233 | i2c5: i2c@e6528000 { | 249 | i2c5: i2c@e6528000 { |
| 250 | /* doesn't need pinmux */ | ||
| 234 | #address-cells = <1>; | 251 | #address-cells = <1>; |
| 235 | #size-cells = <0>; | 252 | #size-cells = <0>; |
| 236 | compatible = "renesas,i2c-r8a7791"; | 253 | compatible = "renesas,i2c-r8a7791"; |
| @@ -240,6 +257,37 @@ | |||
| 240 | status = "disabled"; | 257 | status = "disabled"; |
| 241 | }; | 258 | }; |
| 242 | 259 | ||
| 260 | i2c6: i2c@e60b0000 { | ||
| 261 | /* doesn't need pinmux */ | ||
| 262 | #address-cells = <1>; | ||
| 263 | #size-cells = <0>; | ||
| 264 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | ||
| 265 | reg = <0 0xe60b0000 0 0x425>; | ||
| 266 | interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; | ||
| 267 | clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; | ||
| 268 | status = "disabled"; | ||
| 269 | }; | ||
| 270 | |||
| 271 | i2c7: i2c@e6500000 { | ||
| 272 | #address-cells = <1>; | ||
| 273 | #size-cells = <0>; | ||
| 274 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | ||
| 275 | reg = <0 0xe6500000 0 0x425>; | ||
| 276 | interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; | ||
| 277 | clocks = <&mstp3_clks R8A7791_CLK_IIC0>; | ||
| 278 | status = "disabled"; | ||
| 279 | }; | ||
| 280 | |||
| 281 | i2c8: i2c@e6510000 { | ||
| 282 | #address-cells = <1>; | ||
| 283 | #size-cells = <0>; | ||
| 284 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | ||
| 285 | reg = <0 0xe6510000 0 0x425>; | ||
| 286 | interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; | ||
| 287 | clocks = <&mstp3_clks R8A7791_CLK_IIC1>; | ||
| 288 | status = "disabled"; | ||
| 289 | }; | ||
| 290 | |||
| 243 | pfc: pfc@e6060000 { | 291 | pfc: pfc@e6060000 { |
| 244 | compatible = "renesas,pfc-r8a7791"; | 292 | compatible = "renesas,pfc-r8a7791"; |
| 245 | reg = <0 0xe6060000 0 0x250>; | 293 | reg = <0 0xe6060000 0 0x250>; |
| @@ -249,7 +297,6 @@ | |||
| 249 | sdhi0: sd@ee100000 { | 297 | sdhi0: sd@ee100000 { |
| 250 | compatible = "renesas,sdhi-r8a7791"; | 298 | compatible = "renesas,sdhi-r8a7791"; |
| 251 | reg = <0 0xee100000 0 0x200>; | 299 | reg = <0 0xee100000 0 0x200>; |
| 252 | interrupt-parent = <&gic>; | ||
| 253 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; | 300 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
| 254 | clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; | 301 | clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; |
| 255 | status = "disabled"; | 302 | status = "disabled"; |
| @@ -258,7 +305,6 @@ | |||
| 258 | sdhi1: sd@ee140000 { | 305 | sdhi1: sd@ee140000 { |
| 259 | compatible = "renesas,sdhi-r8a7791"; | 306 | compatible = "renesas,sdhi-r8a7791"; |
| 260 | reg = <0 0xee140000 0 0x100>; | 307 | reg = <0 0xee140000 0 0x100>; |
| 261 | interrupt-parent = <&gic>; | ||
| 262 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; | 308 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
| 263 | clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; | 309 | clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; |
| 264 | status = "disabled"; | 310 | status = "disabled"; |
| @@ -267,7 +313,6 @@ | |||
| 267 | sdhi2: sd@ee160000 { | 313 | sdhi2: sd@ee160000 { |
| 268 | compatible = "renesas,sdhi-r8a7791"; | 314 | compatible = "renesas,sdhi-r8a7791"; |
| 269 | reg = <0 0xee160000 0 0x100>; | 315 | reg = <0 0xee160000 0 0x100>; |
| 270 | interrupt-parent = <&gic>; | ||
| 271 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; | 316 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; |
| 272 | clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; | 317 | clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; |
| 273 | status = "disabled"; | 318 | status = "disabled"; |
| @@ -688,7 +733,7 @@ | |||
| 688 | renesas,clock-indices = < | 733 | renesas,clock-indices = < |
| 689 | R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 | 734 | R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 |
| 690 | R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 | 735 | R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 |
| 691 | R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY | 736 | R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S |
| 692 | >; | 737 | >; |
| 693 | clock-output-names = | 738 | clock-output-names = |
| 694 | "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", | 739 | "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", |
| @@ -712,15 +757,16 @@ | |||
| 712 | mstp3_clks: mstp3_clks@e615013c { | 757 | mstp3_clks: mstp3_clks@e615013c { |
| 713 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | 758 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 714 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | 759 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; |
| 715 | clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, | 760 | clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, |
| 716 | <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>; | 761 | <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>; |
| 717 | #clock-cells = <1>; | 762 | #clock-cells = <1>; |
| 718 | renesas,clock-indices = < | 763 | renesas,clock-indices = < |
| 719 | R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 | 764 | R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 |
| 720 | R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1 | 765 | R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_CMT1 |
| 721 | >; | 766 | >; |
| 722 | clock-output-names = | 767 | clock-output-names = |
| 723 | "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1"; | 768 | "tpu0", "sdhi2", "sdhi1", "sdhi0", |
| 769 | "mmcif0", "i2c7", "i2c8", "cmt1"; | ||
| 724 | }; | 770 | }; |
| 725 | mstp5_clks: mstp5_clks@e6150144 { | 771 | mstp5_clks: mstp5_clks@e6150144 { |
| 726 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | 772 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| @@ -733,19 +779,19 @@ | |||
| 733 | mstp7_clks: mstp7_clks@e615014c { | 779 | mstp7_clks: mstp7_clks@e615014c { |
| 734 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | 780 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 735 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | 781 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; |
| 736 | clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, | 782 | clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, |
| 737 | <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | 783 | <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
| 738 | <&zx_clk>, <&zx_clk>, <&zx_clk>; | 784 | <&zx_clk>, <&zx_clk>, <&zx_clk>; |
| 739 | #clock-cells = <1>; | 785 | #clock-cells = <1>; |
| 740 | renesas,clock-indices = < | 786 | renesas,clock-indices = < |
| 741 | R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 | 787 | R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 |
| 742 | R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 | 788 | R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 |
| 743 | R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 | 789 | R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 |
| 744 | R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 | 790 | R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 |
| 745 | R8A7791_CLK_LVDS0 | 791 | R8A7791_CLK_LVDS0 |
| 746 | >; | 792 | >; |
| 747 | clock-output-names = | 793 | clock-output-names = |
| 748 | "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", | 794 | "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", |
| 749 | "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; | 795 | "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; |
| 750 | }; | 796 | }; |
| 751 | mstp8_clks: mstp8_clks@e6150990 { | 797 | mstp8_clks: mstp8_clks@e6150990 { |
| @@ -764,18 +810,23 @@ | |||
| 764 | mstp9_clks: mstp9_clks@e6150994 { | 810 | mstp9_clks: mstp9_clks@e6150994 { |
| 765 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | 811 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 766 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | 812 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; |
| 767 | clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, | 813 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
| 768 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | 814 | <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
| 769 | <&p_clk>; | 815 | <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, |
| 816 | <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, | ||
| 817 | <&hp_clk>, <&hp_clk>; | ||
| 770 | #clock-cells = <1>; | 818 | #clock-cells = <1>; |
| 771 | renesas,clock-indices = < | 819 | renesas,clock-indices = < |
| 772 | R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD | 820 | R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 |
| 773 | R8A7791_CLK_I2C5 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 | 821 | R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 |
| 774 | R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 | 822 | R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 |
| 823 | R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 | ||
| 824 | R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 | ||
| 775 | >; | 825 | >; |
| 776 | clock-output-names = | 826 | clock-output-names = |
| 777 | "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3", | 827 | "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", |
| 778 | "i2c2", "i2c1", "i2c0"; | 828 | "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", |
| 829 | "i2c1", "i2c0"; | ||
| 779 | }; | 830 | }; |
| 780 | mstp11_clks: mstp11_clks@e615099c { | 831 | mstp11_clks: mstp11_clks@e615099c { |
| 781 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | 832 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| @@ -789,7 +840,7 @@ | |||
| 789 | }; | 840 | }; |
| 790 | }; | 841 | }; |
| 791 | 842 | ||
| 792 | spi: spi@e6b10000 { | 843 | qspi: spi@e6b10000 { |
| 793 | compatible = "renesas,qspi-r8a7791", "renesas,qspi"; | 844 | compatible = "renesas,qspi-r8a7791", "renesas,qspi"; |
| 794 | reg = <0 0xe6b10000 0 0x2c>; | 845 | reg = <0 0xe6b10000 0 0x2c>; |
| 795 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; | 846 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -799,4 +850,34 @@ | |||
| 799 | #size-cells = <0>; | 850 | #size-cells = <0>; |
| 800 | status = "disabled"; | 851 | status = "disabled"; |
| 801 | }; | 852 | }; |
| 853 | |||
| 854 | msiof0: spi@e6e20000 { | ||
| 855 | compatible = "renesas,msiof-r8a7791"; | ||
| 856 | reg = <0 0xe6e20000 0 0x0064>; | ||
| 857 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; | ||
| 858 | clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; | ||
| 859 | #address-cells = <1>; | ||
| 860 | #size-cells = <0>; | ||
| 861 | status = "disabled"; | ||
| 862 | }; | ||
| 863 | |||
| 864 | msiof1: spi@e6e10000 { | ||
| 865 | compatible = "renesas,msiof-r8a7791"; | ||
| 866 | reg = <0 0xe6e10000 0 0x0064>; | ||
| 867 | interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; | ||
| 868 | clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; | ||
| 869 | #address-cells = <1>; | ||
| 870 | #size-cells = <0>; | ||
| 871 | status = "disabled"; | ||
| 872 | }; | ||
| 873 | |||
| 874 | msiof2: spi@e6e00000 { | ||
| 875 | compatible = "renesas,msiof-r8a7791"; | ||
| 876 | reg = <0 0xe6e00000 0 0x0064>; | ||
| 877 | interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; | ||
| 878 | clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; | ||
| 879 | #address-cells = <1>; | ||
| 880 | #size-cells = <0>; | ||
| 881 | status = "disabled"; | ||
| 882 | }; | ||
| 802 | }; | 883 | }; |
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 035df4053c21..afb327322a4a 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | 18 | ||
| 19 | / { | 19 | / { |
| 20 | model = "bq Curie 2"; | 20 | model = "bq Curie 2"; |
| 21 | compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; | ||
| 21 | 22 | ||
| 22 | memory { | 23 | memory { |
| 23 | reg = <0x60000000 0x40000000>; | 24 | reg = <0x60000000 0x40000000>; |
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 4d4dfbb59f4b..4387cfd420ba 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | cpus { | 24 | cpus { |
| 25 | #address-cells = <1>; | 25 | #address-cells = <1>; |
| 26 | #size-cells = <0>; | 26 | #size-cells = <0>; |
| 27 | enable-method = "rockchip,rk3066-smp"; | ||
| 27 | 28 | ||
| 28 | cpu@0 { | 29 | cpu@0 { |
| 29 | device_type = "cpu"; | 30 | device_type = "cpu"; |
| @@ -79,7 +80,7 @@ | |||
| 79 | 80 | ||
| 80 | pinctrl@20008000 { | 81 | pinctrl@20008000 { |
| 81 | compatible = "rockchip,rk3066a-pinctrl"; | 82 | compatible = "rockchip,rk3066a-pinctrl"; |
| 82 | reg = <0x20008000 0x150>; | 83 | rockchip,grf = <&grf>; |
| 83 | #address-cells = <1>; | 84 | #address-cells = <1>; |
| 84 | #size-cells = <1>; | 85 | #size-cells = <1>; |
| 85 | ranges; | 86 | ranges; |
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 3ba1968a70ab..a5eee55079cb 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | 17 | ||
| 18 | / { | 18 | / { |
| 19 | model = "Radxa Rock"; | 19 | model = "Radxa Rock"; |
| 20 | compatible = "radxa,rock", "rockchip,rk3188"; | ||
| 20 | 21 | ||
| 21 | memory { | 22 | memory { |
| 22 | reg = <0x60000000 0x80000000>; | 23 | reg = <0x60000000 0x80000000>; |
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index ed9a70af3e3f..238c996d4a7f 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | cpus { | 24 | cpus { |
| 25 | #address-cells = <1>; | 25 | #address-cells = <1>; |
| 26 | #size-cells = <0>; | 26 | #size-cells = <0>; |
| 27 | enable-method = "rockchip,rk3066-smp"; | ||
| 27 | 28 | ||
| 28 | cpu@0 { | 29 | cpu@0 { |
| 29 | device_type = "cpu"; | 30 | device_type = "cpu"; |
| @@ -75,17 +76,16 @@ | |||
| 75 | 76 | ||
| 76 | pinctrl@20008000 { | 77 | pinctrl@20008000 { |
| 77 | compatible = "rockchip,rk3188-pinctrl"; | 78 | compatible = "rockchip,rk3188-pinctrl"; |
| 78 | reg = <0x20008000 0xa0>, | 79 | rockchip,grf = <&grf>; |
| 79 | <0x20008164 0x1a0>; | 80 | rockchip,pmu = <&pmu>; |
| 80 | reg-names = "base", "pull"; | 81 | |
| 81 | #address-cells = <1>; | 82 | #address-cells = <1>; |
| 82 | #size-cells = <1>; | 83 | #size-cells = <1>; |
| 83 | ranges; | 84 | ranges; |
| 84 | 85 | ||
| 85 | gpio0: gpio0@0x2000a000 { | 86 | gpio0: gpio0@0x2000a000 { |
| 86 | compatible = "rockchip,rk3188-gpio-bank0"; | 87 | compatible = "rockchip,rk3188-gpio-bank0"; |
| 87 | reg = <0x2000a000 0x100>, | 88 | reg = <0x2000a000 0x100>; |
| 88 | <0x20004064 0x8>; | ||
| 89 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | 89 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
| 90 | clocks = <&clk_gates8 9>; | 90 | clocks = <&clk_gates8 9>; |
| 91 | 91 | ||
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 26e5a968d49d..2adf1cc9e85d 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi | |||
| @@ -31,11 +31,16 @@ | |||
| 31 | reg = <0x1013c000 0x100>; | 31 | reg = <0x1013c000 0x100>; |
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| 34 | pmu@20004000 { | 34 | pmu: pmu@20004000 { |
| 35 | compatible = "rockchip,rk3066-pmu"; | 35 | compatible = "rockchip,rk3066-pmu", "syscon"; |
| 36 | reg = <0x20004000 0x100>; | 36 | reg = <0x20004000 0x100>; |
| 37 | }; | 37 | }; |
| 38 | 38 | ||
| 39 | grf: grf@20008000 { | ||
| 40 | compatible = "syscon"; | ||
| 41 | reg = <0x20008000 0x200>; | ||
| 42 | }; | ||
| 43 | |||
| 39 | gic: interrupt-controller@1013d000 { | 44 | gic: interrupt-controller@1013d000 { |
| 40 | compatible = "arm,cortex-a9-gic"; | 45 | compatible = "arm,cortex-a9-gic"; |
| 41 | interrupt-controller; | 46 | interrupt-controller; |
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts index 59594cf15998..ea92fd69529a 100644 --- a/arch/arm/boot/dts/s3c2416-smdk2416.dts +++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts | |||
| @@ -19,6 +19,19 @@ | |||
| 19 | reg = <0x30000000 0x4000000>; | 19 | reg = <0x30000000 0x4000000>; |
| 20 | }; | 20 | }; |
| 21 | 21 | ||
| 22 | clocks { | ||
| 23 | compatible = "simple-bus"; | ||
| 24 | #address-cells = <1>; | ||
| 25 | #size-cells = <1>; | ||
| 26 | |||
| 27 | xti: xti { | ||
| 28 | compatible = "fixed-clock"; | ||
| 29 | clock-frequency = <12000000>; | ||
| 30 | clock-output-names = "xti"; | ||
| 31 | #clock-cells = <0>; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | |||
| 22 | serial@50000000 { | 35 | serial@50000000 { |
| 23 | status = "okay"; | 36 | status = "okay"; |
| 24 | pinctrl-names = "default"; | 37 | pinctrl-names = "default"; |
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi index e6555bdd81b8..955e4a4f8c31 100644 --- a/arch/arm/boot/dts/s3c2416.dtsi +++ b/arch/arm/boot/dts/s3c2416.dtsi | |||
| @@ -8,6 +8,7 @@ | |||
| 8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <dt-bindings/clock/s3c2443.h> | ||
| 11 | #include "s3c24xx.dtsi" | 12 | #include "s3c24xx.dtsi" |
| 12 | #include "s3c2416-pinctrl.dtsi" | 13 | #include "s3c2416-pinctrl.dtsi" |
| 13 | 14 | ||
| @@ -28,26 +29,53 @@ | |||
| 28 | compatible = "samsung,s3c2416-irq"; | 29 | compatible = "samsung,s3c2416-irq"; |
| 29 | }; | 30 | }; |
| 30 | 31 | ||
| 32 | clocks: clock-controller@0x4c000000 { | ||
| 33 | compatible = "samsung,s3c2416-clock"; | ||
| 34 | reg = <0x4c000000 0x40>; | ||
| 35 | #clock-cells = <1>; | ||
| 36 | }; | ||
| 37 | |||
| 31 | pinctrl@56000000 { | 38 | pinctrl@56000000 { |
| 32 | compatible = "samsung,s3c2416-pinctrl"; | 39 | compatible = "samsung,s3c2416-pinctrl"; |
| 33 | }; | 40 | }; |
| 34 | 41 | ||
| 42 | timer@51000000 { | ||
| 43 | clocks = <&clocks PCLK_PWM>; | ||
| 44 | clock-names = "timers"; | ||
| 45 | }; | ||
| 46 | |||
| 35 | serial@50000000 { | 47 | serial@50000000 { |
| 36 | compatible = "samsung,s3c2440-uart"; | 48 | compatible = "samsung,s3c2440-uart"; |
| 49 | clock-names = "uart", "clk_uart_baud2", | ||
| 50 | "clk_uart_baud3"; | ||
| 51 | clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, | ||
| 52 | <&clocks SCLK_UART>; | ||
| 37 | }; | 53 | }; |
| 38 | 54 | ||
| 39 | serial@50004000 { | 55 | serial@50004000 { |
| 40 | compatible = "samsung,s3c2440-uart"; | 56 | compatible = "samsung,s3c2440-uart"; |
| 57 | clock-names = "uart", "clk_uart_baud2", | ||
| 58 | "clk_uart_baud3"; | ||
| 59 | clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, | ||
| 60 | <&clocks SCLK_UART>; | ||
| 41 | }; | 61 | }; |
| 42 | 62 | ||
| 43 | serial@50008000 { | 63 | serial@50008000 { |
| 44 | compatible = "samsung,s3c2440-uart"; | 64 | compatible = "samsung,s3c2440-uart"; |
| 65 | clock-names = "uart", "clk_uart_baud2", | ||
| 66 | "clk_uart_baud3"; | ||
| 67 | clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, | ||
| 68 | <&clocks SCLK_UART>; | ||
| 45 | }; | 69 | }; |
| 46 | 70 | ||
| 47 | serial@5000C000 { | 71 | serial@5000C000 { |
| 48 | compatible = "samsung,s3c2440-uart"; | 72 | compatible = "samsung,s3c2440-uart"; |
| 49 | reg = <0x5000C000 0x4000>; | 73 | reg = <0x5000C000 0x4000>; |
| 50 | interrupts = <1 18 24 4>, <1 18 25 4>; | 74 | interrupts = <1 18 24 4>, <1 18 25 4>; |
| 75 | clock-names = "uart", "clk_uart_baud2", | ||
| 76 | "clk_uart_baud3"; | ||
| 77 | clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>, | ||
| 78 | <&clocks SCLK_UART>; | ||
| 51 | status = "disabled"; | 79 | status = "disabled"; |
| 52 | }; | 80 | }; |
| 53 | 81 | ||
| @@ -55,6 +83,10 @@ | |||
| 55 | compatible = "samsung,s3c6410-sdhci"; | 83 | compatible = "samsung,s3c6410-sdhci"; |
| 56 | reg = <0x4AC00000 0x100>; | 84 | reg = <0x4AC00000 0x100>; |
| 57 | interrupts = <0 0 21 3>; | 85 | interrupts = <0 0 21 3>; |
| 86 | clock-names = "hsmmc", "mmc_busclk.0", | ||
| 87 | "mmc_busclk.2"; | ||
| 88 | clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>, | ||
| 89 | <&clocks MUX_HSMMC0>; | ||
| 58 | status = "disabled"; | 90 | status = "disabled"; |
| 59 | }; | 91 | }; |
| 60 | 92 | ||
| @@ -62,18 +94,28 @@ | |||
| 62 | compatible = "samsung,s3c6410-sdhci"; | 94 | compatible = "samsung,s3c6410-sdhci"; |
| 63 | reg = <0x4A800000 0x100>; | 95 | reg = <0x4A800000 0x100>; |
| 64 | interrupts = <0 0 20 3>; | 96 | interrupts = <0 0 20 3>; |
| 97 | clock-names = "hsmmc", "mmc_busclk.0", | ||
| 98 | "mmc_busclk.2"; | ||
| 99 | clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>, | ||
| 100 | <&clocks MUX_HSMMC1>; | ||
| 65 | status = "disabled"; | 101 | status = "disabled"; |
| 66 | }; | 102 | }; |
| 67 | 103 | ||
| 68 | watchdog@53000000 { | 104 | watchdog@53000000 { |
| 69 | interrupts = <1 9 27 3>; | 105 | interrupts = <1 9 27 3>; |
| 106 | clocks = <&clocks PCLK_WDT>; | ||
| 107 | clock-names = "watchdog"; | ||
| 70 | }; | 108 | }; |
| 71 | 109 | ||
| 72 | rtc@57000000 { | 110 | rtc@57000000 { |
| 73 | compatible = "samsung,s3c2416-rtc"; | 111 | compatible = "samsung,s3c2416-rtc"; |
| 112 | clocks = <&clocks PCLK_RTC>; | ||
| 113 | clock-names = "rtc"; | ||
| 74 | }; | 114 | }; |
| 75 | 115 | ||
| 76 | i2c@54000000 { | 116 | i2c@54000000 { |
| 77 | compatible = "samsung,s3c2440-i2c"; | 117 | compatible = "samsung,s3c2440-i2c"; |
| 118 | clocks = <&clocks PCLK_I2C0>; | ||
| 119 | clock-names = "i2c"; | ||
| 78 | }; | 120 | }; |
| 79 | }; | 121 | }; |
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index a106b0872910..e0b15a6e8897 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi | |||
| @@ -58,6 +58,18 @@ | |||
| 58 | reg = <0x20000000 0x8000000>; | 58 | reg = <0x20000000 0x8000000>; |
| 59 | }; | 59 | }; |
| 60 | 60 | ||
| 61 | slow_xtal: slow_xtal { | ||
| 62 | compatible = "fixed-clock"; | ||
| 63 | #clock-cells = <0>; | ||
| 64 | clock-frequency = <0>; | ||
| 65 | }; | ||
| 66 | |||
| 67 | main_xtal: main_xtal { | ||
| 68 | compatible = "fixed-clock"; | ||
| 69 | #clock-cells = <0>; | ||
| 70 | clock-frequency = <0>; | ||
| 71 | }; | ||
| 72 | |||
| 61 | clocks { | 73 | clocks { |
| 62 | adc_op_clk: adc_op_clk{ | 74 | adc_op_clk: adc_op_clk{ |
| 63 | compatible = "fixed-clock"; | 75 | compatible = "fixed-clock"; |
| @@ -113,6 +125,9 @@ | |||
| 113 | compatible = "atmel,at91sam9g45-ssc"; | 125 | compatible = "atmel,at91sam9g45-ssc"; |
| 114 | reg = <0xf0008000 0x4000>; | 126 | reg = <0xf0008000 0x4000>; |
| 115 | interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; | 127 | interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; |
| 128 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>, | ||
| 129 | <&dma0 2 AT91_DMA_CFG_PER_ID(14)>; | ||
| 130 | dma-names = "tx", "rx"; | ||
| 116 | pinctrl-names = "default"; | 131 | pinctrl-names = "default"; |
| 117 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | 132 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 118 | clocks = <&ssc0_clk>; | 133 | clocks = <&ssc0_clk>; |
| @@ -231,6 +246,9 @@ | |||
| 231 | compatible = "atmel,at91sam9g45-ssc"; | 246 | compatible = "atmel,at91sam9g45-ssc"; |
| 232 | reg = <0xf800c000 0x4000>; | 247 | reg = <0xf800c000 0x4000>; |
| 233 | interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; | 248 | interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; |
| 249 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>, | ||
| 250 | <&dma1 2 AT91_DMA_CFG_PER_ID(4)>; | ||
| 251 | dma-names = "tx", "rx"; | ||
| 234 | pinctrl-names = "default"; | 252 | pinctrl-names = "default"; |
| 235 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | 253 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; |
| 236 | clocks = <&ssc1_clk>; | 254 | clocks = <&ssc1_clk>; |
| @@ -577,6 +595,84 @@ | |||
| 577 | }; | 595 | }; |
| 578 | }; | 596 | }; |
| 579 | 597 | ||
| 598 | pwm0 { | ||
| 599 | pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { | ||
| 600 | atmel,pins = | ||
| 601 | <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */ | ||
| 602 | }; | ||
| 603 | pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { | ||
| 604 | atmel,pins = | ||
| 605 | <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */ | ||
| 606 | }; | ||
| 607 | pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { | ||
| 608 | atmel,pins = | ||
| 609 | <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */ | ||
| 610 | }; | ||
| 611 | pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { | ||
| 612 | atmel,pins = | ||
| 613 | <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */ | ||
| 614 | }; | ||
| 615 | |||
| 616 | pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { | ||
| 617 | atmel,pins = | ||
| 618 | <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */ | ||
| 619 | }; | ||
| 620 | pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { | ||
| 621 | atmel,pins = | ||
| 622 | <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */ | ||
| 623 | }; | ||
| 624 | pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { | ||
| 625 | atmel,pins = | ||
| 626 | <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */ | ||
| 627 | }; | ||
| 628 | pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { | ||
| 629 | atmel,pins = | ||
| 630 | <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */ | ||
| 631 | }; | ||
| 632 | pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { | ||
| 633 | atmel,pins = | ||
| 634 | <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */ | ||
| 635 | }; | ||
| 636 | pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { | ||
| 637 | atmel,pins = | ||
| 638 | <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */ | ||
| 639 | }; | ||
| 640 | |||
| 641 | pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { | ||
| 642 | atmel,pins = | ||
| 643 | <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */ | ||
| 644 | }; | ||
| 645 | pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { | ||
| 646 | atmel,pins = | ||
| 647 | <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */ | ||
| 648 | }; | ||
| 649 | pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 { | ||
| 650 | atmel,pins = | ||
| 651 | <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */ | ||
| 652 | }; | ||
| 653 | pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 { | ||
| 654 | atmel,pins = | ||
| 655 | <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */ | ||
| 656 | }; | ||
| 657 | |||
| 658 | pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { | ||
| 659 | atmel,pins = | ||
| 660 | <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */ | ||
| 661 | }; | ||
| 662 | pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { | ||
| 663 | atmel,pins = | ||
| 664 | <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */ | ||
| 665 | }; | ||
| 666 | pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 { | ||
| 667 | atmel,pins = | ||
| 668 | <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */ | ||
| 669 | }; | ||
| 670 | pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 { | ||
| 671 | atmel,pins = | ||
| 672 | <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */ | ||
| 673 | }; | ||
| 674 | }; | ||
| 675 | |||
| 580 | spi0 { | 676 | spi0 { |
| 581 | pinctrl_spi0: spi0-0 { | 677 | pinctrl_spi0: spi0-0 { |
| 582 | atmel,pins = | 678 | atmel,pins = |
| @@ -749,18 +845,29 @@ | |||
| 749 | #size-cells = <0>; | 845 | #size-cells = <0>; |
| 750 | #interrupt-cells = <1>; | 846 | #interrupt-cells = <1>; |
| 751 | 847 | ||
| 752 | clk32k: slck { | 848 | main_rc_osc: main_rc_osc { |
| 753 | compatible = "fixed-clock"; | 849 | compatible = "atmel,at91sam9x5-clk-main-rc-osc"; |
| 754 | #clock-cells = <0>; | 850 | #clock-cells = <0>; |
| 755 | clock-frequency = <32768>; | 851 | interrupt-parent = <&pmc>; |
| 852 | interrupts = <AT91_PMC_MOSCRCS>; | ||
| 853 | clock-frequency = <12000000>; | ||
| 854 | clock-accuracy = <50000000>; | ||
| 756 | }; | 855 | }; |
| 757 | 856 | ||
| 758 | main: mainck { | 857 | main_osc: main_osc { |
| 759 | compatible = "atmel,at91rm9200-clk-main"; | 858 | compatible = "atmel,at91rm9200-clk-main-osc"; |
| 760 | #clock-cells = <0>; | 859 | #clock-cells = <0>; |
| 761 | interrupt-parent = <&pmc>; | 860 | interrupt-parent = <&pmc>; |
| 762 | interrupts = <AT91_PMC_MOSCS>; | 861 | interrupts = <AT91_PMC_MOSCS>; |
| 763 | clocks = <&clk32k>; | 862 | clocks = <&main_xtal>; |
| 863 | }; | ||
| 864 | |||
| 865 | main: mainck { | ||
| 866 | compatible = "atmel,at91sam9x5-clk-main"; | ||
| 867 | #clock-cells = <0>; | ||
| 868 | interrupt-parent = <&pmc>; | ||
| 869 | interrupts = <AT91_PMC_MOSCSELS>; | ||
| 870 | clocks = <&main_rc_osc &main_osc>; | ||
| 764 | }; | 871 | }; |
| 765 | 872 | ||
| 766 | plla: pllack { | 873 | plla: pllack { |
| @@ -1089,6 +1196,32 @@ | |||
| 1089 | status = "disabled"; | 1196 | status = "disabled"; |
| 1090 | }; | 1197 | }; |
| 1091 | 1198 | ||
| 1199 | sckc@fffffe50 { | ||
| 1200 | compatible = "atmel,at91sam9x5-sckc"; | ||
| 1201 | reg = <0xfffffe50 0x4>; | ||
| 1202 | |||
| 1203 | slow_rc_osc: slow_rc_osc { | ||
| 1204 | compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; | ||
| 1205 | #clock-cells = <0>; | ||
| 1206 | clock-frequency = <32768>; | ||
| 1207 | clock-accuracy = <50000000>; | ||
| 1208 | atmel,startup-time-usec = <75>; | ||
| 1209 | }; | ||
| 1210 | |||
| 1211 | slow_osc: slow_osc { | ||
| 1212 | compatible = "atmel,at91sam9x5-clk-slow-osc"; | ||
| 1213 | #clock-cells = <0>; | ||
| 1214 | clocks = <&slow_xtal>; | ||
| 1215 | atmel,startup-time-usec = <1200000>; | ||
| 1216 | }; | ||
| 1217 | |||
| 1218 | clk32k: slowck { | ||
| 1219 | compatible = "atmel,at91sam9x5-clk-slow"; | ||
| 1220 | #clock-cells = <0>; | ||
| 1221 | clocks = <&slow_rc_osc &slow_osc>; | ||
| 1222 | }; | ||
| 1223 | }; | ||
| 1224 | |||
| 1092 | rtc@fffffeb0 { | 1225 | rtc@fffffeb0 { |
| 1093 | compatible = "atmel,at91rm9200-rtc"; | 1226 | compatible = "atmel,at91rm9200-rtc"; |
| 1094 | reg = <0xfffffeb0 0x30>; | 1227 | reg = <0xfffffeb0 0x30>; |
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index f55ed072c8e6..b0b1331c1974 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi | |||
| @@ -18,6 +18,14 @@ | |||
| 18 | reg = <0x20000000 0x20000000>; | 18 | reg = <0x20000000 0x20000000>; |
| 19 | }; | 19 | }; |
| 20 | 20 | ||
| 21 | slow_xtal { | ||
| 22 | clock-frequency = <32768>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | main_xtal { | ||
| 26 | clock-frequency = <12000000>; | ||
| 27 | }; | ||
| 28 | |||
| 21 | ahb { | 29 | ahb { |
| 22 | apb { | 30 | apb { |
| 23 | spi0: spi@f0004000 { | 31 | spi0: spi@f0004000 { |
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index dba739b6ef36..306eef0f97ef 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi | |||
| @@ -32,6 +32,10 @@ | |||
| 32 | }; | 32 | }; |
| 33 | }; | 33 | }; |
| 34 | 34 | ||
| 35 | ssc0: ssc@f0008000 { | ||
| 36 | atmel,clk-from-rk-pin; | ||
| 37 | }; | ||
| 38 | |||
| 35 | /* | 39 | /* |
| 36 | * i2c0 conflicts with ISI: | 40 | * i2c0 conflicts with ISI: |
| 37 | * disable it to allow the use of ISI | 41 | * disable it to allow the use of ISI |
| @@ -156,7 +160,7 @@ | |||
| 156 | }; | 160 | }; |
| 157 | 161 | ||
| 158 | sound { | 162 | sound { |
| 159 | compatible = "atmel,sama5d3ek-wm8904"; | 163 | compatible = "atmel,asoc-wm8904"; |
| 160 | pinctrl-names = "default"; | 164 | pinctrl-names = "default"; |
| 161 | pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; | 165 | pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; |
| 162 | 166 | ||
| @@ -166,9 +170,12 @@ | |||
| 166 | "Headphone Jack", "HPOUTR", | 170 | "Headphone Jack", "HPOUTR", |
| 167 | "IN2L", "Line In Jack", | 171 | "IN2L", "Line In Jack", |
| 168 | "IN2R", "Line In Jack", | 172 | "IN2R", "Line In Jack", |
| 173 | "MICBIAS", "IN1L", | ||
| 169 | "IN1L", "Mic"; | 174 | "IN1L", "Mic"; |
| 170 | 175 | ||
| 171 | atmel,ssc-controller = <&ssc0>; | 176 | atmel,ssc-controller = <&ssc0>; |
| 172 | atmel,audio-codec = <&wm8904>; | 177 | atmel,audio-codec = <&wm8904>; |
| 178 | |||
| 179 | status = "disabled"; | ||
| 173 | }; | 180 | }; |
| 174 | }; | 181 | }; |
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index eb8886b535e4..a99171c8a782 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | /dts-v1/; | 14 | /dts-v1/; |
| 15 | #include "sh73a0.dtsi" | 15 | #include "sh73a0.dtsi" |
| 16 | #include <dt-bindings/gpio/gpio.h> | 16 | #include <dt-bindings/gpio/gpio.h> |
| 17 | #include <dt-bindings/input/input.h> | ||
| 17 | #include <dt-bindings/interrupt-controller/irq.h> | 18 | #include <dt-bindings/interrupt-controller/irq.h> |
| 18 | 19 | ||
| 19 | / { | 20 | / { |
| @@ -112,43 +113,43 @@ | |||
| 112 | 113 | ||
| 113 | back-key { | 114 | back-key { |
| 114 | gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>; | 115 | gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>; |
| 115 | linux,code = <158>; | 116 | linux,code = <KEY_BACK>; |
| 116 | label = "SW3"; | 117 | label = "SW3"; |
| 117 | }; | 118 | }; |
| 118 | 119 | ||
| 119 | right-key { | 120 | right-key { |
| 120 | gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>; | 121 | gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>; |
| 121 | linux,code = <106>; | 122 | linux,code = <KEY_RIGHT>; |
| 122 | label = "SW2-R"; | 123 | label = "SW2-R"; |
| 123 | }; | 124 | }; |
| 124 | 125 | ||
| 125 | left-key { | 126 | left-key { |
| 126 | gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>; | 127 | gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>; |
| 127 | linux,code = <105>; | 128 | linux,code = <KEY_LEFT>; |
| 128 | label = "SW2-L"; | 129 | label = "SW2-L"; |
| 129 | }; | 130 | }; |
| 130 | 131 | ||
| 131 | enter-key { | 132 | enter-key { |
| 132 | gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>; | 133 | gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>; |
| 133 | linux,code = <28>; | 134 | linux,code = <KEY_ENTER>; |
| 134 | label = "SW2-P"; | 135 | label = "SW2-P"; |
| 135 | }; | 136 | }; |
| 136 | 137 | ||
| 137 | up-key { | 138 | up-key { |
| 138 | gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>; | 139 | gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>; |
| 139 | linux,code = <103>; | 140 | linux,code = <KEY_UP>; |
| 140 | label = "SW2-U"; | 141 | label = "SW2-U"; |
| 141 | }; | 142 | }; |
| 142 | 143 | ||
| 143 | down-key { | 144 | down-key { |
| 144 | gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>; | 145 | gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>; |
| 145 | linux,code = <108>; | 146 | linux,code = <KEY_DOWN>; |
| 146 | label = "SW2-D"; | 147 | label = "SW2-D"; |
| 147 | }; | 148 | }; |
| 148 | 149 | ||
| 149 | home-key { | 150 | home-key { |
| 150 | gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>; | 151 | gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>; |
| 151 | linux,code = <102>; | 152 | linux,code = <KEY_HOME>; |
| 152 | label = "SW1"; | 153 | label = "SW1"; |
| 153 | }; | 154 | }; |
| 154 | }; | 155 | }; |
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 56fc214e6d2c..4676f25e87a7 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi | |||
| @@ -15,7 +15,8 @@ | |||
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ | 16 | */ |
| 17 | 17 | ||
| 18 | /include/ "skeleton.dtsi" | 18 | #include "skeleton.dtsi" |
| 19 | #include <dt-bindings/reset/altr,rst-mgr.h> | ||
| 19 | 20 | ||
| 20 | / { | 21 | / { |
| 21 | #address-cells = <1>; | 22 | #address-cells = <1>; |
| @@ -75,7 +76,14 @@ | |||
| 75 | pdma: pdma@ffe01000 { | 76 | pdma: pdma@ffe01000 { |
| 76 | compatible = "arm,pl330", "arm,primecell"; | 77 | compatible = "arm,pl330", "arm,primecell"; |
| 77 | reg = <0xffe01000 0x1000>; | 78 | reg = <0xffe01000 0x1000>; |
| 78 | interrupts = <0 180 4>; | 79 | interrupts = <0 104 4>, |
| 80 | <0 105 4>, | ||
| 81 | <0 106 4>, | ||
| 82 | <0 107 4>, | ||
| 83 | <0 108 4>, | ||
| 84 | <0 109 4>, | ||
| 85 | <0 110 4>, | ||
| 86 | <0 111 4>; | ||
| 79 | #dma-cells = <1>; | 87 | #dma-cells = <1>; |
| 80 | #dma-channels = <8>; | 88 | #dma-channels = <8>; |
| 81 | #dma-requests = <32>; | 89 | #dma-requests = <32>; |
| @@ -84,6 +92,22 @@ | |||
| 84 | }; | 92 | }; |
| 85 | }; | 93 | }; |
| 86 | 94 | ||
| 95 | can0: can@ffc00000 { | ||
| 96 | compatible = "bosch,d_can"; | ||
| 97 | reg = <0xffc00000 0x1000>; | ||
| 98 | interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; | ||
| 99 | clocks = <&can0_clk>; | ||
| 100 | status = "disabled"; | ||
| 101 | }; | ||
| 102 | |||
| 103 | can1: can@ffc01000 { | ||
| 104 | compatible = "bosch,d_can"; | ||
| 105 | reg = <0xffc01000 0x1000>; | ||
| 106 | interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; | ||
| 107 | clocks = <&can1_clk>; | ||
| 108 | status = "disabled"; | ||
| 109 | }; | ||
| 110 | |||
| 87 | clkmgr@ffd04000 { | 111 | clkmgr@ffd04000 { |
| 88 | compatible = "altr,clk-mgr"; | 112 | compatible = "altr,clk-mgr"; |
| 89 | reg = <0xffd04000 0x1000>; | 113 | reg = <0xffd04000 0x1000>; |
| @@ -124,7 +148,7 @@ | |||
| 124 | #clock-cells = <0>; | 148 | #clock-cells = <0>; |
| 125 | compatible = "altr,socfpga-perip-clk"; | 149 | compatible = "altr,socfpga-perip-clk"; |
| 126 | clocks = <&main_pll>; | 150 | clocks = <&main_pll>; |
| 127 | fixed-divider = <2>; | 151 | div-reg = <0xe0 0 9>; |
| 128 | reg = <0x48>; | 152 | reg = <0x48>; |
| 129 | }; | 153 | }; |
| 130 | 154 | ||
| @@ -132,7 +156,7 @@ | |||
| 132 | #clock-cells = <0>; | 156 | #clock-cells = <0>; |
| 133 | compatible = "altr,socfpga-perip-clk"; | 157 | compatible = "altr,socfpga-perip-clk"; |
| 134 | clocks = <&main_pll>; | 158 | clocks = <&main_pll>; |
| 135 | fixed-divider = <4>; | 159 | div-reg = <0xe4 0 9>; |
| 136 | reg = <0x4C>; | 160 | reg = <0x4C>; |
| 137 | }; | 161 | }; |
| 138 | 162 | ||
| @@ -140,7 +164,7 @@ | |||
| 140 | #clock-cells = <0>; | 164 | #clock-cells = <0>; |
| 141 | compatible = "altr,socfpga-perip-clk"; | 165 | compatible = "altr,socfpga-perip-clk"; |
| 142 | clocks = <&main_pll>; | 166 | clocks = <&main_pll>; |
| 143 | fixed-divider = <4>; | 167 | div-reg = <0xe8 0 9>; |
| 144 | reg = <0x50>; | 168 | reg = <0x50>; |
| 145 | }; | 169 | }; |
| 146 | 170 | ||
| @@ -460,6 +484,8 @@ | |||
| 460 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ | 484 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ |
| 461 | clocks = <&emac0_clk>; | 485 | clocks = <&emac0_clk>; |
| 462 | clock-names = "stmmaceth"; | 486 | clock-names = "stmmaceth"; |
| 487 | resets = <&rst EMAC0_RESET>; | ||
| 488 | reset-names = "stmmaceth"; | ||
| 463 | status = "disabled"; | 489 | status = "disabled"; |
| 464 | }; | 490 | }; |
| 465 | 491 | ||
| @@ -472,9 +498,111 @@ | |||
| 472 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ | 498 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ |
| 473 | clocks = <&emac1_clk>; | 499 | clocks = <&emac1_clk>; |
| 474 | clock-names = "stmmaceth"; | 500 | clock-names = "stmmaceth"; |
| 501 | resets = <&rst EMAC1_RESET>; | ||
| 502 | reset-names = "stmmaceth"; | ||
| 503 | status = "disabled"; | ||
| 504 | }; | ||
| 505 | |||
| 506 | i2c0: i2c@ffc04000 { | ||
| 507 | #address-cells = <1>; | ||
| 508 | #size-cells = <0>; | ||
| 509 | compatible = "snps,designware-i2c"; | ||
| 510 | reg = <0xffc04000 0x1000>; | ||
| 511 | clocks = <&l4_sp_clk>; | ||
| 512 | interrupts = <0 158 0x4>; | ||
| 513 | status = "disabled"; | ||
| 514 | }; | ||
| 515 | |||
| 516 | i2c1: i2c@ffc05000 { | ||
| 517 | #address-cells = <1>; | ||
| 518 | #size-cells = <0>; | ||
| 519 | compatible = "snps,designware-i2c"; | ||
| 520 | reg = <0xffc05000 0x1000>; | ||
| 521 | clocks = <&l4_sp_clk>; | ||
| 522 | interrupts = <0 159 0x4>; | ||
| 475 | status = "disabled"; | 523 | status = "disabled"; |
| 476 | }; | 524 | }; |
| 477 | 525 | ||
| 526 | i2c2: i2c@ffc06000 { | ||
| 527 | #address-cells = <1>; | ||
| 528 | #size-cells = <0>; | ||
| 529 | compatible = "snps,designware-i2c"; | ||
| 530 | reg = <0xffc06000 0x1000>; | ||
| 531 | clocks = <&l4_sp_clk>; | ||
| 532 | interrupts = <0 160 0x4>; | ||
| 533 | status = "disabled"; | ||
| 534 | }; | ||
| 535 | |||
| 536 | i2c3: i2c@ffc07000 { | ||
| 537 | #address-cells = <1>; | ||
| 538 | #size-cells = <0>; | ||
| 539 | compatible = "snps,designware-i2c"; | ||
| 540 | reg = <0xffc07000 0x1000>; | ||
| 541 | clocks = <&l4_sp_clk>; | ||
| 542 | interrupts = <0 161 0x4>; | ||
| 543 | status = "disabled"; | ||
| 544 | }; | ||
| 545 | |||
| 546 | gpio@ff708000 { | ||
| 547 | #address-cells = <1>; | ||
| 548 | #size-cells = <0>; | ||
| 549 | compatible = "snps,dw-apb-gpio"; | ||
| 550 | reg = <0xff708000 0x1000>; | ||
| 551 | clocks = <&per_base_clk>; | ||
| 552 | status = "disabled"; | ||
| 553 | |||
| 554 | gpio0: gpio-controller@0 { | ||
| 555 | compatible = "snps,dw-apb-gpio-port"; | ||
| 556 | gpio-controller; | ||
| 557 | #gpio-cells = <2>; | ||
| 558 | snps,nr-gpios = <29>; | ||
| 559 | reg = <0>; | ||
| 560 | interrupt-controller; | ||
| 561 | #interrupt-cells = <2>; | ||
| 562 | interrupts = <0 164 4>; | ||
| 563 | }; | ||
| 564 | }; | ||
| 565 | |||
| 566 | gpio@ff709000 { | ||
| 567 | #address-cells = <1>; | ||
| 568 | #size-cells = <0>; | ||
| 569 | compatible = "snps,dw-apb-gpio"; | ||
| 570 | reg = <0xff709000 0x1000>; | ||
| 571 | clocks = <&per_base_clk>; | ||
| 572 | status = "disabled"; | ||
| 573 | |||
| 574 | gpio1: gpio-controller@0 { | ||
| 575 | compatible = "snps,dw-apb-gpio-port"; | ||
| 576 | gpio-controller; | ||
| 577 | #gpio-cells = <2>; | ||
| 578 | snps,nr-gpios = <29>; | ||
| 579 | reg = <0>; | ||
| 580 | interrupt-controller; | ||
| 581 | #interrupt-cells = <2>; | ||
| 582 | interrupts = <0 165 4>; | ||
| 583 | }; | ||
| 584 | }; | ||
| 585 | |||
| 586 | gpio@ff70a000 { | ||
| 587 | #address-cells = <1>; | ||
| 588 | #size-cells = <0>; | ||
| 589 | compatible = "snps,dw-apb-gpio"; | ||
| 590 | reg = <0xff70a000 0x1000>; | ||
| 591 | clocks = <&per_base_clk>; | ||
| 592 | status = "disabled"; | ||
| 593 | |||
| 594 | gpio2: gpio-controller@0 { | ||
| 595 | compatible = "snps,dw-apb-gpio-port"; | ||
| 596 | gpio-controller; | ||
| 597 | #gpio-cells = <2>; | ||
| 598 | snps,nr-gpios = <27>; | ||
| 599 | reg = <0>; | ||
| 600 | interrupt-controller; | ||
| 601 | #interrupt-cells = <2>; | ||
| 602 | interrupts = <0 166 4>; | ||
| 603 | }; | ||
| 604 | }; | ||
| 605 | |||
| 478 | L2: l2-cache@fffef000 { | 606 | L2: l2-cache@fffef000 { |
| 479 | compatible = "arm,pl310-cache"; | 607 | compatible = "arm,pl310-cache"; |
| 480 | reg = <0xfffef000 0x1000>; | 608 | reg = <0xfffef000 0x1000>; |
| @@ -508,24 +636,32 @@ | |||
| 508 | compatible = "snps,dw-apb-timer"; | 636 | compatible = "snps,dw-apb-timer"; |
| 509 | interrupts = <0 167 4>; | 637 | interrupts = <0 167 4>; |
| 510 | reg = <0xffc08000 0x1000>; | 638 | reg = <0xffc08000 0x1000>; |
| 639 | clocks = <&l4_sp_clk>; | ||
| 640 | clock-names = "timer"; | ||
| 511 | }; | 641 | }; |
| 512 | 642 | ||
| 513 | timer1: timer1@ffc09000 { | 643 | timer1: timer1@ffc09000 { |
| 514 | compatible = "snps,dw-apb-timer"; | 644 | compatible = "snps,dw-apb-timer"; |
| 515 | interrupts = <0 168 4>; | 645 | interrupts = <0 168 4>; |
| 516 | reg = <0xffc09000 0x1000>; | 646 | reg = <0xffc09000 0x1000>; |
| 647 | clocks = <&l4_sp_clk>; | ||
| 648 | clock-names = "timer"; | ||
| 517 | }; | 649 | }; |
| 518 | 650 | ||
| 519 | timer2: timer2@ffd00000 { | 651 | timer2: timer2@ffd00000 { |
| 520 | compatible = "snps,dw-apb-timer"; | 652 | compatible = "snps,dw-apb-timer"; |
| 521 | interrupts = <0 169 4>; | 653 | interrupts = <0 169 4>; |
| 522 | reg = <0xffd00000 0x1000>; | 654 | reg = <0xffd00000 0x1000>; |
| 655 | clocks = <&osc1>; | ||
| 656 | clock-names = "timer"; | ||
| 523 | }; | 657 | }; |
| 524 | 658 | ||
| 525 | timer3: timer3@ffd01000 { | 659 | timer3: timer3@ffd01000 { |
| 526 | compatible = "snps,dw-apb-timer"; | 660 | compatible = "snps,dw-apb-timer"; |
| 527 | interrupts = <0 170 4>; | 661 | interrupts = <0 170 4>; |
| 528 | reg = <0xffd01000 0x1000>; | 662 | reg = <0xffd01000 0x1000>; |
| 663 | clocks = <&osc1>; | ||
| 664 | clock-names = "timer"; | ||
| 529 | }; | 665 | }; |
| 530 | 666 | ||
| 531 | uart0: serial0@ffc02000 { | 667 | uart0: serial0@ffc02000 { |
| @@ -534,6 +670,7 @@ | |||
| 534 | interrupts = <0 162 4>; | 670 | interrupts = <0 162 4>; |
| 535 | reg-shift = <2>; | 671 | reg-shift = <2>; |
| 536 | reg-io-width = <4>; | 672 | reg-io-width = <4>; |
| 673 | clocks = <&l4_sp_clk>; | ||
| 537 | }; | 674 | }; |
| 538 | 675 | ||
| 539 | uart1: serial1@ffc03000 { | 676 | uart1: serial1@ffc03000 { |
| @@ -542,13 +679,58 @@ | |||
| 542 | interrupts = <0 163 4>; | 679 | interrupts = <0 163 4>; |
| 543 | reg-shift = <2>; | 680 | reg-shift = <2>; |
| 544 | reg-io-width = <4>; | 681 | reg-io-width = <4>; |
| 682 | clocks = <&l4_sp_clk>; | ||
| 545 | }; | 683 | }; |
| 546 | 684 | ||
| 547 | rstmgr@ffd05000 { | 685 | rst: rstmgr@ffd05000 { |
| 548 | compatible = "altr,rst-mgr"; | 686 | compatible = "altr,rst-mgr"; |
| 549 | reg = <0xffd05000 0x1000>; | 687 | reg = <0xffd05000 0x1000>; |
| 550 | }; | 688 | }; |
| 551 | 689 | ||
| 690 | usbphy0: usbphy@0 { | ||
| 691 | #phy-cells = <0>; | ||
| 692 | compatible = "usb-nop-xceiv"; | ||
| 693 | status = "okay"; | ||
| 694 | }; | ||
| 695 | |||
| 696 | usb0: usb@ffb00000 { | ||
| 697 | compatible = "snps,dwc2"; | ||
| 698 | reg = <0xffb00000 0xffff>; | ||
| 699 | interrupts = <0 125 4>; | ||
| 700 | clocks = <&usb_mp_clk>; | ||
| 701 | clock-names = "otg"; | ||
| 702 | phys = <&usbphy0>; | ||
| 703 | phy-names = "usb2-phy"; | ||
| 704 | status = "disabled"; | ||
| 705 | }; | ||
| 706 | |||
| 707 | usb1: usb@ffb40000 { | ||
| 708 | compatible = "snps,dwc2"; | ||
| 709 | reg = <0xffb40000 0xffff>; | ||
| 710 | interrupts = <0 128 4>; | ||
| 711 | clocks = <&usb_mp_clk>; | ||
| 712 | clock-names = "otg"; | ||
| 713 | phys = <&usbphy0>; | ||
| 714 | phy-names = "usb2-phy"; | ||
| 715 | status = "disabled"; | ||
| 716 | }; | ||
| 717 | |||
| 718 | watchdog0: watchdog@ffd02000 { | ||
| 719 | compatible = "snps,dw-wdt"; | ||
| 720 | reg = <0xffd02000 0x1000>; | ||
| 721 | interrupts = <0 171 4>; | ||
| 722 | clocks = <&osc1>; | ||
| 723 | status = "disabled"; | ||
| 724 | }; | ||
| 725 | |||
| 726 | watchdog1: watchdog@ffd03000 { | ||
| 727 | compatible = "snps,dw-wdt"; | ||
| 728 | reg = <0xffd03000 0x1000>; | ||
| 729 | interrupts = <0 172 4>; | ||
| 730 | clocks = <&osc1>; | ||
| 731 | status = "disabled"; | ||
| 732 | }; | ||
| 733 | |||
| 552 | sysmgr: sysmgr@ffd08000 { | 734 | sysmgr: sysmgr@ffd08000 { |
| 553 | compatible = "altr,sys-mgr", "syscon"; | 735 | compatible = "altr,sys-mgr", "syscon"; |
| 554 | reg = <0xffd08000 0x4000>; | 736 | reg = <0xffd08000 0x4000>; |
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index 6c87b7070ca7..12d1c2ccaf5b 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi | |||
| @@ -15,7 +15,7 @@ | |||
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | /dts-v1/; | 17 | /dts-v1/; |
| 18 | /include/ "socfpga.dtsi" | 18 | #include "socfpga.dtsi" |
| 19 | 19 | ||
| 20 | / { | 20 | / { |
| 21 | soc { | 21 | soc { |
| @@ -38,32 +38,8 @@ | |||
| 38 | }; | 38 | }; |
| 39 | }; | 39 | }; |
| 40 | 40 | ||
| 41 | serial0@ffc02000 { | ||
| 42 | clock-frequency = <100000000>; | ||
| 43 | }; | ||
| 44 | |||
| 45 | serial1@ffc03000 { | ||
| 46 | clock-frequency = <100000000>; | ||
| 47 | }; | ||
| 48 | |||
| 49 | sysmgr@ffd08000 { | 41 | sysmgr@ffd08000 { |
| 50 | cpu1-start-addr = <0xffd080c4>; | 42 | cpu1-start-addr = <0xffd080c4>; |
| 51 | }; | 43 | }; |
| 52 | |||
| 53 | timer0@ffc08000 { | ||
| 54 | clock-frequency = <100000000>; | ||
| 55 | }; | ||
| 56 | |||
| 57 | timer1@ffc09000 { | ||
| 58 | clock-frequency = <100000000>; | ||
| 59 | }; | ||
| 60 | |||
| 61 | timer2@ffd00000 { | ||
| 62 | clock-frequency = <25000000>; | ||
| 63 | }; | ||
| 64 | |||
| 65 | timer3@ffd01000 { | ||
| 66 | clock-frequency = <25000000>; | ||
| 67 | }; | ||
| 68 | }; | 44 | }; |
| 69 | }; | 45 | }; |
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index a87ee1c07661..d532d171e391 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts | |||
| @@ -15,7 +15,7 @@ | |||
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ | 16 | */ |
| 17 | 17 | ||
| 18 | /include/ "socfpga_arria5.dtsi" | 18 | #include "socfpga_arria5.dtsi" |
| 19 | 19 | ||
| 20 | / { | 20 | / { |
| 21 | model = "Altera SOCFPGA Arria V SoC Development Kit"; | 21 | model = "Altera SOCFPGA Arria V SoC Development Kit"; |
| @@ -59,3 +59,22 @@ | |||
| 59 | rxdv-skew-ps = <0>; | 59 | rxdv-skew-ps = <0>; |
| 60 | rxc-skew-ps = <2000>; | 60 | rxc-skew-ps = <2000>; |
| 61 | }; | 61 | }; |
| 62 | |||
| 63 | &i2c0 { | ||
| 64 | status = "okay"; | ||
| 65 | |||
| 66 | eeprom@51 { | ||
| 67 | compatible = "atmel,24c32"; | ||
| 68 | reg = <0x51>; | ||
| 69 | pagesize = <32>; | ||
| 70 | }; | ||
| 71 | |||
| 72 | rtc@68 { | ||
| 73 | compatible = "dallas,ds1339"; | ||
| 74 | reg = <0x68>; | ||
| 75 | }; | ||
| 76 | }; | ||
| 77 | |||
| 78 | &usb1 { | ||
| 79 | status = "okay"; | ||
| 80 | }; | ||
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index ca41b0ebf461..bf511828729f 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi | |||
| @@ -16,7 +16,7 @@ | |||
| 16 | */ | 16 | */ |
| 17 | 17 | ||
| 18 | /dts-v1/; | 18 | /dts-v1/; |
| 19 | /include/ "socfpga.dtsi" | 19 | #include "socfpga.dtsi" |
| 20 | 20 | ||
| 21 | / { | 21 | / { |
| 22 | soc { | 22 | soc { |
| @@ -45,30 +45,6 @@ | |||
| 45 | status = "okay"; | 45 | status = "okay"; |
| 46 | }; | 46 | }; |
| 47 | 47 | ||
| 48 | timer0@ffc08000 { | ||
| 49 | clock-frequency = <100000000>; | ||
| 50 | }; | ||
| 51 | |||
| 52 | timer1@ffc09000 { | ||
| 53 | clock-frequency = <100000000>; | ||
| 54 | }; | ||
| 55 | |||
| 56 | timer2@ffd00000 { | ||
| 57 | clock-frequency = <25000000>; | ||
| 58 | }; | ||
| 59 | |||
| 60 | timer3@ffd01000 { | ||
| 61 | clock-frequency = <25000000>; | ||
| 62 | }; | ||
| 63 | |||
| 64 | serial0@ffc02000 { | ||
| 65 | clock-frequency = <100000000>; | ||
| 66 | }; | ||
| 67 | |||
| 68 | serial1@ffc03000 { | ||
| 69 | clock-frequency = <100000000>; | ||
| 70 | }; | ||
| 71 | |||
| 72 | sysmgr@ffd08000 { | 48 | sysmgr@ffd08000 { |
| 73 | cpu1-start-addr = <0xffd080c4>; | 49 | cpu1-start-addr = <0xffd080c4>; |
| 74 | }; | 50 | }; |
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index ae16d975196d..45de1514af0a 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | |||
| @@ -15,7 +15,7 @@ | |||
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ | 16 | */ |
| 17 | 17 | ||
| 18 | /include/ "socfpga_cyclone5.dtsi" | 18 | #include "socfpga_cyclone5.dtsi" |
| 19 | 19 | ||
| 20 | / { | 20 | / { |
| 21 | model = "Altera SOCFPGA Cyclone V SoC Development Kit"; | 21 | model = "Altera SOCFPGA Cyclone V SoC Development Kit"; |
| @@ -52,3 +52,22 @@ | |||
| 52 | rxdv-skew-ps = <0>; | 52 | rxdv-skew-ps = <0>; |
| 53 | rxc-skew-ps = <2000>; | 53 | rxc-skew-ps = <2000>; |
| 54 | }; | 54 | }; |
| 55 | |||
| 56 | &i2c0 { | ||
| 57 | status = "okay"; | ||
| 58 | |||
| 59 | eeprom@51 { | ||
| 60 | compatible = "atmel,24c32"; | ||
| 61 | reg = <0x51>; | ||
| 62 | pagesize = <32>; | ||
| 63 | }; | ||
| 64 | |||
| 65 | rtc@68 { | ||
| 66 | compatible = "dallas,ds1339"; | ||
| 67 | reg = <0x68>; | ||
| 68 | }; | ||
| 69 | }; | ||
| 70 | |||
| 71 | &usb1 { | ||
| 72 | status = "okay"; | ||
| 73 | }; | ||
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index b79e2a2bf175..d26f155f5fd9 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | |||
| @@ -15,7 +15,7 @@ | |||
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ | 16 | */ |
| 17 | 17 | ||
| 18 | /include/ "socfpga_cyclone5.dtsi" | 18 | #include "socfpga_cyclone5.dtsi" |
| 19 | 19 | ||
| 20 | / { | 20 | / { |
| 21 | model = "Terasic SoCkit"; | 21 | model = "Terasic SoCkit"; |
| @@ -52,3 +52,7 @@ | |||
| 52 | rxdv-skew-ps = <0>; | 52 | rxdv-skew-ps = <0>; |
| 53 | rxc-skew-ps = <2000>; | 53 | rxc-skew-ps = <2000>; |
| 54 | }; | 54 | }; |
| 55 | |||
| 56 | &usb1 { | ||
| 57 | status = "okay"; | ||
| 58 | }; | ||
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts new file mode 100644 index 000000000000..a1814b457450 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts | |||
| @@ -0,0 +1,50 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include "socfpga_cyclone5.dtsi" | ||
| 19 | |||
| 20 | / { | ||
| 21 | model = "EBV SOCrates"; | ||
| 22 | compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; | ||
| 23 | |||
| 24 | chosen { | ||
| 25 | bootargs = "console=ttyS0,115200"; | ||
| 26 | }; | ||
| 27 | |||
| 28 | memory { | ||
| 29 | name = "memory"; | ||
| 30 | device_type = "memory"; | ||
| 31 | reg = <0x0 0x40000000>; /* 1GB */ | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | |||
| 35 | &gmac1 { | ||
| 36 | status = "okay"; | ||
| 37 | }; | ||
| 38 | |||
| 39 | &i2c0 { | ||
| 40 | status = "okay"; | ||
| 41 | |||
| 42 | rtc: rtc@68 { | ||
| 43 | compatible = "stm,m41t82"; | ||
| 44 | reg = <0x68>; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | |||
| 48 | &mmc { | ||
| 49 | status = "okay"; | ||
| 50 | }; | ||
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index 87d6f759a9c1..09792b411110 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts | |||
| @@ -16,7 +16,7 @@ | |||
| 16 | */ | 16 | */ |
| 17 | 17 | ||
| 18 | /dts-v1/; | 18 | /dts-v1/; |
| 19 | /include/ "socfpga.dtsi" | 19 | #include "socfpga.dtsi" |
| 20 | 20 | ||
| 21 | / { | 21 | / { |
| 22 | model = "Altera SOCFPGA VT"; | 22 | model = "Altera SOCFPGA VT"; |
diff --git a/arch/arm/boot/dts/ste-ccu9540.dts b/arch/arm/boot/dts/ste-ccu9540.dts index 229508750890..651c56d400a4 100644 --- a/arch/arm/boot/dts/ste-ccu9540.dts +++ b/arch/arm/boot/dts/ste-ccu9540.dts | |||
| @@ -38,8 +38,8 @@ | |||
| 38 | arm,primecell-periphid = <0x10480180>; | 38 | arm,primecell-periphid = <0x10480180>; |
| 39 | max-frequency = <100000000>; | 39 | max-frequency = <100000000>; |
| 40 | bus-width = <4>; | 40 | bus-width = <4>; |
| 41 | mmc-cap-sd-highspeed; | 41 | cap-sd-highspeed; |
| 42 | mmc-cap-mmc-highspeed; | 42 | cap-mmc-highspeed; |
| 43 | vmmc-supply = <&ab8500_ldo_aux3_reg>; | 43 | vmmc-supply = <&ab8500_ldo_aux3_reg>; |
| 44 | 44 | ||
| 45 | cd-gpios = <&gpio7 6 0x4>; // 230 | 45 | cd-gpios = <&gpio7 6 0x4>; // 230 |
| @@ -63,7 +63,7 @@ | |||
| 63 | arm,primecell-periphid = <0x10480180>; | 63 | arm,primecell-periphid = <0x10480180>; |
| 64 | max-frequency = <100000000>; | 64 | max-frequency = <100000000>; |
| 65 | bus-width = <8>; | 65 | bus-width = <8>; |
| 66 | mmc-cap-mmc-highspeed; | 66 | cap-mmc-highspeed; |
| 67 | vmmc-supply = <&ab8500_ldo_aux2_reg>; | 67 | vmmc-supply = <&ab8500_ldo_aux2_reg>; |
| 68 | 68 | ||
| 69 | status = "okay"; | 69 | status = "okay"; |
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 6cb9b68e2188..bf8f0eddc2c0 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi | |||
| @@ -116,8 +116,15 @@ | |||
| 116 | arm,primecell-periphid = <0x10480180>; | 116 | arm,primecell-periphid = <0x10480180>; |
| 117 | max-frequency = <100000000>; | 117 | max-frequency = <100000000>; |
| 118 | bus-width = <4>; | 118 | bus-width = <4>; |
| 119 | mmc-cap-sd-highspeed; | 119 | cap-sd-highspeed; |
| 120 | mmc-cap-mmc-highspeed; | 120 | cap-mmc-highspeed; |
| 121 | sd-uhs-sdr12; | ||
| 122 | sd-uhs-sdr25; | ||
| 123 | full-pwr-cycle; | ||
| 124 | st,sig-dir-dat0; | ||
| 125 | st,sig-dir-dat2; | ||
| 126 | st,sig-dir-cmd; | ||
| 127 | st,sig-pin-fbclk; | ||
| 121 | vmmc-supply = <&ab8500_ldo_aux3_reg>; | 128 | vmmc-supply = <&ab8500_ldo_aux3_reg>; |
| 122 | vqmmc-supply = <&vmmci>; | 129 | vqmmc-supply = <&vmmci>; |
| 123 | pinctrl-names = "default", "sleep"; | 130 | pinctrl-names = "default", "sleep"; |
| @@ -132,6 +139,7 @@ | |||
| 132 | arm,primecell-periphid = <0x10480180>; | 139 | arm,primecell-periphid = <0x10480180>; |
| 133 | max-frequency = <100000000>; | 140 | max-frequency = <100000000>; |
| 134 | bus-width = <4>; | 141 | bus-width = <4>; |
| 142 | non-removable; | ||
| 135 | pinctrl-names = "default", "sleep"; | 143 | pinctrl-names = "default", "sleep"; |
| 136 | pinctrl-0 = <&sdi1_default_mode>; | 144 | pinctrl-0 = <&sdi1_default_mode>; |
| 137 | pinctrl-1 = <&sdi1_sleep_mode>; | 145 | pinctrl-1 = <&sdi1_sleep_mode>; |
| @@ -144,7 +152,9 @@ | |||
| 144 | arm,primecell-periphid = <0x10480180>; | 152 | arm,primecell-periphid = <0x10480180>; |
| 145 | max-frequency = <100000000>; | 153 | max-frequency = <100000000>; |
| 146 | bus-width = <8>; | 154 | bus-width = <8>; |
| 147 | mmc-cap-mmc-highspeed; | 155 | cap-mmc-highspeed; |
| 156 | non-removable; | ||
| 157 | vmmc-supply = <&db8500_vsmps2_reg>; | ||
| 148 | pinctrl-names = "default", "sleep"; | 158 | pinctrl-names = "default", "sleep"; |
| 149 | pinctrl-0 = <&sdi2_default_mode>; | 159 | pinctrl-0 = <&sdi2_default_mode>; |
| 150 | pinctrl-1 = <&sdi2_sleep_mode>; | 160 | pinctrl-1 = <&sdi2_sleep_mode>; |
| @@ -157,7 +167,8 @@ | |||
| 157 | arm,primecell-periphid = <0x10480180>; | 167 | arm,primecell-periphid = <0x10480180>; |
| 158 | max-frequency = <100000000>; | 168 | max-frequency = <100000000>; |
| 159 | bus-width = <8>; | 169 | bus-width = <8>; |
| 160 | mmc-cap-mmc-highspeed; | 170 | cap-mmc-highspeed; |
| 171 | non-removable; | ||
| 161 | vmmc-supply = <&ab8500_ldo_aux2_reg>; | 172 | vmmc-supply = <&ab8500_ldo_aux2_reg>; |
| 162 | pinctrl-names = "default", "sleep"; | 173 | pinctrl-names = "default", "sleep"; |
| 163 | pinctrl-0 = <&sdi4_default_mode>; | 174 | pinctrl-0 = <&sdi4_default_mode>; |
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index 5acc0449676a..d316c955bd5f 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | |||
| @@ -840,8 +840,8 @@ | |||
| 840 | interrupts = <22>; | 840 | interrupts = <22>; |
| 841 | max-frequency = <48000000>; | 841 | max-frequency = <48000000>; |
| 842 | bus-width = <4>; | 842 | bus-width = <4>; |
| 843 | mmc-cap-mmc-highspeed; | 843 | cap-mmc-highspeed; |
| 844 | mmc-cap-sd-highspeed; | 844 | cap-sd-highspeed; |
| 845 | cd-gpios = <&gpio3 15 0x1>; | 845 | cd-gpios = <&gpio3 15 0x1>; |
| 846 | cd-inverted; | 846 | cd-inverted; |
| 847 | pinctrl-names = "default"; | 847 | pinctrl-names = "default"; |
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index a2f632d0be2a..474ef83229cd 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts | |||
| @@ -156,7 +156,7 @@ | |||
| 156 | arm,primecell-periphid = <0x10480180>; | 156 | arm,primecell-periphid = <0x10480180>; |
| 157 | max-frequency = <100000000>; | 157 | max-frequency = <100000000>; |
| 158 | bus-width = <4>; | 158 | bus-width = <4>; |
| 159 | mmc-cap-mmc-highspeed; | 159 | cap-mmc-highspeed; |
| 160 | vmmc-supply = <&ab8500_ldo_aux3_reg>; | 160 | vmmc-supply = <&ab8500_ldo_aux3_reg>; |
| 161 | vqmmc-supply = <&vmmci>; | 161 | vqmmc-supply = <&vmmci>; |
| 162 | pinctrl-names = "default", "sleep"; | 162 | pinctrl-names = "default", "sleep"; |
| @@ -195,7 +195,7 @@ | |||
| 195 | arm,primecell-periphid = <0x10480180>; | 195 | arm,primecell-periphid = <0x10480180>; |
| 196 | max-frequency = <100000000>; | 196 | max-frequency = <100000000>; |
| 197 | bus-width = <8>; | 197 | bus-width = <8>; |
| 198 | mmc-cap-mmc-highspeed; | 198 | cap-mmc-highspeed; |
| 199 | vmmc-supply = <&ab8500_ldo_aux2_reg>; | 199 | vmmc-supply = <&ab8500_ldo_aux2_reg>; |
| 200 | pinctrl-names = "default", "sleep"; | 200 | pinctrl-names = "default", "sleep"; |
| 201 | pinctrl-0 = <&sdi4_default_mode>; | 201 | pinctrl-0 = <&sdi4_default_mode>; |
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts index 6fe688e9e4da..82a661677e97 100644 --- a/arch/arm/boot/dts/ste-u300.dts +++ b/arch/arm/boot/dts/ste-u300.dts | |||
| @@ -442,8 +442,8 @@ | |||
| 442 | clock-names = "apb_pclk", "mclk"; | 442 | clock-names = "apb_pclk", "mclk"; |
| 443 | max-frequency = <24000000>; | 443 | max-frequency = <24000000>; |
| 444 | bus-width = <4>; // SD-card slot | 444 | bus-width = <4>; // SD-card slot |
| 445 | mmc-cap-mmc-highspeed; | 445 | cap-mmc-highspeed; |
| 446 | mmc-cap-sd-highspeed; | 446 | cap-sd-highspeed; |
| 447 | cd-gpios = <&gpio 12 0x4>; | 447 | cd-gpios = <&gpio 12 0x4>; |
| 448 | cd-inverted; | 448 | cd-inverted; |
| 449 | vmmc-supply = <&ab3100_ldo_g_reg>; | 449 | vmmc-supply = <&ab3100_ldo_g_reg>; |
diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts new file mode 100644 index 000000000000..fe69f92e5f82 --- /dev/null +++ b/arch/arm/boot/dts/stih407-b2120.dts | |||
| @@ -0,0 +1,78 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 STMicroelectronics (R&D) Limited. | ||
| 3 | * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | /dts-v1/; | ||
| 10 | #include "stih407.dtsi" | ||
| 11 | / { | ||
| 12 | model = "STiH407 B2120"; | ||
| 13 | compatible = "st,stih407-b2120", "st,stih407"; | ||
| 14 | |||
| 15 | chosen { | ||
| 16 | bootargs = "console=ttyAS0,115200"; | ||
| 17 | linux,stdout-path = &sbc_serial0; | ||
| 18 | }; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | device_type = "memory"; | ||
| 22 | reg = <0x40000000 0x80000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | aliases { | ||
| 26 | ttyAS0 = &sbc_serial0; | ||
| 27 | }; | ||
| 28 | |||
| 29 | soc { | ||
| 30 | sbc_serial0: serial@9530000 { | ||
| 31 | status = "okay"; | ||
| 32 | }; | ||
| 33 | |||
| 34 | leds { | ||
| 35 | compatible = "gpio-leds"; | ||
| 36 | red { | ||
| 37 | #gpio-cells = <2>; | ||
| 38 | label = "Front Panel LED"; | ||
| 39 | gpios = <&pio4 1 0>; | ||
| 40 | linux,default-trigger = "heartbeat"; | ||
| 41 | }; | ||
| 42 | green { | ||
| 43 | #gpio-cells = <2>; | ||
| 44 | gpios = <&pio1 3 0>; | ||
| 45 | default-state = "off"; | ||
| 46 | }; | ||
| 47 | }; | ||
| 48 | |||
| 49 | i2c@9842000 { | ||
| 50 | status = "okay"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | i2c@9843000 { | ||
| 54 | status = "okay"; | ||
| 55 | }; | ||
| 56 | |||
| 57 | i2c@9844000 { | ||
| 58 | status = "okay"; | ||
| 59 | }; | ||
| 60 | |||
| 61 | i2c@9845000 { | ||
| 62 | status = "okay"; | ||
| 63 | }; | ||
| 64 | |||
| 65 | i2c@9540000 { | ||
| 66 | status = "okay"; | ||
| 67 | }; | ||
| 68 | |||
| 69 | /* SSC11 to HDMI */ | ||
| 70 | i2c@9541000 { | ||
| 71 | status = "okay"; | ||
| 72 | /* HDMI V1.3a supports Standard mode only */ | ||
| 73 | clock-frequency = <100000>; | ||
| 74 | st,i2c-min-scl-pulse-width-us = <0>; | ||
| 75 | st,i2c-min-sda-pulse-width-us = <5>; | ||
| 76 | }; | ||
| 77 | }; | ||
| 78 | }; | ||
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi new file mode 100644 index 000000000000..800f46f009f3 --- /dev/null +++ b/arch/arm/boot/dts/stih407-clock.dtsi | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 STMicroelectronics R&D Limited | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | / { | ||
| 9 | clocks { | ||
| 10 | /* | ||
| 11 | * Fixed 30MHz oscillator inputs to SoC | ||
| 12 | */ | ||
| 13 | clk_sysin: clk-sysin { | ||
| 14 | #clock-cells = <0>; | ||
| 15 | compatible = "fixed-clock"; | ||
| 16 | clock-frequency = <30000000>; | ||
| 17 | }; | ||
| 18 | |||
| 19 | /* | ||
| 20 | * ARM Peripheral clock for timers | ||
| 21 | */ | ||
| 22 | arm_periph_clk: arm-periph-clk { | ||
| 23 | #clock-cells = <0>; | ||
| 24 | compatible = "fixed-clock"; | ||
| 25 | clock-frequency = <600000000>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Bootloader initialized system infrastructure clock for | ||
| 30 | * serial devices. | ||
| 31 | */ | ||
| 32 | clk_ext2f_a9: clockgen-c0@13 { | ||
| 33 | #clock-cells = <0>; | ||
| 34 | compatible = "fixed-clock"; | ||
| 35 | clock-frequency = <200000000>; | ||
| 36 | clock-output-names = "clk-s-icn-reg-0"; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | }; | ||
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi new file mode 100644 index 000000000000..402844cb3152 --- /dev/null +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi | |||
| @@ -0,0 +1,615 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 STMicroelectronics Limited. | ||
| 3 | * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * publishhed by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include "st-pincfg.h" | ||
| 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 11 | / { | ||
| 12 | |||
| 13 | aliases { | ||
| 14 | /* 0-5: PIO_SBC */ | ||
| 15 | gpio0 = &pio0; | ||
| 16 | gpio1 = &pio1; | ||
| 17 | gpio2 = &pio2; | ||
| 18 | gpio3 = &pio3; | ||
| 19 | gpio4 = &pio4; | ||
| 20 | gpio5 = &pio5; | ||
| 21 | /* 10-19: PIO_FRONT0 */ | ||
| 22 | gpio6 = &pio10; | ||
| 23 | gpio7 = &pio11; | ||
| 24 | gpio8 = &pio12; | ||
| 25 | gpio9 = &pio13; | ||
| 26 | gpio10 = &pio14; | ||
| 27 | gpio11 = &pio15; | ||
| 28 | gpio12 = &pio16; | ||
| 29 | gpio13 = &pio17; | ||
| 30 | gpio14 = &pio18; | ||
| 31 | gpio15 = &pio19; | ||
| 32 | /* 20: PIO_FRONT1 */ | ||
| 33 | gpio16 = &pio20; | ||
| 34 | /* 30-35: PIO_REAR */ | ||
| 35 | gpio17 = &pio30; | ||
| 36 | gpio18 = &pio31; | ||
| 37 | gpio19 = &pio32; | ||
| 38 | gpio20 = &pio33; | ||
| 39 | gpio21 = &pio34; | ||
| 40 | gpio22 = &pio35; | ||
| 41 | /* 40-42: PIO_FLASH */ | ||
| 42 | gpio23 = &pio40; | ||
| 43 | gpio24 = &pio41; | ||
| 44 | gpio25 = &pio42; | ||
| 45 | }; | ||
| 46 | |||
| 47 | soc { | ||
| 48 | pin-controller-sbc { | ||
| 49 | #address-cells = <1>; | ||
| 50 | #size-cells = <1>; | ||
| 51 | compatible = "st,stih407-sbc-pinctrl"; | ||
| 52 | st,syscfg = <&syscfg_sbc>; | ||
| 53 | reg = <0x0961f080 0x4>; | ||
| 54 | reg-names = "irqmux"; | ||
| 55 | interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>; | ||
| 56 | interrupts-names = "irqmux"; | ||
| 57 | ranges = <0 0x09610000 0x6000>; | ||
| 58 | |||
| 59 | pio0: gpio@09610000 { | ||
| 60 | gpio-controller; | ||
| 61 | #gpio-cells = <1>; | ||
| 62 | interrupt-controller; | ||
| 63 | #interrupt-cells = <2>; | ||
| 64 | reg = <0x0 0x100>; | ||
| 65 | st,bank-name = "PIO0"; | ||
| 66 | }; | ||
| 67 | pio1: gpio@09611000 { | ||
| 68 | gpio-controller; | ||
| 69 | #gpio-cells = <1>; | ||
| 70 | interrupt-controller; | ||
| 71 | #interrupt-cells = <2>; | ||
| 72 | reg = <0x1000 0x100>; | ||
| 73 | st,bank-name = "PIO1"; | ||
| 74 | }; | ||
| 75 | pio2: gpio@09612000 { | ||
| 76 | gpio-controller; | ||
| 77 | #gpio-cells = <1>; | ||
| 78 | interrupt-controller; | ||
| 79 | #interrupt-cells = <2>; | ||
| 80 | reg = <0x2000 0x100>; | ||
| 81 | st,bank-name = "PIO2"; | ||
| 82 | }; | ||
| 83 | pio3: gpio@09613000 { | ||
| 84 | gpio-controller; | ||
| 85 | #gpio-cells = <1>; | ||
| 86 | interrupt-controller; | ||
| 87 | #interrupt-cells = <2>; | ||
| 88 | reg = <0x3000 0x100>; | ||
| 89 | st,bank-name = "PIO3"; | ||
| 90 | }; | ||
| 91 | pio4: gpio@09614000 { | ||
| 92 | gpio-controller; | ||
| 93 | #gpio-cells = <1>; | ||
| 94 | interrupt-controller; | ||
| 95 | #interrupt-cells = <2>; | ||
| 96 | reg = <0x4000 0x100>; | ||
| 97 | st,bank-name = "PIO4"; | ||
| 98 | }; | ||
| 99 | |||
| 100 | pio5: gpio@09615000 { | ||
| 101 | gpio-controller; | ||
| 102 | #gpio-cells = <1>; | ||
| 103 | interrupt-controller; | ||
| 104 | #interrupt-cells = <2>; | ||
| 105 | reg = <0x5000 0x100>; | ||
| 106 | st,bank-name = "PIO5"; | ||
| 107 | }; | ||
| 108 | |||
| 109 | rc { | ||
| 110 | pinctrl_ir: ir0 { | ||
| 111 | st,pins { | ||
| 112 | ir = <&pio4 0 ALT2 IN>; | ||
| 113 | }; | ||
| 114 | }; | ||
| 115 | }; | ||
| 116 | |||
| 117 | /* SBC_ASC0 - UART10 */ | ||
| 118 | sbc_serial0 { | ||
| 119 | pinctrl_sbc_serial0: sbc_serial0-0 { | ||
| 120 | st,pins { | ||
| 121 | tx = <&pio3 4 ALT1 OUT>; | ||
| 122 | rx = <&pio3 5 ALT1 IN>; | ||
| 123 | }; | ||
| 124 | }; | ||
| 125 | }; | ||
| 126 | /* SBC_ASC1 - UART11 */ | ||
| 127 | sbc_serial1 { | ||
| 128 | pinctrl_sbc_serial1: sbc_serial1-0 { | ||
| 129 | st,pins { | ||
| 130 | tx = <&pio2 6 ALT3 OUT>; | ||
| 131 | rx = <&pio2 7 ALT3 IN>; | ||
| 132 | }; | ||
| 133 | }; | ||
| 134 | }; | ||
| 135 | |||
| 136 | i2c10 { | ||
| 137 | pinctrl_i2c10_default: i2c10-default { | ||
| 138 | st,pins { | ||
| 139 | sda = <&pio4 6 ALT1 BIDIR>; | ||
| 140 | scl = <&pio4 5 ALT1 BIDIR>; | ||
| 141 | }; | ||
| 142 | }; | ||
| 143 | }; | ||
| 144 | |||
| 145 | i2c11 { | ||
| 146 | pinctrl_i2c11_default: i2c11-default { | ||
| 147 | st,pins { | ||
| 148 | sda = <&pio5 1 ALT1 BIDIR>; | ||
| 149 | scl = <&pio5 0 ALT1 BIDIR>; | ||
| 150 | }; | ||
| 151 | }; | ||
| 152 | }; | ||
| 153 | |||
| 154 | keyscan { | ||
| 155 | pinctrl_keyscan: keyscan { | ||
| 156 | st,pins { | ||
| 157 | keyin0 = <&pio4 0 ALT6 IN>; | ||
| 158 | keyin1 = <&pio4 5 ALT4 IN>; | ||
| 159 | keyin2 = <&pio0 4 ALT2 IN>; | ||
| 160 | keyin3 = <&pio2 6 ALT2 IN>; | ||
| 161 | |||
| 162 | keyout0 = <&pio4 6 ALT4 OUT>; | ||
| 163 | keyout1 = <&pio1 7 ALT2 OUT>; | ||
| 164 | keyout2 = <&pio0 6 ALT2 OUT>; | ||
| 165 | keyout3 = <&pio2 7 ALT2 OUT>; | ||
| 166 | }; | ||
| 167 | }; | ||
| 168 | }; | ||
| 169 | |||
| 170 | gmac1 { | ||
| 171 | /* | ||
| 172 | * Almost all the boards based on STiH407 SoC have an embedded | ||
| 173 | * switch where the mdio/mdc have been used for managing the SMI | ||
| 174 | * iface via I2C. For this reason these lines can be allocated | ||
| 175 | * by using dedicated configuration (in case of there will be a | ||
| 176 | * standard PHY transceiver on-board). | ||
| 177 | */ | ||
| 178 | pinctrl_rgmii1: rgmii1-0 { | ||
| 179 | st,pins { | ||
| 180 | |||
| 181 | txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>; | ||
| 182 | txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>; | ||
| 183 | txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>; | ||
| 184 | txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>; | ||
| 185 | txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; | ||
| 186 | txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; | ||
| 187 | rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; | ||
| 188 | rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; | ||
| 189 | rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; | ||
| 190 | rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; | ||
| 191 | rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>; | ||
| 192 | rxclk = <&pio2 2 ALT1 IN NICLK 500 CLK_A>; | ||
| 193 | clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>; | ||
| 194 | phyclk = <&pio2 3 ALT4 OUT NICLK 1750 CLK_B>; | ||
| 195 | }; | ||
| 196 | }; | ||
| 197 | |||
| 198 | pinctrl_rgmii1_mdio: rgmii1-mdio { | ||
| 199 | st,pins { | ||
| 200 | mdio = <&pio1 0 ALT1 OUT BYPASS 0>; | ||
| 201 | mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; | ||
| 202 | mdint = <&pio1 3 ALT1 IN BYPASS 0>; | ||
| 203 | }; | ||
| 204 | }; | ||
| 205 | |||
| 206 | pinctrl_mii1: mii1 { | ||
| 207 | st,pins { | ||
| 208 | txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | ||
| 209 | txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | ||
| 210 | txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | ||
| 211 | txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | ||
| 212 | txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | ||
| 213 | txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | ||
| 214 | txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; | ||
| 215 | col = <&pio0 7 ALT1 IN BYPASS 1000>; | ||
| 216 | |||
| 217 | mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; | ||
| 218 | mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; | ||
| 219 | crs = <&pio1 2 ALT1 IN BYPASS 1000>; | ||
| 220 | mdint = <&pio1 3 ALT1 IN BYPASS 0>; | ||
| 221 | rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; | ||
| 222 | rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; | ||
| 223 | rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; | ||
| 224 | rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; | ||
| 225 | |||
| 226 | rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; | ||
| 227 | rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; | ||
| 228 | rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; | ||
| 229 | phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; | ||
| 230 | }; | ||
| 231 | }; | ||
| 232 | }; | ||
| 233 | |||
| 234 | pwm1 { | ||
| 235 | pinctrl_pwm1_chan0_default: pwm1-0-default { | ||
| 236 | st,pins { | ||
| 237 | pwm-out = <&pio3 0 ALT1 OUT>; | ||
| 238 | }; | ||
| 239 | }; | ||
| 240 | pinctrl_pwm1_chan1_default: pwm1-1-default { | ||
| 241 | st,pins { | ||
| 242 | pwm-out = <&pio4 4 ALT1 OUT>; | ||
| 243 | }; | ||
| 244 | }; | ||
| 245 | pinctrl_pwm1_chan2_default: pwm1-2-default { | ||
| 246 | st,pins { | ||
| 247 | pwm-out = <&pio4 6 ALT3 OUT>; | ||
| 248 | }; | ||
| 249 | }; | ||
| 250 | pinctrl_pwm1_chan3_default: pwm1-3-default { | ||
| 251 | st,pins { | ||
| 252 | pwm-out = <&pio4 7 ALT3 OUT>; | ||
| 253 | }; | ||
| 254 | }; | ||
| 255 | }; | ||
| 256 | }; | ||
| 257 | |||
| 258 | pin-controller-front0 { | ||
| 259 | #address-cells = <1>; | ||
| 260 | #size-cells = <1>; | ||
| 261 | compatible = "st,stih407-front-pinctrl"; | ||
| 262 | st,syscfg = <&syscfg_front>; | ||
| 263 | reg = <0x0920f080 0x4>; | ||
| 264 | reg-names = "irqmux"; | ||
| 265 | interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>; | ||
| 266 | interrupts-names = "irqmux"; | ||
| 267 | ranges = <0 0x09200000 0x10000>; | ||
| 268 | |||
| 269 | pio10: pio@09200000 { | ||
| 270 | gpio-controller; | ||
| 271 | #gpio-cells = <1>; | ||
| 272 | interrupt-controller; | ||
| 273 | #interrupt-cells = <2>; | ||
| 274 | reg = <0x0 0x100>; | ||
| 275 | st,bank-name = "PIO10"; | ||
| 276 | }; | ||
| 277 | pio11: pio@09201000 { | ||
| 278 | gpio-controller; | ||
| 279 | #gpio-cells = <1>; | ||
| 280 | interrupt-controller; | ||
| 281 | #interrupt-cells = <2>; | ||
| 282 | reg = <0x1000 0x100>; | ||
| 283 | st,bank-name = "PIO11"; | ||
| 284 | }; | ||
| 285 | pio12: pio@09202000 { | ||
| 286 | gpio-controller; | ||
| 287 | #gpio-cells = <1>; | ||
| 288 | interrupt-controller; | ||
| 289 | #interrupt-cells = <2>; | ||
| 290 | reg = <0x2000 0x100>; | ||
| 291 | st,bank-name = "PIO12"; | ||
| 292 | }; | ||
| 293 | pio13: pio@09203000 { | ||
| 294 | gpio-controller; | ||
| 295 | #gpio-cells = <1>; | ||
| 296 | interrupt-controller; | ||
| 297 | #interrupt-cells = <2>; | ||
| 298 | reg = <0x3000 0x100>; | ||
| 299 | st,bank-name = "PIO13"; | ||
| 300 | }; | ||
| 301 | pio14: pio@09204000 { | ||
| 302 | gpio-controller; | ||
| 303 | #gpio-cells = <1>; | ||
| 304 | interrupt-controller; | ||
| 305 | #interrupt-cells = <2>; | ||
| 306 | reg = <0x4000 0x100>; | ||
| 307 | st,bank-name = "PIO14"; | ||
| 308 | }; | ||
| 309 | pio15: pio@09205000 { | ||
| 310 | gpio-controller; | ||
| 311 | #gpio-cells = <1>; | ||
| 312 | interrupt-controller; | ||
| 313 | #interrupt-cells = <2>; | ||
| 314 | reg = <0x5000 0x100>; | ||
| 315 | st,bank-name = "PIO15"; | ||
| 316 | }; | ||
| 317 | pio16: pio@09206000 { | ||
| 318 | gpio-controller; | ||
| 319 | #gpio-cells = <1>; | ||
| 320 | interrupt-controller; | ||
| 321 | #interrupt-cells = <2>; | ||
| 322 | reg = <0x6000 0x100>; | ||
| 323 | st,bank-name = "PIO16"; | ||
| 324 | }; | ||
| 325 | pio17: pio@09207000 { | ||
| 326 | gpio-controller; | ||
| 327 | #gpio-cells = <1>; | ||
| 328 | interrupt-controller; | ||
| 329 | #interrupt-cells = <2>; | ||
| 330 | reg = <0x7000 0x100>; | ||
| 331 | st,bank-name = "PIO17"; | ||
| 332 | }; | ||
| 333 | pio18: pio@09208000 { | ||
| 334 | gpio-controller; | ||
| 335 | #gpio-cells = <1>; | ||
| 336 | interrupt-controller; | ||
| 337 | #interrupt-cells = <2>; | ||
| 338 | reg = <0x8000 0x100>; | ||
| 339 | st,bank-name = "PIO18"; | ||
| 340 | }; | ||
| 341 | pio19: pio@09209000 { | ||
| 342 | gpio-controller; | ||
| 343 | #gpio-cells = <1>; | ||
| 344 | interrupt-controller; | ||
| 345 | #interrupt-cells = <2>; | ||
| 346 | reg = <0x9000 0x100>; | ||
| 347 | st,bank-name = "PIO19"; | ||
| 348 | }; | ||
| 349 | |||
| 350 | /* Comms */ | ||
| 351 | serial0 { | ||
| 352 | pinctrl_serial0: serial0-0 { | ||
| 353 | st,pins { | ||
| 354 | tx = <&pio17 0 ALT1 OUT>; | ||
| 355 | rx = <&pio17 1 ALT1 IN>; | ||
| 356 | }; | ||
| 357 | }; | ||
| 358 | }; | ||
| 359 | |||
| 360 | serial1 { | ||
| 361 | pinctrl_serial1: serial1-0 { | ||
| 362 | st,pins { | ||
| 363 | tx = <&pio16 0 ALT1 OUT>; | ||
| 364 | rx = <&pio16 1 ALT1 IN>; | ||
| 365 | }; | ||
| 366 | }; | ||
| 367 | }; | ||
| 368 | |||
| 369 | serial2 { | ||
| 370 | pinctrl_serial2: serial2-0 { | ||
| 371 | st,pins { | ||
| 372 | tx = <&pio15 0 ALT1 OUT>; | ||
| 373 | rx = <&pio15 1 ALT1 IN>; | ||
| 374 | }; | ||
| 375 | }; | ||
| 376 | }; | ||
| 377 | |||
| 378 | mmc1 { | ||
| 379 | pinctrl_sd1: sd1-0 { | ||
| 380 | st,pins { | ||
| 381 | sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>; | ||
| 382 | sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>; | ||
| 383 | sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>; | ||
| 384 | sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>; | ||
| 385 | sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>; | ||
| 386 | sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>; | ||
| 387 | sd_led = <&pio16 6 ALT6 OUT>; | ||
| 388 | sd_pwren = <&pio16 7 ALT6 OUT>; | ||
| 389 | sd_cd = <&pio19 0 ALT6 IN>; | ||
| 390 | sd_wp = <&pio19 1 ALT6 IN>; | ||
| 391 | }; | ||
| 392 | }; | ||
| 393 | }; | ||
| 394 | |||
| 395 | |||
| 396 | i2c0 { | ||
| 397 | pinctrl_i2c0_default: i2c0-default { | ||
| 398 | st,pins { | ||
| 399 | sda = <&pio10 6 ALT2 BIDIR>; | ||
| 400 | scl = <&pio10 5 ALT2 BIDIR>; | ||
| 401 | }; | ||
| 402 | }; | ||
| 403 | }; | ||
| 404 | |||
| 405 | i2c1 { | ||
| 406 | pinctrl_i2c1_default: i2c1-default { | ||
| 407 | st,pins { | ||
| 408 | sda = <&pio11 1 ALT2 BIDIR>; | ||
| 409 | scl = <&pio11 0 ALT2 BIDIR>; | ||
| 410 | }; | ||
| 411 | }; | ||
| 412 | }; | ||
| 413 | |||
| 414 | i2c2 { | ||
| 415 | pinctrl_i2c2_default: i2c2-default { | ||
| 416 | st,pins { | ||
| 417 | sda = <&pio15 6 ALT2 BIDIR>; | ||
| 418 | scl = <&pio15 5 ALT2 BIDIR>; | ||
| 419 | }; | ||
| 420 | }; | ||
| 421 | }; | ||
| 422 | |||
| 423 | i2c3 { | ||
| 424 | pinctrl_i2c3_default: i2c3-default { | ||
| 425 | st,pins { | ||
| 426 | sda = <&pio18 6 ALT1 BIDIR>; | ||
| 427 | scl = <&pio18 5 ALT1 BIDIR>; | ||
| 428 | }; | ||
| 429 | }; | ||
| 430 | }; | ||
| 431 | |||
| 432 | spi0 { | ||
| 433 | pinctrl_spi0_default: spi0-default { | ||
| 434 | st,pins { | ||
| 435 | mtsr = <&pio12 6 ALT2 BIDIR>; | ||
| 436 | mrst = <&pio12 7 ALT2 BIDIR>; | ||
| 437 | scl = <&pio12 5 ALT2 BIDIR>; | ||
| 438 | }; | ||
| 439 | }; | ||
| 440 | }; | ||
| 441 | }; | ||
| 442 | |||
| 443 | pin-controller-front1 { | ||
| 444 | #address-cells = <1>; | ||
| 445 | #size-cells = <1>; | ||
| 446 | compatible = "st,stih407-front-pinctrl"; | ||
| 447 | st,syscfg = <&syscfg_front>; | ||
| 448 | reg = <0x0921f080 0x4>; | ||
| 449 | reg-names = "irqmux"; | ||
| 450 | interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>; | ||
| 451 | interrupts-names = "irqmux"; | ||
| 452 | ranges = <0 0x09210000 0x10000>; | ||
| 453 | |||
| 454 | pio20: pio@09210000 { | ||
| 455 | gpio-controller; | ||
| 456 | #gpio-cells = <1>; | ||
| 457 | interrupt-controller; | ||
| 458 | #interrupt-cells = <2>; | ||
| 459 | reg = <0x0 0x100>; | ||
| 460 | st,bank-name = "PIO20"; | ||
| 461 | }; | ||
| 462 | }; | ||
| 463 | |||
| 464 | pin-controller-rear { | ||
| 465 | #address-cells = <1>; | ||
| 466 | #size-cells = <1>; | ||
| 467 | compatible = "st,stih407-rear-pinctrl"; | ||
| 468 | st,syscfg = <&syscfg_rear>; | ||
| 469 | reg = <0x0922f080 0x4>; | ||
| 470 | reg-names = "irqmux"; | ||
| 471 | interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>; | ||
| 472 | interrupts-names = "irqmux"; | ||
| 473 | ranges = <0 0x09220000 0x6000>; | ||
| 474 | |||
| 475 | pio30: gpio@09220000 { | ||
| 476 | gpio-controller; | ||
| 477 | #gpio-cells = <1>; | ||
| 478 | interrupt-controller; | ||
| 479 | #interrupt-cells = <2>; | ||
| 480 | reg = <0x0 0x100>; | ||
| 481 | st,bank-name = "PIO30"; | ||
| 482 | }; | ||
| 483 | pio31: gpio@09221000 { | ||
| 484 | gpio-controller; | ||
| 485 | #gpio-cells = <1>; | ||
| 486 | interrupt-controller; | ||
| 487 | #interrupt-cells = <2>; | ||
| 488 | reg = <0x1000 0x100>; | ||
| 489 | st,bank-name = "PIO31"; | ||
| 490 | }; | ||
| 491 | pio32: gpio@09222000 { | ||
| 492 | gpio-controller; | ||
| 493 | #gpio-cells = <1>; | ||
| 494 | interrupt-controller; | ||
| 495 | #interrupt-cells = <2>; | ||
| 496 | reg = <0x2000 0x100>; | ||
| 497 | st,bank-name = "PIO32"; | ||
| 498 | }; | ||
| 499 | pio33: gpio@09223000 { | ||
| 500 | gpio-controller; | ||
| 501 | #gpio-cells = <1>; | ||
| 502 | interrupt-controller; | ||
| 503 | #interrupt-cells = <2>; | ||
| 504 | reg = <0x3000 0x100>; | ||
| 505 | st,bank-name = "PIO33"; | ||
| 506 | }; | ||
| 507 | pio34: gpio@09224000 { | ||
| 508 | gpio-controller; | ||
| 509 | #gpio-cells = <1>; | ||
| 510 | interrupt-controller; | ||
| 511 | #interrupt-cells = <2>; | ||
| 512 | reg = <0x4000 0x100>; | ||
| 513 | st,bank-name = "PIO34"; | ||
| 514 | }; | ||
| 515 | pio35: gpio@09225000 { | ||
| 516 | gpio-controller; | ||
| 517 | #gpio-cells = <1>; | ||
| 518 | interrupt-controller; | ||
| 519 | #interrupt-cells = <2>; | ||
| 520 | reg = <0x5000 0x100>; | ||
| 521 | st,bank-name = "PIO35"; | ||
| 522 | }; | ||
| 523 | |||
| 524 | i2c4 { | ||
| 525 | pinctrl_i2c4_default: i2c4-default { | ||
| 526 | st,pins { | ||
| 527 | sda = <&pio30 1 ALT1 BIDIR>; | ||
| 528 | scl = <&pio30 0 ALT1 BIDIR>; | ||
| 529 | }; | ||
| 530 | }; | ||
| 531 | }; | ||
| 532 | |||
| 533 | i2c5 { | ||
| 534 | pinctrl_i2c5_default: i2c5-default { | ||
| 535 | st,pins { | ||
| 536 | sda = <&pio34 4 ALT1 BIDIR>; | ||
| 537 | scl = <&pio34 3 ALT1 BIDIR>; | ||
| 538 | }; | ||
| 539 | }; | ||
| 540 | }; | ||
| 541 | |||
| 542 | usb3 { | ||
| 543 | pinctrl_usb3: usb3-2 { | ||
| 544 | st,pins { | ||
| 545 | usb-oc-detect = <&pio35 4 ALT1 IN>; | ||
| 546 | usb-pwr-enable = <&pio35 5 ALT1 OUT>; | ||
| 547 | usb-vbus-valid = <&pio35 6 ALT1 IN>; | ||
| 548 | }; | ||
| 549 | }; | ||
| 550 | }; | ||
| 551 | |||
| 552 | pwm0 { | ||
| 553 | pinctrl_pwm0_chan0_default: pwm0-0-default { | ||
| 554 | st,pins { | ||
| 555 | pwm-out = <&pio31 1 ALT1 OUT>; | ||
| 556 | }; | ||
| 557 | }; | ||
| 558 | }; | ||
| 559 | }; | ||
| 560 | |||
| 561 | pin-controller-flash { | ||
| 562 | #address-cells = <1>; | ||
| 563 | #size-cells = <1>; | ||
| 564 | compatible = "st,stih407-flash-pinctrl"; | ||
| 565 | st,syscfg = <&syscfg_flash>; | ||
| 566 | reg = <0x0923f080 0x4>; | ||
| 567 | reg-names = "irqmux"; | ||
| 568 | interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>; | ||
| 569 | interrupts-names = "irqmux"; | ||
| 570 | ranges = <0 0x09230000 0x3000>; | ||
| 571 | |||
| 572 | pio40: gpio@09230000 { | ||
| 573 | gpio-controller; | ||
| 574 | #gpio-cells = <1>; | ||
| 575 | interrupt-controller; | ||
| 576 | #interrupt-cells = <2>; | ||
| 577 | reg = <0 0x100>; | ||
| 578 | st,bank-name = "PIO40"; | ||
| 579 | }; | ||
| 580 | pio41: gpio@09231000 { | ||
| 581 | gpio-controller; | ||
| 582 | #gpio-cells = <1>; | ||
| 583 | interrupt-controller; | ||
| 584 | #interrupt-cells = <2>; | ||
| 585 | reg = <0x1000 0x100>; | ||
| 586 | st,bank-name = "PIO41"; | ||
| 587 | }; | ||
| 588 | pio42: gpio@09232000 { | ||
| 589 | gpio-controller; | ||
| 590 | #gpio-cells = <1>; | ||
| 591 | interrupt-controller; | ||
| 592 | #interrupt-cells = <2>; | ||
| 593 | reg = <0x2000 0x100>; | ||
| 594 | st,bank-name = "PIO42"; | ||
| 595 | }; | ||
| 596 | |||
| 597 | mmc0 { | ||
| 598 | pinctrl_mmc0: mmc0-0 { | ||
| 599 | st,pins { | ||
| 600 | emmc_clk = <&pio40 6 ALT1 BIDIR>; | ||
| 601 | emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>; | ||
| 602 | emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>; | ||
| 603 | emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>; | ||
| 604 | emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>; | ||
| 605 | emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>; | ||
| 606 | emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>; | ||
| 607 | emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>; | ||
| 608 | emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>; | ||
| 609 | emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>; | ||
| 610 | }; | ||
| 611 | }; | ||
| 612 | }; | ||
| 613 | }; | ||
| 614 | }; | ||
| 615 | }; | ||
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi new file mode 100644 index 000000000000..4f9024f19866 --- /dev/null +++ b/arch/arm/boot/dts/stih407.dtsi | |||
| @@ -0,0 +1,263 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 STMicroelectronics Limited. | ||
| 3 | * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * publishhed by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include "stih407-clock.dtsi" | ||
| 10 | #include "stih407-pinctrl.dtsi" | ||
| 11 | / { | ||
| 12 | #address-cells = <1>; | ||
| 13 | #size-cells = <1>; | ||
| 14 | |||
| 15 | cpus { | ||
| 16 | #address-cells = <1>; | ||
| 17 | #size-cells = <0>; | ||
| 18 | cpu@0 { | ||
| 19 | device_type = "cpu"; | ||
| 20 | compatible = "arm,cortex-a9"; | ||
| 21 | reg = <0>; | ||
| 22 | }; | ||
| 23 | cpu@1 { | ||
| 24 | device_type = "cpu"; | ||
| 25 | compatible = "arm,cortex-a9"; | ||
| 26 | reg = <1>; | ||
| 27 | }; | ||
| 28 | }; | ||
| 29 | |||
| 30 | intc: interrupt-controller@08761000 { | ||
| 31 | compatible = "arm,cortex-a9-gic"; | ||
| 32 | #interrupt-cells = <3>; | ||
| 33 | interrupt-controller; | ||
| 34 | reg = <0x08761000 0x1000>, <0x08760100 0x100>; | ||
| 35 | }; | ||
| 36 | |||
| 37 | scu@08760000 { | ||
| 38 | compatible = "arm,cortex-a9-scu"; | ||
| 39 | reg = <0x08760000 0x1000>; | ||
| 40 | }; | ||
| 41 | |||
| 42 | timer@08760200 { | ||
| 43 | interrupt-parent = <&intc>; | ||
| 44 | compatible = "arm,cortex-a9-global-timer"; | ||
| 45 | reg = <0x08760200 0x100>; | ||
| 46 | interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; | ||
| 47 | clocks = <&arm_periph_clk>; | ||
| 48 | }; | ||
| 49 | |||
| 50 | l2: cache-controller { | ||
| 51 | compatible = "arm,pl310-cache"; | ||
| 52 | reg = <0x08762000 0x1000>; | ||
| 53 | arm,data-latency = <3 3 3>; | ||
| 54 | arm,tag-latency = <2 2 2>; | ||
| 55 | cache-unified; | ||
| 56 | cache-level = <2>; | ||
| 57 | }; | ||
| 58 | |||
| 59 | soc { | ||
| 60 | #address-cells = <1>; | ||
| 61 | #size-cells = <1>; | ||
| 62 | interrupt-parent = <&intc>; | ||
| 63 | ranges; | ||
| 64 | compatible = "simple-bus"; | ||
| 65 | |||
| 66 | syscfg_sbc: sbc-syscfg@9620000 { | ||
| 67 | compatible = "st,stih407-sbc-syscfg", "syscon"; | ||
| 68 | reg = <0x9620000 0x1000>; | ||
| 69 | }; | ||
| 70 | |||
| 71 | syscfg_front: front-syscfg@9280000 { | ||
| 72 | compatible = "st,stih407-front-syscfg", "syscon"; | ||
| 73 | reg = <0x9280000 0x1000>; | ||
| 74 | }; | ||
| 75 | |||
| 76 | syscfg_rear: rear-syscfg@9290000 { | ||
| 77 | compatible = "st,stih407-rear-syscfg", "syscon"; | ||
| 78 | reg = <0x9290000 0x1000>; | ||
| 79 | }; | ||
| 80 | |||
| 81 | syscfg_flash: flash-syscfg@92a0000 { | ||
| 82 | compatible = "st,stih407-flash-syscfg", "syscon"; | ||
| 83 | reg = <0x92a0000 0x1000>; | ||
| 84 | }; | ||
| 85 | |||
| 86 | syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { | ||
| 87 | compatible = "st,stih407-sbc-reg-syscfg", "syscon"; | ||
| 88 | reg = <0x9600000 0x1000>; | ||
| 89 | }; | ||
| 90 | |||
| 91 | syscfg_core: core-syscfg@92b0000 { | ||
| 92 | compatible = "st,stih407-core-syscfg", "syscon"; | ||
| 93 | reg = <0x92b0000 0x1000>; | ||
| 94 | }; | ||
| 95 | |||
| 96 | syscfg_lpm: lpm-syscfg@94b5100 { | ||
| 97 | compatible = "st,stih407-lpm-syscfg", "syscon"; | ||
| 98 | reg = <0x94b5100 0x1000>; | ||
| 99 | }; | ||
| 100 | |||
| 101 | serial@9830000 { | ||
| 102 | compatible = "st,asc"; | ||
| 103 | reg = <0x9830000 0x2c>; | ||
| 104 | interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>; | ||
| 105 | pinctrl-names = "default"; | ||
| 106 | pinctrl-0 = <&pinctrl_serial0>; | ||
| 107 | clocks = <&clk_ext2f_a9>; | ||
| 108 | |||
| 109 | status = "disabled"; | ||
| 110 | }; | ||
| 111 | |||
| 112 | serial@9831000 { | ||
| 113 | compatible = "st,asc"; | ||
| 114 | reg = <0x9831000 0x2c>; | ||
| 115 | interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>; | ||
| 116 | pinctrl-names = "default"; | ||
| 117 | pinctrl-0 = <&pinctrl_serial1>; | ||
| 118 | clocks = <&clk_ext2f_a9>; | ||
| 119 | |||
| 120 | status = "disabled"; | ||
| 121 | }; | ||
| 122 | |||
| 123 | serial@9832000 { | ||
| 124 | compatible = "st,asc"; | ||
| 125 | reg = <0x9832000 0x2c>; | ||
| 126 | interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; | ||
| 127 | pinctrl-names = "default"; | ||
| 128 | pinctrl-0 = <&pinctrl_serial2>; | ||
| 129 | clocks = <&clk_ext2f_a9>; | ||
| 130 | |||
| 131 | status = "disabled"; | ||
| 132 | }; | ||
| 133 | |||
| 134 | /* SBC_ASC0 - UART10 */ | ||
| 135 | sbc_serial0: serial@9530000 { | ||
| 136 | compatible = "st,asc"; | ||
| 137 | reg = <0x9530000 0x2c>; | ||
| 138 | interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>; | ||
| 139 | pinctrl-names = "default"; | ||
| 140 | pinctrl-0 = <&pinctrl_sbc_serial0>; | ||
| 141 | clocks = <&clk_sysin>; | ||
| 142 | |||
| 143 | status = "disabled"; | ||
| 144 | }; | ||
| 145 | |||
| 146 | serial@9531000 { | ||
| 147 | compatible = "st,asc"; | ||
| 148 | reg = <0x9531000 0x2c>; | ||
| 149 | interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>; | ||
| 150 | pinctrl-names = "default"; | ||
| 151 | pinctrl-0 = <&pinctrl_sbc_serial1>; | ||
| 152 | clocks = <&clk_sysin>; | ||
| 153 | |||
| 154 | status = "disabled"; | ||
| 155 | }; | ||
| 156 | |||
| 157 | i2c@9840000 { | ||
| 158 | compatible = "st,comms-ssc4-i2c"; | ||
| 159 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | ||
| 160 | reg = <0x9840000 0x110>; | ||
| 161 | clocks = <&clk_ext2f_a9>; | ||
| 162 | clock-names = "ssc"; | ||
| 163 | clock-frequency = <400000>; | ||
| 164 | pinctrl-names = "default"; | ||
| 165 | pinctrl-0 = <&pinctrl_i2c0_default>; | ||
| 166 | |||
| 167 | status = "disabled"; | ||
| 168 | }; | ||
| 169 | |||
| 170 | i2c@9841000 { | ||
| 171 | compatible = "st,comms-ssc4-i2c"; | ||
| 172 | reg = <0x9841000 0x110>; | ||
| 173 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | ||
| 174 | clocks = <&clk_ext2f_a9>; | ||
| 175 | clock-names = "ssc"; | ||
| 176 | clock-frequency = <400000>; | ||
| 177 | pinctrl-names = "default"; | ||
| 178 | pinctrl-0 = <&pinctrl_i2c1_default>; | ||
| 179 | |||
| 180 | status = "disabled"; | ||
| 181 | }; | ||
| 182 | |||
| 183 | i2c@9842000 { | ||
| 184 | compatible = "st,comms-ssc4-i2c"; | ||
| 185 | reg = <0x9842000 0x110>; | ||
| 186 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | ||
| 187 | clocks = <&clk_ext2f_a9>; | ||
| 188 | clock-names = "ssc"; | ||
| 189 | clock-frequency = <400000>; | ||
| 190 | pinctrl-names = "default"; | ||
| 191 | pinctrl-0 = <&pinctrl_i2c2_default>; | ||
| 192 | |||
| 193 | status = "disabled"; | ||
| 194 | }; | ||
| 195 | |||
| 196 | i2c@9843000 { | ||
| 197 | compatible = "st,comms-ssc4-i2c"; | ||
| 198 | reg = <0x9843000 0x110>; | ||
| 199 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | ||
| 200 | clocks = <&clk_ext2f_a9>; | ||
| 201 | clock-names = "ssc"; | ||
| 202 | clock-frequency = <400000>; | ||
| 203 | pinctrl-names = "default"; | ||
| 204 | pinctrl-0 = <&pinctrl_i2c3_default>; | ||
| 205 | |||
| 206 | status = "disabled"; | ||
| 207 | }; | ||
| 208 | |||
| 209 | i2c@9844000 { | ||
| 210 | compatible = "st,comms-ssc4-i2c"; | ||
| 211 | reg = <0x9844000 0x110>; | ||
| 212 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | ||
| 213 | clocks = <&clk_ext2f_a9>; | ||
| 214 | clock-names = "ssc"; | ||
| 215 | clock-frequency = <400000>; | ||
| 216 | pinctrl-names = "default"; | ||
| 217 | pinctrl-0 = <&pinctrl_i2c4_default>; | ||
| 218 | |||
| 219 | status = "disabled"; | ||
| 220 | }; | ||
| 221 | |||
| 222 | i2c@9845000 { | ||
| 223 | compatible = "st,comms-ssc4-i2c"; | ||
| 224 | reg = <0x9845000 0x110>; | ||
| 225 | interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; | ||
| 226 | clocks = <&clk_ext2f_a9>; | ||
| 227 | clock-names = "ssc"; | ||
| 228 | clock-frequency = <400000>; | ||
| 229 | pinctrl-names = "default"; | ||
| 230 | pinctrl-0 = <&pinctrl_i2c5_default>; | ||
| 231 | |||
| 232 | status = "disabled"; | ||
| 233 | }; | ||
| 234 | |||
| 235 | |||
| 236 | /* SSCs on SBC */ | ||
| 237 | i2c@9540000 { | ||
| 238 | compatible = "st,comms-ssc4-i2c"; | ||
| 239 | reg = <0x9540000 0x110>; | ||
| 240 | interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; | ||
| 241 | clocks = <&clk_sysin>; | ||
| 242 | clock-names = "ssc"; | ||
| 243 | clock-frequency = <400000>; | ||
| 244 | pinctrl-names = "default"; | ||
| 245 | pinctrl-0 = <&pinctrl_i2c10_default>; | ||
| 246 | |||
| 247 | status = "disabled"; | ||
| 248 | }; | ||
| 249 | |||
| 250 | i2c@9541000 { | ||
| 251 | compatible = "st,comms-ssc4-i2c"; | ||
| 252 | reg = <0x9541000 0x110>; | ||
| 253 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; | ||
| 254 | clocks = <&clk_sysin>; | ||
| 255 | clock-names = "ssc"; | ||
| 256 | clock-frequency = <400000>; | ||
| 257 | pinctrl-names = "default"; | ||
| 258 | pinctrl-0 = <&pinctrl_i2c11_default>; | ||
| 259 | |||
| 260 | status = "disabled"; | ||
| 261 | }; | ||
| 262 | }; | ||
| 263 | }; | ||
diff --git a/arch/arm/boot/dts/stih415-b2000.dts b/arch/arm/boot/dts/stih415-b2000.dts index d4af53160435..bdfbd3765db2 100644 --- a/arch/arm/boot/dts/stih415-b2000.dts +++ b/arch/arm/boot/dts/stih415-b2000.dts | |||
| @@ -11,5 +11,5 @@ | |||
| 11 | #include "stih41x-b2000.dtsi" | 11 | #include "stih41x-b2000.dtsi" |
| 12 | / { | 12 | / { |
| 13 | model = "STiH415 B2000 Board"; | 13 | model = "STiH415 B2000 Board"; |
| 14 | compatible = "st,stih415", "st,stih415-b2000"; | 14 | compatible = "st,stih415-b2000", "st,stih415"; |
| 15 | }; | 15 | }; |
diff --git a/arch/arm/boot/dts/stih415-b2020.dts b/arch/arm/boot/dts/stih415-b2020.dts index 442b019e9a3a..71903a87bd31 100644 --- a/arch/arm/boot/dts/stih415-b2020.dts +++ b/arch/arm/boot/dts/stih415-b2020.dts | |||
| @@ -11,5 +11,5 @@ | |||
| 11 | #include "stih41x-b2020.dtsi" | 11 | #include "stih41x-b2020.dtsi" |
| 12 | / { | 12 | / { |
| 13 | model = "STiH415 B2020 Board"; | 13 | model = "STiH415 B2020 Board"; |
| 14 | compatible = "st,stih415", "st,stih415-b2020"; | 14 | compatible = "st,stih415-b2020", "st,stih415"; |
| 15 | }; | 15 | }; |
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi index d047dbc28d61..3ee34514bc4b 100644 --- a/arch/arm/boot/dts/stih415-clock.dtsi +++ b/arch/arm/boot/dts/stih415-clock.dtsi | |||
| @@ -5,48 +5,529 @@ | |||
| 5 | * it under the terms of the GNU General Public License version 2 as | 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
| 7 | */ | 7 | */ |
| 8 | |||
| 9 | #include <dt-bindings/clock/stih415-clks.h> | ||
| 10 | |||
| 8 | / { | 11 | / { |
| 9 | clocks { | 12 | clocks { |
| 13 | #address-cells = <1>; | ||
| 14 | #size-cells = <1>; | ||
| 15 | ranges; | ||
| 16 | |||
| 10 | /* | 17 | /* |
| 11 | * Fixed 30MHz oscillator input to SoC | 18 | * Fixed 30MHz oscillator input to SoC |
| 12 | */ | 19 | */ |
| 13 | CLK_SYSIN: CLK_SYSIN { | 20 | clk_sysin: clk-sysin { |
| 14 | #clock-cells = <0>; | 21 | #clock-cells = <0>; |
| 15 | compatible = "fixed-clock"; | 22 | compatible = "fixed-clock"; |
| 16 | clock-frequency = <30000000>; | 23 | clock-frequency = <30000000>; |
| 17 | }; | 24 | }; |
| 18 | 25 | ||
| 19 | /* | 26 | /* |
| 20 | * ARM Peripheral clock for timers | 27 | * ClockGenAs on SASG1 |
| 21 | */ | 28 | */ |
| 22 | arm_periph_clk: arm_periph_clk { | 29 | clockgen-a@fee62000 { |
| 23 | #clock-cells = <0>; | 30 | reg = <0xfee62000 0xb48>; |
| 24 | compatible = "fixed-clock"; | 31 | |
| 25 | clock-frequency = <500000000>; | 32 | clk_s_a0_pll: clk-s-a0-pll { |
| 33 | #clock-cells = <1>; | ||
| 34 | compatible = "st,clkgena-plls-c65"; | ||
| 35 | |||
| 36 | clocks = <&clk_sysin>; | ||
| 37 | |||
| 38 | clock-output-names = "clk-s-a0-pll0-hs", | ||
| 39 | "clk-s-a0-pll0-ls", | ||
| 40 | "clk-s-a0-pll1"; | ||
| 41 | }; | ||
| 42 | |||
| 43 | clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { | ||
| 44 | #clock-cells = <0>; | ||
| 45 | compatible = "st,clkgena-prediv-c65", | ||
| 46 | "st,clkgena-prediv"; | ||
| 47 | |||
| 48 | clocks = <&clk_sysin>; | ||
| 49 | |||
| 50 | clock-output-names = "clk-s-a0-osc-prediv"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | clk_s_a0_hs: clk-s-a0-hs { | ||
| 54 | #clock-cells = <1>; | ||
| 55 | compatible = "st,clkgena-divmux-c65-hs", | ||
| 56 | "st,clkgena-divmux"; | ||
| 57 | |||
| 58 | clocks = <&clk_s_a0_osc_prediv>, | ||
| 59 | <&clk_s_a0_pll 0>, /* PLL0 HS */ | ||
| 60 | <&clk_s_a0_pll 2>; /* PLL1 */ | ||
| 61 | |||
| 62 | clock-output-names = "clk-s-fdma-0", | ||
| 63 | "clk-s-fdma-1", | ||
| 64 | ""; /* clk-s-jit-sense */ | ||
| 65 | /* Fourth output unused */ | ||
| 66 | }; | ||
| 67 | |||
| 68 | clk_s_a0_ls: clk-s-a0-ls { | ||
| 69 | #clock-cells = <1>; | ||
| 70 | compatible = "st,clkgena-divmux-c65-ls", | ||
| 71 | "st,clkgena-divmux"; | ||
| 72 | |||
| 73 | clocks = <&clk_s_a0_osc_prediv>, | ||
| 74 | <&clk_s_a0_pll 1>, /* PLL0 LS */ | ||
| 75 | <&clk_s_a0_pll 2>; /* PLL1 */ | ||
| 76 | |||
| 77 | clock-output-names = "clk-s-icn-reg-0", | ||
| 78 | "clk-s-icn-if-0", | ||
| 79 | "clk-s-icn-reg-lp-0", | ||
| 80 | "clk-s-emiss", | ||
| 81 | "clk-s-eth1-phy", | ||
| 82 | "clk-s-mii-ref-out"; | ||
| 83 | /* Remaining outputs unused */ | ||
| 84 | }; | ||
| 85 | }; | ||
| 86 | |||
| 87 | clockgen-a@fee81000 { | ||
| 88 | reg = <0xfee81000 0xb48>; | ||
| 89 | |||
| 90 | clk_s_a1_pll: clk-s-a1-pll { | ||
| 91 | #clock-cells = <1>; | ||
| 92 | compatible = "st,clkgena-plls-c65"; | ||
| 93 | |||
| 94 | clocks = <&clk_sysin>; | ||
| 95 | |||
| 96 | clock-output-names = "clk-s-a1-pll0-hs", | ||
| 97 | "clk-s-a1-pll0-ls", | ||
| 98 | "clk-s-a1-pll1"; | ||
| 99 | }; | ||
| 100 | |||
| 101 | clk_s_a1_osc_prediv: clk-s-a1-osc-prediv { | ||
| 102 | #clock-cells = <0>; | ||
| 103 | compatible = "st,clkgena-prediv-c65", | ||
| 104 | "st,clkgena-prediv"; | ||
| 105 | |||
| 106 | clocks = <&clk_sysin>; | ||
| 107 | |||
| 108 | clock-output-names = "clk-s-a1-osc-prediv"; | ||
| 109 | }; | ||
| 110 | |||
| 111 | clk_s_a1_hs: clk-s-a1-hs { | ||
| 112 | #clock-cells = <1>; | ||
| 113 | compatible = "st,clkgena-divmux-c65-hs", | ||
| 114 | "st,clkgena-divmux"; | ||
| 115 | |||
| 116 | clocks = <&clk_s_a1_osc_prediv>, | ||
| 117 | <&clk_s_a1_pll 0>, /* PLL0 HS */ | ||
| 118 | <&clk_s_a1_pll 2>; /* PLL1 */ | ||
| 119 | |||
| 120 | clock-output-names = "", /* Reserved */ | ||
| 121 | "", /* Reserved */ | ||
| 122 | "clk-s-stac-phy", | ||
| 123 | "clk-s-vtac-tx-phy"; | ||
| 124 | }; | ||
| 125 | |||
| 126 | clk_s_a1_ls: clk-s-a1-ls { | ||
| 127 | #clock-cells = <1>; | ||
| 128 | compatible = "st,clkgena-divmux-c65-ls", | ||
| 129 | "st,clkgena-divmux"; | ||
| 130 | |||
| 131 | clocks = <&clk_s_a1_osc_prediv>, | ||
| 132 | <&clk_s_a1_pll 1>, /* PLL0 LS */ | ||
| 133 | <&clk_s_a1_pll 2>; /* PLL1 */ | ||
| 134 | |||
| 135 | clock-output-names = "clk-s-icn-if-2", | ||
| 136 | "clk-s-card-mmc", | ||
| 137 | "clk-s-icn-if-1", | ||
| 138 | "clk-s-gmac0-phy", | ||
| 139 | "clk-s-nand-ctrl", | ||
| 140 | "", /* Reserved */ | ||
| 141 | "clk-s-mii0-ref-out", | ||
| 142 | ""; /* clk-s-stac-sys */ | ||
| 143 | /* Remaining outputs unused */ | ||
| 144 | }; | ||
| 26 | }; | 145 | }; |
| 27 | 146 | ||
| 28 | /* | 147 | /* |
| 29 | * Bootloader initialized system infrastructure clock for | 148 | * ClockGenAs on MPE41 |
| 30 | * serial devices. | ||
| 31 | */ | 149 | */ |
| 32 | CLKS_ICN_REG_0: CLKS_ICN_REG_0 { | 150 | clockgen-a@fde12000 { |
| 151 | reg = <0xfde12000 0xb50>; | ||
| 152 | |||
| 153 | clk_m_a0_pll0: clk-m-a0-pll0 { | ||
| 154 | #clock-cells = <1>; | ||
| 155 | compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; | ||
| 156 | |||
| 157 | clocks = <&clk_sysin>; | ||
| 158 | |||
| 159 | clock-output-names = "clk-m-a0-pll0-phi0", | ||
| 160 | "clk-m-a0-pll0-phi1", | ||
| 161 | "clk-m-a0-pll0-phi2", | ||
| 162 | "clk-m-a0-pll0-phi3"; | ||
| 163 | }; | ||
| 164 | |||
| 165 | clk_m_a0_pll1: clk-m-a0-pll1 { | ||
| 166 | #clock-cells = <1>; | ||
| 167 | compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; | ||
| 168 | |||
| 169 | clocks = <&clk_sysin>; | ||
| 170 | |||
| 171 | clock-output-names = "clk-m-a0-pll1-phi0", | ||
| 172 | "clk-m-a0-pll1-phi1", | ||
| 173 | "clk-m-a0-pll1-phi2", | ||
| 174 | "clk-m-a0-pll1-phi3"; | ||
| 175 | }; | ||
| 176 | |||
| 177 | clk_m_a0_osc_prediv: clk-m-a0-osc-prediv { | ||
| 178 | #clock-cells = <0>; | ||
| 179 | compatible = "st,clkgena-prediv-c32", | ||
| 180 | "st,clkgena-prediv"; | ||
| 181 | |||
| 182 | clocks = <&clk_sysin>; | ||
| 183 | |||
| 184 | clock-output-names = "clk-m-a0-osc-prediv"; | ||
| 185 | }; | ||
| 186 | |||
| 187 | clk_m_a0_div0: clk-m-a0-div0 { | ||
| 188 | #clock-cells = <1>; | ||
| 189 | compatible = "st,clkgena-divmux-c32-odf0", | ||
| 190 | "st,clkgena-divmux"; | ||
| 191 | |||
| 192 | clocks = <&clk_m_a0_osc_prediv>, | ||
| 193 | <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */ | ||
| 194 | <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */ | ||
| 195 | |||
| 196 | clock-output-names = "clk-m-apb-pm", /* Unused */ | ||
| 197 | "", /* Unused */ | ||
| 198 | "", /* Unused */ | ||
| 199 | "", /* Unused */ | ||
| 200 | "clk-m-pp-dmu-0", | ||
| 201 | "clk-m-pp-dmu-1", | ||
| 202 | "clk-m-icm-disp", | ||
| 203 | ""; /* Unused */ | ||
| 204 | }; | ||
| 205 | |||
| 206 | clk_m_a0_div1: clk-m-a0-div1 { | ||
| 207 | #clock-cells = <1>; | ||
| 208 | compatible = "st,clkgena-divmux-c32-odf1", | ||
| 209 | "st,clkgena-divmux"; | ||
| 210 | |||
| 211 | clocks = <&clk_m_a0_osc_prediv>, | ||
| 212 | <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */ | ||
| 213 | <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */ | ||
| 214 | |||
| 215 | clock-output-names = "", /* Unused */ | ||
| 216 | "", /* Unused */ | ||
| 217 | "clk-m-a9-ext2f", | ||
| 218 | "clk-m-st40rt", | ||
| 219 | "clk-m-st231-dmu-0", | ||
| 220 | "clk-m-st231-dmu-1", | ||
| 221 | "clk-m-st231-aud", | ||
| 222 | "clk-m-st231-gp-0"; | ||
| 223 | }; | ||
| 224 | |||
| 225 | clk_m_a0_div2: clk-m-a0-div2 { | ||
| 226 | #clock-cells = <1>; | ||
| 227 | compatible = "st,clkgena-divmux-c32-odf2", | ||
| 228 | "st,clkgena-divmux"; | ||
| 229 | |||
| 230 | clocks = <&clk_m_a0_osc_prediv>, | ||
| 231 | <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */ | ||
| 232 | <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */ | ||
| 233 | |||
| 234 | clock-output-names = "clk-m-st231-gp-1", | ||
| 235 | "clk-m-icn-cpu", | ||
| 236 | "clk-m-icn-stac", | ||
| 237 | "clk-m-icn-dmu-0", | ||
| 238 | "clk-m-icn-dmu-1", | ||
| 239 | "", /* Unused */ | ||
| 240 | "", /* Unused */ | ||
| 241 | ""; /* Unused */ | ||
| 242 | }; | ||
| 243 | |||
| 244 | clk_m_a0_div3: clk-m-a0-div3 { | ||
| 245 | #clock-cells = <1>; | ||
| 246 | compatible = "st,clkgena-divmux-c32-odf3", | ||
| 247 | "st,clkgena-divmux"; | ||
| 248 | |||
| 249 | clocks = <&clk_m_a0_osc_prediv>, | ||
| 250 | <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */ | ||
| 251 | <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */ | ||
| 252 | |||
| 253 | clock-output-names = "", /* Unused */ | ||
| 254 | "", /* Unused */ | ||
| 255 | "", /* Unused */ | ||
| 256 | "", /* Unused */ | ||
| 257 | "", /* Unused */ | ||
| 258 | "", /* Unused */ | ||
| 259 | "clk-m-icn-eram", | ||
| 260 | "clk-m-a9-trace"; | ||
| 261 | }; | ||
| 262 | }; | ||
| 263 | |||
| 264 | clockgen-a@fd6db000 { | ||
| 265 | reg = <0xfd6db000 0xb50>; | ||
| 266 | |||
| 267 | clk_m_a1_pll0: clk-m-a1-pll0 { | ||
| 268 | #clock-cells = <1>; | ||
| 269 | compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; | ||
| 270 | |||
| 271 | clocks = <&clk_sysin>; | ||
| 272 | |||
| 273 | clock-output-names = "clk-m-a1-pll0-phi0", | ||
| 274 | "clk-m-a1-pll0-phi1", | ||
| 275 | "clk-m-a1-pll0-phi2", | ||
| 276 | "clk-m-a1-pll0-phi3"; | ||
| 277 | }; | ||
| 278 | |||
| 279 | clk_m_a1_pll1: clk-m-a1-pll1 { | ||
| 280 | #clock-cells = <1>; | ||
| 281 | compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; | ||
| 282 | |||
| 283 | clocks = <&clk_sysin>; | ||
| 284 | |||
| 285 | clock-output-names = "clk-m-a1-pll1-phi0", | ||
| 286 | "clk-m-a1-pll1-phi1", | ||
| 287 | "clk-m-a1-pll1-phi2", | ||
| 288 | "clk-m-a1-pll1-phi3"; | ||
| 289 | }; | ||
| 290 | |||
| 291 | clk_m_a1_osc_prediv: clk-m-a1-osc-prediv { | ||
| 292 | #clock-cells = <0>; | ||
| 293 | compatible = "st,clkgena-prediv-c32", | ||
| 294 | "st,clkgena-prediv"; | ||
| 295 | |||
| 296 | clocks = <&clk_sysin>; | ||
| 297 | |||
| 298 | clock-output-names = "clk-m-a1-osc-prediv"; | ||
| 299 | }; | ||
| 300 | |||
| 301 | clk_m_a1_div0: clk-m-a1-div0 { | ||
| 302 | #clock-cells = <1>; | ||
| 303 | compatible = "st,clkgena-divmux-c32-odf0", | ||
| 304 | "st,clkgena-divmux"; | ||
| 305 | |||
| 306 | clocks = <&clk_m_a1_osc_prediv>, | ||
| 307 | <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */ | ||
| 308 | <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */ | ||
| 309 | |||
| 310 | clock-output-names = "clk-m-fdma-12", | ||
| 311 | "clk-m-fdma-10", | ||
| 312 | "clk-m-fdma-11", | ||
| 313 | "clk-m-hva-lmi", | ||
| 314 | "clk-m-proc-sc", | ||
| 315 | "clk-m-tp", | ||
| 316 | "clk-m-icn-gpu", | ||
| 317 | "clk-m-icn-vdp-0"; | ||
| 318 | }; | ||
| 319 | |||
| 320 | clk_m_a1_div1: clk-m-a1-div1 { | ||
| 321 | #clock-cells = <1>; | ||
| 322 | compatible = "st,clkgena-divmux-c32-odf1", | ||
| 323 | "st,clkgena-divmux"; | ||
| 324 | |||
| 325 | clocks = <&clk_m_a1_osc_prediv>, | ||
| 326 | <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */ | ||
| 327 | <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */ | ||
| 328 | |||
| 329 | clock-output-names = "clk-m-icn-vdp-1", | ||
| 330 | "clk-m-icn-vdp-2", | ||
| 331 | "clk-m-icn-vdp-3", | ||
| 332 | "clk-m-prv-t1-bus", | ||
| 333 | "clk-m-icn-vdp-4", | ||
| 334 | "clk-m-icn-reg-10", | ||
| 335 | "", /* Unused */ | ||
| 336 | ""; /* clk-m-icn-st231 */ | ||
| 337 | }; | ||
| 338 | |||
| 339 | clk_m_a1_div2: clk-m-a1-div2 { | ||
| 340 | #clock-cells = <1>; | ||
| 341 | compatible = "st,clkgena-divmux-c32-odf2", | ||
| 342 | "st,clkgena-divmux"; | ||
| 343 | |||
| 344 | clocks = <&clk_m_a1_osc_prediv>, | ||
| 345 | <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */ | ||
| 346 | <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */ | ||
| 347 | |||
| 348 | clock-output-names = "clk-m-fvdp-proc-alt", | ||
| 349 | "", /* Unused */ | ||
| 350 | "", /* Unused */ | ||
| 351 | "", /* Unused */ | ||
| 352 | "", /* Unused */ | ||
| 353 | "", /* Unused */ | ||
| 354 | "", /* Unused */ | ||
| 355 | ""; /* Unused */ | ||
| 356 | }; | ||
| 357 | |||
| 358 | clk_m_a1_div3: clk-m-a1-div3 { | ||
| 359 | #clock-cells = <1>; | ||
| 360 | compatible = "st,clkgena-divmux-c32-odf3", | ||
| 361 | "st,clkgena-divmux"; | ||
| 362 | |||
| 363 | clocks = <&clk_m_a1_osc_prediv>, | ||
| 364 | <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */ | ||
| 365 | <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */ | ||
| 366 | |||
| 367 | clock-output-names = "", /* Unused */ | ||
| 368 | "", /* Unused */ | ||
| 369 | "", /* Unused */ | ||
| 370 | "", /* Unused */ | ||
| 371 | "", /* Unused */ | ||
| 372 | "", /* Unused */ | ||
| 373 | "", /* Unused */ | ||
| 374 | ""; /* Unused */ | ||
| 375 | }; | ||
| 376 | }; | ||
| 377 | |||
| 378 | clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 { | ||
| 33 | #clock-cells = <0>; | 379 | #clock-cells = <0>; |
| 34 | compatible = "fixed-clock"; | 380 | compatible = "fixed-factor-clock"; |
| 35 | clock-frequency = <100000000>; | 381 | clocks = <&clk_m_a0_div1 2>; |
| 382 | clock-div = <2>; | ||
| 383 | clock-mult = <1>; | ||
| 36 | }; | 384 | }; |
| 37 | 385 | ||
| 38 | CLKS_GMAC0_PHY: clockgenA1@7 { | 386 | clockgen-a@fd345000 { |
| 387 | reg = <0xfd345000 0xb50>; | ||
| 388 | |||
| 389 | clk_m_a2_pll0: clk-m-a2-pll0 { | ||
| 390 | #clock-cells = <1>; | ||
| 391 | compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; | ||
| 392 | |||
| 393 | clocks = <&clk_sysin>; | ||
| 394 | |||
| 395 | clock-output-names = "clk-m-a2-pll0-phi0", | ||
| 396 | "clk-m-a2-pll0-phi1", | ||
| 397 | "clk-m-a2-pll0-phi2", | ||
| 398 | "clk-m-a2-pll0-phi3"; | ||
| 399 | }; | ||
| 400 | |||
| 401 | clk_m_a2_pll1: clk-m-a2-pll1 { | ||
| 402 | #clock-cells = <1>; | ||
| 403 | compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; | ||
| 404 | |||
| 405 | clocks = <&clk_sysin>; | ||
| 406 | |||
| 407 | clock-output-names = "clk-m-a2-pll1-phi0", | ||
| 408 | "clk-m-a2-pll1-phi1", | ||
| 409 | "clk-m-a2-pll1-phi2", | ||
| 410 | "clk-m-a2-pll1-phi3"; | ||
| 411 | }; | ||
| 412 | |||
| 413 | clk_m_a2_osc_prediv: clk-m-a2-osc-prediv { | ||
| 414 | #clock-cells = <0>; | ||
| 415 | compatible = "st,clkgena-prediv-c32", | ||
| 416 | "st,clkgena-prediv"; | ||
| 417 | |||
| 418 | clocks = <&clk_sysin>; | ||
| 419 | |||
| 420 | clock-output-names = "clk-m-a2-osc-prediv"; | ||
| 421 | }; | ||
| 422 | |||
| 423 | clk_m_a2_div0: clk-m-a2-div0 { | ||
| 424 | #clock-cells = <1>; | ||
| 425 | compatible = "st,clkgena-divmux-c32-odf0", | ||
| 426 | "st,clkgena-divmux"; | ||
| 427 | |||
| 428 | clocks = <&clk_m_a2_osc_prediv>, | ||
| 429 | <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */ | ||
| 430 | <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */ | ||
| 431 | |||
| 432 | clock-output-names = "clk-m-vtac-main-phy", | ||
| 433 | "clk-m-vtac-aux-phy", | ||
| 434 | "clk-m-stac-phy", | ||
| 435 | "clk-m-stac-sys", | ||
| 436 | "", /* clk-m-mpestac-pg */ | ||
| 437 | "", /* clk-m-mpestac-wc */ | ||
| 438 | "", /* clk-m-mpevtacaux-pg*/ | ||
| 439 | ""; /* clk-m-mpevtacmain-pg*/ | ||
| 440 | }; | ||
| 441 | |||
| 442 | clk_m_a2_div1: clk-m-a2-div1 { | ||
| 443 | #clock-cells = <1>; | ||
| 444 | compatible = "st,clkgena-divmux-c32-odf1", | ||
| 445 | "st,clkgena-divmux"; | ||
| 446 | |||
| 447 | clocks = <&clk_m_a2_osc_prediv>, | ||
| 448 | <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */ | ||
| 449 | <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */ | ||
| 450 | |||
| 451 | clock-output-names = "", /* clk-m-mpevtacrx0-wc */ | ||
| 452 | "", /* clk-m-mpevtacrx1-wc */ | ||
| 453 | "clk-m-compo-main", | ||
| 454 | "clk-m-compo-aux", | ||
| 455 | "clk-m-bdisp-0", | ||
| 456 | "clk-m-bdisp-1", | ||
| 457 | "clk-m-icn-bdisp-0", | ||
| 458 | "clk-m-icn-bdisp-1"; | ||
| 459 | }; | ||
| 460 | |||
| 461 | clk_m_a2_div2: clk-m-a2-div2 { | ||
| 462 | #clock-cells = <1>; | ||
| 463 | compatible = "st,clkgena-divmux-c32-odf2", | ||
| 464 | "st,clkgena-divmux"; | ||
| 465 | |||
| 466 | clocks = <&clk_m_a2_osc_prediv>, | ||
| 467 | <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */ | ||
| 468 | <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */ | ||
| 469 | |||
| 470 | clock-output-names = "", /* clk-m-icn-hqvdp0 */ | ||
| 471 | "", /* clk-m-icn-hqvdp1 */ | ||
| 472 | "clk-m-icn-compo", | ||
| 473 | "", /* clk-m-icn-vdpaux */ | ||
| 474 | "clk-m-icn-ts", | ||
| 475 | "clk-m-icn-reg-lp-10", | ||
| 476 | "clk-m-dcephy-impctrl", | ||
| 477 | ""; /* Unused */ | ||
| 478 | }; | ||
| 479 | |||
| 480 | clk_m_a2_div3: clk-m-a2-div3 { | ||
| 481 | #clock-cells = <1>; | ||
| 482 | compatible = "st,clkgena-divmux-c32-odf3", | ||
| 483 | "st,clkgena-divmux"; | ||
| 484 | |||
| 485 | clocks = <&clk_m_a2_osc_prediv>, | ||
| 486 | <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */ | ||
| 487 | <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */ | ||
| 488 | |||
| 489 | clock-output-names = ""; /* Unused */ | ||
| 490 | /* Remaining outputs unused */ | ||
| 491 | }; | ||
| 492 | }; | ||
| 493 | |||
| 494 | /* | ||
| 495 | * A9 PLL | ||
| 496 | */ | ||
| 497 | clockgen-a9@fdde00d8 { | ||
| 498 | reg = <0xfdde00d8 0x70>; | ||
| 499 | |||
| 500 | clockgen_a9_pll: clockgen-a9-pll { | ||
| 501 | #clock-cells = <1>; | ||
| 502 | compatible = "st,stih415-plls-c32-a9", "st,clkgen-plls-c32"; | ||
| 503 | |||
| 504 | clocks = <&clk_sysin>; | ||
| 505 | clock-output-names = "clockgen-a9-pll-odf"; | ||
| 506 | }; | ||
| 507 | }; | ||
| 508 | |||
| 509 | /* | ||
| 510 | * ARM CPU related clocks | ||
| 511 | */ | ||
| 512 | clk_m_a9: clk-m-a9@fdde00d8 { | ||
| 39 | #clock-cells = <0>; | 513 | #clock-cells = <0>; |
| 40 | compatible = "fixed-clock"; | 514 | compatible = "st,stih415-clkgen-a9-mux", "st,clkgen-mux"; |
| 41 | clock-frequency = <25000000>; | 515 | reg = <0xfdde00d8 0x4>; |
| 42 | clock-output-names = "CLKS_GMAC0_PHY"; | 516 | clocks = <&clockgen_a9_pll 0>, |
| 517 | <&clockgen_a9_pll 0>, | ||
| 518 | <&clk_m_a0_div1 2>, | ||
| 519 | <&clk_m_a9_ext2f_div2>; | ||
| 43 | }; | 520 | }; |
| 44 | 521 | ||
| 45 | CLKS_ETH1_PHY: clockgenA0@7 { | 522 | /* |
| 523 | * ARM Peripheral clock for timers | ||
| 524 | */ | ||
| 525 | arm_periph_clk: clk-m-a9-periphs { | ||
| 46 | #clock-cells = <0>; | 526 | #clock-cells = <0>; |
| 47 | compatible = "fixed-clock"; | 527 | compatible = "fixed-factor-clock"; |
| 48 | clock-frequency = <25000000>; | 528 | clocks = <&clk_m_a9>; |
| 49 | clock-output-names = "CLKS_ETH1_PHY"; | 529 | clock-div = <2>; |
| 530 | clock-mult = <1>; | ||
| 50 | }; | 531 | }; |
| 51 | }; | 532 | }; |
| 52 | }; | 533 | }; |
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi index 81df870e5ee6..8509a037ae21 100644 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi | |||
| @@ -102,6 +102,22 @@ | |||
| 102 | }; | 102 | }; |
| 103 | }; | 103 | }; |
| 104 | 104 | ||
| 105 | keyscan { | ||
| 106 | pinctrl_keyscan: keyscan { | ||
| 107 | st,pins { | ||
| 108 | keyin0 = <&PIO0 2 ALT2 IN>; | ||
| 109 | keyin1 = <&PIO0 3 ALT2 IN>; | ||
| 110 | keyin2 = <&PIO0 4 ALT2 IN>; | ||
| 111 | keyin3 = <&PIO2 6 ALT2 IN>; | ||
| 112 | |||
| 113 | keyout0 = <&PIO1 6 ALT2 OUT>; | ||
| 114 | keyout1 = <&PIO1 7 ALT2 OUT>; | ||
| 115 | keyout2 = <&PIO0 6 ALT2 OUT>; | ||
| 116 | keyout3 = <&PIO2 7 ALT2 OUT>; | ||
| 117 | }; | ||
| 118 | }; | ||
| 119 | }; | ||
| 120 | |||
| 105 | sbc_i2c0 { | 121 | sbc_i2c0 { |
| 106 | pinctrl_sbc_i2c0_default: sbc_i2c0-default { | 122 | pinctrl_sbc_i2c0_default: sbc_i2c0-default { |
| 107 | st,pins { | 123 | st,pins { |
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi index d89064c20c8a..d6f254f302fe 100644 --- a/arch/arm/boot/dts/stih415.dtsi +++ b/arch/arm/boot/dts/stih415.dtsi | |||
| @@ -82,7 +82,7 @@ | |||
| 82 | interrupts = <0 197 0>; | 82 | interrupts = <0 197 0>; |
| 83 | pinctrl-names = "default"; | 83 | pinctrl-names = "default"; |
| 84 | pinctrl-0 = <&pinctrl_serial2>; | 84 | pinctrl-0 = <&pinctrl_serial2>; |
| 85 | clocks = <&CLKS_ICN_REG_0>; | 85 | clocks = <&clk_s_a0_ls CLK_ICN_REG>; |
| 86 | }; | 86 | }; |
| 87 | 87 | ||
| 88 | /* SBC comms block ASCs in SASG1 */ | 88 | /* SBC comms block ASCs in SASG1 */ |
| @@ -91,7 +91,7 @@ | |||
| 91 | status = "disabled"; | 91 | status = "disabled"; |
| 92 | reg = <0xfe531000 0x2c>; | 92 | reg = <0xfe531000 0x2c>; |
| 93 | interrupts = <0 210 0>; | 93 | interrupts = <0 210 0>; |
| 94 | clocks = <&CLK_SYSIN>; | 94 | clocks = <&clk_sysin>; |
| 95 | pinctrl-names = "default"; | 95 | pinctrl-names = "default"; |
| 96 | pinctrl-0 = <&pinctrl_sbc_serial1>; | 96 | pinctrl-0 = <&pinctrl_sbc_serial1>; |
| 97 | }; | 97 | }; |
| @@ -100,7 +100,7 @@ | |||
| 100 | compatible = "st,comms-ssc4-i2c"; | 100 | compatible = "st,comms-ssc4-i2c"; |
| 101 | reg = <0xfed40000 0x110>; | 101 | reg = <0xfed40000 0x110>; |
| 102 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; | 102 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; |
| 103 | clocks = <&CLKS_ICN_REG_0>; | 103 | clocks = <&clk_s_a0_ls CLK_ICN_REG>; |
| 104 | clock-names = "ssc"; | 104 | clock-names = "ssc"; |
| 105 | clock-frequency = <400000>; | 105 | clock-frequency = <400000>; |
| 106 | pinctrl-names = "default"; | 106 | pinctrl-names = "default"; |
| @@ -113,7 +113,7 @@ | |||
| 113 | compatible = "st,comms-ssc4-i2c"; | 113 | compatible = "st,comms-ssc4-i2c"; |
| 114 | reg = <0xfed41000 0x110>; | 114 | reg = <0xfed41000 0x110>; |
| 115 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; | 115 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; |
| 116 | clocks = <&CLKS_ICN_REG_0>; | 116 | clocks = <&clk_s_a0_ls CLK_ICN_REG>; |
| 117 | clock-names = "ssc"; | 117 | clock-names = "ssc"; |
| 118 | clock-frequency = <400000>; | 118 | clock-frequency = <400000>; |
| 119 | pinctrl-names = "default"; | 119 | pinctrl-names = "default"; |
| @@ -126,7 +126,7 @@ | |||
| 126 | compatible = "st,comms-ssc4-i2c"; | 126 | compatible = "st,comms-ssc4-i2c"; |
| 127 | reg = <0xfe540000 0x110>; | 127 | reg = <0xfe540000 0x110>; |
| 128 | interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; | 128 | interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 129 | clocks = <&CLK_SYSIN>; | 129 | clocks = <&clk_sysin>; |
| 130 | clock-names = "ssc"; | 130 | clock-names = "ssc"; |
| 131 | clock-frequency = <400000>; | 131 | clock-frequency = <400000>; |
| 132 | pinctrl-names = "default"; | 132 | pinctrl-names = "default"; |
| @@ -139,7 +139,7 @@ | |||
| 139 | compatible = "st,comms-ssc4-i2c"; | 139 | compatible = "st,comms-ssc4-i2c"; |
| 140 | reg = <0xfe541000 0x110>; | 140 | reg = <0xfe541000 0x110>; |
| 141 | interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; | 141 | interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; |
| 142 | clocks = <&CLK_SYSIN>; | 142 | clocks = <&clk_sysin>; |
| 143 | clock-names = "ssc"; | 143 | clock-names = "ssc"; |
| 144 | clock-frequency = <400000>; | 144 | clock-frequency = <400000>; |
| 145 | pinctrl-names = "default"; | 145 | pinctrl-names = "default"; |
| @@ -170,7 +170,7 @@ | |||
| 170 | pinctrl-names = "default"; | 170 | pinctrl-names = "default"; |
| 171 | pinctrl-0 = <&pinctrl_mii0>; | 171 | pinctrl-0 = <&pinctrl_mii0>; |
| 172 | clock-names = "stmmaceth"; | 172 | clock-names = "stmmaceth"; |
| 173 | clocks = <&CLKS_GMAC0_PHY>; | 173 | clocks = <&clk_s_a1_ls CLK_GMAC0_PHY>; |
| 174 | }; | 174 | }; |
| 175 | 175 | ||
| 176 | ethernet1: dwmac@fef08000 { | 176 | ethernet1: dwmac@fef08000 { |
| @@ -193,18 +193,30 @@ | |||
| 193 | pinctrl-names = "default"; | 193 | pinctrl-names = "default"; |
| 194 | pinctrl-0 = <&pinctrl_mii1>; | 194 | pinctrl-0 = <&pinctrl_mii1>; |
| 195 | clock-names = "stmmaceth"; | 195 | clock-names = "stmmaceth"; |
| 196 | clocks = <&CLKS_ETH1_PHY>; | 196 | clocks = <&clk_s_a0_ls CLK_ETH1_PHY>; |
| 197 | }; | 197 | }; |
| 198 | 198 | ||
| 199 | rc: rc@fe518000 { | 199 | rc: rc@fe518000 { |
| 200 | compatible = "st,comms-irb"; | 200 | compatible = "st,comms-irb"; |
| 201 | reg = <0xfe518000 0x234>; | 201 | reg = <0xfe518000 0x234>; |
| 202 | interrupts = <0 203 0>; | 202 | interrupts = <0 203 0>; |
| 203 | clocks = <&CLK_SYSIN>; | 203 | clocks = <&clk_sysin>; |
| 204 | rx-mode = "infrared"; | 204 | rx-mode = "infrared"; |
| 205 | pinctrl-names = "default"; | 205 | pinctrl-names = "default"; |
| 206 | pinctrl-0 = <&pinctrl_ir>; | 206 | pinctrl-0 = <&pinctrl_ir>; |
| 207 | resets = <&softreset STIH415_IRB_SOFTRESET>; | 207 | resets = <&softreset STIH415_IRB_SOFTRESET>; |
| 208 | }; | 208 | }; |
| 209 | |||
| 210 | keyscan: keyscan@fe4b0000 { | ||
| 211 | compatible = "st,sti-keyscan"; | ||
| 212 | status = "disabled"; | ||
| 213 | reg = <0xfe4b0000 0x2000>; | ||
| 214 | interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>; | ||
| 215 | clocks = <&clk_sysin>; | ||
| 216 | pinctrl-names = "default"; | ||
| 217 | pinctrl-0 = <&pinctrl_keyscan>; | ||
| 218 | resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>, | ||
| 219 | <&softreset STIH415_KEYSCAN_SOFTRESET>; | ||
| 220 | }; | ||
| 209 | }; | 221 | }; |
| 210 | }; | 222 | }; |
diff --git a/arch/arm/boot/dts/stih416-b2000.dts b/arch/arm/boot/dts/stih416-b2000.dts index a5eb6eee10bf..488e80a5d69d 100644 --- a/arch/arm/boot/dts/stih416-b2000.dts +++ b/arch/arm/boot/dts/stih416-b2000.dts | |||
| @@ -9,8 +9,7 @@ | |||
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | #include "stih416.dtsi" | 10 | #include "stih416.dtsi" |
| 11 | #include "stih41x-b2000.dtsi" | 11 | #include "stih41x-b2000.dtsi" |
| 12 | |||
| 13 | / { | 12 | / { |
| 14 | compatible = "st,stih416", "st,stih416-b2000"; | ||
| 15 | model = "STiH416 B2000"; | 13 | model = "STiH416 B2000"; |
| 14 | compatible = "st,stih416-b2000", "st,stih416"; | ||
| 16 | }; | 15 | }; |
diff --git a/arch/arm/boot/dts/stih416-b2020-revE.dts b/arch/arm/boot/dts/stih416-b2020-revE.dts new file mode 100644 index 000000000000..ba0fa2caaf18 --- /dev/null +++ b/arch/arm/boot/dts/stih416-b2020-revE.dts | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 STMicroelectronics (R&D) Limited. | ||
| 3 | * Author: Lee Jones <lee.jones@linaro.org> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * publishhed by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | /dts-v1/; | ||
| 10 | #include "stih416.dtsi" | ||
| 11 | #include "stih41x-b2020.dtsi" | ||
| 12 | / { | ||
| 13 | model = "STiH416 B2020 REV-E"; | ||
| 14 | compatible = "st,stih416-b2020", "st,stih416"; | ||
| 15 | |||
| 16 | soc { | ||
| 17 | leds { | ||
| 18 | compatible = "gpio-leds"; | ||
| 19 | red { | ||
| 20 | #gpio-cells = <1>; | ||
| 21 | label = "Front Panel LED"; | ||
| 22 | gpios = <&PIO4 1>; | ||
| 23 | linux,default-trigger = "heartbeat"; | ||
| 24 | }; | ||
| 25 | green { | ||
| 26 | gpios = <&PIO1 3>; | ||
| 27 | default-state = "off"; | ||
| 28 | }; | ||
| 29 | }; | ||
| 30 | |||
| 31 | ethernet1: dwmac@fef08000 { | ||
| 32 | snps,reset-gpio = <&PIO0 7>; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | }; | ||
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts index 276f28da573a..4e2df66b99ea 100644 --- a/arch/arm/boot/dts/stih416-b2020.dts +++ b/arch/arm/boot/dts/stih416-b2020.dts | |||
| @@ -11,6 +11,5 @@ | |||
| 11 | #include "stih41x-b2020.dtsi" | 11 | #include "stih41x-b2020.dtsi" |
| 12 | / { | 12 | / { |
| 13 | model = "STiH416 B2020"; | 13 | model = "STiH416 B2020"; |
| 14 | compatible = "st,stih416", "st,stih416-b2020"; | 14 | compatible = "st,stih416-b2020", "st,stih416"; |
| 15 | |||
| 16 | }; | 15 | }; |
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi index a6942c75cbbb..5b4fb838cddb 100644 --- a/arch/arm/boot/dts/stih416-clock.dtsi +++ b/arch/arm/boot/dts/stih416-clock.dtsi | |||
| @@ -6,50 +6,751 @@ | |||
| 6 | * it under the terms of the GNU General Public License version 2 as | 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. | 7 | * published by the Free Software Foundation. |
| 8 | */ | 8 | */ |
| 9 | |||
| 10 | #include <dt-bindings/clock/stih416-clks.h> | ||
| 11 | |||
| 9 | / { | 12 | / { |
| 10 | clocks { | 13 | clocks { |
| 14 | #address-cells = <1>; | ||
| 15 | #size-cells = <1>; | ||
| 16 | ranges; | ||
| 17 | |||
| 11 | /* | 18 | /* |
| 12 | * Fixed 30MHz oscillator inputs to SoC | 19 | * Fixed 30MHz oscillator inputs to SoC |
| 13 | */ | 20 | */ |
| 14 | CLK_SYSIN: CLK_SYSIN { | 21 | clk_sysin: clk-sysin { |
| 15 | #clock-cells = <0>; | 22 | #clock-cells = <0>; |
| 16 | compatible = "fixed-clock"; | 23 | compatible = "fixed-clock"; |
| 17 | clock-frequency = <30000000>; | 24 | clock-frequency = <30000000>; |
| 18 | clock-output-names = "CLK_SYSIN"; | 25 | }; |
| 26 | |||
| 27 | /* | ||
| 28 | * ClockGenAs on SASG2 | ||
| 29 | */ | ||
| 30 | clockgen-a@fee62000 { | ||
| 31 | reg = <0xfee62000 0xb48>; | ||
| 32 | |||
| 33 | clk_s_a0_pll: clk-s-a0-pll { | ||
| 34 | #clock-cells = <1>; | ||
| 35 | compatible = "st,clkgena-plls-c65"; | ||
| 36 | |||
| 37 | clocks = <&clk_sysin>; | ||
| 38 | |||
| 39 | clock-output-names = "clk-s-a0-pll0-hs", | ||
| 40 | "clk-s-a0-pll0-ls", | ||
| 41 | "clk-s-a0-pll1"; | ||
| 42 | }; | ||
| 43 | |||
| 44 | clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { | ||
| 45 | #clock-cells = <0>; | ||
| 46 | compatible = "st,clkgena-prediv-c65", | ||
| 47 | "st,clkgena-prediv"; | ||
| 48 | |||
| 49 | clocks = <&clk_sysin>; | ||
| 50 | |||
| 51 | clock-output-names = "clk-s-a0-osc-prediv"; | ||
| 52 | }; | ||
| 53 | |||
| 54 | clk_s_a0_hs: clk-s-a0-hs { | ||
| 55 | #clock-cells = <1>; | ||
| 56 | compatible = "st,clkgena-divmux-c65-hs", | ||
| 57 | "st,clkgena-divmux"; | ||
| 58 | |||
| 59 | clocks = <&clk_s_a0_osc_prediv>, | ||
| 60 | <&clk_s_a0_pll 0>, /* PLL0 HS */ | ||
| 61 | <&clk_s_a0_pll 2>; /* PLL1 */ | ||
| 62 | |||
| 63 | clock-output-names = "clk-s-fdma-0", | ||
| 64 | "clk-s-fdma-1", | ||
| 65 | ""; /* clk-s-jit-sense */ | ||
| 66 | /* Fourth output unused */ | ||
| 67 | }; | ||
| 68 | |||
| 69 | clk_s_a0_ls: clk-s-a0-ls { | ||
| 70 | #clock-cells = <1>; | ||
| 71 | compatible = "st,clkgena-divmux-c65-ls", | ||
| 72 | "st,clkgena-divmux"; | ||
| 73 | |||
| 74 | clocks = <&clk_s_a0_osc_prediv>, | ||
| 75 | <&clk_s_a0_pll 1>, /* PLL0 LS */ | ||
| 76 | <&clk_s_a0_pll 2>; /* PLL1 */ | ||
| 77 | |||
| 78 | clock-output-names = "clk-s-icn-reg-0", | ||
| 79 | "clk-s-icn-if-0", | ||
| 80 | "clk-s-icn-reg-lp-0", | ||
| 81 | "clk-s-emiss", | ||
| 82 | "clk-s-eth1-phy", | ||
| 83 | "clk-s-mii-ref-out"; | ||
| 84 | /* Remaining outputs unused */ | ||
| 85 | }; | ||
| 86 | }; | ||
| 87 | |||
| 88 | clockgen-a@fee81000 { | ||
| 89 | reg = <0xfee81000 0xb48>; | ||
| 90 | |||
| 91 | clk_s_a1_pll: clk-s-a1-pll { | ||
| 92 | #clock-cells = <1>; | ||
| 93 | compatible = "st,clkgena-plls-c65"; | ||
| 94 | |||
| 95 | clocks = <&clk_sysin>; | ||
| 96 | |||
| 97 | clock-output-names = "clk-s-a1-pll0-hs", | ||
| 98 | "clk-s-a1-pll0-ls", | ||
| 99 | "clk-s-a1-pll1"; | ||
| 100 | }; | ||
| 101 | |||
| 102 | clk_s_a1_osc_prediv: clk-s-a1-osc-prediv { | ||
| 103 | #clock-cells = <0>; | ||
| 104 | compatible = "st,clkgena-prediv-c65", | ||
| 105 | "st,clkgena-prediv"; | ||
| 106 | |||
| 107 | clocks = <&clk_sysin>; | ||
| 108 | |||
| 109 | clock-output-names = "clk-s-a1-osc-prediv"; | ||
| 110 | }; | ||
| 111 | |||
| 112 | clk_s_a1_hs: clk-s-a1-hs { | ||
| 113 | #clock-cells = <1>; | ||
| 114 | compatible = "st,clkgena-divmux-c65-hs", | ||
| 115 | "st,clkgena-divmux"; | ||
| 116 | |||
| 117 | clocks = <&clk_s_a1_osc_prediv>, | ||
| 118 | <&clk_s_a1_pll 0>, /* PLL0 HS */ | ||
| 119 | <&clk_s_a1_pll 2>; /* PLL1 */ | ||
| 120 | |||
| 121 | clock-output-names = "", /* Reserved */ | ||
| 122 | "", /* Reserved */ | ||
| 123 | "clk-s-stac-phy", | ||
| 124 | "clk-s-vtac-tx-phy"; | ||
| 125 | }; | ||
| 126 | |||
| 127 | clk_s_a1_ls: clk-s-a1-ls { | ||
| 128 | #clock-cells = <1>; | ||
| 129 | compatible = "st,clkgena-divmux-c65-ls", | ||
| 130 | "st,clkgena-divmux"; | ||
| 131 | |||
| 132 | clocks = <&clk_s_a1_osc_prediv>, | ||
| 133 | <&clk_s_a1_pll 1>, /* PLL0 LS */ | ||
| 134 | <&clk_s_a1_pll 2>; /* PLL1 */ | ||
| 135 | |||
| 136 | clock-output-names = "clk-s-icn-if-2", | ||
| 137 | "clk-s-card-mmc-0", | ||
| 138 | "clk-s-icn-if-1", | ||
| 139 | "clk-s-gmac0-phy", | ||
| 140 | "clk-s-nand-ctrl", | ||
| 141 | "", /* Reserved */ | ||
| 142 | "clk-s-mii0-ref-out", | ||
| 143 | "clk-s-stac-sys", | ||
| 144 | "clk-s-card-mmc-1"; | ||
| 145 | /* Remaining outputs unused */ | ||
| 146 | }; | ||
| 147 | }; | ||
| 148 | |||
| 149 | /* | ||
| 150 | * ClockGenAs on MPE42 | ||
| 151 | */ | ||
| 152 | clockgen-a@fde12000 { | ||
| 153 | reg = <0xfde12000 0xb50>; | ||
| 154 | |||
| 155 | clk_m_a0_pll0: clk-m-a0-pll0 { | ||
| 156 | #clock-cells = <1>; | ||
| 157 | compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; | ||
| 158 | |||
| 159 | clocks = <&clk_sysin>; | ||
| 160 | |||
| 161 | clock-output-names = "clk-m-a0-pll0-phi0", | ||
| 162 | "clk-m-a0-pll0-phi1", | ||
| 163 | "clk-m-a0-pll0-phi2", | ||
| 164 | "clk-m-a0-pll0-phi3"; | ||
| 165 | }; | ||
| 166 | |||
| 167 | clk_m_a0_pll1: clk-m-a0-pll1 { | ||
| 168 | #clock-cells = <1>; | ||
| 169 | compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; | ||
| 170 | |||
| 171 | clocks = <&clk_sysin>; | ||
| 172 | |||
| 173 | clock-output-names = "clk-m-a0-pll1-phi0", | ||
| 174 | "clk-m-a0-pll1-phi1", | ||
| 175 | "clk-m-a0-pll1-phi2", | ||
| 176 | "clk-m-a0-pll1-phi3"; | ||
| 177 | }; | ||
| 178 | |||
| 179 | clk_m_a0_osc_prediv: clk-m-a0-osc-prediv { | ||
| 180 | #clock-cells = <0>; | ||
| 181 | compatible = "st,clkgena-prediv-c32", | ||
| 182 | "st,clkgena-prediv"; | ||
| 183 | |||
| 184 | clocks = <&clk_sysin>; | ||
| 185 | |||
| 186 | clock-output-names = "clk-m-a0-osc-prediv"; | ||
| 187 | }; | ||
| 188 | |||
| 189 | clk_m_a0_div0: clk-m-a0-div0 { | ||
| 190 | #clock-cells = <1>; | ||
| 191 | compatible = "st,clkgena-divmux-c32-odf0", | ||
| 192 | "st,clkgena-divmux"; | ||
| 193 | |||
| 194 | clocks = <&clk_m_a0_osc_prediv>, | ||
| 195 | <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */ | ||
| 196 | <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */ | ||
| 197 | |||
| 198 | clock-output-names = "", /* Unused */ | ||
| 199 | "", /* Unused */ | ||
| 200 | "clk-m-fdma-12", | ||
| 201 | "", /* Unused */ | ||
| 202 | "clk-m-pp-dmu-0", | ||
| 203 | "clk-m-pp-dmu-1", | ||
| 204 | "clk-m-icm-lmi", | ||
| 205 | "clk-m-vid-dmu-0"; | ||
| 206 | }; | ||
| 207 | |||
| 208 | clk_m_a0_div1: clk-m-a0-div1 { | ||
| 209 | #clock-cells = <1>; | ||
| 210 | compatible = "st,clkgena-divmux-c32-odf1", | ||
| 211 | "st,clkgena-divmux"; | ||
| 212 | |||
| 213 | clocks = <&clk_m_a0_osc_prediv>, | ||
| 214 | <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */ | ||
| 215 | <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */ | ||
| 216 | |||
| 217 | clock-output-names = "clk-m-vid-dmu-1", | ||
| 218 | "", /* Unused */ | ||
| 219 | "clk-m-a9-ext2f", | ||
| 220 | "clk-m-st40rt", | ||
| 221 | "clk-m-st231-dmu-0", | ||
| 222 | "clk-m-st231-dmu-1", | ||
| 223 | "clk-m-st231-aud", | ||
| 224 | "clk-m-st231-gp-0"; | ||
| 225 | }; | ||
| 226 | |||
| 227 | clk_m_a0_div2: clk-m-a0-div2 { | ||
| 228 | #clock-cells = <1>; | ||
| 229 | compatible = "st,clkgena-divmux-c32-odf2", | ||
| 230 | "st,clkgena-divmux"; | ||
| 231 | |||
| 232 | clocks = <&clk_m_a0_osc_prediv>, | ||
| 233 | <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */ | ||
| 234 | <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */ | ||
| 235 | |||
| 236 | clock-output-names = "clk-m-st231-gp-1", | ||
| 237 | "clk-m-icn-cpu", | ||
| 238 | "clk-m-icn-stac", | ||
| 239 | "clk-m-tx-icn-dmu-0", | ||
| 240 | "clk-m-tx-icn-dmu-1", | ||
| 241 | "clk-m-tx-icn-ts", | ||
| 242 | "clk-m-icn-vdp-0", | ||
| 243 | "clk-m-icn-vdp-1"; | ||
| 244 | }; | ||
| 245 | |||
| 246 | clk_m_a0_div3: clk-m-a0-div3 { | ||
| 247 | #clock-cells = <1>; | ||
| 248 | compatible = "st,clkgena-divmux-c32-odf3", | ||
| 249 | "st,clkgena-divmux"; | ||
| 250 | |||
| 251 | clocks = <&clk_m_a0_osc_prediv>, | ||
| 252 | <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */ | ||
| 253 | <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */ | ||
| 254 | |||
| 255 | clock-output-names = "", /* Unused */ | ||
| 256 | "", /* Unused */ | ||
| 257 | "", /* Unused */ | ||
| 258 | "", /* Unused */ | ||
| 259 | "clk-m-icn-vp8", | ||
| 260 | "", /* Unused */ | ||
| 261 | "clk-m-icn-reg-11", | ||
| 262 | "clk-m-a9-trace"; | ||
| 263 | }; | ||
| 264 | }; | ||
| 265 | |||
| 266 | clockgen-a@fd6db000 { | ||
| 267 | reg = <0xfd6db000 0xb50>; | ||
| 268 | |||
| 269 | clk_m_a1_pll0: clk-m-a1-pll0 { | ||
| 270 | #clock-cells = <1>; | ||
| 271 | compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; | ||
| 272 | |||
| 273 | clocks = <&clk_sysin>; | ||
| 274 | |||
| 275 | clock-output-names = "clk-m-a1-pll0-phi0", | ||
| 276 | "clk-m-a1-pll0-phi1", | ||
| 277 | "clk-m-a1-pll0-phi2", | ||
| 278 | "clk-m-a1-pll0-phi3"; | ||
| 279 | }; | ||
| 280 | |||
| 281 | clk_m_a1_pll1: clk-m-a1-pll1 { | ||
| 282 | #clock-cells = <1>; | ||
| 283 | compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; | ||
| 284 | |||
| 285 | clocks = <&clk_sysin>; | ||
| 286 | |||
| 287 | clock-output-names = "clk-m-a1-pll1-phi0", | ||
| 288 | "clk-m-a1-pll1-phi1", | ||
| 289 | "clk-m-a1-pll1-phi2", | ||
| 290 | "clk-m-a1-pll1-phi3"; | ||
| 291 | }; | ||
| 292 | |||
| 293 | clk_m_a1_osc_prediv: clk-m-a1-osc-prediv { | ||
| 294 | #clock-cells = <0>; | ||
| 295 | compatible = "st,clkgena-prediv-c32", | ||
| 296 | "st,clkgena-prediv"; | ||
| 297 | |||
| 298 | clocks = <&clk_sysin>; | ||
| 299 | |||
| 300 | clock-output-names = "clk-m-a1-osc-prediv"; | ||
| 301 | }; | ||
| 302 | |||
| 303 | clk_m_a1_div0: clk-m-a1-div0 { | ||
| 304 | #clock-cells = <1>; | ||
| 305 | compatible = "st,clkgena-divmux-c32-odf0", | ||
| 306 | "st,clkgena-divmux"; | ||
| 307 | |||
| 308 | clocks = <&clk_m_a1_osc_prediv>, | ||
| 309 | <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */ | ||
| 310 | <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */ | ||
| 311 | |||
| 312 | clock-output-names = "", /* Unused */ | ||
| 313 | "clk-m-fdma-10", | ||
| 314 | "clk-m-fdma-11", | ||
| 315 | "clk-m-hva-alt", | ||
| 316 | "clk-m-proc-sc", | ||
| 317 | "clk-m-tp", | ||
| 318 | "clk-m-rx-icn-dmu-0", | ||
| 319 | "clk-m-rx-icn-dmu-1"; | ||
| 320 | }; | ||
| 321 | |||
| 322 | clk_m_a1_div1: clk-m-a1-div1 { | ||
| 323 | #clock-cells = <1>; | ||
| 324 | compatible = "st,clkgena-divmux-c32-odf1", | ||
| 325 | "st,clkgena-divmux"; | ||
| 326 | |||
| 327 | clocks = <&clk_m_a1_osc_prediv>, | ||
| 328 | <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */ | ||
| 329 | <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */ | ||
| 330 | |||
| 331 | clock-output-names = "clk-m-rx-icn-ts", | ||
| 332 | "clk-m-rx-icn-vdp-0", | ||
| 333 | "", /* Unused */ | ||
| 334 | "clk-m-prv-t1-bus", | ||
| 335 | "clk-m-icn-reg-12", | ||
| 336 | "clk-m-icn-reg-10", | ||
| 337 | "", /* Unused */ | ||
| 338 | "clk-m-icn-st231"; | ||
| 339 | }; | ||
| 340 | |||
| 341 | clk_m_a1_div2: clk-m-a1-div2 { | ||
| 342 | #clock-cells = <1>; | ||
| 343 | compatible = "st,clkgena-divmux-c32-odf2", | ||
| 344 | "st,clkgena-divmux"; | ||
| 345 | |||
| 346 | clocks = <&clk_m_a1_osc_prediv>, | ||
| 347 | <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */ | ||
| 348 | <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */ | ||
| 349 | |||
| 350 | clock-output-names = "clk-m-fvdp-proc-alt", | ||
| 351 | "clk-m-icn-reg-13", | ||
| 352 | "clk-m-tx-icn-gpu", | ||
| 353 | "clk-m-rx-icn-gpu", | ||
| 354 | "", /* Unused */ | ||
| 355 | "", /* Unused */ | ||
| 356 | "", /* clk-m-apb-pm-12 */ | ||
| 357 | ""; /* Unused */ | ||
| 358 | }; | ||
| 359 | |||
| 360 | clk_m_a1_div3: clk-m-a1-div3 { | ||
| 361 | #clock-cells = <1>; | ||
| 362 | compatible = "st,clkgena-divmux-c32-odf3", | ||
| 363 | "st,clkgena-divmux"; | ||
| 364 | |||
| 365 | clocks = <&clk_m_a1_osc_prediv>, | ||
| 366 | <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */ | ||
| 367 | <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */ | ||
| 368 | |||
| 369 | clock-output-names = "", /* Unused */ | ||
| 370 | "", /* Unused */ | ||
| 371 | "", /* Unused */ | ||
| 372 | "", /* Unused */ | ||
| 373 | "", /* Unused */ | ||
| 374 | "", /* Unused */ | ||
| 375 | "", /* Unused */ | ||
| 376 | ""; /* clk-m-gpu-alt */ | ||
| 377 | }; | ||
| 378 | }; | ||
| 379 | |||
| 380 | clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 { | ||
| 381 | #clock-cells = <0>; | ||
| 382 | compatible = "fixed-factor-clock"; | ||
| 383 | clocks = <&clk_m_a0_div1 2>; | ||
| 384 | clock-div = <2>; | ||
| 385 | clock-mult = <1>; | ||
| 386 | }; | ||
| 387 | |||
| 388 | clockgen-a@fd345000 { | ||
| 389 | reg = <0xfd345000 0xb50>; | ||
| 390 | |||
| 391 | clk_m_a2_pll0: clk-m-a2-pll0 { | ||
| 392 | #clock-cells = <1>; | ||
| 393 | compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; | ||
| 394 | |||
| 395 | clocks = <&clk_sysin>; | ||
| 396 | |||
| 397 | clock-output-names = "clk-m-a2-pll0-phi0", | ||
| 398 | "clk-m-a2-pll0-phi1", | ||
| 399 | "clk-m-a2-pll0-phi2", | ||
| 400 | "clk-m-a2-pll0-phi3"; | ||
| 401 | }; | ||
| 402 | |||
| 403 | clk_m_a2_pll1: clk-m-a2-pll1 { | ||
| 404 | #clock-cells = <1>; | ||
| 405 | compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; | ||
| 406 | |||
| 407 | clocks = <&clk_sysin>; | ||
| 408 | |||
| 409 | clock-output-names = "clk-m-a2-pll1-phi0", | ||
| 410 | "clk-m-a2-pll1-phi1", | ||
| 411 | "clk-m-a2-pll1-phi2", | ||
| 412 | "clk-m-a2-pll1-phi3"; | ||
| 413 | }; | ||
| 414 | |||
| 415 | clk_m_a2_osc_prediv: clk-m-a2-osc-prediv { | ||
| 416 | #clock-cells = <0>; | ||
| 417 | compatible = "st,clkgena-prediv-c32", | ||
| 418 | "st,clkgena-prediv"; | ||
| 419 | |||
| 420 | clocks = <&clk_sysin>; | ||
| 421 | |||
| 422 | clock-output-names = "clk-m-a2-osc-prediv"; | ||
| 423 | }; | ||
| 424 | |||
| 425 | clk_m_a2_div0: clk-m-a2-div0 { | ||
| 426 | #clock-cells = <1>; | ||
| 427 | compatible = "st,clkgena-divmux-c32-odf0", | ||
| 428 | "st,clkgena-divmux"; | ||
| 429 | |||
| 430 | clocks = <&clk_m_a2_osc_prediv>, | ||
| 431 | <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */ | ||
| 432 | <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */ | ||
| 433 | |||
| 434 | clock-output-names = "clk-m-vtac-main-phy", | ||
| 435 | "clk-m-vtac-aux-phy", | ||
| 436 | "clk-m-stac-phy", | ||
| 437 | "clk-m-stac-sys", | ||
| 438 | "", /* clk-m-mpestac-pg */ | ||
| 439 | "", /* clk-m-mpestac-wc */ | ||
| 440 | "", /* clk-m-mpevtacaux-pg*/ | ||
| 441 | ""; /* clk-m-mpevtacmain-pg*/ | ||
| 442 | }; | ||
| 443 | |||
| 444 | clk_m_a2_div1: clk-m-a2-div1 { | ||
| 445 | #clock-cells = <1>; | ||
| 446 | compatible = "st,clkgena-divmux-c32-odf1", | ||
| 447 | "st,clkgena-divmux"; | ||
| 448 | |||
| 449 | clocks = <&clk_m_a2_osc_prediv>, | ||
| 450 | <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */ | ||
| 451 | <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */ | ||
| 452 | |||
| 453 | clock-output-names = "", /* clk-m-mpevtacrx0-wc */ | ||
| 454 | "", /* clk-m-mpevtacrx1-wc */ | ||
| 455 | "clk-m-compo-main", | ||
| 456 | "clk-m-compo-aux", | ||
| 457 | "clk-m-bdisp-0", | ||
| 458 | "clk-m-bdisp-1", | ||
| 459 | "clk-m-icn-bdisp", | ||
| 460 | "clk-m-icn-compo"; | ||
| 461 | }; | ||
| 462 | |||
| 463 | clk_m_a2_div2: clk-m-a2-div2 { | ||
| 464 | #clock-cells = <1>; | ||
| 465 | compatible = "st,clkgena-divmux-c32-odf2", | ||
| 466 | "st,clkgena-divmux"; | ||
| 467 | |||
| 468 | clocks = <&clk_m_a2_osc_prediv>, | ||
| 469 | <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */ | ||
| 470 | <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */ | ||
| 471 | |||
| 472 | clock-output-names = "clk-m-icn-vdp-2", | ||
| 473 | "", /* Unused */ | ||
| 474 | "clk-m-icn-reg-14", | ||
| 475 | "clk-m-mdtp", | ||
| 476 | "clk-m-jpegdec", | ||
| 477 | "", /* Unused */ | ||
| 478 | "clk-m-dcephy-impctrl", | ||
| 479 | ""; /* Unused */ | ||
| 480 | }; | ||
| 481 | |||
| 482 | clk_m_a2_div3: clk-m-a2-div3 { | ||
| 483 | #clock-cells = <1>; | ||
| 484 | compatible = "st,clkgena-divmux-c32-odf3", | ||
| 485 | "st,clkgena-divmux"; | ||
| 486 | |||
| 487 | clocks = <&clk_m_a2_osc_prediv>, | ||
| 488 | <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */ | ||
| 489 | <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */ | ||
| 490 | |||
| 491 | clock-output-names = "", /* Unused */ | ||
| 492 | ""; /* clk-m-apb-pm-11 */ | ||
| 493 | /* Remaining outputs unused */ | ||
| 494 | }; | ||
| 495 | }; | ||
| 496 | |||
| 497 | /* | ||
| 498 | * A9 PLL | ||
| 499 | */ | ||
| 500 | clockgen-a9@fdde08b0 { | ||
| 501 | reg = <0xfdde08b0 0x70>; | ||
| 502 | |||
| 503 | clockgen_a9_pll: clockgen-a9-pll { | ||
| 504 | #clock-cells = <1>; | ||
| 505 | compatible = "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"; | ||
| 506 | |||
| 507 | clocks = <&clk_sysin>; | ||
| 508 | clock-output-names = "clockgen-a9-pll-odf"; | ||
| 509 | }; | ||
| 510 | }; | ||
| 511 | |||
| 512 | /* | ||
| 513 | * ARM CPU related clocks | ||
| 514 | */ | ||
| 515 | clk_m_a9: clk-m-a9@fdde08ac { | ||
| 516 | #clock-cells = <0>; | ||
| 517 | compatible = "st,stih416-clkgen-a9-mux", "st,clkgen-mux"; | ||
| 518 | reg = <0xfdde08ac 0x4>; | ||
| 519 | clocks = <&clockgen_a9_pll 0>, | ||
| 520 | <&clockgen_a9_pll 0>, | ||
| 521 | <&clk_m_a0_div1 2>, | ||
| 522 | <&clk_m_a9_ext2f_div2>; | ||
| 19 | }; | 523 | }; |
| 20 | 524 | ||
| 21 | /* | 525 | /* |
| 22 | * ARM Peripheral clock for timers | 526 | * ARM Peripheral clock for timers |
| 23 | */ | 527 | */ |
| 24 | arm_periph_clk: arm_periph_clk { | 528 | arm_periph_clk: clk-m-a9-periphs { |
| 25 | #clock-cells = <0>; | 529 | #clock-cells = <0>; |
| 26 | compatible = "fixed-clock"; | 530 | compatible = "fixed-factor-clock"; |
| 27 | clock-frequency = <600000000>; | 531 | clocks = <&clk_m_a9>; |
| 532 | clock-div = <2>; | ||
| 533 | clock-mult = <1>; | ||
| 28 | }; | 534 | }; |
| 29 | 535 | ||
| 30 | /* | 536 | /* |
| 31 | * Bootloader initialized system infrastructure clock for | 537 | * Frequency synthesizers on the SASG2 |
| 32 | * serial devices. | ||
| 33 | */ | 538 | */ |
| 34 | CLK_S_ICN_REG_0: clockgenA0@4 { | 539 | clockgen_b0: clockgen-b0@fee108b4 { |
| 540 | #clock-cells = <1>; | ||
| 541 | compatible = "st,stih416-quadfs216", "st,quadfs"; | ||
| 542 | reg = <0xfee108b4 0x44>; | ||
| 543 | |||
| 544 | clocks = <&clk_sysin>; | ||
| 545 | clock-output-names = "clk-s-usb48", | ||
| 546 | "clk-s-dss", | ||
| 547 | "clk-s-stfe-frc-2", | ||
| 548 | "clk-s-thsens-scard"; | ||
| 549 | }; | ||
| 550 | |||
| 551 | clockgen_b1: clockgen-b1@fe8308c4 { | ||
| 552 | #clock-cells = <1>; | ||
| 553 | compatible = "st,stih416-quadfs216", "st,quadfs"; | ||
| 554 | reg = <0xfe8308c4 0x44>; | ||
| 555 | |||
| 556 | clocks = <&clk_sysin>; | ||
| 557 | clock-output-names = "clk-s-pcm-0", | ||
| 558 | "clk-s-pcm-1", | ||
| 559 | "clk-s-pcm-2", | ||
| 560 | "clk-s-pcm-3"; | ||
| 561 | }; | ||
| 562 | |||
| 563 | clockgen_c: clockgen-c@fe8307d0 { | ||
| 564 | #clock-cells = <1>; | ||
| 565 | compatible = "st,stih416-quadfs432", "st,quadfs"; | ||
| 566 | reg = <0xfe8307d0 0x44>; | ||
| 567 | |||
| 568 | clocks = <&clk_sysin>; | ||
| 569 | clock-output-names = "clk-s-c-fs0-ch0", | ||
| 570 | "clk-s-c-vcc-sd", | ||
| 571 | "clk-s-c-fs0-ch2"; | ||
| 572 | }; | ||
| 573 | |||
| 574 | clk_s_vcc_hd: clk-s-vcc-hd@fe8308b8 { | ||
| 35 | #clock-cells = <0>; | 575 | #clock-cells = <0>; |
| 36 | compatible = "fixed-clock"; | 576 | compatible = "st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"; |
| 37 | clock-frequency = <100000000>; | 577 | reg = <0xfe8308b8 0x4>; /* SYSCFG2558 */ |
| 38 | clock-output-names = "CLK_S_ICN_REG_0"; | 578 | |
| 579 | clocks = <&clk_sysin>, | ||
| 580 | <&clockgen_c 0>; | ||
| 39 | }; | 581 | }; |
| 40 | 582 | ||
| 41 | CLK_S_GMAC0_PHY: clockgenA1@7 { | 583 | /* |
| 584 | * Add a dummy clock for the HDMI PHY for the VCC input mux | ||
| 585 | */ | ||
| 586 | clk_s_tmds_fromphy: clk-s-tmds-fromphy { | ||
| 42 | #clock-cells = <0>; | 587 | #clock-cells = <0>; |
| 43 | compatible = "fixed-clock"; | 588 | compatible = "fixed-clock"; |
| 44 | clock-frequency = <25000000>; | 589 | clock-frequency = <0>; |
| 45 | clock-output-names = "CLK_S_GMAC0_PHY"; | 590 | }; |
| 591 | |||
| 592 | clockgen_c_vcc: clockgen-c-vcc@fe8308ac { | ||
| 593 | #clock-cells = <1>; | ||
| 594 | compatible = "st,stih416-clkgenc", "st,clkgen-vcc"; | ||
| 595 | reg = <0xfe8308ac 0xc>; /* SYSCFG2555,2556,2557 */ | ||
| 596 | |||
| 597 | clocks = <&clk_s_vcc_hd>, | ||
| 598 | <&clockgen_c 1>, | ||
| 599 | <&clk_s_tmds_fromphy>, | ||
| 600 | <&clockgen_c 2>; | ||
| 601 | |||
| 602 | clock-output-names = "clk-s-pix-hdmi", | ||
| 603 | "clk-s-pix-dvo", | ||
| 604 | "clk-s-out-dvo", | ||
| 605 | "clk-s-pix-hd", | ||
| 606 | "clk-s-hddac", | ||
| 607 | "clk-s-denc", | ||
| 608 | "clk-s-sddac", | ||
| 609 | "clk-s-pix-main", | ||
| 610 | "clk-s-pix-aux", | ||
| 611 | "clk-s-stfe-frc-0", | ||
| 612 | "clk-s-ref-mcru", | ||
| 613 | "clk-s-slave-mcru", | ||
| 614 | "clk-s-tmds-hdmi", | ||
| 615 | "clk-s-hdmi-reject-pll", | ||
| 616 | "clk-s-thsens"; | ||
| 46 | }; | 617 | }; |
| 47 | 618 | ||
| 48 | CLK_S_ETH1_PHY: clockgenA0@7 { | 619 | clockgen_d: clockgen-d@fee107e0 { |
| 620 | #clock-cells = <1>; | ||
| 621 | compatible = "st,stih416-quadfs216", "st,quadfs"; | ||
| 622 | reg = <0xfee107e0 0x44>; | ||
| 623 | |||
| 624 | clocks = <&clk_sysin>; | ||
| 625 | clock-output-names = "clk-s-ccsc", | ||
| 626 | "clk-s-stfe-frc-1", | ||
| 627 | "clk-s-tsout-1", | ||
| 628 | "clk-s-mchi"; | ||
| 629 | }; | ||
| 630 | |||
| 631 | /* | ||
| 632 | * Frequency synthesizers on the MPE42 | ||
| 633 | */ | ||
| 634 | clockgen_e: clockgen-e@fd3208bc { | ||
| 635 | #clock-cells = <1>; | ||
| 636 | compatible = "st,stih416-quadfs660-E", "st,quadfs"; | ||
| 637 | reg = <0xfd3208bc 0xb0>; | ||
| 638 | |||
| 639 | clocks = <&clk_sysin>; | ||
| 640 | clock-output-names = "clk-m-pix-mdtp-0", | ||
| 641 | "clk-m-pix-mdtp-1", | ||
| 642 | "clk-m-pix-mdtp-2", | ||
| 643 | "clk-m-mpelpc"; | ||
| 644 | }; | ||
| 645 | |||
| 646 | clockgen_f: clockgen-f@fd320878 { | ||
| 647 | #clock-cells = <1>; | ||
| 648 | compatible = "st,stih416-quadfs660-F", "st,quadfs"; | ||
| 649 | reg = <0xfd320878 0xf0>; | ||
| 650 | |||
| 651 | clocks = <&clk_sysin>; | ||
| 652 | clock-output-names = "clk-m-main-vidfs", | ||
| 653 | "clk-m-hva-fs", | ||
| 654 | "clk-m-fvdp-vcpu", | ||
| 655 | "clk-m-fvdp-proc-fs"; | ||
| 656 | }; | ||
| 657 | |||
| 658 | clk_m_fvdp_proc: clk-m-fvdp-proc@fd320910 { | ||
| 659 | #clock-cells = <0>; | ||
| 660 | compatible = "st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"; | ||
| 661 | reg = <0xfd320910 0x4>; /* SYSCFG8580 */ | ||
| 662 | |||
| 663 | clocks = <&clk_m_a1_div2 0>, | ||
| 664 | <&clockgen_f 3>; | ||
| 665 | }; | ||
| 666 | |||
| 667 | clk_m_hva: clk-m-hva@fd690868 { | ||
| 668 | #clock-cells = <0>; | ||
| 669 | compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"; | ||
| 670 | reg = <0xfd690868 0x4>; /* SYSCFG9538 */ | ||
| 671 | |||
| 672 | clocks = <&clockgen_f 1>, | ||
| 673 | <&clk_m_a1_div0 3>; | ||
| 674 | }; | ||
| 675 | |||
| 676 | clk_m_f_vcc_hd: clk-m-f-vcc-hd@fd32086c { | ||
| 677 | #clock-cells = <0>; | ||
| 678 | compatible = "st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"; | ||
| 679 | reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ | ||
| 680 | |||
| 681 | clocks = <&clockgen_c_vcc 7>, | ||
| 682 | <&clockgen_f 0>; | ||
| 683 | }; | ||
| 684 | |||
| 685 | clk_m_f_vcc_sd: clk-m-f-vcc-sd@fd32086c { | ||
| 686 | #clock-cells = <0>; | ||
| 687 | compatible = "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"; | ||
| 688 | reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ | ||
| 689 | |||
| 690 | clocks = <&clockgen_c_vcc 8>, | ||
| 691 | <&clockgen_f 1>; | ||
| 692 | }; | ||
| 693 | |||
| 694 | /* | ||
| 695 | * Add a dummy clock for the HDMIRx external signal clock | ||
| 696 | */ | ||
| 697 | clk_m_pix_hdmirx_sas: clk-m-pix-hdmirx-sas { | ||
| 49 | #clock-cells = <0>; | 698 | #clock-cells = <0>; |
| 50 | compatible = "fixed-clock"; | 699 | compatible = "fixed-clock"; |
| 51 | clock-frequency = <25000000>; | 700 | clock-frequency = <0>; |
| 52 | clock-output-names = "CLK_S_ETH1_PHY"; | 701 | }; |
| 702 | |||
| 703 | clockgen_f_vcc: clockgen-f-vcc@fd32086c { | ||
| 704 | #clock-cells = <1>; | ||
| 705 | compatible = "st,stih416-clkgenf", "st,clkgen-vcc"; | ||
| 706 | reg = <0xfd32086c 0xc>; /* SYSCFG8539,8540,8541 */ | ||
| 707 | |||
| 708 | clocks = <&clk_m_f_vcc_hd>, | ||
| 709 | <&clk_m_f_vcc_sd>, | ||
| 710 | <&clockgen_f 0>, | ||
| 711 | <&clk_m_pix_hdmirx_sas>; | ||
| 712 | |||
| 713 | clock-output-names = "clk-m-pix-main-pipe", | ||
| 714 | "clk-m-pix-aux-pipe", | ||
| 715 | "clk-m-pix-main-cru", | ||
| 716 | "clk-m-pix-aux-cru", | ||
| 717 | "clk-m-xfer-be-compo", | ||
| 718 | "clk-m-xfer-pip-compo", | ||
| 719 | "clk-m-xfer-aux-compo", | ||
| 720 | "clk-m-vsens", | ||
| 721 | "clk-m-pix-hdmirx-0", | ||
| 722 | "clk-m-pix-hdmirx-1"; | ||
| 723 | }; | ||
| 724 | |||
| 725 | /* | ||
| 726 | * DDR PLL | ||
| 727 | */ | ||
| 728 | clockgen-ddr@0xfdde07d8 { | ||
| 729 | reg = <0xfdde07d8 0x110>; | ||
| 730 | |||
| 731 | clockgen_ddr_pll: clockgen-ddr-pll { | ||
| 732 | #clock-cells = <1>; | ||
| 733 | compatible = "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"; | ||
| 734 | |||
| 735 | clocks = <&clk_sysin>; | ||
| 736 | clock-output-names = "clockgen-ddr0", | ||
| 737 | "clockgen-ddr1"; | ||
| 738 | }; | ||
| 739 | }; | ||
| 740 | |||
| 741 | /* | ||
| 742 | * GPU PLL | ||
| 743 | */ | ||
| 744 | clockgen-gpu@fd68ff00 { | ||
| 745 | reg = <0xfd68ff00 0x910>; | ||
| 746 | |||
| 747 | clockgen_gpu_pll: clockgen-gpu-pll { | ||
| 748 | #clock-cells = <1>; | ||
| 749 | compatible = "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"; | ||
| 750 | |||
| 751 | clocks = <&clk_sysin>; | ||
| 752 | clock-output-names = "clockgen-gpu-pll"; | ||
| 753 | }; | ||
| 53 | }; | 754 | }; |
| 54 | }; | 755 | }; |
| 55 | }; | 756 | }; |
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index 250d5ecc951e..ee6c119e261e 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi | |||
| @@ -122,6 +122,22 @@ | |||
| 122 | }; | 122 | }; |
| 123 | }; | 123 | }; |
| 124 | 124 | ||
| 125 | keyscan { | ||
| 126 | pinctrl_keyscan: keyscan { | ||
| 127 | st,pins { | ||
| 128 | keyin0 = <&PIO0 2 ALT2 IN>; | ||
| 129 | keyin1 = <&PIO0 3 ALT2 IN>; | ||
| 130 | keyin2 = <&PIO0 4 ALT2 IN>; | ||
| 131 | keyin3 = <&PIO2 6 ALT2 IN>; | ||
| 132 | |||
| 133 | keyout0 = <&PIO1 6 ALT2 OUT>; | ||
| 134 | keyout1 = <&PIO1 7 ALT2 OUT>; | ||
| 135 | keyout2 = <&PIO0 6 ALT2 OUT>; | ||
| 136 | keyout3 = <&PIO2 7 ALT2 OUT>; | ||
| 137 | }; | ||
| 138 | }; | ||
| 139 | }; | ||
| 140 | |||
| 125 | sbc_i2c0 { | 141 | sbc_i2c0 { |
| 126 | pinctrl_sbc_i2c0_default: sbc_i2c0-default { | 142 | pinctrl_sbc_i2c0_default: sbc_i2c0-default { |
| 127 | st,pins { | 143 | st,pins { |
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 78746d20382e..06473c5d9ea9 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi | |||
| @@ -89,7 +89,7 @@ | |||
| 89 | status = "disabled"; | 89 | status = "disabled"; |
| 90 | reg = <0xfed32000 0x2c>; | 90 | reg = <0xfed32000 0x2c>; |
| 91 | interrupts = <0 197 0>; | 91 | interrupts = <0 197 0>; |
| 92 | clocks = <&CLK_S_ICN_REG_0>; | 92 | clocks = <&clk_s_a0_ls CLK_ICN_REG>; |
| 93 | pinctrl-names = "default"; | 93 | pinctrl-names = "default"; |
| 94 | pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>; | 94 | pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>; |
| 95 | }; | 95 | }; |
| @@ -102,14 +102,14 @@ | |||
| 102 | interrupts = <0 210 0>; | 102 | interrupts = <0 210 0>; |
| 103 | pinctrl-names = "default"; | 103 | pinctrl-names = "default"; |
| 104 | pinctrl-0 = <&pinctrl_sbc_serial1>; | 104 | pinctrl-0 = <&pinctrl_sbc_serial1>; |
| 105 | clocks = <&CLK_SYSIN>; | 105 | clocks = <&clk_sysin>; |
| 106 | }; | 106 | }; |
| 107 | 107 | ||
| 108 | i2c@fed40000 { | 108 | i2c@fed40000 { |
| 109 | compatible = "st,comms-ssc4-i2c"; | 109 | compatible = "st,comms-ssc4-i2c"; |
| 110 | reg = <0xfed40000 0x110>; | 110 | reg = <0xfed40000 0x110>; |
| 111 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; | 111 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; |
| 112 | clocks = <&CLK_S_ICN_REG_0>; | 112 | clocks = <&clk_s_a0_ls CLK_ICN_REG>; |
| 113 | clock-names = "ssc"; | 113 | clock-names = "ssc"; |
| 114 | clock-frequency = <400000>; | 114 | clock-frequency = <400000>; |
| 115 | pinctrl-names = "default"; | 115 | pinctrl-names = "default"; |
| @@ -122,7 +122,7 @@ | |||
| 122 | compatible = "st,comms-ssc4-i2c"; | 122 | compatible = "st,comms-ssc4-i2c"; |
| 123 | reg = <0xfed41000 0x110>; | 123 | reg = <0xfed41000 0x110>; |
| 124 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; | 124 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; |
| 125 | clocks = <&CLK_S_ICN_REG_0>; | 125 | clocks = <&clk_s_a0_ls CLK_ICN_REG>; |
| 126 | clock-names = "ssc"; | 126 | clock-names = "ssc"; |
| 127 | clock-frequency = <400000>; | 127 | clock-frequency = <400000>; |
| 128 | pinctrl-names = "default"; | 128 | pinctrl-names = "default"; |
| @@ -135,7 +135,7 @@ | |||
| 135 | compatible = "st,comms-ssc4-i2c"; | 135 | compatible = "st,comms-ssc4-i2c"; |
| 136 | reg = <0xfe540000 0x110>; | 136 | reg = <0xfe540000 0x110>; |
| 137 | interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; | 137 | interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 138 | clocks = <&CLK_SYSIN>; | 138 | clocks = <&clk_sysin>; |
| 139 | clock-names = "ssc"; | 139 | clock-names = "ssc"; |
| 140 | clock-frequency = <400000>; | 140 | clock-frequency = <400000>; |
| 141 | pinctrl-names = "default"; | 141 | pinctrl-names = "default"; |
| @@ -148,7 +148,7 @@ | |||
| 148 | compatible = "st,comms-ssc4-i2c"; | 148 | compatible = "st,comms-ssc4-i2c"; |
| 149 | reg = <0xfe541000 0x110>; | 149 | reg = <0xfe541000 0x110>; |
| 150 | interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; | 150 | interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; |
| 151 | clocks = <&CLK_SYSIN>; | 151 | clocks = <&clk_sysin>; |
| 152 | clock-names = "ssc"; | 152 | clock-names = "ssc"; |
| 153 | clock-frequency = <400000>; | 153 | clock-frequency = <400000>; |
| 154 | pinctrl-names = "default"; | 154 | pinctrl-names = "default"; |
| @@ -176,7 +176,7 @@ | |||
| 176 | pinctrl-names = "default"; | 176 | pinctrl-names = "default"; |
| 177 | pinctrl-0 = <&pinctrl_mii0>; | 177 | pinctrl-0 = <&pinctrl_mii0>; |
| 178 | clock-names = "stmmaceth"; | 178 | clock-names = "stmmaceth"; |
| 179 | clocks = <&CLK_S_GMAC0_PHY>; | 179 | clocks = <&clk_s_a1_ls CLK_GMAC0_PHY>; |
| 180 | }; | 180 | }; |
| 181 | 181 | ||
| 182 | ethernet1: dwmac@fef08000 { | 182 | ethernet1: dwmac@fef08000 { |
| @@ -198,7 +198,7 @@ | |||
| 198 | pinctrl-names = "default"; | 198 | pinctrl-names = "default"; |
| 199 | pinctrl-0 = <&pinctrl_mii1>; | 199 | pinctrl-0 = <&pinctrl_mii1>; |
| 200 | clock-names = "stmmaceth"; | 200 | clock-names = "stmmaceth"; |
| 201 | clocks = <&CLK_S_ETH1_PHY>; | 201 | clocks = <&clk_s_a0_ls CLK_ETH1_PHY>; |
| 202 | }; | 202 | }; |
| 203 | 203 | ||
| 204 | rc: rc@fe518000 { | 204 | rc: rc@fe518000 { |
| @@ -206,7 +206,7 @@ | |||
| 206 | reg = <0xfe518000 0x234>; | 206 | reg = <0xfe518000 0x234>; |
| 207 | interrupts = <0 203 0>; | 207 | interrupts = <0 203 0>; |
| 208 | rx-mode = "infrared"; | 208 | rx-mode = "infrared"; |
| 209 | clocks = <&CLK_SYSIN>; | 209 | clocks = <&clk_sysin>; |
| 210 | pinctrl-names = "default"; | 210 | pinctrl-names = "default"; |
| 211 | pinctrl-0 = <&pinctrl_ir>; | 211 | pinctrl-0 = <&pinctrl_ir>; |
| 212 | resets = <&softreset STIH416_IRB_SOFTRESET>; | 212 | resets = <&softreset STIH416_IRB_SOFTRESET>; |
| @@ -224,5 +224,17 @@ | |||
| 224 | 224 | ||
| 225 | status = "disabled"; | 225 | status = "disabled"; |
| 226 | }; | 226 | }; |
| 227 | |||
| 228 | keyscan: keyscan@fe4b0000 { | ||
| 229 | compatible = "st,sti-keyscan"; | ||
| 230 | status = "disabled"; | ||
| 231 | reg = <0xfe4b0000 0x2000>; | ||
| 232 | interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>; | ||
| 233 | clocks = <&clk_sysin>; | ||
| 234 | pinctrl-names = "default"; | ||
| 235 | pinctrl-0 = <&pinctrl_keyscan>; | ||
| 236 | resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>, | ||
| 237 | <&softreset STIH416_KEYSCAN_SOFTRESET>; | ||
| 238 | }; | ||
| 227 | }; | 239 | }; |
| 228 | }; | 240 | }; |
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi index bf65c49095af..b3dd6ca5c2ae 100644 --- a/arch/arm/boot/dts/stih41x-b2000.dtsi +++ b/arch/arm/boot/dts/stih41x-b2000.dtsi | |||
| @@ -6,6 +6,7 @@ | |||
| 6 | * it under the terms of the GNU General Public License version 2 as | 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * publishhed by the Free Software Foundation. | 7 | * publishhed by the Free Software Foundation. |
| 8 | */ | 8 | */ |
| 9 | #include <dt-bindings/input/input.h> | ||
| 9 | / { | 10 | / { |
| 10 | 11 | ||
| 11 | memory{ | 12 | memory{ |
| @@ -14,7 +15,7 @@ | |||
| 14 | }; | 15 | }; |
| 15 | 16 | ||
| 16 | chosen { | 17 | chosen { |
| 17 | bootargs = "console=ttyAS0,115200"; | 18 | bootargs = "console=ttyAS0,115200 clk_ignore_unused"; |
| 18 | linux,stdout-path = &serial2; | 19 | linux,stdout-path = &serial2; |
| 19 | }; | 20 | }; |
| 20 | 21 | ||
| @@ -68,5 +69,27 @@ | |||
| 68 | snps,reset-active-low; | 69 | snps,reset-active-low; |
| 69 | snps,reset-delays-us = <0 10000 10000>; | 70 | snps,reset-delays-us = <0 10000 10000>; |
| 70 | }; | 71 | }; |
| 72 | |||
| 73 | keyscan: keyscan@fe4b0000 { | ||
| 74 | keypad,num-rows = <4>; | ||
| 75 | keypad,num-columns = <4>; | ||
| 76 | st,debounce-us = <5000>; | ||
| 77 | linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_F13) | ||
| 78 | MATRIX_KEY(0x00, 0x01, KEY_F9) | ||
| 79 | MATRIX_KEY(0x00, 0x02, KEY_F5) | ||
| 80 | MATRIX_KEY(0x00, 0x03, KEY_F1) | ||
| 81 | MATRIX_KEY(0x01, 0x00, KEY_F14) | ||
| 82 | MATRIX_KEY(0x01, 0x01, KEY_F10) | ||
| 83 | MATRIX_KEY(0x01, 0x02, KEY_F6) | ||
| 84 | MATRIX_KEY(0x01, 0x03, KEY_F2) | ||
| 85 | MATRIX_KEY(0x02, 0x00, KEY_F15) | ||
| 86 | MATRIX_KEY(0x02, 0x01, KEY_F11) | ||
| 87 | MATRIX_KEY(0x02, 0x02, KEY_F7) | ||
| 88 | MATRIX_KEY(0x02, 0x03, KEY_F3) | ||
| 89 | MATRIX_KEY(0x03, 0x00, KEY_F16) | ||
| 90 | MATRIX_KEY(0x03, 0x01, KEY_F12) | ||
| 91 | MATRIX_KEY(0x03, 0x02, KEY_F8) | ||
| 92 | MATRIX_KEY(0x03, 0x03, KEY_F4) >; | ||
| 93 | }; | ||
| 71 | }; | 94 | }; |
| 72 | }; | 95 | }; |
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi index 838513f9ddc0..d8a84295c328 100644 --- a/arch/arm/boot/dts/stih41x-b2020.dtsi +++ b/arch/arm/boot/dts/stih41x-b2020.dtsi | |||
| @@ -14,7 +14,7 @@ | |||
| 14 | }; | 14 | }; |
| 15 | 15 | ||
| 16 | chosen { | 16 | chosen { |
| 17 | bootargs = "console=ttyAS0,115200"; | 17 | bootargs = "console=ttyAS0,115200 clk_ignore_unused"; |
| 18 | linux,stdout-path = &sbc_serial1; | 18 | linux,stdout-path = &sbc_serial1; |
| 19 | }; | 19 | }; |
| 20 | 20 | ||
diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi index f5b9898d9c6e..5cb0e63376b5 100644 --- a/arch/arm/boot/dts/stih41x.dtsi +++ b/arch/arm/boot/dts/stih41x.dtsi | |||
| @@ -1,3 +1,10 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 STMicroelectronics Limited. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * publishhed by the Free Software Foundation. | ||
| 7 | */ | ||
| 1 | / { | 8 | / { |
| 2 | #address-cells = <1>; | 9 | #address-cells = <1>; |
| 3 | #size-cells = <1>; | 10 | #size-cells = <1>; |
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index fa746aea5e66..0b97c071dd56 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts | |||
| @@ -36,6 +36,16 @@ | |||
| 36 | }; | 36 | }; |
| 37 | }; | 37 | }; |
| 38 | 38 | ||
| 39 | mmc0: mmc@01c0f000 { | ||
| 40 | pinctrl-names = "default"; | ||
| 41 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; | ||
| 42 | vmmc-supply = <®_vcc3v3>; | ||
| 43 | bus-width = <4>; | ||
| 44 | cd-gpios = <&pio 7 1 0>; /* PH1 */ | ||
| 45 | cd-inverted; | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
| 48 | |||
| 39 | usbphy: phy@01c13400 { | 49 | usbphy: phy@01c13400 { |
| 40 | usb1_vbus-supply = <®_usb1_vbus>; | 50 | usb1_vbus-supply = <®_usb1_vbus>; |
| 41 | usb2_vbus-supply = <®_usb2_vbus>; | 51 | usb2_vbus-supply = <®_usb2_vbus>; |
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 4684cbe6843b..c200eacc66e8 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts | |||
| @@ -34,6 +34,16 @@ | |||
| 34 | }; | 34 | }; |
| 35 | }; | 35 | }; |
| 36 | 36 | ||
| 37 | mmc0: mmc@01c0f000 { | ||
| 38 | pinctrl-names = "default"; | ||
| 39 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; | ||
| 40 | vmmc-supply = <®_vcc3v3>; | ||
| 41 | bus-width = <4>; | ||
| 42 | cd-gpios = <&pio 7 1 0>; /* PH1 */ | ||
| 43 | cd-inverted; | ||
| 44 | status = "okay"; | ||
| 45 | }; | ||
| 46 | |||
| 37 | usbphy: phy@01c13400 { | 47 | usbphy: phy@01c13400 { |
| 38 | usb1_vbus-supply = <®_usb1_vbus>; | 48 | usb1_vbus-supply = <®_usb1_vbus>; |
| 39 | usb2_vbus-supply = <®_usb2_vbus>; | 49 | usb2_vbus-supply = <®_usb2_vbus>; |
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index d7c17e46ce23..547fadcb984b 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts | |||
| @@ -36,6 +36,16 @@ | |||
| 36 | }; | 36 | }; |
| 37 | }; | 37 | }; |
| 38 | 38 | ||
| 39 | mmc0: mmc@01c0f000 { | ||
| 40 | pinctrl-names = "default"; | ||
| 41 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; | ||
| 42 | vmmc-supply = <®_vcc3v3>; | ||
| 43 | bus-width = <4>; | ||
| 44 | cd-gpios = <&pio 7 1 0>; /* PH1 */ | ||
| 45 | cd-inverted; | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
| 48 | |||
| 39 | usbphy: phy@01c13400 { | 49 | usbphy: phy@01c13400 { |
| 40 | usb1_vbus-supply = <®_usb1_vbus>; | 50 | usb1_vbus-supply = <®_usb1_vbus>; |
| 41 | usb2_vbus-supply = <®_usb2_vbus>; | 51 | usb2_vbus-supply = <®_usb2_vbus>; |
diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts index fe9272ee55c3..f13723e18b86 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | |||
| @@ -24,6 +24,16 @@ | |||
| 24 | }; | 24 | }; |
| 25 | 25 | ||
| 26 | soc@01c00000 { | 26 | soc@01c00000 { |
| 27 | mmc0: mmc@01c0f000 { | ||
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; | ||
| 30 | vmmc-supply = <®_vcc3v3>; | ||
| 31 | bus-width = <4>; | ||
| 32 | cd-gpios = <&pio 7 1 0>; /* PH1 */ | ||
| 33 | cd-inverted; | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | |||
| 27 | uart0: serial@01c28000 { | 37 | uart0: serial@01c28000 { |
| 28 | pinctrl-names = "default"; | 38 | pinctrl-names = "default"; |
| 29 | pinctrl-0 = <&uart0_pins_a>; | 39 | pinctrl-0 = <&uart0_pins_a>; |
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index dd84a9e313b3..c01cea50cf0c 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | |||
| @@ -20,6 +20,16 @@ | |||
| 20 | compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; | 20 | compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; |
| 21 | 21 | ||
| 22 | soc@01c00000 { | 22 | soc@01c00000 { |
| 23 | mmc0: mmc@01c0f000 { | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; | ||
| 26 | vmmc-supply = <®_vcc3v3>; | ||
| 27 | bus-width = <4>; | ||
| 28 | cd-gpios = <&pio 7 1 0>; /* PH1 */ | ||
| 29 | cd-inverted; | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 23 | usbphy: phy@01c13400 { | 33 | usbphy: phy@01c13400 { |
| 24 | usb1_vbus-supply = <®_usb1_vbus>; | 34 | usb1_vbus-supply = <®_usb1_vbus>; |
| 25 | usb2_vbus-supply = <®_usb2_vbus>; | 35 | usb2_vbus-supply = <®_usb2_vbus>; |
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index 66cf0c7cf5b7..d46a7dbecef5 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | |||
| @@ -33,6 +33,16 @@ | |||
| 33 | }; | 33 | }; |
| 34 | }; | 34 | }; |
| 35 | 35 | ||
| 36 | mmc0: mmc@01c0f000 { | ||
| 37 | pinctrl-names = "default"; | ||
| 38 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; | ||
| 39 | vmmc-supply = <®_vcc3v3>; | ||
| 40 | bus-width = <4>; | ||
| 41 | cd-gpios = <&pio 7 1 0>; /* PH1 */ | ||
| 42 | cd-inverted; | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
| 45 | |||
| 36 | usbphy: phy@01c13400 { | 46 | usbphy: phy@01c13400 { |
| 37 | usb1_vbus-supply = <®_usb1_vbus>; | 47 | usb1_vbus-supply = <®_usb1_vbus>; |
| 38 | usb2_vbus-supply = <®_usb2_vbus>; | 48 | usb2_vbus-supply = <®_usb2_vbus>; |
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index 255b47e7019c..fb03bccb78d2 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts | |||
| @@ -34,6 +34,16 @@ | |||
| 34 | }; | 34 | }; |
| 35 | }; | 35 | }; |
| 36 | 36 | ||
| 37 | mmc0: mmc@01c0f000 { | ||
| 38 | pinctrl-names = "default"; | ||
| 39 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; | ||
| 40 | vmmc-supply = <®_vcc3v3>; | ||
| 41 | bus-width = <4>; | ||
| 42 | cd-gpios = <&pio 7 1 0>; /* PH1 */ | ||
| 43 | cd-inverted; | ||
| 44 | status = "okay"; | ||
| 45 | }; | ||
| 46 | |||
| 37 | usbphy: phy@01c13400 { | 47 | usbphy: phy@01c13400 { |
| 38 | usb1_vbus-supply = <®_usb1_vbus>; | 48 | usb1_vbus-supply = <®_usb1_vbus>; |
| 39 | usb2_vbus-supply = <®_usb2_vbus>; | 49 | usb2_vbus-supply = <®_usb2_vbus>; |
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 9174724571e2..d96e179490ce 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi | |||
| @@ -377,6 +377,42 @@ | |||
| 377 | #size-cells = <0>; | 377 | #size-cells = <0>; |
| 378 | }; | 378 | }; |
| 379 | 379 | ||
| 380 | mmc0: mmc@01c0f000 { | ||
| 381 | compatible = "allwinner,sun4i-a10-mmc"; | ||
| 382 | reg = <0x01c0f000 0x1000>; | ||
| 383 | clocks = <&ahb_gates 8>, <&mmc0_clk>; | ||
| 384 | clock-names = "ahb", "mmc"; | ||
| 385 | interrupts = <32>; | ||
| 386 | status = "disabled"; | ||
| 387 | }; | ||
| 388 | |||
| 389 | mmc1: mmc@01c10000 { | ||
| 390 | compatible = "allwinner,sun4i-a10-mmc"; | ||
| 391 | reg = <0x01c10000 0x1000>; | ||
| 392 | clocks = <&ahb_gates 9>, <&mmc1_clk>; | ||
| 393 | clock-names = "ahb", "mmc"; | ||
| 394 | interrupts = <33>; | ||
| 395 | status = "disabled"; | ||
| 396 | }; | ||
| 397 | |||
| 398 | mmc2: mmc@01c11000 { | ||
| 399 | compatible = "allwinner,sun4i-a10-mmc"; | ||
| 400 | reg = <0x01c11000 0x1000>; | ||
| 401 | clocks = <&ahb_gates 10>, <&mmc2_clk>; | ||
| 402 | clock-names = "ahb", "mmc"; | ||
| 403 | interrupts = <34>; | ||
| 404 | status = "disabled"; | ||
| 405 | }; | ||
| 406 | |||
| 407 | mmc3: mmc@01c12000 { | ||
| 408 | compatible = "allwinner,sun4i-a10-mmc"; | ||
| 409 | reg = <0x01c12000 0x1000>; | ||
| 410 | clocks = <&ahb_gates 11>, <&mmc3_clk>; | ||
| 411 | clock-names = "ahb", "mmc"; | ||
| 412 | interrupts = <35>; | ||
| 413 | status = "disabled"; | ||
| 414 | }; | ||
| 415 | |||
| 380 | usbphy: phy@01c13400 { | 416 | usbphy: phy@01c13400 { |
| 381 | #phy-cells = <1>; | 417 | #phy-cells = <1>; |
| 382 | compatible = "allwinner,sun4i-a10-usb-phy"; | 418 | compatible = "allwinner,sun4i-a10-usb-phy"; |
| @@ -477,6 +513,20 @@ | |||
| 477 | #size-cells = <0>; | 513 | #size-cells = <0>; |
| 478 | #gpio-cells = <3>; | 514 | #gpio-cells = <3>; |
| 479 | 515 | ||
| 516 | pwm0_pins_a: pwm0@0 { | ||
| 517 | allwinner,pins = "PB2"; | ||
| 518 | allwinner,function = "pwm"; | ||
| 519 | allwinner,drive = <0>; | ||
| 520 | allwinner,pull = <0>; | ||
| 521 | }; | ||
| 522 | |||
| 523 | pwm1_pins_a: pwm1@0 { | ||
| 524 | allwinner,pins = "PI3"; | ||
| 525 | allwinner,function = "pwm"; | ||
| 526 | allwinner,drive = <0>; | ||
| 527 | allwinner,pull = <0>; | ||
| 528 | }; | ||
| 529 | |||
| 480 | uart0_pins_a: uart0@0 { | 530 | uart0_pins_a: uart0@0 { |
| 481 | allwinner,pins = "PB22", "PB23"; | 531 | allwinner,pins = "PB22", "PB23"; |
| 482 | allwinner,function = "uart0"; | 532 | allwinner,function = "uart0"; |
| @@ -529,6 +579,20 @@ | |||
| 529 | allwinner,drive = <0>; | 579 | allwinner,drive = <0>; |
| 530 | allwinner,pull = <0>; | 580 | allwinner,pull = <0>; |
| 531 | }; | 581 | }; |
| 582 | |||
| 583 | mmc0_pins_a: mmc0@0 { | ||
| 584 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | ||
| 585 | allwinner,function = "mmc0"; | ||
| 586 | allwinner,drive = <2>; | ||
| 587 | allwinner,pull = <0>; | ||
| 588 | }; | ||
| 589 | |||
| 590 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | ||
| 591 | allwinner,pins = "PH1"; | ||
| 592 | allwinner,function = "gpio_in"; | ||
| 593 | allwinner,drive = <0>; | ||
| 594 | allwinner,pull = <1>; | ||
| 595 | }; | ||
| 532 | }; | 596 | }; |
| 533 | 597 | ||
| 534 | timer@01c20c00 { | 598 | timer@01c20c00 { |
| @@ -549,6 +613,14 @@ | |||
| 549 | interrupts = <24>; | 613 | interrupts = <24>; |
| 550 | }; | 614 | }; |
| 551 | 615 | ||
| 616 | pwm: pwm@01c20e00 { | ||
| 617 | compatible = "allwinner,sun4i-a10-pwm"; | ||
| 618 | reg = <0x01c20e00 0xc>; | ||
| 619 | clocks = <&osc24M>; | ||
| 620 | #pwm-cells = <3>; | ||
| 621 | status = "disabled"; | ||
| 622 | }; | ||
| 623 | |||
| 552 | sid: eeprom@01c23800 { | 624 | sid: eeprom@01c23800 { |
| 553 | compatible = "allwinner,sun4i-a10-sid"; | 625 | compatible = "allwinner,sun4i-a10-sid"; |
| 554 | reg = <0x01c23800 0x10>; | 626 | reg = <0x01c23800 0x10>; |
| @@ -641,30 +713,36 @@ | |||
| 641 | }; | 713 | }; |
| 642 | 714 | ||
| 643 | i2c0: i2c@01c2ac00 { | 715 | i2c0: i2c@01c2ac00 { |
| 644 | compatible = "allwinner,sun4i-i2c"; | 716 | compatible = "allwinner,sun4i-a10-i2c"; |
| 645 | reg = <0x01c2ac00 0x400>; | 717 | reg = <0x01c2ac00 0x400>; |
| 646 | interrupts = <7>; | 718 | interrupts = <7>; |
| 647 | clocks = <&apb1_gates 0>; | 719 | clocks = <&apb1_gates 0>; |
| 648 | clock-frequency = <100000>; | 720 | clock-frequency = <100000>; |
| 649 | status = "disabled"; | 721 | status = "disabled"; |
| 722 | #address-cells = <1>; | ||
| 723 | #size-cells = <0>; | ||
| 650 | }; | 724 | }; |
| 651 | 725 | ||
| 652 | i2c1: i2c@01c2b000 { | 726 | i2c1: i2c@01c2b000 { |
| 653 | compatible = "allwinner,sun4i-i2c"; | 727 | compatible = "allwinner,sun4i-a10-i2c"; |
| 654 | reg = <0x01c2b000 0x400>; | 728 | reg = <0x01c2b000 0x400>; |
| 655 | interrupts = <8>; | 729 | interrupts = <8>; |
| 656 | clocks = <&apb1_gates 1>; | 730 | clocks = <&apb1_gates 1>; |
| 657 | clock-frequency = <100000>; | 731 | clock-frequency = <100000>; |
| 658 | status = "disabled"; | 732 | status = "disabled"; |
| 733 | #address-cells = <1>; | ||
| 734 | #size-cells = <0>; | ||
| 659 | }; | 735 | }; |
| 660 | 736 | ||
| 661 | i2c2: i2c@01c2b400 { | 737 | i2c2: i2c@01c2b400 { |
| 662 | compatible = "allwinner,sun4i-i2c"; | 738 | compatible = "allwinner,sun4i-a10-i2c"; |
| 663 | reg = <0x01c2b400 0x400>; | 739 | reg = <0x01c2b400 0x400>; |
| 664 | interrupts = <9>; | 740 | interrupts = <9>; |
| 665 | clocks = <&apb1_gates 2>; | 741 | clocks = <&apb1_gates 2>; |
| 666 | clock-frequency = <100000>; | 742 | clock-frequency = <100000>; |
| 667 | status = "disabled"; | 743 | status = "disabled"; |
| 744 | #address-cells = <1>; | ||
| 745 | #size-cells = <0>; | ||
| 668 | }; | 746 | }; |
| 669 | }; | 747 | }; |
| 670 | }; | 748 | }; |
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index 23611b71d3aa..ea9519da5764 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | |||
| @@ -35,6 +35,26 @@ | |||
| 35 | }; | 35 | }; |
| 36 | }; | 36 | }; |
| 37 | 37 | ||
| 38 | mmc0: mmc@01c0f000 { | ||
| 39 | pinctrl-names = "default"; | ||
| 40 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>; | ||
| 41 | vmmc-supply = <®_vcc3v3>; | ||
| 42 | bus-width = <4>; | ||
| 43 | cd-gpios = <&pio 6 1 0>; /* PG1 */ | ||
| 44 | cd-inverted; | ||
| 45 | status = "okay"; | ||
| 46 | }; | ||
| 47 | |||
| 48 | mmc1: mmc@01c10000 { | ||
| 49 | pinctrl-names = "default"; | ||
| 50 | pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>; | ||
| 51 | vmmc-supply = <®_vcc3v3>; | ||
| 52 | bus-width = <4>; | ||
| 53 | cd-gpios = <&pio 6 13 0>; /* PG13 */ | ||
| 54 | cd-inverted; | ||
| 55 | status = "okay"; | ||
| 56 | }; | ||
| 57 | |||
| 38 | usbphy: phy@01c13400 { | 58 | usbphy: phy@01c13400 { |
| 39 | usb1_vbus-supply = <®_usb1_vbus>; | 59 | usb1_vbus-supply = <®_usb1_vbus>; |
| 40 | status = "okay"; | 60 | status = "okay"; |
| @@ -49,6 +69,20 @@ | |||
| 49 | }; | 69 | }; |
| 50 | 70 | ||
| 51 | pinctrl@01c20800 { | 71 | pinctrl@01c20800 { |
| 72 | mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 { | ||
| 73 | allwinner,pins = "PG1"; | ||
| 74 | allwinner,function = "gpio_in"; | ||
| 75 | allwinner,drive = <0>; | ||
| 76 | allwinner,pull = <1>; | ||
| 77 | }; | ||
| 78 | |||
| 79 | mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 { | ||
| 80 | allwinner,pins = "PG13"; | ||
| 81 | allwinner,function = "gpio_in"; | ||
| 82 | allwinner,drive = <0>; | ||
| 83 | allwinner,pull = <1>; | ||
| 84 | }; | ||
| 85 | |||
| 52 | led_pins_olinuxino: led_pins@0 { | 86 | led_pins_olinuxino: led_pins@0 { |
| 53 | allwinner,pins = "PE3"; | 87 | allwinner,pins = "PE3"; |
| 54 | allwinner,function = "gpio_out"; | 88 | allwinner,function = "gpio_out"; |
diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts new file mode 100644 index 000000000000..43a93762d4f2 --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts | |||
| @@ -0,0 +1,100 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2014 Hans de Goede <hdegoede@redhat.com> | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | /include/ "sun5i-a10s.dtsi" | ||
| 14 | /include/ "sunxi-common-regulators.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "R7 A10s hdmi tv-stick"; | ||
| 18 | compatible = "allwinner,r7-tv-dongle", "allwinner,sun5i-a10s"; | ||
| 19 | |||
| 20 | soc@01c00000 { | ||
| 21 | mmc0: mmc@01c0f000 { | ||
| 22 | pinctrl-names = "default"; | ||
| 23 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>; | ||
| 24 | vmmc-supply = <®_vcc3v3>; | ||
| 25 | bus-width = <4>; | ||
| 26 | cd-gpios = <&pio 6 1 0>; /* PG1 */ | ||
| 27 | cd-inverted; | ||
| 28 | status = "okay"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | mmc1: mmc@01c10000 { | ||
| 32 | pinctrl-names = "default"; | ||
| 33 | pinctrl-0 = <&mmc1_pins_a>; | ||
| 34 | vmmc-supply = <®_vcc3v3>; | ||
| 35 | bus-width = <4>; | ||
| 36 | non-removable; | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | |||
| 40 | usbphy: phy@01c13400 { | ||
| 41 | usb1_vbus-supply = <®_usb1_vbus>; | ||
| 42 | status = "okay"; | ||
| 43 | }; | ||
| 44 | |||
| 45 | ehci0: usb@01c14000 { | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
| 48 | |||
| 49 | ohci0: usb@01c14400 { | ||
| 50 | status = "okay"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | pinctrl@01c20800 { | ||
| 54 | mmc0_cd_pin_r7: mmc0_cd_pin@0 { | ||
| 55 | allwinner,pins = "PG1"; | ||
| 56 | allwinner,function = "gpio_in"; | ||
| 57 | allwinner,drive = <0>; | ||
| 58 | allwinner,pull = <1>; | ||
| 59 | }; | ||
| 60 | |||
| 61 | led_pins_r7: led_pins@0 { | ||
| 62 | allwinner,pins = "PB2"; | ||
| 63 | allwinner,function = "gpio_out"; | ||
| 64 | allwinner,drive = <1>; | ||
| 65 | allwinner,pull = <0>; | ||
| 66 | }; | ||
| 67 | |||
| 68 | usb1_vbus_pin_r7: usb1_vbus_pin@0 { | ||
| 69 | allwinner,pins = "PG13"; | ||
| 70 | allwinner,function = "gpio_out"; | ||
| 71 | allwinner,drive = <0>; | ||
| 72 | allwinner,pull = <0>; | ||
| 73 | }; | ||
| 74 | }; | ||
| 75 | |||
| 76 | uart0: serial@01c28000 { | ||
| 77 | pinctrl-names = "default"; | ||
| 78 | pinctrl-0 = <&uart0_pins_a>; | ||
| 79 | status = "okay"; | ||
| 80 | }; | ||
| 81 | }; | ||
| 82 | |||
| 83 | leds { | ||
| 84 | compatible = "gpio-leds"; | ||
| 85 | pinctrl-names = "default"; | ||
| 86 | pinctrl-0 = <&led_pins_r7>; | ||
| 87 | |||
| 88 | green { | ||
| 89 | label = "r7-tv-dongle:green:usr"; | ||
| 90 | gpios = <&pio 1 2 0>; | ||
| 91 | default-state = "on"; | ||
| 92 | }; | ||
| 93 | }; | ||
| 94 | |||
| 95 | reg_usb1_vbus: usb1-vbus { | ||
| 96 | pinctrl-0 = <&usb1_vbus_pin_r7>; | ||
| 97 | gpio = <&pio 6 13 0>; | ||
| 98 | status = "okay"; | ||
| 99 | }; | ||
| 100 | }; | ||
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 79989ed5658d..b64f705d9008 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi | |||
| @@ -338,6 +338,33 @@ | |||
| 338 | #size-cells = <0>; | 338 | #size-cells = <0>; |
| 339 | }; | 339 | }; |
| 340 | 340 | ||
| 341 | mmc0: mmc@01c0f000 { | ||
| 342 | compatible = "allwinner,sun5i-a13-mmc"; | ||
| 343 | reg = <0x01c0f000 0x1000>; | ||
| 344 | clocks = <&ahb_gates 8>, <&mmc0_clk>; | ||
| 345 | clock-names = "ahb", "mmc"; | ||
| 346 | interrupts = <32>; | ||
| 347 | status = "disabled"; | ||
| 348 | }; | ||
| 349 | |||
| 350 | mmc1: mmc@01c10000 { | ||
| 351 | compatible = "allwinner,sun5i-a13-mmc"; | ||
| 352 | reg = <0x01c10000 0x1000>; | ||
| 353 | clocks = <&ahb_gates 9>, <&mmc1_clk>; | ||
| 354 | clock-names = "ahb", "mmc"; | ||
| 355 | interrupts = <33>; | ||
| 356 | status = "disabled"; | ||
| 357 | }; | ||
| 358 | |||
| 359 | mmc2: mmc@01c11000 { | ||
| 360 | compatible = "allwinner,sun5i-a13-mmc"; | ||
| 361 | reg = <0x01c11000 0x1000>; | ||
| 362 | clocks = <&ahb_gates 10>, <&mmc2_clk>; | ||
| 363 | clock-names = "ahb", "mmc"; | ||
| 364 | interrupts = <34>; | ||
| 365 | status = "disabled"; | ||
| 366 | }; | ||
| 367 | |||
| 341 | usbphy: phy@01c13400 { | 368 | usbphy: phy@01c13400 { |
| 342 | #phy-cells = <1>; | 369 | #phy-cells = <1>; |
| 343 | compatible = "allwinner,sun5i-a13-usb-phy"; | 370 | compatible = "allwinner,sun5i-a13-usb-phy"; |
| @@ -451,6 +478,20 @@ | |||
| 451 | allwinner,drive = <0>; | 478 | allwinner,drive = <0>; |
| 452 | allwinner,pull = <0>; | 479 | allwinner,pull = <0>; |
| 453 | }; | 480 | }; |
| 481 | |||
| 482 | mmc0_pins_a: mmc0@0 { | ||
| 483 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | ||
| 484 | allwinner,function = "mmc0"; | ||
| 485 | allwinner,drive = <2>; | ||
| 486 | allwinner,pull = <0>; | ||
| 487 | }; | ||
| 488 | |||
| 489 | mmc1_pins_a: mmc1@0 { | ||
| 490 | allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8"; | ||
| 491 | allwinner,function = "mmc1"; | ||
| 492 | allwinner,drive = <2>; | ||
| 493 | allwinner,pull = <0>; | ||
| 494 | }; | ||
| 454 | }; | 495 | }; |
| 455 | 496 | ||
| 456 | timer@01c20c00 { | 497 | timer@01c20c00 { |
| @@ -519,7 +560,7 @@ | |||
| 519 | i2c0: i2c@01c2ac00 { | 560 | i2c0: i2c@01c2ac00 { |
| 520 | #address-cells = <1>; | 561 | #address-cells = <1>; |
| 521 | #size-cells = <0>; | 562 | #size-cells = <0>; |
| 522 | compatible = "allwinner,sun4i-i2c"; | 563 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
| 523 | reg = <0x01c2ac00 0x400>; | 564 | reg = <0x01c2ac00 0x400>; |
| 524 | interrupts = <7>; | 565 | interrupts = <7>; |
| 525 | clocks = <&apb1_gates 0>; | 566 | clocks = <&apb1_gates 0>; |
| @@ -530,7 +571,7 @@ | |||
| 530 | i2c1: i2c@01c2b000 { | 571 | i2c1: i2c@01c2b000 { |
| 531 | #address-cells = <1>; | 572 | #address-cells = <1>; |
| 532 | #size-cells = <0>; | 573 | #size-cells = <0>; |
| 533 | compatible = "allwinner,sun4i-i2c"; | 574 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
| 534 | reg = <0x01c2b000 0x400>; | 575 | reg = <0x01c2b000 0x400>; |
| 535 | interrupts = <8>; | 576 | interrupts = <8>; |
| 536 | clocks = <&apb1_gates 1>; | 577 | clocks = <&apb1_gates 1>; |
| @@ -541,7 +582,7 @@ | |||
| 541 | i2c2: i2c@01c2b400 { | 582 | i2c2: i2c@01c2b400 { |
| 542 | #address-cells = <1>; | 583 | #address-cells = <1>; |
| 543 | #size-cells = <0>; | 584 | #size-cells = <0>; |
| 544 | compatible = "allwinner,sun4i-i2c"; | 585 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
| 545 | reg = <0x01c2b400 0x400>; | 586 | reg = <0x01c2b400 0x400>; |
| 546 | interrupts = <9>; | 587 | interrupts = <9>; |
| 547 | clocks = <&apb1_gates 2>; | 588 | clocks = <&apb1_gates 2>; |
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index 11169d5b5b86..fa44b026483b 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | |||
| @@ -21,6 +21,16 @@ | |||
| 21 | compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; | 21 | compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; |
| 22 | 22 | ||
| 23 | soc@01c00000 { | 23 | soc@01c00000 { |
| 24 | mmc0: mmc@01c0f000 { | ||
| 25 | pinctrl-names = "default"; | ||
| 26 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>; | ||
| 27 | vmmc-supply = <®_vcc3v3>; | ||
| 28 | bus-width = <4>; | ||
| 29 | cd-gpios = <&pio 6 0 0>; /* PG0 */ | ||
| 30 | cd-inverted; | ||
| 31 | status = "okay"; | ||
| 32 | }; | ||
| 33 | |||
| 24 | usbphy: phy@01c13400 { | 34 | usbphy: phy@01c13400 { |
| 25 | usb1_vbus-supply = <®_usb1_vbus>; | 35 | usb1_vbus-supply = <®_usb1_vbus>; |
| 26 | status = "okay"; | 36 | status = "okay"; |
| @@ -35,6 +45,13 @@ | |||
| 35 | }; | 45 | }; |
| 36 | 46 | ||
| 37 | pinctrl@01c20800 { | 47 | pinctrl@01c20800 { |
| 48 | mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 { | ||
| 49 | allwinner,pins = "PG0"; | ||
| 50 | allwinner,function = "gpio_in"; | ||
| 51 | allwinner,drive = <0>; | ||
| 52 | allwinner,pull = <1>; | ||
| 53 | }; | ||
| 54 | |||
| 38 | led_pins_olinuxinom: led_pins@0 { | 55 | led_pins_olinuxinom: led_pins@0 { |
| 39 | allwinner,pins = "PG9"; | 56 | allwinner,pins = "PG9"; |
| 40 | allwinner,function = "gpio_out"; | 57 | allwinner,function = "gpio_out"; |
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 7a9187bbeb28..429994e1943e 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts | |||
| @@ -20,6 +20,16 @@ | |||
| 20 | compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; | 20 | compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; |
| 21 | 21 | ||
| 22 | soc@01c00000 { | 22 | soc@01c00000 { |
| 23 | mmc0: mmc@01c0f000 { | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; | ||
| 26 | vmmc-supply = <®_vcc3v3>; | ||
| 27 | bus-width = <4>; | ||
| 28 | cd-gpios = <&pio 6 0 0>; /* PG0 */ | ||
| 29 | cd-inverted; | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 23 | usbphy: phy@01c13400 { | 33 | usbphy: phy@01c13400 { |
| 24 | usb1_vbus-supply = <®_usb1_vbus>; | 34 | usb1_vbus-supply = <®_usb1_vbus>; |
| 25 | status = "okay"; | 35 | status = "okay"; |
| @@ -34,6 +44,13 @@ | |||
| 34 | }; | 44 | }; |
| 35 | 45 | ||
| 36 | pinctrl@01c20800 { | 46 | pinctrl@01c20800 { |
| 47 | mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { | ||
| 48 | allwinner,pins = "PG0"; | ||
| 49 | allwinner,function = "gpio_in"; | ||
| 50 | allwinner,drive = <0>; | ||
| 51 | allwinner,pull = <1>; | ||
| 52 | }; | ||
| 53 | |||
| 37 | led_pins_olinuxino: led_pins@0 { | 54 | led_pins_olinuxino: led_pins@0 { |
| 38 | allwinner,pins = "PG9"; | 55 | allwinner,pins = "PG9"; |
| 39 | allwinner,function = "gpio_out"; | 56 | allwinner,function = "gpio_out"; |
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index f01c315bdc4b..3b2a94c40f6e 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi | |||
| @@ -320,6 +320,24 @@ | |||
| 320 | #size-cells = <0>; | 320 | #size-cells = <0>; |
| 321 | }; | 321 | }; |
| 322 | 322 | ||
| 323 | mmc0: mmc@01c0f000 { | ||
| 324 | compatible = "allwinner,sun5i-a13-mmc"; | ||
| 325 | reg = <0x01c0f000 0x1000>; | ||
| 326 | clocks = <&ahb_gates 8>, <&mmc0_clk>; | ||
| 327 | clock-names = "ahb", "mmc"; | ||
| 328 | interrupts = <32>; | ||
| 329 | status = "disabled"; | ||
| 330 | }; | ||
| 331 | |||
| 332 | mmc2: mmc@01c11000 { | ||
| 333 | compatible = "allwinner,sun5i-a13-mmc"; | ||
| 334 | reg = <0x01c11000 0x1000>; | ||
| 335 | clocks = <&ahb_gates 10>, <&mmc2_clk>; | ||
| 336 | clock-names = "ahb", "mmc"; | ||
| 337 | interrupts = <34>; | ||
| 338 | status = "disabled"; | ||
| 339 | }; | ||
| 340 | |||
| 323 | usbphy: phy@01c13400 { | 341 | usbphy: phy@01c13400 { |
| 324 | #phy-cells = <1>; | 342 | #phy-cells = <1>; |
| 325 | compatible = "allwinner,sun5i-a13-usb-phy"; | 343 | compatible = "allwinner,sun5i-a13-usb-phy"; |
| @@ -415,6 +433,13 @@ | |||
| 415 | allwinner,drive = <0>; | 433 | allwinner,drive = <0>; |
| 416 | allwinner,pull = <0>; | 434 | allwinner,pull = <0>; |
| 417 | }; | 435 | }; |
| 436 | |||
| 437 | mmc0_pins_a: mmc0@0 { | ||
| 438 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | ||
| 439 | allwinner,function = "mmc0"; | ||
| 440 | allwinner,drive = <2>; | ||
| 441 | allwinner,pull = <0>; | ||
| 442 | }; | ||
| 418 | }; | 443 | }; |
| 419 | 444 | ||
| 420 | timer@01c20c00 { | 445 | timer@01c20c00 { |
| @@ -461,30 +486,36 @@ | |||
| 461 | }; | 486 | }; |
| 462 | 487 | ||
| 463 | i2c0: i2c@01c2ac00 { | 488 | i2c0: i2c@01c2ac00 { |
| 464 | compatible = "allwinner,sun4i-i2c"; | 489 | compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c"; |
| 465 | reg = <0x01c2ac00 0x400>; | 490 | reg = <0x01c2ac00 0x400>; |
| 466 | interrupts = <7>; | 491 | interrupts = <7>; |
| 467 | clocks = <&apb1_gates 0>; | 492 | clocks = <&apb1_gates 0>; |
| 468 | clock-frequency = <100000>; | 493 | clock-frequency = <100000>; |
| 469 | status = "disabled"; | 494 | status = "disabled"; |
| 495 | #address-cells = <1>; | ||
| 496 | #size-cells = <0>; | ||
| 470 | }; | 497 | }; |
| 471 | 498 | ||
| 472 | i2c1: i2c@01c2b000 { | 499 | i2c1: i2c@01c2b000 { |
| 473 | compatible = "allwinner,sun4i-i2c"; | 500 | compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c"; |
| 474 | reg = <0x01c2b000 0x400>; | 501 | reg = <0x01c2b000 0x400>; |
| 475 | interrupts = <8>; | 502 | interrupts = <8>; |
| 476 | clocks = <&apb1_gates 1>; | 503 | clocks = <&apb1_gates 1>; |
| 477 | clock-frequency = <100000>; | 504 | clock-frequency = <100000>; |
| 478 | status = "disabled"; | 505 | status = "disabled"; |
| 506 | #address-cells = <1>; | ||
| 507 | #size-cells = <0>; | ||
| 479 | }; | 508 | }; |
| 480 | 509 | ||
| 481 | i2c2: i2c@01c2b400 { | 510 | i2c2: i2c@01c2b400 { |
| 482 | compatible = "allwinner,sun4i-i2c"; | 511 | compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c"; |
| 483 | reg = <0x01c2b400 0x400>; | 512 | reg = <0x01c2b400 0x400>; |
| 484 | interrupts = <9>; | 513 | interrupts = <9>; |
| 485 | clocks = <&apb1_gates 2>; | 514 | clocks = <&apb1_gates 2>; |
| 486 | clock-frequency = <100000>; | 515 | clock-frequency = <100000>; |
| 487 | status = "disabled"; | 516 | status = "disabled"; |
| 517 | #address-cells = <1>; | ||
| 518 | #size-cells = <0>; | ||
| 488 | }; | 519 | }; |
| 489 | 520 | ||
| 490 | timer@01c60000 { | 521 | timer@01c60000 { |
diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts new file mode 100644 index 000000000000..2bbf8867362b --- /dev/null +++ b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2014 Boris Brezillon | ||
| 3 | * | ||
| 4 | * Boris Brezillon <boris.brezillon@free-electrons.com> | ||
| 5 | * | ||
| 6 | * The code contained herein is licensed under the GNU General Public | ||
| 7 | * License. You may obtain a copy of the GNU General Public License | ||
| 8 | * Version 2 or later at the following locations: | ||
| 9 | * | ||
| 10 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 11 | * http://www.gnu.org/copyleft/gpl.html | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | /include/ "sun6i-a31.dtsi" | ||
| 16 | /include/ "sunxi-common-regulators.dtsi" | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "Allwinner A31 APP4 EVB1 Evaluation Board"; | ||
| 20 | compatible = "allwinner,app4-evb1", "allwinner,sun6i-a31"; | ||
| 21 | |||
| 22 | chosen { | ||
| 23 | bootargs = "earlyprintk console=ttyS0,115200"; | ||
| 24 | }; | ||
| 25 | |||
| 26 | soc@01c00000 { | ||
| 27 | pio: pinctrl@01c20800 { | ||
| 28 | usb1_vbus_pin_a: usb1_vbus_pin@0 { | ||
| 29 | allwinner,pins = "PH27"; | ||
| 30 | allwinner,function = "gpio_out"; | ||
| 31 | allwinner,drive = <0>; | ||
| 32 | allwinner,pull = <0>; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | |||
| 36 | usbphy: phy@01c19400 { | ||
| 37 | usb1_vbus-supply = <®_usb1_vbus>; | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | ehci0: usb@01c1a000 { | ||
| 42 | status = "okay"; | ||
| 43 | }; | ||
| 44 | |||
| 45 | uart0: serial@01c28000 { | ||
| 46 | pinctrl-names = "default"; | ||
| 47 | pinctrl-0 = <&uart0_pins_a>; | ||
| 48 | status = "okay"; | ||
| 49 | }; | ||
| 50 | }; | ||
| 51 | |||
| 52 | reg_usb1_vbus: usb1-vbus { | ||
| 53 | pinctrl-0 = <&usb1_vbus_pin_a>; | ||
| 54 | gpio = <&pio 7 27 0>; | ||
| 55 | status = "okay"; | ||
| 56 | }; | ||
| 57 | }; | ||
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts index 3898a7bce831..546cf6eff5c7 100644 --- a/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | 13 | ||
| 14 | /dts-v1/; | 14 | /dts-v1/; |
| 15 | /include/ "sun6i-a31.dtsi" | 15 | /include/ "sun6i-a31.dtsi" |
| 16 | /include/ "sunxi-common-regulators.dtsi" | ||
| 16 | 17 | ||
| 17 | / { | 18 | / { |
| 18 | model = "WITS A31 Colombus Evaluation Board"; | 19 | model = "WITS A31 Colombus Evaluation Board"; |
| @@ -23,6 +24,45 @@ | |||
| 23 | }; | 24 | }; |
| 24 | 25 | ||
| 25 | soc@01c00000 { | 26 | soc@01c00000 { |
| 27 | mmc0: mmc@01c0f000 { | ||
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>; | ||
| 30 | vmmc-supply = <®_vcc3v0>; | ||
| 31 | bus-width = <4>; | ||
| 32 | cd-gpios = <&pio 0 8 0>; /* PA8 */ | ||
| 33 | cd-inverted; | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | |||
| 37 | usbphy: phy@01c19400 { | ||
| 38 | usb2_vbus-supply = <®_usb2_vbus>; | ||
| 39 | status = "okay"; | ||
| 40 | }; | ||
| 41 | |||
| 42 | ehci1: usb@01c1b000 { | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | pio: pinctrl@01c20800 { | ||
| 47 | mmc0_pins_a: mmc0@0 { | ||
| 48 | allwinner,pull = <1>; | ||
| 49 | }; | ||
| 50 | |||
| 51 | mmc0_cd_pin_colombus: mmc0_cd_pin@0 { | ||
| 52 | allwinner,pins = "PA8"; | ||
| 53 | allwinner,function = "gpio_in"; | ||
| 54 | allwinner,drive = <0>; | ||
| 55 | allwinner,pull = <1>; | ||
| 56 | }; | ||
| 57 | |||
| 58 | usb2_vbus_pin_colombus: usb2_vbus_pin@0 { | ||
| 59 | allwinner,pins = "PH24"; | ||
| 60 | allwinner,function = "gpio_out"; | ||
| 61 | allwinner,drive = <0>; | ||
| 62 | allwinner,pull = <0>; | ||
| 63 | }; | ||
| 64 | }; | ||
| 65 | |||
| 26 | uart0: serial@01c28000 { | 66 | uart0: serial@01c28000 { |
| 27 | pinctrl-names = "default"; | 67 | pinctrl-names = "default"; |
| 28 | pinctrl-0 = <&uart0_pins_a>; | 68 | pinctrl-0 = <&uart0_pins_a>; |
| @@ -47,4 +87,11 @@ | |||
| 47 | status = "okay"; | 87 | status = "okay"; |
| 48 | }; | 88 | }; |
| 49 | }; | 89 | }; |
| 90 | |||
| 91 | reg_usb2_vbus: usb2-vbus { | ||
| 92 | pinctrl-names = "default"; | ||
| 93 | pinctrl-0 = <&usb2_vbus_pin_colombus>; | ||
| 94 | gpio = <&pio 7 24 0>; | ||
| 95 | status = "okay"; | ||
| 96 | }; | ||
| 50 | }; | 97 | }; |
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts new file mode 100644 index 000000000000..bc6115da5ae1 --- /dev/null +++ b/arch/arm/boot/dts/sun6i-a31-m9.dts | |||
| @@ -0,0 +1,50 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2014 Hans de Goede <hdegoede@redhat.com> | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | /include/ "sun6i-a31.dtsi" | ||
| 14 | /include/ "sunxi-common-regulators.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Mele M9 / A1000G Quad top set box"; | ||
| 18 | compatible = "mele,m9", "allwinner,sun6i-a31"; | ||
| 19 | |||
| 20 | chosen { | ||
| 21 | bootargs = "earlyprintk console=ttyS0,115200"; | ||
| 22 | }; | ||
| 23 | |||
| 24 | soc@01c00000 { | ||
| 25 | mmc0: mmc@01c0f000 { | ||
| 26 | pinctrl-names = "default"; | ||
| 27 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; | ||
| 28 | vmmc-supply = <®_vcc3v3>; | ||
| 29 | bus-width = <4>; | ||
| 30 | cd-gpios = <&pio 7 22 0>; /* PH22 */ | ||
| 31 | cd-inverted; | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | pio: pinctrl@01c20800 { | ||
| 36 | mmc0_cd_pin_m9: mmc0_cd_pin@0 { | ||
| 37 | allwinner,pins = "PH22"; | ||
| 38 | allwinner,function = "gpio_in"; | ||
| 39 | allwinner,drive = <0>; | ||
| 40 | allwinner,pull = <1>; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | |||
| 44 | uart0: serial@01c28000 { | ||
| 45 | pinctrl-names = "default"; | ||
| 46 | pinctrl-0 = <&uart0_pins_a>; | ||
| 47 | status = "okay"; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | }; | ||
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index d45efa74827c..a9dfa12eb735 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | 27 | ||
| 28 | 28 | ||
| 29 | cpus { | 29 | cpus { |
| 30 | enable-method = "allwinner,sun6i-a31"; | ||
| 30 | #address-cells = <1>; | 31 | #address-cells = <1>; |
| 31 | #size-cells = <0>; | 32 | #size-cells = <0>; |
| 32 | 33 | ||
| @@ -59,6 +60,14 @@ | |||
| 59 | reg = <0x40000000 0x80000000>; | 60 | reg = <0x40000000 0x80000000>; |
| 60 | }; | 61 | }; |
| 61 | 62 | ||
| 63 | pmu { | ||
| 64 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; | ||
| 65 | interrupts = <0 120 4>, | ||
| 66 | <0 121 4>, | ||
| 67 | <0 122 4>, | ||
| 68 | <0 123 4>; | ||
| 69 | }; | ||
| 70 | |||
| 62 | clocks { | 71 | clocks { |
| 63 | #address-cells = <1>; | 72 | #address-cells = <1>; |
| 64 | #size-cells = <1>; | 73 | #size-cells = <1>; |
| @@ -198,6 +207,38 @@ | |||
| 198 | "apb2_uart4", "apb2_uart5"; | 207 | "apb2_uart4", "apb2_uart5"; |
| 199 | }; | 208 | }; |
| 200 | 209 | ||
| 210 | mmc0_clk: clk@01c20088 { | ||
| 211 | #clock-cells = <0>; | ||
| 212 | compatible = "allwinner,sun4i-a10-mod0-clk"; | ||
| 213 | reg = <0x01c20088 0x4>; | ||
| 214 | clocks = <&osc24M>, <&pll6>; | ||
| 215 | clock-output-names = "mmc0"; | ||
| 216 | }; | ||
| 217 | |||
| 218 | mmc1_clk: clk@01c2008c { | ||
| 219 | #clock-cells = <0>; | ||
| 220 | compatible = "allwinner,sun4i-a10-mod0-clk"; | ||
| 221 | reg = <0x01c2008c 0x4>; | ||
| 222 | clocks = <&osc24M>, <&pll6>; | ||
| 223 | clock-output-names = "mmc1"; | ||
| 224 | }; | ||
| 225 | |||
| 226 | mmc2_clk: clk@01c20090 { | ||
| 227 | #clock-cells = <0>; | ||
| 228 | compatible = "allwinner,sun4i-a10-mod0-clk"; | ||
| 229 | reg = <0x01c20090 0x4>; | ||
| 230 | clocks = <&osc24M>, <&pll6>; | ||
| 231 | clock-output-names = "mmc2"; | ||
| 232 | }; | ||
| 233 | |||
| 234 | mmc3_clk: clk@01c20094 { | ||
| 235 | #clock-cells = <0>; | ||
| 236 | compatible = "allwinner,sun4i-a10-mod0-clk"; | ||
| 237 | reg = <0x01c20094 0x4>; | ||
| 238 | clocks = <&osc24M>, <&pll6>; | ||
| 239 | clock-output-names = "mmc3"; | ||
| 240 | }; | ||
| 241 | |||
| 201 | spi0_clk: clk@01c200a0 { | 242 | spi0_clk: clk@01c200a0 { |
| 202 | #clock-cells = <0>; | 243 | #clock-cells = <0>; |
| 203 | compatible = "allwinner,sun4i-a10-mod0-clk"; | 244 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| @@ -229,6 +270,17 @@ | |||
| 229 | clocks = <&osc24M>, <&pll6>; | 270 | clocks = <&osc24M>, <&pll6>; |
| 230 | clock-output-names = "spi3"; | 271 | clock-output-names = "spi3"; |
| 231 | }; | 272 | }; |
| 273 | |||
| 274 | usb_clk: clk@01c200cc { | ||
| 275 | #clock-cells = <1>; | ||
| 276 | #reset-cells = <1>; | ||
| 277 | compatible = "allwinner,sun6i-a31-usb-clk"; | ||
| 278 | reg = <0x01c200cc 0x4>; | ||
| 279 | clocks = <&osc24M>; | ||
| 280 | clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", | ||
| 281 | "usb_ohci0", "usb_ohci1", | ||
| 282 | "usb_ohci2"; | ||
| 283 | }; | ||
| 232 | }; | 284 | }; |
| 233 | 285 | ||
| 234 | soc@01c00000 { | 286 | soc@01c00000 { |
| @@ -237,12 +289,134 @@ | |||
| 237 | #size-cells = <1>; | 289 | #size-cells = <1>; |
| 238 | ranges; | 290 | ranges; |
| 239 | 291 | ||
| 240 | nmi_intc: interrupt-controller@01f00c0c { | 292 | dma: dma-controller@01c02000 { |
| 241 | compatible = "allwinner,sun6i-a31-sc-nmi"; | 293 | compatible = "allwinner,sun6i-a31-dma"; |
| 242 | interrupt-controller; | 294 | reg = <0x01c02000 0x1000>; |
| 243 | #interrupt-cells = <2>; | 295 | interrupts = <0 50 4>; |
| 244 | reg = <0x01f00c0c 0x38>; | 296 | clocks = <&ahb1_gates 6>; |
| 245 | interrupts = <0 32 4>; | 297 | resets = <&ahb1_rst 6>; |
| 298 | #dma-cells = <1>; | ||
| 299 | }; | ||
| 300 | |||
| 301 | mmc0: mmc@01c0f000 { | ||
| 302 | compatible = "allwinner,sun5i-a13-mmc"; | ||
| 303 | reg = <0x01c0f000 0x1000>; | ||
| 304 | clocks = <&ahb1_gates 8>, <&mmc0_clk>; | ||
| 305 | clock-names = "ahb", "mmc"; | ||
| 306 | resets = <&ahb1_rst 8>; | ||
| 307 | reset-names = "ahb"; | ||
| 308 | interrupts = <0 60 4>; | ||
| 309 | status = "disabled"; | ||
| 310 | }; | ||
| 311 | |||
| 312 | mmc1: mmc@01c10000 { | ||
| 313 | compatible = "allwinner,sun5i-a13-mmc"; | ||
| 314 | reg = <0x01c10000 0x1000>; | ||
| 315 | clocks = <&ahb1_gates 9>, <&mmc1_clk>; | ||
| 316 | clock-names = "ahb", "mmc"; | ||
| 317 | resets = <&ahb1_rst 9>; | ||
| 318 | reset-names = "ahb"; | ||
| 319 | interrupts = <0 61 4>; | ||
| 320 | status = "disabled"; | ||
| 321 | }; | ||
| 322 | |||
| 323 | mmc2: mmc@01c11000 { | ||
| 324 | compatible = "allwinner,sun5i-a13-mmc"; | ||
| 325 | reg = <0x01c11000 0x1000>; | ||
| 326 | clocks = <&ahb1_gates 10>, <&mmc2_clk>; | ||
| 327 | clock-names = "ahb", "mmc"; | ||
| 328 | resets = <&ahb1_rst 10>; | ||
| 329 | reset-names = "ahb"; | ||
| 330 | interrupts = <0 62 4>; | ||
| 331 | status = "disabled"; | ||
| 332 | }; | ||
| 333 | |||
| 334 | mmc3: mmc@01c12000 { | ||
| 335 | compatible = "allwinner,sun5i-a13-mmc"; | ||
| 336 | reg = <0x01c12000 0x1000>; | ||
| 337 | clocks = <&ahb1_gates 11>, <&mmc3_clk>; | ||
| 338 | clock-names = "ahb", "mmc"; | ||
| 339 | resets = <&ahb1_rst 11>; | ||
| 340 | reset-names = "ahb"; | ||
| 341 | interrupts = <0 63 4>; | ||
| 342 | status = "disabled"; | ||
| 343 | }; | ||
| 344 | |||
| 345 | usbphy: phy@01c19400 { | ||
| 346 | compatible = "allwinner,sun6i-a31-usb-phy"; | ||
| 347 | reg = <0x01c19400 0x10>, | ||
| 348 | <0x01c1a800 0x4>, | ||
| 349 | <0x01c1b800 0x4>; | ||
| 350 | reg-names = "phy_ctrl", | ||
| 351 | "pmu1", | ||
| 352 | "pmu2"; | ||
| 353 | clocks = <&usb_clk 8>, | ||
| 354 | <&usb_clk 9>, | ||
| 355 | <&usb_clk 10>; | ||
| 356 | clock-names = "usb0_phy", | ||
| 357 | "usb1_phy", | ||
| 358 | "usb2_phy"; | ||
| 359 | resets = <&usb_clk 0>, | ||
| 360 | <&usb_clk 1>, | ||
| 361 | <&usb_clk 2>; | ||
| 362 | reset-names = "usb0_reset", | ||
| 363 | "usb1_reset", | ||
| 364 | "usb2_reset"; | ||
| 365 | status = "disabled"; | ||
| 366 | #phy-cells = <1>; | ||
| 367 | }; | ||
| 368 | |||
| 369 | ehci0: usb@01c1a000 { | ||
| 370 | compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; | ||
| 371 | reg = <0x01c1a000 0x100>; | ||
| 372 | interrupts = <0 72 4>; | ||
| 373 | clocks = <&ahb1_gates 26>; | ||
| 374 | resets = <&ahb1_rst 26>; | ||
| 375 | phys = <&usbphy 1>; | ||
| 376 | phy-names = "usb"; | ||
| 377 | status = "disabled"; | ||
| 378 | }; | ||
| 379 | |||
| 380 | ohci0: usb@01c1a400 { | ||
| 381 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; | ||
| 382 | reg = <0x01c1a400 0x100>; | ||
| 383 | interrupts = <0 73 4>; | ||
| 384 | clocks = <&ahb1_gates 29>, <&usb_clk 16>; | ||
| 385 | resets = <&ahb1_rst 29>; | ||
| 386 | phys = <&usbphy 1>; | ||
| 387 | phy-names = "usb"; | ||
| 388 | status = "disabled"; | ||
| 389 | }; | ||
| 390 | |||
| 391 | ehci1: usb@01c1b000 { | ||
| 392 | compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; | ||
| 393 | reg = <0x01c1b000 0x100>; | ||
| 394 | interrupts = <0 74 4>; | ||
| 395 | clocks = <&ahb1_gates 27>; | ||
| 396 | resets = <&ahb1_rst 27>; | ||
| 397 | phys = <&usbphy 2>; | ||
| 398 | phy-names = "usb"; | ||
| 399 | status = "disabled"; | ||
| 400 | }; | ||
| 401 | |||
| 402 | ohci1: usb@01c1b400 { | ||
| 403 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; | ||
| 404 | reg = <0x01c1b400 0x100>; | ||
| 405 | interrupts = <0 75 4>; | ||
| 406 | clocks = <&ahb1_gates 30>, <&usb_clk 17>; | ||
| 407 | resets = <&ahb1_rst 30>; | ||
| 408 | phys = <&usbphy 2>; | ||
| 409 | phy-names = "usb"; | ||
| 410 | status = "disabled"; | ||
| 411 | }; | ||
| 412 | |||
| 413 | ohci2: usb@01c1c400 { | ||
| 414 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; | ||
| 415 | reg = <0x01c1c400 0x100>; | ||
| 416 | interrupts = <0 77 4>; | ||
| 417 | clocks = <&ahb1_gates 31>, <&usb_clk 18>; | ||
| 418 | resets = <&ahb1_rst 31>; | ||
| 419 | status = "disabled"; | ||
| 246 | }; | 420 | }; |
| 247 | 421 | ||
| 248 | pio: pinctrl@01c20800 { | 422 | pio: pinctrl@01c20800 { |
| @@ -286,6 +460,13 @@ | |||
| 286 | allwinner,drive = <0>; | 460 | allwinner,drive = <0>; |
| 287 | allwinner,pull = <0>; | 461 | allwinner,pull = <0>; |
| 288 | }; | 462 | }; |
| 463 | |||
| 464 | mmc0_pins_a: mmc0@0 { | ||
| 465 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | ||
| 466 | allwinner,function = "mmc0"; | ||
| 467 | allwinner,drive = <2>; | ||
| 468 | allwinner,pull = <0>; | ||
| 469 | }; | ||
| 289 | }; | 470 | }; |
| 290 | 471 | ||
| 291 | ahb1_rst: reset@01c202c0 { | 472 | ahb1_rst: reset@01c202c0 { |
| @@ -330,6 +511,8 @@ | |||
| 330 | reg-io-width = <4>; | 511 | reg-io-width = <4>; |
| 331 | clocks = <&apb2_gates 16>; | 512 | clocks = <&apb2_gates 16>; |
| 332 | resets = <&apb2_rst 16>; | 513 | resets = <&apb2_rst 16>; |
| 514 | dmas = <&dma 6>, <&dma 6>; | ||
| 515 | dma-names = "rx", "tx"; | ||
| 333 | status = "disabled"; | 516 | status = "disabled"; |
| 334 | }; | 517 | }; |
| 335 | 518 | ||
| @@ -341,6 +524,8 @@ | |||
| 341 | reg-io-width = <4>; | 524 | reg-io-width = <4>; |
| 342 | clocks = <&apb2_gates 17>; | 525 | clocks = <&apb2_gates 17>; |
| 343 | resets = <&apb2_rst 17>; | 526 | resets = <&apb2_rst 17>; |
| 527 | dmas = <&dma 7>, <&dma 7>; | ||
| 528 | dma-names = "rx", "tx"; | ||
| 344 | status = "disabled"; | 529 | status = "disabled"; |
| 345 | }; | 530 | }; |
| 346 | 531 | ||
| @@ -352,6 +537,8 @@ | |||
| 352 | reg-io-width = <4>; | 537 | reg-io-width = <4>; |
| 353 | clocks = <&apb2_gates 18>; | 538 | clocks = <&apb2_gates 18>; |
| 354 | resets = <&apb2_rst 18>; | 539 | resets = <&apb2_rst 18>; |
| 540 | dmas = <&dma 8>, <&dma 8>; | ||
| 541 | dma-names = "rx", "tx"; | ||
| 355 | status = "disabled"; | 542 | status = "disabled"; |
| 356 | }; | 543 | }; |
| 357 | 544 | ||
| @@ -363,6 +550,8 @@ | |||
| 363 | reg-io-width = <4>; | 550 | reg-io-width = <4>; |
| 364 | clocks = <&apb2_gates 19>; | 551 | clocks = <&apb2_gates 19>; |
| 365 | resets = <&apb2_rst 19>; | 552 | resets = <&apb2_rst 19>; |
| 553 | dmas = <&dma 9>, <&dma 9>; | ||
| 554 | dma-names = "rx", "tx"; | ||
| 366 | status = "disabled"; | 555 | status = "disabled"; |
| 367 | }; | 556 | }; |
| 368 | 557 | ||
| @@ -374,6 +563,8 @@ | |||
| 374 | reg-io-width = <4>; | 563 | reg-io-width = <4>; |
| 375 | clocks = <&apb2_gates 20>; | 564 | clocks = <&apb2_gates 20>; |
| 376 | resets = <&apb2_rst 20>; | 565 | resets = <&apb2_rst 20>; |
| 566 | dmas = <&dma 10>, <&dma 10>; | ||
| 567 | dma-names = "rx", "tx"; | ||
| 377 | status = "disabled"; | 568 | status = "disabled"; |
| 378 | }; | 569 | }; |
| 379 | 570 | ||
| @@ -385,6 +576,8 @@ | |||
| 385 | reg-io-width = <4>; | 576 | reg-io-width = <4>; |
| 386 | clocks = <&apb2_gates 21>; | 577 | clocks = <&apb2_gates 21>; |
| 387 | resets = <&apb2_rst 21>; | 578 | resets = <&apb2_rst 21>; |
| 579 | dmas = <&dma 22>, <&dma 22>; | ||
| 580 | dma-names = "rx", "tx"; | ||
| 388 | status = "disabled"; | 581 | status = "disabled"; |
| 389 | }; | 582 | }; |
| 390 | 583 | ||
| @@ -428,12 +621,25 @@ | |||
| 428 | status = "disabled"; | 621 | status = "disabled"; |
| 429 | }; | 622 | }; |
| 430 | 623 | ||
| 624 | timer@01c60000 { | ||
| 625 | compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; | ||
| 626 | reg = <0x01c60000 0x1000>; | ||
| 627 | interrupts = <0 51 4>, | ||
| 628 | <0 52 4>, | ||
| 629 | <0 53 4>, | ||
| 630 | <0 54 4>; | ||
| 631 | clocks = <&ahb1_gates 19>; | ||
| 632 | resets = <&ahb1_rst 19>; | ||
| 633 | }; | ||
| 634 | |||
| 431 | spi0: spi@01c68000 { | 635 | spi0: spi@01c68000 { |
| 432 | compatible = "allwinner,sun6i-a31-spi"; | 636 | compatible = "allwinner,sun6i-a31-spi"; |
| 433 | reg = <0x01c68000 0x1000>; | 637 | reg = <0x01c68000 0x1000>; |
| 434 | interrupts = <0 65 4>; | 638 | interrupts = <0 65 4>; |
| 435 | clocks = <&ahb1_gates 20>, <&spi0_clk>; | 639 | clocks = <&ahb1_gates 20>, <&spi0_clk>; |
| 436 | clock-names = "ahb", "mod"; | 640 | clock-names = "ahb", "mod"; |
| 641 | dmas = <&dma 23>, <&dma 23>; | ||
| 642 | dma-names = "rx", "tx"; | ||
| 437 | resets = <&ahb1_rst 20>; | 643 | resets = <&ahb1_rst 20>; |
| 438 | status = "disabled"; | 644 | status = "disabled"; |
| 439 | }; | 645 | }; |
| @@ -444,6 +650,8 @@ | |||
| 444 | interrupts = <0 66 4>; | 650 | interrupts = <0 66 4>; |
| 445 | clocks = <&ahb1_gates 21>, <&spi1_clk>; | 651 | clocks = <&ahb1_gates 21>, <&spi1_clk>; |
| 446 | clock-names = "ahb", "mod"; | 652 | clock-names = "ahb", "mod"; |
| 653 | dmas = <&dma 24>, <&dma 24>; | ||
| 654 | dma-names = "rx", "tx"; | ||
| 447 | resets = <&ahb1_rst 21>; | 655 | resets = <&ahb1_rst 21>; |
| 448 | status = "disabled"; | 656 | status = "disabled"; |
| 449 | }; | 657 | }; |
| @@ -454,6 +662,8 @@ | |||
| 454 | interrupts = <0 67 4>; | 662 | interrupts = <0 67 4>; |
| 455 | clocks = <&ahb1_gates 22>, <&spi2_clk>; | 663 | clocks = <&ahb1_gates 22>, <&spi2_clk>; |
| 456 | clock-names = "ahb", "mod"; | 664 | clock-names = "ahb", "mod"; |
| 665 | dmas = <&dma 25>, <&dma 25>; | ||
| 666 | dma-names = "rx", "tx"; | ||
| 457 | resets = <&ahb1_rst 22>; | 667 | resets = <&ahb1_rst 22>; |
| 458 | status = "disabled"; | 668 | status = "disabled"; |
| 459 | }; | 669 | }; |
| @@ -464,6 +674,8 @@ | |||
| 464 | interrupts = <0 68 4>; | 674 | interrupts = <0 68 4>; |
| 465 | clocks = <&ahb1_gates 23>, <&spi3_clk>; | 675 | clocks = <&ahb1_gates 23>, <&spi3_clk>; |
| 466 | clock-names = "ahb", "mod"; | 676 | clock-names = "ahb", "mod"; |
| 677 | dmas = <&dma 26>, <&dma 26>; | ||
| 678 | dma-names = "rx", "tx"; | ||
| 467 | resets = <&ahb1_rst 23>; | 679 | resets = <&ahb1_rst 23>; |
| 468 | status = "disabled"; | 680 | status = "disabled"; |
| 469 | }; | 681 | }; |
| @@ -479,14 +691,74 @@ | |||
| 479 | interrupts = <1 9 0xf04>; | 691 | interrupts = <1 9 0xf04>; |
| 480 | }; | 692 | }; |
| 481 | 693 | ||
| 694 | nmi_intc: interrupt-controller@01f00c0c { | ||
| 695 | compatible = "allwinner,sun6i-a31-sc-nmi"; | ||
| 696 | interrupt-controller; | ||
| 697 | #interrupt-cells = <2>; | ||
| 698 | reg = <0x01f00c0c 0x38>; | ||
| 699 | interrupts = <0 32 4>; | ||
| 700 | }; | ||
| 701 | |||
| 702 | prcm@01f01400 { | ||
| 703 | compatible = "allwinner,sun6i-a31-prcm"; | ||
| 704 | reg = <0x01f01400 0x200>; | ||
| 705 | |||
| 706 | ar100: ar100_clk { | ||
| 707 | compatible = "allwinner,sun6i-a31-ar100-clk"; | ||
| 708 | #clock-cells = <0>; | ||
| 709 | clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; | ||
| 710 | clock-output-names = "ar100"; | ||
| 711 | }; | ||
| 712 | |||
| 713 | ahb0: ahb0_clk { | ||
| 714 | compatible = "fixed-factor-clock"; | ||
| 715 | #clock-cells = <0>; | ||
| 716 | clock-div = <1>; | ||
| 717 | clock-mult = <1>; | ||
| 718 | clocks = <&ar100>; | ||
| 719 | clock-output-names = "ahb0"; | ||
| 720 | }; | ||
| 721 | |||
| 722 | apb0: apb0_clk { | ||
| 723 | compatible = "allwinner,sun6i-a31-apb0-clk"; | ||
| 724 | #clock-cells = <0>; | ||
| 725 | clocks = <&ahb0>; | ||
| 726 | clock-output-names = "apb0"; | ||
| 727 | }; | ||
| 728 | |||
| 729 | apb0_gates: apb0_gates_clk { | ||
| 730 | compatible = "allwinner,sun6i-a31-apb0-gates-clk"; | ||
| 731 | #clock-cells = <1>; | ||
| 732 | clocks = <&apb0>; | ||
| 733 | clock-output-names = "apb0_pio", "apb0_ir", | ||
| 734 | "apb0_timer", "apb0_p2wi", | ||
| 735 | "apb0_uart", "apb0_1wire", | ||
| 736 | "apb0_i2c"; | ||
| 737 | }; | ||
| 738 | |||
| 739 | apb0_rst: apb0_rst { | ||
| 740 | compatible = "allwinner,sun6i-a31-clock-reset"; | ||
| 741 | #reset-cells = <1>; | ||
| 742 | }; | ||
| 743 | }; | ||
| 744 | |||
| 482 | cpucfg@01f01c00 { | 745 | cpucfg@01f01c00 { |
| 483 | compatible = "allwinner,sun6i-a31-cpuconfig"; | 746 | compatible = "allwinner,sun6i-a31-cpuconfig"; |
| 484 | reg = <0x01f01c00 0x300>; | 747 | reg = <0x01f01c00 0x300>; |
| 485 | }; | 748 | }; |
| 486 | 749 | ||
| 487 | prcm@01f01c00 { | 750 | r_pio: pinctrl@01f02c00 { |
| 488 | compatible = "allwinner,sun6i-a31-prcm"; | 751 | compatible = "allwinner,sun6i-a31-r-pinctrl"; |
| 489 | reg = <0x01f01400 0x200>; | 752 | reg = <0x01f02c00 0x400>; |
| 753 | interrupts = <0 45 4>, | ||
| 754 | <0 46 4>; | ||
| 755 | clocks = <&apb0_gates 0>; | ||
| 756 | resets = <&apb0_rst 0>; | ||
| 757 | gpio-controller; | ||
| 758 | interrupt-controller; | ||
| 759 | #address-cells = <1>; | ||
| 760 | #size-cells = <0>; | ||
| 761 | #gpio-cells = <3>; | ||
| 490 | }; | 762 | }; |
| 491 | }; | 763 | }; |
| 492 | }; | 764 | }; |
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 68de89ffbdfa..a5ad945197e8 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | |||
| @@ -20,6 +20,16 @@ | |||
| 20 | compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; | 20 | compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; |
| 21 | 21 | ||
| 22 | soc@01c00000 { | 22 | soc@01c00000 { |
| 23 | mmc0: mmc@01c0f000 { | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; | ||
| 26 | vmmc-supply = <®_vcc3v3>; | ||
| 27 | bus-width = <4>; | ||
| 28 | cd-gpios = <&pio 7 1 0>; /* PH1 */ | ||
| 29 | cd-inverted; | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 23 | usbphy: phy@01c13400 { | 33 | usbphy: phy@01c13400 { |
| 24 | usb1_vbus-supply = <®_usb1_vbus>; | 34 | usb1_vbus-supply = <®_usb1_vbus>; |
| 25 | usb2_vbus-supply = <®_usb2_vbus>; | 35 | usb2_vbus-supply = <®_usb2_vbus>; |
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index cb25d3c8da58..b87fea901489 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts | |||
| @@ -20,6 +20,25 @@ | |||
| 20 | compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; | 20 | compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; |
| 21 | 21 | ||
| 22 | soc@01c00000 { | 22 | soc@01c00000 { |
| 23 | mmc0: mmc@01c0f000 { | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; | ||
| 26 | vmmc-supply = <®_vcc3v3>; | ||
| 27 | bus-width = <4>; | ||
| 28 | cd-gpios = <&pio 7 1 0>; /* PH1 */ | ||
| 29 | cd-inverted; | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | mmc3: mmc@01c12000 { | ||
| 34 | pinctrl-names = "default"; | ||
| 35 | pinctrl-0 = <&mmc3_pins_a>; | ||
| 36 | vmmc-supply = <®_vmmc3>; | ||
| 37 | bus-width = <4>; | ||
| 38 | non-removable; | ||
| 39 | status = "okay"; | ||
| 40 | }; | ||
| 41 | |||
| 23 | usbphy: phy@01c13400 { | 42 | usbphy: phy@01c13400 { |
| 24 | usb1_vbus-supply = <®_usb1_vbus>; | 43 | usb1_vbus-supply = <®_usb1_vbus>; |
| 25 | usb2_vbus-supply = <®_usb2_vbus>; | 44 | usb2_vbus-supply = <®_usb2_vbus>; |
| @@ -48,6 +67,18 @@ | |||
| 48 | }; | 67 | }; |
| 49 | 68 | ||
| 50 | pinctrl@01c20800 { | 69 | pinctrl@01c20800 { |
| 70 | mmc3_pins_a: mmc3@0 { | ||
| 71 | /* AP6210 requires pull-up */ | ||
| 72 | allwinner,pull = <1>; | ||
| 73 | }; | ||
| 74 | |||
| 75 | vmmc3_pin_cubietruck: vmmc3_pin@0 { | ||
| 76 | allwinner,pins = "PH9"; | ||
| 77 | allwinner,function = "gpio_out"; | ||
| 78 | allwinner,drive = <0>; | ||
| 79 | allwinner,pull = <0>; | ||
| 80 | }; | ||
| 81 | |||
| 51 | ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { | 82 | ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { |
| 52 | allwinner,pins = "PH12"; | 83 | allwinner,pins = "PH12"; |
| 53 | allwinner,function = "gpio_out"; | 84 | allwinner,function = "gpio_out"; |
| @@ -63,6 +94,12 @@ | |||
| 63 | }; | 94 | }; |
| 64 | }; | 95 | }; |
| 65 | 96 | ||
| 97 | pwm: pwm@01c20e00 { | ||
| 98 | pinctrl-names = "default"; | ||
| 99 | pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>; | ||
| 100 | status = "okay"; | ||
| 101 | }; | ||
| 102 | |||
| 66 | uart0: serial@01c28000 { | 103 | uart0: serial@01c28000 { |
| 67 | pinctrl-names = "default"; | 104 | pinctrl-names = "default"; |
| 68 | pinctrl-0 = <&uart0_pins_a>; | 105 | pinctrl-0 = <&uart0_pins_a>; |
| @@ -139,4 +176,15 @@ | |||
| 139 | reg_usb2_vbus: usb2-vbus { | 176 | reg_usb2_vbus: usb2-vbus { |
| 140 | status = "okay"; | 177 | status = "okay"; |
| 141 | }; | 178 | }; |
| 179 | |||
| 180 | reg_vmmc3: vmmc3 { | ||
| 181 | compatible = "regulator-fixed"; | ||
| 182 | pinctrl-names = "default"; | ||
| 183 | pinctrl-0 = <&vmmc3_pin_cubietruck>; | ||
| 184 | regulator-name = "vmmc3"; | ||
| 185 | regulator-min-microvolt = <3300000>; | ||
| 186 | regulator-max-microvolt = <3300000>; | ||
| 187 | enable-active-high; | ||
| 188 | gpio = <&pio 7 9 0>; | ||
| 189 | }; | ||
| 142 | }; | 190 | }; |
diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts new file mode 100644 index 000000000000..b77308e90199 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | |||
| @@ -0,0 +1,176 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2014 Hans de Goede <hdegoede@redhat.com> | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | /include/ "sun7i-a20.dtsi" | ||
| 14 | /include/ "sunxi-common-regulators.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "I12 / Q5 / QT840A A20 tvbox"; | ||
| 18 | compatible = "allwinner,i12-tvbox", "allwinner,sun7i-a20"; | ||
| 19 | |||
| 20 | soc@01c00000 { | ||
| 21 | mmc0: mmc@01c0f000 { | ||
| 22 | pinctrl-names = "default"; | ||
| 23 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; | ||
| 24 | vmmc-supply = <®_vcc3v3>; | ||
| 25 | bus-width = <4>; | ||
| 26 | cd-gpios = <&pio 7 1 0>; /* PH1 */ | ||
| 27 | cd-inverted; | ||
| 28 | status = "okay"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | mmc3: mmc@01c12000 { | ||
| 32 | pinctrl-names = "default"; | ||
| 33 | pinctrl-0 = <&mmc3_pins_a>; | ||
| 34 | vmmc-supply = <®_vmmc3>; | ||
| 35 | bus-width = <4>; | ||
| 36 | non-removable; | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | |||
| 40 | usbphy: phy@01c13400 { | ||
| 41 | usb1_vbus-supply = <®_usb1_vbus>; | ||
| 42 | usb2_vbus-supply = <®_usb2_vbus>; | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | ehci0: usb@01c14000 { | ||
| 47 | status = "okay"; | ||
| 48 | }; | ||
| 49 | |||
| 50 | ohci0: usb@01c14400 { | ||
| 51 | status = "okay"; | ||
| 52 | }; | ||
| 53 | |||
| 54 | ehci1: usb@01c1c000 { | ||
| 55 | status = "okay"; | ||
| 56 | }; | ||
| 57 | |||
| 58 | ohci1: usb@01c1c400 { | ||
| 59 | status = "okay"; | ||
| 60 | }; | ||
| 61 | |||
| 62 | pinctrl@01c20800 { | ||
| 63 | mmc3_pins_a: mmc3@0 { | ||
| 64 | /* AP6210 / AP6330 requires pull-up */ | ||
| 65 | allwinner,pull = <1>; | ||
| 66 | }; | ||
| 67 | |||
| 68 | vmmc3_pin_i12_tvbox: vmmc3_pin@0 { | ||
| 69 | allwinner,pins = "PH2"; | ||
| 70 | allwinner,function = "gpio_out"; | ||
| 71 | allwinner,drive = <0>; | ||
| 72 | allwinner,pull = <0>; | ||
| 73 | }; | ||
| 74 | |||
| 75 | vmmc3_io_pin_i12_tvbox: vmmc3_io_pin@0 { | ||
| 76 | allwinner,pins = "PH12"; | ||
| 77 | allwinner,function = "gpio_out"; | ||
| 78 | allwinner,drive = <0>; | ||
| 79 | allwinner,pull = <0>; | ||
| 80 | }; | ||
| 81 | |||
| 82 | gmac_power_pin_i12_tvbox: gmac_power_pin@0 { | ||
| 83 | allwinner,pins = "PH21"; | ||
| 84 | allwinner,function = "gpio_out"; | ||
| 85 | allwinner,drive = <0>; | ||
| 86 | allwinner,pull = <0>; | ||
| 87 | }; | ||
| 88 | |||
| 89 | led_pins_i12_tvbox: led_pins@0 { | ||
| 90 | allwinner,pins = "PH9", "PH20"; | ||
| 91 | allwinner,function = "gpio_out"; | ||
| 92 | allwinner,drive = <0>; | ||
| 93 | allwinner,pull = <0>; | ||
| 94 | }; | ||
| 95 | }; | ||
| 96 | |||
| 97 | uart0: serial@01c28000 { | ||
| 98 | pinctrl-names = "default"; | ||
| 99 | pinctrl-0 = <&uart0_pins_a>; | ||
| 100 | status = "okay"; | ||
| 101 | }; | ||
| 102 | |||
| 103 | gmac: ethernet@01c50000 { | ||
| 104 | pinctrl-names = "default"; | ||
| 105 | pinctrl-0 = <&gmac_pins_mii_a>; | ||
| 106 | phy = <&phy1>; | ||
| 107 | phy-mode = "mii"; | ||
| 108 | phy-supply = <®_gmac_3v3>; | ||
| 109 | status = "okay"; | ||
| 110 | |||
| 111 | phy1: ethernet-phy@1 { | ||
| 112 | reg = <1>; | ||
| 113 | }; | ||
| 114 | }; | ||
| 115 | }; | ||
| 116 | |||
| 117 | leds { | ||
| 118 | compatible = "gpio-leds"; | ||
| 119 | pinctrl-names = "default"; | ||
| 120 | pinctrl-0 = <&led_pins_i12_tvbox>; | ||
| 121 | |||
| 122 | red { | ||
| 123 | label = "i12_tvbox:red:usr"; | ||
| 124 | gpios = <&pio 7 9 1>; | ||
| 125 | }; | ||
| 126 | |||
| 127 | blue { | ||
| 128 | label = "i12_tvbox:blue:usr"; | ||
| 129 | gpios = <&pio 7 20 0>; | ||
| 130 | }; | ||
| 131 | }; | ||
| 132 | |||
| 133 | reg_usb1_vbus: usb1-vbus { | ||
| 134 | status = "okay"; | ||
| 135 | }; | ||
| 136 | |||
| 137 | reg_usb2_vbus: usb2-vbus { | ||
| 138 | status = "okay"; | ||
| 139 | }; | ||
| 140 | |||
| 141 | reg_vmmc3: vmmc3 { | ||
| 142 | compatible = "regulator-fixed"; | ||
| 143 | pinctrl-names = "default"; | ||
| 144 | pinctrl-0 = <&vmmc3_pin_i12_tvbox>; | ||
| 145 | regulator-name = "vmmc3"; | ||
| 146 | regulator-min-microvolt = <3300000>; | ||
| 147 | regulator-max-microvolt = <3300000>; | ||
| 148 | enable-active-high; | ||
| 149 | gpio = <&pio 7 2 0>; | ||
| 150 | }; | ||
| 151 | |||
| 152 | reg_vmmc3_io: vmmc3-io { | ||
| 153 | compatible = "regulator-fixed"; | ||
| 154 | pinctrl-names = "default"; | ||
| 155 | pinctrl-0 = <&vmmc3_io_pin_i12_tvbox>; | ||
| 156 | regulator-name = "vmmc3-io"; | ||
| 157 | regulator-min-microvolt = <3300000>; | ||
| 158 | regulator-max-microvolt = <3300000>; | ||
| 159 | /* This controls VCC-PI, must be always on! */ | ||
| 160 | regulator-always-on; | ||
| 161 | enable-active-high; | ||
| 162 | gpio = <&pio 7 12 0>; | ||
| 163 | }; | ||
| 164 | |||
| 165 | reg_gmac_3v3: gmac-3v3 { | ||
| 166 | compatible = "regulator-fixed"; | ||
| 167 | pinctrl-names = "default"; | ||
| 168 | pinctrl-0 = <&gmac_power_pin_i12_tvbox>; | ||
| 169 | regulator-name = "gmac-3v3"; | ||
| 170 | regulator-min-microvolt = <3300000>; | ||
| 171 | regulator-max-microvolt = <3300000>; | ||
| 172 | startup-delay-us = <50000>; | ||
| 173 | enable-active-high; | ||
| 174 | gpio = <&pio 7 21 0>; | ||
| 175 | }; | ||
| 176 | }; | ||
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index eeadf76362fa..b759630bc9a9 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | |||
| @@ -31,6 +31,26 @@ | |||
| 31 | status = "okay"; | 31 | status = "okay"; |
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| 34 | mmc0: mmc@01c0f000 { | ||
| 35 | pinctrl-names = "default"; | ||
| 36 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; | ||
| 37 | vmmc-supply = <®_vcc3v3>; | ||
| 38 | bus-width = <4>; | ||
| 39 | cd-gpios = <&pio 7 1 0>; /* PH1 */ | ||
| 40 | cd-inverted; | ||
| 41 | status = "okay"; | ||
| 42 | }; | ||
| 43 | |||
| 44 | mmc3: mmc@01c12000 { | ||
| 45 | pinctrl-names = "default"; | ||
| 46 | pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>; | ||
| 47 | vmmc-supply = <®_vcc3v3>; | ||
| 48 | bus-width = <4>; | ||
| 49 | cd-gpios = <&pio 7 11 0>; /* PH11 */ | ||
| 50 | cd-inverted; | ||
| 51 | status = "okay"; | ||
| 52 | }; | ||
| 53 | |||
| 34 | usbphy: phy@01c13400 { | 54 | usbphy: phy@01c13400 { |
| 35 | usb1_vbus-supply = <®_usb1_vbus>; | 55 | usb1_vbus-supply = <®_usb1_vbus>; |
| 36 | usb2_vbus-supply = <®_usb2_vbus>; | 56 | usb2_vbus-supply = <®_usb2_vbus>; |
| @@ -65,6 +85,13 @@ | |||
| 65 | }; | 85 | }; |
| 66 | 86 | ||
| 67 | pinctrl@01c20800 { | 87 | pinctrl@01c20800 { |
| 88 | mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 { | ||
| 89 | allwinner,pins = "PH11"; | ||
| 90 | allwinner,function = "gpio_in"; | ||
| 91 | allwinner,drive = <0>; | ||
| 92 | allwinner,pull = <1>; | ||
| 93 | }; | ||
| 94 | |||
| 68 | led_pins_olinuxino: led_pins@0 { | 95 | led_pins_olinuxino: led_pins@0 { |
| 69 | allwinner,pins = "PH2"; | 96 | allwinner,pins = "PH2"; |
| 70 | allwinner,function = "gpio_out"; | 97 | allwinner,function = "gpio_out"; |
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index aba1c8a3f388..01e94664232a 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi | |||
| @@ -57,6 +57,12 @@ | |||
| 57 | <1 10 0xf08>; | 57 | <1 10 0xf08>; |
| 58 | }; | 58 | }; |
| 59 | 59 | ||
| 60 | pmu { | ||
| 61 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; | ||
| 62 | interrupts = <0 120 4>, | ||
| 63 | <0 121 4>; | ||
| 64 | }; | ||
| 65 | |||
| 60 | clocks { | 66 | clocks { |
| 61 | #address-cells = <1>; | 67 | #address-cells = <1>; |
| 62 | #size-cells = <1>; | 68 | #size-cells = <1>; |
| @@ -455,6 +461,42 @@ | |||
| 455 | #size-cells = <0>; | 461 | #size-cells = <0>; |
| 456 | }; | 462 | }; |
| 457 | 463 | ||
| 464 | mmc0: mmc@01c0f000 { | ||
| 465 | compatible = "allwinner,sun5i-a13-mmc"; | ||
| 466 | reg = <0x01c0f000 0x1000>; | ||
| 467 | clocks = <&ahb_gates 8>, <&mmc0_clk>; | ||
| 468 | clock-names = "ahb", "mmc"; | ||
| 469 | interrupts = <0 32 4>; | ||
| 470 | status = "disabled"; | ||
| 471 | }; | ||
| 472 | |||
| 473 | mmc1: mmc@01c10000 { | ||
| 474 | compatible = "allwinner,sun5i-a13-mmc"; | ||
| 475 | reg = <0x01c10000 0x1000>; | ||
| 476 | clocks = <&ahb_gates 9>, <&mmc1_clk>; | ||
| 477 | clock-names = "ahb", "mmc"; | ||
| 478 | interrupts = <0 33 4>; | ||
| 479 | status = "disabled"; | ||
| 480 | }; | ||
| 481 | |||
| 482 | mmc2: mmc@01c11000 { | ||
| 483 | compatible = "allwinner,sun5i-a13-mmc"; | ||
| 484 | reg = <0x01c11000 0x1000>; | ||
| 485 | clocks = <&ahb_gates 10>, <&mmc2_clk>; | ||
| 486 | clock-names = "ahb", "mmc"; | ||
| 487 | interrupts = <0 34 4>; | ||
| 488 | status = "disabled"; | ||
| 489 | }; | ||
| 490 | |||
| 491 | mmc3: mmc@01c12000 { | ||
| 492 | compatible = "allwinner,sun5i-a13-mmc"; | ||
| 493 | reg = <0x01c12000 0x1000>; | ||
| 494 | clocks = <&ahb_gates 11>, <&mmc3_clk>; | ||
| 495 | clock-names = "ahb", "mmc"; | ||
| 496 | interrupts = <0 35 4>; | ||
| 497 | status = "disabled"; | ||
| 498 | }; | ||
| 499 | |||
| 458 | usbphy: phy@01c13400 { | 500 | usbphy: phy@01c13400 { |
| 459 | #phy-cells = <1>; | 501 | #phy-cells = <1>; |
| 460 | compatible = "allwinner,sun7i-a20-usb-phy"; | 502 | compatible = "allwinner,sun7i-a20-usb-phy"; |
| @@ -548,6 +590,20 @@ | |||
| 548 | #size-cells = <0>; | 590 | #size-cells = <0>; |
| 549 | #gpio-cells = <3>; | 591 | #gpio-cells = <3>; |
| 550 | 592 | ||
| 593 | pwm0_pins_a: pwm0@0 { | ||
| 594 | allwinner,pins = "PB2"; | ||
| 595 | allwinner,function = "pwm"; | ||
| 596 | allwinner,drive = <0>; | ||
| 597 | allwinner,pull = <0>; | ||
| 598 | }; | ||
| 599 | |||
| 600 | pwm1_pins_a: pwm1@0 { | ||
| 601 | allwinner,pins = "PI3"; | ||
| 602 | allwinner,function = "pwm"; | ||
| 603 | allwinner,drive = <0>; | ||
| 604 | allwinner,pull = <0>; | ||
| 605 | }; | ||
| 606 | |||
| 551 | uart0_pins_a: uart0@0 { | 607 | uart0_pins_a: uart0@0 { |
| 552 | allwinner,pins = "PB22", "PB23"; | 608 | allwinner,pins = "PB22", "PB23"; |
| 553 | allwinner,function = "uart0"; | 609 | allwinner,function = "uart0"; |
| @@ -661,6 +717,27 @@ | |||
| 661 | allwinner,drive = <0>; | 717 | allwinner,drive = <0>; |
| 662 | allwinner,pull = <0>; | 718 | allwinner,pull = <0>; |
| 663 | }; | 719 | }; |
| 720 | |||
| 721 | mmc0_pins_a: mmc0@0 { | ||
| 722 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | ||
| 723 | allwinner,function = "mmc0"; | ||
| 724 | allwinner,drive = <2>; | ||
| 725 | allwinner,pull = <0>; | ||
| 726 | }; | ||
| 727 | |||
| 728 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | ||
| 729 | allwinner,pins = "PH1"; | ||
| 730 | allwinner,function = "gpio_in"; | ||
| 731 | allwinner,drive = <0>; | ||
| 732 | allwinner,pull = <1>; | ||
| 733 | }; | ||
| 734 | |||
| 735 | mmc3_pins_a: mmc3@0 { | ||
| 736 | allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; | ||
| 737 | allwinner,function = "mmc3"; | ||
| 738 | allwinner,drive = <2>; | ||
| 739 | allwinner,pull = <0>; | ||
| 740 | }; | ||
| 664 | }; | 741 | }; |
| 665 | 742 | ||
| 666 | timer@01c20c00 { | 743 | timer@01c20c00 { |
| @@ -686,6 +763,14 @@ | |||
| 686 | interrupts = <0 24 4>; | 763 | interrupts = <0 24 4>; |
| 687 | }; | 764 | }; |
| 688 | 765 | ||
| 766 | pwm: pwm@01c20e00 { | ||
| 767 | compatible = "allwinner,sun7i-a20-pwm"; | ||
| 768 | reg = <0x01c20e00 0xc>; | ||
| 769 | clocks = <&osc24M>; | ||
| 770 | #pwm-cells = <3>; | ||
| 771 | status = "disabled"; | ||
| 772 | }; | ||
| 773 | |||
| 689 | sid: eeprom@01c23800 { | 774 | sid: eeprom@01c23800 { |
| 690 | compatible = "allwinner,sun7i-a20-sid"; | 775 | compatible = "allwinner,sun7i-a20-sid"; |
| 691 | reg = <0x01c23800 0x200>; | 776 | reg = <0x01c23800 0x200>; |
| @@ -778,48 +863,58 @@ | |||
| 778 | }; | 863 | }; |
| 779 | 864 | ||
| 780 | i2c0: i2c@01c2ac00 { | 865 | i2c0: i2c@01c2ac00 { |
| 781 | compatible = "allwinner,sun4i-i2c"; | 866 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
| 782 | reg = <0x01c2ac00 0x400>; | 867 | reg = <0x01c2ac00 0x400>; |
| 783 | interrupts = <0 7 4>; | 868 | interrupts = <0 7 4>; |
| 784 | clocks = <&apb1_gates 0>; | 869 | clocks = <&apb1_gates 0>; |
| 785 | clock-frequency = <100000>; | 870 | clock-frequency = <100000>; |
| 786 | status = "disabled"; | 871 | status = "disabled"; |
| 872 | #address-cells = <1>; | ||
| 873 | #size-cells = <0>; | ||
| 787 | }; | 874 | }; |
| 788 | 875 | ||
| 789 | i2c1: i2c@01c2b000 { | 876 | i2c1: i2c@01c2b000 { |
| 790 | compatible = "allwinner,sun4i-i2c"; | 877 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
| 791 | reg = <0x01c2b000 0x400>; | 878 | reg = <0x01c2b000 0x400>; |
| 792 | interrupts = <0 8 4>; | 879 | interrupts = <0 8 4>; |
| 793 | clocks = <&apb1_gates 1>; | 880 | clocks = <&apb1_gates 1>; |
| 794 | clock-frequency = <100000>; | 881 | clock-frequency = <100000>; |
| 795 | status = "disabled"; | 882 | status = "disabled"; |
| 883 | #address-cells = <1>; | ||
| 884 | #size-cells = <0>; | ||
| 796 | }; | 885 | }; |
| 797 | 886 | ||
| 798 | i2c2: i2c@01c2b400 { | 887 | i2c2: i2c@01c2b400 { |
| 799 | compatible = "allwinner,sun4i-i2c"; | 888 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
| 800 | reg = <0x01c2b400 0x400>; | 889 | reg = <0x01c2b400 0x400>; |
| 801 | interrupts = <0 9 4>; | 890 | interrupts = <0 9 4>; |
| 802 | clocks = <&apb1_gates 2>; | 891 | clocks = <&apb1_gates 2>; |
| 803 | clock-frequency = <100000>; | 892 | clock-frequency = <100000>; |
| 804 | status = "disabled"; | 893 | status = "disabled"; |
| 894 | #address-cells = <1>; | ||
| 895 | #size-cells = <0>; | ||
| 805 | }; | 896 | }; |
| 806 | 897 | ||
| 807 | i2c3: i2c@01c2b800 { | 898 | i2c3: i2c@01c2b800 { |
| 808 | compatible = "allwinner,sun4i-i2c"; | 899 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
| 809 | reg = <0x01c2b800 0x400>; | 900 | reg = <0x01c2b800 0x400>; |
| 810 | interrupts = <0 88 4>; | 901 | interrupts = <0 88 4>; |
| 811 | clocks = <&apb1_gates 3>; | 902 | clocks = <&apb1_gates 3>; |
| 812 | clock-frequency = <100000>; | 903 | clock-frequency = <100000>; |
| 813 | status = "disabled"; | 904 | status = "disabled"; |
| 905 | #address-cells = <1>; | ||
| 906 | #size-cells = <0>; | ||
| 814 | }; | 907 | }; |
| 815 | 908 | ||
| 816 | i2c4: i2c@01c2c000 { | 909 | i2c4: i2c@01c2c000 { |
| 817 | compatible = "allwinner,sun4i-i2c"; | 910 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
| 818 | reg = <0x01c2c000 0x400>; | 911 | reg = <0x01c2c000 0x400>; |
| 819 | interrupts = <0 89 4>; | 912 | interrupts = <0 89 4>; |
| 820 | clocks = <&apb1_gates 15>; | 913 | clocks = <&apb1_gates 15>; |
| 821 | clock-frequency = <100000>; | 914 | clock-frequency = <100000>; |
| 822 | status = "disabled"; | 915 | status = "disabled"; |
| 916 | #address-cells = <1>; | ||
| 917 | #size-cells = <0>; | ||
| 823 | }; | 918 | }; |
| 824 | 919 | ||
| 825 | gmac: ethernet@01c50000 { | 920 | gmac: ethernet@01c50000 { |
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi index 18eeac0670b9..3d021efd1a38 100644 --- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi +++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi | |||
| @@ -72,4 +72,18 @@ | |||
| 72 | gpio = <&pio 7 3 0>; | 72 | gpio = <&pio 7 3 0>; |
| 73 | status = "disabled"; | 73 | status = "disabled"; |
| 74 | }; | 74 | }; |
| 75 | |||
| 76 | reg_vcc3v0: vcc3v0 { | ||
| 77 | compatible = "regulator-fixed"; | ||
| 78 | regulator-name = "vcc3v0"; | ||
| 79 | regulator-min-microvolt = <3000000>; | ||
| 80 | regulator-max-microvolt = <3000000>; | ||
| 81 | }; | ||
| 82 | |||
| 83 | reg_vcc3v3: vcc3v3 { | ||
| 84 | compatible = "regulator-fixed"; | ||
| 85 | regulator-name = "vcc3v3"; | ||
| 86 | regulator-min-microvolt = <3300000>; | ||
| 87 | regulator-max-microvolt = <3300000>; | ||
| 88 | }; | ||
| 75 | }; | 89 | }; |
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index a288a12823ed..5c21d216515a 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | hdmi@54280000 { | 25 | hdmi@54280000 { |
| 26 | status = "okay"; | 26 | status = "okay"; |
| 27 | 27 | ||
| 28 | hdmi-supply = <&vdd_5v0_hdmi>; | ||
| 28 | vdd-supply = <&vdd_hdmi_reg>; | 29 | vdd-supply = <&vdd_hdmi_reg>; |
| 29 | pll-supply = <&palmas_smps3_reg>; | 30 | pll-supply = <&palmas_smps3_reg>; |
| 30 | 31 | ||
| @@ -36,6 +37,8 @@ | |||
| 36 | dsi@54300000 { | 37 | dsi@54300000 { |
| 37 | status = "okay"; | 38 | status = "okay"; |
| 38 | 39 | ||
| 40 | avdd-dsi-csi-supply = <&avdd_1v2_reg>; | ||
| 41 | |||
| 39 | panel@0 { | 42 | panel@0 { |
| 40 | compatible = "panasonic,vvx10f004b00", | 43 | compatible = "panasonic,vvx10f004b00", |
| 41 | "simple-panel"; | 44 | "simple-panel"; |
| @@ -982,12 +985,10 @@ | |||
| 982 | regulator-max-microvolt = <2800000>; | 985 | regulator-max-microvolt = <2800000>; |
| 983 | }; | 986 | }; |
| 984 | 987 | ||
| 985 | ldo3 { | 988 | avdd_1v2_reg: ldo3 { |
| 986 | regulator-name = "avdd-dsi-csi"; | 989 | regulator-name = "avdd-dsi-csi"; |
| 987 | regulator-min-microvolt = <1200000>; | 990 | regulator-min-microvolt = <1200000>; |
| 988 | regulator-max-microvolt = <1200000>; | 991 | regulator-max-microvolt = <1200000>; |
| 989 | regulator-always-on; | ||
| 990 | regulator-boot-on; | ||
| 991 | }; | 992 | }; |
| 992 | 993 | ||
| 993 | ldo4 { | 994 | ldo4 { |
| @@ -1105,6 +1106,7 @@ | |||
| 1105 | 1106 | ||
| 1106 | sdhci@78000400 { | 1107 | sdhci@78000400 { |
| 1107 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; | 1108 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
| 1109 | wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; | ||
| 1108 | bus-width = <4>; | 1110 | bus-width = <4>; |
| 1109 | status = "okay"; | 1111 | status = "okay"; |
| 1110 | }; | 1112 | }; |
| @@ -1231,8 +1233,6 @@ | |||
| 1231 | regulator-name = "vdd_hdmi_5v0"; | 1233 | regulator-name = "vdd_hdmi_5v0"; |
| 1232 | regulator-min-microvolt = <5000000>; | 1234 | regulator-min-microvolt = <5000000>; |
| 1233 | regulator-max-microvolt = <5000000>; | 1235 | regulator-max-microvolt = <5000000>; |
| 1234 | enable-active-high; | ||
| 1235 | gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; | ||
| 1236 | vin-supply = <&tps65090_dcdc1_reg>; | 1236 | vin-supply = <&tps65090_dcdc1_reg>; |
| 1237 | }; | 1237 | }; |
| 1238 | 1238 | ||
| @@ -1245,6 +1245,17 @@ | |||
| 1245 | enable-active-high; | 1245 | enable-active-high; |
| 1246 | gpio = <&palmas_gpio 6 0>; | 1246 | gpio = <&palmas_gpio 6 0>; |
| 1247 | }; | 1247 | }; |
| 1248 | |||
| 1249 | vdd_5v0_hdmi: regulator@7 { | ||
| 1250 | compatible = "regulator-fixed"; | ||
| 1251 | reg = <7>; | ||
| 1252 | regulator-name = "VDD_5V0_HDMI_CON"; | ||
| 1253 | regulator-min-microvolt = <5000000>; | ||
| 1254 | regulator-max-microvolt = <5000000>; | ||
| 1255 | gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; | ||
| 1256 | enable-active-high; | ||
| 1257 | vin-supply = <&tps65090_dcdc1_reg>; | ||
| 1258 | }; | ||
| 1248 | }; | 1259 | }; |
| 1249 | 1260 | ||
| 1250 | sound { | 1261 | sound { |
diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts new file mode 100644 index 000000000000..0b0e8e07d965 --- /dev/null +++ b/arch/arm/boot/dts/tegra114-roth.dts | |||
| @@ -0,0 +1,1113 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | #include <dt-bindings/input/input.h> | ||
| 4 | #include "tegra114.dtsi" | ||
| 5 | |||
| 6 | / { | ||
| 7 | model = "NVIDIA SHIELD"; | ||
| 8 | compatible = "nvidia,roth", "nvidia,tegra114"; | ||
| 9 | |||
| 10 | chosen { | ||
| 11 | /* SHIELD's bootloader's arguments need to be overridden */ | ||
| 12 | bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:1"; | ||
| 13 | /* SHIELD's bootloader will place initrd at this address */ | ||
| 14 | linux,initrd-start = <0x82000000>; | ||
| 15 | linux,initrd-end = <0x82800000>; | ||
| 16 | }; | ||
| 17 | |||
| 18 | firmware { | ||
| 19 | trusted-foundations { | ||
| 20 | compatible = "tlm,trusted-foundations"; | ||
| 21 | tlm,version-major = <2>; | ||
| 22 | tlm,version-minor = <8>; | ||
| 23 | }; | ||
| 24 | }; | ||
| 25 | |||
| 26 | memory { | ||
| 27 | /* memory >= 0x79600000 is reserved for firmware usage */ | ||
| 28 | reg = <0x80000000 0x79600000>; | ||
| 29 | }; | ||
| 30 | |||
| 31 | pinmux@70000868 { | ||
| 32 | pinctrl-names = "default"; | ||
| 33 | pinctrl-0 = <&state_default>; | ||
| 34 | |||
| 35 | state_default: pinmux { | ||
| 36 | clk1_out_pw4 { | ||
| 37 | nvidia,pins = "clk1_out_pw4"; | ||
| 38 | nvidia,function = "extperiph1"; | ||
| 39 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 40 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 41 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 42 | }; | ||
| 43 | dap1_din_pn1 { | ||
| 44 | nvidia,pins = "dap1_din_pn1"; | ||
| 45 | nvidia,function = "i2s0"; | ||
| 46 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 47 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 48 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 49 | }; | ||
| 50 | dap1_dout_pn2 { | ||
| 51 | nvidia,pins = "dap1_dout_pn2", | ||
| 52 | "dap1_fs_pn0", | ||
| 53 | "dap1_sclk_pn3"; | ||
| 54 | nvidia,function = "i2s0"; | ||
| 55 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 56 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 57 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 58 | }; | ||
| 59 | dap2_din_pa4 { | ||
| 60 | nvidia,pins = "dap2_din_pa4"; | ||
| 61 | nvidia,function = "i2s1"; | ||
| 62 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 63 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 64 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 65 | }; | ||
| 66 | dap2_dout_pa5 { | ||
| 67 | nvidia,pins = "dap2_dout_pa5", | ||
| 68 | "dap2_fs_pa2", | ||
| 69 | "dap2_sclk_pa3"; | ||
| 70 | nvidia,function = "i2s1"; | ||
| 71 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 72 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 73 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 74 | }; | ||
| 75 | dap4_din_pp5 { | ||
| 76 | nvidia,pins = "dap4_din_pp5", | ||
| 77 | "dap4_dout_pp6", | ||
| 78 | "dap4_fs_pp4", | ||
| 79 | "dap4_sclk_pp7"; | ||
| 80 | nvidia,function = "i2s3"; | ||
| 81 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 82 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 83 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 84 | }; | ||
| 85 | dvfs_pwm_px0 { | ||
| 86 | nvidia,pins = "dvfs_pwm_px0", | ||
| 87 | "dvfs_clk_px2"; | ||
| 88 | nvidia,function = "cldvfs"; | ||
| 89 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 90 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 91 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 92 | }; | ||
| 93 | ulpi_clk_py0 { | ||
| 94 | nvidia,pins = "ulpi_clk_py0", | ||
| 95 | "ulpi_data0_po1", | ||
| 96 | "ulpi_data1_po2", | ||
| 97 | "ulpi_data2_po3", | ||
| 98 | "ulpi_data3_po4", | ||
| 99 | "ulpi_data4_po5", | ||
| 100 | "ulpi_data5_po6", | ||
| 101 | "ulpi_data6_po7", | ||
| 102 | "ulpi_data7_po0"; | ||
| 103 | nvidia,function = "ulpi"; | ||
| 104 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 105 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 106 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 107 | }; | ||
| 108 | ulpi_dir_py1 { | ||
| 109 | nvidia,pins = "ulpi_dir_py1", | ||
| 110 | "ulpi_nxt_py2"; | ||
| 111 | nvidia,function = "ulpi"; | ||
| 112 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 113 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 114 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 115 | }; | ||
| 116 | ulpi_stp_py3 { | ||
| 117 | nvidia,pins = "ulpi_stp_py3"; | ||
| 118 | nvidia,function = "ulpi"; | ||
| 119 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 120 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 121 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 122 | }; | ||
| 123 | cam_i2c_scl_pbb1 { | ||
| 124 | nvidia,pins = "cam_i2c_scl_pbb1", | ||
| 125 | "cam_i2c_sda_pbb2"; | ||
| 126 | nvidia,function = "i2c3"; | ||
| 127 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 128 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 129 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 130 | nvidia,lock = <TEGRA_PIN_DISABLE>; | ||
| 131 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | ||
| 132 | }; | ||
| 133 | cam_mclk_pcc0 { | ||
| 134 | nvidia,pins = "cam_mclk_pcc0", | ||
| 135 | "pbb0"; | ||
| 136 | nvidia,function = "vi_alt3"; | ||
| 137 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 138 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 139 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 140 | nvidia,lock = <TEGRA_PIN_DISABLE>; | ||
| 141 | }; | ||
| 142 | pbb4 { | ||
| 143 | nvidia,pins = "pbb4"; | ||
| 144 | nvidia,function = "vgp4"; | ||
| 145 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 146 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 147 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 148 | nvidia,lock = <TEGRA_PIN_DISABLE>; | ||
| 149 | }; | ||
| 150 | gen2_i2c_scl_pt5 { | ||
| 151 | nvidia,pins = "gen2_i2c_scl_pt5", | ||
| 152 | "gen2_i2c_sda_pt6"; | ||
| 153 | nvidia,function = "i2c2"; | ||
| 154 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 155 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 156 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 157 | nvidia,lock = <TEGRA_PIN_DISABLE>; | ||
| 158 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | ||
| 159 | }; | ||
| 160 | gmi_a16_pj7 { | ||
| 161 | nvidia,pins = "gmi_a16_pj7", | ||
| 162 | "gmi_a19_pk7"; | ||
| 163 | nvidia,function = "uartd"; | ||
| 164 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 165 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 166 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 167 | }; | ||
| 168 | gmi_a17_pb0 { | ||
| 169 | nvidia,pins = "gmi_a17_pb0", | ||
| 170 | "gmi_a18_pb1"; | ||
| 171 | nvidia,function = "uartd"; | ||
| 172 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 173 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 174 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 175 | }; | ||
| 176 | gmi_ad5_pg5 { | ||
| 177 | nvidia,pins = "gmi_ad5_pg5", | ||
| 178 | "gmi_wr_n_pi0"; | ||
| 179 | nvidia,function = "spi4"; | ||
| 180 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 181 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 182 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 183 | }; | ||
| 184 | gmi_ad6_pg6 { | ||
| 185 | nvidia,pins = "gmi_ad6_pg6", | ||
| 186 | "gmi_ad7_pg7"; | ||
| 187 | nvidia,function = "spi4"; | ||
| 188 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 189 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 190 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 191 | }; | ||
| 192 | gmi_ad12_ph4 { | ||
| 193 | nvidia,pins = "gmi_ad12_ph4"; | ||
| 194 | nvidia,function = "rsvd4"; | ||
| 195 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 196 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 197 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 198 | }; | ||
| 199 | gmi_cs6_n_pi13 { | ||
| 200 | nvidia,pins = "gmi_cs6_n_pi3"; | ||
| 201 | nvidia,function = "nand"; | ||
| 202 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 203 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 204 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 205 | }; | ||
| 206 | gmi_ad9_ph1 { | ||
| 207 | nvidia,pins = "gmi_ad9_ph1"; | ||
| 208 | nvidia,function = "pwm1"; | ||
| 209 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 210 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 211 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 212 | }; | ||
| 213 | gmi_cs1_n_pj2 { | ||
| 214 | nvidia,pins = "gmi_cs1_n_pj2", | ||
| 215 | "gmi_oe_n_pi1"; | ||
| 216 | nvidia,function = "soc"; | ||
| 217 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 218 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 219 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 220 | }; | ||
| 221 | gmi_rst_n_pi4 { | ||
| 222 | nvidia,pins = "gmi_rst_n_pi4"; | ||
| 223 | nvidia,function = "gmi"; | ||
| 224 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 225 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 226 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 227 | }; | ||
| 228 | gmi_iordy_pi5 { | ||
| 229 | nvidia,pins = "gmi_iordy_pi5"; | ||
| 230 | nvidia,function = "gmi"; | ||
| 231 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 232 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 233 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 234 | }; | ||
| 235 | clk2_out_pw5 { | ||
| 236 | nvidia,pins = "clk2_out_pw5"; | ||
| 237 | nvidia,function = "extperiph2"; | ||
| 238 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 239 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 240 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 241 | }; | ||
| 242 | sdmmc1_clk_pz0 { | ||
| 243 | nvidia,pins = "sdmmc1_clk_pz0"; | ||
| 244 | nvidia,function = "sdmmc1"; | ||
| 245 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 246 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 247 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 248 | }; | ||
| 249 | sdmmc1_cmd_pz1 { | ||
| 250 | nvidia,pins = "sdmmc1_cmd_pz1", | ||
| 251 | "sdmmc1_dat0_py7", | ||
| 252 | "sdmmc1_dat1_py6", | ||
| 253 | "sdmmc1_dat2_py5", | ||
| 254 | "sdmmc1_dat3_py4"; | ||
| 255 | nvidia,function = "sdmmc1"; | ||
| 256 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 257 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 258 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 259 | }; | ||
| 260 | sdmmc3_clk_pa6 { | ||
| 261 | nvidia,pins = "sdmmc3_clk_pa6"; | ||
| 262 | nvidia,function = "sdmmc3"; | ||
| 263 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 264 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 265 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 266 | }; | ||
| 267 | sdmmc3_cmd_pa7 { | ||
| 268 | nvidia,pins = "sdmmc3_cmd_pa7", | ||
| 269 | "sdmmc3_dat0_pb7", | ||
| 270 | "sdmmc3_dat1_pb6", | ||
| 271 | "sdmmc3_dat2_pb5", | ||
| 272 | "sdmmc3_dat3_pb4", | ||
| 273 | "sdmmc3_cd_n_pv2", | ||
| 274 | "sdmmc3_clk_lb_out_pee4", | ||
| 275 | "sdmmc3_clk_lb_in_pee5"; | ||
| 276 | nvidia,function = "sdmmc3"; | ||
| 277 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 278 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 279 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 280 | }; | ||
| 281 | kb_col4_pq4 { | ||
| 282 | nvidia,pins = "kb_col4_pq4"; | ||
| 283 | nvidia,function = "sdmmc3"; | ||
| 284 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 285 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 286 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 287 | }; | ||
| 288 | sdmmc4_clk_pcc4 { | ||
| 289 | nvidia,pins = "sdmmc4_clk_pcc4"; | ||
| 290 | nvidia,function = "sdmmc4"; | ||
| 291 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 292 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 293 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 294 | }; | ||
| 295 | sdmmc4_cmd_pt7 { | ||
| 296 | nvidia,pins = "sdmmc4_cmd_pt7", | ||
| 297 | "sdmmc4_dat0_paa0", | ||
| 298 | "sdmmc4_dat1_paa1", | ||
| 299 | "sdmmc4_dat2_paa2", | ||
| 300 | "sdmmc4_dat3_paa3", | ||
| 301 | "sdmmc4_dat4_paa4", | ||
| 302 | "sdmmc4_dat5_paa5", | ||
| 303 | "sdmmc4_dat6_paa6", | ||
| 304 | "sdmmc4_dat7_paa7"; | ||
| 305 | nvidia,function = "sdmmc4"; | ||
| 306 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 307 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 308 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 309 | }; | ||
| 310 | clk_32k_out_pa0 { | ||
| 311 | nvidia,pins = "clk_32k_out_pa0"; | ||
| 312 | nvidia,function = "blink"; | ||
| 313 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 314 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 315 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 316 | }; | ||
| 317 | kb_col0_pq0 { | ||
| 318 | nvidia,pins = "kb_col0_pq0", | ||
| 319 | "kb_col1_pq1", | ||
| 320 | "kb_col2_pq2", | ||
| 321 | "kb_row0_pr0", | ||
| 322 | "kb_row1_pr1", | ||
| 323 | "kb_row2_pr2", | ||
| 324 | "kb_row8_ps0"; | ||
| 325 | nvidia,function = "kbc"; | ||
| 326 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 327 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 328 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 329 | }; | ||
| 330 | kb_row7_pr7 { | ||
| 331 | nvidia,pins = "kb_row7_pr7"; | ||
| 332 | nvidia,function = "rsvd2"; | ||
| 333 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 334 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 335 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 336 | }; | ||
| 337 | kb_row10_ps2 { | ||
| 338 | nvidia,pins = "kb_row10_ps2"; | ||
| 339 | nvidia,function = "uarta"; | ||
| 340 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 341 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 342 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 343 | }; | ||
| 344 | kb_row9_ps1 { | ||
| 345 | nvidia,pins = "kb_row9_ps1"; | ||
| 346 | nvidia,function = "uarta"; | ||
| 347 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 348 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 349 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 350 | }; | ||
| 351 | pwr_i2c_scl_pz6 { | ||
| 352 | nvidia,pins = "pwr_i2c_scl_pz6", | ||
| 353 | "pwr_i2c_sda_pz7"; | ||
| 354 | nvidia,function = "i2cpwr"; | ||
| 355 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 356 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 357 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 358 | nvidia,lock = <TEGRA_PIN_DISABLE>; | ||
| 359 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | ||
| 360 | }; | ||
| 361 | sys_clk_req_pz5 { | ||
| 362 | nvidia,pins = "sys_clk_req_pz5"; | ||
| 363 | nvidia,function = "sysclk"; | ||
| 364 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 365 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 366 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 367 | }; | ||
| 368 | core_pwr_req { | ||
| 369 | nvidia,pins = "core_pwr_req"; | ||
| 370 | nvidia,function = "pwron"; | ||
| 371 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 372 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 373 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 374 | }; | ||
| 375 | cpu_pwr_req { | ||
| 376 | nvidia,pins = "cpu_pwr_req"; | ||
| 377 | nvidia,function = "cpu"; | ||
| 378 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 379 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 380 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 381 | }; | ||
| 382 | pwr_int_n { | ||
| 383 | nvidia,pins = "pwr_int_n"; | ||
| 384 | nvidia,function = "pmi"; | ||
| 385 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 386 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 387 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 388 | }; | ||
| 389 | reset_out_n { | ||
| 390 | nvidia,pins = "reset_out_n"; | ||
| 391 | nvidia,function = "reset_out_n"; | ||
| 392 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 393 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 394 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 395 | }; | ||
| 396 | clk3_out_pee0 { | ||
| 397 | nvidia,pins = "clk3_out_pee0"; | ||
| 398 | nvidia,function = "extperiph3"; | ||
| 399 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 400 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 401 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 402 | }; | ||
| 403 | gen1_i2c_scl_pc4 { | ||
| 404 | nvidia,pins = "gen1_i2c_scl_pc4", | ||
| 405 | "gen1_i2c_sda_pc5"; | ||
| 406 | nvidia,function = "i2c1"; | ||
| 407 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 408 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 409 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 410 | nvidia,lock = <TEGRA_PIN_DISABLE>; | ||
| 411 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | ||
| 412 | }; | ||
| 413 | uart2_cts_n_pj5 { | ||
| 414 | nvidia,pins = "uart2_cts_n_pj5"; | ||
| 415 | nvidia,function = "uartb"; | ||
| 416 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 417 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 418 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 419 | }; | ||
| 420 | uart2_rts_n_pj6 { | ||
| 421 | nvidia,pins = "uart2_rts_n_pj6"; | ||
| 422 | nvidia,function = "uartb"; | ||
| 423 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 424 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 425 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 426 | }; | ||
| 427 | uart2_rxd_pc3 { | ||
| 428 | nvidia,pins = "uart2_rxd_pc3"; | ||
| 429 | nvidia,function = "irda"; | ||
| 430 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 431 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 432 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 433 | }; | ||
| 434 | uart2_txd_pc2 { | ||
| 435 | nvidia,pins = "uart2_txd_pc2"; | ||
| 436 | nvidia,function = "irda"; | ||
| 437 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 438 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 439 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 440 | }; | ||
| 441 | uart3_cts_n_pa1 { | ||
| 442 | nvidia,pins = "uart3_cts_n_pa1", | ||
| 443 | "uart3_rxd_pw7"; | ||
| 444 | nvidia,function = "uartc"; | ||
| 445 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 446 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 447 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 448 | }; | ||
| 449 | uart3_rts_n_pc0 { | ||
| 450 | nvidia,pins = "uart3_rts_n_pc0", | ||
| 451 | "uart3_txd_pw6"; | ||
| 452 | nvidia,function = "uartc"; | ||
| 453 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 454 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 455 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 456 | }; | ||
| 457 | owr { | ||
| 458 | nvidia,pins = "owr"; | ||
| 459 | nvidia,function = "owr"; | ||
| 460 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 461 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 462 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 463 | }; | ||
| 464 | hdmi_cec_pee3 { | ||
| 465 | nvidia,pins = "hdmi_cec_pee3"; | ||
| 466 | nvidia,function = "cec"; | ||
| 467 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 468 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 469 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 470 | nvidia,lock = <TEGRA_PIN_DISABLE>; | ||
| 471 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | ||
| 472 | }; | ||
| 473 | ddc_scl_pv4 { | ||
| 474 | nvidia,pins = "ddc_scl_pv4", | ||
| 475 | "ddc_sda_pv5"; | ||
| 476 | nvidia,function = "i2c4"; | ||
| 477 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 478 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 479 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 480 | nvidia,lock = <TEGRA_PIN_DISABLE>; | ||
| 481 | nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; | ||
| 482 | }; | ||
| 483 | spdif_in_pk6 { | ||
| 484 | nvidia,pins = "spdif_in_pk6"; | ||
| 485 | nvidia,function = "usb"; | ||
| 486 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 487 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 488 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 489 | nvidia,lock = <TEGRA_PIN_DISABLE>; | ||
| 490 | }; | ||
| 491 | usb_vbus_en0_pn4 { | ||
| 492 | nvidia,pins = "usb_vbus_en0_pn4"; | ||
| 493 | nvidia,function = "usb"; | ||
| 494 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 495 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 496 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 497 | nvidia,lock = <TEGRA_PIN_DISABLE>; | ||
| 498 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
| 499 | }; | ||
| 500 | gpio_x6_aud_px6 { | ||
| 501 | nvidia,pins = "gpio_x6_aud_px6"; | ||
| 502 | nvidia,function = "spi6"; | ||
| 503 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 504 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 505 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 506 | }; | ||
| 507 | gpio_x1_aud_px1 { | ||
| 508 | nvidia,pins = "gpio_x1_aud_px1"; | ||
| 509 | nvidia,function = "rsvd2"; | ||
| 510 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 511 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 512 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 513 | }; | ||
| 514 | gpio_x7_aud_px7 { | ||
| 515 | nvidia,pins = "gpio_x7_aud_px7"; | ||
| 516 | nvidia,function = "rsvd1"; | ||
| 517 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 518 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 519 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 520 | }; | ||
| 521 | gmi_adv_n_pk0 { | ||
| 522 | nvidia,pins = "gmi_adv_n_pk0"; | ||
| 523 | nvidia,function = "gmi"; | ||
| 524 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 525 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 526 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 527 | }; | ||
| 528 | gmi_cs0_n_pj0 { | ||
| 529 | nvidia,pins = "gmi_cs0_n_pj0"; | ||
| 530 | nvidia,function = "gmi"; | ||
| 531 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 532 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 533 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 534 | }; | ||
| 535 | pu3 { | ||
| 536 | nvidia,pins = "pu3"; | ||
| 537 | nvidia,function = "pwm0"; | ||
| 538 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 539 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 540 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 541 | }; | ||
| 542 | gpio_x4_aud_px4 { | ||
| 543 | nvidia,pins = "gpio_x4_aud_px4", | ||
| 544 | "gpio_x5_aud_px5"; | ||
| 545 | nvidia,function = "rsvd1"; | ||
| 546 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 547 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 548 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 549 | }; | ||
| 550 | gpio_x3_aud_px3 { | ||
| 551 | nvidia,pins = "gpio_x3_aud_px3"; | ||
| 552 | nvidia,function = "rsvd4"; | ||
| 553 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 554 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 555 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 556 | }; | ||
| 557 | gpio_w2_aud_pw2 { | ||
| 558 | nvidia,pins = "gpio_w2_aud_pw2"; | ||
| 559 | nvidia,function = "rsvd2"; | ||
| 560 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 561 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 562 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 563 | }; | ||
| 564 | gpio_w3_aud_pw3 { | ||
| 565 | nvidia,pins = "gpio_w3_aud_pw3"; | ||
| 566 | nvidia,function = "spi6"; | ||
| 567 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 568 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 569 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 570 | }; | ||
| 571 | dap3_fs_pp0 { | ||
| 572 | nvidia,pins = "dap3_fs_pp0", | ||
| 573 | "dap3_din_pp1", | ||
| 574 | "dap3_dout_pp2", | ||
| 575 | "dap3_sclk_pp3"; | ||
| 576 | nvidia,function = "i2s2"; | ||
| 577 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 578 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 579 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 580 | }; | ||
| 581 | pv0 { | ||
| 582 | nvidia,pins = "pv0"; | ||
| 583 | nvidia,function = "rsvd4"; | ||
| 584 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 585 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 586 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 587 | }; | ||
| 588 | pv1 { | ||
| 589 | nvidia,pins = "pv1"; | ||
| 590 | nvidia,function = "rsvd1"; | ||
| 591 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 592 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 593 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 594 | }; | ||
| 595 | pbb3 { | ||
| 596 | nvidia,pins = "pbb3", | ||
| 597 | "pbb5", | ||
| 598 | "pbb6", | ||
| 599 | "pbb7"; | ||
| 600 | nvidia,function = "rsvd4"; | ||
| 601 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 602 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 603 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 604 | }; | ||
| 605 | pcc1 { | ||
| 606 | nvidia,pins = "pcc1", | ||
| 607 | "pcc2"; | ||
| 608 | nvidia,function = "rsvd4"; | ||
| 609 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 610 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 611 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 612 | }; | ||
| 613 | gmi_ad0_pg0 { | ||
| 614 | nvidia,pins = "gmi_ad0_pg0", | ||
| 615 | "gmi_ad1_pg1"; | ||
| 616 | nvidia,function = "gmi"; | ||
| 617 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 618 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 619 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 620 | }; | ||
| 621 | gmi_ad10_ph2 { | ||
| 622 | nvidia,pins = "gmi_ad10_ph2", | ||
| 623 | "gmi_ad12_ph4", | ||
| 624 | "gmi_ad15_ph7", | ||
| 625 | "gmi_cs3_n_pk4"; | ||
| 626 | nvidia,function = "gmi"; | ||
| 627 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 628 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 629 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 630 | }; | ||
| 631 | gmi_ad11_ph3 { | ||
| 632 | nvidia,pins = "gmi_ad11_ph3", | ||
| 633 | "gmi_ad13_ph5", | ||
| 634 | "gmi_ad8_ph0", | ||
| 635 | "gmi_clk_pk1", | ||
| 636 | "gmi_cs2_n_pk3"; | ||
| 637 | nvidia,function = "gmi"; | ||
| 638 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 639 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 640 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 641 | }; | ||
| 642 | gmi_ad14_ph6 { | ||
| 643 | nvidia,pins = "gmi_ad14_ph6", | ||
| 644 | "gmi_cs0_n_pj0", | ||
| 645 | "gmi_cs4_n_pk2", | ||
| 646 | "gmi_cs7_n_pi6", | ||
| 647 | "gmi_dqs_p_pj3", | ||
| 648 | "gmi_wp_n_pc7"; | ||
| 649 | nvidia,function = "gmi"; | ||
| 650 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 651 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 652 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 653 | }; | ||
| 654 | gmi_ad2_pg2 { | ||
| 655 | nvidia,pins = "gmi_ad2_pg2", | ||
| 656 | "gmi_ad3_pg3"; | ||
| 657 | nvidia,function = "gmi"; | ||
| 658 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 659 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 660 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 661 | }; | ||
| 662 | sdmmc1_wp_n_pv3 { | ||
| 663 | nvidia,pins = "sdmmc1_wp_n_pv3"; | ||
| 664 | nvidia,function = "spi4"; | ||
| 665 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 666 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 667 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 668 | }; | ||
| 669 | clk2_req_pcc5 { | ||
| 670 | nvidia,pins = "clk2_req_pcc5"; | ||
| 671 | nvidia,function = "rsvd4"; | ||
| 672 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 673 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 674 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 675 | }; | ||
| 676 | kb_col3_pq3 { | ||
| 677 | nvidia,pins = "kb_col3_pq3"; | ||
| 678 | nvidia,function = "pwm2"; | ||
| 679 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 680 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 681 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 682 | }; | ||
| 683 | kb_col5_pq5 { | ||
| 684 | nvidia,pins = "kb_col5_pq5"; | ||
| 685 | nvidia,function = "kbc"; | ||
| 686 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 687 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 688 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 689 | }; | ||
| 690 | kb_col6_pq6 { | ||
| 691 | nvidia,pins = "kb_col6_pq6", | ||
| 692 | "kb_col7_pq7"; | ||
| 693 | nvidia,function = "kbc"; | ||
| 694 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 695 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 696 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 697 | }; | ||
| 698 | kb_row3_pr3 { | ||
| 699 | nvidia,pins = "kb_row3_pr3", | ||
| 700 | "kb_row4_pr4", | ||
| 701 | "kb_row6_pr6"; | ||
| 702 | nvidia,function = "kbc"; | ||
| 703 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 704 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 705 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 706 | }; | ||
| 707 | clk3_req_pee1 { | ||
| 708 | nvidia,pins = "clk3_req_pee1"; | ||
| 709 | nvidia,function = "rsvd4"; | ||
| 710 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 711 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 712 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 713 | }; | ||
| 714 | pu2 { | ||
| 715 | nvidia,pins = "pu2"; | ||
| 716 | nvidia,function = "rsvd1"; | ||
| 717 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 718 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 719 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 720 | }; | ||
| 721 | hdmi_int_pn7 { | ||
| 722 | nvidia,pins = "hdmi_int_pn7"; | ||
| 723 | nvidia,function = "rsvd1"; | ||
| 724 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 725 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 726 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 727 | }; | ||
| 728 | |||
| 729 | drive_sdio1 { | ||
| 730 | nvidia,pins = "drive_sdio1"; | ||
| 731 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | ||
| 732 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | ||
| 733 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | ||
| 734 | nvidia,pull-down-strength = <36>; | ||
| 735 | nvidia,pull-up-strength = <20>; | ||
| 736 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; | ||
| 737 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; | ||
| 738 | }; | ||
| 739 | drive_sdio3 { | ||
| 740 | nvidia,pins = "drive_sdio3"; | ||
| 741 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | ||
| 742 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | ||
| 743 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | ||
| 744 | nvidia,pull-down-strength = <36>; | ||
| 745 | nvidia,pull-up-strength = <20>; | ||
| 746 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | ||
| 747 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | ||
| 748 | }; | ||
| 749 | drive_gma { | ||
| 750 | nvidia,pins = "drive_gma"; | ||
| 751 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | ||
| 752 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | ||
| 753 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | ||
| 754 | nvidia,pull-down-strength = <2>; | ||
| 755 | nvidia,pull-up-strength = <2>; | ||
| 756 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | ||
| 757 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | ||
| 758 | nvidia,drive-type = <1>; | ||
| 759 | }; | ||
| 760 | }; | ||
| 761 | }; | ||
| 762 | |||
| 763 | /* Usable on reworked devices only */ | ||
| 764 | serial@70006300 { | ||
| 765 | status = "okay"; | ||
| 766 | }; | ||
| 767 | |||
| 768 | pwm@7000a000 { | ||
| 769 | status = "okay"; | ||
| 770 | }; | ||
| 771 | |||
| 772 | i2c@7000d000 { | ||
| 773 | status = "okay"; | ||
| 774 | clock-frequency = <400000>; | ||
| 775 | |||
| 776 | regulator@43 { | ||
| 777 | compatible = "ti,tps51632"; | ||
| 778 | reg = <0x43>; | ||
| 779 | regulator-name = "vdd-cpu"; | ||
| 780 | regulator-min-microvolt = <500000>; | ||
| 781 | regulator-max-microvolt = <1520000>; | ||
| 782 | regulator-always-on; | ||
| 783 | regulator-boot-on; | ||
| 784 | }; | ||
| 785 | |||
| 786 | palmas: pmic@58 { | ||
| 787 | compatible = "ti,palmas"; | ||
| 788 | reg = <0x58>; | ||
| 789 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; | ||
| 790 | |||
| 791 | #interrupt-cells = <2>; | ||
| 792 | interrupt-controller; | ||
| 793 | |||
| 794 | ti,system-power-controller; | ||
| 795 | |||
| 796 | palmas_gpio: gpio { | ||
| 797 | compatible = "ti,palmas-gpio"; | ||
| 798 | gpio-controller; | ||
| 799 | #gpio-cells = <2>; | ||
| 800 | }; | ||
| 801 | |||
| 802 | pmic { | ||
| 803 | compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; | ||
| 804 | |||
| 805 | regulators { | ||
| 806 | smps12 { | ||
| 807 | regulator-name = "vdd-ddr"; | ||
| 808 | regulator-min-microvolt = <1200000>; | ||
| 809 | regulator-max-microvolt = <1500000>; | ||
| 810 | regulator-always-on; | ||
| 811 | regulator-boot-on; | ||
| 812 | }; | ||
| 813 | |||
| 814 | vdd_1v8: smps3 { | ||
| 815 | regulator-name = "vdd-1v8"; | ||
| 816 | regulator-min-microvolt = <1800000>; | ||
| 817 | regulator-max-microvolt = <1800000>; | ||
| 818 | regulator-always-on; | ||
| 819 | regulator-boot-on; | ||
| 820 | }; | ||
| 821 | |||
| 822 | smps457 { | ||
| 823 | regulator-name = "vdd-soc"; | ||
| 824 | regulator-min-microvolt = <900000>; | ||
| 825 | regulator-max-microvolt = <1400000>; | ||
| 826 | regulator-always-on; | ||
| 827 | regulator-boot-on; | ||
| 828 | }; | ||
| 829 | |||
| 830 | smps8 { | ||
| 831 | regulator-name = "avdd-pll-1v05"; | ||
| 832 | regulator-min-microvolt = <1050000>; | ||
| 833 | regulator-max-microvolt = <1050000>; | ||
| 834 | regulator-always-on; | ||
| 835 | regulator-boot-on; | ||
| 836 | }; | ||
| 837 | |||
| 838 | smps9 { | ||
| 839 | regulator-name = "vdd-2v85-emmc"; | ||
| 840 | regulator-min-microvolt = <2800000>; | ||
| 841 | regulator-max-microvolt = <2800000>; | ||
| 842 | regulator-always-on; | ||
| 843 | }; | ||
| 844 | |||
| 845 | smps10_out1 { | ||
| 846 | regulator-name = "vdd-fan"; | ||
| 847 | regulator-min-microvolt = <5000000>; | ||
| 848 | regulator-max-microvolt = <5000000>; | ||
| 849 | regulator-always-on; | ||
| 850 | regulator-boot-on; | ||
| 851 | }; | ||
| 852 | |||
| 853 | smps10_out2 { | ||
| 854 | regulator-name = "vdd-5v0-sys"; | ||
| 855 | regulator-min-microvolt = <5000000>; | ||
| 856 | regulator-max-microvolt = <5000000>; | ||
| 857 | regulator-always-on; | ||
| 858 | regulator-boot-on; | ||
| 859 | }; | ||
| 860 | |||
| 861 | ldo2 { | ||
| 862 | regulator-name = "vdd-2v8-display"; | ||
| 863 | regulator-min-microvolt = <2800000>; | ||
| 864 | regulator-max-microvolt = <2800000>; | ||
| 865 | regulator-boot-on; | ||
| 866 | }; | ||
| 867 | |||
| 868 | ldo3 { | ||
| 869 | regulator-name = "avdd-1v2"; | ||
| 870 | regulator-min-microvolt = <1200000>; | ||
| 871 | regulator-max-microvolt = <1200000>; | ||
| 872 | regulator-always-on; | ||
| 873 | regulator-boot-on; | ||
| 874 | }; | ||
| 875 | |||
| 876 | ldo4 { | ||
| 877 | regulator-name = "vpp-fuse"; | ||
| 878 | regulator-min-microvolt = <1800000>; | ||
| 879 | regulator-max-microvolt = <1800000>; | ||
| 880 | }; | ||
| 881 | |||
| 882 | ldo5 { | ||
| 883 | regulator-name = "avdd-hdmi-pll"; | ||
| 884 | regulator-min-microvolt = <1200000>; | ||
| 885 | regulator-max-microvolt = <1200000>; | ||
| 886 | }; | ||
| 887 | |||
| 888 | ldo6 { | ||
| 889 | regulator-name = "vdd-sensor-2v8"; | ||
| 890 | regulator-min-microvolt = <2850000>; | ||
| 891 | regulator-max-microvolt = <2850000>; | ||
| 892 | }; | ||
| 893 | |||
| 894 | ldo8 { | ||
| 895 | regulator-name = "vdd-rtc"; | ||
| 896 | regulator-min-microvolt = <1100000>; | ||
| 897 | regulator-max-microvolt = <1100000>; | ||
| 898 | regulator-always-on; | ||
| 899 | regulator-boot-on; | ||
| 900 | ti,enable-ldo8-tracking; | ||
| 901 | }; | ||
| 902 | |||
| 903 | vddio_sdmmc3: ldo9 { | ||
| 904 | regulator-name = "vddio-sdmmc3"; | ||
| 905 | regulator-min-microvolt = <1800000>; | ||
| 906 | regulator-max-microvolt = <3300000>; | ||
| 907 | regulator-always-on; | ||
| 908 | regulator-boot-on; | ||
| 909 | }; | ||
| 910 | |||
| 911 | ldousb { | ||
| 912 | regulator-name = "avdd-usb-hdmi"; | ||
| 913 | regulator-min-microvolt = <3300000>; | ||
| 914 | regulator-max-microvolt = <3300000>; | ||
| 915 | regulator-always-on; | ||
| 916 | regulator-boot-on; | ||
| 917 | }; | ||
| 918 | |||
| 919 | vdd_3v3_sys: regen1 { | ||
| 920 | regulator-name = "rail-3v3"; | ||
| 921 | regulator-max-microvolt = <3300000>; | ||
| 922 | regulator-always-on; | ||
| 923 | regulator-boot-on; | ||
| 924 | }; | ||
| 925 | |||
| 926 | regen2 { | ||
| 927 | regulator-name = "rail-5v0"; | ||
| 928 | regulator-max-microvolt = <5000000>; | ||
| 929 | regulator-always-on; | ||
| 930 | regulator-boot-on; | ||
| 931 | }; | ||
| 932 | |||
| 933 | }; | ||
| 934 | }; | ||
| 935 | |||
| 936 | rtc { | ||
| 937 | compatible = "ti,palmas-rtc"; | ||
| 938 | interrupt-parent = <&palmas>; | ||
| 939 | interrupts = <8 0>; | ||
| 940 | }; | ||
| 941 | |||
| 942 | }; | ||
| 943 | }; | ||
| 944 | |||
| 945 | pmc@7000e400 { | ||
| 946 | nvidia,invert-interrupt; | ||
| 947 | }; | ||
| 948 | |||
| 949 | /* SD card */ | ||
| 950 | sdhci@78000400 { | ||
| 951 | status = "okay"; | ||
| 952 | bus-width = <4>; | ||
| 953 | vmmc-supply = <&vddio_sdmmc3>; | ||
| 954 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; | ||
| 955 | power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; | ||
| 956 | }; | ||
| 957 | |||
| 958 | /* eMMC */ | ||
| 959 | sdhci@78000600 { | ||
| 960 | status = "okay"; | ||
| 961 | bus-width = <8>; | ||
| 962 | vmmc-supply = <&vdd_1v8>; | ||
| 963 | non-removable; | ||
| 964 | }; | ||
| 965 | |||
| 966 | /* External USB port (must be powered) */ | ||
| 967 | usb@7d000000 { | ||
| 968 | status = "okay"; | ||
| 969 | }; | ||
| 970 | |||
| 971 | usb-phy@7d000000 { | ||
| 972 | status = "okay"; | ||
| 973 | nvidia,xcvr-setup = <7>; | ||
| 974 | nvidia,xcvr-lsfslew = <2>; | ||
| 975 | nvidia,xcvr-lsrslew = <2>; | ||
| 976 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | ||
| 977 | /* Should be changed to "otg" once we have vbus_supply */ | ||
| 978 | /* As of now, USB devices need to be powered externally */ | ||
| 979 | dr_mode = "host"; | ||
| 980 | }; | ||
| 981 | |||
| 982 | /* SHIELD controller */ | ||
| 983 | usb@7d008000 { | ||
| 984 | status = "okay"; | ||
| 985 | }; | ||
| 986 | |||
| 987 | usb-phy@7d008000 { | ||
| 988 | status = "okay"; | ||
| 989 | nvidia,xcvr-setup = <7>; | ||
| 990 | nvidia,xcvr-lsfslew = <2>; | ||
| 991 | nvidia,xcvr-lsrslew = <2>; | ||
| 992 | }; | ||
| 993 | |||
| 994 | backlight: backlight { | ||
| 995 | compatible = "pwm-backlight"; | ||
| 996 | pwms = <&pwm 1 40000>; | ||
| 997 | |||
| 998 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
| 999 | default-brightness-level = <6>; | ||
| 1000 | |||
| 1001 | power-supply = <&lcd_bl_en>; | ||
| 1002 | enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; | ||
| 1003 | }; | ||
| 1004 | |||
| 1005 | clocks { | ||
| 1006 | compatible = "simple-bus"; | ||
| 1007 | #address-cells = <1>; | ||
| 1008 | #size-cells = <0>; | ||
| 1009 | |||
| 1010 | clk32k_in: clock { | ||
| 1011 | compatible = "fixed-clock"; | ||
| 1012 | reg=<0>; | ||
| 1013 | #clock-cells = <0>; | ||
| 1014 | clock-frequency = <32768>; | ||
| 1015 | }; | ||
| 1016 | }; | ||
| 1017 | |||
| 1018 | gpio-keys { | ||
| 1019 | compatible = "gpio-keys"; | ||
| 1020 | |||
| 1021 | back { | ||
| 1022 | label = "Back"; | ||
| 1023 | gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; | ||
| 1024 | linux,code = <KEY_BACK>; | ||
| 1025 | }; | ||
| 1026 | |||
| 1027 | home { | ||
| 1028 | label = "Home"; | ||
| 1029 | gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; | ||
| 1030 | linux,code = <KEY_HOME>; | ||
| 1031 | }; | ||
| 1032 | |||
| 1033 | power { | ||
| 1034 | label = "Power"; | ||
| 1035 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; | ||
| 1036 | linux,code = <KEY_POWER>; | ||
| 1037 | gpio-key,wakeup; | ||
| 1038 | }; | ||
| 1039 | }; | ||
| 1040 | |||
| 1041 | regulators { | ||
| 1042 | compatible = "simple-bus"; | ||
| 1043 | #address-cells = <1>; | ||
| 1044 | #size-cells = <0>; | ||
| 1045 | |||
| 1046 | lcd_bl_en: regulator@0 { | ||
| 1047 | compatible = "regulator-fixed"; | ||
| 1048 | reg = <0>; | ||
| 1049 | regulator-name = "lcd_bl_en"; | ||
| 1050 | regulator-min-microvolt = <5000000>; | ||
| 1051 | regulator-max-microvolt = <5000000>; | ||
| 1052 | regulator-boot-on; | ||
| 1053 | }; | ||
| 1054 | |||
| 1055 | regulator@1 { | ||
| 1056 | compatible = "regulator-fixed"; | ||
| 1057 | reg = <1>; | ||
| 1058 | regulator-name = "vdd_lcd_1v8"; | ||
| 1059 | regulator-min-microvolt = <1800000>; | ||
| 1060 | regulator-max-microvolt = <1800000>; | ||
| 1061 | vin-supply = <&vdd_1v8>; | ||
| 1062 | enable-active-high; | ||
| 1063 | gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; | ||
| 1064 | regulator-boot-on; | ||
| 1065 | }; | ||
| 1066 | |||
| 1067 | regulator@2 { | ||
| 1068 | compatible = "regulator-fixed"; | ||
| 1069 | reg = <2>; | ||
| 1070 | regulator-name = "vdd_1v8_ts"; | ||
| 1071 | regulator-min-microvolt = <1800000>; | ||
| 1072 | regulator-max-microvolt = <1800000>; | ||
| 1073 | gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>; | ||
| 1074 | regulator-boot-on; | ||
| 1075 | }; | ||
| 1076 | |||
| 1077 | regulator@3 { | ||
| 1078 | compatible = "regulator-fixed"; | ||
| 1079 | reg = <3>; | ||
| 1080 | regulator-name = "vdd_3v3_ts"; | ||
| 1081 | regulator-min-microvolt = <3300000>; | ||
| 1082 | regulator-max-microvolt = <3300000>; | ||
| 1083 | enable-active-high; | ||
| 1084 | gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; | ||
| 1085 | regulator-boot-on; | ||
| 1086 | }; | ||
| 1087 | |||
| 1088 | regulator@4 { | ||
| 1089 | compatible = "regulator-fixed"; | ||
| 1090 | reg = <4>; | ||
| 1091 | regulator-name = "vdd_1v8_com"; | ||
| 1092 | regulator-min-microvolt = <1800000>; | ||
| 1093 | regulator-max-microvolt = <1800000>; | ||
| 1094 | vin-supply = <&vdd_1v8>; | ||
| 1095 | enable-active-high; | ||
| 1096 | gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; | ||
| 1097 | regulator-boot-on; | ||
| 1098 | }; | ||
| 1099 | |||
| 1100 | regulator@5 { | ||
| 1101 | compatible = "regulator-fixed"; | ||
| 1102 | reg = <5>; | ||
| 1103 | regulator-name = "vdd_3v3_com"; | ||
| 1104 | regulator-min-microvolt = <3300000>; | ||
| 1105 | regulator-max-microvolt = <3300000>; | ||
| 1106 | vin-supply = <&vdd_3v3_sys>; | ||
| 1107 | enable-active-high; | ||
| 1108 | gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; | ||
| 1109 | regulator-always-on; | ||
| 1110 | regulator-boot-on; | ||
| 1111 | }; | ||
| 1112 | }; | ||
| 1113 | }; | ||
diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts new file mode 100644 index 000000000000..963662145635 --- /dev/null +++ b/arch/arm/boot/dts/tegra114-tn7.dts | |||
| @@ -0,0 +1,348 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | #include <dt-bindings/input/input.h> | ||
| 4 | #include "tegra114.dtsi" | ||
| 5 | |||
| 6 | / { | ||
| 7 | model = "Tegra Note 7"; | ||
| 8 | compatible = "nvidia,tn7", "nvidia,tegra114"; | ||
| 9 | |||
| 10 | chosen { | ||
| 11 | /* TN7's bootloader's arguments need to be overridden */ | ||
| 12 | bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:2"; | ||
| 13 | /* TN7's bootloader will place initrd at this address */ | ||
| 14 | linux,initrd-start = <0x82000000>; | ||
| 15 | linux,initrd-end = <0x82800000>; | ||
| 16 | }; | ||
| 17 | |||
| 18 | firmware { | ||
| 19 | trusted-foundations { | ||
| 20 | compatible = "tlm,trusted-foundations"; | ||
| 21 | tlm,version-major = <2>; | ||
| 22 | tlm,version-minor = <8>; | ||
| 23 | }; | ||
| 24 | }; | ||
| 25 | |||
| 26 | memory { | ||
| 27 | /* memory >= 0x37e00000 is reserved for firmware usage */ | ||
| 28 | reg = <0x80000000 0x37e00000>; | ||
| 29 | }; | ||
| 30 | |||
| 31 | host1x@50000000 { | ||
| 32 | dsi@54300000 { | ||
| 33 | status = "okay"; | ||
| 34 | |||
| 35 | vdd-supply = <&vdd_1v2_ap>; | ||
| 36 | |||
| 37 | panel@0 { | ||
| 38 | compatible = "lg,ld070wx3-sl01"; | ||
| 39 | reg = <0>; | ||
| 40 | |||
| 41 | power-supply = <&vdd_lcd>; | ||
| 42 | backlight = <&backlight>; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | |||
| 47 | serial@70006300 { | ||
| 48 | status = "okay"; | ||
| 49 | }; | ||
| 50 | |||
| 51 | pwm@7000a000 { | ||
| 52 | status = "okay"; | ||
| 53 | }; | ||
| 54 | |||
| 55 | i2c@7000d000 { | ||
| 56 | status = "okay"; | ||
| 57 | clock-frequency = <400000>; | ||
| 58 | |||
| 59 | palmas: pmic@58 { | ||
| 60 | compatible = "ti,palmas"; | ||
| 61 | reg = <0x58>; | ||
| 62 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; | ||
| 63 | |||
| 64 | #interrupt-cells = <2>; | ||
| 65 | interrupt-controller; | ||
| 66 | |||
| 67 | ti,system-power-controller; | ||
| 68 | |||
| 69 | palmas_gpio: gpio { | ||
| 70 | compatible = "ti,palmas-gpio"; | ||
| 71 | gpio-controller; | ||
| 72 | #gpio-cells = <2>; | ||
| 73 | }; | ||
| 74 | |||
| 75 | pmic { | ||
| 76 | compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; | ||
| 77 | |||
| 78 | ldoln-in-supply = <&vdd_smps10_out2>; | ||
| 79 | |||
| 80 | regulators { | ||
| 81 | smps123 { | ||
| 82 | regulator-name = "vd-cpu"; | ||
| 83 | regulator-min-microvolt = <1000000>; | ||
| 84 | regulator-max-microvolt = <1000000>; | ||
| 85 | regulator-always-on; | ||
| 86 | regulator-boot-on; | ||
| 87 | }; | ||
| 88 | |||
| 89 | smps45 { | ||
| 90 | regulator-name = "vd-soc"; | ||
| 91 | regulator-min-microvolt = <1100000>; | ||
| 92 | regulator-max-microvolt = <1100000>; | ||
| 93 | regulator-always-on; | ||
| 94 | regulator-boot-on; | ||
| 95 | }; | ||
| 96 | |||
| 97 | smps6 { | ||
| 98 | regulator-name = "va-lcd-hv"; | ||
| 99 | regulator-min-microvolt = <3000000>; | ||
| 100 | regulator-max-microvolt = <3000000>; | ||
| 101 | regulator-always-on; | ||
| 102 | regulator-boot-on; | ||
| 103 | }; | ||
| 104 | |||
| 105 | smps7 { | ||
| 106 | regulator-name = "vd-ddr"; | ||
| 107 | regulator-min-microvolt = <1350000>; | ||
| 108 | regulator-max-microvolt = <1350000>; | ||
| 109 | regulator-always-on; | ||
| 110 | regulator-boot-on; | ||
| 111 | }; | ||
| 112 | |||
| 113 | vdd_1v8: smps8 { | ||
| 114 | regulator-name = "vs-pmu-1v8"; | ||
| 115 | regulator-min-microvolt = <1800000>; | ||
| 116 | regulator-max-microvolt = <1800000>; | ||
| 117 | regulator-always-on; | ||
| 118 | regulator-boot-on; | ||
| 119 | }; | ||
| 120 | |||
| 121 | vdd_2v9_sys: smps9 { | ||
| 122 | regulator-name = "vs-sys-2v9"; | ||
| 123 | regulator-min-microvolt = <2900000>; | ||
| 124 | regulator-max-microvolt = <2900000>; | ||
| 125 | regulator-always-on; | ||
| 126 | regulator-boot-on; | ||
| 127 | }; | ||
| 128 | |||
| 129 | vdd_smps10_out1: smps10_out1 { | ||
| 130 | regulator-name = "vd-smps10-out1"; | ||
| 131 | regulator-min-microvolt = <5000000>; | ||
| 132 | regulator-max-microvolt = <5000000>; | ||
| 133 | regulator-always-on; | ||
| 134 | regulator-boot-on; | ||
| 135 | }; | ||
| 136 | |||
| 137 | vdd_smps10_out2: smps10_out2 { | ||
| 138 | regulator-name = "vd-smps10-out2"; | ||
| 139 | regulator-min-microvolt = <5000000>; | ||
| 140 | regulator-max-microvolt = <5000000>; | ||
| 141 | regulator-always-on; | ||
| 142 | regulator-boot-on; | ||
| 143 | }; | ||
| 144 | |||
| 145 | ldo1 { | ||
| 146 | regulator-name = "va-pllx"; | ||
| 147 | regulator-min-microvolt = <1050000>; | ||
| 148 | regulator-max-microvolt = <1050000>; | ||
| 149 | regulator-always-on; | ||
| 150 | regulator-boot-on; | ||
| 151 | }; | ||
| 152 | |||
| 153 | vdd_1v2_ap: ldo2 { | ||
| 154 | regulator-name = "va-ap-1v2"; | ||
| 155 | regulator-min-microvolt = <1200000>; | ||
| 156 | regulator-max-microvolt = <1200000>; | ||
| 157 | regulator-always-on; | ||
| 158 | regulator-boot-on; | ||
| 159 | }; | ||
| 160 | |||
| 161 | ldo3 { | ||
| 162 | regulator-name = "vd-fuse"; | ||
| 163 | regulator-min-microvolt = <1800000>; | ||
| 164 | regulator-max-microvolt = <1800000>; | ||
| 165 | regulator-always-on; | ||
| 166 | regulator-boot-on; | ||
| 167 | }; | ||
| 168 | |||
| 169 | ldo4 { | ||
| 170 | regulator-name = "vd-ts-hv"; | ||
| 171 | regulator-min-microvolt = <3200000>; | ||
| 172 | regulator-max-microvolt = <3200000>; | ||
| 173 | regulator-always-on; | ||
| 174 | regulator-boot-on; | ||
| 175 | }; | ||
| 176 | |||
| 177 | ldo5 { | ||
| 178 | regulator-name = "va-cam2-hv"; | ||
| 179 | regulator-min-microvolt = <2700000>; | ||
| 180 | regulator-max-microvolt = <2700000>; | ||
| 181 | }; | ||
| 182 | |||
| 183 | ldo6 { | ||
| 184 | regulator-name = "va-sns-hv"; | ||
| 185 | regulator-min-microvolt = <2850000>; | ||
| 186 | regulator-max-microvolt = <2850000>; | ||
| 187 | }; | ||
| 188 | |||
| 189 | ldo7 { | ||
| 190 | regulator-name = "va-cam1-hv"; | ||
| 191 | regulator-min-microvolt = <2700000>; | ||
| 192 | regulator-max-microvolt = <2700000>; | ||
| 193 | }; | ||
| 194 | |||
| 195 | ldo8 { | ||
| 196 | regulator-name = "va-ap-rtc"; | ||
| 197 | regulator-min-microvolt = <1100000>; | ||
| 198 | regulator-max-microvolt = <1100000>; | ||
| 199 | ti,enable-ldo8-tracking; | ||
| 200 | regulator-always-on; | ||
| 201 | regulator-boot-on; | ||
| 202 | }; | ||
| 203 | |||
| 204 | ldo9 { | ||
| 205 | regulator-name = "vi-sdcard"; | ||
| 206 | regulator-min-microvolt = <2900000>; | ||
| 207 | regulator-max-microvolt = <2900000>; | ||
| 208 | }; | ||
| 209 | |||
| 210 | ldousb { | ||
| 211 | regulator-name = "avdd-usb"; | ||
| 212 | regulator-min-microvolt = <3300000>; | ||
| 213 | regulator-max-microvolt = <3300000>; | ||
| 214 | regulator-always-on; | ||
| 215 | regulator-boot-on; | ||
| 216 | }; | ||
| 217 | |||
| 218 | ldoln { | ||
| 219 | regulator-name = "va-hdmi"; | ||
| 220 | regulator-min-microvolt = <3300000>; | ||
| 221 | regulator-max-microvolt = <3300000>; | ||
| 222 | }; | ||
| 223 | }; | ||
| 224 | }; | ||
| 225 | |||
| 226 | rtc { | ||
| 227 | compatible = "ti,palmas-rtc"; | ||
| 228 | interrupt-parent = <&palmas>; | ||
| 229 | interrupts = <8 0>; | ||
| 230 | }; | ||
| 231 | |||
| 232 | }; | ||
| 233 | }; | ||
| 234 | |||
| 235 | pmc@7000e400 { | ||
| 236 | nvidia,invert-interrupt; | ||
| 237 | }; | ||
| 238 | |||
| 239 | /* eMMC */ | ||
| 240 | sdhci@78000600 { | ||
| 241 | status = "okay"; | ||
| 242 | bus-width = <8>; | ||
| 243 | vmmc-supply = <&vdd_1v8>; | ||
| 244 | non-removable; | ||
| 245 | }; | ||
| 246 | |||
| 247 | usb@7d000000 { | ||
| 248 | status = "okay"; | ||
| 249 | }; | ||
| 250 | |||
| 251 | usb-phy@7d000000 { | ||
| 252 | status = "okay"; | ||
| 253 | nvidia,xcvr-setup = <7>; | ||
| 254 | nvidia,xcvr-lsfslew = <2>; | ||
| 255 | nvidia,xcvr-lsrslew = <2>; | ||
| 256 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | ||
| 257 | /* Should be changed to "otg" once we have vbus_supply */ | ||
| 258 | /* As of now, USB devices need to be powered externally */ | ||
| 259 | dr_mode = "host"; | ||
| 260 | }; | ||
| 261 | |||
| 262 | backlight: backlight { | ||
| 263 | compatible = "pwm-backlight"; | ||
| 264 | pwms = <&pwm 1 40000>; | ||
| 265 | |||
| 266 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
| 267 | default-brightness-level = <6>; | ||
| 268 | |||
| 269 | power-supply = <&lcd_bl_en>; | ||
| 270 | }; | ||
| 271 | |||
| 272 | clocks { | ||
| 273 | compatible = "simple-bus"; | ||
| 274 | #address-cells = <1>; | ||
| 275 | #size-cells = <0>; | ||
| 276 | |||
| 277 | clk32k_in: clock { | ||
| 278 | compatible = "fixed-clock"; | ||
| 279 | reg = <0>; | ||
| 280 | #clock-cells = <0>; | ||
| 281 | clock-frequency = <32768>; | ||
| 282 | }; | ||
| 283 | }; | ||
| 284 | |||
| 285 | gpio-keys { | ||
| 286 | compatible = "gpio-keys"; | ||
| 287 | |||
| 288 | power { | ||
| 289 | label = "Power"; | ||
| 290 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; | ||
| 291 | linux,code = <KEY_POWER>; | ||
| 292 | gpio-key,wakeup; | ||
| 293 | }; | ||
| 294 | |||
| 295 | volume_down { | ||
| 296 | label = "Volume Down"; | ||
| 297 | gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; | ||
| 298 | linux,code = <KEY_VOLUMEDOWN>; | ||
| 299 | }; | ||
| 300 | |||
| 301 | volume_up { | ||
| 302 | label = "Volume Up"; | ||
| 303 | gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; | ||
| 304 | linux,code = <KEY_VOLUMEUP>; | ||
| 305 | }; | ||
| 306 | }; | ||
| 307 | |||
| 308 | regulators { | ||
| 309 | compatible = "simple-bus"; | ||
| 310 | #address-cells = <1>; | ||
| 311 | #size-cells = <0>; | ||
| 312 | |||
| 313 | /* FIXME: output of BQ24192 */ | ||
| 314 | vs_sys: regulator@0 { | ||
| 315 | compatible = "regulator-fixed"; | ||
| 316 | reg = <0>; | ||
| 317 | regulator-name = "VS_SYS"; | ||
| 318 | regulator-min-microvolt = <4200000>; | ||
| 319 | regulator-max-microvolt = <4200000>; | ||
| 320 | regulator-always-on; | ||
| 321 | regulator-boot-on; | ||
| 322 | }; | ||
| 323 | |||
| 324 | lcd_bl_en: regulator@1 { | ||
| 325 | compatible = "regulator-fixed"; | ||
| 326 | reg = <1>; | ||
| 327 | regulator-name = "VDD_LCD_BL"; | ||
| 328 | regulator-min-microvolt = <16500000>; | ||
| 329 | regulator-max-microvolt = <16500000>; | ||
| 330 | gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; | ||
| 331 | enable-active-high; | ||
| 332 | vin-supply = <&vs_sys>; | ||
| 333 | regulator-boot-on; | ||
| 334 | }; | ||
| 335 | |||
| 336 | vdd_lcd: regulator@2 { | ||
| 337 | compatible = "regulator-fixed"; | ||
| 338 | reg = <2>; | ||
| 339 | regulator-name = "VD_LCD_1V8"; | ||
| 340 | regulator-min-microvolt = <1800000>; | ||
| 341 | regulator-max-microvolt = <1800000>; | ||
| 342 | gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; | ||
| 343 | enable-active-high; | ||
| 344 | vin-supply = <&vdd_1v8>; | ||
| 345 | regulator-boot-on; | ||
| 346 | }; | ||
| 347 | }; | ||
| 348 | }; | ||
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts new file mode 100644 index 000000000000..e31fb61a81d3 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts | |||
| @@ -0,0 +1,1827 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | #include <dt-bindings/input/input.h> | ||
| 4 | #include "tegra124.dtsi" | ||
| 5 | |||
| 6 | / { | ||
| 7 | model = "NVIDIA Tegra124 Jetson TK1"; | ||
| 8 | compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; | ||
| 9 | |||
| 10 | aliases { | ||
| 11 | rtc0 = "/i2c@0,7000d000/pmic@40"; | ||
| 12 | rtc1 = "/rtc@0,7000e000"; | ||
| 13 | }; | ||
| 14 | |||
| 15 | memory { | ||
| 16 | reg = <0x0 0x80000000 0x0 0x80000000>; | ||
| 17 | }; | ||
| 18 | |||
| 19 | host1x@0,50000000 { | ||
| 20 | hdmi@0,54280000 { | ||
| 21 | status = "okay"; | ||
| 22 | |||
| 23 | hdmi-supply = <&vdd_5v0_hdmi>; | ||
| 24 | pll-supply = <&vdd_hdmi_pll>; | ||
| 25 | vdd-supply = <&vdd_3v3_hdmi>; | ||
| 26 | |||
| 27 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | ||
| 28 | nvidia,hpd-gpio = | ||
| 29 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | |||
| 33 | pinmux: pinmux@0,70000868 { | ||
| 34 | pinctrl-names = "default"; | ||
| 35 | pinctrl-0 = <&state_default>; | ||
| 36 | |||
| 37 | state_default: pinmux { | ||
| 38 | clk_32k_out_pa0 { | ||
| 39 | nvidia,pins = "clk_32k_out_pa0"; | ||
| 40 | nvidia,function = "soc"; | ||
| 41 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 42 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 43 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 44 | }; | ||
| 45 | uart3_cts_n_pa1 { | ||
| 46 | nvidia,pins = "uart3_cts_n_pa1"; | ||
| 47 | nvidia,function = "uartc"; | ||
| 48 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 49 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 50 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 51 | }; | ||
| 52 | dap2_fs_pa2 { | ||
| 53 | nvidia,pins = "dap2_fs_pa2"; | ||
| 54 | nvidia,function = "i2s1"; | ||
| 55 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 56 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 57 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 58 | }; | ||
| 59 | dap2_sclk_pa3 { | ||
| 60 | nvidia,pins = "dap2_sclk_pa3"; | ||
| 61 | nvidia,function = "i2s1"; | ||
| 62 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 63 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 64 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 65 | }; | ||
| 66 | dap2_din_pa4 { | ||
| 67 | nvidia,pins = "dap2_din_pa4"; | ||
| 68 | nvidia,function = "i2s1"; | ||
| 69 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 70 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 71 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 72 | }; | ||
| 73 | dap2_dout_pa5 { | ||
| 74 | nvidia,pins = "dap2_dout_pa5"; | ||
| 75 | nvidia,function = "i2s1"; | ||
| 76 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 77 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 78 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 79 | }; | ||
| 80 | sdmmc3_clk_pa6 { | ||
| 81 | nvidia,pins = "sdmmc3_clk_pa6"; | ||
| 82 | nvidia,function = "sdmmc3"; | ||
| 83 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 84 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 85 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 86 | }; | ||
| 87 | sdmmc3_cmd_pa7 { | ||
| 88 | nvidia,pins = "sdmmc3_cmd_pa7"; | ||
| 89 | nvidia,function = "sdmmc3"; | ||
| 90 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 91 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 92 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 93 | }; | ||
| 94 | pb0 { | ||
| 95 | nvidia,pins = "pb0"; | ||
| 96 | nvidia,function = "uartd"; | ||
| 97 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 98 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 99 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 100 | }; | ||
| 101 | pb1 { | ||
| 102 | nvidia,pins = "pb1"; | ||
| 103 | nvidia,function = "uartd"; | ||
| 104 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 105 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 106 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 107 | }; | ||
| 108 | sdmmc3_dat3_pb4 { | ||
| 109 | nvidia,pins = "sdmmc3_dat3_pb4"; | ||
| 110 | nvidia,function = "sdmmc3"; | ||
| 111 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 112 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 113 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 114 | }; | ||
| 115 | sdmmc3_dat2_pb5 { | ||
| 116 | nvidia,pins = "sdmmc3_dat2_pb5"; | ||
| 117 | nvidia,function = "sdmmc3"; | ||
| 118 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 119 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 120 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 121 | }; | ||
| 122 | sdmmc3_dat1_pb6 { | ||
| 123 | nvidia,pins = "sdmmc3_dat1_pb6"; | ||
| 124 | nvidia,function = "sdmmc3"; | ||
| 125 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 126 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 127 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 128 | }; | ||
| 129 | sdmmc3_dat0_pb7 { | ||
| 130 | nvidia,pins = "sdmmc3_dat0_pb7"; | ||
| 131 | nvidia,function = "sdmmc3"; | ||
| 132 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 133 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 134 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 135 | }; | ||
| 136 | uart3_rts_n_pc0 { | ||
| 137 | nvidia,pins = "uart3_rts_n_pc0"; | ||
| 138 | nvidia,function = "uartc"; | ||
| 139 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 140 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 141 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 142 | }; | ||
| 143 | uart2_txd_pc2 { | ||
| 144 | nvidia,pins = "uart2_txd_pc2"; | ||
| 145 | nvidia,function = "irda"; | ||
| 146 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 147 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 148 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 149 | }; | ||
| 150 | uart2_rxd_pc3 { | ||
| 151 | nvidia,pins = "uart2_rxd_pc3"; | ||
| 152 | nvidia,function = "irda"; | ||
| 153 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 154 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 155 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 156 | }; | ||
| 157 | gen1_i2c_scl_pc4 { | ||
| 158 | nvidia,pins = "gen1_i2c_scl_pc4"; | ||
| 159 | nvidia,function = "i2c1"; | ||
| 160 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 161 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 162 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 163 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
| 164 | }; | ||
| 165 | gen1_i2c_sda_pc5 { | ||
| 166 | nvidia,pins = "gen1_i2c_sda_pc5"; | ||
| 167 | nvidia,function = "i2c1"; | ||
| 168 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 169 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 170 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 171 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
| 172 | }; | ||
| 173 | pc7 { | ||
| 174 | nvidia,pins = "pc7"; | ||
| 175 | nvidia,function = "rsvd1"; | ||
| 176 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 177 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 178 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 179 | }; | ||
| 180 | pg0 { | ||
| 181 | nvidia,pins = "pg0"; | ||
| 182 | nvidia,function = "rsvd1"; | ||
| 183 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 184 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 185 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 186 | }; | ||
| 187 | pg1 { | ||
| 188 | nvidia,pins = "pg1"; | ||
| 189 | nvidia,function = "rsvd1"; | ||
| 190 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 191 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 192 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 193 | }; | ||
| 194 | pg2 { | ||
| 195 | nvidia,pins = "pg2"; | ||
| 196 | nvidia,function = "rsvd1"; | ||
| 197 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 198 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 199 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 200 | }; | ||
| 201 | pg3 { | ||
| 202 | nvidia,pins = "pg3"; | ||
| 203 | nvidia,function = "rsvd1"; | ||
| 204 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 205 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 206 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 207 | }; | ||
| 208 | pg4 { | ||
| 209 | nvidia,pins = "pg4"; | ||
| 210 | nvidia,function = "spi4"; | ||
| 211 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 212 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 213 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 214 | }; | ||
| 215 | pg5 { | ||
| 216 | nvidia,pins = "pg5"; | ||
| 217 | nvidia,function = "spi4"; | ||
| 218 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 219 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 220 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 221 | }; | ||
| 222 | pg6 { | ||
| 223 | nvidia,pins = "pg6"; | ||
| 224 | nvidia,function = "spi4"; | ||
| 225 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 226 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 227 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 228 | }; | ||
| 229 | pg7 { | ||
| 230 | nvidia,pins = "pg7"; | ||
| 231 | nvidia,function = "spi4"; | ||
| 232 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 233 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 234 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 235 | }; | ||
| 236 | ph0 { | ||
| 237 | nvidia,pins = "ph0"; | ||
| 238 | nvidia,function = "gmi"; | ||
| 239 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 240 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 241 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 242 | }; | ||
| 243 | ph1 { | ||
| 244 | nvidia,pins = "ph1"; | ||
| 245 | nvidia,function = "pwm1"; | ||
| 246 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 247 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 248 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 249 | }; | ||
| 250 | ph2 { | ||
| 251 | nvidia,pins = "ph2"; | ||
| 252 | nvidia,function = "gmi"; | ||
| 253 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 254 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 255 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 256 | }; | ||
| 257 | ph3 { | ||
| 258 | nvidia,pins = "ph3"; | ||
| 259 | nvidia,function = "gmi"; | ||
| 260 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 261 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 262 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 263 | }; | ||
| 264 | ph4 { | ||
| 265 | nvidia,pins = "ph4"; | ||
| 266 | nvidia,function = "rsvd2"; | ||
| 267 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 268 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 269 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 270 | }; | ||
| 271 | ph5 { | ||
| 272 | nvidia,pins = "ph5"; | ||
| 273 | nvidia,function = "rsvd2"; | ||
| 274 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 275 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 276 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 277 | }; | ||
| 278 | ph6 { | ||
| 279 | nvidia,pins = "ph6"; | ||
| 280 | nvidia,function = "gmi"; | ||
| 281 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 282 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 283 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 284 | }; | ||
| 285 | ph7 { | ||
| 286 | nvidia,pins = "ph7"; | ||
| 287 | nvidia,function = "gmi"; | ||
| 288 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 289 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 290 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 291 | }; | ||
| 292 | pi0 { | ||
| 293 | nvidia,pins = "pi0"; | ||
| 294 | nvidia,function = "rsvd1"; | ||
| 295 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 296 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 297 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 298 | }; | ||
| 299 | pi1 { | ||
| 300 | nvidia,pins = "pi1"; | ||
| 301 | nvidia,function = "rsvd1"; | ||
| 302 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 303 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 304 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 305 | }; | ||
| 306 | pi2 { | ||
| 307 | nvidia,pins = "pi2"; | ||
| 308 | nvidia,function = "rsvd4"; | ||
| 309 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 310 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 311 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 312 | }; | ||
| 313 | pi3 { | ||
| 314 | nvidia,pins = "pi3"; | ||
| 315 | nvidia,function = "spi4"; | ||
| 316 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 317 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 318 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 319 | }; | ||
| 320 | pi4 { | ||
| 321 | nvidia,pins = "pi4"; | ||
| 322 | nvidia,function = "gmi"; | ||
| 323 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 324 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 325 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 326 | }; | ||
| 327 | pi5 { | ||
| 328 | nvidia,pins = "pi5"; | ||
| 329 | nvidia,function = "rsvd2"; | ||
| 330 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 331 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 332 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 333 | }; | ||
| 334 | pi6 { | ||
| 335 | nvidia,pins = "pi6"; | ||
| 336 | nvidia,function = "rsvd1"; | ||
| 337 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 338 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 339 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 340 | }; | ||
| 341 | pi7 { | ||
| 342 | nvidia,pins = "pi7"; | ||
| 343 | nvidia,function = "rsvd1"; | ||
| 344 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 345 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 346 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 347 | }; | ||
| 348 | pj0 { | ||
| 349 | nvidia,pins = "pj0"; | ||
| 350 | nvidia,function = "rsvd1"; | ||
| 351 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 352 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 353 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 354 | }; | ||
| 355 | pj2 { | ||
| 356 | nvidia,pins = "pj2"; | ||
| 357 | nvidia,function = "rsvd1"; | ||
| 358 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 359 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 360 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 361 | }; | ||
| 362 | uart2_cts_n_pj5 { | ||
| 363 | nvidia,pins = "uart2_cts_n_pj5"; | ||
| 364 | nvidia,function = "uartb"; | ||
| 365 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 366 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 367 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 368 | }; | ||
| 369 | uart2_rts_n_pj6 { | ||
| 370 | nvidia,pins = "uart2_rts_n_pj6"; | ||
| 371 | nvidia,function = "uartb"; | ||
| 372 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 373 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 374 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 375 | }; | ||
| 376 | pj7 { | ||
| 377 | nvidia,pins = "pj7"; | ||
| 378 | nvidia,function = "uartd"; | ||
| 379 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 380 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 381 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 382 | }; | ||
| 383 | pk0 { | ||
| 384 | nvidia,pins = "pk0"; | ||
| 385 | nvidia,function = "soc"; | ||
| 386 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 387 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 388 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 389 | }; | ||
| 390 | pk1 { | ||
| 391 | nvidia,pins = "pk1"; | ||
| 392 | nvidia,function = "rsvd4"; | ||
| 393 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 394 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 395 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 396 | }; | ||
| 397 | pk2 { | ||
| 398 | nvidia,pins = "pk2"; | ||
| 399 | nvidia,function = "rsvd1"; | ||
| 400 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 401 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 402 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 403 | }; | ||
| 404 | pk3 { | ||
| 405 | nvidia,pins = "pk3"; | ||
| 406 | nvidia,function = "gmi"; | ||
| 407 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 408 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 409 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 410 | }; | ||
| 411 | pk4 { | ||
| 412 | nvidia,pins = "pk4"; | ||
| 413 | nvidia,function = "rsvd2"; | ||
| 414 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 415 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 416 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 417 | }; | ||
| 418 | spdif_out_pk5 { | ||
| 419 | nvidia,pins = "spdif_out_pk5"; | ||
| 420 | nvidia,function = "rsvd2"; | ||
| 421 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 422 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 423 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 424 | }; | ||
| 425 | spdif_in_pk6 { | ||
| 426 | nvidia,pins = "spdif_in_pk6"; | ||
| 427 | nvidia,function = "rsvd2"; | ||
| 428 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 429 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 430 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 431 | }; | ||
| 432 | pk7 { | ||
| 433 | nvidia,pins = "pk7"; | ||
| 434 | nvidia,function = "uartd"; | ||
| 435 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 436 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 437 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 438 | }; | ||
| 439 | dap1_fs_pn0 { | ||
| 440 | nvidia,pins = "dap1_fs_pn0"; | ||
| 441 | nvidia,function = "i2s0"; | ||
| 442 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 443 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 444 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 445 | }; | ||
| 446 | dap1_din_pn1 { | ||
| 447 | nvidia,pins = "dap1_din_pn1"; | ||
| 448 | nvidia,function = "i2s0"; | ||
| 449 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 450 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 451 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 452 | }; | ||
| 453 | dap1_dout_pn2 { | ||
| 454 | nvidia,pins = "dap1_dout_pn2"; | ||
| 455 | nvidia,function = "sata"; | ||
| 456 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 457 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 458 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 459 | }; | ||
| 460 | dap1_sclk_pn3 { | ||
| 461 | nvidia,pins = "dap1_sclk_pn3"; | ||
| 462 | nvidia,function = "i2s0"; | ||
| 463 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 464 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 465 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 466 | }; | ||
| 467 | usb_vbus_en0_pn4 { | ||
| 468 | nvidia,pins = "usb_vbus_en0_pn4"; | ||
| 469 | nvidia,function = "usb"; | ||
| 470 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 471 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 472 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 473 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
| 474 | }; | ||
| 475 | usb_vbus_en1_pn5 { | ||
| 476 | nvidia,pins = "usb_vbus_en1_pn5"; | ||
| 477 | nvidia,function = "usb"; | ||
| 478 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 479 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 480 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 481 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
| 482 | }; | ||
| 483 | hdmi_int_pn7 { | ||
| 484 | nvidia,pins = "hdmi_int_pn7"; | ||
| 485 | nvidia,function = "rsvd1"; | ||
| 486 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 487 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 488 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 489 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | ||
| 490 | }; | ||
| 491 | ulpi_data7_po0 { | ||
| 492 | nvidia,pins = "ulpi_data7_po0"; | ||
| 493 | nvidia,function = "ulpi"; | ||
| 494 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 495 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 496 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 497 | }; | ||
| 498 | ulpi_data0_po1 { | ||
| 499 | nvidia,pins = "ulpi_data0_po1"; | ||
| 500 | nvidia,function = "ulpi"; | ||
| 501 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 502 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 503 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 504 | }; | ||
| 505 | ulpi_data1_po2 { | ||
| 506 | nvidia,pins = "ulpi_data1_po2"; | ||
| 507 | nvidia,function = "ulpi"; | ||
| 508 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 509 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 510 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 511 | }; | ||
| 512 | ulpi_data2_po3 { | ||
| 513 | nvidia,pins = "ulpi_data2_po3"; | ||
| 514 | nvidia,function = "ulpi"; | ||
| 515 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 516 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 517 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 518 | }; | ||
| 519 | ulpi_data3_po4 { | ||
| 520 | nvidia,pins = "ulpi_data3_po4"; | ||
| 521 | nvidia,function = "ulpi"; | ||
| 522 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 523 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 524 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 525 | }; | ||
| 526 | ulpi_data4_po5 { | ||
| 527 | nvidia,pins = "ulpi_data4_po5"; | ||
| 528 | nvidia,function = "ulpi"; | ||
| 529 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 530 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 531 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 532 | }; | ||
| 533 | ulpi_data5_po6 { | ||
| 534 | nvidia,pins = "ulpi_data5_po6"; | ||
| 535 | nvidia,function = "ulpi"; | ||
| 536 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 537 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 538 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 539 | }; | ||
| 540 | ulpi_data6_po7 { | ||
| 541 | nvidia,pins = "ulpi_data6_po7"; | ||
| 542 | nvidia,function = "ulpi"; | ||
| 543 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 544 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 545 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 546 | }; | ||
| 547 | dap3_fs_pp0 { | ||
| 548 | nvidia,pins = "dap3_fs_pp0"; | ||
| 549 | nvidia,function = "i2s2"; | ||
| 550 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 551 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 552 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 553 | }; | ||
| 554 | dap3_din_pp1 { | ||
| 555 | nvidia,pins = "dap3_din_pp1"; | ||
| 556 | nvidia,function = "i2s2"; | ||
| 557 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 558 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 559 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 560 | }; | ||
| 561 | dap3_dout_pp2 { | ||
| 562 | nvidia,pins = "dap3_dout_pp2"; | ||
| 563 | nvidia,function = "rsvd4"; | ||
| 564 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 565 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 566 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 567 | }; | ||
| 568 | dap3_sclk_pp3 { | ||
| 569 | nvidia,pins = "dap3_sclk_pp3"; | ||
| 570 | nvidia,function = "rsvd3"; | ||
| 571 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 572 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 573 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 574 | }; | ||
| 575 | dap4_fs_pp4 { | ||
| 576 | nvidia,pins = "dap4_fs_pp4"; | ||
| 577 | nvidia,function = "i2s3"; | ||
| 578 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 579 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 580 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 581 | }; | ||
| 582 | dap4_din_pp5 { | ||
| 583 | nvidia,pins = "dap4_din_pp5"; | ||
| 584 | nvidia,function = "i2s3"; | ||
| 585 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 586 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 587 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 588 | }; | ||
| 589 | dap4_dout_pp6 { | ||
| 590 | nvidia,pins = "dap4_dout_pp6"; | ||
| 591 | nvidia,function = "i2s3"; | ||
| 592 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 593 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 594 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 595 | }; | ||
| 596 | dap4_sclk_pp7 { | ||
| 597 | nvidia,pins = "dap4_sclk_pp7"; | ||
| 598 | nvidia,function = "i2s3"; | ||
| 599 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 600 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 601 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 602 | }; | ||
| 603 | kb_col0_pq0 { | ||
| 604 | nvidia,pins = "kb_col0_pq0"; | ||
| 605 | nvidia,function = "rsvd2"; | ||
| 606 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 607 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 608 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 609 | }; | ||
| 610 | kb_col1_pq1 { | ||
| 611 | nvidia,pins = "kb_col1_pq1"; | ||
| 612 | nvidia,function = "rsvd2"; | ||
| 613 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 614 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 615 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 616 | }; | ||
| 617 | kb_col2_pq2 { | ||
| 618 | nvidia,pins = "kb_col2_pq2"; | ||
| 619 | nvidia,function = "rsvd2"; | ||
| 620 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 621 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 622 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 623 | }; | ||
| 624 | kb_col3_pq3 { | ||
| 625 | nvidia,pins = "kb_col3_pq3"; | ||
| 626 | nvidia,function = "kbc"; | ||
| 627 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 628 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 629 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 630 | }; | ||
| 631 | kb_col4_pq4 { | ||
| 632 | nvidia,pins = "kb_col4_pq4"; | ||
| 633 | nvidia,function = "sdmmc3"; | ||
| 634 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 635 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 636 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 637 | }; | ||
| 638 | kb_col5_pq5 { | ||
| 639 | nvidia,pins = "kb_col5_pq5"; | ||
| 640 | nvidia,function = "rsvd2"; | ||
| 641 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 642 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 643 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 644 | }; | ||
| 645 | kb_col6_pq6 { | ||
| 646 | nvidia,pins = "kb_col6_pq6"; | ||
| 647 | nvidia,function = "rsvd2"; | ||
| 648 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 649 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 650 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 651 | }; | ||
| 652 | kb_col7_pq7 { | ||
| 653 | nvidia,pins = "kb_col7_pq7"; | ||
| 654 | nvidia,function = "rsvd2"; | ||
| 655 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 656 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 657 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 658 | }; | ||
| 659 | kb_row0_pr0 { | ||
| 660 | nvidia,pins = "kb_row0_pr0"; | ||
| 661 | nvidia,function = "rsvd2"; | ||
| 662 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 663 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 664 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 665 | }; | ||
| 666 | kb_row1_pr1 { | ||
| 667 | nvidia,pins = "kb_row1_pr1"; | ||
| 668 | nvidia,function = "rsvd2"; | ||
| 669 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 670 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 671 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 672 | }; | ||
| 673 | kb_row2_pr2 { | ||
| 674 | nvidia,pins = "kb_row2_pr2"; | ||
| 675 | nvidia,function = "rsvd2"; | ||
| 676 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 677 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 678 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 679 | }; | ||
| 680 | kb_row3_pr3 { | ||
| 681 | nvidia,pins = "kb_row3_pr3"; | ||
| 682 | nvidia,function = "sys"; | ||
| 683 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 684 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 685 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 686 | }; | ||
| 687 | kb_row4_pr4 { | ||
| 688 | nvidia,pins = "kb_row4_pr4"; | ||
| 689 | nvidia,function = "rsvd3"; | ||
| 690 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 691 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 692 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 693 | }; | ||
| 694 | kb_row5_pr5 { | ||
| 695 | nvidia,pins = "kb_row5_pr5"; | ||
| 696 | nvidia,function = "rsvd3"; | ||
| 697 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 698 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 699 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 700 | }; | ||
| 701 | kb_row6_pr6 { | ||
| 702 | nvidia,pins = "kb_row6_pr6"; | ||
| 703 | nvidia,function = "displaya_alt"; | ||
| 704 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 705 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 706 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 707 | }; | ||
| 708 | kb_row7_pr7 { | ||
| 709 | nvidia,pins = "kb_row7_pr7"; | ||
| 710 | nvidia,function = "rsvd2"; | ||
| 711 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 712 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 713 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 714 | }; | ||
| 715 | kb_row8_ps0 { | ||
| 716 | nvidia,pins = "kb_row8_ps0"; | ||
| 717 | nvidia,function = "rsvd2"; | ||
| 718 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 719 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 720 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 721 | }; | ||
| 722 | kb_row9_ps1 { | ||
| 723 | nvidia,pins = "kb_row9_ps1"; | ||
| 724 | nvidia,function = "rsvd2"; | ||
| 725 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 726 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 727 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 728 | }; | ||
| 729 | kb_row10_ps2 { | ||
| 730 | nvidia,pins = "kb_row10_ps2"; | ||
| 731 | nvidia,function = "rsvd2"; | ||
| 732 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 733 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 734 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 735 | }; | ||
| 736 | kb_row11_ps3 { | ||
| 737 | nvidia,pins = "kb_row11_ps3"; | ||
| 738 | nvidia,function = "rsvd2"; | ||
| 739 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 740 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 741 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 742 | }; | ||
| 743 | kb_row12_ps4 { | ||
| 744 | nvidia,pins = "kb_row12_ps4"; | ||
| 745 | nvidia,function = "rsvd2"; | ||
| 746 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 747 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 748 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 749 | }; | ||
| 750 | kb_row13_ps5 { | ||
| 751 | nvidia,pins = "kb_row13_ps5"; | ||
| 752 | nvidia,function = "rsvd2"; | ||
| 753 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 754 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 755 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 756 | }; | ||
| 757 | kb_row14_ps6 { | ||
| 758 | nvidia,pins = "kb_row14_ps6"; | ||
| 759 | nvidia,function = "rsvd2"; | ||
| 760 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 761 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 762 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 763 | }; | ||
| 764 | kb_row15_ps7 { | ||
| 765 | nvidia,pins = "kb_row15_ps7"; | ||
| 766 | nvidia,function = "soc"; | ||
| 767 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 768 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 769 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 770 | }; | ||
| 771 | kb_row16_pt0 { | ||
| 772 | nvidia,pins = "kb_row16_pt0"; | ||
| 773 | nvidia,function = "rsvd2"; | ||
| 774 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 775 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 776 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 777 | }; | ||
| 778 | kb_row17_pt1 { | ||
| 779 | nvidia,pins = "kb_row17_pt1"; | ||
| 780 | nvidia,function = "rsvd2"; | ||
| 781 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 782 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 783 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 784 | }; | ||
| 785 | gen2_i2c_scl_pt5 { | ||
| 786 | nvidia,pins = "gen2_i2c_scl_pt5"; | ||
| 787 | nvidia,function = "i2c2"; | ||
| 788 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 789 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 790 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 791 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
| 792 | }; | ||
| 793 | gen2_i2c_sda_pt6 { | ||
| 794 | nvidia,pins = "gen2_i2c_sda_pt6"; | ||
| 795 | nvidia,function = "i2c2"; | ||
| 796 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 797 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 798 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 799 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
| 800 | }; | ||
| 801 | sdmmc4_cmd_pt7 { | ||
| 802 | nvidia,pins = "sdmmc4_cmd_pt7"; | ||
| 803 | nvidia,function = "sdmmc4"; | ||
| 804 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 805 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 806 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 807 | }; | ||
| 808 | pu0 { | ||
| 809 | nvidia,pins = "pu0"; | ||
| 810 | nvidia,function = "rsvd4"; | ||
| 811 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 812 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 813 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 814 | }; | ||
| 815 | pu1 { | ||
| 816 | nvidia,pins = "pu1"; | ||
| 817 | nvidia,function = "rsvd1"; | ||
| 818 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 819 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 820 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 821 | }; | ||
| 822 | pu2 { | ||
| 823 | nvidia,pins = "pu2"; | ||
| 824 | nvidia,function = "rsvd1"; | ||
| 825 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 826 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 827 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 828 | }; | ||
| 829 | pu3 { | ||
| 830 | nvidia,pins = "pu3"; | ||
| 831 | nvidia,function = "gmi"; | ||
| 832 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 833 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 834 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 835 | }; | ||
| 836 | pu4 { | ||
| 837 | nvidia,pins = "pu4"; | ||
| 838 | nvidia,function = "gmi"; | ||
| 839 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 840 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 841 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 842 | }; | ||
| 843 | pu5 { | ||
| 844 | nvidia,pins = "pu5"; | ||
| 845 | nvidia,function = "gmi"; | ||
| 846 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 847 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 848 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 849 | }; | ||
| 850 | pu6 { | ||
| 851 | nvidia,pins = "pu6"; | ||
| 852 | nvidia,function = "rsvd3"; | ||
| 853 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 854 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 855 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 856 | }; | ||
| 857 | pv0 { | ||
| 858 | nvidia,pins = "pv0"; | ||
| 859 | nvidia,function = "rsvd1"; | ||
| 860 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 861 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 862 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 863 | }; | ||
| 864 | pv1 { | ||
| 865 | nvidia,pins = "pv1"; | ||
| 866 | nvidia,function = "rsvd1"; | ||
| 867 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 868 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 869 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 870 | }; | ||
| 871 | sdmmc3_cd_n_pv2 { | ||
| 872 | nvidia,pins = "sdmmc3_cd_n_pv2"; | ||
| 873 | nvidia,function = "sdmmc3"; | ||
| 874 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 875 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 876 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 877 | }; | ||
| 878 | sdmmc1_wp_n_pv3 { | ||
| 879 | nvidia,pins = "sdmmc1_wp_n_pv3"; | ||
| 880 | nvidia,function = "sdmmc1"; | ||
| 881 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 882 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 883 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 884 | }; | ||
| 885 | ddc_scl_pv4 { | ||
| 886 | nvidia,pins = "ddc_scl_pv4"; | ||
| 887 | nvidia,function = "i2c4"; | ||
| 888 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 889 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 890 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 891 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | ||
| 892 | }; | ||
| 893 | ddc_sda_pv5 { | ||
| 894 | nvidia,pins = "ddc_sda_pv5"; | ||
| 895 | nvidia,function = "i2c4"; | ||
| 896 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 897 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 898 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 899 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | ||
| 900 | }; | ||
| 901 | gpio_w2_aud_pw2 { | ||
| 902 | nvidia,pins = "gpio_w2_aud_pw2"; | ||
| 903 | nvidia,function = "rsvd2"; | ||
| 904 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 905 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 906 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 907 | }; | ||
| 908 | gpio_w3_aud_pw3 { | ||
| 909 | nvidia,pins = "gpio_w3_aud_pw3"; | ||
| 910 | nvidia,function = "spi6"; | ||
| 911 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 912 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 913 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 914 | }; | ||
| 915 | dap_mclk1_pw4 { | ||
| 916 | nvidia,pins = "dap_mclk1_pw4"; | ||
| 917 | nvidia,function = "extperiph1"; | ||
| 918 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 919 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 920 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 921 | }; | ||
| 922 | clk2_out_pw5 { | ||
| 923 | nvidia,pins = "clk2_out_pw5"; | ||
| 924 | nvidia,function = "extperiph2"; | ||
| 925 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 926 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 927 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 928 | }; | ||
| 929 | uart3_txd_pw6 { | ||
| 930 | nvidia,pins = "uart3_txd_pw6"; | ||
| 931 | nvidia,function = "uartc"; | ||
| 932 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 933 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 934 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 935 | }; | ||
| 936 | uart3_rxd_pw7 { | ||
| 937 | nvidia,pins = "uart3_rxd_pw7"; | ||
| 938 | nvidia,function = "uartc"; | ||
| 939 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 940 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 941 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 942 | }; | ||
| 943 | dvfs_pwm_px0 { | ||
| 944 | nvidia,pins = "dvfs_pwm_px0"; | ||
| 945 | nvidia,function = "cldvfs"; | ||
| 946 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 947 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 948 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 949 | }; | ||
| 950 | gpio_x1_aud_px1 { | ||
| 951 | nvidia,pins = "gpio_x1_aud_px1"; | ||
| 952 | nvidia,function = "rsvd2"; | ||
| 953 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 954 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 955 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 956 | }; | ||
| 957 | dvfs_clk_px2 { | ||
| 958 | nvidia,pins = "dvfs_clk_px2"; | ||
| 959 | nvidia,function = "cldvfs"; | ||
| 960 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 961 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 962 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 963 | }; | ||
| 964 | gpio_x3_aud_px3 { | ||
| 965 | nvidia,pins = "gpio_x3_aud_px3"; | ||
| 966 | nvidia,function = "rsvd4"; | ||
| 967 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 968 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 969 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 970 | }; | ||
| 971 | gpio_x4_aud_px4 { | ||
| 972 | nvidia,pins = "gpio_x4_aud_px4"; | ||
| 973 | nvidia,function = "gmi"; | ||
| 974 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 975 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 976 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 977 | }; | ||
| 978 | gpio_x5_aud_px5 { | ||
| 979 | nvidia,pins = "gpio_x5_aud_px5"; | ||
| 980 | nvidia,function = "rsvd4"; | ||
| 981 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 982 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 983 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 984 | }; | ||
| 985 | gpio_x6_aud_px6 { | ||
| 986 | nvidia,pins = "gpio_x6_aud_px6"; | ||
| 987 | nvidia,function = "gmi"; | ||
| 988 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 989 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 990 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 991 | }; | ||
| 992 | gpio_x7_aud_px7 { | ||
| 993 | nvidia,pins = "gpio_x7_aud_px7"; | ||
| 994 | nvidia,function = "rsvd1"; | ||
| 995 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 996 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 997 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 998 | }; | ||
| 999 | ulpi_clk_py0 { | ||
| 1000 | nvidia,pins = "ulpi_clk_py0"; | ||
| 1001 | nvidia,function = "spi1"; | ||
| 1002 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1003 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1004 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1005 | }; | ||
| 1006 | ulpi_dir_py1 { | ||
| 1007 | nvidia,pins = "ulpi_dir_py1"; | ||
| 1008 | nvidia,function = "spi1"; | ||
| 1009 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 1010 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1011 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1012 | }; | ||
| 1013 | ulpi_nxt_py2 { | ||
| 1014 | nvidia,pins = "ulpi_nxt_py2"; | ||
| 1015 | nvidia,function = "spi1"; | ||
| 1016 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1017 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1018 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1019 | }; | ||
| 1020 | ulpi_stp_py3 { | ||
| 1021 | nvidia,pins = "ulpi_stp_py3"; | ||
| 1022 | nvidia,function = "spi1"; | ||
| 1023 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1024 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1025 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1026 | }; | ||
| 1027 | sdmmc1_dat3_py4 { | ||
| 1028 | nvidia,pins = "sdmmc1_dat3_py4"; | ||
| 1029 | nvidia,function = "sdmmc1"; | ||
| 1030 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1031 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1032 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1033 | }; | ||
| 1034 | sdmmc1_dat2_py5 { | ||
| 1035 | nvidia,pins = "sdmmc1_dat2_py5"; | ||
| 1036 | nvidia,function = "sdmmc1"; | ||
| 1037 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1038 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1039 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1040 | }; | ||
| 1041 | sdmmc1_dat1_py6 { | ||
| 1042 | nvidia,pins = "sdmmc1_dat1_py6"; | ||
| 1043 | nvidia,function = "sdmmc1"; | ||
| 1044 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1045 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1046 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1047 | }; | ||
| 1048 | sdmmc1_dat0_py7 { | ||
| 1049 | nvidia,pins = "sdmmc1_dat0_py7"; | ||
| 1050 | nvidia,function = "sdmmc1"; | ||
| 1051 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1052 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1053 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1054 | }; | ||
| 1055 | sdmmc1_clk_pz0 { | ||
| 1056 | nvidia,pins = "sdmmc1_clk_pz0"; | ||
| 1057 | nvidia,function = "sdmmc1"; | ||
| 1058 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1059 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1060 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1061 | }; | ||
| 1062 | sdmmc1_cmd_pz1 { | ||
| 1063 | nvidia,pins = "sdmmc1_cmd_pz1"; | ||
| 1064 | nvidia,function = "sdmmc1"; | ||
| 1065 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1066 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1067 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1068 | }; | ||
| 1069 | pwr_i2c_scl_pz6 { | ||
| 1070 | nvidia,pins = "pwr_i2c_scl_pz6"; | ||
| 1071 | nvidia,function = "i2cpwr"; | ||
| 1072 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1073 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1074 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1075 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
| 1076 | }; | ||
| 1077 | pwr_i2c_sda_pz7 { | ||
| 1078 | nvidia,pins = "pwr_i2c_sda_pz7"; | ||
| 1079 | nvidia,function = "i2cpwr"; | ||
| 1080 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1081 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1082 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1083 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
| 1084 | }; | ||
| 1085 | sdmmc4_dat0_paa0 { | ||
| 1086 | nvidia,pins = "sdmmc4_dat0_paa0"; | ||
| 1087 | nvidia,function = "sdmmc4"; | ||
| 1088 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1089 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1090 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1091 | }; | ||
| 1092 | sdmmc4_dat1_paa1 { | ||
| 1093 | nvidia,pins = "sdmmc4_dat1_paa1"; | ||
| 1094 | nvidia,function = "sdmmc4"; | ||
| 1095 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1096 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1097 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1098 | }; | ||
| 1099 | sdmmc4_dat2_paa2 { | ||
| 1100 | nvidia,pins = "sdmmc4_dat2_paa2"; | ||
| 1101 | nvidia,function = "sdmmc4"; | ||
| 1102 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1103 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1104 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1105 | }; | ||
| 1106 | sdmmc4_dat3_paa3 { | ||
| 1107 | nvidia,pins = "sdmmc4_dat3_paa3"; | ||
| 1108 | nvidia,function = "sdmmc4"; | ||
| 1109 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1110 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1111 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1112 | }; | ||
| 1113 | sdmmc4_dat4_paa4 { | ||
| 1114 | nvidia,pins = "sdmmc4_dat4_paa4"; | ||
| 1115 | nvidia,function = "sdmmc4"; | ||
| 1116 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1117 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1118 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1119 | }; | ||
| 1120 | sdmmc4_dat5_paa5 { | ||
| 1121 | nvidia,pins = "sdmmc4_dat5_paa5"; | ||
| 1122 | nvidia,function = "sdmmc4"; | ||
| 1123 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1124 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1125 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1126 | }; | ||
| 1127 | sdmmc4_dat6_paa6 { | ||
| 1128 | nvidia,pins = "sdmmc4_dat6_paa6"; | ||
| 1129 | nvidia,function = "sdmmc4"; | ||
| 1130 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1131 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1132 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1133 | }; | ||
| 1134 | sdmmc4_dat7_paa7 { | ||
| 1135 | nvidia,pins = "sdmmc4_dat7_paa7"; | ||
| 1136 | nvidia,function = "sdmmc4"; | ||
| 1137 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1138 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1139 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1140 | }; | ||
| 1141 | pbb0 { | ||
| 1142 | nvidia,pins = "pbb0"; | ||
| 1143 | nvidia,function = "vimclk2_alt"; | ||
| 1144 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1145 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1146 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1147 | }; | ||
| 1148 | cam_i2c_scl_pbb1 { | ||
| 1149 | nvidia,pins = "cam_i2c_scl_pbb1"; | ||
| 1150 | nvidia,function = "i2c3"; | ||
| 1151 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1152 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1153 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1154 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
| 1155 | }; | ||
| 1156 | cam_i2c_sda_pbb2 { | ||
| 1157 | nvidia,pins = "cam_i2c_sda_pbb2"; | ||
| 1158 | nvidia,function = "i2c3"; | ||
| 1159 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1160 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1161 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1162 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
| 1163 | }; | ||
| 1164 | pbb3 { | ||
| 1165 | nvidia,pins = "pbb3"; | ||
| 1166 | nvidia,function = "vgp3"; | ||
| 1167 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1168 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1169 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1170 | }; | ||
| 1171 | pbb4 { | ||
| 1172 | nvidia,pins = "pbb4"; | ||
| 1173 | nvidia,function = "vgp4"; | ||
| 1174 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1175 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1176 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1177 | }; | ||
| 1178 | pbb5 { | ||
| 1179 | nvidia,pins = "pbb5"; | ||
| 1180 | nvidia,function = "rsvd3"; | ||
| 1181 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1182 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1183 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1184 | }; | ||
| 1185 | pbb6 { | ||
| 1186 | nvidia,pins = "pbb6"; | ||
| 1187 | nvidia,function = "rsvd2"; | ||
| 1188 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1189 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1190 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1191 | }; | ||
| 1192 | pbb7 { | ||
| 1193 | nvidia,pins = "pbb7"; | ||
| 1194 | nvidia,function = "rsvd2"; | ||
| 1195 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1196 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1197 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1198 | }; | ||
| 1199 | cam_mclk_pcc0 { | ||
| 1200 | nvidia,pins = "cam_mclk_pcc0"; | ||
| 1201 | nvidia,function = "vi_alt3"; | ||
| 1202 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1203 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1204 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1205 | }; | ||
| 1206 | pcc1 { | ||
| 1207 | nvidia,pins = "pcc1"; | ||
| 1208 | nvidia,function = "rsvd2"; | ||
| 1209 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 1210 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1211 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1212 | }; | ||
| 1213 | pcc2 { | ||
| 1214 | nvidia,pins = "pcc2"; | ||
| 1215 | nvidia,function = "rsvd2"; | ||
| 1216 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 1217 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1218 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1219 | }; | ||
| 1220 | sdmmc4_clk_pcc4 { | ||
| 1221 | nvidia,pins = "sdmmc4_clk_pcc4"; | ||
| 1222 | nvidia,function = "sdmmc4"; | ||
| 1223 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1224 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1225 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1226 | }; | ||
| 1227 | clk2_req_pcc5 { | ||
| 1228 | nvidia,pins = "clk2_req_pcc5"; | ||
| 1229 | nvidia,function = "rsvd2"; | ||
| 1230 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1231 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1232 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1233 | }; | ||
| 1234 | clk3_out_pee0 { | ||
| 1235 | nvidia,pins = "clk3_out_pee0"; | ||
| 1236 | nvidia,function = "extperiph3"; | ||
| 1237 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1238 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1239 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1240 | }; | ||
| 1241 | clk3_req_pee1 { | ||
| 1242 | nvidia,pins = "clk3_req_pee1"; | ||
| 1243 | nvidia,function = "rsvd2"; | ||
| 1244 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1245 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1246 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1247 | }; | ||
| 1248 | dap_mclk1_req_pee2 { | ||
| 1249 | nvidia,pins = "dap_mclk1_req_pee2"; | ||
| 1250 | nvidia,function = "sata"; | ||
| 1251 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1252 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1253 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1254 | }; | ||
| 1255 | hdmi_cec_pee3 { | ||
| 1256 | nvidia,pins = "hdmi_cec_pee3"; | ||
| 1257 | nvidia,function = "cec"; | ||
| 1258 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1259 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1260 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1261 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
| 1262 | }; | ||
| 1263 | sdmmc3_clk_lb_out_pee4 { | ||
| 1264 | nvidia,pins = "sdmmc3_clk_lb_out_pee4"; | ||
| 1265 | nvidia,function = "sdmmc3"; | ||
| 1266 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1267 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1268 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1269 | }; | ||
| 1270 | sdmmc3_clk_lb_in_pee5 { | ||
| 1271 | nvidia,pins = "sdmmc3_clk_lb_in_pee5"; | ||
| 1272 | nvidia,function = "sdmmc3"; | ||
| 1273 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1274 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1275 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1276 | }; | ||
| 1277 | dp_hpd_pff0 { | ||
| 1278 | nvidia,pins = "dp_hpd_pff0"; | ||
| 1279 | nvidia,function = "dp"; | ||
| 1280 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1281 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1282 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1283 | }; | ||
| 1284 | usb_vbus_en2_pff1 { | ||
| 1285 | nvidia,pins = "usb_vbus_en2_pff1"; | ||
| 1286 | nvidia,function = "rsvd2"; | ||
| 1287 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1288 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1289 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1290 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | ||
| 1291 | }; | ||
| 1292 | pff2 { | ||
| 1293 | nvidia,pins = "pff2"; | ||
| 1294 | nvidia,function = "rsvd2"; | ||
| 1295 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1296 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1297 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1298 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | ||
| 1299 | }; | ||
| 1300 | core_pwr_req { | ||
| 1301 | nvidia,pins = "core_pwr_req"; | ||
| 1302 | nvidia,function = "pwron"; | ||
| 1303 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1304 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1305 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1306 | }; | ||
| 1307 | cpu_pwr_req { | ||
| 1308 | nvidia,pins = "cpu_pwr_req"; | ||
| 1309 | nvidia,function = "rsvd2"; | ||
| 1310 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1311 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1312 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1313 | }; | ||
| 1314 | pwr_int_n { | ||
| 1315 | nvidia,pins = "pwr_int_n"; | ||
| 1316 | nvidia,function = "pmi"; | ||
| 1317 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1318 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1319 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1320 | }; | ||
| 1321 | reset_out_n { | ||
| 1322 | nvidia,pins = "reset_out_n"; | ||
| 1323 | nvidia,function = "reset_out_n"; | ||
| 1324 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1325 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1326 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1327 | }; | ||
| 1328 | owr { | ||
| 1329 | nvidia,pins = "owr"; | ||
| 1330 | nvidia,function = "rsvd2"; | ||
| 1331 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
| 1332 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 1333 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1334 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | ||
| 1335 | }; | ||
| 1336 | clk_32k_in { | ||
| 1337 | nvidia,pins = "clk_32k_in"; | ||
| 1338 | nvidia,function = "rsvd2"; | ||
| 1339 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 1340 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1341 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 1342 | }; | ||
| 1343 | jtag_rtck { | ||
| 1344 | nvidia,pins = "jtag_rtck"; | ||
| 1345 | nvidia,function = "rtck"; | ||
| 1346 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 1347 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 1348 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
| 1349 | }; | ||
| 1350 | }; | ||
| 1351 | }; | ||
| 1352 | |||
| 1353 | /* DB9 serial port */ | ||
| 1354 | serial@0,70006300 { | ||
| 1355 | status = "okay"; | ||
| 1356 | }; | ||
| 1357 | |||
| 1358 | /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ | ||
| 1359 | i2c@0,7000c000 { | ||
| 1360 | status = "okay"; | ||
| 1361 | clock-frequency = <100000>; | ||
| 1362 | |||
| 1363 | rt5639: audio-codec@1c { | ||
| 1364 | compatible = "realtek,rt5639"; | ||
| 1365 | reg = <0x1c>; | ||
| 1366 | interrupt-parent = <&gpio>; | ||
| 1367 | interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; | ||
| 1368 | realtek,ldo1-en-gpios = | ||
| 1369 | <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; | ||
| 1370 | }; | ||
| 1371 | |||
| 1372 | temperature-sensor@4c { | ||
| 1373 | compatible = "ti,tmp451"; | ||
| 1374 | reg = <0x4c>; | ||
| 1375 | interrupt-parent = <&gpio>; | ||
| 1376 | interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; | ||
| 1377 | }; | ||
| 1378 | |||
| 1379 | eeprom@56 { | ||
| 1380 | compatible = "atmel,24c02"; | ||
| 1381 | reg = <0x56>; | ||
| 1382 | pagesize = <8>; | ||
| 1383 | }; | ||
| 1384 | }; | ||
| 1385 | |||
| 1386 | /* Expansion GEN2_I2C_* */ | ||
| 1387 | i2c@0,7000c400 { | ||
| 1388 | status = "okay"; | ||
| 1389 | clock-frequency = <100000>; | ||
| 1390 | }; | ||
| 1391 | |||
| 1392 | /* Expansion CAM_I2C_* */ | ||
| 1393 | i2c@0,7000c500 { | ||
| 1394 | status = "okay"; | ||
| 1395 | clock-frequency = <100000>; | ||
| 1396 | }; | ||
| 1397 | |||
| 1398 | /* HDMI DDC */ | ||
| 1399 | hdmi_ddc: i2c@0,7000c700 { | ||
| 1400 | status = "okay"; | ||
| 1401 | clock-frequency = <100000>; | ||
| 1402 | }; | ||
| 1403 | |||
| 1404 | /* Expansion PWR_I2C_*, on-board components */ | ||
| 1405 | i2c@0,7000d000 { | ||
| 1406 | status = "okay"; | ||
| 1407 | clock-frequency = <400000>; | ||
| 1408 | |||
| 1409 | pmic: pmic@40 { | ||
| 1410 | compatible = "ams,as3722"; | ||
| 1411 | reg = <0x40>; | ||
| 1412 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; | ||
| 1413 | |||
| 1414 | ams,system-power-controller; | ||
| 1415 | |||
| 1416 | #interrupt-cells = <2>; | ||
| 1417 | interrupt-controller; | ||
| 1418 | |||
| 1419 | gpio-controller; | ||
| 1420 | #gpio-cells = <2>; | ||
| 1421 | |||
| 1422 | pinctrl-names = "default"; | ||
| 1423 | pinctrl-0 = <&as3722_default>; | ||
| 1424 | |||
| 1425 | as3722_default: pinmux { | ||
| 1426 | gpio0 { | ||
| 1427 | pins = "gpio0"; | ||
| 1428 | function = "gpio"; | ||
| 1429 | bias-pull-down; | ||
| 1430 | }; | ||
| 1431 | |||
| 1432 | gpio1_2_4_7 { | ||
| 1433 | pins = "gpio1", "gpio2", "gpio4", "gpio7"; | ||
| 1434 | function = "gpio"; | ||
| 1435 | bias-pull-up; | ||
| 1436 | }; | ||
| 1437 | |||
| 1438 | gpio3_5_6 { | ||
| 1439 | pins = "gpio3", "gpio5", "gpio6"; | ||
| 1440 | bias-high-impedance; | ||
| 1441 | }; | ||
| 1442 | }; | ||
| 1443 | |||
| 1444 | regulators { | ||
| 1445 | vsup-sd2-supply = <&vdd_5v0_sys>; | ||
| 1446 | vsup-sd3-supply = <&vdd_5v0_sys>; | ||
| 1447 | vsup-sd4-supply = <&vdd_5v0_sys>; | ||
| 1448 | vsup-sd5-supply = <&vdd_5v0_sys>; | ||
| 1449 | vin-ldo0-supply = <&vdd_1v35_lp0>; | ||
| 1450 | vin-ldo1-6-supply = <&vdd_3v3_run>; | ||
| 1451 | vin-ldo2-5-7-supply = <&vddio_1v8>; | ||
| 1452 | vin-ldo3-4-supply = <&vdd_3v3_sys>; | ||
| 1453 | vin-ldo9-10-supply = <&vdd_5v0_sys>; | ||
| 1454 | vin-ldo11-supply = <&vdd_3v3_run>; | ||
| 1455 | |||
| 1456 | sd0 { | ||
| 1457 | regulator-name = "+VDD_CPU_AP"; | ||
| 1458 | regulator-min-microvolt = <700000>; | ||
| 1459 | regulator-max-microvolt = <1400000>; | ||
| 1460 | regulator-min-microamp = <3500000>; | ||
| 1461 | regulator-max-microamp = <3500000>; | ||
| 1462 | regulator-always-on; | ||
| 1463 | regulator-boot-on; | ||
| 1464 | ams,external-control = <2>; | ||
| 1465 | }; | ||
| 1466 | |||
| 1467 | sd1 { | ||
| 1468 | regulator-name = "+VDD_CORE"; | ||
| 1469 | regulator-min-microvolt = <700000>; | ||
| 1470 | regulator-max-microvolt = <1350000>; | ||
| 1471 | regulator-min-microamp = <2500000>; | ||
| 1472 | regulator-max-microamp = <2500000>; | ||
| 1473 | regulator-always-on; | ||
| 1474 | regulator-boot-on; | ||
| 1475 | ams,external-control = <1>; | ||
| 1476 | }; | ||
| 1477 | |||
| 1478 | vdd_1v35_lp0: sd2 { | ||
| 1479 | regulator-name = "+1.35V_LP0(sd2)"; | ||
| 1480 | regulator-min-microvolt = <1350000>; | ||
| 1481 | regulator-max-microvolt = <1350000>; | ||
| 1482 | regulator-always-on; | ||
| 1483 | regulator-boot-on; | ||
| 1484 | }; | ||
| 1485 | |||
| 1486 | sd3 { | ||
| 1487 | regulator-name = "+1.35V_LP0(sd3)"; | ||
| 1488 | regulator-min-microvolt = <1350000>; | ||
| 1489 | regulator-max-microvolt = <1350000>; | ||
| 1490 | regulator-always-on; | ||
| 1491 | regulator-boot-on; | ||
| 1492 | }; | ||
| 1493 | |||
| 1494 | vdd_1v05_run: sd4 { | ||
| 1495 | regulator-name = "+1.05V_RUN"; | ||
| 1496 | regulator-min-microvolt = <1050000>; | ||
| 1497 | regulator-max-microvolt = <1050000>; | ||
| 1498 | }; | ||
| 1499 | |||
| 1500 | vddio_1v8: sd5 { | ||
| 1501 | regulator-name = "+1.8V_VDDIO"; | ||
| 1502 | regulator-min-microvolt = <1800000>; | ||
| 1503 | regulator-max-microvolt = <1800000>; | ||
| 1504 | regulator-boot-on; | ||
| 1505 | regulator-always-on; | ||
| 1506 | }; | ||
| 1507 | |||
| 1508 | sd6 { | ||
| 1509 | regulator-name = "+VDD_GPU_AP"; | ||
| 1510 | regulator-min-microvolt = <650000>; | ||
| 1511 | regulator-max-microvolt = <1200000>; | ||
| 1512 | regulator-min-microamp = <3500000>; | ||
| 1513 | regulator-max-microamp = <3500000>; | ||
| 1514 | regulator-boot-on; | ||
| 1515 | regulator-always-on; | ||
| 1516 | }; | ||
| 1517 | |||
| 1518 | ldo0 { | ||
| 1519 | regulator-name = "+1.05V_RUN_AVDD"; | ||
| 1520 | regulator-min-microvolt = <1050000>; | ||
| 1521 | regulator-max-microvolt = <1050000>; | ||
| 1522 | regulator-boot-on; | ||
| 1523 | regulator-always-on; | ||
| 1524 | ams,external-control = <1>; | ||
| 1525 | }; | ||
| 1526 | |||
| 1527 | ldo1 { | ||
| 1528 | regulator-name = "+1.8V_RUN_CAM"; | ||
| 1529 | regulator-min-microvolt = <1800000>; | ||
| 1530 | regulator-max-microvolt = <1800000>; | ||
| 1531 | }; | ||
| 1532 | |||
| 1533 | ldo2 { | ||
| 1534 | regulator-name = "+1.2V_GEN_AVDD"; | ||
| 1535 | regulator-min-microvolt = <1200000>; | ||
| 1536 | regulator-max-microvolt = <1200000>; | ||
| 1537 | regulator-boot-on; | ||
| 1538 | regulator-always-on; | ||
| 1539 | }; | ||
| 1540 | |||
| 1541 | ldo3 { | ||
| 1542 | regulator-name = "+1.05V_LP0_VDD_RTC"; | ||
| 1543 | regulator-min-microvolt = <1000000>; | ||
| 1544 | regulator-max-microvolt = <1000000>; | ||
| 1545 | regulator-boot-on; | ||
| 1546 | regulator-always-on; | ||
| 1547 | ams,enable-tracking; | ||
| 1548 | }; | ||
| 1549 | |||
| 1550 | ldo4 { | ||
| 1551 | regulator-name = "+2.8V_RUN_CAM"; | ||
| 1552 | regulator-min-microvolt = <2800000>; | ||
| 1553 | regulator-max-microvolt = <2800000>; | ||
| 1554 | }; | ||
| 1555 | |||
| 1556 | ldo5 { | ||
| 1557 | regulator-name = "+1.2V_RUN_CAM_FRONT"; | ||
| 1558 | regulator-min-microvolt = <1200000>; | ||
| 1559 | regulator-max-microvolt = <1200000>; | ||
| 1560 | }; | ||
| 1561 | |||
| 1562 | vddio_sdmmc3: ldo6 { | ||
| 1563 | regulator-name = "+VDDIO_SDMMC3"; | ||
| 1564 | regulator-min-microvolt = <1800000>; | ||
| 1565 | regulator-max-microvolt = <3300000>; | ||
| 1566 | }; | ||
| 1567 | |||
| 1568 | ldo7 { | ||
| 1569 | regulator-name = "+1.05V_RUN_CAM_REAR"; | ||
| 1570 | regulator-min-microvolt = <1050000>; | ||
| 1571 | regulator-max-microvolt = <1050000>; | ||
| 1572 | }; | ||
| 1573 | |||
| 1574 | ldo9 { | ||
| 1575 | regulator-name = "+3.3V_RUN_TOUCH"; | ||
| 1576 | regulator-min-microvolt = <2800000>; | ||
| 1577 | regulator-max-microvolt = <2800000>; | ||
| 1578 | }; | ||
| 1579 | |||
| 1580 | ldo10 { | ||
| 1581 | regulator-name = "+2.8V_RUN_CAM_AF"; | ||
| 1582 | regulator-min-microvolt = <2800000>; | ||
| 1583 | regulator-max-microvolt = <2800000>; | ||
| 1584 | }; | ||
| 1585 | |||
| 1586 | ldo11 { | ||
| 1587 | regulator-name = "+1.8V_RUN_VPP_FUSE"; | ||
| 1588 | regulator-min-microvolt = <1800000>; | ||
| 1589 | regulator-max-microvolt = <1800000>; | ||
| 1590 | }; | ||
| 1591 | }; | ||
| 1592 | }; | ||
| 1593 | }; | ||
| 1594 | |||
| 1595 | /* Expansion TS_SPI_* */ | ||
| 1596 | spi@0,7000d400 { | ||
| 1597 | status = "okay"; | ||
| 1598 | }; | ||
| 1599 | |||
| 1600 | /* Internal SPI */ | ||
| 1601 | spi@0,7000da00 { | ||
| 1602 | status = "okay"; | ||
| 1603 | spi-max-frequency = <25000000>; | ||
| 1604 | spi-flash@0 { | ||
| 1605 | compatible = "winbond,w25q32dw"; | ||
| 1606 | reg = <0>; | ||
| 1607 | spi-max-frequency = <20000000>; | ||
| 1608 | }; | ||
| 1609 | }; | ||
| 1610 | |||
| 1611 | pmc@0,7000e400 { | ||
| 1612 | nvidia,invert-interrupt; | ||
| 1613 | nvidia,suspend-mode = <1>; | ||
| 1614 | nvidia,cpu-pwr-good-time = <500>; | ||
| 1615 | nvidia,cpu-pwr-off-time = <300>; | ||
| 1616 | nvidia,core-pwr-good-time = <641 3845>; | ||
| 1617 | nvidia,core-pwr-off-time = <61036>; | ||
| 1618 | nvidia,core-power-req-active-high; | ||
| 1619 | nvidia,sys-clock-req-active-high; | ||
| 1620 | }; | ||
| 1621 | |||
| 1622 | /* SD card */ | ||
| 1623 | sdhci@0,700b0400 { | ||
| 1624 | status = "okay"; | ||
| 1625 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; | ||
| 1626 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; | ||
| 1627 | wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; | ||
| 1628 | bus-width = <4>; | ||
| 1629 | vqmmc-supply = <&vddio_sdmmc3>; | ||
| 1630 | }; | ||
| 1631 | |||
| 1632 | /* eMMC */ | ||
| 1633 | sdhci@0,700b0600 { | ||
| 1634 | status = "okay"; | ||
| 1635 | bus-width = <8>; | ||
| 1636 | }; | ||
| 1637 | |||
| 1638 | ahub@0,70300000 { | ||
| 1639 | i2s@0,70301100 { | ||
| 1640 | status = "okay"; | ||
| 1641 | }; | ||
| 1642 | }; | ||
| 1643 | |||
| 1644 | /* mini-PCIe USB */ | ||
| 1645 | usb@0,7d004000 { | ||
| 1646 | status = "okay"; | ||
| 1647 | }; | ||
| 1648 | |||
| 1649 | usb-phy@0,7d004000 { | ||
| 1650 | status = "okay"; | ||
| 1651 | }; | ||
| 1652 | |||
| 1653 | /* USB A connector */ | ||
| 1654 | usb@0,7d008000 { | ||
| 1655 | status = "okay"; | ||
| 1656 | }; | ||
| 1657 | |||
| 1658 | usb-phy@0,7d008000 { | ||
| 1659 | status = "okay"; | ||
| 1660 | vbus-supply = <&vdd_usb3_vbus>; | ||
| 1661 | }; | ||
| 1662 | |||
| 1663 | clocks { | ||
| 1664 | compatible = "simple-bus"; | ||
| 1665 | #address-cells = <1>; | ||
| 1666 | #size-cells = <0>; | ||
| 1667 | |||
| 1668 | clk32k_in: clock@0 { | ||
| 1669 | compatible = "fixed-clock"; | ||
| 1670 | reg = <0>; | ||
| 1671 | #clock-cells = <0>; | ||
| 1672 | clock-frequency = <32768>; | ||
| 1673 | }; | ||
| 1674 | }; | ||
| 1675 | |||
| 1676 | gpio-keys { | ||
| 1677 | compatible = "gpio-keys"; | ||
| 1678 | |||
| 1679 | power { | ||
| 1680 | label = "Power"; | ||
| 1681 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; | ||
| 1682 | linux,code = <KEY_POWER>; | ||
| 1683 | debounce-interval = <10>; | ||
| 1684 | gpio-key,wakeup; | ||
| 1685 | }; | ||
| 1686 | }; | ||
| 1687 | |||
| 1688 | regulators { | ||
| 1689 | compatible = "simple-bus"; | ||
| 1690 | #address-cells = <1>; | ||
| 1691 | #size-cells = <0>; | ||
| 1692 | |||
| 1693 | vdd_mux: regulator@0 { | ||
| 1694 | compatible = "regulator-fixed"; | ||
| 1695 | reg = <0>; | ||
| 1696 | regulator-name = "+VDD_MUX"; | ||
| 1697 | regulator-min-microvolt = <12000000>; | ||
| 1698 | regulator-max-microvolt = <12000000>; | ||
| 1699 | regulator-always-on; | ||
| 1700 | regulator-boot-on; | ||
| 1701 | }; | ||
| 1702 | |||
| 1703 | vdd_5v0_sys: regulator@1 { | ||
| 1704 | compatible = "regulator-fixed"; | ||
| 1705 | reg = <1>; | ||
| 1706 | regulator-name = "+5V_SYS"; | ||
| 1707 | regulator-min-microvolt = <5000000>; | ||
| 1708 | regulator-max-microvolt = <5000000>; | ||
| 1709 | regulator-always-on; | ||
| 1710 | regulator-boot-on; | ||
| 1711 | vin-supply = <&vdd_mux>; | ||
| 1712 | }; | ||
| 1713 | |||
| 1714 | vdd_3v3_sys: regulator@2 { | ||
| 1715 | compatible = "regulator-fixed"; | ||
| 1716 | reg = <2>; | ||
| 1717 | regulator-name = "+3.3V_SYS"; | ||
| 1718 | regulator-min-microvolt = <3300000>; | ||
| 1719 | regulator-max-microvolt = <3300000>; | ||
| 1720 | regulator-always-on; | ||
| 1721 | regulator-boot-on; | ||
| 1722 | vin-supply = <&vdd_mux>; | ||
| 1723 | }; | ||
| 1724 | |||
| 1725 | vdd_3v3_run: regulator@3 { | ||
| 1726 | compatible = "regulator-fixed"; | ||
| 1727 | reg = <3>; | ||
| 1728 | regulator-name = "+3.3V_RUN"; | ||
| 1729 | regulator-min-microvolt = <3300000>; | ||
| 1730 | regulator-max-microvolt = <3300000>; | ||
| 1731 | regulator-always-on; | ||
| 1732 | regulator-boot-on; | ||
| 1733 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; | ||
| 1734 | enable-active-high; | ||
| 1735 | vin-supply = <&vdd_3v3_sys>; | ||
| 1736 | }; | ||
| 1737 | |||
| 1738 | vdd_3v3_hdmi: regulator@4 { | ||
| 1739 | compatible = "regulator-fixed"; | ||
| 1740 | reg = <4>; | ||
| 1741 | regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; | ||
| 1742 | regulator-min-microvolt = <3300000>; | ||
| 1743 | regulator-max-microvolt = <3300000>; | ||
| 1744 | vin-supply = <&vdd_3v3_run>; | ||
| 1745 | }; | ||
| 1746 | |||
| 1747 | vdd_usb1_vbus: regulator@7 { | ||
| 1748 | compatible = "regulator-fixed"; | ||
| 1749 | reg = <7>; | ||
| 1750 | regulator-name = "+USB0_VBUS_SW"; | ||
| 1751 | regulator-min-microvolt = <5000000>; | ||
| 1752 | regulator-max-microvolt = <5000000>; | ||
| 1753 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; | ||
| 1754 | enable-active-high; | ||
| 1755 | gpio-open-drain; | ||
| 1756 | vin-supply = <&vdd_5v0_sys>; | ||
| 1757 | }; | ||
| 1758 | |||
| 1759 | vdd_usb3_vbus: regulator@8 { | ||
| 1760 | compatible = "regulator-fixed"; | ||
| 1761 | reg = <8>; | ||
| 1762 | regulator-name = "+5V_USB_HS"; | ||
| 1763 | regulator-min-microvolt = <5000000>; | ||
| 1764 | regulator-max-microvolt = <5000000>; | ||
| 1765 | gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; | ||
| 1766 | enable-active-high; | ||
| 1767 | gpio-open-drain; | ||
| 1768 | vin-supply = <&vdd_5v0_sys>; | ||
| 1769 | }; | ||
| 1770 | |||
| 1771 | vdd_3v3_lp0: regulator@10 { | ||
| 1772 | compatible = "regulator-fixed"; | ||
| 1773 | reg = <10>; | ||
| 1774 | regulator-name = "+3.3V_LP0"; | ||
| 1775 | regulator-min-microvolt = <3300000>; | ||
| 1776 | regulator-max-microvolt = <3300000>; | ||
| 1777 | regulator-always-on; | ||
| 1778 | regulator-boot-on; | ||
| 1779 | gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; | ||
| 1780 | enable-active-high; | ||
| 1781 | vin-supply = <&vdd_3v3_sys>; | ||
| 1782 | }; | ||
| 1783 | |||
| 1784 | vdd_hdmi_pll: regulator@11 { | ||
| 1785 | compatible = "regulator-fixed"; | ||
| 1786 | reg = <11>; | ||
| 1787 | regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; | ||
| 1788 | regulator-min-microvolt = <1050000>; | ||
| 1789 | regulator-max-microvolt = <1050000>; | ||
| 1790 | gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; | ||
| 1791 | vin-supply = <&vdd_1v05_run>; | ||
| 1792 | }; | ||
| 1793 | |||
| 1794 | vdd_5v0_hdmi: regulator@12 { | ||
| 1795 | compatible = "regulator-fixed"; | ||
| 1796 | reg = <12>; | ||
| 1797 | regulator-name = "+5V_HDMI_CON"; | ||
| 1798 | regulator-min-microvolt = <5000000>; | ||
| 1799 | regulator-max-microvolt = <5000000>; | ||
| 1800 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; | ||
| 1801 | enable-active-high; | ||
| 1802 | vin-supply = <&vdd_5v0_sys>; | ||
| 1803 | }; | ||
| 1804 | }; | ||
| 1805 | |||
| 1806 | sound { | ||
| 1807 | compatible = "nvidia,tegra-audio-rt5640-jetson-tk1", | ||
| 1808 | "nvidia,tegra-audio-rt5640"; | ||
| 1809 | nvidia,model = "NVIDIA Tegra Jetson TK1"; | ||
| 1810 | |||
| 1811 | nvidia,audio-routing = | ||
| 1812 | "Headphones", "HPOR", | ||
| 1813 | "Headphones", "HPOL", | ||
| 1814 | "Mic Jack", "MICBIAS1", | ||
| 1815 | "IN2P", "Mic Jack"; | ||
| 1816 | |||
| 1817 | nvidia,i2s-controller = <&tegra_i2s1>; | ||
| 1818 | nvidia,audio-codec = <&rt5639>; | ||
| 1819 | |||
| 1820 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; | ||
| 1821 | |||
| 1822 | clocks = <&tegra_car TEGRA124_CLK_PLL_A>, | ||
| 1823 | <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, | ||
| 1824 | <&tegra_car TEGRA124_CLK_EXTERN1>; | ||
| 1825 | clock-names = "pll_a", "pll_a_out0", "mclk"; | ||
| 1826 | }; | ||
| 1827 | }; | ||
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index c17283c04598..f0bb84244025 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts | |||
| @@ -17,6 +17,18 @@ | |||
| 17 | }; | 17 | }; |
| 18 | 18 | ||
| 19 | host1x@0,50000000 { | 19 | host1x@0,50000000 { |
| 20 | hdmi@0,54280000 { | ||
| 21 | status = "okay"; | ||
| 22 | |||
| 23 | vdd-supply = <&vdd_3v3_hdmi>; | ||
| 24 | pll-supply = <&vdd_hdmi_pll>; | ||
| 25 | hdmi-supply = <&vdd_5v0_hdmi>; | ||
| 26 | |||
| 27 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | ||
| 28 | nvidia,hpd-gpio = | ||
| 29 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | ||
| 30 | }; | ||
| 31 | |||
| 20 | sor@0,54540000 { | 32 | sor@0,54540000 { |
| 21 | status = "okay"; | 33 | status = "okay"; |
| 22 | 34 | ||
| @@ -601,7 +613,7 @@ | |||
| 601 | clock-frequency = <100000>; | 613 | clock-frequency = <100000>; |
| 602 | }; | 614 | }; |
| 603 | 615 | ||
| 604 | i2c@0,7000c700 { | 616 | hdmi_ddc: i2c@0,7000c700 { |
| 605 | status = "okay"; | 617 | status = "okay"; |
| 606 | clock-frequency = <100000>; | 618 | clock-frequency = <100000>; |
| 607 | }; | 619 | }; |
| @@ -700,7 +712,7 @@ | |||
| 700 | regulator-boot-on; | 712 | regulator-boot-on; |
| 701 | }; | 713 | }; |
| 702 | 714 | ||
| 703 | sd4 { | 715 | vdd_1v05_run: sd4 { |
| 704 | regulator-name = "+1.05V_RUN"; | 716 | regulator-name = "+1.05V_RUN"; |
| 705 | regulator-min-microvolt = <1050000>; | 717 | regulator-min-microvolt = <1050000>; |
| 706 | regulator-max-microvolt = <1050000>; | 718 | regulator-max-microvolt = <1050000>; |
| @@ -931,9 +943,10 @@ | |||
| 931 | sdhci@0,700b0400 { | 943 | sdhci@0,700b0400 { |
| 932 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; | 944 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; |
| 933 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; | 945 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; |
| 946 | wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; | ||
| 934 | status = "okay"; | 947 | status = "okay"; |
| 935 | bus-width = <4>; | 948 | bus-width = <4>; |
| 936 | vmmc-supply = <&vddio_sdmmc3>; | 949 | vqmmc-supply = <&vddio_sdmmc3>; |
| 937 | }; | 950 | }; |
| 938 | 951 | ||
| 939 | sdhci@0,700b0600 { | 952 | sdhci@0,700b0600 { |
| @@ -1060,6 +1073,8 @@ | |||
| 1060 | regulator-name = "+3.3V_RUN"; | 1073 | regulator-name = "+3.3V_RUN"; |
| 1061 | regulator-min-microvolt = <3300000>; | 1074 | regulator-min-microvolt = <3300000>; |
| 1062 | regulator-max-microvolt = <3300000>; | 1075 | regulator-max-microvolt = <3300000>; |
| 1076 | regulator-always-on; | ||
| 1077 | regulator-boot-on; | ||
| 1063 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; | 1078 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
| 1064 | enable-active-high; | 1079 | enable-active-high; |
| 1065 | vin-supply = <&vdd_3v3_sys>; | 1080 | vin-supply = <&vdd_3v3_sys>; |
| @@ -1145,6 +1160,27 @@ | |||
| 1145 | enable-active-high; | 1160 | enable-active-high; |
| 1146 | vin-supply = <&vdd_3v3_sys>; | 1161 | vin-supply = <&vdd_3v3_sys>; |
| 1147 | }; | 1162 | }; |
| 1163 | |||
| 1164 | vdd_hdmi_pll: regulator@11 { | ||
| 1165 | compatible = "regulator-fixed"; | ||
| 1166 | reg = <11>; | ||
| 1167 | regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; | ||
| 1168 | regulator-min-microvolt = <1050000>; | ||
| 1169 | regulator-max-microvolt = <1050000>; | ||
| 1170 | gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; | ||
| 1171 | vin-supply = <&vdd_1v05_run>; | ||
| 1172 | }; | ||
| 1173 | |||
| 1174 | vdd_5v0_hdmi: regulator@12 { | ||
| 1175 | compatible = "regulator-fixed"; | ||
| 1176 | reg = <12>; | ||
| 1177 | regulator-name = "+5V_HDMI_CON"; | ||
| 1178 | regulator-min-microvolt = <5000000>; | ||
| 1179 | regulator-max-microvolt = <5000000>; | ||
| 1180 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; | ||
| 1181 | enable-active-high; | ||
| 1182 | vin-supply = <&vdd_5v0_sys>; | ||
| 1183 | }; | ||
| 1148 | }; | 1184 | }; |
| 1149 | 1185 | ||
| 1150 | sound { | 1186 | sound { |
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 6d540a025148..6e6bc4e8185c 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi | |||
| @@ -51,6 +51,18 @@ | |||
| 51 | nvidia,head = <1>; | 51 | nvidia,head = <1>; |
| 52 | }; | 52 | }; |
| 53 | 53 | ||
| 54 | hdmi@0,54280000 { | ||
| 55 | compatible = "nvidia,tegra124-hdmi"; | ||
| 56 | reg = <0x0 0x54280000 0x0 0x00040000>; | ||
| 57 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | ||
| 58 | clocks = <&tegra_car TEGRA124_CLK_HDMI>, | ||
| 59 | <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; | ||
| 60 | clock-names = "hdmi", "parent"; | ||
| 61 | resets = <&tegra_car 51>; | ||
| 62 | reset-names = "hdmi"; | ||
| 63 | status = "disabled"; | ||
| 64 | }; | ||
| 65 | |||
| 54 | sor@0,54540000 { | 66 | sor@0,54540000 { |
| 55 | compatible = "nvidia,tegra124-sor"; | 67 | compatible = "nvidia,tegra124-sor"; |
| 56 | reg = <0x0 0x54540000 0x0 0x00040000>; | 68 | reg = <0x0 0x54540000 0x0 0x00040000>; |
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 3fb1f50f6d46..f45aad688d9b 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | hdmi@54280000 { | 28 | hdmi@54280000 { |
| 29 | status = "okay"; | 29 | status = "okay"; |
| 30 | 30 | ||
| 31 | hdmi-supply = <&vdd_5v0_hdmi>; | ||
| 31 | vdd-supply = <&hdmi_vdd_reg>; | 32 | vdd-supply = <&hdmi_vdd_reg>; |
| 32 | pll-supply = <&hdmi_pll_reg>; | 33 | pll-supply = <&hdmi_pll_reg>; |
| 33 | 34 | ||
| @@ -724,6 +725,17 @@ | |||
| 724 | gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; | 725 | gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; |
| 725 | enable-active-high; | 726 | enable-active-high; |
| 726 | }; | 727 | }; |
| 728 | |||
| 729 | vdd_5v0_hdmi: regulator@6 { | ||
| 730 | compatible = "regulator-fixed"; | ||
| 731 | reg = <6>; | ||
| 732 | regulator-name = "VDDIO_HDMI"; | ||
| 733 | regulator-min-microvolt = <5000000>; | ||
| 734 | regulator-max-microvolt = <5000000>; | ||
| 735 | gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; | ||
| 736 | enable-active-high; | ||
| 737 | vin-supply = <&vdd_5v0_reg>; | ||
| 738 | }; | ||
| 727 | }; | 739 | }; |
| 728 | 740 | ||
| 729 | sound { | 741 | sound { |
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index e93fe45b7803..3189791a9289 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts | |||
| @@ -40,6 +40,7 @@ | |||
| 40 | hdmi@54280000 { | 40 | hdmi@54280000 { |
| 41 | status = "okay"; | 41 | status = "okay"; |
| 42 | 42 | ||
| 43 | hdmi-supply = <&vdd_5v0_hdmi>; | ||
| 43 | vdd-supply = <&sys_3v3_reg>; | 44 | vdd-supply = <&sys_3v3_reg>; |
| 44 | pll-supply = <&vio_reg>; | 45 | pll-supply = <&vio_reg>; |
| 45 | 46 | ||
| @@ -478,6 +479,17 @@ | |||
| 478 | gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; | 479 | gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; |
| 479 | vin-supply = <&sys_3v3_reg>; | 480 | vin-supply = <&sys_3v3_reg>; |
| 480 | }; | 481 | }; |
| 482 | |||
| 483 | vdd_5v0_hdmi: regulator@8 { | ||
| 484 | compatible = "regulator-fixed"; | ||
| 485 | reg = <8>; | ||
| 486 | regulator-name = "+VDD_5V_HDMI"; | ||
| 487 | regulator-min-microvolt = <5000000>; | ||
| 488 | regulator-max-microvolt = <5000000>; | ||
| 489 | regulator-always-on; | ||
| 490 | regulator-boot-on; | ||
| 491 | vin-supply = <&sys_3v3_reg>; | ||
| 492 | }; | ||
| 481 | }; | 493 | }; |
| 482 | 494 | ||
| 483 | sound { | 495 | sound { |
diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts new file mode 100644 index 000000000000..7793abd5bef1 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | |||
| @@ -0,0 +1,205 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | #include "tegra30-colibri.dtsi" | ||
| 4 | |||
| 5 | / { | ||
| 6 | model = "Toradex Colibri T30 on Colibri Evaluation Board"; | ||
| 7 | compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30", "nvidia,tegra30"; | ||
| 8 | |||
| 9 | aliases { | ||
| 10 | rtc0 = "/i2c@7000c000/rtc@68"; | ||
| 11 | rtc1 = "/i2c@7000d000/tps65911@2d"; | ||
| 12 | rtc2 = "/rtc@7000e000"; | ||
| 13 | }; | ||
| 14 | |||
| 15 | host1x@50000000 { | ||
| 16 | dc@54200000 { | ||
| 17 | rgb { | ||
| 18 | status = "okay"; | ||
| 19 | nvidia,panel = <&panel>; | ||
| 20 | }; | ||
| 21 | }; | ||
| 22 | hdmi@54280000 { | ||
| 23 | status = "okay"; | ||
| 24 | }; | ||
| 25 | }; | ||
| 26 | |||
| 27 | serial@70006000 { | ||
| 28 | status = "okay"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | serial@70006040 { | ||
| 32 | compatible = "nvidia,tegra30-hsuart"; | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | serial@70006300 { | ||
| 37 | compatible = "nvidia,tegra30-hsuart"; | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | pwm@7000a000 { | ||
| 42 | status = "okay"; | ||
| 43 | }; | ||
| 44 | |||
| 45 | /* | ||
| 46 | * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier | ||
| 47 | * board) | ||
| 48 | */ | ||
| 49 | i2c@7000c000 { | ||
| 50 | status = "okay"; | ||
| 51 | clock-frequency = <100000>; | ||
| 52 | |||
| 53 | /* M41T0M6 real time clock on carrier board */ | ||
| 54 | rtc@68 { | ||
| 55 | compatible = "stm,m41t00"; | ||
| 56 | reg = <0x68>; | ||
| 57 | }; | ||
| 58 | }; | ||
| 59 | |||
| 60 | /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ | ||
| 61 | hdmiddc: i2c@7000c700 { | ||
| 62 | status = "okay"; | ||
| 63 | }; | ||
| 64 | |||
| 65 | /* SPI1: Colibri SSP */ | ||
| 66 | spi@7000d400 { | ||
| 67 | status = "okay"; | ||
| 68 | spi-max-frequency = <25000000>; | ||
| 69 | can0: can@0 { | ||
| 70 | compatible = "microchip,mcp2515"; | ||
| 71 | reg = <0>; | ||
| 72 | clocks = <&clk16m>; | ||
| 73 | interrupt-parent = <&gpio>; | ||
| 74 | interrupts = <TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; | ||
| 75 | spi-max-frequency = <10000000>; | ||
| 76 | }; | ||
| 77 | spidev0: spi@1 { | ||
| 78 | compatible = "spidev"; | ||
| 79 | reg = <1>; | ||
| 80 | spi-max-frequency = <25000000>; | ||
| 81 | }; | ||
| 82 | }; | ||
| 83 | |||
| 84 | sdhci@78000200 { | ||
| 85 | status = "okay"; | ||
| 86 | bus-width = <4>; | ||
| 87 | cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; | ||
| 88 | no-1-8-v; | ||
| 89 | }; | ||
| 90 | |||
| 91 | /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ | ||
| 92 | usb@7d000000 { | ||
| 93 | status = "okay"; | ||
| 94 | }; | ||
| 95 | |||
| 96 | usb-phy@7d000000 { | ||
| 97 | status = "okay"; | ||
| 98 | dr_mode = "otg"; | ||
| 99 | vbus-supply = <&usbc_vbus_reg>; | ||
| 100 | }; | ||
| 101 | |||
| 102 | /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ | ||
| 103 | usb@7d008000 { | ||
| 104 | status = "okay"; | ||
| 105 | }; | ||
| 106 | |||
| 107 | usb-phy@7d008000 { | ||
| 108 | status = "okay"; | ||
| 109 | vbus-supply = <&usbh_vbus_reg>; | ||
| 110 | }; | ||
| 111 | |||
| 112 | backlight: backlight { | ||
| 113 | compatible = "pwm-backlight"; | ||
| 114 | |||
| 115 | /* PWM<A> */ | ||
| 116 | pwms = <&pwm 0 5000000>; | ||
| 117 | brightness-levels = <255 128 64 32 16 8 4 0>; | ||
| 118 | default-brightness-level = <6>; | ||
| 119 | /* BL_ON */ | ||
| 120 | enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; | ||
| 121 | }; | ||
| 122 | |||
| 123 | clocks { | ||
| 124 | clk16m: clk@1 { | ||
| 125 | compatible = "fixed-clock"; | ||
| 126 | reg=<1>; | ||
| 127 | #clock-cells = <0>; | ||
| 128 | clock-frequency = <16000000>; | ||
| 129 | clock-output-names = "clk16m"; | ||
| 130 | }; | ||
| 131 | }; | ||
| 132 | |||
| 133 | gpio-keys { | ||
| 134 | compatible = "gpio-keys"; | ||
| 135 | |||
| 136 | power { | ||
| 137 | label = "Power"; | ||
| 138 | gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; | ||
| 139 | linux,code = <KEY_POWER>; | ||
| 140 | debounce-interval = <10>; | ||
| 141 | gpio-key,wakeup; | ||
| 142 | }; | ||
| 143 | }; | ||
| 144 | |||
| 145 | panel: panel { | ||
| 146 | /* | ||
| 147 | * edt,et057090dhu: EDT 5.7" LCD TFT | ||
| 148 | * edt,et070080dh6: EDT 7.0" LCD TFT | ||
| 149 | */ | ||
| 150 | compatible = "edt,et057090dhu", "simple-panel"; | ||
| 151 | |||
| 152 | backlight = <&backlight>; | ||
| 153 | }; | ||
| 154 | |||
| 155 | pwmleds { | ||
| 156 | compatible = "pwm-leds"; | ||
| 157 | |||
| 158 | pwmb { | ||
| 159 | label = "PWM<B>"; | ||
| 160 | pwms = <&pwm 1 19600>; | ||
| 161 | max-brightness = <255>; | ||
| 162 | }; | ||
| 163 | pwmc { | ||
| 164 | label = "PWM<C>"; | ||
| 165 | pwms = <&pwm 2 19600>; | ||
| 166 | max-brightness = <255>; | ||
| 167 | }; | ||
| 168 | pwmd { | ||
| 169 | label = "PWM<D>"; | ||
| 170 | pwms = <&pwm 3 19600>; | ||
| 171 | max-brightness = <255>; | ||
| 172 | }; | ||
| 173 | }; | ||
| 174 | |||
| 175 | regulators { | ||
| 176 | sys_5v0_reg: regulator@1 { | ||
| 177 | compatible = "regulator-fixed"; | ||
| 178 | reg = <1>; | ||
| 179 | regulator-name = "5v0"; | ||
| 180 | regulator-min-microvolt = <5000000>; | ||
| 181 | regulator-max-microvolt = <5000000>; | ||
| 182 | regulator-always-on; | ||
| 183 | }; | ||
| 184 | |||
| 185 | usbc_vbus_reg: regulator@2 { | ||
| 186 | compatible = "regulator-fixed"; | ||
| 187 | reg = <2>; | ||
| 188 | regulator-name = "usbc_vbus"; | ||
| 189 | regulator-min-microvolt = <5000000>; | ||
| 190 | regulator-max-microvolt = <5000000>; | ||
| 191 | vin-supply = <&sys_5v0_reg>; | ||
| 192 | }; | ||
| 193 | |||
| 194 | /* USBH_PEN */ | ||
| 195 | usbh_vbus_reg: regulator@3 { | ||
| 196 | compatible = "regulator-fixed"; | ||
| 197 | reg = <3>; | ||
| 198 | regulator-name = "usbh_vbus"; | ||
| 199 | regulator-min-microvolt = <5000000>; | ||
| 200 | regulator-max-microvolt = <5000000>; | ||
| 201 | gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; | ||
| 202 | vin-supply = <&sys_5v0_reg>; | ||
| 203 | }; | ||
| 204 | }; | ||
| 205 | }; | ||
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi new file mode 100644 index 000000000000..bf16f8e65627 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi | |||
| @@ -0,0 +1,377 @@ | |||
| 1 | #include <dt-bindings/input/input.h> | ||
| 2 | #include "tegra30.dtsi" | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Toradex Colibri T30 Device Tree | ||
| 6 | * Compatible for Revisions 1.1B/1.1C/1.1D | ||
| 7 | */ | ||
| 8 | / { | ||
| 9 | model = "Toradex Colibri T30"; | ||
| 10 | compatible = "toradex,colibri_t30", "nvidia,tegra30"; | ||
| 11 | |||
| 12 | memory { | ||
| 13 | reg = <0x80000000 0x40000000>; | ||
| 14 | }; | ||
| 15 | |||
| 16 | host1x@50000000 { | ||
| 17 | hdmi@54280000 { | ||
| 18 | vdd-supply = <&sys_3v3_reg>; | ||
| 19 | pll-supply = <&vio_reg>; | ||
| 20 | |||
| 21 | nvidia,hpd-gpio = | ||
| 22 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | ||
| 23 | nvidia,ddc-i2c-bus = <&hdmiddc>; | ||
| 24 | }; | ||
| 25 | }; | ||
| 26 | |||
| 27 | pinmux@70000868 { | ||
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&state_default>; | ||
| 30 | |||
| 31 | state_default: pinmux { | ||
| 32 | /* Colibri BL_ON */ | ||
| 33 | pv2 { | ||
| 34 | nvidia,pins = "pv2"; | ||
| 35 | nvidia,function = "rsvd4"; | ||
| 36 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 37 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 38 | }; | ||
| 39 | |||
| 40 | /* Colibri Backlight PWM<A> */ | ||
| 41 | sdmmc3_dat3_pb4 { | ||
| 42 | nvidia,pins = "sdmmc3_dat3_pb4"; | ||
| 43 | nvidia,function = "pwm0"; | ||
| 44 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 45 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 46 | }; | ||
| 47 | |||
| 48 | /* Colibri CAN_INT */ | ||
| 49 | kb_row8_ps0 { | ||
| 50 | nvidia,pins = "kb_row8_ps0"; | ||
| 51 | nvidia,function = "kbc"; | ||
| 52 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 53 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 54 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 55 | }; | ||
| 56 | |||
| 57 | /* | ||
| 58 | * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE | ||
| 59 | * todays display need DE, disable LCD_M1 | ||
| 60 | */ | ||
| 61 | lcd_m1_pw1 { | ||
| 62 | nvidia,pins = "lcd_m1_pw1"; | ||
| 63 | nvidia,function = "rsvd3"; | ||
| 64 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 65 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 66 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 67 | }; | ||
| 68 | |||
| 69 | /* Thermal alert, need to be disabled */ | ||
| 70 | lcd_dc1_pd2 { | ||
| 71 | nvidia,pins = "lcd_dc1_pd2"; | ||
| 72 | nvidia,function = "rsvd3"; | ||
| 73 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 74 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 75 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
| 76 | }; | ||
| 77 | |||
| 78 | /* Colibri MMC */ | ||
| 79 | kb_row10_ps2 { | ||
| 80 | nvidia,pins = "kb_row10_ps2"; | ||
| 81 | nvidia,function = "sdmmc2"; | ||
| 82 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 83 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 84 | }; | ||
| 85 | kb_row11_ps3 { | ||
| 86 | nvidia,pins = "kb_row11_ps3", | ||
| 87 | "kb_row12_ps4", | ||
| 88 | "kb_row13_ps5", | ||
| 89 | "kb_row14_ps6", | ||
| 90 | "kb_row15_ps7"; | ||
| 91 | nvidia,function = "sdmmc2"; | ||
| 92 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 93 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 94 | }; | ||
| 95 | |||
| 96 | /* Colibri SSP */ | ||
| 97 | ulpi_clk_py0 { | ||
| 98 | nvidia,pins = "ulpi_clk_py0", | ||
| 99 | "ulpi_dir_py1", | ||
| 100 | "ulpi_nxt_py2", | ||
| 101 | "ulpi_stp_py3"; | ||
| 102 | nvidia,function = "spi1"; | ||
| 103 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 104 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 105 | }; | ||
| 106 | sdmmc3_dat6_pd3 { | ||
| 107 | nvidia,pins = "sdmmc3_dat6_pd3", | ||
| 108 | "sdmmc3_dat7_pd4"; | ||
| 109 | nvidia,function = "spdif"; | ||
| 110 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 111 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
| 112 | }; | ||
| 113 | |||
| 114 | /* Colibri UART_A */ | ||
| 115 | ulpi_data0 { | ||
| 116 | nvidia,pins = "ulpi_data0_po1", | ||
| 117 | "ulpi_data1_po2", | ||
| 118 | "ulpi_data2_po3", | ||
| 119 | "ulpi_data3_po4", | ||
| 120 | "ulpi_data4_po5", | ||
| 121 | "ulpi_data5_po6", | ||
| 122 | "ulpi_data6_po7", | ||
| 123 | "ulpi_data7_po0"; | ||
| 124 | nvidia,function = "uarta"; | ||
| 125 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 126 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 127 | }; | ||
| 128 | |||
| 129 | /* Colibri UART_B */ | ||
| 130 | gmi_a16_pj7 { | ||
| 131 | nvidia,pins = "gmi_a16_pj7", | ||
| 132 | "gmi_a17_pb0", | ||
| 133 | "gmi_a18_pb1", | ||
| 134 | "gmi_a19_pk7"; | ||
| 135 | nvidia,function = "uartd"; | ||
| 136 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 137 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 138 | }; | ||
| 139 | |||
| 140 | /* Colibri UART_C */ | ||
| 141 | uart2_rxd { | ||
| 142 | nvidia,pins = "uart2_rxd_pc3", | ||
| 143 | "uart2_txd_pc2"; | ||
| 144 | nvidia,function = "uartb"; | ||
| 145 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 146 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 147 | }; | ||
| 148 | |||
| 149 | /* eMMC */ | ||
| 150 | sdmmc4_clk_pcc4 { | ||
| 151 | nvidia,pins = "sdmmc4_clk_pcc4", | ||
| 152 | "sdmmc4_rst_n_pcc3"; | ||
| 153 | nvidia,function = "sdmmc4"; | ||
| 154 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
| 155 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 156 | }; | ||
| 157 | sdmmc4_dat0_paa0 { | ||
| 158 | nvidia,pins = "sdmmc4_dat0_paa0", | ||
| 159 | "sdmmc4_dat1_paa1", | ||
| 160 | "sdmmc4_dat2_paa2", | ||
| 161 | "sdmmc4_dat3_paa3", | ||
| 162 | "sdmmc4_dat4_paa4", | ||
| 163 | "sdmmc4_dat5_paa5", | ||
| 164 | "sdmmc4_dat6_paa6", | ||
| 165 | "sdmmc4_dat7_paa7"; | ||
| 166 | nvidia,function = "sdmmc4"; | ||
| 167 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
| 168 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
| 169 | }; | ||
| 170 | }; | ||
| 171 | }; | ||
| 172 | |||
| 173 | hdmiddc: i2c@7000c700 { | ||
| 174 | clock-frequency = <100000>; | ||
| 175 | }; | ||
| 176 | |||
| 177 | /* | ||
| 178 | * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and | ||
| 179 | * touch screen controller | ||
| 180 | */ | ||
| 181 | i2c@7000d000 { | ||
| 182 | status = "okay"; | ||
| 183 | clock-frequency = <100000>; | ||
| 184 | |||
| 185 | pmic: tps65911@2d { | ||
| 186 | compatible = "ti,tps65911"; | ||
| 187 | reg = <0x2d>; | ||
| 188 | |||
| 189 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | ||
| 190 | #interrupt-cells = <2>; | ||
| 191 | interrupt-controller; | ||
| 192 | |||
| 193 | ti,system-power-controller; | ||
| 194 | |||
| 195 | #gpio-cells = <2>; | ||
| 196 | gpio-controller; | ||
| 197 | |||
| 198 | vcc1-supply = <&sys_3v3_reg>; | ||
| 199 | vcc2-supply = <&sys_3v3_reg>; | ||
| 200 | vcc3-supply = <&vio_reg>; | ||
| 201 | vcc4-supply = <&sys_3v3_reg>; | ||
| 202 | vcc5-supply = <&sys_3v3_reg>; | ||
| 203 | vcc6-supply = <&vio_reg>; | ||
| 204 | vcc7-supply = <&sys_5v0_reg>; | ||
| 205 | vccio-supply = <&sys_3v3_reg>; | ||
| 206 | |||
| 207 | regulators { | ||
| 208 | /* SW1: +V1.35_VDDIO_DDR */ | ||
| 209 | vdd1_reg: vdd1 { | ||
| 210 | regulator-name = "vddio_ddr_1v35"; | ||
| 211 | regulator-min-microvolt = <1350000>; | ||
| 212 | regulator-max-microvolt = <1350000>; | ||
| 213 | regulator-always-on; | ||
| 214 | }; | ||
| 215 | |||
| 216 | /* SW2: unused */ | ||
| 217 | |||
| 218 | /* SW CTRL: +V1.0_VDD_CPU */ | ||
| 219 | vddctrl_reg: vddctrl { | ||
| 220 | regulator-name = "vdd_cpu,vdd_sys"; | ||
| 221 | regulator-min-microvolt = <1150000>; | ||
| 222 | regulator-max-microvolt = <1150000>; | ||
| 223 | regulator-always-on; | ||
| 224 | }; | ||
| 225 | |||
| 226 | /* SWIO: +V1.8 */ | ||
| 227 | vio_reg: vio { | ||
| 228 | regulator-name = "vdd_1v8_gen"; | ||
| 229 | regulator-min-microvolt = <1800000>; | ||
| 230 | regulator-max-microvolt = <1800000>; | ||
| 231 | regulator-always-on; | ||
| 232 | }; | ||
| 233 | |||
| 234 | /* LDO1: unused */ | ||
| 235 | |||
| 236 | /* | ||
| 237 | * EN_+V3.3 switching via FET: | ||
| 238 | * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN | ||
| 239 | * see also v3_3 fixed supply | ||
| 240 | */ | ||
| 241 | ldo2_reg: ldo2 { | ||
| 242 | regulator-name = "en_3v3"; | ||
| 243 | regulator-min-microvolt = <3300000>; | ||
| 244 | regulator-max-microvolt = <3300000>; | ||
| 245 | regulator-always-on; | ||
| 246 | }; | ||
| 247 | |||
| 248 | /* LDO3: unused */ | ||
| 249 | |||
| 250 | /* +V1.2_VDD_RTC */ | ||
| 251 | ldo4_reg: ldo4 { | ||
| 252 | regulator-name = "vdd_rtc"; | ||
| 253 | regulator-min-microvolt = <1200000>; | ||
| 254 | regulator-max-microvolt = <1200000>; | ||
| 255 | regulator-always-on; | ||
| 256 | }; | ||
| 257 | |||
| 258 | /* | ||
| 259 | * +V2.8_AVDD_VDAC: | ||
| 260 | * only required for analog RGB | ||
| 261 | */ | ||
| 262 | ldo5_reg: ldo5 { | ||
| 263 | regulator-name = "avdd_vdac"; | ||
| 264 | regulator-min-microvolt = <2800000>; | ||
| 265 | regulator-max-microvolt = <2800000>; | ||
| 266 | regulator-always-on; | ||
| 267 | }; | ||
| 268 | |||
| 269 | /* | ||
| 270 | * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V | ||
| 271 | * but LDO6 can't set voltage in 50mV | ||
| 272 | * granularity | ||
| 273 | */ | ||
| 274 | ldo6_reg: ldo6 { | ||
| 275 | regulator-name = "avdd_plle"; | ||
| 276 | regulator-min-microvolt = <1100000>; | ||
| 277 | regulator-max-microvolt = <1100000>; | ||
| 278 | }; | ||
| 279 | |||
| 280 | /* +V1.2_AVDD_PLL */ | ||
| 281 | ldo7_reg: ldo7 { | ||
| 282 | regulator-name = "avdd_pll"; | ||
| 283 | regulator-min-microvolt = <1200000>; | ||
| 284 | regulator-max-microvolt = <1200000>; | ||
| 285 | regulator-always-on; | ||
| 286 | }; | ||
| 287 | |||
| 288 | /* +V1.0_VDD_DDR_HS */ | ||
| 289 | ldo8_reg: ldo8 { | ||
| 290 | regulator-name = "vdd_ddr_hs"; | ||
| 291 | regulator-min-microvolt = <1000000>; | ||
| 292 | regulator-max-microvolt = <1000000>; | ||
| 293 | regulator-always-on; | ||
| 294 | }; | ||
| 295 | }; | ||
| 296 | }; | ||
| 297 | |||
| 298 | /* | ||
| 299 | * LM95245 temperature sensor | ||
| 300 | * Note: OVERT_N directly connected to PMIC PWRDN | ||
| 301 | */ | ||
| 302 | temp-sensor@4c { | ||
| 303 | compatible = "national,lm95245"; | ||
| 304 | reg = <0x4c>; | ||
| 305 | }; | ||
| 306 | |||
| 307 | /* SW: +V1.2_VDD_CORE */ | ||
| 308 | tps62362@60 { | ||
| 309 | compatible = "ti,tps62362"; | ||
| 310 | reg = <0x60>; | ||
| 311 | |||
| 312 | regulator-name = "tps62362-vout"; | ||
| 313 | regulator-min-microvolt = <900000>; | ||
| 314 | regulator-max-microvolt = <1400000>; | ||
| 315 | regulator-boot-on; | ||
| 316 | regulator-always-on; | ||
| 317 | ti,vsel0-state-low; | ||
| 318 | /* VSEL1: EN_CORE_DVFS_N low for DVFS */ | ||
| 319 | ti,vsel1-state-low; | ||
| 320 | }; | ||
| 321 | }; | ||
| 322 | |||
| 323 | pmc@7000e400 { | ||
| 324 | nvidia,invert-interrupt; | ||
| 325 | nvidia,suspend-mode = <1>; | ||
| 326 | nvidia,cpu-pwr-good-time = <5000>; | ||
| 327 | nvidia,cpu-pwr-off-time = <5000>; | ||
| 328 | nvidia,core-pwr-good-time = <3845 3845>; | ||
| 329 | nvidia,core-pwr-off-time = <0>; | ||
| 330 | nvidia,core-power-req-active-high; | ||
| 331 | nvidia,sys-clock-req-active-high; | ||
| 332 | }; | ||
| 333 | |||
| 334 | emmc: sdhci@78000600 { | ||
| 335 | status = "okay"; | ||
| 336 | bus-width = <8>; | ||
| 337 | non-removable; | ||
| 338 | }; | ||
| 339 | |||
| 340 | /* EHCI instance 1: USB2_DP/N -> AX88772B */ | ||
| 341 | usb@7d004000 { | ||
| 342 | status = "okay"; | ||
| 343 | }; | ||
| 344 | |||
| 345 | usb-phy@7d004000 { | ||
| 346 | status = "okay"; | ||
| 347 | nvidia,is-wired = <1>; | ||
| 348 | }; | ||
| 349 | |||
| 350 | clocks { | ||
| 351 | compatible = "simple-bus"; | ||
| 352 | #address-cells = <1>; | ||
| 353 | #size-cells = <0>; | ||
| 354 | |||
| 355 | clk32k_in: clk@0 { | ||
| 356 | compatible = "fixed-clock"; | ||
| 357 | reg=<0>; | ||
| 358 | #clock-cells = <0>; | ||
| 359 | clock-frequency = <32768>; | ||
| 360 | }; | ||
| 361 | }; | ||
| 362 | |||
| 363 | regulators { | ||
| 364 | compatible = "simple-bus"; | ||
| 365 | #address-cells = <1>; | ||
| 366 | #size-cells = <0>; | ||
| 367 | |||
| 368 | sys_3v3_reg: regulator@100 { | ||
| 369 | compatible = "regulator-fixed"; | ||
| 370 | reg = <100>; | ||
| 371 | regulator-name = "3v3"; | ||
| 372 | regulator-min-microvolt = <3300000>; | ||
| 373 | regulator-max-microvolt = <3300000>; | ||
| 374 | regulator-always-on; | ||
| 375 | }; | ||
| 376 | }; | ||
| 377 | }; | ||
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi index 86cfc7d15ca7..36ae9160b558 100644 --- a/arch/arm/boot/dts/twl4030.dtsi +++ b/arch/arm/boot/dts/twl4030.dtsi | |||
| @@ -152,4 +152,10 @@ | |||
| 152 | keypad,num-rows = <8>; | 152 | keypad,num-rows = <8>; |
| 153 | keypad,num-columns = <8>; | 153 | keypad,num-columns = <8>; |
| 154 | }; | 154 | }; |
| 155 | |||
| 156 | twl_madc: madc { | ||
| 157 | compatible = "ti,twl4030-madc"; | ||
| 158 | interrupts = <3>; | ||
| 159 | #io-channel-cells = <1>; | ||
| 160 | }; | ||
| 155 | }; | 161 | }; |
diff --git a/arch/arm/boot/dts/twl4030_omap3.dtsi b/arch/arm/boot/dts/twl4030_omap3.dtsi index c353ef0a6ac7..3537ae5b2146 100644 --- a/arch/arm/boot/dts/twl4030_omap3.dtsi +++ b/arch/arm/boot/dts/twl4030_omap3.dtsi | |||
| @@ -8,7 +8,7 @@ | |||
| 8 | 8 | ||
| 9 | &twl { | 9 | &twl { |
| 10 | pinctrl-names = "default"; | 10 | pinctrl-names = "default"; |
| 11 | pinctrl-0 = <&twl4030_pins>; | 11 | pinctrl-0 = <&twl4030_pins &twl4030_vpins>; |
| 12 | }; | 12 | }; |
| 13 | 13 | ||
| 14 | &omap3_pmx_core { | 14 | &omap3_pmx_core { |
| @@ -23,3 +23,20 @@ | |||
| 23 | >; | 23 | >; |
| 24 | }; | 24 | }; |
| 25 | }; | 25 | }; |
| 26 | |||
| 27 | /* | ||
| 28 | * If your board is not using the I2C4 pins with twl4030, then don't include | ||
| 29 | * this file. For proper idle mode signaling with sys_clkreq and sys_off_mode | ||
| 30 | * pins we need to configure I2C4, or else use the legacy sys_nvmode1 and | ||
| 31 | * sys_nvmode2 signaling. | ||
| 32 | */ | ||
| 33 | &omap3_pmx_wkup { | ||
| 34 | twl4030_vpins: pinmux_twl4030_vpins { | ||
| 35 | pinctrl-single,pins = < | ||
| 36 | OMAP3_WKUP_IOPAD(0x2a00, PIN_INPUT | MUX_MODE0) /* i2c4_scl.i2c4_scl */ | ||
| 37 | OMAP3_WKUP_IOPAD(0x2a02, PIN_INPUT | MUX_MODE0) /* i2c4_sda.i2c4_sda */ | ||
| 38 | OMAP3_WKUP_IOPAD(0x2a06, PIN_OUTPUT | MUX_MODE0) /* sys_clkreq.sys_clkreq */ | ||
| 39 | OMAP3_WKUP_IOPAD(0x2a18, PIN_OUTPUT | MUX_MODE0) /* sys_off_mode.sys_off_mode */ | ||
| 40 | >; | ||
| 41 | }; | ||
| 42 | }; | ||
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index ac870fb3fa0d..756c986995a3 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | |||
| @@ -74,8 +74,24 @@ | |||
| 74 | v2m_sysreg: sysreg@010000 { | 74 | v2m_sysreg: sysreg@010000 { |
| 75 | compatible = "arm,vexpress-sysreg"; | 75 | compatible = "arm,vexpress-sysreg"; |
| 76 | reg = <0x010000 0x1000>; | 76 | reg = <0x010000 0x1000>; |
| 77 | gpio-controller; | 77 | |
| 78 | #gpio-cells = <2>; | 78 | v2m_led_gpios: sys_led@08 { |
| 79 | compatible = "arm,vexpress-sysreg,sys_led"; | ||
| 80 | gpio-controller; | ||
| 81 | #gpio-cells = <2>; | ||
| 82 | }; | ||
| 83 | |||
| 84 | v2m_mmc_gpios: sys_mci@48 { | ||
| 85 | compatible = "arm,vexpress-sysreg,sys_mci"; | ||
| 86 | gpio-controller; | ||
| 87 | #gpio-cells = <2>; | ||
| 88 | }; | ||
| 89 | |||
| 90 | v2m_flash_gpios: sys_flash@4c { | ||
| 91 | compatible = "arm,vexpress-sysreg,sys_flash"; | ||
| 92 | gpio-controller; | ||
| 93 | #gpio-cells = <2>; | ||
| 94 | }; | ||
| 79 | }; | 95 | }; |
| 80 | 96 | ||
| 81 | v2m_sysctl: sysctl@020000 { | 97 | v2m_sysctl: sysctl@020000 { |
| @@ -113,8 +129,8 @@ | |||
| 113 | compatible = "arm,pl180", "arm,primecell"; | 129 | compatible = "arm,pl180", "arm,primecell"; |
| 114 | reg = <0x050000 0x1000>; | 130 | reg = <0x050000 0x1000>; |
| 115 | interrupts = <9 10>; | 131 | interrupts = <9 10>; |
| 116 | cd-gpios = <&v2m_sysreg 0 0>; | 132 | cd-gpios = <&v2m_mmc_gpios 0 0>; |
| 117 | wp-gpios = <&v2m_sysreg 1 0>; | 133 | wp-gpios = <&v2m_mmc_gpios 1 0>; |
| 118 | max-frequency = <12000000>; | 134 | max-frequency = <12000000>; |
| 119 | vmmc-supply = <&v2m_fixed_3v3>; | 135 | vmmc-supply = <&v2m_fixed_3v3>; |
| 120 | clocks = <&v2m_clk24mhz>, <&smbclk>; | 136 | clocks = <&v2m_clk24mhz>, <&smbclk>; |
| @@ -265,6 +281,58 @@ | |||
| 265 | clock-output-names = "v2m:refclk32khz"; | 281 | clock-output-names = "v2m:refclk32khz"; |
| 266 | }; | 282 | }; |
| 267 | 283 | ||
| 284 | leds { | ||
| 285 | compatible = "gpio-leds"; | ||
| 286 | |||
| 287 | user@1 { | ||
| 288 | label = "v2m:green:user1"; | ||
| 289 | gpios = <&v2m_led_gpios 0 0>; | ||
| 290 | linux,default-trigger = "heartbeat"; | ||
| 291 | }; | ||
| 292 | |||
| 293 | user@2 { | ||
| 294 | label = "v2m:green:user2"; | ||
| 295 | gpios = <&v2m_led_gpios 1 0>; | ||
| 296 | linux,default-trigger = "mmc0"; | ||
| 297 | }; | ||
| 298 | |||
| 299 | user@3 { | ||
| 300 | label = "v2m:green:user3"; | ||
| 301 | gpios = <&v2m_led_gpios 2 0>; | ||
| 302 | linux,default-trigger = "cpu0"; | ||
| 303 | }; | ||
| 304 | |||
| 305 | user@4 { | ||
| 306 | label = "v2m:green:user4"; | ||
| 307 | gpios = <&v2m_led_gpios 3 0>; | ||
| 308 | linux,default-trigger = "cpu1"; | ||
| 309 | }; | ||
| 310 | |||
| 311 | user@5 { | ||
| 312 | label = "v2m:green:user5"; | ||
| 313 | gpios = <&v2m_led_gpios 4 0>; | ||
| 314 | linux,default-trigger = "cpu2"; | ||
| 315 | }; | ||
| 316 | |||
| 317 | user@6 { | ||
| 318 | label = "v2m:green:user6"; | ||
| 319 | gpios = <&v2m_led_gpios 5 0>; | ||
| 320 | linux,default-trigger = "cpu3"; | ||
| 321 | }; | ||
| 322 | |||
| 323 | user@7 { | ||
| 324 | label = "v2m:green:user7"; | ||
| 325 | gpios = <&v2m_led_gpios 6 0>; | ||
| 326 | linux,default-trigger = "cpu4"; | ||
| 327 | }; | ||
| 328 | |||
| 329 | user@8 { | ||
| 330 | label = "v2m:green:user8"; | ||
| 331 | gpios = <&v2m_led_gpios 7 0>; | ||
| 332 | linux,default-trigger = "cpu5"; | ||
| 333 | }; | ||
| 334 | }; | ||
| 335 | |||
| 268 | mcc { | 336 | mcc { |
| 269 | compatible = "arm,vexpress,config-bus"; | 337 | compatible = "arm,vexpress,config-bus"; |
| 270 | arm,vexpress,config-bridge = <&v2m_sysreg>; | 338 | arm,vexpress,config-bridge = <&v2m_sysreg>; |
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index f1420368355b..ba856d604fb7 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi | |||
| @@ -73,8 +73,24 @@ | |||
| 73 | v2m_sysreg: sysreg@00000 { | 73 | v2m_sysreg: sysreg@00000 { |
| 74 | compatible = "arm,vexpress-sysreg"; | 74 | compatible = "arm,vexpress-sysreg"; |
| 75 | reg = <0x00000 0x1000>; | 75 | reg = <0x00000 0x1000>; |
| 76 | gpio-controller; | 76 | |
| 77 | #gpio-cells = <2>; | 77 | v2m_led_gpios: sys_led@08 { |
| 78 | compatible = "arm,vexpress-sysreg,sys_led"; | ||
| 79 | gpio-controller; | ||
| 80 | #gpio-cells = <2>; | ||
| 81 | }; | ||
| 82 | |||
| 83 | v2m_mmc_gpios: sys_mci@48 { | ||
| 84 | compatible = "arm,vexpress-sysreg,sys_mci"; | ||
| 85 | gpio-controller; | ||
| 86 | #gpio-cells = <2>; | ||
| 87 | }; | ||
| 88 | |||
| 89 | v2m_flash_gpios: sys_flash@4c { | ||
| 90 | compatible = "arm,vexpress-sysreg,sys_flash"; | ||
| 91 | gpio-controller; | ||
| 92 | #gpio-cells = <2>; | ||
| 93 | }; | ||
| 78 | }; | 94 | }; |
| 79 | 95 | ||
| 80 | v2m_sysctl: sysctl@01000 { | 96 | v2m_sysctl: sysctl@01000 { |
| @@ -112,8 +128,8 @@ | |||
| 112 | compatible = "arm,pl180", "arm,primecell"; | 128 | compatible = "arm,pl180", "arm,primecell"; |
| 113 | reg = <0x05000 0x1000>; | 129 | reg = <0x05000 0x1000>; |
| 114 | interrupts = <9 10>; | 130 | interrupts = <9 10>; |
| 115 | cd-gpios = <&v2m_sysreg 0 0>; | 131 | cd-gpios = <&v2m_mmc_gpios 0 0>; |
| 116 | wp-gpios = <&v2m_sysreg 1 0>; | 132 | wp-gpios = <&v2m_mmc_gpios 1 0>; |
| 117 | max-frequency = <12000000>; | 133 | max-frequency = <12000000>; |
| 118 | vmmc-supply = <&v2m_fixed_3v3>; | 134 | vmmc-supply = <&v2m_fixed_3v3>; |
| 119 | clocks = <&v2m_clk24mhz>, <&smbclk>; | 135 | clocks = <&v2m_clk24mhz>, <&smbclk>; |
| @@ -264,6 +280,58 @@ | |||
| 264 | clock-output-names = "v2m:refclk32khz"; | 280 | clock-output-names = "v2m:refclk32khz"; |
| 265 | }; | 281 | }; |
| 266 | 282 | ||
| 283 | leds { | ||
| 284 | compatible = "gpio-leds"; | ||
| 285 | |||
| 286 | user@1 { | ||
| 287 | label = "v2m:green:user1"; | ||
| 288 | gpios = <&v2m_led_gpios 0 0>; | ||
| 289 | linux,default-trigger = "heartbeat"; | ||
| 290 | }; | ||
| 291 | |||
| 292 | user@2 { | ||
| 293 | label = "v2m:green:user2"; | ||
| 294 | gpios = <&v2m_led_gpios 1 0>; | ||
| 295 | linux,default-trigger = "mmc0"; | ||
| 296 | }; | ||
| 297 | |||
| 298 | user@3 { | ||
| 299 | label = "v2m:green:user3"; | ||
| 300 | gpios = <&v2m_led_gpios 2 0>; | ||
| 301 | linux,default-trigger = "cpu0"; | ||
| 302 | }; | ||
| 303 | |||
| 304 | user@4 { | ||
| 305 | label = "v2m:green:user4"; | ||
| 306 | gpios = <&v2m_led_gpios 3 0>; | ||
| 307 | linux,default-trigger = "cpu1"; | ||
| 308 | }; | ||
| 309 | |||
| 310 | user@5 { | ||
| 311 | label = "v2m:green:user5"; | ||
| 312 | gpios = <&v2m_led_gpios 4 0>; | ||
| 313 | linux,default-trigger = "cpu2"; | ||
| 314 | }; | ||
| 315 | |||
| 316 | user@6 { | ||
| 317 | label = "v2m:green:user6"; | ||
| 318 | gpios = <&v2m_led_gpios 5 0>; | ||
| 319 | linux,default-trigger = "cpu3"; | ||
| 320 | }; | ||
| 321 | |||
| 322 | user@7 { | ||
| 323 | label = "v2m:green:user7"; | ||
| 324 | gpios = <&v2m_led_gpios 6 0>; | ||
| 325 | linux,default-trigger = "cpu4"; | ||
| 326 | }; | ||
| 327 | |||
| 328 | user@8 { | ||
| 329 | label = "v2m:green:user8"; | ||
| 330 | gpios = <&v2m_led_gpios 7 0>; | ||
| 331 | linux,default-trigger = "cpu5"; | ||
| 332 | }; | ||
| 333 | }; | ||
| 334 | |||
| 267 | mcc { | 335 | mcc { |
| 268 | compatible = "arm,vexpress,config-bus"; | 336 | compatible = "arm,vexpress,config-bus"; |
| 269 | arm,vexpress,config-bridge = <&v2m_sysreg>; | 337 | arm,vexpress,config-bridge = <&v2m_sysreg>; |
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 15f98cbcb75a..a25c262326dc 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | |||
| @@ -312,6 +312,7 @@ | |||
| 312 | arm,vexpress-sysreg,func = <12 0>; | 312 | arm,vexpress-sysreg,func = <12 0>; |
| 313 | label = "A15 Pcore"; | 313 | label = "A15 Pcore"; |
| 314 | }; | 314 | }; |
| 315 | |||
| 315 | power@1 { | 316 | power@1 { |
| 316 | /* Total power for the three A7 cores */ | 317 | /* Total power for the three A7 cores */ |
| 317 | compatible = "arm,vexpress-power"; | 318 | compatible = "arm,vexpress-power"; |
| @@ -322,14 +323,14 @@ | |||
| 322 | energy@0 { | 323 | energy@0 { |
| 323 | /* Total energy for the two A15 cores */ | 324 | /* Total energy for the two A15 cores */ |
| 324 | compatible = "arm,vexpress-energy"; | 325 | compatible = "arm,vexpress-energy"; |
| 325 | arm,vexpress-sysreg,func = <13 0>; | 326 | arm,vexpress-sysreg,func = <13 0>, <13 1>; |
| 326 | label = "A15 Jcore"; | 327 | label = "A15 Jcore"; |
| 327 | }; | 328 | }; |
| 328 | 329 | ||
| 329 | energy@2 { | 330 | energy@2 { |
| 330 | /* Total energy for the three A7 cores */ | 331 | /* Total energy for the three A7 cores */ |
| 331 | compatible = "arm,vexpress-energy"; | 332 | compatible = "arm,vexpress-energy"; |
| 332 | arm,vexpress-sysreg,func = <13 2>; | 333 | arm,vexpress-sysreg,func = <13 2>, <13 3>; |
| 333 | label = "A7 Jcore"; | 334 | label = "A7 Jcore"; |
| 334 | }; | 335 | }; |
| 335 | }; | 336 | }; |
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts index c544a5504591..d2709b73316b 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts | |||
| @@ -88,6 +88,14 @@ | |||
| 88 | interrupts = <1 13 0x304>; | 88 | interrupts = <1 13 0x304>; |
| 89 | }; | 89 | }; |
| 90 | 90 | ||
| 91 | timer@2c000200 { | ||
| 92 | compatible = "arm,cortex-a5-global-timer", | ||
| 93 | "arm,cortex-a9-global-timer"; | ||
| 94 | reg = <0x2c000200 0x20>; | ||
| 95 | interrupts = <1 11 0x304>; | ||
| 96 | clocks = <&oscclk0>; | ||
| 97 | }; | ||
| 98 | |||
| 91 | watchdog@2c000620 { | 99 | watchdog@2c000620 { |
| 92 | compatible = "arm,cortex-a5-twd-wdt"; | 100 | compatible = "arm,cortex-a5-twd-wdt"; |
| 93 | reg = <0x2c000620 0x20>; | 101 | reg = <0x2c000620 0x20>; |
| @@ -120,7 +128,7 @@ | |||
| 120 | compatible = "arm,vexpress,config-bus"; | 128 | compatible = "arm,vexpress,config-bus"; |
| 121 | arm,vexpress,config-bridge = <&v2m_sysreg>; | 129 | arm,vexpress,config-bridge = <&v2m_sysreg>; |
| 122 | 130 | ||
| 123 | osc@0 { | 131 | oscclk0: osc@0 { |
| 124 | /* CPU and internal AXI reference clock */ | 132 | /* CPU and internal AXI reference clock */ |
| 125 | compatible = "arm,vexpress-osc"; | 133 | compatible = "arm,vexpress-osc"; |
| 126 | arm,vexpress-sysreg,func = <1 0>; | 134 | arm,vexpress-sysreg,func = <1 0>; |
diff --git a/arch/arm/boot/dts/vf610-colibri.dts b/arch/arm/boot/dts/vf610-colibri.dts new file mode 100644 index 000000000000..aecc7dbc65e8 --- /dev/null +++ b/arch/arm/boot/dts/vf610-colibri.dts | |||
| @@ -0,0 +1,123 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2014 Toradex AG | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | #include "vf610.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Toradex Colibri VF61 COM"; | ||
| 15 | compatible = "toradex,vf610-colibri", "fsl,vf610"; | ||
| 16 | |||
| 17 | chosen { | ||
| 18 | bootargs = "console=ttyLP0,115200"; | ||
| 19 | }; | ||
| 20 | |||
| 21 | memory { | ||
| 22 | reg = <0x80000000 0x10000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | clocks { | ||
| 26 | enet_ext { | ||
| 27 | compatible = "fixed-clock"; | ||
| 28 | #clock-cells = <0>; | ||
| 29 | clock-frequency = <50000000>; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | |||
| 33 | }; | ||
| 34 | |||
| 35 | &esdhc1 { | ||
| 36 | pinctrl-names = "default"; | ||
| 37 | pinctrl-0 = <&pinctrl_esdhc1>; | ||
| 38 | bus-width = <4>; | ||
| 39 | status = "okay"; | ||
| 40 | }; | ||
| 41 | |||
| 42 | &fec1 { | ||
| 43 | phy-mode = "rmii"; | ||
| 44 | pinctrl-names = "default"; | ||
| 45 | pinctrl-0 = <&pinctrl_fec1>; | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
| 48 | |||
| 49 | &L2 { | ||
| 50 | arm,data-latency = <2 1 2>; | ||
| 51 | arm,tag-latency = <3 2 3>; | ||
| 52 | }; | ||
| 53 | |||
| 54 | &uart0 { | ||
| 55 | pinctrl-names = "default"; | ||
| 56 | pinctrl-0 = <&pinctrl_uart0>; | ||
| 57 | status = "okay"; | ||
| 58 | }; | ||
| 59 | |||
| 60 | &uart1 { | ||
| 61 | pinctrl-names = "default"; | ||
| 62 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 63 | status = "okay"; | ||
| 64 | }; | ||
| 65 | |||
| 66 | &uart2 { | ||
| 67 | pinctrl-names = "default"; | ||
| 68 | pinctrl-0 = <&pinctrl_uart2>; | ||
| 69 | status = "okay"; | ||
| 70 | }; | ||
| 71 | |||
| 72 | &iomuxc { | ||
| 73 | vf610-colibri { | ||
| 74 | pinctrl_esdhc1: esdhc1grp { | ||
| 75 | fsl,fsl,pins = < | ||
| 76 | VF610_PAD_PTA24__ESDHC1_CLK 0x31ef | ||
| 77 | VF610_PAD_PTA25__ESDHC1_CMD 0x31ef | ||
| 78 | VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef | ||
| 79 | VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef | ||
| 80 | VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef | ||
| 81 | VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef | ||
| 82 | VF610_PAD_PTB20__GPIO_42 0x219d | ||
| 83 | >; | ||
| 84 | }; | ||
| 85 | |||
| 86 | pinctrl_fec1: fec1grp { | ||
| 87 | fsl,pins = < | ||
| 88 | VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 | ||
| 89 | VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 | ||
| 90 | VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 | ||
| 91 | VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 | ||
| 92 | VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 | ||
| 93 | VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 | ||
| 94 | VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 | ||
| 95 | VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 | ||
| 96 | VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 | ||
| 97 | >; | ||
| 98 | }; | ||
| 99 | |||
| 100 | pinctrl_uart0: uart0grp { | ||
| 101 | fsl,pins = < | ||
| 102 | VF610_PAD_PTB10__UART0_TX 0x21a2 | ||
| 103 | VF610_PAD_PTB11__UART0_RX 0x21a1 | ||
| 104 | >; | ||
| 105 | }; | ||
| 106 | |||
| 107 | pinctrl_uart1: uart1grp { | ||
| 108 | fsl,pins = < | ||
| 109 | VF610_PAD_PTB4__UART1_TX 0x21a2 | ||
| 110 | VF610_PAD_PTB5__UART1_RX 0x21a1 | ||
| 111 | >; | ||
| 112 | }; | ||
| 113 | |||
| 114 | pinctrl_uart2: uart2grp { | ||
| 115 | fsl,pins = < | ||
| 116 | VF610_PAD_PTD0__UART2_TX 0x21a2 | ||
| 117 | VF610_PAD_PTD1__UART2_RX 0x21a1 | ||
| 118 | VF610_PAD_PTD2__UART2_RTS 0x21a2 | ||
| 119 | VF610_PAD_PTD3__UART2_CTS 0x21a1 | ||
| 120 | >; | ||
| 121 | }; | ||
| 122 | }; | ||
| 123 | }; | ||
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index ded361075aab..11d733406c7e 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts | |||
| @@ -113,6 +113,13 @@ | |||
| 113 | }; | 113 | }; |
| 114 | }; | 114 | }; |
| 115 | 115 | ||
| 116 | &esdhc1 { | ||
| 117 | pinctrl-names = "default"; | ||
| 118 | pinctrl-0 = <&pinctrl_esdhc1>; | ||
| 119 | bus-width = <4>; | ||
| 120 | status = "okay"; | ||
| 121 | }; | ||
| 122 | |||
| 116 | &fec0 { | 123 | &fec0 { |
| 117 | phy-mode = "rmii"; | 124 | phy-mode = "rmii"; |
| 118 | pinctrl-names = "default"; | 125 | pinctrl-names = "default"; |
| @@ -160,6 +167,18 @@ | |||
| 160 | >; | 167 | >; |
| 161 | }; | 168 | }; |
| 162 | 169 | ||
| 170 | pinctrl_esdhc1: esdhc1grp { | ||
| 171 | fsl,fsl,pins = < | ||
| 172 | VF610_PAD_PTA24__ESDHC1_CLK 0x31ef | ||
| 173 | VF610_PAD_PTA25__ESDHC1_CMD 0x31ef | ||
| 174 | VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef | ||
| 175 | VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef | ||
| 176 | VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef | ||
| 177 | VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef | ||
| 178 | VF610_PAD_PTA7__GPIO_134 0x219d | ||
| 179 | >; | ||
| 180 | }; | ||
| 181 | |||
| 163 | pinctrl_fec0: fec0grp { | 182 | pinctrl_fec0: fec0grp { |
| 164 | fsl,pins = < | 183 | fsl,pins = < |
| 165 | VF610_PAD_PTA6__RMII_CLKIN 0x30d1 | 184 | VF610_PAD_PTA6__RMII_CLKIN 0x30d1 |
| @@ -196,6 +215,17 @@ | |||
| 196 | >; | 215 | >; |
| 197 | }; | 216 | }; |
| 198 | 217 | ||
| 218 | pinctrl_pwm0: pwm0grp { | ||
| 219 | fsl,pins = < | ||
| 220 | VF610_PAD_PTB0__FTM0_CH0 0x1582 | ||
| 221 | VF610_PAD_PTB1__FTM0_CH1 0x1582 | ||
| 222 | VF610_PAD_PTB2__FTM0_CH2 0x1582 | ||
| 223 | VF610_PAD_PTB3__FTM0_CH3 0x1582 | ||
| 224 | VF610_PAD_PTB6__FTM0_CH6 0x1582 | ||
| 225 | VF610_PAD_PTB7__FTM0_CH7 0x1582 | ||
| 226 | >; | ||
| 227 | }; | ||
| 228 | |||
| 199 | pinctrl_sai2: sai2grp { | 229 | pinctrl_sai2: sai2grp { |
| 200 | fsl,pins = < | 230 | fsl,pins = < |
| 201 | VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed | 231 | VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed |
| @@ -217,6 +247,12 @@ | |||
| 217 | }; | 247 | }; |
| 218 | }; | 248 | }; |
| 219 | 249 | ||
| 250 | &pwm0 { | ||
| 251 | pinctrl-names = "default"; | ||
| 252 | pinctrl-0 = <&pinctrl_pwm0>; | ||
| 253 | status = "okay"; | ||
| 254 | }; | ||
| 255 | |||
| 220 | &sai2 { | 256 | &sai2 { |
| 221 | #sound-dai-cells = <0>; | 257 | #sound-dai-cells = <0>; |
| 222 | pinctrl-names = "default"; | 258 | pinctrl-names = "default"; |
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index b8ce0aa7b157..6cc314e7b8fb 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi | |||
| @@ -183,6 +183,19 @@ | |||
| 183 | clock-names = "pit"; | 183 | clock-names = "pit"; |
| 184 | }; | 184 | }; |
| 185 | 185 | ||
| 186 | pwm0: pwm@40038000 { | ||
| 187 | compatible = "fsl,vf610-ftm-pwm"; | ||
| 188 | #pwm-cells = <3>; | ||
| 189 | reg = <0x40038000 0x1000>; | ||
| 190 | clock-names = "ftm_sys", "ftm_ext", | ||
| 191 | "ftm_fix", "ftm_cnt_clk_en"; | ||
| 192 | clocks = <&clks VF610_CLK_FTM0>, | ||
| 193 | <&clks VF610_CLK_FTM0_EXT_SEL>, | ||
| 194 | <&clks VF610_CLK_FTM0_FIX_SEL>, | ||
| 195 | <&clks VF610_CLK_FTM0_EXT_FIX_EN>; | ||
| 196 | status = "disabled"; | ||
| 197 | }; | ||
| 198 | |||
| 186 | adc0: adc@4003b000 { | 199 | adc0: adc@4003b000 { |
| 187 | compatible = "fsl,vf610-adc"; | 200 | compatible = "fsl,vf610-adc"; |
| 188 | reg = <0x4003b000 0x1000>; | 201 | reg = <0x4003b000 0x1000>; |
| @@ -347,6 +360,30 @@ | |||
| 347 | status = "disabled"; | 360 | status = "disabled"; |
| 348 | }; | 361 | }; |
| 349 | 362 | ||
| 363 | esdhc1: esdhc@400b2000 { | ||
| 364 | compatible = "fsl,imx53-esdhc"; | ||
| 365 | reg = <0x400b2000 0x4000>; | ||
| 366 | interrupts = <0 28 0x04>; | ||
| 367 | clocks = <&clks VF610_CLK_IPG_BUS>, | ||
| 368 | <&clks VF610_CLK_PLATFORM_BUS>, | ||
| 369 | <&clks VF610_CLK_ESDHC1>; | ||
| 370 | clock-names = "ipg", "ahb", "per"; | ||
| 371 | status = "disabled"; | ||
| 372 | }; | ||
| 373 | |||
| 374 | ftm: ftm@400b8000 { | ||
| 375 | compatible = "fsl,ftm-timer"; | ||
| 376 | reg = <0x400b8000 0x1000 0x400b9000 0x1000>; | ||
| 377 | interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; | ||
| 378 | clock-names = "ftm-evt", "ftm-src", | ||
| 379 | "ftm-evt-counter-en", "ftm-src-counter-en"; | ||
| 380 | clocks = <&clks VF610_CLK_FTM2>, | ||
| 381 | <&clks VF610_CLK_FTM3>, | ||
| 382 | <&clks VF610_CLK_FTM2_EXT_FIX_EN>, | ||
| 383 | <&clks VF610_CLK_FTM3_EXT_FIX_EN>; | ||
| 384 | status = "disabled"; | ||
| 385 | }; | ||
| 386 | |||
| 350 | fec0: ethernet@400d0000 { | 387 | fec0: ethernet@400d0000 { |
| 351 | compatible = "fsl,mvf600-fec"; | 388 | compatible = "fsl,mvf600-fec"; |
| 352 | reg = <0x400d0000 0x1000>; | 389 | reg = <0x400d0000 0x1000>; |
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index c1176abc34d9..760bbc463c5b 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2011 Xilinx | 2 | * Copyright (C) 2011 - 2014 Xilinx |
| 3 | * | 3 | * |
| 4 | * This software is licensed under the terms of the GNU General Public | 4 | * This software is licensed under the terms of the GNU General Public |
| 5 | * License version 2, as published by the Free Software Foundation, and | 5 | * License version 2, as published by the Free Software Foundation, and |
| @@ -25,6 +25,7 @@ | |||
| 25 | reg = <0>; | 25 | reg = <0>; |
| 26 | clocks = <&clkc 3>; | 26 | clocks = <&clkc 3>; |
| 27 | clock-latency = <1000>; | 27 | clock-latency = <1000>; |
| 28 | cpu0-supply = <®ulator_vccpint>; | ||
| 28 | operating-points = < | 29 | operating-points = < |
| 29 | /* kHz uV */ | 30 | /* kHz uV */ |
| 30 | 666667 1000000 | 31 | 666667 1000000 |
| @@ -48,6 +49,15 @@ | |||
| 48 | reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; | 49 | reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; |
| 49 | }; | 50 | }; |
| 50 | 51 | ||
| 52 | regulator_vccpint: fixedregulator@0 { | ||
| 53 | compatible = "regulator-fixed"; | ||
| 54 | regulator-name = "VCCPINT"; | ||
| 55 | regulator-min-microvolt = <1000000>; | ||
| 56 | regulator-max-microvolt = <1000000>; | ||
| 57 | regulator-boot-on; | ||
| 58 | regulator-always-on; | ||
| 59 | }; | ||
| 60 | |||
| 51 | amba { | 61 | amba { |
| 52 | compatible = "simple-bus"; | 62 | compatible = "simple-bus"; |
| 53 | #address-cells = <1>; | 63 | #address-cells = <1>; |
| @@ -55,7 +65,7 @@ | |||
| 55 | interrupt-parent = <&intc>; | 65 | interrupt-parent = <&intc>; |
| 56 | ranges; | 66 | ranges; |
| 57 | 67 | ||
| 58 | i2c0: zynq-i2c@e0004000 { | 68 | i2c0: i2c@e0004000 { |
| 59 | compatible = "cdns,i2c-r1p10"; | 69 | compatible = "cdns,i2c-r1p10"; |
| 60 | status = "disabled"; | 70 | status = "disabled"; |
| 61 | clocks = <&clkc 38>; | 71 | clocks = <&clkc 38>; |
| @@ -66,7 +76,7 @@ | |||
| 66 | #size-cells = <0>; | 76 | #size-cells = <0>; |
| 67 | }; | 77 | }; |
| 68 | 78 | ||
| 69 | i2c1: zynq-i2c@e0005000 { | 79 | i2c1: i2c@e0005000 { |
| 70 | compatible = "cdns,i2c-r1p10"; | 80 | compatible = "cdns,i2c-r1p10"; |
| 71 | status = "disabled"; | 81 | status = "disabled"; |
| 72 | clocks = <&clkc 39>; | 82 | clocks = <&clkc 39>; |
| @@ -80,7 +90,6 @@ | |||
| 80 | intc: interrupt-controller@f8f01000 { | 90 | intc: interrupt-controller@f8f01000 { |
| 81 | compatible = "arm,cortex-a9-gic"; | 91 | compatible = "arm,cortex-a9-gic"; |
| 82 | #interrupt-cells = <3>; | 92 | #interrupt-cells = <3>; |
| 83 | #address-cells = <1>; | ||
| 84 | interrupt-controller; | 93 | interrupt-controller; |
| 85 | reg = <0xF8F01000 0x1000>, | 94 | reg = <0xF8F01000 0x1000>, |
| 86 | <0xF8F00100 0x100>; | 95 | <0xF8F00100 0x100>; |
| @@ -95,7 +104,7 @@ | |||
| 95 | cache-level = <2>; | 104 | cache-level = <2>; |
| 96 | }; | 105 | }; |
| 97 | 106 | ||
| 98 | uart0: uart@e0000000 { | 107 | uart0: serial@e0000000 { |
| 99 | compatible = "xlnx,xuartps"; | 108 | compatible = "xlnx,xuartps"; |
| 100 | status = "disabled"; | 109 | status = "disabled"; |
| 101 | clocks = <&clkc 23>, <&clkc 40>; | 110 | clocks = <&clkc 23>, <&clkc 40>; |
| @@ -104,7 +113,7 @@ | |||
| 104 | interrupts = <0 27 4>; | 113 | interrupts = <0 27 4>; |
| 105 | }; | 114 | }; |
| 106 | 115 | ||
| 107 | uart1: uart@e0001000 { | 116 | uart1: serial@e0001000 { |
| 108 | compatible = "xlnx,xuartps"; | 117 | compatible = "xlnx,xuartps"; |
| 109 | status = "disabled"; | 118 | status = "disabled"; |
| 110 | clocks = <&clkc 24>, <&clkc 41>; | 119 | clocks = <&clkc 24>, <&clkc 41>; |
| @@ -131,7 +140,7 @@ | |||
| 131 | clock-names = "pclk", "hclk", "tx_clk"; | 140 | clock-names = "pclk", "hclk", "tx_clk"; |
| 132 | }; | 141 | }; |
| 133 | 142 | ||
| 134 | sdhci0: ps7-sdhci@e0100000 { | 143 | sdhci0: sdhci@e0100000 { |
| 135 | compatible = "arasan,sdhci-8.9a"; | 144 | compatible = "arasan,sdhci-8.9a"; |
| 136 | status = "disabled"; | 145 | status = "disabled"; |
| 137 | clock-names = "clk_xin", "clk_ahb"; | 146 | clock-names = "clk_xin", "clk_ahb"; |
| @@ -141,7 +150,7 @@ | |||
| 141 | reg = <0xe0100000 0x1000>; | 150 | reg = <0xe0100000 0x1000>; |
| 142 | } ; | 151 | } ; |
| 143 | 152 | ||
| 144 | sdhci1: ps7-sdhci@e0101000 { | 153 | sdhci1: sdhci@e0101000 { |
| 145 | compatible = "arasan,sdhci-8.9a"; | 154 | compatible = "arasan,sdhci-8.9a"; |
| 146 | status = "disabled"; | 155 | status = "disabled"; |
| 147 | clock-names = "clk_xin", "clk_ahb"; | 156 | clock-names = "clk_xin", "clk_ahb"; |
| @@ -177,6 +186,11 @@ | |||
| 177 | }; | 186 | }; |
| 178 | }; | 187 | }; |
| 179 | 188 | ||
| 189 | devcfg: devcfg@f8007000 { | ||
| 190 | compatible = "xlnx,zynq-devcfg-1.0"; | ||
| 191 | reg = <0xf8007000 0x100>; | ||
| 192 | } ; | ||
| 193 | |||
| 180 | global_timer: timer@f8f00200 { | 194 | global_timer: timer@f8f00200 { |
| 181 | compatible = "arm,cortex-a9-global-timer"; | 195 | compatible = "arm,cortex-a9-global-timer"; |
| 182 | reg = <0xf8f00200 0x20>; | 196 | reg = <0xf8f00200 0x20>; |
| @@ -185,26 +199,27 @@ | |||
| 185 | clocks = <&clkc 4>; | 199 | clocks = <&clkc 4>; |
| 186 | }; | 200 | }; |
| 187 | 201 | ||
| 188 | ttc0: ttc0@f8001000 { | 202 | ttc0: timer@f8001000 { |
| 189 | interrupt-parent = <&intc>; | 203 | interrupt-parent = <&intc>; |
| 190 | interrupts = < 0 10 4 0 11 4 0 12 4 >; | 204 | interrupts = <0 10 4>, <0 11 4>, <0 12 4>; |
| 191 | compatible = "cdns,ttc"; | 205 | compatible = "cdns,ttc"; |
| 192 | clocks = <&clkc 6>; | 206 | clocks = <&clkc 6>; |
| 193 | reg = <0xF8001000 0x1000>; | 207 | reg = <0xF8001000 0x1000>; |
| 194 | }; | 208 | }; |
| 195 | 209 | ||
| 196 | ttc1: ttc1@f8002000 { | 210 | ttc1: timer@f8002000 { |
| 197 | interrupt-parent = <&intc>; | 211 | interrupt-parent = <&intc>; |
| 198 | interrupts = < 0 37 4 0 38 4 0 39 4 >; | 212 | interrupts = <0 37 4>, <0 38 4>, <0 39 4>; |
| 199 | compatible = "cdns,ttc"; | 213 | compatible = "cdns,ttc"; |
| 200 | clocks = <&clkc 6>; | 214 | clocks = <&clkc 6>; |
| 201 | reg = <0xF8002000 0x1000>; | 215 | reg = <0xF8002000 0x1000>; |
| 202 | }; | 216 | }; |
| 203 | scutimer: scutimer@f8f00600 { | 217 | |
| 218 | scutimer: timer@f8f00600 { | ||
| 204 | interrupt-parent = <&intc>; | 219 | interrupt-parent = <&intc>; |
| 205 | interrupts = < 1 13 0x301 >; | 220 | interrupts = <1 13 0x301>; |
| 206 | compatible = "arm,cortex-a9-twd-timer"; | 221 | compatible = "arm,cortex-a9-twd-timer"; |
| 207 | reg = < 0xf8f00600 0x20 >; | 222 | reg = <0xf8f00600 0x20>; |
| 208 | clocks = <&clkc 4>; | 223 | clocks = <&clkc 4>; |
| 209 | } ; | 224 | } ; |
| 210 | }; | 225 | }; |