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-rw-r--r--arch/arm/boot/Makefile22
-rw-r--r--arch/arm/boot/compressed/head.S14
-rw-r--r--arch/arm/boot/dts/Makefile56
-rw-r--r--arch/arm/boot/dts/animeo_ip.dts178
-rw-r--r--arch/arm/boot/dts/at91rm9200.dtsi349
-rw-r--r--arch/arm/boot/dts/at91rm9200ek.dts79
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi295
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi299
-rw-r--r--arch/arm/boot/dts/at91sam9263ek.dts29
-rw-r--r--arch/arm/boot/dts/at91sam9g15.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9g15ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9g20ek_2mmc.dts26
-rw-r--r--arch/arm/boot/dts/at91sam9g20ek_common.dtsi30
-rw-r--r--arch/arm/boot/dts/at91sam9g25.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9g25ek.dts49
-rw-r--r--arch/arm/boot/dts/at91sam9g35.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9g35ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi301
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts48
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi225
-rw-r--r--arch/arm/boot/dts/at91sam9n12ek.dts22
-rw-r--r--arch/arm/boot/dts/at91sam9x25.dtsi49
-rw-r--r--arch/arm/boot/dts/at91sam9x25ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9x35.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9x35ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi270
-rw-r--r--arch/arm/boot/dts/at91sam9x5ek.dtsi101
-rw-r--r--arch/arm/boot/dts/dbx5x0.dtsi14
-rw-r--r--arch/arm/boot/dts/imx28.dtsi1
-rw-r--r--arch/arm/boot/dts/pm9g45.dts165
-rw-r--r--arch/arm/boot/dts/snowball.dts31
-rw-r--r--arch/arm/boot/dts/spear1310-evb.dts4
-rw-r--r--arch/arm/boot/dts/spear1310.dtsi27
-rw-r--r--arch/arm/boot/dts/spear1340-evb.dts4
-rw-r--r--arch/arm/boot/dts/spear1340.dtsi26
-rw-r--r--arch/arm/boot/dts/spear310.dtsi22
-rw-r--r--arch/arm/boot/dts/spear320-evb.dts4
-rw-r--r--arch/arm/boot/dts/spear320.dtsi23
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts4
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi4
40 files changed, 2674 insertions, 273 deletions
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index f2aa09eb658e..abfce280f57b 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -15,8 +15,6 @@ ifneq ($(MACHINE),)
15include $(srctree)/$(MACHINE)/Makefile.boot 15include $(srctree)/$(MACHINE)/Makefile.boot
16endif 16endif
17 17
18include $(srctree)/arch/arm/boot/dts/Makefile
19
20# Note: the following conditions must always be true: 18# Note: the following conditions must always be true:
21# ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET) 19# ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
22# PARAMS_PHYS must be within 4MB of ZRELADDR 20# PARAMS_PHYS must be within 4MB of ZRELADDR
@@ -33,7 +31,7 @@ ifeq ($(CONFIG_XIP_KERNEL),y)
33 31
34$(obj)/xipImage: vmlinux FORCE 32$(obj)/xipImage: vmlinux FORCE
35 $(call if_changed,objcopy) 33 $(call if_changed,objcopy)
36 $(kecho) ' Kernel: $@ is ready (physical address: $(CONFIG_XIP_PHYS_ADDR))' 34 @$(kecho) ' Kernel: $@ is ready (physical address: $(CONFIG_XIP_PHYS_ADDR))'
37 35
38$(obj)/Image $(obj)/zImage: FORCE 36$(obj)/Image $(obj)/zImage: FORCE
39 @echo 'Kernel configured for XIP (CONFIG_XIP_KERNEL=y)' 37 @echo 'Kernel configured for XIP (CONFIG_XIP_KERNEL=y)'
@@ -48,27 +46,17 @@ $(obj)/xipImage: FORCE
48 46
49$(obj)/Image: vmlinux FORCE 47$(obj)/Image: vmlinux FORCE
50 $(call if_changed,objcopy) 48 $(call if_changed,objcopy)
51 $(kecho) ' Kernel: $@ is ready' 49 @$(kecho) ' Kernel: $@ is ready'
52 50
53$(obj)/compressed/vmlinux: $(obj)/Image FORCE 51$(obj)/compressed/vmlinux: $(obj)/Image FORCE
54 $(Q)$(MAKE) $(build)=$(obj)/compressed $@ 52 $(Q)$(MAKE) $(build)=$(obj)/compressed $@
55 53
56$(obj)/zImage: $(obj)/compressed/vmlinux FORCE 54$(obj)/zImage: $(obj)/compressed/vmlinux FORCE
57 $(call if_changed,objcopy) 55 $(call if_changed,objcopy)
58 $(kecho) ' Kernel: $@ is ready' 56 @$(kecho) ' Kernel: $@ is ready'
59 57
60endif 58endif
61 59
62targets += $(dtb-y)
63
64# Rule to build device tree blobs
65$(obj)/%.dtb: $(src)/dts/%.dts FORCE
66 $(call if_changed_dep,dtc)
67
68$(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y))
69
70clean-files := *.dtb
71
72ifneq ($(LOADADDR),) 60ifneq ($(LOADADDR),)
73 UIMAGE_LOADADDR=$(LOADADDR) 61 UIMAGE_LOADADDR=$(LOADADDR)
74else 62else
@@ -90,7 +78,7 @@ fi
90$(obj)/uImage: $(obj)/zImage FORCE 78$(obj)/uImage: $(obj)/zImage FORCE
91 @$(check_for_multiple_loadaddr) 79 @$(check_for_multiple_loadaddr)
92 $(call if_changed,uimage) 80 $(call if_changed,uimage)
93 $(kecho) ' Image $@ is ready' 81 @$(kecho) ' Image $@ is ready'
94 82
95$(obj)/bootp/bootp: $(obj)/zImage initrd FORCE 83$(obj)/bootp/bootp: $(obj)/zImage initrd FORCE
96 $(Q)$(MAKE) $(build)=$(obj)/bootp $@ 84 $(Q)$(MAKE) $(build)=$(obj)/bootp $@
@@ -98,7 +86,7 @@ $(obj)/bootp/bootp: $(obj)/zImage initrd FORCE
98 86
99$(obj)/bootpImage: $(obj)/bootp/bootp FORCE 87$(obj)/bootpImage: $(obj)/bootp/bootp FORCE
100 $(call if_changed,objcopy) 88 $(call if_changed,objcopy)
101 $(kecho) ' Kernel: $@ is ready' 89 @$(kecho) ' Kernel: $@ is ready'
102 90
103PHONY += initrd FORCE 91PHONY += initrd FORCE
104initrd: 92initrd:
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 90275f036cd1..49ca86e37b8d 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -652,6 +652,15 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
652 mov pc, lr 652 mov pc, lr
653ENDPROC(__setup_mmu) 653ENDPROC(__setup_mmu)
654 654
655@ Enable unaligned access on v6, to allow better code generation
656@ for the decompressor C code:
657__armv6_mmu_cache_on:
658 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
659 bic r0, r0, #2 @ A (no unaligned access fault)
660 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
661 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
662 b __armv4_mmu_cache_on
663
655__arm926ejs_mmu_cache_on: 664__arm926ejs_mmu_cache_on:
656#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 665#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
657 mov r0, #4 @ put dcache in WT mode 666 mov r0, #4 @ put dcache in WT mode
@@ -694,6 +703,9 @@ __armv7_mmu_cache_on:
694 bic r0, r0, #1 << 28 @ clear SCTLR.TRE 703 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
695 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 704 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
696 orr r0, r0, #0x003c @ write buffer 705 orr r0, r0, #0x003c @ write buffer
706 bic r0, r0, #2 @ A (no unaligned access fault)
707 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
708 @ (needed for ARM1176)
697#ifdef CONFIG_MMU 709#ifdef CONFIG_MMU
698#ifdef CONFIG_CPU_ENDIAN_BE8 710#ifdef CONFIG_CPU_ENDIAN_BE8
699 orr r0, r0, #1 << 25 @ big-endian page tables 711 orr r0, r0, #1 << 25 @ big-endian page tables
@@ -914,7 +926,7 @@ proc_types:
914 926
915 .word 0x0007b000 @ ARMv6 927 .word 0x0007b000 @ ARMv6
916 .word 0x000ff000 928 .word 0x000ff000
917 W(b) __armv4_mmu_cache_on 929 W(b) __armv6_mmu_cache_on
918 W(b) __armv4_mmu_cache_off 930 W(b) __armv4_mmu_cache_off
919 W(b) __armv6_mmu_cache_flush 931 W(b) __armv6_mmu_cache_flush
920 932
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f37cf9fa5fa0..262493752234 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1,21 +1,37 @@
1ifeq ($(CONFIG_OF),y) 1ifeq ($(CONFIG_OF),y)
2 2
3dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \ 3# Keep at91 dtb files sorted alphabetically for each SoC
4 at91sam9263ek.dtb \ 4# rm9200
5 at91sam9g20ek_2mmc.dtb \ 5dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb
6 at91sam9g20ek.dtb \ 6# sam9260
7 at91sam9g25ek.dtb \ 7dtb-$(CONFIG_ARCH_AT91) += animeo_ip.dtb
8 at91sam9m10g45ek.dtb \ 8dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb
9 at91sam9n12ek.dtb \ 9dtb-$(CONFIG_ARCH_AT91) += ethernut5.dtb
10 ethernut5.dtb \ 10dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb
11 evk-pro3.dtb \ 11dtb-$(CONFIG_ARCH_AT91) += tny_a9260.dtb
12 kizbox.dtb \ 12dtb-$(CONFIG_ARCH_AT91) += usb_a9260.dtb
13 tny_a9260.dtb \ 13# sam9263
14 tny_a9263.dtb \ 14dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
15 tny_a9g20.dtb \ 15dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
16 usb_a9260.dtb \ 16dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb
17 usb_a9263.dtb \ 17# sam9g20
18 usb_a9g20.dtb 18dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb
19dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb
20dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb
21dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb
22dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb
23# sam9g45
24dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
25dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
26# sam9n12
27dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
28# sam9x5
29dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
30dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
31dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
32dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
33dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
34
19dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 35dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
20dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ 36dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
21 dove-cubox.dtb \ 37 dove-cubox.dtb \
@@ -104,4 +120,12 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
104 wm8505-ref.dtb \ 120 wm8505-ref.dtb \
105 wm8650-mid.dtb 121 wm8650-mid.dtb
106 122
123targets += dtbs
107endif 124endif
125
126# *.dtb used to be generated in the directory above. Clean out the
127# old build results so people don't accidentally use them.
128dtbs: $(addprefix $(obj)/, $(dtb-y))
129 $(Q)rm -f $(obj)/../*.dtb
130
131clean-files := *.dtb
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
new file mode 100644
index 000000000000..74d92cd29d87
--- /dev/null
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -0,0 +1,178 @@
1/*
2 * animeo_ip.dts - Device Tree file for Somfy Animeo IP Boards
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only.
7 */
8
9/dts-v1/;
10/include/ "at91sam9260.dtsi"
11
12/ {
13 model = "Somfy Animeo IP";
14 compatible = "somfy,animeo-ip", "atmel,at91sam9260", "atmel,at91sam9";
15
16 aliases {
17 serial0 = &usart1;
18 serial1 = &usart2;
19 serial2 = &usart0;
20 serial3 = &dbgu;
21 serial4 = &usart3;
22 serial5 = &uart0;
23 serial6 = &uart1;
24 };
25
26 chosen {
27 linux,stdout-path = &usart2;
28 };
29
30 memory {
31 reg = <0x20000000 0x4000000>;
32 };
33
34 clocks {
35 #address-cells = <1>;
36 #size-cells = <1>;
37 ranges;
38
39 main_clock: clock@0 {
40 compatible = "atmel,osc", "fixed-clock";
41 clock-frequency = <18432000>;
42 };
43 };
44
45 ahb {
46 apb {
47 usart0: serial@fffb0000 {
48 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts>;
49 linux,rs485-enabled-at-boot-time;
50 status = "okay";
51 };
52
53 usart1: serial@fffb4000 {
54 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts>;
55 linux,rs485-enabled-at-boot-time;
56 status = "okay";
57 };
58
59 usart2: serial@fffb8000 {
60 pinctrl-0 = <&pinctrl_usart2>;
61 status = "okay";
62 };
63
64 macb0: ethernet@fffc4000 {
65 pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii>;
66 phy-mode = "mii";
67 status = "okay";
68 };
69
70 mmc0: mmc@fffa8000 {
71 pinctrl-0 = <&pinctrl_mmc0_clk
72 &pinctrl_mmc0_slot1_cmd_dat0
73 &pinctrl_mmc0_slot1_dat1_3>;
74 status = "okay";
75
76 slot@1 {
77 reg = <1>;
78 bus-width = <4>;
79 };
80 };
81 };
82
83 nand0: nand@40000000 {
84 nand-bus-width = <8>;
85 nand-ecc-mode = "soft";
86 nand-on-flash-bbt;
87 status = "okay";
88
89 at91bootstrap@0 {
90 label = "at91bootstrap";
91 reg = <0x0 0x8000>;
92 };
93
94 barebox@8000 {
95 label = "barebox";
96 reg = <0x8000 0x40000>;
97 };
98
99 bareboxenv@48000 {
100 label = "bareboxenv";
101 reg = <0x48000 0x8000>;
102 };
103
104 user_block@0x50000 {
105 label = "user_block";
106 reg = <0x50000 0xb0000>;
107 };
108
109 kernel@100000 {
110 label = "kernel";
111 reg = <0x100000 0x1b0000>;
112 };
113
114 root@2b0000 {
115 label = "root";
116 reg = <0x2b0000 0x1D50000>;
117 };
118 };
119
120 usb0: ohci@00500000 {
121 num-ports = <2>;
122 atmel,vbus-gpio = <&pioB 15 1>;
123 status = "okay";
124 };
125 };
126
127 leds {
128 compatible = "gpio-leds";
129
130 power_green {
131 label = "power_green";
132 gpios = <&pioC 17 0>;
133 linux,default-trigger = "heartbeat";
134 };
135
136 power_red {
137 label = "power_red";
138 gpios = <&pioA 2 0>;
139 };
140
141 tx_green {
142 label = "tx_green";
143 gpios = <&pioC 19 0>;
144 };
145
146 tx_red {
147 label = "tx_red";
148 gpios = <&pioC 18 0>;
149 };
150 };
151
152 gpio_keys {
153 compatible = "gpio-keys";
154 #address-cells = <1>;
155 #size-cells = <0>;
156
157 keyswitch_in {
158 label = "keyswitch_in";
159 gpios = <&pioB 1 0>;
160 linux,code = <28>;
161 gpio-key,wakeup;
162 };
163
164 error_in {
165 label = "error_in";
166 gpios = <&pioB 2 0>;
167 linux,code = <29>;
168 gpio-key,wakeup;
169 };
170
171 btn {
172 label = "btn";
173 gpios = <&pioC 23 0>;
174 linux,code = <31>;
175 gpio-key,wakeup;
176 };
177 };
178};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
new file mode 100644
index 000000000000..e154f242c680
--- /dev/null
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -0,0 +1,349 @@
1/*
2 * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 * 2012 Joachim Eastwood <manabian@gmail.com>
7 *
8 * Based on at91sam9260.dtsi
9 *
10 * Licensed under GPLv2 or later.
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 model = "Atmel AT91RM9200 family SoC";
17 compatible = "atmel,at91rm9200";
18 interrupt-parent = <&aic>;
19
20 aliases {
21 serial0 = &dbgu;
22 serial1 = &usart0;
23 serial2 = &usart1;
24 serial3 = &usart2;
25 serial4 = &usart3;
26 gpio0 = &pioA;
27 gpio1 = &pioB;
28 gpio2 = &pioC;
29 gpio3 = &pioD;
30 tcb0 = &tcb0;
31 tcb1 = &tcb1;
32 };
33 cpus {
34 cpu@0 {
35 compatible = "arm,arm920t";
36 };
37 };
38
39 memory {
40 reg = <0x20000000 0x04000000>;
41 };
42
43 ahb {
44 compatible = "simple-bus";
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 apb {
50 compatible = "simple-bus";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 ranges;
54
55 aic: interrupt-controller@fffff000 {
56 #interrupt-cells = <3>;
57 compatible = "atmel,at91rm9200-aic";
58 interrupt-controller;
59 reg = <0xfffff000 0x200>;
60 atmel,external-irqs = <25 26 27 28 29 30 31>;
61 };
62
63 ramc0: ramc@ffffff00 {
64 compatible = "atmel,at91rm9200-sdramc";
65 reg = <0xffffff00 0x100>;
66 };
67
68 pmc: pmc@fffffc00 {
69 compatible = "atmel,at91rm9200-pmc";
70 reg = <0xfffffc00 0x100>;
71 };
72
73 st: timer@fffffd00 {
74 compatible = "atmel,at91rm9200-st";
75 reg = <0xfffffd00 0x100>;
76 interrupts = <1 4 7>;
77 };
78
79 tcb0: timer@fffa0000 {
80 compatible = "atmel,at91rm9200-tcb";
81 reg = <0xfffa0000 0x100>;
82 interrupts = <17 4 0 18 4 0 19 4 0>;
83 };
84
85 tcb1: timer@fffa4000 {
86 compatible = "atmel,at91rm9200-tcb";
87 reg = <0xfffa4000 0x100>;
88 interrupts = <20 4 0 21 4 0 22 4 0>;
89 };
90
91 pinctrl@fffff400 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
95 ranges = <0xfffff400 0xfffff400 0x800>;
96
97 atmel,mux-mask = <
98 /* A B */
99 0xffffffff 0xffffffff /* pioA */
100 0xffffffff 0x083fffff /* pioB */
101 0xffff3fff 0x00000000 /* pioC */
102 0x03ff87ff 0x0fffff80 /* pioD */
103 >;
104
105 /* shared pinctrl settings */
106 dbgu {
107 pinctrl_dbgu: dbgu-0 {
108 atmel,pins =
109 <0 30 0x1 0x0 /* PA30 periph A */
110 0 31 0x1 0x1>; /* PA31 periph with pullup */
111 };
112 };
113
114 uart0 {
115 pinctrl_uart0: uart0-0 {
116 atmel,pins =
117 <0 17 0x1 0x0 /* PA17 periph A */
118 0 18 0x1 0x0>; /* PA18 periph A */
119 };
120
121 pinctrl_uart0_rts: uart0_rts-0 {
122 atmel,pins =
123 <0 20 0x1 0x0>; /* PA20 periph A */
124 };
125
126 pinctrl_uart0_cts: uart0_cts-0 {
127 atmel,pins =
128 <0 21 0x1 0x0>; /* PA21 periph A */
129 };
130 };
131
132 uart1 {
133 pinctrl_uart1: uart1-0 {
134 atmel,pins =
135 <1 20 0x1 0x1 /* PB20 periph A with pullup */
136 1 21 0x1 0x0>; /* PB21 periph A */
137 };
138
139 pinctrl_uart1_rts: uart1_rts-0 {
140 atmel,pins =
141 <1 24 0x1 0x0>; /* PB24 periph A */
142 };
143
144 pinctrl_uart1_cts: uart1_cts-0 {
145 atmel,pins =
146 <1 26 0x1 0x0>; /* PB26 periph A */
147 };
148
149 pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
150 atmel,pins =
151 <1 19 0x1 0x0 /* PB19 periph A */
152 1 25 0x1 0x0>; /* PB25 periph A */
153 };
154
155 pinctrl_uart1_dcd: uart1_dcd-0 {
156 atmel,pins =
157 <1 23 0x1 0x0>; /* PB23 periph A */
158 };
159
160 pinctrl_uart1_ri: uart1_ri-0 {
161 atmel,pins =
162 <1 18 0x1 0x0>; /* PB18 periph A */
163 };
164 };
165
166 uart2 {
167 pinctrl_uart2: uart2-0 {
168 atmel,pins =
169 <0 22 0x1 0x0 /* PA22 periph A */
170 0 23 0x1 0x1>; /* PA23 periph A with pullup */
171 };
172
173 pinctrl_uart2_rts: uart2_rts-0 {
174 atmel,pins =
175 <0 30 0x2 0x0>; /* PA30 periph B */
176 };
177
178 pinctrl_uart2_cts: uart2_cts-0 {
179 atmel,pins =
180 <0 31 0x2 0x0>; /* PA31 periph B */
181 };
182 };
183
184 uart3 {
185 pinctrl_uart3: uart3-0 {
186 atmel,pins =
187 <0 5 0x2 0x1 /* PA5 periph B with pullup */
188 0 6 0x2 0x0>; /* PA6 periph B */
189 };
190
191 pinctrl_uart3_rts: uart3_rts-0 {
192 atmel,pins =
193 <1 0 0x2 0x0>; /* PB0 periph B */
194 };
195
196 pinctrl_uart3_cts: uart3_cts-0 {
197 atmel,pins =
198 <1 1 0x2 0x0>; /* PB1 periph B */
199 };
200 };
201
202 nand {
203 pinctrl_nand: nand-0 {
204 atmel,pins =
205 <2 2 0x0 0x1 /* PC2 gpio RDY pin pull_up */
206 1 1 0x0 0x1>; /* PB1 gpio CD pin pull_up */
207 };
208 };
209
210 pioA: gpio@fffff400 {
211 compatible = "atmel,at91rm9200-gpio";
212 reg = <0xfffff400 0x200>;
213 interrupts = <2 4 1>;
214 #gpio-cells = <2>;
215 gpio-controller;
216 interrupt-controller;
217 #interrupt-cells = <2>;
218 };
219
220 pioB: gpio@fffff600 {
221 compatible = "atmel,at91rm9200-gpio";
222 reg = <0xfffff600 0x200>;
223 interrupts = <3 4 1>;
224 #gpio-cells = <2>;
225 gpio-controller;
226 interrupt-controller;
227 #interrupt-cells = <2>;
228 };
229
230 pioC: gpio@fffff800 {
231 compatible = "atmel,at91rm9200-gpio";
232 reg = <0xfffff800 0x200>;
233 interrupts = <4 4 1>;
234 #gpio-cells = <2>;
235 gpio-controller;
236 interrupt-controller;
237 #interrupt-cells = <2>;
238 };
239
240 pioD: gpio@fffffa00 {
241 compatible = "atmel,at91rm9200-gpio";
242 reg = <0xfffffa00 0x200>;
243 interrupts = <5 4 1>;
244 #gpio-cells = <2>;
245 gpio-controller;
246 interrupt-controller;
247 #interrupt-cells = <2>;
248 };
249 };
250
251 dbgu: serial@fffff200 {
252 compatible = "atmel,at91rm9200-usart";
253 reg = <0xfffff200 0x200>;
254 interrupts = <1 4 7>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_dbgu>;
257 status = "disabled";
258 };
259
260 usart0: serial@fffc0000 {
261 compatible = "atmel,at91rm9200-usart";
262 reg = <0xfffc0000 0x200>;
263 interrupts = <6 4 5>;
264 atmel,use-dma-rx;
265 atmel,use-dma-tx;
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_uart0>;
268 status = "disabled";
269 };
270
271 usart1: serial@fffc4000 {
272 compatible = "atmel,at91rm9200-usart";
273 reg = <0xfffc4000 0x200>;
274 interrupts = <7 4 5>;
275 atmel,use-dma-rx;
276 atmel,use-dma-tx;
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_uart1>;
279 status = "disabled";
280 };
281
282 usart2: serial@fffc8000 {
283 compatible = "atmel,at91rm9200-usart";
284 reg = <0xfffc8000 0x200>;
285 interrupts = <8 4 5>;
286 atmel,use-dma-rx;
287 atmel,use-dma-tx;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_uart2>;
290 status = "disabled";
291 };
292
293 usart3: serial@fffcc000 {
294 compatible = "atmel,at91rm9200-usart";
295 reg = <0xfffcc000 0x200>;
296 interrupts = <23 4 5>;
297 atmel,use-dma-rx;
298 atmel,use-dma-tx;
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_uart3>;
301 status = "disabled";
302 };
303
304 usb1: gadget@fffb0000 {
305 compatible = "atmel,at91rm9200-udc";
306 reg = <0xfffb0000 0x4000>;
307 interrupts = <11 4 2>;
308 status = "disabled";
309 };
310 };
311
312 nand0: nand@40000000 {
313 compatible = "atmel,at91rm9200-nand";
314 #address-cells = <1>;
315 #size-cells = <1>;
316 reg = <0x40000000 0x10000000>;
317 atmel,nand-addr-offset = <21>;
318 atmel,nand-cmd-offset = <22>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_nand>;
321 nand-ecc-mode = "soft";
322 gpios = <&pioC 2 0
323 0
324 &pioB 1 0
325 >;
326 status = "disabled";
327 };
328
329 usb0: ohci@00300000 {
330 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
331 reg = <0x00300000 0x100000>;
332 interrupts = <23 4 2>;
333 status = "disabled";
334 };
335 };
336
337 i2c@0 {
338 compatible = "i2c-gpio";
339 gpios = <&pioA 23 0 /* sda */
340 &pioA 24 0 /* scl */
341 >;
342 i2c-gpio,sda-open-drain;
343 i2c-gpio,scl-open-drain;
344 i2c-gpio,delay-us = <2>; /* ~100 kHz */
345 #address-cells = <1>;
346 #size-cells = <0>;
347 status = "disabled";
348 };
349};
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
new file mode 100644
index 000000000000..8aa48931e0a2
--- /dev/null
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -0,0 +1,79 @@
1/*
2 * at91rm9200ek.dts - Device Tree file for Atmel AT91RM9200 evaluation kit
3 *
4 * Copyright (C) 2012 Joachim Eastwood <manabian@gmail.com>
5 *
6 * Licensed under GPLv2 only
7 */
8/dts-v1/;
9/include/ "at91rm9200.dtsi"
10
11/ {
12 model = "Atmel AT91RM9200 evaluation kit";
13 compatible = "atmel,at91rm9200ek", "atmel,at91rm9200";
14
15 memory {
16 reg = <0x20000000 0x4000000>;
17 };
18
19 clocks {
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
23
24 main_clock: clock@0 {
25 compatible = "atmel,osc", "fixed-clock";
26 clock-frequency = <18432000>;
27 };
28 };
29
30 ahb {
31 apb {
32 dbgu: serial@fffff200 {
33 status = "okay";
34 };
35
36 usart1: serial@fffc4000 {
37 pinctrl-0 =
38 <&pinctrl_uart1
39 &pinctrl_uart1_rts
40 &pinctrl_uart1_cts
41 &pinctrl_uart1_dtr_dsr
42 &pinctrl_uart1_dcd
43 &pinctrl_uart1_ri>;
44 status = "okay";
45 };
46
47 usb1: gadget@fffb0000 {
48 atmel,vbus-gpio = <&pioD 4 0>;
49 status = "okay";
50 };
51 };
52
53 usb0: ohci@00300000 {
54 num-ports = <2>;
55 status = "okay";
56 };
57 };
58
59 leds {
60 compatible = "gpio-leds";
61
62 ds2 {
63 label = "green";
64 gpios = <&pioB 0 0x1>;
65 linux,default-trigger = "mmc0";
66 };
67
68 ds4 {
69 label = "yellow";
70 gpios = <&pioB 1 0x1>;
71 linux,default-trigger = "heartbeat";
72 };
73
74 ds6 {
75 label = "red";
76 gpios = <&pioB 2 0x1>;
77 };
78 };
79};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index d410581a5a85..b1d3fab60e0a 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -21,8 +21,8 @@
21 serial2 = &usart1; 21 serial2 = &usart1;
22 serial3 = &usart2; 22 serial3 = &usart2;
23 serial4 = &usart3; 23 serial4 = &usart3;
24 serial5 = &usart4; 24 serial5 = &uart0;
25 serial6 = &usart5; 25 serial6 = &uart1;
26 gpio0 = &pioA; 26 gpio0 = &pioA;
27 gpio1 = &pioB; 27 gpio1 = &pioB;
28 gpio2 = &pioC; 28 gpio2 = &pioC;
@@ -98,40 +98,250 @@
98 interrupts = <26 4 0 27 4 0 28 4 0>; 98 interrupts = <26 4 0 27 4 0 28 4 0>;
99 }; 99 };
100 100
101 pioA: gpio@fffff400 { 101 pinctrl@fffff400 {
102 compatible = "atmel,at91rm9200-gpio"; 102 #address-cells = <1>;
103 reg = <0xfffff400 0x100>; 103 #size-cells = <1>;
104 interrupts = <2 4 1>; 104 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
105 #gpio-cells = <2>; 105 ranges = <0xfffff400 0xfffff400 0x600>;
106 gpio-controller; 106
107 interrupt-controller; 107 atmel,mux-mask = <
108 #interrupt-cells = <2>; 108 /* A B */
109 }; 109 0xffffffff 0xffc00c3b /* pioA */
110 0xffffffff 0x7fff3ccf /* pioB */
111 0xffffffff 0x007fffff /* pioC */
112 >;
113
114 /* shared pinctrl settings */
115 dbgu {
116 pinctrl_dbgu: dbgu-0 {
117 atmel,pins =
118 <1 14 0x1 0x0 /* PB14 periph A */
119 1 15 0x1 0x1>; /* PB15 periph with pullup */
120 };
121 };
110 122
111 pioB: gpio@fffff600 { 123 usart0 {
112 compatible = "atmel,at91rm9200-gpio"; 124 pinctrl_usart0: usart0-0 {
113 reg = <0xfffff600 0x100>; 125 atmel,pins =
114 interrupts = <3 4 1>; 126 <1 4 0x1 0x0 /* PB4 periph A */
115 #gpio-cells = <2>; 127 1 5 0x1 0x0>; /* PB5 periph A */
116 gpio-controller; 128 };
117 interrupt-controller; 129
118 #interrupt-cells = <2>; 130 pinctrl_usart0_rts: usart0_rts-0 {
119 }; 131 atmel,pins =
132 <1 26 0x1 0x0>; /* PB26 periph A */
133 };
134
135 pinctrl_usart0_cts: usart0_cts-0 {
136 atmel,pins =
137 <1 27 0x1 0x0>; /* PB27 periph A */
138 };
139
140 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
141 atmel,pins =
142 <1 24 0x1 0x0 /* PB24 periph A */
143 1 22 0x1 0x0>; /* PB22 periph A */
144 };
145
146 pinctrl_usart0_dcd: usart0_dcd-0 {
147 atmel,pins =
148 <1 23 0x1 0x0>; /* PB23 periph A */
149 };
150
151 pinctrl_usart0_ri: usart0_ri-0 {
152 atmel,pins =
153 <1 25 0x1 0x0>; /* PB25 periph A */
154 };
155 };
120 156
121 pioC: gpio@fffff800 { 157 usart1 {
122 compatible = "atmel,at91rm9200-gpio"; 158 pinctrl_usart1: usart1-0 {
123 reg = <0xfffff800 0x100>; 159 atmel,pins =
124 interrupts = <4 4 1>; 160 <2 6 0x1 0x1 /* PB6 periph A with pullup */
125 #gpio-cells = <2>; 161 2 7 0x1 0x0>; /* PB7 periph A */
126 gpio-controller; 162 };
127 interrupt-controller; 163
128 #interrupt-cells = <2>; 164 pinctrl_usart1_rts: usart1_rts-0 {
165 atmel,pins =
166 <1 28 0x1 0x0>; /* PB28 periph A */
167 };
168
169 pinctrl_usart1_cts: usart1_cts-0 {
170 atmel,pins =
171 <1 29 0x1 0x0>; /* PB29 periph A */
172 };
173 };
174
175 usart2 {
176 pinctrl_usart2: usart2-0 {
177 atmel,pins =
178 <1 8 0x1 0x1 /* PB8 periph A with pullup */
179 1 9 0x1 0x0>; /* PB9 periph A */
180 };
181
182 pinctrl_usart2_rts: usart2_rts-0 {
183 atmel,pins =
184 <0 4 0x1 0x0>; /* PA4 periph A */
185 };
186
187 pinctrl_usart2_cts: usart2_cts-0 {
188 atmel,pins =
189 <0 5 0x1 0x0>; /* PA5 periph A */
190 };
191 };
192
193 usart3 {
194 pinctrl_usart3: usart3-0 {
195 atmel,pins =
196 <2 10 0x1 0x1 /* PB10 periph A with pullup */
197 2 11 0x1 0x0>; /* PB11 periph A */
198 };
199
200 pinctrl_usart3_rts: usart3_rts-0 {
201 atmel,pins =
202 <3 8 0x2 0x0>; /* PB8 periph B */
203 };
204
205 pinctrl_usart3_cts: usart3_cts-0 {
206 atmel,pins =
207 <3 10 0x2 0x0>; /* PB10 periph B */
208 };
209 };
210
211 uart0 {
212 pinctrl_uart0: uart0-0 {
213 atmel,pins =
214 <0 31 0x2 0x1 /* PA31 periph B with pullup */
215 0 30 0x2 0x0>; /* PA30 periph B */
216 };
217 };
218
219 uart1 {
220 pinctrl_uart1: uart1-0 {
221 atmel,pins =
222 <2 12 0x1 0x1 /* PB12 periph A with pullup */
223 2 13 0x1 0x0>; /* PB13 periph A */
224 };
225 };
226
227 nand {
228 pinctrl_nand: nand-0 {
229 atmel,pins =
230 <2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */
231 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
232 };
233 };
234
235 macb {
236 pinctrl_macb_rmii: macb_rmii-0 {
237 atmel,pins =
238 <0 12 0x1 0x0 /* PA12 periph A */
239 0 13 0x1 0x0 /* PA13 periph A */
240 0 14 0x1 0x0 /* PA14 periph A */
241 0 15 0x1 0x0 /* PA15 periph A */
242 0 16 0x1 0x0 /* PA16 periph A */
243 0 17 0x1 0x0 /* PA17 periph A */
244 0 18 0x1 0x0 /* PA18 periph A */
245 0 19 0x1 0x0 /* PA19 periph A */
246 0 20 0x1 0x0 /* PA20 periph A */
247 0 21 0x1 0x0>; /* PA21 periph A */
248 };
249
250 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
251 atmel,pins =
252 <0 22 0x2 0x0 /* PA22 periph B */
253 0 23 0x2 0x0 /* PA23 periph B */
254 0 24 0x2 0x0 /* PA24 periph B */
255 0 25 0x2 0x0 /* PA25 periph B */
256 0 26 0x2 0x0 /* PA26 periph B */
257 0 27 0x2 0x0 /* PA27 periph B */
258 0 28 0x2 0x0 /* PA28 periph B */
259 0 29 0x2 0x0>; /* PA29 periph B */
260 };
261
262 pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
263 atmel,pins =
264 <0 10 0x2 0x0 /* PA10 periph B */
265 0 11 0x2 0x0 /* PA11 periph B */
266 0 24 0x2 0x0 /* PA24 periph B */
267 0 25 0x2 0x0 /* PA25 periph B */
268 0 26 0x2 0x0 /* PA26 periph B */
269 0 27 0x2 0x0 /* PA27 periph B */
270 0 28 0x2 0x0 /* PA28 periph B */
271 0 29 0x2 0x0>; /* PA29 periph B */
272 };
273 };
274
275 mmc0 {
276 pinctrl_mmc0_clk: mmc0_clk-0 {
277 atmel,pins =
278 <0 8 0x1 0x0>; /* PA8 periph A */
279 };
280
281 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
282 atmel,pins =
283 <0 7 0x1 0x1 /* PA7 periph A with pullup */
284 0 6 0x1 0x1>; /* PA6 periph A with pullup */
285 };
286
287 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
288 atmel,pins =
289 <0 9 0x1 0x1 /* PA9 periph A with pullup */
290 0 10 0x1 0x1 /* PA10 periph A with pullup */
291 0 11 0x1 0x1>; /* PA11 periph A with pullup */
292 };
293
294 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
295 atmel,pins =
296 <0 1 0x2 0x1 /* PA1 periph B with pullup */
297 0 0 0x2 0x1>; /* PA0 periph B with pullup */
298 };
299
300 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
301 atmel,pins =
302 <0 5 0x2 0x1 /* PA5 periph B with pullup */
303 0 4 0x2 0x1 /* PA4 periph B with pullup */
304 0 3 0x2 0x1>; /* PA3 periph B with pullup */
305 };
306 };
307
308 pioA: gpio@fffff400 {
309 compatible = "atmel,at91rm9200-gpio";
310 reg = <0xfffff400 0x200>;
311 interrupts = <2 4 1>;
312 #gpio-cells = <2>;
313 gpio-controller;
314 interrupt-controller;
315 #interrupt-cells = <2>;
316 };
317
318 pioB: gpio@fffff600 {
319 compatible = "atmel,at91rm9200-gpio";
320 reg = <0xfffff600 0x200>;
321 interrupts = <3 4 1>;
322 #gpio-cells = <2>;
323 gpio-controller;
324 interrupt-controller;
325 #interrupt-cells = <2>;
326 };
327
328 pioC: gpio@fffff800 {
329 compatible = "atmel,at91rm9200-gpio";
330 reg = <0xfffff800 0x200>;
331 interrupts = <4 4 1>;
332 #gpio-cells = <2>;
333 gpio-controller;
334 interrupt-controller;
335 #interrupt-cells = <2>;
336 };
129 }; 337 };
130 338
131 dbgu: serial@fffff200 { 339 dbgu: serial@fffff200 {
132 compatible = "atmel,at91sam9260-usart"; 340 compatible = "atmel,at91sam9260-usart";
133 reg = <0xfffff200 0x200>; 341 reg = <0xfffff200 0x200>;
134 interrupts = <1 4 7>; 342 interrupts = <1 4 7>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_dbgu>;
135 status = "disabled"; 345 status = "disabled";
136 }; 346 };
137 347
@@ -141,6 +351,8 @@
141 interrupts = <6 4 5>; 351 interrupts = <6 4 5>;
142 atmel,use-dma-rx; 352 atmel,use-dma-rx;
143 atmel,use-dma-tx; 353 atmel,use-dma-tx;
354 pinctrl-names = "default";
355 pinctrl-0 = <&pinctrl_usart0>;
144 status = "disabled"; 356 status = "disabled";
145 }; 357 };
146 358
@@ -150,6 +362,8 @@
150 interrupts = <7 4 5>; 362 interrupts = <7 4 5>;
151 atmel,use-dma-rx; 363 atmel,use-dma-rx;
152 atmel,use-dma-tx; 364 atmel,use-dma-tx;
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_usart1>;
153 status = "disabled"; 367 status = "disabled";
154 }; 368 };
155 369
@@ -159,6 +373,8 @@
159 interrupts = <8 4 5>; 373 interrupts = <8 4 5>;
160 atmel,use-dma-rx; 374 atmel,use-dma-rx;
161 atmel,use-dma-tx; 375 atmel,use-dma-tx;
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_usart2>;
162 status = "disabled"; 378 status = "disabled";
163 }; 379 };
164 380
@@ -168,24 +384,30 @@
168 interrupts = <23 4 5>; 384 interrupts = <23 4 5>;
169 atmel,use-dma-rx; 385 atmel,use-dma-rx;
170 atmel,use-dma-tx; 386 atmel,use-dma-tx;
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_usart3>;
171 status = "disabled"; 389 status = "disabled";
172 }; 390 };
173 391
174 usart4: serial@fffd4000 { 392 uart0: serial@fffd4000 {
175 compatible = "atmel,at91sam9260-usart"; 393 compatible = "atmel,at91sam9260-usart";
176 reg = <0xfffd4000 0x200>; 394 reg = <0xfffd4000 0x200>;
177 interrupts = <24 4 5>; 395 interrupts = <24 4 5>;
178 atmel,use-dma-rx; 396 atmel,use-dma-rx;
179 atmel,use-dma-tx; 397 atmel,use-dma-tx;
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_uart0>;
180 status = "disabled"; 400 status = "disabled";
181 }; 401 };
182 402
183 usart5: serial@fffd8000 { 403 uart1: serial@fffd8000 {
184 compatible = "atmel,at91sam9260-usart"; 404 compatible = "atmel,at91sam9260-usart";
185 reg = <0xfffd8000 0x200>; 405 reg = <0xfffd8000 0x200>;
186 interrupts = <25 4 5>; 406 interrupts = <25 4 5>;
187 atmel,use-dma-rx; 407 atmel,use-dma-rx;
188 atmel,use-dma-tx; 408 atmel,use-dma-tx;
409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_uart1>;
189 status = "disabled"; 411 status = "disabled";
190 }; 412 };
191 413
@@ -193,6 +415,8 @@
193 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 415 compatible = "cdns,at32ap7000-macb", "cdns,macb";
194 reg = <0xfffc4000 0x100>; 416 reg = <0xfffc4000 0x100>;
195 interrupts = <21 4 3>; 417 interrupts = <21 4 3>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_macb_rmii>;
196 status = "disabled"; 420 status = "disabled";
197 }; 421 };
198 422
@@ -212,6 +436,15 @@
212 status = "disabled"; 436 status = "disabled";
213 }; 437 };
214 438
439 mmc0: mmc@fffa8000 {
440 compatible = "atmel,hsmci";
441 reg = <0xfffa8000 0x600>;
442 interrupts = <9 4 0>;
443 #address-cells = <1>;
444 #size-cells = <0>;
445 status = "disabled";
446 };
447
215 adc0: adc@fffe0000 { 448 adc0: adc@fffe0000 {
216 compatible = "atmel,at91sam9260-adc"; 449 compatible = "atmel,at91sam9260-adc";
217 reg = <0xfffe0000 0x100>; 450 reg = <0xfffe0000 0x100>;
@@ -257,6 +490,8 @@
257 >; 490 >;
258 atmel,nand-addr-offset = <21>; 491 atmel,nand-addr-offset = <21>;
259 atmel,nand-cmd-offset = <22>; 492 atmel,nand-cmd-offset = <22>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&pinctrl_nand>;
260 gpios = <&pioC 13 0 495 gpios = <&pioC 13 0
261 &pioC 14 0 496 &pioC 14 0
262 0 497 0
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 3e6e5c1abbf3..66106eecf1ed 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -89,60 +89,243 @@
89 reg = <0xfffffd10 0x10>; 89 reg = <0xfffffd10 0x10>;
90 }; 90 };
91 91
92 pioA: gpio@fffff200 { 92 pinctrl@fffff200 {
93 compatible = "atmel,at91rm9200-gpio"; 93 #address-cells = <1>;
94 reg = <0xfffff200 0x100>; 94 #size-cells = <1>;
95 interrupts = <2 4 1>; 95 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
96 #gpio-cells = <2>; 96 ranges = <0xfffff200 0xfffff200 0xa00>;
97 gpio-controller;
98 interrupt-controller;
99 #interrupt-cells = <2>;
100 };
101 97
102 pioB: gpio@fffff400 { 98 atmel,mux-mask = <
103 compatible = "atmel,at91rm9200-gpio"; 99 /* A B */
104 reg = <0xfffff400 0x100>; 100 0xfffffffb 0xffffe07f /* pioA */
105 interrupts = <3 4 1>; 101 0x0007ffff 0x39072fff /* pioB */
106 #gpio-cells = <2>; 102 0xffffffff 0x3ffffff8 /* pioC */
107 gpio-controller; 103 0xfffffbff 0xffffffff /* pioD */
108 interrupt-controller; 104 0xffe00fff 0xfbfcff00 /* pioE */
109 #interrupt-cells = <2>; 105 >;
110 };
111 106
112 pioC: gpio@fffff600 { 107 /* shared pinctrl settings */
113 compatible = "atmel,at91rm9200-gpio"; 108 dbgu {
114 reg = <0xfffff600 0x100>; 109 pinctrl_dbgu: dbgu-0 {
115 interrupts = <4 4 1>; 110 atmel,pins =
116 #gpio-cells = <2>; 111 <2 30 0x1 0x0 /* PC30 periph A */
117 gpio-controller; 112 2 31 0x1 0x1>; /* PC31 periph with pullup */
118 interrupt-controller; 113 };
119 #interrupt-cells = <2>; 114 };
120 };
121 115
122 pioD: gpio@fffff800 { 116 usart0 {
123 compatible = "atmel,at91rm9200-gpio"; 117 pinctrl_usart0: usart0-0 {
124 reg = <0xfffff800 0x100>; 118 atmel,pins =
125 interrupts = <4 4 1>; 119 <0 26 0x1 0x1 /* PA26 periph A with pullup */
126 #gpio-cells = <2>; 120 0 27 0x1 0x0>; /* PA27 periph A */
127 gpio-controller; 121 };
128 interrupt-controller;
129 #interrupt-cells = <2>;
130 };
131 122
132 pioE: gpio@fffffa00 { 123 pinctrl_usart0_rts: usart0_rts-0 {
133 compatible = "atmel,at91rm9200-gpio"; 124 atmel,pins =
134 reg = <0xfffffa00 0x100>; 125 <0 28 0x1 0x0>; /* PA28 periph A */
135 interrupts = <4 4 1>; 126 };
136 #gpio-cells = <2>; 127
137 gpio-controller; 128 pinctrl_usart0_cts: usart0_cts-0 {
138 interrupt-controller; 129 atmel,pins =
139 #interrupt-cells = <2>; 130 <0 29 0x1 0x0>; /* PA29 periph A */
131 };
132 };
133
134 usart1 {
135 pinctrl_usart1: usart1-0 {
136 atmel,pins =
137 <3 0 0x1 0x1 /* PD0 periph A with pullup */
138 3 1 0x1 0x0>; /* PD1 periph A */
139 };
140
141 pinctrl_usart1_rts: usart1_rts-0 {
142 atmel,pins =
143 <3 7 0x2 0x0>; /* PD7 periph B */
144 };
145
146 pinctrl_usart1_cts: usart1_cts-0 {
147 atmel,pins =
148 <3 8 0x2 0x0>; /* PD8 periph B */
149 };
150 };
151
152 usart2 {
153 pinctrl_usart2: usart2-0 {
154 atmel,pins =
155 <3 2 0x1 0x1 /* PD2 periph A with pullup */
156 3 3 0x1 0x0>; /* PD3 periph A */
157 };
158
159 pinctrl_usart2_rts: usart2_rts-0 {
160 atmel,pins =
161 <3 5 0x2 0x0>; /* PD5 periph B */
162 };
163
164 pinctrl_usart2_cts: usart2_cts-0 {
165 atmel,pins =
166 <4 6 0x2 0x0>; /* PD6 periph B */
167 };
168 };
169
170 nand {
171 pinctrl_nand: nand-0 {
172 atmel,pins =
173 <0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/
174 3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
175 };
176 };
177
178 macb {
179 pinctrl_macb_rmii: macb_rmii-0 {
180 atmel,pins =
181 <2 25 0x2 0x0 /* PC25 periph B */
182 4 21 0x1 0x0 /* PE21 periph A */
183 4 23 0x1 0x0 /* PE23 periph A */
184 4 24 0x1 0x0 /* PE24 periph A */
185 4 25 0x1 0x0 /* PE25 periph A */
186 4 26 0x1 0x0 /* PE26 periph A */
187 4 27 0x1 0x0 /* PE27 periph A */
188 4 28 0x1 0x0 /* PE28 periph A */
189 4 29 0x1 0x0 /* PE29 periph A */
190 4 30 0x1 0x0>; /* PE30 periph A */
191 };
192
193 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
194 atmel,pins =
195 <2 20 0x2 0x0 /* PC20 periph B */
196 2 21 0x2 0x0 /* PC21 periph B */
197 2 22 0x2 0x0 /* PC22 periph B */
198 2 23 0x2 0x0 /* PC23 periph B */
199 2 24 0x2 0x0 /* PC24 periph B */
200 2 25 0x2 0x0 /* PC25 periph B */
201 2 27 0x2 0x0 /* PC27 periph B */
202 4 22 0x2 0x0>; /* PE22 periph B */
203 };
204 };
205
206 mmc0 {
207 pinctrl_mmc0_clk: mmc0_clk-0 {
208 atmel,pins =
209 <0 12 0x1 0x0>; /* PA12 periph A */
210 };
211
212 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
213 atmel,pins =
214 <0 1 0x1 0x1 /* PA1 periph A with pullup */
215 0 0 0x1 0x1>; /* PA0 periph A with pullup */
216 };
217
218 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
219 atmel,pins =
220 <0 3 0x1 0x1 /* PA3 periph A with pullup */
221 0 4 0x1 0x1 /* PA4 periph A with pullup */
222 0 5 0x1 0x1>; /* PA5 periph A with pullup */
223 };
224
225 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
226 atmel,pins =
227 <0 16 0x1 0x1 /* PA16 periph A with pullup */
228 0 17 0x1 0x1>; /* PA17 periph A with pullup */
229 };
230
231 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
232 atmel,pins =
233 <0 18 0x1 0x1 /* PA18 periph A with pullup */
234 0 19 0x1 0x1 /* PA19 periph A with pullup */
235 0 20 0x1 0x1>; /* PA20 periph A with pullup */
236 };
237 };
238
239 mmc1 {
240 pinctrl_mmc1_clk: mmc1_clk-0 {
241 atmel,pins =
242 <0 6 0x1 0x0>; /* PA6 periph A */
243 };
244
245 pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
246 atmel,pins =
247 <0 7 0x1 0x1 /* PA7 periph A with pullup */
248 0 8 0x1 0x1>; /* PA8 periph A with pullup */
249 };
250
251 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
252 atmel,pins =
253 <0 9 0x1 0x1 /* PA9 periph A with pullup */
254 0 10 0x1 0x1 /* PA10 periph A with pullup */
255 0 11 0x1 0x1>; /* PA11 periph A with pullup */
256 };
257
258 pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
259 atmel,pins =
260 <0 21 0x1 0x1 /* PA21 periph A with pullup */
261 0 22 0x1 0x1>; /* PA22 periph A with pullup */
262 };
263
264 pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
265 atmel,pins =
266 <0 23 0x1 0x1 /* PA23 periph A with pullup */
267 0 24 0x1 0x1 /* PA24 periph A with pullup */
268 0 25 0x1 0x1>; /* PA25 periph A with pullup */
269 };
270 };
271
272 pioA: gpio@fffff200 {
273 compatible = "atmel,at91rm9200-gpio";
274 reg = <0xfffff200 0x200>;
275 interrupts = <2 4 1>;
276 #gpio-cells = <2>;
277 gpio-controller;
278 interrupt-controller;
279 #interrupt-cells = <2>;
280 };
281
282 pioB: gpio@fffff400 {
283 compatible = "atmel,at91rm9200-gpio";
284 reg = <0xfffff400 0x200>;
285 interrupts = <3 4 1>;
286 #gpio-cells = <2>;
287 gpio-controller;
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 };
291
292 pioC: gpio@fffff600 {
293 compatible = "atmel,at91rm9200-gpio";
294 reg = <0xfffff600 0x200>;
295 interrupts = <4 4 1>;
296 #gpio-cells = <2>;
297 gpio-controller;
298 interrupt-controller;
299 #interrupt-cells = <2>;
300 };
301
302 pioD: gpio@fffff800 {
303 compatible = "atmel,at91rm9200-gpio";
304 reg = <0xfffff800 0x200>;
305 interrupts = <4 4 1>;
306 #gpio-cells = <2>;
307 gpio-controller;
308 interrupt-controller;
309 #interrupt-cells = <2>;
310 };
311
312 pioE: gpio@fffffa00 {
313 compatible = "atmel,at91rm9200-gpio";
314 reg = <0xfffffa00 0x200>;
315 interrupts = <4 4 1>;
316 #gpio-cells = <2>;
317 gpio-controller;
318 interrupt-controller;
319 #interrupt-cells = <2>;
320 };
140 }; 321 };
141 322
142 dbgu: serial@ffffee00 { 323 dbgu: serial@ffffee00 {
143 compatible = "atmel,at91sam9260-usart"; 324 compatible = "atmel,at91sam9260-usart";
144 reg = <0xffffee00 0x200>; 325 reg = <0xffffee00 0x200>;
145 interrupts = <1 4 7>; 326 interrupts = <1 4 7>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_dbgu>;
146 status = "disabled"; 329 status = "disabled";
147 }; 330 };
148 331
@@ -152,6 +335,8 @@
152 interrupts = <7 4 5>; 335 interrupts = <7 4 5>;
153 atmel,use-dma-rx; 336 atmel,use-dma-rx;
154 atmel,use-dma-tx; 337 atmel,use-dma-tx;
338 pinctrl-names = "default";
339 pinctrl-0 = <&pinctrl_usart0>;
155 status = "disabled"; 340 status = "disabled";
156 }; 341 };
157 342
@@ -161,6 +346,8 @@
161 interrupts = <8 4 5>; 346 interrupts = <8 4 5>;
162 atmel,use-dma-rx; 347 atmel,use-dma-rx;
163 atmel,use-dma-tx; 348 atmel,use-dma-tx;
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_usart1>;
164 status = "disabled"; 351 status = "disabled";
165 }; 352 };
166 353
@@ -170,6 +357,8 @@
170 interrupts = <9 4 5>; 357 interrupts = <9 4 5>;
171 atmel,use-dma-rx; 358 atmel,use-dma-rx;
172 atmel,use-dma-tx; 359 atmel,use-dma-tx;
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_usart2>;
173 status = "disabled"; 362 status = "disabled";
174 }; 363 };
175 364
@@ -177,6 +366,8 @@
177 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 366 compatible = "cdns,at32ap7000-macb", "cdns,macb";
178 reg = <0xfffbc000 0x100>; 367 reg = <0xfffbc000 0x100>;
179 interrupts = <21 4 3>; 368 interrupts = <21 4 3>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_macb_rmii>;
180 status = "disabled"; 371 status = "disabled";
181 }; 372 };
182 373
@@ -195,6 +386,24 @@
195 #size-cells = <0>; 386 #size-cells = <0>;
196 status = "disabled"; 387 status = "disabled";
197 }; 388 };
389
390 mmc0: mmc@fff80000 {
391 compatible = "atmel,hsmci";
392 reg = <0xfff80000 0x600>;
393 interrupts = <10 4 0>;
394 #address-cells = <1>;
395 #size-cells = <0>;
396 status = "disabled";
397 };
398
399 mmc1: mmc@fff84000 {
400 compatible = "atmel,hsmci";
401 reg = <0xfff84000 0x600>;
402 interrupts = <11 4 0>;
403 #address-cells = <1>;
404 #size-cells = <0>;
405 status = "disabled";
406 };
198 }; 407 };
199 408
200 nand0: nand@40000000 { 409 nand0: nand@40000000 {
@@ -206,6 +415,8 @@
206 >; 415 >;
207 atmel,nand-addr-offset = <21>; 416 atmel,nand-addr-offset = <21>;
208 atmel,nand-cmd-offset = <22>; 417 atmel,nand-cmd-offset = <22>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_nand>;
209 gpios = <&pioA 22 0 420 gpios = <&pioA 22 0
210 &pioD 15 0 421 &pioD 15 0
211 0 422 0
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index f86ac4b609fc..1eb08728f527 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -38,6 +38,10 @@
38 }; 38 };
39 39
40 usart0: serial@fff8c000 { 40 usart0: serial@fff8c000 {
41 pinctrl-0 = <
42 &pinctrl_usart0
43 &pinctrl_usart0_rts
44 &pinctrl_usart0_cts>;
41 status = "okay"; 45 status = "okay";
42 }; 46 };
43 47
@@ -50,6 +54,31 @@
50 atmel,vbus-gpio = <&pioA 25 0>; 54 atmel,vbus-gpio = <&pioA 25 0>;
51 status = "okay"; 55 status = "okay";
52 }; 56 };
57
58 mmc0: mmc@fff80000 {
59 pinctrl-0 = <
60 &pinctrl_board_mmc0
61 &pinctrl_mmc0_clk
62 &pinctrl_mmc0_slot0_cmd_dat0
63 &pinctrl_mmc0_slot0_dat1_3>;
64 status = "okay";
65 slot@0 {
66 reg = <0>;
67 bus-width = <4>;
68 cd-gpios = <&pioE 18 0>;
69 wp-gpios = <&pioE 19 0>;
70 };
71 };
72
73 pinctrl@fffff200 {
74 mmc0 {
75 pinctrl_board_mmc0: mmc0-board {
76 atmel,pins =
77 <5 18 0x0 0x5 /* PE18 gpio CD pin pull up and deglitch */
78 5 19 0x0 0x1>; /* PE19 gpio WP pin pull up */
79 };
80 };
81 };
53 }; 82 };
54 83
55 nand0: nand@40000000 { 84 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
new file mode 100644
index 000000000000..fbe7a7089c2a
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9G15 SoC";
13 compatible = "atmel, at91sam9g15, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe0399f 0x00000000 /* pioA */
21 0x00040000 0x00047e3f 0x00000000 /* pioB */
22 0xfdffffff 0x00000000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts
new file mode 100644
index 000000000000..86dd3f6d938f
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g15ek.dts
@@ -0,0 +1,16 @@
1/*
2 * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9g15.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
index f1b2e148ac8c..66467b113126 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
+++ b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
@@ -12,6 +12,32 @@
12 model = "Atmel at91sam9g20ek 2 mmc"; 12 model = "Atmel at91sam9g20ek 2 mmc";
13 compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9"; 13 compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9";
14 14
15 ahb {
16 apb{
17 mmc0: mmc@fffa8000 {
18 /* clk already mux wuth slot0 */
19 pinctrl-0 = <
20 &pinctrl_board_mmc0_slot0
21 &pinctrl_mmc0_slot0_cmd_dat0
22 &pinctrl_mmc0_slot0_dat1_3>;
23 slot@0 {
24 reg = <0>;
25 bus-width = <4>;
26 cd-gpios = <&pioC 2 0>;
27 };
28 };
29
30 pinctrl@fffff400 {
31 mmc0_slot0 {
32 pinctrl_board_mmc0_slot0: mmc0_slot0-board {
33 atmel,pins =
34 <2 2 0x0 0x5>; /* PC2 gpio CD pin pull up and deglitch */
35 };
36 };
37 };
38 };
39 };
40
15 leds { 41 leds {
16 compatible = "gpio-leds"; 42 compatible = "gpio-leds";
17 43
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index e6391a4e6649..32a500a0e481 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -35,6 +35,13 @@
35 }; 35 };
36 36
37 usart0: serial@fffb0000 { 37 usart0: serial@fffb0000 {
38 pinctrl-0 =
39 <&pinctrl_usart0
40 &pinctrl_usart0_rts
41 &pinctrl_usart0_cts
42 &pinctrl_usart0_dtr_dsr
43 &pinctrl_usart0_dcd
44 &pinctrl_usart0_ri>;
38 status = "okay"; 45 status = "okay";
39 }; 46 };
40 47
@@ -51,6 +58,29 @@
51 atmel,vbus-gpio = <&pioC 5 0>; 58 atmel,vbus-gpio = <&pioC 5 0>;
52 status = "okay"; 59 status = "okay";
53 }; 60 };
61
62 mmc0: mmc@fffa8000 {
63 pinctrl-0 = <
64 &pinctrl_board_mmc0_slot1
65 &pinctrl_mmc0_clk
66 &pinctrl_mmc0_slot1_cmd_dat0
67 &pinctrl_mmc0_slot1_dat1_3>;
68 status = "okay";
69 slot@1 {
70 reg = <1>;
71 bus-width = <4>;
72 cd-gpios = <&pioC 9 0>;
73 };
74 };
75
76 pinctrl@fffff400 {
77 mmc0_slot1 {
78 pinctrl_board_mmc0_slot1: mmc0_slot1-board {
79 atmel,pins =
80 <2 9 0x0 0x5>; /* PC9 gpio CD pin pull up and deglitch */
81 };
82 };
83 };
54 }; 84 };
55 85
56 nand0: nand@40000000 { 86 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
new file mode 100644
index 000000000000..05a718fb83c4
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9G25 SoC";
13 compatible = "atmel, at91sam9g25, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe0399f 0xc000001c /* pioA */
21 0x0007ffff 0x8000fe3f 0x00000000 /* pioB */
22 0x80000000 0x07c0ffff 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 877c08f06763..c5ab16fba059 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -7,55 +7,10 @@
7 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
8 */ 8 */
9/dts-v1/; 9/dts-v1/;
10/include/ "at91sam9x5.dtsi" 10/include/ "at91sam9g25.dtsi"
11/include/ "at91sam9x5cm.dtsi" 11/include/ "at91sam9x5ek.dtsi"
12 12
13/ { 13/ {
14 model = "Atmel AT91SAM9G25-EK"; 14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; 15 compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16
17 chosen {
18 bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
19 };
20
21 ahb {
22 apb {
23 dbgu: serial@fffff200 {
24 status = "okay";
25 };
26
27 usart0: serial@f801c000 {
28 status = "okay";
29 };
30
31 macb0: ethernet@f802c000 {
32 phy-mode = "rmii";
33 status = "okay";
34 };
35
36 i2c0: i2c@f8010000 {
37 status = "okay";
38 };
39
40 i2c1: i2c@f8014000 {
41 status = "okay";
42 };
43
44 i2c2: i2c@f8018000 {
45 status = "okay";
46 };
47 };
48
49 usb0: ohci@00600000 {
50 status = "okay";
51 num-ports = <2>;
52 atmel,vbus-gpio = <&pioD 19 1
53 &pioD 20 1
54 >;
55 };
56
57 usb1: ehci@00700000 {
58 status = "okay";
59 };
60 };
61}; 16};
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
new file mode 100644
index 000000000000..f9d14a722794
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9G35 SoC";
13 compatible = "atmel, at91sam9g35, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe0399f 0xc000000c /* pioA */
21 0x000406ff 0x00047e3f 0x00000000 /* pioB */
22 0xfdffffff 0x00000000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts
new file mode 100644
index 000000000000..95944bdd798d
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g35ek.dts
@@ -0,0 +1,16 @@
1/*
2 * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9g35.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G35-EK";
15 compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 3add030d61f8..0741caeeced1 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -108,60 +108,243 @@
108 interrupts = <21 4 0>; 108 interrupts = <21 4 0>;
109 }; 109 };
110 110
111 pioA: gpio@fffff200 { 111 pinctrl@fffff200 {
112 compatible = "atmel,at91rm9200-gpio"; 112 #address-cells = <1>;
113 reg = <0xfffff200 0x100>; 113 #size-cells = <1>;
114 interrupts = <2 4 1>; 114 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
115 #gpio-cells = <2>; 115 ranges = <0xfffff200 0xfffff200 0xa00>;
116 gpio-controller; 116
117 interrupt-controller; 117 atmel,mux-mask = <
118 #interrupt-cells = <2>; 118 /* A B */
119 }; 119 0xffffffff 0xffc003ff /* pioA */
120 0xffffffff 0x800f8f00 /* pioB */
121 0xffffffff 0x00000e00 /* pioC */
122 0xffffffff 0xff0c1381 /* pioD */
123 0xffffffff 0x81ffff81 /* pioE */
124 >;
125
126 /* shared pinctrl settings */
127 dbgu {
128 pinctrl_dbgu: dbgu-0 {
129 atmel,pins =
130 <1 12 0x1 0x0 /* PB12 periph A */
131 1 13 0x1 0x0>; /* PB13 periph A */
132 };
133 };
120 134
121 pioB: gpio@fffff400 { 135 usart0 {
122 compatible = "atmel,at91rm9200-gpio"; 136 pinctrl_usart0: usart0-0 {
123 reg = <0xfffff400 0x100>; 137 atmel,pins =
124 interrupts = <3 4 1>; 138 <1 19 0x1 0x1 /* PB19 periph A with pullup */
125 #gpio-cells = <2>; 139 1 18 0x1 0x0>; /* PB18 periph A */
126 gpio-controller; 140 };
127 interrupt-controller; 141
128 #interrupt-cells = <2>; 142 pinctrl_usart0_rts: usart0_rts-0 {
129 }; 143 atmel,pins =
144 <1 17 0x2 0x0>; /* PB17 periph B */
145 };
146
147 pinctrl_usart0_cts: usart0_cts-0 {
148 atmel,pins =
149 <1 15 0x2 0x0>; /* PB15 periph B */
150 };
151 };
130 152
131 pioC: gpio@fffff600 { 153 uart1 {
132 compatible = "atmel,at91rm9200-gpio"; 154 pinctrl_usart1: usart1-0 {
133 reg = <0xfffff600 0x100>; 155 atmel,pins =
134 interrupts = <4 4 1>; 156 <1 4 0x1 0x1 /* PB4 periph A with pullup */
135 #gpio-cells = <2>; 157 1 5 0x1 0x0>; /* PB5 periph A */
136 gpio-controller; 158 };
137 interrupt-controller; 159
138 #interrupt-cells = <2>; 160 pinctrl_usart1_rts: usart1_rts-0 {
139 }; 161 atmel,pins =
162 <3 16 0x1 0x0>; /* PD16 periph A */
163 };
164
165 pinctrl_usart1_cts: usart1_cts-0 {
166 atmel,pins =
167 <3 17 0x1 0x0>; /* PD17 periph A */
168 };
169 };
140 170
141 pioD: gpio@fffff800 { 171 usart2 {
142 compatible = "atmel,at91rm9200-gpio"; 172 pinctrl_usart2: usart2-0 {
143 reg = <0xfffff800 0x100>; 173 atmel,pins =
144 interrupts = <5 4 1>; 174 <1 6 0x1 0x1 /* PB6 periph A with pullup */
145 #gpio-cells = <2>; 175 1 7 0x1 0x0>; /* PB7 periph A */
146 gpio-controller; 176 };
147 interrupt-controller; 177
148 #interrupt-cells = <2>; 178 pinctrl_usart2_rts: usart2_rts-0 {
149 }; 179 atmel,pins =
180 <2 9 0x2 0x0>; /* PC9 periph B */
181 };
182
183 pinctrl_usart2_cts: usart2_cts-0 {
184 atmel,pins =
185 <2 11 0x2 0x0>; /* PC11 periph B */
186 };
187 };
150 188
151 pioE: gpio@fffffa00 { 189 usart3 {
152 compatible = "atmel,at91rm9200-gpio"; 190 pinctrl_usart3: usart3-0 {
153 reg = <0xfffffa00 0x100>; 191 atmel,pins =
154 interrupts = <5 4 1>; 192 <1 8 0x1 0x1 /* PB9 periph A with pullup */
155 #gpio-cells = <2>; 193 1 9 0x1 0x0>; /* PB8 periph A */
156 gpio-controller; 194 };
157 interrupt-controller; 195
158 #interrupt-cells = <2>; 196 pinctrl_usart3_rts: usart3_rts-0 {
197 atmel,pins =
198 <0 23 0x2 0x0>; /* PA23 periph B */
199 };
200
201 pinctrl_usart3_cts: usart3_cts-0 {
202 atmel,pins =
203 <0 24 0x2 0x0>; /* PA24 periph B */
204 };
205 };
206
207 nand {
208 pinctrl_nand: nand-0 {
209 atmel,pins =
210 <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
211 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
212 };
213 };
214
215 macb {
216 pinctrl_macb_rmii: macb_rmii-0 {
217 atmel,pins =
218 <0 10 0x1 0x0 /* PA10 periph A */
219 0 11 0x1 0x0 /* PA11 periph A */
220 0 12 0x1 0x0 /* PA12 periph A */
221 0 13 0x1 0x0 /* PA13 periph A */
222 0 14 0x1 0x0 /* PA14 periph A */
223 0 15 0x1 0x0 /* PA15 periph A */
224 0 16 0x1 0x0 /* PA16 periph A */
225 0 17 0x1 0x0 /* PA17 periph A */
226 0 18 0x1 0x0 /* PA18 periph A */
227 0 19 0x1 0x0>; /* PA19 periph A */
228 };
229
230 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
231 atmel,pins =
232 <0 6 0x2 0x0 /* PA6 periph B */
233 0 7 0x2 0x0 /* PA7 periph B */
234 0 8 0x2 0x0 /* PA8 periph B */
235 0 9 0x2 0x0 /* PA9 periph B */
236 0 27 0x2 0x0 /* PA27 periph B */
237 0 28 0x2 0x0 /* PA28 periph B */
238 0 29 0x2 0x0 /* PA29 periph B */
239 0 30 0x2 0x0>; /* PA30 periph B */
240 };
241 };
242
243 mmc0 {
244 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
245 atmel,pins =
246 <0 0 0x1 0x0 /* PA0 periph A */
247 0 1 0x1 0x1 /* PA1 periph A with pullup */
248 0 2 0x1 0x1>; /* PA2 periph A with pullup */
249 };
250
251 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
252 atmel,pins =
253 <0 3 0x1 0x1 /* PA3 periph A with pullup */
254 0 4 0x1 0x1 /* PA4 periph A with pullup */
255 0 5 0x1 0x1>; /* PA5 periph A with pullup */
256 };
257
258 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
259 atmel,pins =
260 <0 6 0x1 0x1 /* PA6 periph A with pullup */
261 0 7 0x1 0x1 /* PA7 periph A with pullup */
262 0 8 0x1 0x1 /* PA8 periph A with pullup */
263 0 9 0x1 0x1>; /* PA9 periph A with pullup */
264 };
265 };
266
267 mmc1 {
268 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
269 atmel,pins =
270 <0 31 0x1 0x0 /* PA31 periph A */
271 0 22 0x1 0x1 /* PA22 periph A with pullup */
272 0 23 0x1 0x1>; /* PA23 periph A with pullup */
273 };
274
275 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
276 atmel,pins =
277 <0 24 0x1 0x1 /* PA24 periph A with pullup */
278 0 25 0x1 0x1 /* PA25 periph A with pullup */
279 0 26 0x1 0x1>; /* PA26 periph A with pullup */
280 };
281
282 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
283 atmel,pins =
284 <0 27 0x1 0x1 /* PA27 periph A with pullup */
285 0 28 0x1 0x1 /* PA28 periph A with pullup */
286 0 29 0x1 0x1 /* PA29 periph A with pullup */
287 0 20 0x1 0x1>; /* PA30 periph A with pullup */
288 };
289 };
290
291 pioA: gpio@fffff200 {
292 compatible = "atmel,at91rm9200-gpio";
293 reg = <0xfffff200 0x200>;
294 interrupts = <2 4 1>;
295 #gpio-cells = <2>;
296 gpio-controller;
297 interrupt-controller;
298 #interrupt-cells = <2>;
299 };
300
301 pioB: gpio@fffff400 {
302 compatible = "atmel,at91rm9200-gpio";
303 reg = <0xfffff400 0x200>;
304 interrupts = <3 4 1>;
305 #gpio-cells = <2>;
306 gpio-controller;
307 interrupt-controller;
308 #interrupt-cells = <2>;
309 };
310
311 pioC: gpio@fffff600 {
312 compatible = "atmel,at91rm9200-gpio";
313 reg = <0xfffff600 0x200>;
314 interrupts = <4 4 1>;
315 #gpio-cells = <2>;
316 gpio-controller;
317 interrupt-controller;
318 #interrupt-cells = <2>;
319 };
320
321 pioD: gpio@fffff800 {
322 compatible = "atmel,at91rm9200-gpio";
323 reg = <0xfffff800 0x200>;
324 interrupts = <5 4 1>;
325 #gpio-cells = <2>;
326 gpio-controller;
327 interrupt-controller;
328 #interrupt-cells = <2>;
329 };
330
331 pioE: gpio@fffffa00 {
332 compatible = "atmel,at91rm9200-gpio";
333 reg = <0xfffffa00 0x200>;
334 interrupts = <5 4 1>;
335 #gpio-cells = <2>;
336 gpio-controller;
337 interrupt-controller;
338 #interrupt-cells = <2>;
339 };
159 }; 340 };
160 341
161 dbgu: serial@ffffee00 { 342 dbgu: serial@ffffee00 {
162 compatible = "atmel,at91sam9260-usart"; 343 compatible = "atmel,at91sam9260-usart";
163 reg = <0xffffee00 0x200>; 344 reg = <0xffffee00 0x200>;
164 interrupts = <1 4 7>; 345 interrupts = <1 4 7>;
346 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_dbgu>;
165 status = "disabled"; 348 status = "disabled";
166 }; 349 };
167 350
@@ -171,6 +354,8 @@
171 interrupts = <7 4 5>; 354 interrupts = <7 4 5>;
172 atmel,use-dma-rx; 355 atmel,use-dma-rx;
173 atmel,use-dma-tx; 356 atmel,use-dma-tx;
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_usart0>;
174 status = "disabled"; 359 status = "disabled";
175 }; 360 };
176 361
@@ -180,6 +365,8 @@
180 interrupts = <8 4 5>; 365 interrupts = <8 4 5>;
181 atmel,use-dma-rx; 366 atmel,use-dma-rx;
182 atmel,use-dma-tx; 367 atmel,use-dma-tx;
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_usart1>;
183 status = "disabled"; 370 status = "disabled";
184 }; 371 };
185 372
@@ -189,6 +376,8 @@
189 interrupts = <9 4 5>; 376 interrupts = <9 4 5>;
190 atmel,use-dma-rx; 377 atmel,use-dma-rx;
191 atmel,use-dma-tx; 378 atmel,use-dma-tx;
379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_usart2>;
192 status = "disabled"; 381 status = "disabled";
193 }; 382 };
194 383
@@ -198,6 +387,8 @@
198 interrupts = <10 4 5>; 387 interrupts = <10 4 5>;
199 atmel,use-dma-rx; 388 atmel,use-dma-rx;
200 atmel,use-dma-tx; 389 atmel,use-dma-tx;
390 pinctrl-names = "default";
391 pinctrl-0 = <&pinctrl_usart3>;
201 status = "disabled"; 392 status = "disabled";
202 }; 393 };
203 394
@@ -205,6 +396,8 @@
205 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 396 compatible = "cdns,at32ap7000-macb", "cdns,macb";
206 reg = <0xfffbc000 0x100>; 397 reg = <0xfffbc000 0x100>;
207 interrupts = <25 4 3>; 398 interrupts = <25 4 3>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_macb_rmii>;
208 status = "disabled"; 401 status = "disabled";
209 }; 402 };
210 403
@@ -262,6 +455,24 @@
262 trigger-value = <0x6>; 455 trigger-value = <0x6>;
263 }; 456 };
264 }; 457 };
458
459 mmc0: mmc@fff80000 {
460 compatible = "atmel,hsmci";
461 reg = <0xfff80000 0x600>;
462 interrupts = <11 4 0>;
463 #address-cells = <1>;
464 #size-cells = <0>;
465 status = "disabled";
466 };
467
468 mmc1: mmc@fffd0000 {
469 compatible = "atmel,hsmci";
470 reg = <0xfffd0000 0x600>;
471 interrupts = <29 4 0>;
472 #address-cells = <1>;
473 #size-cells = <0>;
474 status = "disabled";
475 };
265 }; 476 };
266 477
267 nand0: nand@40000000 { 478 nand0: nand@40000000 {
@@ -273,6 +484,8 @@
273 >; 484 >;
274 atmel,nand-addr-offset = <21>; 485 atmel,nand-addr-offset = <21>;
275 atmel,nand-cmd-offset = <22>; 486 atmel,nand-cmd-offset = <22>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_nand>;
276 gpios = <&pioC 8 0 489 gpios = <&pioC 8 0
277 &pioC 14 0 490 &pioC 14 0
278 0 491 0
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 15e1dd43f625..20c31913c270 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -39,6 +39,10 @@
39 }; 39 };
40 40
41 usart1: serial@fff90000 { 41 usart1: serial@fff90000 {
42 pinctrl-0 =
43 <&pinctrl_usart1
44 &pinctrl_usart1_rts
45 &pinctrl_usart1_cts>;
42 status = "okay"; 46 status = "okay";
43 }; 47 };
44 48
@@ -54,6 +58,50 @@
54 i2c1: i2c@fff88000 { 58 i2c1: i2c@fff88000 {
55 status = "okay"; 59 status = "okay";
56 }; 60 };
61
62 mmc0: mmc@fff80000 {
63 pinctrl-0 = <
64 &pinctrl_board_mmc0
65 &pinctrl_mmc0_slot0_clk_cmd_dat0
66 &pinctrl_mmc0_slot0_dat1_3>;
67 status = "okay";
68 slot@0 {
69 reg = <0>;
70 bus-width = <4>;
71 cd-gpios = <&pioD 10 0>;
72 };
73 };
74
75 mmc1: mmc@fffd0000 {
76 pinctrl-0 = <
77 &pinctrl_board_mmc1
78 &pinctrl_mmc1_slot0_clk_cmd_dat0
79 &pinctrl_mmc1_slot0_dat1_3>;
80 status = "okay";
81 slot@0 {
82 reg = <0>;
83 bus-width = <4>;
84 cd-gpios = <&pioD 11 0>;
85 wp-gpios = <&pioD 29 0>;
86 };
87 };
88
89 pinctrl@fffff200 {
90 mmc0 {
91 pinctrl_board_mmc0: mmc0-board {
92 atmel,pins =
93 <3 10 0x0 0x5>; /* PD10 gpio CD pin pull up and deglitch */
94 };
95 };
96
97 mmc1 {
98 pinctrl_board_mmc1: mmc1-board {
99 atmel,pins =
100 <3 11 0x0 0x5 /* PD11 gpio CD pin pull up and deglitch */
101 3 29 0x0 0x1>; /* PD29 gpio WP pin pull up */
102 };
103 };
104 };
57 }; 105 };
58 106
59 nand0: nand@40000000 { 107 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 82508d68aa7e..e9efb34f4379 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -84,6 +84,15 @@
84 reg = <0xfffffe10 0x10>; 84 reg = <0xfffffe10 0x10>;
85 }; 85 };
86 86
87 mmc0: mmc@f0008000 {
88 compatible = "atmel,hsmci";
89 reg = <0xf0008000 0x600>;
90 interrupts = <12 4 0>;
91 #address-cells = <1>;
92 #size-cells = <0>;
93 status = "disabled";
94 };
95
87 tcb0: timer@f8008000 { 96 tcb0: timer@f8008000 {
88 compatible = "atmel,at91sam9x5-tcb"; 97 compatible = "atmel,at91sam9x5-tcb";
89 reg = <0xf8008000 0x100>; 98 reg = <0xf8008000 0x100>;
@@ -102,50 +111,186 @@
102 interrupts = <20 4 0>; 111 interrupts = <20 4 0>;
103 }; 112 };
104 113
105 pioA: gpio@fffff400 { 114 pinctrl@fffff400 {
106 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 115 #address-cells = <1>;
107 reg = <0xfffff400 0x100>; 116 #size-cells = <1>;
108 interrupts = <2 4 1>; 117 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
109 #gpio-cells = <2>; 118 ranges = <0xfffff400 0xfffff400 0x800>;
110 gpio-controller;
111 interrupt-controller;
112 #interrupt-cells = <2>;
113 };
114 119
115 pioB: gpio@fffff600 { 120 atmel,mux-mask = <
116 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 121 /* A B C */
117 reg = <0xfffff600 0x100>; 122 0xffffffff 0xffe07983 0x00000000 /* pioA */
118 interrupts = <2 4 1>; 123 0x00040000 0x00047e0f 0x00000000 /* pioB */
119 #gpio-cells = <2>; 124 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
120 gpio-controller; 125 0x003fffff 0x003f8000 0x00000000 /* pioD */
121 interrupt-controller; 126 >;
122 #interrupt-cells = <2>;
123 };
124 127
125 pioC: gpio@fffff800 { 128 /* shared pinctrl settings */
126 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 129 dbgu {
127 reg = <0xfffff800 0x100>; 130 pinctrl_dbgu: dbgu-0 {
128 interrupts = <3 4 1>; 131 atmel,pins =
129 #gpio-cells = <2>; 132 <0 9 0x1 0x0 /* PA9 periph A */
130 gpio-controller; 133 0 10 0x1 0x1>; /* PA10 periph with pullup */
131 interrupt-controller; 134 };
132 #interrupt-cells = <2>; 135 };
133 };
134 136
135 pioD: gpio@fffffa00 { 137 usart0 {
136 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 138 pinctrl_usart0: usart0-0 {
137 reg = <0xfffffa00 0x100>; 139 atmel,pins =
138 interrupts = <3 4 1>; 140 <0 1 0x1 0x1 /* PA1 periph A with pullup */
139 #gpio-cells = <2>; 141 0 0 0x1 0x0>; /* PA0 periph A */
140 gpio-controller; 142 };
141 interrupt-controller; 143
142 #interrupt-cells = <2>; 144 pinctrl_usart0_rts: usart0_rts-0 {
145 atmel,pins =
146 <0 2 0x1 0x0>; /* PA2 periph A */
147 };
148
149 pinctrl_usart0_cts: usart0_cts-0 {
150 atmel,pins =
151 <0 3 0x1 0x0>; /* PA3 periph A */
152 };
153 };
154
155 usart1 {
156 pinctrl_usart1: usart1-0 {
157 atmel,pins =
158 <0 6 0x1 0x1 /* PA6 periph A with pullup */
159 0 5 0x1 0x0>; /* PA5 periph A */
160 };
161 };
162
163 usart2 {
164 pinctrl_usart2: usart2-0 {
165 atmel,pins =
166 <0 8 0x1 0x1 /* PA8 periph A with pullup */
167 0 7 0x1 0x0>; /* PA7 periph A */
168 };
169
170 pinctrl_usart2_rts: usart2_rts-0 {
171 atmel,pins =
172 <1 0 0x2 0x0>; /* PB0 periph B */
173 };
174
175 pinctrl_usart2_cts: usart2_cts-0 {
176 atmel,pins =
177 <1 1 0x2 0x0>; /* PB1 periph B */
178 };
179 };
180
181 usart3 {
182 pinctrl_usart3: usart3-0 {
183 atmel,pins =
184 <2 23 0x2 0x1 /* PC23 periph B with pullup */
185 2 22 0x2 0x0>; /* PC22 periph B */
186 };
187
188 pinctrl_usart3_rts: usart3_rts-0 {
189 atmel,pins =
190 <2 24 0x2 0x0>; /* PC24 periph B */
191 };
192
193 pinctrl_usart3_cts: usart3_cts-0 {
194 atmel,pins =
195 <2 25 0x2 0x0>; /* PC25 periph B */
196 };
197 };
198
199 uart0 {
200 pinctrl_uart0: uart0-0 {
201 atmel,pins =
202 <2 9 0x3 0x1 /* PC9 periph C with pullup */
203 2 8 0x3 0x0>; /* PC8 periph C */
204 };
205 };
206
207 uart1 {
208 pinctrl_uart1: uart1-0 {
209 atmel,pins =
210 <2 16 0x3 0x1 /* PC17 periph C with pullup */
211 2 17 0x3 0x0>; /* PC16 periph C */
212 };
213 };
214
215 nand {
216 pinctrl_nand: nand-0 {
217 atmel,pins =
218 <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
219 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
220 };
221 };
222
223 mmc0 {
224 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
225 atmel,pins =
226 <0 17 0x1 0x0 /* PA17 periph A */
227 0 16 0x1 0x1 /* PA16 periph A with pullup */
228 0 15 0x1 0x1>; /* PA15 periph A with pullup */
229 };
230
231 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
232 atmel,pins =
233 <0 18 0x1 0x1 /* PA18 periph A with pullup */
234 0 19 0x1 0x1 /* PA19 periph A with pullup */
235 0 20 0x1 0x1>; /* PA20 periph A with pullup */
236 };
237
238 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
239 atmel,pins =
240 <0 11 0x2 0x1 /* PA11 periph B with pullup */
241 0 12 0x2 0x1 /* PA12 periph B with pullup */
242 0 13 0x2 0x1 /* PA13 periph B with pullup */
243 0 14 0x2 0x1>; /* PA14 periph B with pullup */
244 };
245 };
246
247 pioA: gpio@fffff400 {
248 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
249 reg = <0xfffff400 0x200>;
250 interrupts = <2 4 1>;
251 #gpio-cells = <2>;
252 gpio-controller;
253 interrupt-controller;
254 #interrupt-cells = <2>;
255 };
256
257 pioB: gpio@fffff600 {
258 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
259 reg = <0xfffff600 0x200>;
260 interrupts = <2 4 1>;
261 #gpio-cells = <2>;
262 gpio-controller;
263 interrupt-controller;
264 #interrupt-cells = <2>;
265 };
266
267 pioC: gpio@fffff800 {
268 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
269 reg = <0xfffff800 0x200>;
270 interrupts = <3 4 1>;
271 #gpio-cells = <2>;
272 gpio-controller;
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 };
276
277 pioD: gpio@fffffa00 {
278 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
279 reg = <0xfffffa00 0x200>;
280 interrupts = <3 4 1>;
281 #gpio-cells = <2>;
282 gpio-controller;
283 interrupt-controller;
284 #interrupt-cells = <2>;
285 };
143 }; 286 };
144 287
145 dbgu: serial@fffff200 { 288 dbgu: serial@fffff200 {
146 compatible = "atmel,at91sam9260-usart"; 289 compatible = "atmel,at91sam9260-usart";
147 reg = <0xfffff200 0x200>; 290 reg = <0xfffff200 0x200>;
148 interrupts = <1 4 7>; 291 interrupts = <1 4 7>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_dbgu>;
149 status = "disabled"; 294 status = "disabled";
150 }; 295 };
151 296
@@ -155,6 +300,8 @@
155 interrupts = <5 4 5>; 300 interrupts = <5 4 5>;
156 atmel,use-dma-rx; 301 atmel,use-dma-rx;
157 atmel,use-dma-tx; 302 atmel,use-dma-tx;
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_usart0>;
158 status = "disabled"; 305 status = "disabled";
159 }; 306 };
160 307
@@ -164,6 +311,8 @@
164 interrupts = <6 4 5>; 311 interrupts = <6 4 5>;
165 atmel,use-dma-rx; 312 atmel,use-dma-rx;
166 atmel,use-dma-tx; 313 atmel,use-dma-tx;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usart1>;
167 status = "disabled"; 316 status = "disabled";
168 }; 317 };
169 318
@@ -173,6 +322,8 @@
173 interrupts = <7 4 5>; 322 interrupts = <7 4 5>;
174 atmel,use-dma-rx; 323 atmel,use-dma-rx;
175 atmel,use-dma-tx; 324 atmel,use-dma-tx;
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_usart2>;
176 status = "disabled"; 327 status = "disabled";
177 }; 328 };
178 329
@@ -182,6 +333,8 @@
182 interrupts = <8 4 5>; 333 interrupts = <8 4 5>;
183 atmel,use-dma-rx; 334 atmel,use-dma-rx;
184 atmel,use-dma-tx; 335 atmel,use-dma-tx;
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_usart3>;
185 status = "disabled"; 338 status = "disabled";
186 }; 339 };
187 340
@@ -215,6 +368,8 @@
215 >; 368 >;
216 atmel,nand-addr-offset = <21>; 369 atmel,nand-addr-offset = <21>;
217 atmel,nand-cmd-offset = <22>; 370 atmel,nand-cmd-offset = <22>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_nand>;
218 gpios = <&pioD 5 0 373 gpios = <&pioD 5 0
219 &pioD 4 0 374 &pioD 4 0
220 0 375 0
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 912b2c283d6f..0376bf4fd66b 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -45,6 +45,28 @@
45 i2c1: i2c@f8014000 { 45 i2c1: i2c@f8014000 {
46 status = "okay"; 46 status = "okay";
47 }; 47 };
48
49 mmc0: mmc@f0008000 {
50 pinctrl-0 = <
51 &pinctrl_board_mmc0
52 &pinctrl_mmc0_slot0_clk_cmd_dat0
53 &pinctrl_mmc0_slot0_dat1_3>;
54 status = "okay";
55 slot@0 {
56 reg = <0>;
57 bus-width = <4>;
58 cd-gpios = <&pioA 7 0>;
59 };
60 };
61
62 pinctrl@fffff400 {
63 mmc0 {
64 pinctrl_board_mmc0: mmc0-board {
65 atmel,pins =
66 <0 7 0x0 0x5>; /* PA7 gpio CD pin pull up and deglitch */
67 };
68 };
69 };
48 }; 70 };
49 71
50 nand0: nand@40000000 { 72 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
new file mode 100644
index 000000000000..54eb33ba6d22
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -0,0 +1,49 @@
1/*
2 * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9X25 SoC";
13 compatible = "atmel, at91sam9x25, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe03fff 0xc000001c /* pioA */
21 0x0007ffff 0x00047e3f 0x00000000 /* pioB */
22 0x80000000 0xfffd0000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25
26 macb1 {
27 pinctrl_macb1_rmii: macb1_rmii-0 {
28 atmel,pins =
29 <2 16 0x2 0x0 /* PC16 periph B */
30 2 18 0x2 0x0 /* PC18 periph B */
31 2 19 0x2 0x0 /* PC19 periph B */
32 2 20 0x2 0x0 /* PC20 periph B */
33 2 21 0x2 0x0 /* PC21 periph B */
34 2 27 0x2 0x0 /* PC27 periph B */
35 2 28 0x2 0x0 /* PC28 periph B */
36 2 29 0x2 0x0 /* PC29 periph B */
37 2 30 0x2 0x0 /* PC30 periph B */
38 2 31 0x2 0x0>; /* PC31 periph B */
39 };
40 };
41 };
42
43 macb1: ethernet@f8030000 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_macb1_rmii>;
46 };
47 };
48 };
49};
diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts
new file mode 100644
index 000000000000..af907eaa1f25
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x25ek.dts
@@ -0,0 +1,16 @@
1/*
2 * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9x25.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
new file mode 100644
index 000000000000..fb102d6126ce
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9X35 SoC";
13 compatible = "atmel, at91sam9x35, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe03fff 0xc000000c /* pioA */
21 0x000406ff 0x00047e3f 0x00000000 /* pioB */
22 0xfdffffff 0x00000000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts
new file mode 100644
index 000000000000..5ccb607b5414
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x35ek.dts
@@ -0,0 +1,16 @@
1/*
2 * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9x35.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9X35-EK";
15 compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 03fc136421c5..7ee49e8daf98 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -111,50 +111,244 @@
111 interrupts = <21 4 0>; 111 interrupts = <21 4 0>;
112 }; 112 };
113 113
114 pioA: gpio@fffff400 { 114 pinctrl@fffff400 {
115 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 115 #address-cells = <1>;
116 reg = <0xfffff400 0x100>; 116 #size-cells = <1>;
117 interrupts = <2 4 1>; 117 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
118 #gpio-cells = <2>; 118 ranges = <0xfffff400 0xfffff400 0x800>;
119 gpio-controller; 119
120 interrupt-controller; 120 /* shared pinctrl settings */
121 #interrupt-cells = <2>; 121 dbgu {
122 }; 122 pinctrl_dbgu: dbgu-0 {
123 atmel,pins =
124 <0 9 0x1 0x0 /* PA9 periph A */
125 0 10 0x1 0x1>; /* PA10 periph A with pullup */
126 };
127 };
123 128
124 pioB: gpio@fffff600 { 129 usart0 {
125 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 130 pinctrl_usart0: usart0-0 {
126 reg = <0xfffff600 0x100>; 131 atmel,pins =
127 interrupts = <2 4 1>; 132 <0 0 0x1 0x1 /* PA0 periph A with pullup */
128 #gpio-cells = <2>; 133 0 1 0x1 0x0>; /* PA1 periph A */
129 gpio-controller; 134 };
130 interrupt-controller; 135
131 #interrupt-cells = <2>; 136 pinctrl_usart0_rts: usart0_rts-0 {
137 atmel,pins =
138 <0 2 0x1 0x0>; /* PA2 periph A */
139 };
140
141 pinctrl_usart0_cts: usart0_cts-0 {
142 atmel,pins =
143 <0 3 0x1 0x0>; /* PA3 periph A */
144 };
145 };
146
147 usart1 {
148 pinctrl_usart1: usart1-0 {
149 atmel,pins =
150 <0 5 0x1 0x1 /* PA5 periph A with pullup */
151 0 6 0x1 0x0>; /* PA6 periph A */
152 };
153
154 pinctrl_usart1_rts: usart1_rts-0 {
155 atmel,pins =
156 <3 27 0x3 0x0>; /* PC27 periph C */
157 };
158
159 pinctrl_usart1_cts: usart1_cts-0 {
160 atmel,pins =
161 <3 28 0x3 0x0>; /* PC28 periph C */
162 };
163 };
164
165 usart2 {
166 pinctrl_usart2: usart2-0 {
167 atmel,pins =
168 <0 7 0x1 0x1 /* PA7 periph A with pullup */
169 0 8 0x1 0x0>; /* PA8 periph A */
170 };
171
172 pinctrl_uart2_rts: uart2_rts-0 {
173 atmel,pins =
174 <0 0 0x2 0x0>; /* PB0 periph B */
175 };
176
177 pinctrl_uart2_cts: uart2_cts-0 {
178 atmel,pins =
179 <0 1 0x2 0x0>; /* PB1 periph B */
180 };
181 };
182
183 usart3 {
184 pinctrl_uart3: usart3-0 {
185 atmel,pins =
186 <3 23 0x2 0x1 /* PC22 periph B with pullup */
187 3 23 0x2 0x0>; /* PC23 periph B */
188 };
189
190 pinctrl_usart3_rts: usart3_rts-0 {
191 atmel,pins =
192 <3 24 0x2 0x0>; /* PC24 periph B */
193 };
194
195 pinctrl_usart3_cts: usart3_cts-0 {
196 atmel,pins =
197 <3 25 0x2 0x0>; /* PC25 periph B */
198 };
199 };
200
201 uart0 {
202 pinctrl_uart0: uart0-0 {
203 atmel,pins =
204 <3 8 0x3 0x0 /* PC8 periph C */
205 3 9 0x3 0x1>; /* PC9 periph C with pullup */
206 };
207 };
208
209 uart1 {
210 pinctrl_uart1: uart1-0 {
211 atmel,pins =
212 <3 16 0x3 0x0 /* PC16 periph C */
213 3 17 0x3 0x1>; /* PC17 periph C with pullup */
214 };
215 };
216
217 nand {
218 pinctrl_nand: nand-0 {
219 atmel,pins =
220 <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
221 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
222 };
223 };
224
225 macb0 {
226 pinctrl_macb0_rmii: macb0_rmii-0 {
227 atmel,pins =
228 <1 0 0x1 0x0 /* PB0 periph A */
229 1 1 0x1 0x0 /* PB1 periph A */
230 1 2 0x1 0x0 /* PB2 periph A */
231 1 3 0x1 0x0 /* PB3 periph A */
232 1 4 0x1 0x0 /* PB4 periph A */
233 1 5 0x1 0x0 /* PB5 periph A */
234 1 6 0x1 0x0 /* PB6 periph A */
235 1 7 0x1 0x0 /* PB7 periph A */
236 1 9 0x1 0x0 /* PB9 periph A */
237 1 10 0x1 0x0>; /* PB10 periph A */
238 };
239
240 pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
241 atmel,pins =
242 <1 8 0x1 0x0 /* PA8 periph A */
243 1 11 0x1 0x0 /* PA11 periph A */
244 1 12 0x1 0x0 /* PA12 periph A */
245 1 13 0x1 0x0 /* PA13 periph A */
246 1 14 0x1 0x0 /* PA14 periph A */
247 1 15 0x1 0x0 /* PA15 periph A */
248 1 16 0x1 0x0 /* PA16 periph A */
249 1 17 0x1 0x0>; /* PA17 periph A */
250 };
251 };
252
253 mmc0 {
254 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
255 atmel,pins =
256 <0 17 0x1 0x0 /* PA17 periph A */
257 0 16 0x1 0x1 /* PA16 periph A with pullup */
258 0 15 0x1 0x1>; /* PA15 periph A with pullup */
259 };
260
261 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
262 atmel,pins =
263 <0 18 0x1 0x1 /* PA18 periph A with pullup */
264 0 19 0x1 0x1 /* PA19 periph A with pullup */
265 0 20 0x1 0x1>; /* PA20 periph A with pullup */
266 };
267 };
268
269 mmc1 {
270 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
271 atmel,pins =
272 <0 13 0x2 0x0 /* PA13 periph B */
273 0 12 0x2 0x1 /* PA12 periph B with pullup */
274 0 11 0x2 0x1>; /* PA11 periph B with pullup */
275 };
276
277 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
278 atmel,pins =
279 <0 2 0x2 0x1 /* PA2 periph B with pullup */
280 0 3 0x2 0x1 /* PA3 periph B with pullup */
281 0 4 0x2 0x1>; /* PA4 periph B with pullup */
282 };
283 };
284
285 pioA: gpio@fffff400 {
286 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
287 reg = <0xfffff400 0x200>;
288 interrupts = <2 4 1>;
289 #gpio-cells = <2>;
290 gpio-controller;
291 interrupt-controller;
292 #interrupt-cells = <2>;
293 };
294
295 pioB: gpio@fffff600 {
296 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
297 reg = <0xfffff600 0x200>;
298 interrupts = <2 4 1>;
299 #gpio-cells = <2>;
300 gpio-controller;
301 #gpio-lines = <19>;
302 interrupt-controller;
303 #interrupt-cells = <2>;
304 };
305
306 pioC: gpio@fffff800 {
307 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
308 reg = <0xfffff800 0x200>;
309 interrupts = <3 4 1>;
310 #gpio-cells = <2>;
311 gpio-controller;
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 };
315
316 pioD: gpio@fffffa00 {
317 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
318 reg = <0xfffffa00 0x200>;
319 interrupts = <3 4 1>;
320 #gpio-cells = <2>;
321 gpio-controller;
322 #gpio-lines = <22>;
323 interrupt-controller;
324 #interrupt-cells = <2>;
325 };
132 }; 326 };
133 327
134 pioC: gpio@fffff800 { 328 mmc0: mmc@f0008000 {
135 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 329 compatible = "atmel,hsmci";
136 reg = <0xfffff800 0x100>; 330 reg = <0xf0008000 0x600>;
137 interrupts = <3 4 1>; 331 interrupts = <12 4 0>;
138 #gpio-cells = <2>; 332 #address-cells = <1>;
139 gpio-controller; 333 #size-cells = <0>;
140 interrupt-controller; 334 status = "disabled";
141 #interrupt-cells = <2>;
142 }; 335 };
143 336
144 pioD: gpio@fffffa00 { 337 mmc1: mmc@f000c000 {
145 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 338 compatible = "atmel,hsmci";
146 reg = <0xfffffa00 0x100>; 339 reg = <0xf000c000 0x600>;
147 interrupts = <3 4 1>; 340 interrupts = <26 4 0>;
148 #gpio-cells = <2>; 341 #address-cells = <1>;
149 gpio-controller; 342 #size-cells = <0>;
150 interrupt-controller; 343 status = "disabled";
151 #interrupt-cells = <2>;
152 }; 344 };
153 345
154 dbgu: serial@fffff200 { 346 dbgu: serial@fffff200 {
155 compatible = "atmel,at91sam9260-usart"; 347 compatible = "atmel,at91sam9260-usart";
156 reg = <0xfffff200 0x200>; 348 reg = <0xfffff200 0x200>;
157 interrupts = <1 4 7>; 349 interrupts = <1 4 7>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_dbgu>;
158 status = "disabled"; 352 status = "disabled";
159 }; 353 };
160 354
@@ -164,6 +358,8 @@
164 interrupts = <5 4 5>; 358 interrupts = <5 4 5>;
165 atmel,use-dma-rx; 359 atmel,use-dma-rx;
166 atmel,use-dma-tx; 360 atmel,use-dma-tx;
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_usart0>;
167 status = "disabled"; 363 status = "disabled";
168 }; 364 };
169 365
@@ -173,6 +369,8 @@
173 interrupts = <6 4 5>; 369 interrupts = <6 4 5>;
174 atmel,use-dma-rx; 370 atmel,use-dma-rx;
175 atmel,use-dma-tx; 371 atmel,use-dma-tx;
372 pinctrl-names = "default";
373 pinctrl-0 = <&pinctrl_usart1>;
176 status = "disabled"; 374 status = "disabled";
177 }; 375 };
178 376
@@ -182,6 +380,8 @@
182 interrupts = <7 4 5>; 380 interrupts = <7 4 5>;
183 atmel,use-dma-rx; 381 atmel,use-dma-rx;
184 atmel,use-dma-tx; 382 atmel,use-dma-tx;
383 pinctrl-names = "default";
384 pinctrl-0 = <&pinctrl_usart2>;
185 status = "disabled"; 385 status = "disabled";
186 }; 386 };
187 387
@@ -189,6 +389,8 @@
189 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 389 compatible = "cdns,at32ap7000-macb", "cdns,macb";
190 reg = <0xf802c000 0x100>; 390 reg = <0xf802c000 0x100>;
191 interrupts = <24 4 3>; 391 interrupts = <24 4 3>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_macb0_rmii>;
192 status = "disabled"; 394 status = "disabled";
193 }; 395 };
194 396
@@ -273,6 +475,8 @@
273 >; 475 >;
274 atmel,nand-addr-offset = <21>; 476 atmel,nand-addr-offset = <21>;
275 atmel,nand-cmd-offset = <22>; 477 atmel,nand-cmd-offset = <22>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_nand>;
276 gpios = <&pioD 5 0 480 gpios = <&pioD 5 0
277 &pioD 4 0 481 &pioD 4 0
278 0 482 0
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
new file mode 100644
index 000000000000..8a7cf1d9cf5d
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -0,0 +1,101 @@
1/*
2 * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/include/ "at91sam9x5cm.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9X5-EK";
13 compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
17 };
18
19 ahb {
20 apb {
21 mmc0: mmc@f0008000 {
22 pinctrl-0 = <
23 &pinctrl_board_mmc0
24 &pinctrl_mmc0_slot0_clk_cmd_dat0
25 &pinctrl_mmc0_slot0_dat1_3>;
26 status = "okay";
27 slot@0 {
28 reg = <0>;
29 bus-width = <4>;
30 cd-gpios = <&pioD 15 0>;
31 };
32 };
33
34 mmc1: mmc@f000c000 {
35 pinctrl-0 = <
36 &pinctrl_board_mmc1
37 &pinctrl_mmc1_slot0_clk_cmd_dat0
38 &pinctrl_mmc1_slot0_dat1_3>;
39 status = "okay";
40 slot@0 {
41 reg = <0>;
42 bus-width = <4>;
43 cd-gpios = <&pioD 14 0>;
44 };
45 };
46
47 dbgu: serial@fffff200 {
48 status = "okay";
49 };
50
51 usart0: serial@f801c000 {
52 status = "okay";
53 };
54
55 macb0: ethernet@f802c000 {
56 phy-mode = "rmii";
57 status = "okay";
58 };
59
60 i2c0: i2c@f8010000 {
61 status = "okay";
62 };
63
64 i2c1: i2c@f8014000 {
65 status = "okay";
66 };
67
68 i2c2: i2c@f8018000 {
69 status = "okay";
70 };
71
72 pinctrl@fffff400 {
73 mmc0 {
74 pinctrl_board_mmc0: mmc0-board {
75 atmel,pins =
76 <3 15 0x0 0x5>; /* PD15 gpio CD pin pull up and deglitch */
77 };
78 };
79
80 mmc1 {
81 pinctrl_board_mmc1: mmc1-board {
82 atmel,pins =
83 <3 14 0x0 0x5>; /* PD14 gpio CD pin pull up and deglitch */
84 };
85 };
86 };
87 };
88
89 usb0: ohci@00600000 {
90 status = "okay";
91 num-ports = <2>;
92 atmel,vbus-gpio = <&pioD 19 1
93 &pioD 20 1
94 >;
95 };
96
97 usb1: ehci@00700000 {
98 status = "okay";
99 };
100 };
101};
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 4b0e0ca08f40..731086b2fca2 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -203,6 +203,14 @@
203 reg = <0x80157450 0xC>; 203 reg = <0x80157450 0xC>;
204 }; 204 };
205 205
206 thermal@801573c0 {
207 compatible = "stericsson,db8500-thermal";
208 reg = <0x801573c0 0x40>;
209 interrupts = <21 0x4>, <22 0x4>;
210 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
211 status = "disabled";
212 };
213
206 db8500-prcmu-regulators { 214 db8500-prcmu-regulators {
207 compatible = "stericsson,db8500-prcmu-regulator"; 215 compatible = "stericsson,db8500-prcmu-regulator";
208 216
@@ -660,5 +668,11 @@
660 ranges = <0 0x50000000 0x4000000>; 668 ranges = <0 0x50000000 0x4000000>;
661 status = "disabled"; 669 status = "disabled";
662 }; 670 };
671
672 cpufreq-cooling {
673 compatible = "stericsson,db8500-cpufreq-cooling";
674 status = "disabled";
675 };
676
663 }; 677 };
664}; 678};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 55c57ea6169e..b4587b27ae42 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -799,6 +799,7 @@
799 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 799 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
800 reg = <0x8006a000 0x2000>; 800 reg = <0x8006a000 0x2000>;
801 interrupts = <112 70 71>; 801 interrupts = <112 70 71>;
802 fsl,auart-dma-channel = <8 9>;
802 clocks = <&clks 45>; 803 clocks = <&clks 45>;
803 status = "disabled"; 804 status = "disabled";
804 }; 805 };
diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts
new file mode 100644
index 000000000000..387fedb58988
--- /dev/null
+++ b/arch/arm/boot/dts/pm9g45.dts
@@ -0,0 +1,165 @@
1/*
2 * pm9g45.dts - Device Tree file for Ronetix pm9g45 board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8/dts-v1/;
9/include/ "at91sam9g45.dtsi"
10
11/ {
12 model = "Ronetix pm9g45";
13 compatible = "ronetix,pm9g45", "atmel,at91sam9g45", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "console=ttyS0,115200";
17 };
18
19 memory {
20 reg = <0x70000000 0x8000000>;
21 };
22
23 clocks {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 main_clock: clock@0 {
29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <12000000>;
31 };
32 };
33
34 ahb {
35 apb {
36 dbgu: serial@ffffee00 {
37 status = "okay";
38 };
39
40 pinctrl@fffff200 {
41
42 board {
43 pinctrl_board_nand: nand0-board {
44 atmel,pins =
45 <3 3 0x0 0x1 /* PD3 gpio RDY pin pull_up*/
46 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
47 };
48 };
49
50 mmc {
51 pinctrl_board_mmc: mmc0-board {
52 atmel,pins =
53 <3 6 0x0 0x5>; /* PD6 gpio CD pin pull_up and deglitch */
54 };
55 };
56 };
57
58 mmc0: mmc@fff80000 {
59 pinctrl-0 = <
60 &pinctrl_board_mmc
61 &pinctrl_mmc0_slot0_clk_cmd_dat0
62 &pinctrl_mmc0_slot0_dat1_3>;
63 status = "okay";
64 slot@0 {
65 reg = <0>;
66 bus-width = <4>;
67 cd-gpios = <&pioD 6 0>;
68 };
69 };
70
71 macb0: ethernet@fffbc000 {
72 phy-mode = "rmii";
73 status = "okay";
74 };
75
76 };
77
78 nand0: nand@40000000 {
79 nand-bus-width = <8>;
80 nand-ecc-mode = "soft";
81 nand-on-flash-bbt;
82 pinctrl-0 = <&pinctrl_board_nand>;
83
84 gpios = <&pioD 3 0
85 &pioC 14 0
86 0
87 >;
88
89 status = "okay";
90
91 at91bootstrap@0 {
92 label = "at91bootstrap";
93 reg = <0x0 0x20000>;
94 };
95
96 barebox@20000 {
97 label = "barebox";
98 reg = <0x20000 0x40000>;
99 };
100
101 bareboxenv@60000 {
102 label = "bareboxenv";
103 reg = <0x60000 0x1A0000>;
104 };
105
106 kernel@200000 {
107 label = "bareboxenv2";
108 reg = <0x200000 0x300000>;
109 };
110
111 kernel@500000 {
112 label = "root";
113 reg = <0x500000 0x400000>;
114 };
115
116 data@900000 {
117 label = "data";
118 reg = <0x900000 0x8340000>;
119 };
120 };
121
122 usb0: ohci@00700000 {
123 status = "okay";
124 num-ports = <2>;
125 };
126
127 usb1: ehci@00800000 {
128 status = "okay";
129 };
130 };
131
132 leds {
133 compatible = "gpio-leds";
134
135 led0 {
136 label = "led0";
137 gpios = <&pioD 0 1>;
138 linux,default-trigger = "nand-disk";
139 };
140
141 led1 {
142 label = "led1";
143 gpios = <&pioD 31 0>;
144 linux,default-trigger = "heartbeat";
145 };
146 };
147
148 gpio_keys {
149 compatible = "gpio-keys";
150 #address-cells = <1>;
151 #size-cells = <0>;
152
153 right {
154 label = "SW4";
155 gpios = <&pioE 7 1>;
156 linux,code = <106>;
157 };
158
159 up {
160 label = "SW3";
161 gpios = <&pioE 8 1>;
162 linux,code = <103>;
163 };
164 };
165};
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index 702c0baa6004..c6f85f0bc531 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -99,6 +99,33 @@
99 status = "okay"; 99 status = "okay";
100 }; 100 };
101 101
102 prcmu@80157000 {
103 thermal@801573c0 {
104 num-trips = <4>;
105
106 trip0-temp = <70000>;
107 trip0-type = "active";
108 trip0-cdev-num = <1>;
109 trip0-cdev-name0 = "thermal-cpufreq-0";
110
111 trip1-temp = <75000>;
112 trip1-type = "active";
113 trip1-cdev-num = <1>;
114 trip1-cdev-name0 = "thermal-cpufreq-0";
115
116 trip2-temp = <80000>;
117 trip2-type = "active";
118 trip2-cdev-num = <1>;
119 trip2-cdev-name0 = "thermal-cpufreq-0";
120
121 trip3-temp = <85000>;
122 trip3-type = "critical";
123 trip3-cdev-num = <0>;
124
125 status = "okay";
126 };
127 };
128
102 external-bus@50000000 { 129 external-bus@50000000 {
103 status = "okay"; 130 status = "okay";
104 131
@@ -183,5 +210,9 @@
183 reg = <0x33>; 210 reg = <0x33>;
184 }; 211 };
185 }; 212 };
213
214 cpufreq-cooling {
215 status = "okay";
216 };
186 }; 217 };
187}; 218};
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index dd4358bc26e2..2e4c5727468e 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -181,6 +181,10 @@
181 status = "okay"; 181 status = "okay";
182 }; 182 };
183 183
184 gpio@d8400000 {
185 status = "okay";
186 };
187
184 i2c0: i2c@e0280000 { 188 i2c0: i2c@e0280000 {
185 status = "okay"; 189 status = "okay";
186 }; 190 };
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 419ea7413d23..7cd25eb4f8e0 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -70,6 +70,12 @@
70 status = "disabled"; 70 status = "disabled";
71 }; 71 };
72 72
73 pinmux: pinmux@e0700000 {
74 compatible = "st,spear1310-pinmux";
75 reg = <0xe0700000 0x1000>;
76 #gpio-range-cells = <2>;
77 };
78
73 spi1: spi@5d400000 { 79 spi1: spi@5d400000 {
74 compatible = "arm,pl022", "arm,primecell"; 80 compatible = "arm,pl022", "arm,primecell";
75 reg = <0x5d400000 0x1000>; 81 reg = <0x5d400000 0x1000>;
@@ -179,6 +185,27 @@
179 thermal@e07008c4 { 185 thermal@e07008c4 {
180 st,thermal-flags = <0x7000>; 186 st,thermal-flags = <0x7000>;
181 }; 187 };
188
189 gpiopinctrl: gpio@d8400000 {
190 compatible = "st,spear-plgpio";
191 reg = <0xd8400000 0x1000>;
192 interrupts = <0 100 0x4>;
193 #interrupt-cells = <1>;
194 interrupt-controller;
195 gpio-controller;
196 #gpio-cells = <2>;
197 gpio-ranges = <&pinmux 0 246>;
198 status = "disabled";
199
200 st-plgpio,ngpio = <246>;
201 st-plgpio,enb-reg = <0xd0>;
202 st-plgpio,wdata-reg = <0x90>;
203 st-plgpio,dir-reg = <0xb0>;
204 st-plgpio,ie-reg = <0x30>;
205 st-plgpio,rdata-reg = <0x70>;
206 st-plgpio,mis-reg = <0x10>;
207 st-plgpio,eit-reg = <0x50>;
208 };
182 }; 209 };
183 }; 210 };
184}; 211};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index c9a54e06fb68..045f7123ffac 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -193,6 +193,10 @@
193 status = "okay"; 193 status = "okay";
194 }; 194 };
195 195
196 gpio@e2800000 {
197 status = "okay";
198 };
199
196 i2c0: i2c@e0280000 { 200 i2c0: i2c@e0280000 {
197 status = "okay"; 201 status = "okay";
198 }; 202 };
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index d71fe2a68f09..6c09eb0a1b2b 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -24,6 +24,12 @@
24 status = "disabled"; 24 status = "disabled";
25 }; 25 };
26 26
27 pinmux: pinmux@e0700000 {
28 compatible = "st,spear1340-pinmux";
29 reg = <0xe0700000 0x1000>;
30 #gpio-range-cells = <2>;
31 };
32
27 spi1: spi@5d400000 { 33 spi1: spi@5d400000 {
28 compatible = "arm,pl022", "arm,primecell"; 34 compatible = "arm,pl022", "arm,primecell";
29 reg = <0x5d400000 0x1000>; 35 reg = <0x5d400000 0x1000>;
@@ -51,6 +57,26 @@
51 thermal@e07008c4 { 57 thermal@e07008c4 {
52 st,thermal-flags = <0x2a00>; 58 st,thermal-flags = <0x2a00>;
53 }; 59 };
60
61 gpiopinctrl: gpio@e2800000 {
62 compatible = "st,spear-plgpio";
63 reg = <0xe2800000 0x1000>;
64 interrupts = <0 107 0x4>;
65 #interrupt-cells = <1>;
66 interrupt-controller;
67 gpio-controller;
68 #gpio-cells = <2>;
69 gpio-ranges = <&pinmux 0 252>;
70 status = "disabled";
71
72 st-plgpio,ngpio = <250>;
73 st-plgpio,wdata-reg = <0x40>;
74 st-plgpio,dir-reg = <0x00>;
75 st-plgpio,ie-reg = <0x80>;
76 st-plgpio,rdata-reg = <0x20>;
77 st-plgpio,mis-reg = <0xa0>;
78 st-plgpio,eit-reg = <0x60>;
79 };
54 }; 80 };
55 }; 81 };
56}; 82};
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
index 62fc4fb3e5f9..930303e48df9 100644
--- a/arch/arm/boot/dts/spear310.dtsi
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -22,9 +22,10 @@
22 0xb0000000 0xb0000000 0x10000000 22 0xb0000000 0xb0000000 0x10000000
23 0xd0000000 0xd0000000 0x30000000>; 23 0xd0000000 0xd0000000 0x30000000>;
24 24
25 pinmux@b4000000 { 25 pinmux: pinmux@b4000000 {
26 compatible = "st,spear310-pinmux"; 26 compatible = "st,spear310-pinmux";
27 reg = <0xb4000000 0x1000>; 27 reg = <0xb4000000 0x1000>;
28 #gpio-range-cells = <2>;
28 }; 29 };
29 30
30 fsmc: flash@44000000 { 31 fsmc: flash@44000000 {
@@ -75,6 +76,25 @@
75 reg = <0xb2200000 0x1000>; 76 reg = <0xb2200000 0x1000>;
76 status = "disabled"; 77 status = "disabled";
77 }; 78 };
79
80 gpiopinctrl: gpio@b4000000 {
81 compatible = "st,spear-plgpio";
82 reg = <0xb4000000 0x1000>;
83 #interrupt-cells = <1>;
84 interrupt-controller;
85 gpio-controller;
86 #gpio-cells = <2>;
87 gpio-ranges = <&pinmux 0 102>;
88 status = "disabled";
89
90 st-plgpio,ngpio = <102>;
91 st-plgpio,enb-reg = <0x10>;
92 st-plgpio,wdata-reg = <0x20>;
93 st-plgpio,dir-reg = <0x30>;
94 st-plgpio,ie-reg = <0x50>;
95 st-plgpio,rdata-reg = <0x40>;
96 st-plgpio,mis-reg = <0x60>;
97 };
78 }; 98 };
79 }; 99 };
80}; 100};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index 082328bd64ab..ad4bfc68ee05 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -164,6 +164,10 @@
164 status = "okay"; 164 status = "okay";
165 }; 165 };
166 166
167 gpio@b3000000 {
168 status = "okay";
169 };
170
167 i2c0: i2c@d0180000 { 171 i2c0: i2c@d0180000 {
168 status = "okay"; 172 status = "okay";
169 }; 173 };
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index 1f49d69595a0..67d7ada71275 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -21,9 +21,10 @@
21 ranges = <0x40000000 0x40000000 0x80000000 21 ranges = <0x40000000 0x40000000 0x80000000
22 0xd0000000 0xd0000000 0x30000000>; 22 0xd0000000 0xd0000000 0x30000000>;
23 23
24 pinmux@b3000000 { 24 pinmux: pinmux@b3000000 {
25 compatible = "st,spear320-pinmux"; 25 compatible = "st,spear320-pinmux";
26 reg = <0xb3000000 0x1000>; 26 reg = <0xb3000000 0x1000>;
27 #gpio-range-cells = <2>;
27 }; 28 };
28 29
29 clcd@90000000 { 30 clcd@90000000 {
@@ -90,6 +91,26 @@
90 reg = <0xa4000000 0x1000>; 91 reg = <0xa4000000 0x1000>;
91 status = "disabled"; 92 status = "disabled";
92 }; 93 };
94
95 gpiopinctrl: gpio@b3000000 {
96 compatible = "st,spear-plgpio";
97 reg = <0xb3000000 0x1000>;
98 #interrupt-cells = <1>;
99 interrupt-controller;
100 gpio-controller;
101 #gpio-cells = <2>;
102 gpio-ranges = <&pinmux 0 102>;
103 status = "disabled";
104
105 st-plgpio,ngpio = <102>;
106 st-plgpio,enb-reg = <0x24>;
107 st-plgpio,wdata-reg = <0x34>;
108 st-plgpio,dir-reg = <0x44>;
109 st-plgpio,ie-reg = <0x64>;
110 st-plgpio,rdata-reg = <0x54>;
111 st-plgpio,mis-reg = <0x84>;
112 st-plgpio,eit-reg = <0x94>;
113 };
93 }; 114 };
94 }; 115 };
95}; 116};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index f0ba901676ac..a20d4ff3fb3c 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -523,12 +523,12 @@
523 }; 523 };
524 524
525 temperature-sensor@4c { 525 temperature-sensor@4c {
526 compatible = "nct1008"; 526 compatible = "onnn,nct1008";
527 reg = <0x4c>; 527 reg = <0x4c>;
528 }; 528 };
529 529
530 magnetometer@c { 530 magnetometer@c {
531 compatible = "ak8975"; 531 compatible = "ak,ak8975";
532 reg = <0xc>; 532 reg = <0xc>;
533 interrupt-parent = <&gpio>; 533 interrupt-parent = <&gpio>;
534 interrupts = <109 0x04>; /* gpio PN5 */ 534 interrupts = <109 0x04>; /* gpio PN5 */
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index b1497c7d7d68..df7f2270fc91 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -73,8 +73,8 @@
73 73
74 pinmux: pinmux { 74 pinmux: pinmux {
75 compatible = "nvidia,tegra30-pinmux"; 75 compatible = "nvidia,tegra30-pinmux";
76 reg = <0x70000868 0xd0 /* Pad control registers */ 76 reg = <0x70000868 0xd4 /* Pad control registers */
77 0x70003000 0x3e0>; /* Mux registers */ 77 0x70003000 0x3e4>; /* Mux registers */
78 }; 78 };
79 79
80 serial@70006000 { 80 serial@70006000 {
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 19:25:37 -0400