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-rw-r--r--arch/arm/boot/dts/am33xx.dtsi4
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi4
-rw-r--r--arch/arm/boot/dts/at91rm9200.dtsi6
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi8
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi8
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi8
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi8
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi8
-rw-r--r--arch/arm/boot/dts/exynos5440.dtsi4
-rw-r--r--arch/arm/boot/dts/imx23.dtsi8
-rw-r--r--arch/arm/boot/dts/imx28.dtsi8
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi4
-rw-r--r--arch/arm/boot/dts/lpc32xx.dtsi8
-rw-r--r--arch/arm/boot/dts/omap2.dtsi6
-rw-r--r--arch/arm/boot/dts/omap3.dtsi5
-rw-r--r--arch/arm/boot/dts/omap4.dtsi7
-rw-r--r--arch/arm/boot/dts/omap5.dtsi7
-rw-r--r--arch/arm/boot/dts/picoxcell-pc3x2.dtsi8
-rw-r--r--arch/arm/boot/dts/picoxcell-pc3x3.dtsi8
-rw-r--r--arch/arm/boot/dts/prima2.dtsi2
-rw-r--r--arch/arm/boot/dts/pxa2xx.dtsi7
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi4
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi2
-rw-r--r--arch/arm/boot/dts/sh7372.dtsi5
-rw-r--r--arch/arm/boot/dts/spear13xx.dtsi2
-rw-r--r--arch/arm/boot/dts/spear3xx.dtsi8
-rw-r--r--arch/arm/boot/dts/spear600.dtsi8
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi2
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi2
30 files changed, 139 insertions, 32 deletions
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 1460d9b88adf..6827853a0a8f 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -26,8 +26,12 @@
26 }; 26 };
27 27
28 cpus { 28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
29 cpu@0 { 31 cpu@0 {
30 compatible = "arm,cortex-a8"; 32 compatible = "arm,cortex-a8";
33 device_type = "cpu";
34 reg = <0>;
31 35
32 /* 36 /*
33 * To consider voltage drop between PMIC and SoC, 37 * To consider voltage drop between PMIC and SoC,
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 0d73570a303d..36feff3a363e 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -23,8 +23,12 @@
23 compatible = "marvell,armada-370-xp"; 23 compatible = "marvell,armada-370-xp";
24 24
25 cpus { 25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
26 cpu@0 { 28 cpu@0 {
27 compatible = "marvell,sheeva-v7"; 29 compatible = "marvell,sheeva-v7";
30 device_type = "cpu";
31 reg = <0>;
28 }; 32 };
29 }; 33 };
30 34
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index b91cf78f2cf1..34c03806fe06 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -38,8 +38,12 @@
38 ssc2 = &ssc2; 38 ssc2 = &ssc2;
39 }; 39 };
40 cpus { 40 cpus {
41 cpu@0 { 41 #address-cells = <0>;
42 #size-cells = <0>;
43
44 cpu {
42 compatible = "arm,arm920t"; 45 compatible = "arm,arm920t";
46 device_type = "cpu";
43 }; 47 };
44 }; 48 };
45 49
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index cae3ba5d18c7..c7ccbcbffb3e 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -35,8 +35,12 @@
35 ssc0 = &ssc0; 35 ssc0 = &ssc0;
36 }; 36 };
37 cpus { 37 cpus {
38 cpu@0 { 38 #address-cells = <0>;
39 compatible = "arm,arm926ejs"; 39 #size-cells = <0>;
40
41 cpu {
42 compatible = "arm,arm926ej-s";
43 device_type = "cpu";
40 }; 44 };
41 }; 45 };
42 46
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index ff638116db14..d5bd65f74602 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -32,8 +32,12 @@
32 ssc1 = &ssc1; 32 ssc1 = &ssc1;
33 }; 33 };
34 cpus { 34 cpus {
35 cpu@0 { 35 #address-cells = <0>;
36 compatible = "arm,arm926ejs"; 36 #size-cells = <0>;
37
38 cpu {
39 compatible = "arm,arm926ej-s";
40 device_type = "cpu";
37 }; 41 };
38 }; 42 };
39 43
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index faec17d1bb33..a03d0c05d027 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -38,8 +38,12 @@
38 ssc1 = &ssc1; 38 ssc1 = &ssc1;
39 }; 39 };
40 cpus { 40 cpus {
41 cpu@0 { 41 #address-cells = <0>;
42 compatible = "arm,arm926ejs"; 42 #size-cells = <0>;
43
44 cpu {
45 compatible = "arm,arm926ej-s";
46 device_type = "cpu";
43 }; 47 };
44 }; 48 };
45 49
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 1d220b26f516..d37761846cd5 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -34,8 +34,12 @@
34 ssc0 = &ssc0; 34 ssc0 = &ssc0;
35 }; 35 };
36 cpus { 36 cpus {
37 cpu@0 { 37 #address-cells = <0>;
38 compatible = "arm,arm926ejs"; 38 #size-cells = <0>;
39
40 cpu {
41 compatible = "arm,arm926ej-s";
42 device_type = "cpu";
39 }; 43 };
40 }; 44 };
41 45
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index e77106ef2ee5..ff4bd7a061b0 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -36,8 +36,12 @@
36 ssc0 = &ssc0; 36 ssc0 = &ssc0;
37 }; 37 };
38 cpus { 38 cpus {
39 cpu@0 { 39 #address-cells = <0>;
40 compatible = "arm,arm926ejs"; 40 #size-cells = <0>;
41
42 cpu {
43 compatible = "arm,arm926ej-s";
44 device_type = "cpu";
41 }; 45 };
42 }; 46 };
43 47
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c8973845..646677edcaae 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -38,18 +38,22 @@
38 #size-cells = <0>; 38 #size-cells = <0>;
39 39
40 cpu@0 { 40 cpu@0 {
41 device_type = "cpu";
41 compatible = "arm,cortex-a15"; 42 compatible = "arm,cortex-a15";
42 reg = <0>; 43 reg = <0>;
43 }; 44 };
44 cpu@1 { 45 cpu@1 {
46 device_type = "cpu";
45 compatible = "arm,cortex-a15"; 47 compatible = "arm,cortex-a15";
46 reg = <1>; 48 reg = <1>;
47 }; 49 };
48 cpu@2 { 50 cpu@2 {
51 device_type = "cpu";
49 compatible = "arm,cortex-a15"; 52 compatible = "arm,cortex-a15";
50 reg = <2>; 53 reg = <2>;
51 }; 54 };
52 cpu@3 { 55 cpu@3 {
56 device_type = "cpu";
53 compatible = "arm,cortex-a15"; 57 compatible = "arm,cortex-a15";
54 reg = <3>; 58 reg = <3>;
55 }; 59 };
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 73fd7d0887b5..587ceef81e45 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -23,8 +23,12 @@
23 }; 23 };
24 24
25 cpus { 25 cpus {
26 cpu@0 { 26 #address-cells = <0>;
27 compatible = "arm,arm926ejs"; 27 #size-cells = <0>;
28
29 cpu {
30 compatible = "arm,arm926ej-s";
31 device_type = "cpu";
28 }; 32 };
29 }; 33 };
30 34
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 600f7cb51f3e..4c10a1968c0e 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -32,8 +32,12 @@
32 }; 32 };
33 33
34 cpus { 34 cpus {
35 cpu@0 { 35 #address-cells = <0>;
36 compatible = "arm,arm926ejs"; 36 #size-cells = <0>;
37
38 cpu {
39 compatible = "arm,arm926ej-s";
40 device_type = "cpu";
37 }; 41 };
38 }; 42 };
39 43
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 5bcdf3a90bb3..62dc78126795 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -18,12 +18,14 @@
18 18
19 cpu@0 { 19 cpu@0 {
20 compatible = "arm,cortex-a9"; 20 compatible = "arm,cortex-a9";
21 device_type = "cpu";
21 reg = <0>; 22 reg = <0>;
22 next-level-cache = <&L2>; 23 next-level-cache = <&L2>;
23 }; 24 };
24 25
25 cpu@1 { 26 cpu@1 {
26 compatible = "arm,cortex-a9"; 27 compatible = "arm,cortex-a9";
28 device_type = "cpu";
27 reg = <1>; 29 reg = <1>;
28 next-level-cache = <&L2>; 30 next-level-cache = <&L2>;
29 }; 31 };
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 21e675848bd1..dc54a72a3bcd 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -18,6 +18,7 @@
18 18
19 cpu@0 { 19 cpu@0 {
20 compatible = "arm,cortex-a9"; 20 compatible = "arm,cortex-a9";
21 device_type = "cpu";
21 reg = <0>; 22 reg = <0>;
22 next-level-cache = <&L2>; 23 next-level-cache = <&L2>;
23 operating-points = < 24 operating-points = <
@@ -39,18 +40,21 @@
39 40
40 cpu@1 { 41 cpu@1 {
41 compatible = "arm,cortex-a9"; 42 compatible = "arm,cortex-a9";
43 device_type = "cpu";
42 reg = <1>; 44 reg = <1>;
43 next-level-cache = <&L2>; 45 next-level-cache = <&L2>;
44 }; 46 };
45 47
46 cpu@2 { 48 cpu@2 {
47 compatible = "arm,cortex-a9"; 49 compatible = "arm,cortex-a9";
50 device_type = "cpu";
48 reg = <2>; 51 reg = <2>;
49 next-level-cache = <&L2>; 52 next-level-cache = <&L2>;
50 }; 53 };
51 54
52 cpu@3 { 55 cpu@3 {
53 compatible = "arm,cortex-a9"; 56 compatible = "arm,cortex-a9";
57 device_type = "cpu";
54 reg = <3>; 58 reg = <3>;
55 next-level-cache = <&L2>; 59 next-level-cache = <&L2>;
56 }; 60 };
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 1582f484a867..3abebb75fc57 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -18,8 +18,12 @@
18 interrupt-parent = <&mic>; 18 interrupt-parent = <&mic>;
19 19
20 cpus { 20 cpus {
21 cpu@0 { 21 #address-cells = <0>;
22 compatible = "arm,arm926ejs"; 22 #size-cells = <0>;
23
24 cpu {
25 compatible = "arm,arm926ej-s";
26 device_type = "cpu";
23 }; 27 };
24 }; 28 };
25 29
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 37aa7487d4d8..4aac404608cb 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -21,8 +21,12 @@
21 }; 21 };
22 22
23 cpus { 23 cpus {
24 cpu@0 { 24 #address-cells = <0>;
25 #size-cells = <0>;
26
27 cpu {
25 compatible = "arm,arm1136jf-s"; 28 compatible = "arm,arm1136jf-s";
29 device_type = "cpu";
26 }; 30 };
27 }; 31 };
28 32
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 99ba6e14ebf3..0bbeff2afd4d 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -21,8 +21,13 @@
21 }; 21 };
22 22
23 cpus { 23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
24 cpu@0 { 27 cpu@0 {
25 compatible = "arm,cortex-a8"; 28 compatible = "arm,cortex-a8";
29 device_type = "cpu";
30 reg = <0x0>;
26 }; 31 };
27 }; 32 };
28 33
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 2a5642882c8a..33a94509a292 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -28,13 +28,20 @@
28 }; 28 };
29 29
30 cpus { 30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
31 cpu@0 { 34 cpu@0 {
32 compatible = "arm,cortex-a9"; 35 compatible = "arm,cortex-a9";
36 device_type = "cpu";
33 next-level-cache = <&L2>; 37 next-level-cache = <&L2>;
38 reg = <0x0>;
34 }; 39 };
35 cpu@1 { 40 cpu@1 {
36 compatible = "arm,cortex-a9"; 41 compatible = "arm,cortex-a9";
42 device_type = "cpu";
37 next-level-cache = <&L2>; 43 next-level-cache = <&L2>;
44 reg = <0x1>;
38 }; 45 };
39 }; 46 };
40 47
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3dd7ff825828..35a6536a10b5 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -34,11 +34,18 @@
34 }; 34 };
35 35
36 cpus { 36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
37 cpu@0 { 40 cpu@0 {
41 device_type = "cpu";
38 compatible = "arm,cortex-a15"; 42 compatible = "arm,cortex-a15";
43 reg = <0x0>;
39 }; 44 };
40 cpu@1 { 45 cpu@1 {
46 device_type = "cpu";
41 compatible = "arm,cortex-a15"; 47 compatible = "arm,cortex-a15";
48 reg = <0x1>;
42 }; 49 };
43 }; 50 };
44 51
diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
index f0a8c2068ea7..533919e96eae 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
@@ -18,13 +18,13 @@
18 #size-cells = <1>; 18 #size-cells = <1>;
19 19
20 cpus { 20 cpus {
21 #address-cells = <1>; 21 #address-cells = <0>;
22 #size-cells = <0>; 22 #size-cells = <0>;
23 23
24 cpu@0 { 24 cpu {
25 compatible = "arm,1176jz-s"; 25 compatible = "arm,arm1176jz-s";
26 device_type = "cpu";
26 clock-frequency = <400000000>; 27 clock-frequency = <400000000>;
27 reg = <0>;
28 d-cache-line-size = <32>; 28 d-cache-line-size = <32>;
29 d-cache-size = <32768>; 29 d-cache-size = <32768>;
30 i-cache-line-size = <32>; 30 i-cache-line-size = <32>;
diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
index daa962d191e6..ab3e80085511 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
@@ -18,13 +18,13 @@
18 #size-cells = <1>; 18 #size-cells = <1>;
19 19
20 cpus { 20 cpus {
21 #address-cells = <1>; 21 #address-cells = <0>;
22 #size-cells = <0>; 22 #size-cells = <0>;
23 23
24 cpu@0 { 24 cpu {
25 compatible = "arm,1176jz-s"; 25 compatible = "arm,arm1176jz-s";
26 device_type = "cpu";
26 cpu-clock = <&arm_clk>, "cpu"; 27 cpu-clock = <&arm_clk>, "cpu";
27 reg = <0>;
28 d-cache-line-size = <32>; 28 d-cache-line-size = <32>;
29 d-cache-size = <32768>; 29 d-cache-size = <32768>;
30 i-cache-line-size = <32>; 30 i-cache-line-size = <32>;
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 3329719a9412..02edd8965f8a 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -18,6 +18,8 @@
18 #size-cells = <0>; 18 #size-cells = <0>;
19 19
20 cpu@0 { 20 cpu@0 {
21 compatible = "arm,cortex-a9";
22 device_type = "cpu";
21 reg = <0x0>; 23 reg = <0x0>;
22 d-cache-line-size = <32>; 24 d-cache-line-size = <32>;
23 i-cache-line-size = <32>; 25 i-cache-line-size = <32>;
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index f18aad35e8b3..a5e90f078aa9 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -23,8 +23,11 @@
23 }; 23 };
24 24
25 cpus { 25 cpus {
26 cpu@0 { 26 #address-cells = <0>;
27 compatible = "arm,xscale"; 27 #size-cells = <0>;
28 cpu {
29 compatible = "marvell,xscale";
30 device_type = "cpu";
28 }; 31 };
29 }; 32 };
30 33
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 798fa35c0005..8a831e91e607 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -14,8 +14,12 @@
14 compatible = "renesas,r8a7740"; 14 compatible = "renesas,r8a7740";
15 15
16 cpus { 16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
17 cpu@0 { 19 cpu@0 {
18 compatible = "arm,cortex-a9"; 20 compatible = "arm,cortex-a9";
21 device_type = "cpu";
22 reg = <0x0>;
19 }; 23 };
20 }; 24 };
21}; 25};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index d5922935523f..abdf1c8336a1 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -39,7 +39,9 @@
39 }; 39 };
40 cpus { 40 cpus {
41 cpu@0 { 41 cpu@0 {
42 device_type = "cpu";
42 compatible = "arm,cortex-a5"; 43 compatible = "arm,cortex-a5";
44 reg = <0x0>;
43 }; 45 };
44 }; 46 };
45 47
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
index 677fc603f8b3..7bf020ecadf5 100644
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -14,8 +14,13 @@
14 compatible = "renesas,sh7372"; 14 compatible = "renesas,sh7372";
15 15
16 cpus { 16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
17 cpu@0 { 20 cpu@0 {
18 compatible = "arm,cortex-a8"; 21 compatible = "arm,cortex-a8";
22 device_type = "cpu";
23 reg = <0x0>;
19 }; 24 };
20 }; 25 };
21}; 26};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 45597fd91050..4382547df58a 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -22,12 +22,14 @@
22 22
23 cpu@0 { 23 cpu@0 {
24 compatible = "arm,cortex-a9"; 24 compatible = "arm,cortex-a9";
25 device_type = "cpu";
25 reg = <0>; 26 reg = <0>;
26 next-level-cache = <&L2>; 27 next-level-cache = <&L2>;
27 }; 28 };
28 29
29 cpu@1 { 30 cpu@1 {
30 compatible = "arm,cortex-a9"; 31 compatible = "arm,cortex-a9";
32 device_type = "cpu";
31 reg = <1>; 33 reg = <1>;
32 next-level-cache = <&L2>; 34 next-level-cache = <&L2>;
33 }; 35 };
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index c2a852d43c48..f0e3fcf8e323 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -17,8 +17,12 @@
17 interrupt-parent = <&vic>; 17 interrupt-parent = <&vic>;
18 18
19 cpus { 19 cpus {
20 cpu@0 { 20 #address-cells = <0>;
21 compatible = "arm,arm926ejs"; 21 #size-cells = <0>;
22
23 cpu {
24 compatible = "arm,arm926ej-s";
25 device_type = "cpu";
22 }; 26 };
23 }; 27 };
24 28
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index 19f99dc4115e..9f60a7b6a42b 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -15,8 +15,12 @@
15 compatible = "st,spear600"; 15 compatible = "st,spear600";
16 16
17 cpus { 17 cpus {
18 cpu@0 { 18 #address-cells = <0>;
19 compatible = "arm,arm926ejs"; 19 #size-cells = <0>;
20
21 cpu {
22 compatible = "arm,arm926ej-s";
23 device_type = "cpu";
20 }; 24 };
21 }; 25 };
22 26
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619a70a2..39a8f61528d9 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -17,7 +17,9 @@
17 17
18 cpus { 18 cpus {
19 cpu@0 { 19 cpu@0 {
20 device_type = "cpu";
20 compatible = "arm,cortex-a8"; 21 compatible = "arm,cortex-a8";
22 reg = <0x0>;
21 }; 23 };
22 }; 24 };
23 25
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 31fa38f8cc98..00a2637da62e 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -18,7 +18,9 @@
18 18
19 cpus { 19 cpus {
20 cpu@0 { 20 cpu@0 {
21 device_type = "cpu";
21 compatible = "arm,cortex-a8"; 22 compatible = "arm,cortex-a8";
23 reg = <0x0>;
22 }; 24 };
23 }; 25 };
24 26
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-16 10:13:24 -0400