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-rw-r--r--arch/arm/boot/dts/Makefile6
-rw-r--r--arch/arm/boot/dts/armada-380.dtsi2
-rw-r--r--arch/arm/boot/dts/armada-385-db.dts2
-rw-r--r--arch/arm/boot/dts/armada-385-rd.dts2
-rw-r--r--arch/arm/boot/dts/armada-385.dtsi2
-rw-r--r--arch/arm/boot/dts/armada-38x.dtsi2
-rw-r--r--arch/arm/boot/dts/at91sam9261.dtsi21
-rw-r--r--arch/arm/boot/dts/at91sam9261ek.dts4
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi4
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi2
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts10
-rw-r--r--arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts4
-rw-r--r--arch/arm/boot/dts/imx53-m53evk.dts40
-rw-r--r--arch/arm/boot/dts/imx6dl-hummingboard.dts10
-rw-r--r--arch/arm/boot/dts/imx6q-gw51xx.dts2
-rw-r--r--arch/arm/boot/dts/imx6qdl-cubox-i.dtsi27
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw51xx.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw52xx.dtsi4
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw53xx.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-microsom.dtsi13
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi2
-rw-r--r--arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts4
-rw-r--r--arch/arm/boot/dts/r8a7779-marzen-reference.dts121
-rw-r--r--arch/arm/boot/dts/r8a7779-marzen.dts116
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi220
-rw-r--r--arch/arm/boot/dts/stih415.dtsi8
-rw-r--r--arch/arm/boot/dts/stih416-b2020e.dts (renamed from arch/arm/boot/dts/stih416-b2020-revE.dts)0
-rw-r--r--arch/arm/boot/dts/stih416.dtsi8
29 files changed, 438 insertions, 206 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5986ff63b901..eb280d3483eb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -327,7 +327,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
327 r8a7778-bockw-reference.dtb \ 327 r8a7778-bockw-reference.dtb \
328 r8a7740-armadillo800eva-reference.dtb \ 328 r8a7740-armadillo800eva-reference.dtb \
329 r8a7779-marzen.dtb \ 329 r8a7779-marzen.dtb \
330 r8a7779-marzen-reference.dtb \
331 r8a7791-koelsch.dtb \ 330 r8a7791-koelsch.dtb \
332 r8a7790-lager.dtb \ 331 r8a7790-lager.dtb \
333 sh73a0-kzm9g.dtb \ 332 sh73a0-kzm9g.dtb \
@@ -339,7 +338,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
339 r7s72100-genmai.dtb \ 338 r7s72100-genmai.dtb \
340 r8a7791-henninger.dtb \ 339 r8a7791-henninger.dtb \
341 r8a7791-koelsch.dtb \ 340 r8a7791-koelsch.dtb \
342 r8a7790-lager.dtb 341 r8a7790-lager.dtb \
342 r8a7779-marzen.dtb
343dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ 343dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
344 socfpga_cyclone5_socdk.dtb \ 344 socfpga_cyclone5_socdk.dtb \
345 socfpga_cyclone5_sockit.dtb \ 345 socfpga_cyclone5_sockit.dtb \
@@ -357,7 +357,7 @@ dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
357 stih415-b2020.dtb \ 357 stih415-b2020.dtb \
358 stih416-b2000.dtb \ 358 stih416-b2000.dtb \
359 stih416-b2020.dtb \ 359 stih416-b2020.dtb \
360 stih416-b2020-revE.dtb 360 stih416-b2020e.dtb
361dtb-$(CONFIG_MACH_SUN4I) += \ 361dtb-$(CONFIG_MACH_SUN4I) += \
362 sun4i-a10-a1000.dtb \ 362 sun4i-a10-a1000.dtb \
363 sun4i-a10-cubieboard.dtb \ 363 sun4i-a10-cubieboard.dtb \
diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
index e69bc6759c39..4173a8ab34e7 100644
--- a/arch/arm/boot/dts/armada-380.dtsi
+++ b/arch/arm/boot/dts/armada-380.dtsi
@@ -16,7 +16,7 @@
16 16
17/ { 17/ {
18 model = "Marvell Armada 380 family SoC"; 18 model = "Marvell Armada 380 family SoC";
19 compatible = "marvell,armada380", "marvell,armada38x"; 19 compatible = "marvell,armada380";
20 20
21 cpus { 21 cpus {
22 #address-cells = <1>; 22 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts
index 5bae4731828b..1af886f1e486 100644
--- a/arch/arm/boot/dts/armada-385-db.dts
+++ b/arch/arm/boot/dts/armada-385-db.dts
@@ -16,7 +16,7 @@
16 16
17/ { 17/ {
18 model = "Marvell Armada 385 Development Board"; 18 model = "Marvell Armada 385 Development Board";
19 compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada38x"; 19 compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada380";
20 20
21 chosen { 21 chosen {
22 bootargs = "console=ttyS0,115200 earlyprintk"; 22 bootargs = "console=ttyS0,115200 earlyprintk";
diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-385-rd.dts
index 40893255a3f0..aaca2861dc87 100644
--- a/arch/arm/boot/dts/armada-385-rd.dts
+++ b/arch/arm/boot/dts/armada-385-rd.dts
@@ -17,7 +17,7 @@
17 17
18/ { 18/ {
19 model = "Marvell Armada 385 Reference Design"; 19 model = "Marvell Armada 385 Reference Design";
20 compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada38x"; 20 compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380";
21 21
22 chosen { 22 chosen {
23 bootargs = "console=ttyS0,115200 earlyprintk"; 23 bootargs = "console=ttyS0,115200 earlyprintk";
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
index f011009bf4cf..6283d7912f71 100644
--- a/arch/arm/boot/dts/armada-385.dtsi
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -16,7 +16,7 @@
16 16
17/ { 17/ {
18 model = "Marvell Armada 385 family SoC"; 18 model = "Marvell Armada 385 family SoC";
19 compatible = "marvell,armada385", "marvell,armada38x"; 19 compatible = "marvell,armada385", "marvell,armada380";
20 20
21 cpus { 21 cpus {
22 #address-cells = <1>; 22 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 3de364e81b52..689fa1a46728 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -20,7 +20,7 @@
20 20
21/ { 21/ {
22 model = "Marvell Armada 38x family SoC"; 22 model = "Marvell Armada 38x family SoC";
23 compatible = "marvell,armada38x"; 23 compatible = "marvell,armada380";
24 24
25 aliases { 25 aliases {
26 gpio0 = &gpio0; 26 gpio0 = &gpio0;
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index b309c1c6e848..04927db1d6bf 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -568,24 +568,17 @@
568 #size-cells = <0>; 568 #size-cells = <0>;
569 #interrupt-cells = <1>; 569 #interrupt-cells = <1>;
570 570
571 slow_rc_osc: slow_rc_osc { 571 main_osc: main_osc {
572 compatible = "fixed-clock"; 572 compatible = "atmel,at91rm9200-clk-main-osc";
573 #clock-cells = <0>; 573 #clock-cells = <0>;
574 clock-frequency = <32768>; 574 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
575 clock-accuracy = <50000000>; 575 clocks = <&main_xtal>;
576 };
577
578 clk32k: slck {
579 compatible = "atmel,at91sam9260-clk-slow";
580 #clock-cells = <0>;
581 clocks = <&slow_rc_osc &slow_xtal>;
582 }; 576 };
583 577
584 main: mainck { 578 main: mainck {
585 compatible = "atmel,at91rm9200-clk-main"; 579 compatible = "atmel,at91rm9200-clk-main";
586 #clock-cells = <0>; 580 #clock-cells = <0>;
587 interrupts-extended = <&pmc AT91_PMC_MOSCS>; 581 clocks = <&main_osc>;
588 clocks = <&main_xtal>;
589 }; 582 };
590 583
591 plla: pllack { 584 plla: pllack {
@@ -615,7 +608,7 @@
615 compatible = "atmel,at91rm9200-clk-master"; 608 compatible = "atmel,at91rm9200-clk-master";
616 #clock-cells = <0>; 609 #clock-cells = <0>;
617 interrupts-extended = <&pmc AT91_PMC_MCKRDY>; 610 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
618 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; 611 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
619 atmel,clk-output-range = <0 94000000>; 612 atmel,clk-output-range = <0 94000000>;
620 atmel,clk-divisors = <1 2 4 0>; 613 atmel,clk-divisors = <1 2 4 0>;
621 }; 614 };
@@ -632,7 +625,7 @@
632 #address-cells = <1>; 625 #address-cells = <1>;
633 #size-cells = <0>; 626 #size-cells = <0>;
634 interrupt-parent = <&pmc>; 627 interrupt-parent = <&pmc>;
635 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; 628 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
636 629
637 prog0: prog0 { 630 prog0: prog0 {
638 #clock-cells = <0>; 631 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts
index c6683ea8b743..aa35a7aec9a8 100644
--- a/arch/arm/boot/dts/at91sam9261ek.dts
+++ b/arch/arm/boot/dts/at91sam9261ek.dts
@@ -20,6 +20,10 @@
20 reg = <0x20000000 0x4000000>; 20 reg = <0x20000000 0x4000000>;
21 }; 21 };
22 22
23 slow_xtal {
24 clock-frequency = <32768>;
25 };
26
23 main_xtal { 27 main_xtal {
24 clock-frequency = <18432000>; 28 clock-frequency = <18432000>;
25 }; 29 };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index d1b82e6635d5..287795985e32 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -132,8 +132,8 @@
132 <595000000 650000000 3 0>, 132 <595000000 650000000 3 0>,
133 <545000000 600000000 0 1>, 133 <545000000 600000000 0 1>,
134 <495000000 555000000 1 1>, 134 <495000000 555000000 1 1>,
135 <445000000 500000000 1 2>, 135 <445000000 500000000 2 1>,
136 <400000000 450000000 1 3>; 136 <400000000 450000000 3 1>;
137 }; 137 };
138 138
139 plladiv: plladivck { 139 plladiv: plladivck {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 1a57298636a5..d6133f497207 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -140,8 +140,8 @@
140 595000000 650000000 3 0 140 595000000 650000000 3 0
141 545000000 600000000 0 1 141 545000000 600000000 0 1
142 495000000 555000000 1 1 142 495000000 555000000 1 1
143 445000000 500000000 1 2 143 445000000 500000000 2 1
144 400000000 450000000 1 3>; 144 400000000 450000000 3 1>;
145 }; 145 };
146 146
147 plladiv: plladivck { 147 plladiv: plladivck {
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index b8ece4be41ca..fbaf426d2daa 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -113,7 +113,7 @@
113 compatible = "arm,cortex-a9-gic"; 113 compatible = "arm,cortex-a9-gic";
114 #interrupt-cells = <3>; 114 #interrupt-cells = <3>;
115 interrupt-controller; 115 interrupt-controller;
116 reg = <0x10490000 0x1000>, <0x10480000 0x100>; 116 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
117 }; 117 };
118 118
119 combiner: interrupt-controller@10440000 { 119 combiner: interrupt-controller@10440000 {
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 6bc3243a80d3..181d77fa2fa6 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -315,15 +315,15 @@
315&esdhc1 { 315&esdhc1 {
316 pinctrl-names = "default"; 316 pinctrl-names = "default";
317 pinctrl-0 = <&pinctrl_esdhc1>; 317 pinctrl-0 = <&pinctrl_esdhc1>;
318 fsl,cd-controller; 318 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
319 fsl,wp-controller; 319 wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
320 status = "okay"; 320 status = "okay";
321}; 321};
322 322
323&esdhc2 { 323&esdhc2 {
324 pinctrl-names = "default"; 324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_esdhc2>; 325 pinctrl-0 = <&pinctrl_esdhc2>;
326 cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 326 cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
327 wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 327 wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
328 status = "okay"; 328 status = "okay";
329}; 329};
@@ -468,8 +468,8 @@
468 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 468 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
469 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 469 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
470 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 470 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
471 MX51_PAD_GPIO1_0__SD1_CD 0x20d5 471 MX51_PAD_GPIO1_0__GPIO1_0 0x100
472 MX51_PAD_GPIO1_1__SD1_WP 0x20d5 472 MX51_PAD_GPIO1_1__GPIO1_1 0x100
473 >; 473 >;
474 }; 474 };
475 475
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
index 75e66c9c6144..31cfb7f2b02e 100644
--- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
+++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
@@ -107,7 +107,7 @@
107&esdhc1 { 107&esdhc1 {
108 pinctrl-names = "default"; 108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_esdhc1 &pinctrl_esdhc1_cd>; 109 pinctrl-0 = <&pinctrl_esdhc1 &pinctrl_esdhc1_cd>;
110 fsl,cd-controller; 110 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
111 status = "okay"; 111 status = "okay";
112}; 112};
113 113
@@ -206,7 +206,7 @@
206 206
207 pinctrl_esdhc1_cd: esdhc1_cd { 207 pinctrl_esdhc1_cd: esdhc1_cd {
208 fsl,pins = < 208 fsl,pins = <
209 MX51_PAD_GPIO1_0__SD1_CD 0x20d5 209 MX51_PAD_GPIO1_0__GPIO1_0 0xd5
210 >; 210 >;
211 }; 211 };
212 212
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index d5d146a8b149..c4956b0ffb35 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -21,27 +21,25 @@
21 <0xb0000000 0x20000000>; 21 <0xb0000000 0x20000000>;
22 }; 22 };
23 23
24 soc { 24 display1: display@di1 {
25 display1: display@di1 { 25 compatible = "fsl,imx-parallel-display";
26 compatible = "fsl,imx-parallel-display"; 26 interface-pix-fmt = "bgr666";
27 interface-pix-fmt = "bgr666"; 27 pinctrl-names = "default";
28 pinctrl-names = "default"; 28 pinctrl-0 = <&pinctrl_ipu_disp1>;
29 pinctrl-0 = <&pinctrl_ipu_disp1>; 29
30 30 display-timings {
31 display-timings { 31 800x480p60 {
32 800x480p60 { 32 native-mode;
33 native-mode; 33 clock-frequency = <31500000>;
34 clock-frequency = <31500000>; 34 hactive = <800>;
35 hactive = <800>; 35 vactive = <480>;
36 vactive = <480>; 36 hfront-porch = <40>;
37 hfront-porch = <40>; 37 hback-porch = <88>;
38 hback-porch = <88>; 38 hsync-len = <128>;
39 hsync-len = <128>; 39 vback-porch = <33>;
40 vback-porch = <33>; 40 vfront-porch = <9>;
41 vfront-porch = <9>; 41 vsync-len = <3>;
42 vsync-len = <3>; 42 vsync-active = <1>;
43 vsync-active = <1>;
44 };
45 }; 43 };
46 }; 44 };
47 45
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
index 5373a5f2782b..c8e51dd41b8f 100644
--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -143,6 +143,14 @@
143 fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>; 143 fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
144 }; 144 };
145 145
146 pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
147 /*
148 * Similar to pinctrl_usbotg_2, but we want it
149 * pulled down for a fixed host connection.
150 */
151 fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
152 };
153
146 pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus { 154 pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
147 fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>; 155 fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
148 }; 156 };
@@ -178,6 +186,8 @@
178}; 186};
179 187
180&usbotg { 188&usbotg {
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
181 vbus-supply = <&reg_usbotg_vbus>; 191 vbus-supply = <&reg_usbotg_vbus>;
182 status = "okay"; 192 status = "okay";
183}; 193};
diff --git a/arch/arm/boot/dts/imx6q-gw51xx.dts b/arch/arm/boot/dts/imx6q-gw51xx.dts
index af4929aee075..0e1406e58eff 100644
--- a/arch/arm/boot/dts/imx6q-gw51xx.dts
+++ b/arch/arm/boot/dts/imx6q-gw51xx.dts
@@ -11,7 +11,7 @@
11 11
12/dts-v1/; 12/dts-v1/;
13#include "imx6q.dtsi" 13#include "imx6q.dtsi"
14#include "imx6qdl-gw54xx.dtsi" 14#include "imx6qdl-gw51xx.dtsi"
15 15
16/ { 16/ {
17 model = "Gateworks Ventana i.MX6 Quad GW51XX"; 17 model = "Gateworks Ventana i.MX6 Quad GW51XX";
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index 25da82a03110..e8e781656b3f 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -12,6 +12,19 @@
12 pinctrl-0 = <&pinctrl_cubox_i_ir>; 12 pinctrl-0 = <&pinctrl_cubox_i_ir>;
13 }; 13 };
14 14
15 pwmleds {
16 compatible = "pwm-leds";
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_cubox_i_pwm1>;
19
20 front {
21 active-low;
22 label = "imx6:red:front";
23 max-brightness = <248>;
24 pwms = <&pwm1 0 50000>;
25 };
26 };
27
15 regulators { 28 regulators {
16 compatible = "simple-bus"; 29 compatible = "simple-bus";
17 30
@@ -109,6 +122,10 @@
109 >; 122 >;
110 }; 123 };
111 124
125 pinctrl_cubox_i_pwm1: cubox-i-pwm1-front-led {
126 fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0>;
127 };
128
112 pinctrl_cubox_i_spdif: cubox-i-spdif { 129 pinctrl_cubox_i_spdif: cubox-i-spdif {
113 fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>; 130 fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
114 }; 131 };
@@ -117,6 +134,14 @@
117 fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>; 134 fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>;
118 }; 135 };
119 136
137 pinctrl_cubox_i_usbotg_id: cubox-i-usbotg-id {
138 /*
139 * The Cubox-i pulls this low, but as it's pointless
140 * leaving it as a pull-up, even if it is just 10uA.
141 */
142 fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
143 };
144
120 pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus { 145 pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus {
121 fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x4001b0b0>; 146 fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x4001b0b0>;
122 }; 147 };
@@ -153,6 +178,8 @@
153}; 178};
154 179
155&usbotg { 180&usbotg {
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_cubox_i_usbotg_id>;
156 vbus-supply = <&reg_usbotg_vbus>; 183 vbus-supply = <&reg_usbotg_vbus>;
157 status = "okay"; 184 status = "okay";
158}; 185};
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index 31665adcbf39..0db15af41cb1 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -161,7 +161,7 @@
161 status = "okay"; 161 status = "okay";
162 162
163 pmic: ltc3676@3c { 163 pmic: ltc3676@3c {
164 compatible = "ltc,ltc3676"; 164 compatible = "lltc,ltc3676";
165 reg = <0x3c>; 165 reg = <0x3c>;
166 166
167 regulators { 167 regulators {
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 367af3ec9435..744c8a2d81f6 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -220,7 +220,7 @@
220 }; 220 };
221 221
222 pmic: ltc3676@3c { 222 pmic: ltc3676@3c {
223 compatible = "ltc,ltc3676"; 223 compatible = "lltc,ltc3676";
224 reg = <0x3c>; 224 reg = <0x3c>;
225 225
226 regulators { 226 regulators {
@@ -288,7 +288,7 @@
288 codec: sgtl5000@0a { 288 codec: sgtl5000@0a {
289 compatible = "fsl,sgtl5000"; 289 compatible = "fsl,sgtl5000";
290 reg = <0x0a>; 290 reg = <0x0a>;
291 clocks = <&clks 169>; 291 clocks = <&clks 201>;
292 VDDA-supply = <&reg_1p8v>; 292 VDDA-supply = <&reg_1p8v>;
293 VDDIO-supply = <&reg_3p3v>; 293 VDDIO-supply = <&reg_3p3v>;
294 }; 294 };
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index c91b5a6c769b..adf150c1be90 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -234,7 +234,7 @@
234 }; 234 };
235 235
236 pmic: ltc3676@3c { 236 pmic: ltc3676@3c {
237 compatible = "ltc,ltc3676"; 237 compatible = "lltc,ltc3676";
238 reg = <0x3c>; 238 reg = <0x3c>;
239 239
240 regulators { 240 regulators {
diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
index d729d0b15f25..79eac6849d4c 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
@@ -10,14 +10,6 @@
10 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 10 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
11 >; 11 >;
12 }; 12 };
13
14 pinctrl_microsom_usbotg: microsom-usbotg {
15 /*
16 * Similar to pinctrl_usbotg_2, but we want it
17 * pulled down for a fixed host connection.
18 */
19 fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
20 };
21 }; 13 };
22}; 14};
23 15
@@ -26,8 +18,3 @@
26 pinctrl-0 = <&pinctrl_microsom_uart1>; 18 pinctrl-0 = <&pinctrl_microsom_uart1>;
27 status = "okay"; 19 status = "okay";
28}; 20};
29
30&usbotg {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_microsom_usbotg>;
33};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 2d4e5285f3f3..57d4abe03a94 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -686,7 +686,7 @@
686 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; 686 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
687 reg = <0x02188000 0x4000>; 687 reg = <0x02188000 0x4000>;
688 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; 688 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&clks IMX6SL_CLK_ENET_REF>, 689 clocks = <&clks IMX6SL_CLK_ENET>,
690 <&clks IMX6SL_CLK_ENET_REF>; 690 <&clks IMX6SL_CLK_ENET_REF>;
691 clock-names = "ipg", "ahb"; 691 clock-names = "ipg", "ahb";
692 status = "disabled"; 692 status = "disabled";
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index c5a1fc75c7a3..b2d9834bf458 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -105,7 +105,6 @@
105 compatible = "ethernet-phy-id0141.0cb0", 105 compatible = "ethernet-phy-id0141.0cb0",
106 "ethernet-phy-ieee802.3-c22"; 106 "ethernet-phy-ieee802.3-c22";
107 reg = <0>; 107 reg = <0>;
108 phy-connection-type = "rgmii-id";
109 }; 108 };
110 109
111 ethphy1: ethernet-phy@1 { 110 ethphy1: ethernet-phy@1 {
@@ -113,7 +112,6 @@
113 compatible = "ethernet-phy-id0141.0cb0", 112 compatible = "ethernet-phy-id0141.0cb0",
114 "ethernet-phy-ieee802.3-c22"; 113 "ethernet-phy-ieee802.3-c22";
115 reg = <1>; 114 reg = <1>;
116 phy-connection-type = "rgmii-id";
117 }; 115 };
118}; 116};
119 117
@@ -121,6 +119,7 @@
121 status = "okay"; 119 status = "okay";
122 ethernet0-port@0 { 120 ethernet0-port@0 {
123 phy-handle = <&ethphy0>; 121 phy-handle = <&ethphy0>;
122 phy-connection-type = "rgmii-id";
124 }; 123 };
125}; 124};
126 125
@@ -128,5 +127,6 @@
128 status = "okay"; 127 status = "okay";
129 ethernet1-port@0 { 128 ethernet1-port@0 {
130 phy-handle = <&ethphy1>; 129 phy-handle = <&ethphy1>;
130 phy-connection-type = "rgmii-id";
131 }; 131 };
132}; 132};
diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
deleted file mode 100644
index b27c6373ff4d..000000000000
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * Reference Device Tree Source for the Marzen board
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Simon Horman
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/dts-v1/;
13#include "r8a7779.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
17/ {
18 model = "marzen";
19 compatible = "renesas,marzen-reference", "renesas,r8a7779";
20
21 chosen {
22 bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on rw";
23 };
24
25 memory {
26 device_type = "memory";
27 reg = <0x60000000 0x40000000>;
28 };
29
30 fixedregulator3v3: fixedregulator@0 {
31 compatible = "regulator-fixed";
32 regulator-name = "fixed-3.3V";
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 regulator-boot-on;
36 regulator-always-on;
37 };
38
39 lan0@18000000 {
40 compatible = "smsc,lan9220", "smsc,lan9115";
41 reg = <0x18000000 0x100>;
42 pinctrl-0 = <&lan0_pins>;
43 pinctrl-names = "default";
44
45 phy-mode = "mii";
46 interrupt-parent = <&irqpin0>;
47 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
48 smsc,irq-push-pull;
49 reg-io-width = <4>;
50 vddvario-supply = <&fixedregulator3v3>;
51 vdd33a-supply = <&fixedregulator3v3>;
52 };
53
54 leds {
55 compatible = "gpio-leds";
56 led2 {
57 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
58 };
59 led3 {
60 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
61 };
62 led4 {
63 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
64 };
65 };
66};
67
68&irqpin0 {
69 status = "okay";
70};
71
72&pfc {
73 pinctrl-0 = <&scif2_pins &scif4_pins>;
74 pinctrl-names = "default";
75
76 lan0_pins: lan0 {
77 intc {
78 renesas,groups = "intc_irq1_b";
79 renesas,function = "intc";
80 };
81 lbsc {
82 renesas,groups = "lbsc_ex_cs0";
83 renesas,function = "lbsc";
84 };
85 };
86
87 scif2_pins: serial2 {
88 renesas,groups = "scif2_data_c";
89 renesas,function = "scif2";
90 };
91
92 scif4_pins: serial4 {
93 renesas,groups = "scif4_data";
94 renesas,function = "scif4";
95 };
96
97 sdhi0_pins: sd0 {
98 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
99 renesas,function = "sdhi0";
100 };
101
102 hspi0_pins: hspi0 {
103 renesas,groups = "hspi0";
104 renesas,function = "hspi0";
105 };
106};
107
108&sdhi0 {
109 pinctrl-0 = <&sdhi0_pins>;
110 pinctrl-names = "default";
111
112 vmmc-supply = <&fixedregulator3v3>;
113 bus-width = <4>;
114 status = "okay";
115};
116
117&hspi0 {
118 pinctrl-0 = <&hspi0_pins>;
119 pinctrl-names = "default";
120 status = "okay";
121};
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index a7af2c2371f2..20b176807848 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -11,17 +11,131 @@
11 11
12/dts-v1/; 12/dts-v1/;
13#include "r8a7779.dtsi" 13#include "r8a7779.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/interrupt-controller/irq.h>
14 16
15/ { 17/ {
16 model = "marzen"; 18 model = "marzen";
17 compatible = "renesas,marzen", "renesas,r8a7779"; 19 compatible = "renesas,marzen", "renesas,r8a7779";
18 20
21 aliases {
22 serial2 = &scif2;
23 serial4 = &scif4;
24 };
25
19 chosen { 26 chosen {
20 bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on"; 27 bootargs = "console=ttySC2,115200 ignore_loglevel root=/dev/nfs ip=on";
21 }; 28 };
22 29
23 memory { 30 memory {
24 device_type = "memory"; 31 device_type = "memory";
25 reg = <0x60000000 0x40000000>; 32 reg = <0x60000000 0x40000000>;
26 }; 33 };
34
35 fixedregulator3v3: fixedregulator@0 {
36 compatible = "regulator-fixed";
37 regulator-name = "fixed-3.3V";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 regulator-boot-on;
41 regulator-always-on;
42 };
43
44 lan0@18000000 {
45 compatible = "smsc,lan9220", "smsc,lan9115";
46 reg = <0x18000000 0x100>;
47 pinctrl-0 = <&lan0_pins>;
48 pinctrl-names = "default";
49
50 phy-mode = "mii";
51 interrupt-parent = <&irqpin0>;
52 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
53 smsc,irq-push-pull;
54 reg-io-width = <4>;
55 vddvario-supply = <&fixedregulator3v3>;
56 vdd33a-supply = <&fixedregulator3v3>;
57 };
58
59 leds {
60 compatible = "gpio-leds";
61 led2 {
62 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
63 };
64 led3 {
65 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
66 };
67 led4 {
68 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
69 };
70 };
71};
72
73&irqpin0 {
74 status = "okay";
75};
76
77&extal_clk {
78 clock-frequency = <31250000>;
79};
80
81&pfc {
82 lan0_pins: lan0 {
83 intc {
84 renesas,groups = "intc_irq1_b";
85 renesas,function = "intc";
86 };
87 lbsc {
88 renesas,groups = "lbsc_ex_cs0";
89 renesas,function = "lbsc";
90 };
91 };
92
93 scif2_pins: serial2 {
94 renesas,groups = "scif2_data_c";
95 renesas,function = "scif2";
96 };
97
98 scif4_pins: serial4 {
99 renesas,groups = "scif4_data";
100 renesas,function = "scif4";
101 };
102
103 sdhi0_pins: sd0 {
104 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
105 renesas,function = "sdhi0";
106 };
107
108 hspi0_pins: hspi0 {
109 renesas,groups = "hspi0";
110 renesas,function = "hspi0";
111 };
112};
113
114&scif2 {
115 pinctrl-0 = <&scif2_pins>;
116 pinctrl-names = "default";
117
118 status = "okay";
119};
120
121&scif4 {
122 pinctrl-0 = <&scif4_pins>;
123 pinctrl-names = "default";
124
125 status = "okay";
126};
127
128&sdhi0 {
129 pinctrl-0 = <&sdhi0_pins>;
130 pinctrl-names = "default";
131
132 vmmc-supply = <&fixedregulator3v3>;
133 bus-width = <4>;
134 status = "okay";
135};
136
137&hspi0 {
138 pinctrl-0 = <&hspi0_pins>;
139 pinctrl-names = "default";
140 status = "okay";
27}; 141};
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index b517c8e6b420..94e2fc836492 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -11,6 +11,7 @@
11 11
12/include/ "skeleton.dtsi" 12/include/ "skeleton.dtsi"
13 13
14#include <dt-bindings/clock/r8a7779-clock.h>
14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/irq.h>
15 16
16/ { 17/ {
@@ -25,21 +26,25 @@
25 device_type = "cpu"; 26 device_type = "cpu";
26 compatible = "arm,cortex-a9"; 27 compatible = "arm,cortex-a9";
27 reg = <0>; 28 reg = <0>;
29 clock-frequency = <1000000000>;
28 }; 30 };
29 cpu@1 { 31 cpu@1 {
30 device_type = "cpu"; 32 device_type = "cpu";
31 compatible = "arm,cortex-a9"; 33 compatible = "arm,cortex-a9";
32 reg = <1>; 34 reg = <1>;
35 clock-frequency = <1000000000>;
33 }; 36 };
34 cpu@2 { 37 cpu@2 {
35 device_type = "cpu"; 38 device_type = "cpu";
36 compatible = "arm,cortex-a9"; 39 compatible = "arm,cortex-a9";
37 reg = <2>; 40 reg = <2>;
41 clock-frequency = <1000000000>;
38 }; 42 };
39 cpu@3 { 43 cpu@3 {
40 device_type = "cpu"; 44 device_type = "cpu";
41 compatible = "arm,cortex-a9"; 45 compatible = "arm,cortex-a9";
42 reg = <3>; 46 reg = <3>;
47 clock-frequency = <1000000000>;
43 }; 48 };
44 }; 49 };
45 50
@@ -157,6 +162,7 @@
157 compatible = "renesas,i2c-r8a7779"; 162 compatible = "renesas,i2c-r8a7779";
158 reg = <0xffc70000 0x1000>; 163 reg = <0xffc70000 0x1000>;
159 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; 164 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
160 status = "disabled"; 166 status = "disabled";
161 }; 167 };
162 168
@@ -166,6 +172,7 @@
166 compatible = "renesas,i2c-r8a7779"; 172 compatible = "renesas,i2c-r8a7779";
167 reg = <0xffc71000 0x1000>; 173 reg = <0xffc71000 0x1000>;
168 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 174 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
169 status = "disabled"; 176 status = "disabled";
170 }; 177 };
171 178
@@ -175,6 +182,7 @@
175 compatible = "renesas,i2c-r8a7779"; 182 compatible = "renesas,i2c-r8a7779";
176 reg = <0xffc72000 0x1000>; 183 reg = <0xffc72000 0x1000>;
177 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 184 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
178 status = "disabled"; 186 status = "disabled";
179 }; 187 };
180 188
@@ -184,6 +192,67 @@
184 compatible = "renesas,i2c-r8a7779"; 192 compatible = "renesas,i2c-r8a7779";
185 reg = <0xffc73000 0x1000>; 193 reg = <0xffc73000 0x1000>;
186 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 194 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
196 status = "disabled";
197 };
198
199 scif0: serial@ffe40000 {
200 compatible = "renesas,scif-r8a7779", "renesas,scif";
201 reg = <0xffe40000 0x100>;
202 interrupt-parent = <&gic>;
203 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&cpg_clocks R8A7779_CLK_P>;
205 clock-names = "sci_ick";
206 status = "disabled";
207 };
208
209 scif1: serial@ffe41000 {
210 compatible = "renesas,scif-r8a7779", "renesas,scif";
211 reg = <0xffe41000 0x100>;
212 interrupt-parent = <&gic>;
213 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&cpg_clocks R8A7779_CLK_P>;
215 clock-names = "sci_ick";
216 status = "disabled";
217 };
218
219 scif2: serial@ffe42000 {
220 compatible = "renesas,scif-r8a7779", "renesas,scif";
221 reg = <0xffe42000 0x100>;
222 interrupt-parent = <&gic>;
223 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&cpg_clocks R8A7779_CLK_P>;
225 clock-names = "sci_ick";
226 status = "disabled";
227 };
228
229 scif3: serial@ffe43000 {
230 compatible = "renesas,scif-r8a7779", "renesas,scif";
231 reg = <0xffe43000 0x100>;
232 interrupt-parent = <&gic>;
233 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&cpg_clocks R8A7779_CLK_P>;
235 clock-names = "sci_ick";
236 status = "disabled";
237 };
238
239 scif4: serial@ffe44000 {
240 compatible = "renesas,scif-r8a7779", "renesas,scif";
241 reg = <0xffe44000 0x100>;
242 interrupt-parent = <&gic>;
243 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&cpg_clocks R8A7779_CLK_P>;
245 clock-names = "sci_ick";
246 status = "disabled";
247 };
248
249 scif5: serial@ffe45000 {
250 compatible = "renesas,scif-r8a7779", "renesas,scif";
251 reg = <0xffe45000 0x100>;
252 interrupt-parent = <&gic>;
253 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&cpg_clocks R8A7779_CLK_P>;
255 clock-names = "sci_ick";
187 status = "disabled"; 256 status = "disabled";
188 }; 257 };
189 258
@@ -201,12 +270,14 @@
201 compatible = "renesas,rcar-sata"; 270 compatible = "renesas,rcar-sata";
202 reg = <0xfc600000 0x2000>; 271 reg = <0xfc600000 0x2000>;
203 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 272 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
204 }; 274 };
205 275
206 sdhi0: sd@ffe4c000 { 276 sdhi0: sd@ffe4c000 {
207 compatible = "renesas,sdhi-r8a7779"; 277 compatible = "renesas,sdhi-r8a7779";
208 reg = <0xffe4c000 0x100>; 278 reg = <0xffe4c000 0x100>;
209 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; 279 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
210 cap-sd-highspeed; 281 cap-sd-highspeed;
211 cap-sdio-irq; 282 cap-sdio-irq;
212 status = "disabled"; 283 status = "disabled";
@@ -216,6 +287,7 @@
216 compatible = "renesas,sdhi-r8a7779"; 287 compatible = "renesas,sdhi-r8a7779";
217 reg = <0xffe4d000 0x100>; 288 reg = <0xffe4d000 0x100>;
218 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 289 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
219 cap-sd-highspeed; 291 cap-sd-highspeed;
220 cap-sdio-irq; 292 cap-sdio-irq;
221 status = "disabled"; 293 status = "disabled";
@@ -225,6 +297,7 @@
225 compatible = "renesas,sdhi-r8a7779"; 297 compatible = "renesas,sdhi-r8a7779";
226 reg = <0xffe4e000 0x100>; 298 reg = <0xffe4e000 0x100>;
227 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 299 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
228 cap-sd-highspeed; 301 cap-sd-highspeed;
229 cap-sdio-irq; 302 cap-sdio-irq;
230 status = "disabled"; 303 status = "disabled";
@@ -234,6 +307,7 @@
234 compatible = "renesas,sdhi-r8a7779"; 307 compatible = "renesas,sdhi-r8a7779";
235 reg = <0xffe4f000 0x100>; 308 reg = <0xffe4f000 0x100>;
236 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 309 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
237 cap-sd-highspeed; 311 cap-sd-highspeed;
238 cap-sdio-irq; 312 cap-sdio-irq;
239 status = "disabled"; 313 status = "disabled";
@@ -245,6 +319,7 @@
245 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 319 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
246 #address-cells = <1>; 320 #address-cells = <1>;
247 #size-cells = <0>; 321 #size-cells = <0>;
322 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
248 status = "disabled"; 323 status = "disabled";
249 }; 324 };
250 325
@@ -254,6 +329,7 @@
254 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 329 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
255 #address-cells = <1>; 330 #address-cells = <1>;
256 #size-cells = <0>; 331 #size-cells = <0>;
332 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
257 status = "disabled"; 333 status = "disabled";
258 }; 334 };
259 335
@@ -263,6 +339,150 @@
263 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 339 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
264 #address-cells = <1>; 340 #address-cells = <1>;
265 #size-cells = <0>; 341 #size-cells = <0>;
342 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
266 status = "disabled"; 343 status = "disabled";
267 }; 344 };
345
346 clocks {
347 #address-cells = <1>;
348 #size-cells = <1>;
349 ranges;
350
351 /* External root clock */
352 extal_clk: extal_clk {
353 compatible = "fixed-clock";
354 #clock-cells = <0>;
355 /* This value must be overriden by the board. */
356 clock-frequency = <0>;
357 clock-output-names = "extal";
358 };
359
360 /* Special CPG clocks */
361 cpg_clocks: clocks@ffc80000 {
362 compatible = "renesas,r8a7779-cpg-clocks";
363 reg = <0xffc80000 0x30>;
364 clocks = <&extal_clk>;
365 #clock-cells = <1>;
366 clock-output-names = "plla", "z", "zs", "s",
367 "s1", "p", "b", "out";
368 };
369
370 /* Fixed factor clocks */
371 i_clk: i_clk {
372 compatible = "fixed-factor-clock";
373 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
374 #clock-cells = <0>;
375 clock-div = <2>;
376 clock-mult = <1>;
377 clock-output-names = "i";
378 };
379 s3_clk: s3_clk {
380 compatible = "fixed-factor-clock";
381 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
382 #clock-cells = <0>;
383 clock-div = <8>;
384 clock-mult = <1>;
385 clock-output-names = "s3";
386 };
387 s4_clk: s4_clk {
388 compatible = "fixed-factor-clock";
389 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
390 #clock-cells = <0>;
391 clock-div = <16>;
392 clock-mult = <1>;
393 clock-output-names = "s4";
394 };
395 g_clk: g_clk {
396 compatible = "fixed-factor-clock";
397 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
398 #clock-cells = <0>;
399 clock-div = <24>;
400 clock-mult = <1>;
401 clock-output-names = "g";
402 };
403
404 /* Gate clocks */
405 mstp0_clks: clocks@ffc80030 {
406 compatible = "renesas,r8a7779-mstp-clocks",
407 "renesas,cpg-mstp-clocks";
408 reg = <0xffc80030 4>;
409 clocks = <&cpg_clocks R8A7779_CLK_S>,
410 <&cpg_clocks R8A7779_CLK_P>,
411 <&cpg_clocks R8A7779_CLK_P>,
412 <&cpg_clocks R8A7779_CLK_P>,
413 <&cpg_clocks R8A7779_CLK_S>,
414 <&cpg_clocks R8A7779_CLK_S>,
415 <&cpg_clocks R8A7779_CLK_S1>,
416 <&cpg_clocks R8A7779_CLK_S1>,
417 <&cpg_clocks R8A7779_CLK_S1>,
418 <&cpg_clocks R8A7779_CLK_S1>,
419 <&cpg_clocks R8A7779_CLK_S1>,
420 <&cpg_clocks R8A7779_CLK_S1>,
421 <&cpg_clocks R8A7779_CLK_P>,
422 <&cpg_clocks R8A7779_CLK_P>,
423 <&cpg_clocks R8A7779_CLK_P>,
424 <&cpg_clocks R8A7779_CLK_P>;
425 #clock-cells = <1>;
426 renesas,clock-indices = <
427 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
428 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
429 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
430 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
431 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
432 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
433 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
434 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
435 >;
436 clock-output-names =
437 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
438 "hscif0", "scif5", "scif4", "scif3", "scif2",
439 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
440 "i2c0";
441 };
442 mstp1_clks: clocks@ffc80034 {
443 compatible = "renesas,r8a7779-mstp-clocks",
444 "renesas,cpg-mstp-clocks";
445 reg = <0xffc80034 4>, <0xffc80044 4>;
446 clocks = <&cpg_clocks R8A7779_CLK_P>,
447 <&cpg_clocks R8A7779_CLK_P>,
448 <&cpg_clocks R8A7779_CLK_S>,
449 <&cpg_clocks R8A7779_CLK_S>,
450 <&cpg_clocks R8A7779_CLK_S>,
451 <&cpg_clocks R8A7779_CLK_S>,
452 <&cpg_clocks R8A7779_CLK_P>,
453 <&cpg_clocks R8A7779_CLK_P>,
454 <&cpg_clocks R8A7779_CLK_P>,
455 <&cpg_clocks R8A7779_CLK_S>;
456 #clock-cells = <1>;
457 renesas,clock-indices = <
458 R8A7779_CLK_USB01 R8A7779_CLK_USB2
459 R8A7779_CLK_DU R8A7779_CLK_VIN2
460 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
461 R8A7779_CLK_ETHER R8A7779_CLK_SATA
462 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
463 >;
464 clock-output-names =
465 "usb01", "usb2",
466 "du", "vin2",
467 "vin1", "vin0",
468 "ether", "sata",
469 "pcie", "vin3";
470 };
471 mstp3_clks: clocks@ffc8003c {
472 compatible = "renesas,r8a7779-mstp-clocks",
473 "renesas,cpg-mstp-clocks";
474 reg = <0xffc8003c 4>;
475 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
476 <&s4_clk>, <&s4_clk>;
477 #clock-cells = <1>;
478 renesas,clock-indices = <
479 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
480 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
481 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
482 >;
483 clock-output-names =
484 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
485 "mmc1", "mmc0";
486 };
487 };
268}; 488};
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index d6f254f302fe..a0f6f75fe3b5 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -169,8 +169,8 @@
169 169
170 pinctrl-names = "default"; 170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_mii0>; 171 pinctrl-0 = <&pinctrl_mii0>;
172 clock-names = "stmmaceth"; 172 clock-names = "stmmaceth", "sti-ethclk";
173 clocks = <&clk_s_a1_ls CLK_GMAC0_PHY>; 173 clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
174 }; 174 };
175 175
176 ethernet1: dwmac@fef08000 { 176 ethernet1: dwmac@fef08000 {
@@ -192,8 +192,8 @@
192 reset-names = "stmmaceth"; 192 reset-names = "stmmaceth";
193 pinctrl-names = "default"; 193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_mii1>; 194 pinctrl-0 = <&pinctrl_mii1>;
195 clock-names = "stmmaceth"; 195 clock-names = "stmmaceth", "sti-ethclk";
196 clocks = <&clk_s_a0_ls CLK_ETH1_PHY>; 196 clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
197 }; 197 };
198 198
199 rc: rc@fe518000 { 199 rc: rc@fe518000 {
diff --git a/arch/arm/boot/dts/stih416-b2020-revE.dts b/arch/arm/boot/dts/stih416-b2020e.dts
index ba0fa2caaf18..ba0fa2caaf18 100644
--- a/arch/arm/boot/dts/stih416-b2020-revE.dts
+++ b/arch/arm/boot/dts/stih416-b2020e.dts
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 06473c5d9ea9..84758d76d064 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -175,8 +175,8 @@
175 reset-names = "stmmaceth"; 175 reset-names = "stmmaceth";
176 pinctrl-names = "default"; 176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_mii0>; 177 pinctrl-0 = <&pinctrl_mii0>;
178 clock-names = "stmmaceth"; 178 clock-names = "stmmaceth", "sti-ethclk";
179 clocks = <&clk_s_a1_ls CLK_GMAC0_PHY>; 179 clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
180 }; 180 };
181 181
182 ethernet1: dwmac@fef08000 { 182 ethernet1: dwmac@fef08000 {
@@ -197,8 +197,8 @@
197 reset-names = "stmmaceth"; 197 reset-names = "stmmaceth";
198 pinctrl-names = "default"; 198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_mii1>; 199 pinctrl-0 = <&pinctrl_mii1>;
200 clock-names = "stmmaceth"; 200 clock-names = "stmmaceth", "sti-ethclk";
201 clocks = <&clk_s_a0_ls CLK_ETH1_PHY>; 201 clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
202 }; 202 };
203 203
204 rc: rc@fe518000 { 204 rc: rc@fe518000 {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 06:09:11 -0500