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-rw-r--r--arch/arm/boot/compressed/.gitignore2
-rw-r--r--arch/arm/boot/compressed/Makefile15
-rw-r--r--arch/arm/boot/compressed/decompress.c6
-rw-r--r--arch/arm/boot/compressed/head.S2
-rw-r--r--arch/arm/boot/compressed/piggy.xzkern.S6
-rw-r--r--arch/arm/boot/dts/am3517_mt_ventoux.dts27
-rw-r--r--arch/arm/boot/dts/at91sam9g20.dtsi131
-rw-r--r--arch/arm/boot/dts/at91sam9g25ek.dts49
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi151
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts118
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi264
-rw-r--r--arch/arm/boot/dts/at91sam9x5cm.dtsi74
-rw-r--r--arch/arm/boot/dts/db8500.dtsi275
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts26
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi413
-rw-r--r--arch/arm/boot/dts/highbank.dts8
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore.dts76
-rw-r--r--arch/arm/boot/dts/imx27.dtsi217
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts91
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts14
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts34
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi6
-rw-r--r--arch/arm/boot/dts/kirkwood-dreamplug.dts24
-rw-r--r--arch/arm/boot/dts/kirkwood.dtsi36
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts9
-rw-r--r--arch/arm/boot/dts/omap3-evm.dts20
-rw-r--r--arch/arm/boot/dts/omap3.dtsi35
-rw-r--r--arch/arm/boot/dts/omap4-panda.dts9
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts9
-rw-r--r--arch/arm/boot/dts/omap4.dtsi38
-rw-r--r--arch/arm/boot/dts/pxa168-aspenite.dts38
-rw-r--r--arch/arm/boot/dts/pxa168.dtsi98
-rw-r--r--arch/arm/boot/dts/snowball.dts139
-rw-r--r--arch/arm/boot/dts/spear600-evb.dts47
-rw-r--r--arch/arm/boot/dts/spear600.dtsi174
-rw-r--r--arch/arm/boot/dts/tegra-cardhu.dts34
-rw-r--r--arch/arm/boot/dts/tegra-harmony.dts45
-rw-r--r--arch/arm/boot/dts/tegra-paz00.dts57
-rw-r--r--arch/arm/boot/dts/tegra-seaboard.dts79
-rw-r--r--arch/arm/boot/dts/tegra-trimslice.dts12
-rw-r--r--arch/arm/boot/dts/tegra-ventana.dts42
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi50
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi61
-rw-r--r--arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi96
-rw-r--r--arch/arm/boot/dts/usb_a9g20.dts97
-rw-r--r--arch/arm/boot/dts/vexpress-v2m-rs1.dtsi201
-rw-r--r--arch/arm/boot/dts/vexpress-v2m.dtsi200
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts157
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca5s.dts162
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca9.dts192
50 files changed, 4081 insertions, 85 deletions
diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore
index e0936a148516..d0d441c429ae 100644
--- a/arch/arm/boot/compressed/.gitignore
+++ b/arch/arm/boot/compressed/.gitignore
@@ -1,8 +1,10 @@
1ashldi3.S
1font.c 2font.c
2lib1funcs.S 3lib1funcs.S
3piggy.gzip 4piggy.gzip
4piggy.lzo 5piggy.lzo
5piggy.lzma 6piggy.lzma
7piggy.xzkern
6vmlinux 8vmlinux
7vmlinux.lds 9vmlinux.lds
8 10
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index cf0a64ce4b83..bb267562e7ed 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -92,6 +92,7 @@ SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/
92suffix_$(CONFIG_KERNEL_GZIP) = gzip 92suffix_$(CONFIG_KERNEL_GZIP) = gzip
93suffix_$(CONFIG_KERNEL_LZO) = lzo 93suffix_$(CONFIG_KERNEL_LZO) = lzo
94suffix_$(CONFIG_KERNEL_LZMA) = lzma 94suffix_$(CONFIG_KERNEL_LZMA) = lzma
95suffix_$(CONFIG_KERNEL_XZ) = xzkern
95 96
96# Borrowed libfdt files for the ATAG compatibility mode 97# Borrowed libfdt files for the ATAG compatibility mode
97 98
@@ -112,10 +113,12 @@ endif
112 113
113targets := vmlinux vmlinux.lds \ 114targets := vmlinux vmlinux.lds \
114 piggy.$(suffix_y) piggy.$(suffix_y).o \ 115 piggy.$(suffix_y) piggy.$(suffix_y).o \
115 lib1funcs.o lib1funcs.S font.o font.c head.o misc.o $(OBJS) 116 lib1funcs.o lib1funcs.S ashldi3.o ashldi3.S \
117 font.o font.c head.o misc.o $(OBJS)
116 118
117# Make sure files are removed during clean 119# Make sure files are removed during clean
118extra-y += piggy.gzip piggy.lzo piggy.lzma lib1funcs.S $(libfdt) $(libfdt_hdrs) 120extra-y += piggy.gzip piggy.lzo piggy.lzma piggy.xzkern \
121 lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs)
119 122
120ifeq ($(CONFIG_FUNCTION_TRACER),y) 123ifeq ($(CONFIG_FUNCTION_TRACER),y)
121ORIG_CFLAGS := $(KBUILD_CFLAGS) 124ORIG_CFLAGS := $(KBUILD_CFLAGS)
@@ -151,6 +154,12 @@ lib1funcs = $(obj)/lib1funcs.o
151$(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S 154$(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S
152 $(call cmd,shipped) 155 $(call cmd,shipped)
153 156
157# For __aeabi_llsl
158ashldi3 = $(obj)/ashldi3.o
159
160$(obj)/ashldi3.S: $(srctree)/arch/$(SRCARCH)/lib/ashldi3.S
161 $(call cmd,shipped)
162
154# We need to prevent any GOTOFF relocs being used with references 163# We need to prevent any GOTOFF relocs being used with references
155# to symbols in the .bss section since we cannot relocate them 164# to symbols in the .bss section since we cannot relocate them
156# independently from the rest at run time. This can be achieved by 165# independently from the rest at run time. This can be achieved by
@@ -172,7 +181,7 @@ if [ $(words $(ZRELADDR)) -gt 1 -a "$(CONFIG_AUTO_ZRELADDR)" = "" ]; then \
172fi 181fi
173 182
174$(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \ 183$(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \
175 $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE 184 $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) $(ashldi3) FORCE
176 @$(check_for_multiple_zreladdr) 185 @$(check_for_multiple_zreladdr)
177 $(call if_changed,ld) 186 $(call if_changed,ld)
178 @$(check_for_bad_syms) 187 @$(check_for_bad_syms)
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index 07be5a2f8302..f41b38cafce8 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
@@ -44,6 +44,12 @@ extern void error(char *);
44#include "../../../../lib/decompress_unlzma.c" 44#include "../../../../lib/decompress_unlzma.c"
45#endif 45#endif
46 46
47#ifdef CONFIG_KERNEL_XZ
48#define memmove memmove
49#define memcpy memcpy
50#include "../../../../lib/decompress_unxz.c"
51#endif
52
47int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)) 53int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x))
48{ 54{
49 return decompress(input, len, NULL, NULL, output, NULL, error); 55 return decompress(input, len, NULL, NULL, output, NULL, error);
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index c5d60250d43d..5f6045f1766c 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -58,7 +58,7 @@
58 add \rb, \rb, #0x00010000 @ Ser1 58 add \rb, \rb, #0x00010000 @ Ser1
59#endif 59#endif
60 .endm 60 .endm
61#elif defined(CONFIG_ARCH_S3C2410) 61#elif defined(CONFIG_ARCH_S3C24XX)
62 .macro loadsp, rb, tmp 62 .macro loadsp, rb, tmp
63 mov \rb, #0x50000000 63 mov \rb, #0x50000000
64 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT 64 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
diff --git a/arch/arm/boot/compressed/piggy.xzkern.S b/arch/arm/boot/compressed/piggy.xzkern.S
new file mode 100644
index 000000000000..5703f300d027
--- /dev/null
+++ b/arch/arm/boot/compressed/piggy.xzkern.S
@@ -0,0 +1,6 @@
1 .section .piggydata,#alloc
2 .globl input_data
3input_data:
4 .incbin "arch/arm/boot/compressed/piggy.xzkern"
5 .globl input_data_end
6input_data_end:
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
new file mode 100644
index 000000000000..5eb26d7d9b4e
--- /dev/null
+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
@@ -0,0 +1,27 @@
1/*
2 * Copyright (C) 2011 Ilya Yanok, EmCraft Systems
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap3.dtsi"
11
12/ {
13 model = "TeeJet Mt.Ventoux";
14 compatible = "teejet,mt_ventoux", "ti,omap3";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 };
20
21 /* AM35xx doesn't have IVA */
22 soc {
23 iva {
24 status = "disabled";
25 };
26 };
27};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 07603b8c9503..92f36627e7f8 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -23,6 +23,11 @@
23 serial4 = &usart3; 23 serial4 = &usart3;
24 serial5 = &usart4; 24 serial5 = &usart4;
25 serial6 = &usart5; 25 serial6 = &usart5;
26 gpio0 = &pioA;
27 gpio1 = &pioB;
28 gpio2 = &pioC;
29 tcb0 = &tcb0;
30 tcb1 = &tcb1;
26 }; 31 };
27 cpus { 32 cpus {
28 cpu@0 { 33 cpu@0 {
@@ -47,24 +52,89 @@
47 ranges; 52 ranges;
48 53
49 aic: interrupt-controller@fffff000 { 54 aic: interrupt-controller@fffff000 {
50 #interrupt-cells = <1>; 55 #interrupt-cells = <2>;
51 compatible = "atmel,at91rm9200-aic"; 56 compatible = "atmel,at91rm9200-aic";
52 interrupt-controller; 57 interrupt-controller;
53 interrupt-parent; 58 interrupt-parent;
54 reg = <0xfffff000 0x200>; 59 reg = <0xfffff000 0x200>;
55 }; 60 };
56 61
62 ramc0: ramc@ffffea00 {
63 compatible = "atmel,at91sam9260-sdramc";
64 reg = <0xffffea00 0x200>;
65 };
66
67 pmc: pmc@fffffc00 {
68 compatible = "atmel,at91rm9200-pmc";
69 reg = <0xfffffc00 0x100>;
70 };
71
72 rstc@fffffd00 {
73 compatible = "atmel,at91sam9260-rstc";
74 reg = <0xfffffd00 0x10>;
75 };
76
77 shdwc@fffffd10 {
78 compatible = "atmel,at91sam9260-shdwc";
79 reg = <0xfffffd10 0x10>;
80 };
81
82 pit: timer@fffffd30 {
83 compatible = "atmel,at91sam9260-pit";
84 reg = <0xfffffd30 0xf>;
85 interrupts = <1 4>;
86 };
87
88 tcb0: timer@fffa0000 {
89 compatible = "atmel,at91rm9200-tcb";
90 reg = <0xfffa0000 0x100>;
91 interrupts = <17 4 18 4 19 4>;
92 };
93
94 tcb1: timer@fffdc000 {
95 compatible = "atmel,at91rm9200-tcb";
96 reg = <0xfffdc000 0x100>;
97 interrupts = <26 4 27 4 28 4>;
98 };
99
100 pioA: gpio@fffff400 {
101 compatible = "atmel,at91rm9200-gpio";
102 reg = <0xfffff400 0x100>;
103 interrupts = <2 4>;
104 #gpio-cells = <2>;
105 gpio-controller;
106 interrupt-controller;
107 };
108
109 pioB: gpio@fffff600 {
110 compatible = "atmel,at91rm9200-gpio";
111 reg = <0xfffff600 0x100>;
112 interrupts = <3 4>;
113 #gpio-cells = <2>;
114 gpio-controller;
115 interrupt-controller;
116 };
117
118 pioC: gpio@fffff800 {
119 compatible = "atmel,at91rm9200-gpio";
120 reg = <0xfffff800 0x100>;
121 interrupts = <4 4>;
122 #gpio-cells = <2>;
123 gpio-controller;
124 interrupt-controller;
125 };
126
57 dbgu: serial@fffff200 { 127 dbgu: serial@fffff200 {
58 compatible = "atmel,at91sam9260-usart"; 128 compatible = "atmel,at91sam9260-usart";
59 reg = <0xfffff200 0x200>; 129 reg = <0xfffff200 0x200>;
60 interrupts = <1>; 130 interrupts = <1 4>;
61 status = "disabled"; 131 status = "disabled";
62 }; 132 };
63 133
64 usart0: serial@fffb0000 { 134 usart0: serial@fffb0000 {
65 compatible = "atmel,at91sam9260-usart"; 135 compatible = "atmel,at91sam9260-usart";
66 reg = <0xfffb0000 0x200>; 136 reg = <0xfffb0000 0x200>;
67 interrupts = <6>; 137 interrupts = <6 4>;
68 atmel,use-dma-rx; 138 atmel,use-dma-rx;
69 atmel,use-dma-tx; 139 atmel,use-dma-tx;
70 status = "disabled"; 140 status = "disabled";
@@ -73,7 +143,7 @@
73 usart1: serial@fffb4000 { 143 usart1: serial@fffb4000 {
74 compatible = "atmel,at91sam9260-usart"; 144 compatible = "atmel,at91sam9260-usart";
75 reg = <0xfffb4000 0x200>; 145 reg = <0xfffb4000 0x200>;
76 interrupts = <7>; 146 interrupts = <7 4>;
77 atmel,use-dma-rx; 147 atmel,use-dma-rx;
78 atmel,use-dma-tx; 148 atmel,use-dma-tx;
79 status = "disabled"; 149 status = "disabled";
@@ -82,7 +152,7 @@
82 usart2: serial@fffb8000 { 152 usart2: serial@fffb8000 {
83 compatible = "atmel,at91sam9260-usart"; 153 compatible = "atmel,at91sam9260-usart";
84 reg = <0xfffb8000 0x200>; 154 reg = <0xfffb8000 0x200>;
85 interrupts = <8>; 155 interrupts = <8 4>;
86 atmel,use-dma-rx; 156 atmel,use-dma-rx;
87 atmel,use-dma-tx; 157 atmel,use-dma-tx;
88 status = "disabled"; 158 status = "disabled";
@@ -91,7 +161,7 @@
91 usart3: serial@fffd0000 { 161 usart3: serial@fffd0000 {
92 compatible = "atmel,at91sam9260-usart"; 162 compatible = "atmel,at91sam9260-usart";
93 reg = <0xfffd0000 0x200>; 163 reg = <0xfffd0000 0x200>;
94 interrupts = <23>; 164 interrupts = <23 4>;
95 atmel,use-dma-rx; 165 atmel,use-dma-rx;
96 atmel,use-dma-tx; 166 atmel,use-dma-tx;
97 status = "disabled"; 167 status = "disabled";
@@ -100,7 +170,7 @@
100 usart4: serial@fffd4000 { 170 usart4: serial@fffd4000 {
101 compatible = "atmel,at91sam9260-usart"; 171 compatible = "atmel,at91sam9260-usart";
102 reg = <0xfffd4000 0x200>; 172 reg = <0xfffd4000 0x200>;
103 interrupts = <24>; 173 interrupts = <24 4>;
104 atmel,use-dma-rx; 174 atmel,use-dma-rx;
105 atmel,use-dma-tx; 175 atmel,use-dma-tx;
106 status = "disabled"; 176 status = "disabled";
@@ -109,7 +179,7 @@
109 usart5: serial@fffd8000 { 179 usart5: serial@fffd8000 {
110 compatible = "atmel,at91sam9260-usart"; 180 compatible = "atmel,at91sam9260-usart";
111 reg = <0xfffd8000 0x200>; 181 reg = <0xfffd8000 0x200>;
112 interrupts = <25>; 182 interrupts = <25 4>;
113 atmel,use-dma-rx; 183 atmel,use-dma-rx;
114 atmel,use-dma-tx; 184 atmel,use-dma-tx;
115 status = "disabled"; 185 status = "disabled";
@@ -118,9 +188,52 @@
118 macb0: ethernet@fffc4000 { 188 macb0: ethernet@fffc4000 {
119 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 189 compatible = "cdns,at32ap7000-macb", "cdns,macb";
120 reg = <0xfffc4000 0x100>; 190 reg = <0xfffc4000 0x100>;
121 interrupts = <21>; 191 interrupts = <21 4>;
192 status = "disabled";
193 };
194
195 usb1: gadget@fffa4000 {
196 compatible = "atmel,at91rm9200-udc";
197 reg = <0xfffa4000 0x4000>;
198 interrupts = <10 4>;
122 status = "disabled"; 199 status = "disabled";
123 }; 200 };
124 }; 201 };
202
203 nand0: nand@40000000 {
204 compatible = "atmel,at91rm9200-nand";
205 #address-cells = <1>;
206 #size-cells = <1>;
207 reg = <0x40000000 0x10000000
208 0xffffe800 0x200
209 >;
210 atmel,nand-addr-offset = <21>;
211 atmel,nand-cmd-offset = <22>;
212 gpios = <&pioC 13 0
213 &pioC 14 0
214 0
215 >;
216 status = "disabled";
217 };
218
219 usb0: ohci@00500000 {
220 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
221 reg = <0x00500000 0x100000>;
222 interrupts = <20 4>;
223 status = "disabled";
224 };
225 };
226
227 i2c@0 {
228 compatible = "i2c-gpio";
229 gpios = <&pioA 23 0 /* sda */
230 &pioA 24 0 /* scl */
231 >;
232 i2c-gpio,sda-open-drain;
233 i2c-gpio,scl-open-drain;
234 i2c-gpio,delay-us = <2>; /* ~100 kHz */
235 #address-cells = <1>;
236 #size-cells = <0>;
237 status = "disabled";
125 }; 238 };
126}; 239};
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
new file mode 100644
index 000000000000..ac0dc0031dda
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -0,0 +1,49 @@
1/*
2 * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9x5.dtsi"
11/include/ "at91sam9x5cm.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16
17 chosen {
18 bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
19 };
20
21 ahb {
22 apb {
23 dbgu: serial@fffff200 {
24 status = "okay";
25 };
26
27 usart0: serial@f801c000 {
28 status = "okay";
29 };
30
31 macb0: ethernet@f802c000 {
32 phy-mode = "rmii";
33 status = "okay";
34 };
35 };
36
37 usb0: ohci@00600000 {
38 status = "okay";
39 num-ports = <2>;
40 atmel,vbus-gpio = <&pioD 19 0
41 &pioD 20 0
42 >;
43 };
44
45 usb1: ehci@00700000 {
46 status = "okay";
47 };
48 };
49};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index fffa005300a4..3d0c32fb218f 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -22,6 +22,13 @@
22 serial2 = &usart1; 22 serial2 = &usart1;
23 serial3 = &usart2; 23 serial3 = &usart2;
24 serial4 = &usart3; 24 serial4 = &usart3;
25 gpio0 = &pioA;
26 gpio1 = &pioB;
27 gpio2 = &pioC;
28 gpio3 = &pioD;
29 gpio4 = &pioE;
30 tcb0 = &tcb0;
31 tcb1 = &tcb1;
25 }; 32 };
26 cpus { 33 cpus {
27 cpu@0 { 34 cpu@0 {
@@ -46,30 +53,115 @@
46 ranges; 53 ranges;
47 54
48 aic: interrupt-controller@fffff000 { 55 aic: interrupt-controller@fffff000 {
49 #interrupt-cells = <1>; 56 #interrupt-cells = <2>;
50 compatible = "atmel,at91rm9200-aic"; 57 compatible = "atmel,at91rm9200-aic";
51 interrupt-controller; 58 interrupt-controller;
52 interrupt-parent; 59 interrupt-parent;
53 reg = <0xfffff000 0x200>; 60 reg = <0xfffff000 0x200>;
54 }; 61 };
55 62
63 ramc0: ramc@ffffe400 {
64 compatible = "atmel,at91sam9g45-ddramc";
65 reg = <0xffffe400 0x200
66 0xffffe600 0x200>;
67 };
68
69 pmc: pmc@fffffc00 {
70 compatible = "atmel,at91rm9200-pmc";
71 reg = <0xfffffc00 0x100>;
72 };
73
74 rstc@fffffd00 {
75 compatible = "atmel,at91sam9g45-rstc";
76 reg = <0xfffffd00 0x10>;
77 };
78
79 pit: timer@fffffd30 {
80 compatible = "atmel,at91sam9260-pit";
81 reg = <0xfffffd30 0xf>;
82 interrupts = <1 4>;
83 };
84
85
86 shdwc@fffffd10 {
87 compatible = "atmel,at91sam9rl-shdwc";
88 reg = <0xfffffd10 0x10>;
89 };
90
91 tcb0: timer@fff7c000 {
92 compatible = "atmel,at91rm9200-tcb";
93 reg = <0xfff7c000 0x100>;
94 interrupts = <18 4>;
95 };
96
97 tcb1: timer@fffd4000 {
98 compatible = "atmel,at91rm9200-tcb";
99 reg = <0xfffd4000 0x100>;
100 interrupts = <18 4>;
101 };
102
56 dma: dma-controller@ffffec00 { 103 dma: dma-controller@ffffec00 {
57 compatible = "atmel,at91sam9g45-dma"; 104 compatible = "atmel,at91sam9g45-dma";
58 reg = <0xffffec00 0x200>; 105 reg = <0xffffec00 0x200>;
59 interrupts = <21>; 106 interrupts = <21 4>;
107 };
108
109 pioA: gpio@fffff200 {
110 compatible = "atmel,at91rm9200-gpio";
111 reg = <0xfffff200 0x100>;
112 interrupts = <2 4>;
113 #gpio-cells = <2>;
114 gpio-controller;
115 interrupt-controller;
116 };
117
118 pioB: gpio@fffff400 {
119 compatible = "atmel,at91rm9200-gpio";
120 reg = <0xfffff400 0x100>;
121 interrupts = <3 4>;
122 #gpio-cells = <2>;
123 gpio-controller;
124 interrupt-controller;
125 };
126
127 pioC: gpio@fffff600 {
128 compatible = "atmel,at91rm9200-gpio";
129 reg = <0xfffff600 0x100>;
130 interrupts = <4 4>;
131 #gpio-cells = <2>;
132 gpio-controller;
133 interrupt-controller;
134 };
135
136 pioD: gpio@fffff800 {
137 compatible = "atmel,at91rm9200-gpio";
138 reg = <0xfffff800 0x100>;
139 interrupts = <5 4>;
140 #gpio-cells = <2>;
141 gpio-controller;
142 interrupt-controller;
143 };
144
145 pioE: gpio@fffffa00 {
146 compatible = "atmel,at91rm9200-gpio";
147 reg = <0xfffffa00 0x100>;
148 interrupts = <5 4>;
149 #gpio-cells = <2>;
150 gpio-controller;
151 interrupt-controller;
60 }; 152 };
61 153
62 dbgu: serial@ffffee00 { 154 dbgu: serial@ffffee00 {
63 compatible = "atmel,at91sam9260-usart"; 155 compatible = "atmel,at91sam9260-usart";
64 reg = <0xffffee00 0x200>; 156 reg = <0xffffee00 0x200>;
65 interrupts = <1>; 157 interrupts = <1 4>;
66 status = "disabled"; 158 status = "disabled";
67 }; 159 };
68 160
69 usart0: serial@fff8c000 { 161 usart0: serial@fff8c000 {
70 compatible = "atmel,at91sam9260-usart"; 162 compatible = "atmel,at91sam9260-usart";
71 reg = <0xfff8c000 0x200>; 163 reg = <0xfff8c000 0x200>;
72 interrupts = <7>; 164 interrupts = <7 4>;
73 atmel,use-dma-rx; 165 atmel,use-dma-rx;
74 atmel,use-dma-tx; 166 atmel,use-dma-tx;
75 status = "disabled"; 167 status = "disabled";
@@ -78,7 +170,7 @@
78 usart1: serial@fff90000 { 170 usart1: serial@fff90000 {
79 compatible = "atmel,at91sam9260-usart"; 171 compatible = "atmel,at91sam9260-usart";
80 reg = <0xfff90000 0x200>; 172 reg = <0xfff90000 0x200>;
81 interrupts = <8>; 173 interrupts = <8 4>;
82 atmel,use-dma-rx; 174 atmel,use-dma-rx;
83 atmel,use-dma-tx; 175 atmel,use-dma-tx;
84 status = "disabled"; 176 status = "disabled";
@@ -87,7 +179,7 @@
87 usart2: serial@fff94000 { 179 usart2: serial@fff94000 {
88 compatible = "atmel,at91sam9260-usart"; 180 compatible = "atmel,at91sam9260-usart";
89 reg = <0xfff94000 0x200>; 181 reg = <0xfff94000 0x200>;
90 interrupts = <9>; 182 interrupts = <9 4>;
91 atmel,use-dma-rx; 183 atmel,use-dma-rx;
92 atmel,use-dma-tx; 184 atmel,use-dma-tx;
93 status = "disabled"; 185 status = "disabled";
@@ -96,7 +188,7 @@
96 usart3: serial@fff98000 { 188 usart3: serial@fff98000 {
97 compatible = "atmel,at91sam9260-usart"; 189 compatible = "atmel,at91sam9260-usart";
98 reg = <0xfff98000 0x200>; 190 reg = <0xfff98000 0x200>;
99 interrupts = <10>; 191 interrupts = <10 4>;
100 atmel,use-dma-rx; 192 atmel,use-dma-rx;
101 atmel,use-dma-tx; 193 atmel,use-dma-tx;
102 status = "disabled"; 194 status = "disabled";
@@ -105,9 +197,52 @@
105 macb0: ethernet@fffbc000 { 197 macb0: ethernet@fffbc000 {
106 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 198 compatible = "cdns,at32ap7000-macb", "cdns,macb";
107 reg = <0xfffbc000 0x100>; 199 reg = <0xfffbc000 0x100>;
108 interrupts = <25>; 200 interrupts = <25 4>;
109 status = "disabled"; 201 status = "disabled";
110 }; 202 };
111 }; 203 };
204
205 nand0: nand@40000000 {
206 compatible = "atmel,at91rm9200-nand";
207 #address-cells = <1>;
208 #size-cells = <1>;
209 reg = <0x40000000 0x10000000
210 0xffffe200 0x200
211 >;
212 atmel,nand-addr-offset = <21>;
213 atmel,nand-cmd-offset = <22>;
214 gpios = <&pioC 8 0
215 &pioC 14 0
216 0
217 >;
218 status = "disabled";
219 };
220
221 usb0: ohci@00700000 {
222 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
223 reg = <0x00700000 0x100000>;
224 interrupts = <22 4>;
225 status = "disabled";
226 };
227
228 usb1: ehci@00800000 {
229 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
230 reg = <0x00800000 0x100000>;
231 interrupts = <22 4>;
232 status = "disabled";
233 };
234 };
235
236 i2c@0 {
237 compatible = "i2c-gpio";
238 gpios = <&pioA 20 0 /* sda */
239 &pioA 21 0 /* scl */
240 >;
241 i2c-gpio,sda-open-drain;
242 i2c-gpio,scl-open-drain;
243 i2c-gpio,delay-us = <5>; /* ~100 kHz */
244 #address-cells = <1>;
245 #size-cells = <0>;
246 status = "disabled";
112 }; 247 };
113}; 248};
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a387e7704ce1..c4c8ae4123d5 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -14,13 +14,24 @@
14 compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9"; 14 compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
15 15
16 chosen { 16 chosen {
17 bootargs = "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:4M(bootstrap/uboot/kernel)ro,60M(rootfs),-(data) root=/dev/mtdblock1 rw rootfstype=jffs2"; 17 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2";
18 }; 18 };
19 19
20 memory@70000000 { 20 memory@70000000 {
21 reg = <0x70000000 0x4000000>; 21 reg = <0x70000000 0x4000000>;
22 }; 22 };
23 23
24 clocks {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges;
28
29 main_clock: clock@0 {
30 compatible = "atmel,osc", "fixed-clock";
31 clock-frequency = <12000000>;
32 };
33 };
34
24 ahb { 35 ahb {
25 apb { 36 apb {
26 dbgu: serial@ffffee00 { 37 dbgu: serial@ffffee00 {
@@ -36,5 +47,110 @@
36 status = "okay"; 47 status = "okay";
37 }; 48 };
38 }; 49 };
50
51 nand0: nand@40000000 {
52 nand-bus-width = <8>;
53 nand-ecc-mode = "soft";
54 nand-on-flash-bbt;
55 status = "okay";
56
57 boot@0 {
58 label = "bootstrap/uboot/kernel";
59 reg = <0x0 0x400000>;
60 };
61
62 rootfs@400000 {
63 label = "rootfs";
64 reg = <0x400000 0x3C00000>;
65 };
66
67 data@4000000 {
68 label = "data";
69 reg = <0x4000000 0xC000000>;
70 };
71 };
72
73 usb0: ohci@00700000 {
74 status = "okay";
75 num-ports = <2>;
76 atmel,vbus-gpio = <&pioD 1 0
77 &pioD 3 0>;
78 };
79
80 usb1: ehci@00800000 {
81 status = "okay";
82 };
83 };
84
85 leds {
86 compatible = "gpio-leds";
87
88 d8 {
89 label = "d8";
90 gpios = <&pioD 30 0>;
91 linux,default-trigger = "heartbeat";
92 };
93
94 d6 {
95 label = "d6";
96 gpios = <&pioD 0 1>;
97 linux,default-trigger = "nand-disk";
98 };
99
100 d7 {
101 label = "d7";
102 gpios = <&pioD 31 1>;
103 linux,default-trigger = "mmc0";
104 };
105 };
106
107 gpio_keys {
108 compatible = "gpio-keys";
109 #address-cells = <1>;
110 #size-cells = <0>;
111
112 left_click {
113 label = "left_click";
114 gpios = <&pioB 6 1>;
115 linux,code = <272>;
116 gpio-key,wakeup;
117 };
118
119 right_click {
120 label = "right_click";
121 gpios = <&pioB 7 1>;
122 linux,code = <273>;
123 gpio-key,wakeup;
124 };
125
126 left {
127 label = "Joystick Left";
128 gpios = <&pioB 14 1>;
129 linux,code = <105>;
130 };
131
132 right {
133 label = "Joystick Right";
134 gpios = <&pioB 15 1>;
135 linux,code = <106>;
136 };
137
138 up {
139 label = "Joystick Up";
140 gpios = <&pioB 16 1>;
141 linux,code = <103>;
142 };
143
144 down {
145 label = "Joystick Down";
146 gpios = <&pioB 17 1>;
147 linux,code = <108>;
148 };
149
150 enter {
151 label = "Joystick Press";
152 gpios = <&pioB 18 1>;
153 linux,code = <28>;
154 };
39 }; 155 };
40}; 156};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
new file mode 100644
index 000000000000..c111001f254e
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -0,0 +1,264 @@
1/*
2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
3 * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
4 * AT91SAM9X25, AT91SAM9X35 SoC
5 *
6 * Copyright (C) 2012 Atmel,
7 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 model = "Atmel AT91SAM9x5 family SoC";
16 compatible = "atmel,at91sam9x5";
17 interrupt-parent = <&aic>;
18
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 gpio0 = &pioA;
25 gpio1 = &pioB;
26 gpio2 = &pioC;
27 gpio3 = &pioD;
28 tcb0 = &tcb0;
29 tcb1 = &tcb1;
30 };
31 cpus {
32 cpu@0 {
33 compatible = "arm,arm926ejs";
34 };
35 };
36
37 memory@20000000 {
38 reg = <0x20000000 0x10000000>;
39 };
40
41 ahb {
42 compatible = "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
45 ranges;
46
47 apb {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 ranges;
52
53 aic: interrupt-controller@fffff000 {
54 #interrupt-cells = <2>;
55 compatible = "atmel,at91rm9200-aic";
56 interrupt-controller;
57 interrupt-parent;
58 reg = <0xfffff000 0x200>;
59 };
60
61 ramc0: ramc@ffffe800 {
62 compatible = "atmel,at91sam9g45-ddramc";
63 reg = <0xffffe800 0x200>;
64 };
65
66 pmc: pmc@fffffc00 {
67 compatible = "atmel,at91rm9200-pmc";
68 reg = <0xfffffc00 0x100>;
69 };
70
71 rstc@fffffe00 {
72 compatible = "atmel,at91sam9g45-rstc";
73 reg = <0xfffffe00 0x10>;
74 };
75
76 shdwc@fffffe10 {
77 compatible = "atmel,at91sam9x5-shdwc";
78 reg = <0xfffffe10 0x10>;
79 };
80
81 pit: timer@fffffe30 {
82 compatible = "atmel,at91sam9260-pit";
83 reg = <0xfffffe30 0xf>;
84 interrupts = <1 4>;
85 };
86
87 tcb0: timer@f8008000 {
88 compatible = "atmel,at91sam9x5-tcb";
89 reg = <0xf8008000 0x100>;
90 interrupts = <17 4>;
91 };
92
93 tcb1: timer@f800c000 {
94 compatible = "atmel,at91sam9x5-tcb";
95 reg = <0xf800c000 0x100>;
96 interrupts = <17 4>;
97 };
98
99 dma0: dma-controller@ffffec00 {
100 compatible = "atmel,at91sam9g45-dma";
101 reg = <0xffffec00 0x200>;
102 interrupts = <20 4>;
103 };
104
105 dma1: dma-controller@ffffee00 {
106 compatible = "atmel,at91sam9g45-dma";
107 reg = <0xffffee00 0x200>;
108 interrupts = <21 4>;
109 };
110
111 pioA: gpio@fffff400 {
112 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
113 reg = <0xfffff400 0x100>;
114 interrupts = <2 4>;
115 #gpio-cells = <2>;
116 gpio-controller;
117 interrupt-controller;
118 };
119
120 pioB: gpio@fffff600 {
121 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
122 reg = <0xfffff600 0x100>;
123 interrupts = <2 4>;
124 #gpio-cells = <2>;
125 gpio-controller;
126 interrupt-controller;
127 };
128
129 pioC: gpio@fffff800 {
130 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
131 reg = <0xfffff800 0x100>;
132 interrupts = <3 4>;
133 #gpio-cells = <2>;
134 gpio-controller;
135 interrupt-controller;
136 };
137
138 pioD: gpio@fffffa00 {
139 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
140 reg = <0xfffffa00 0x100>;
141 interrupts = <3 4>;
142 #gpio-cells = <2>;
143 gpio-controller;
144 interrupt-controller;
145 };
146
147 dbgu: serial@fffff200 {
148 compatible = "atmel,at91sam9260-usart";
149 reg = <0xfffff200 0x200>;
150 interrupts = <1 4>;
151 status = "disabled";
152 };
153
154 usart0: serial@f801c000 {
155 compatible = "atmel,at91sam9260-usart";
156 reg = <0xf801c000 0x200>;
157 interrupts = <5 4>;
158 atmel,use-dma-rx;
159 atmel,use-dma-tx;
160 status = "disabled";
161 };
162
163 usart1: serial@f8020000 {
164 compatible = "atmel,at91sam9260-usart";
165 reg = <0xf8020000 0x200>;
166 interrupts = <6 4>;
167 atmel,use-dma-rx;
168 atmel,use-dma-tx;
169 status = "disabled";
170 };
171
172 usart2: serial@f8024000 {
173 compatible = "atmel,at91sam9260-usart";
174 reg = <0xf8024000 0x200>;
175 interrupts = <7 4>;
176 atmel,use-dma-rx;
177 atmel,use-dma-tx;
178 status = "disabled";
179 };
180
181 macb0: ethernet@f802c000 {
182 compatible = "cdns,at32ap7000-macb", "cdns,macb";
183 reg = <0xf802c000 0x100>;
184 interrupts = <24 4>;
185 status = "disabled";
186 };
187
188 macb1: ethernet@f8030000 {
189 compatible = "cdns,at32ap7000-macb", "cdns,macb";
190 reg = <0xf8030000 0x100>;
191 interrupts = <27 4>;
192 status = "disabled";
193 };
194 };
195
196 nand0: nand@40000000 {
197 compatible = "atmel,at91rm9200-nand";
198 #address-cells = <1>;
199 #size-cells = <1>;
200 reg = <0x40000000 0x10000000
201 >;
202 atmel,nand-addr-offset = <21>;
203 atmel,nand-cmd-offset = <22>;
204 gpios = <&pioC 8 0
205 &pioC 14 0
206 0
207 >;
208 status = "disabled";
209 };
210
211 usb0: ohci@00600000 {
212 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
213 reg = <0x00600000 0x100000>;
214 interrupts = <22 4>;
215 status = "disabled";
216 };
217
218 usb1: ehci@00700000 {
219 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
220 reg = <0x00700000 0x100000>;
221 interrupts = <22 4>;
222 status = "disabled";
223 };
224 };
225
226 i2c@0 {
227 compatible = "i2c-gpio";
228 gpios = <&pioA 30 0 /* sda */
229 &pioA 31 0 /* scl */
230 >;
231 i2c-gpio,sda-open-drain;
232 i2c-gpio,scl-open-drain;
233 i2c-gpio,delay-us = <2>; /* ~100 kHz */
234 #address-cells = <1>;
235 #size-cells = <0>;
236 status = "disabled";
237 };
238
239 i2c@1 {
240 compatible = "i2c-gpio";
241 gpios = <&pioC 0 0 /* sda */
242 &pioC 1 0 /* scl */
243 >;
244 i2c-gpio,sda-open-drain;
245 i2c-gpio,scl-open-drain;
246 i2c-gpio,delay-us = <2>; /* ~100 kHz */
247 #address-cells = <1>;
248 #size-cells = <0>;
249 status = "disabled";
250 };
251
252 i2c@2 {
253 compatible = "i2c-gpio";
254 gpios = <&pioB 4 0 /* sda */
255 &pioB 5 0 /* scl */
256 >;
257 i2c-gpio,sda-open-drain;
258 i2c-gpio,scl-open-drain;
259 i2c-gpio,delay-us = <2>; /* ~100 kHz */
260 #address-cells = <1>;
261 #size-cells = <0>;
262 status = "disabled";
263 };
264};
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
new file mode 100644
index 000000000000..67936f83c694
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -0,0 +1,74 @@
1/*
2 * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/ {
11 memory@20000000 {
12 reg = <0x20000000 0x8000000>;
13 };
14
15 clocks {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges;
19
20 main_clock: clock@0 {
21 compatible = "atmel,osc", "fixed-clock";
22 clock-frequency = <12000000>;
23 };
24 };
25
26 ahb {
27 nand0: nand@40000000 {
28 nand-bus-width = <8>;
29 nand-ecc-mode = "soft";
30 nand-on-flash-bbt;
31 status = "okay";
32
33 at91bootstrap@0 {
34 label = "at91bootstrap";
35 reg = <0x0 0x40000>;
36 };
37
38 uboot@40000 {
39 label = "u-boot";
40 reg = <0x40000 0x80000>;
41 };
42
43 ubootenv@c0000 {
44 label = "U-Boot Env";
45 reg = <0xc0000 0x140000>;
46 };
47
48 kernel@200000 {
49 label = "kernel";
50 reg = <0x200000 0x600000>;
51 };
52
53 rootfs@800000 {
54 label = "rootfs";
55 reg = <0x800000 0x1f800000>;
56 };
57 };
58 };
59
60 leds {
61 compatible = "gpio-leds";
62
63 pb18 {
64 label = "pb18";
65 gpios = <&pioB 18 1>;
66 linux,default-trigger = "heartbeat";
67 };
68
69 pd21 {
70 label = "pd21";
71 gpios = <&pioD 21 0>;
72 };
73 };
74};
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
new file mode 100644
index 000000000000..d73dce645667
--- /dev/null
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -0,0 +1,275 @@
1/*
2 * Copyright 2012 Linaro Ltd
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 soc-u9500 {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 compatible = "stericsson,db8500";
19 interrupt-parent = <&intc>;
20 ranges;
21
22 intc: interrupt-controller@a0411000 {
23 compatible = "arm,cortex-a9-gic";
24 #interrupt-cells = <3>;
25 #address-cells = <1>;
26 interrupt-controller;
27 interrupt-parent;
28 reg = <0xa0411000 0x1000>,
29 <0xa0410100 0x100>;
30 };
31
32 L2: l2-cache {
33 compatible = "arm,pl310-cache";
34 reg = <0xa0412000 0x1000>;
35 interrupts = <0 13 4>;
36 cache-unified;
37 cache-level = <2>;
38 };
39
40 pmu {
41 compatible = "arm,cortex-a9-pmu";
42 interrupts = <0 7 0x4>;
43 };
44
45 timer@a0410600 {
46 compatible = "arm,cortex-a9-twd-timer";
47 reg = <0xa0410600 0x20>;
48 interrupts = <1 13 0x304>;
49 };
50
51 rtc@80154000 {
52 compatible = "stericsson,db8500-rtc";
53 reg = <0x80154000 0x1000>;
54 interrupts = <0 18 0x4>;
55 };
56
57 gpio0: gpio@8012e000 {
58 compatible = "stericsson,db8500-gpio",
59 "stmicroelectronics,nomadik-gpio";
60 reg = <0x8012e000 0x80>;
61 interrupts = <0 119 0x4>;
62 supports-sleepmode;
63 gpio-controller;
64 };
65
66 gpio1: gpio@8012e080 {
67 compatible = "stericsson,db8500-gpio",
68 "stmicroelectronics,nomadik-gpio";
69 reg = <0x8012e080 0x80>;
70 interrupts = <0 120 0x4>;
71 supports-sleepmode;
72 gpio-controller;
73 };
74
75 gpio2: gpio@8000e000 {
76 compatible = "stericsson,db8500-gpio",
77 "stmicroelectronics,nomadik-gpio";
78 reg = <0x8000e000 0x80>;
79 interrupts = <0 121 0x4>;
80 supports-sleepmode;
81 gpio-controller;
82 };
83
84 gpio3: gpio@8000e080 {
85 compatible = "stericsson,db8500-gpio",
86 "stmicroelectronics,nomadik-gpio";
87 reg = <0x8000e080 0x80>;
88 interrupts = <0 122 0x4>;
89 supports-sleepmode;
90 gpio-controller;
91 };
92
93 gpio4: gpio@8000e100 {
94 compatible = "stericsson,db8500-gpio",
95 "stmicroelectronics,nomadik-gpio";
96 reg = <0x8000e100 0x80>;
97 interrupts = <0 123 0x4>;
98 supports-sleepmode;
99 gpio-controller;
100 };
101
102 gpio5: gpio@8000e180 {
103 compatible = "stericsson,db8500-gpio",
104 "stmicroelectronics,nomadik-gpio";
105 reg = <0x8000e180 0x80>;
106 interrupts = <0 124 0x4>;
107 supports-sleepmode;
108 gpio-controller;
109 };
110
111 gpio6: gpio@8011e000 {
112 compatible = "stericsson,db8500-gpio",
113 "stmicroelectronics,nomadik-gpio";
114 reg = <0x8011e000 0x80>;
115 interrupts = <0 125 0x4>;
116 supports-sleepmode;
117 gpio-controller;
118 };
119
120 gpio7: gpio@8011e080 {
121 compatible = "stericsson,db8500-gpio",
122 "stmicroelectronics,nomadik-gpio";
123 reg = <0x8011e080 0x80>;
124 interrupts = <0 126 0x4>;
125 supports-sleepmode;
126 gpio-controller;
127 };
128
129 gpio8: gpio@a03fe000 {
130 compatible = "stericsson,db8500-gpio",
131 "stmicroelectronics,nomadik-gpio";
132 reg = <0xa03fe000 0x80>;
133 interrupts = <0 127 0x4>;
134 supports-sleepmode;
135 gpio-controller;
136 };
137
138 usb@a03e0000 {
139 compatible = "stericsson,db8500-musb",
140 "mentor,musb";
141 reg = <0xa03e0000 0x10000>;
142 interrupts = <0 23 0x4>;
143 };
144
145 dma-controller@801C0000 {
146 compatible = "stericsson,db8500-dma40",
147 "stericsson,dma40";
148 reg = <0x801C0000 0x1000 0x40010000 0x800>;
149 interrupts = <0 25 0x4>;
150 };
151
152 prcmu@80157000 {
153 compatible = "stericsson,db8500-prcmu";
154 reg = <0x80157000 0x1000>;
155 interrupts = <46 47>;
156 #address-cells = <1>;
157 #size-cells = <0>;
158
159 ab8500@5 {
160 compatible = "stericsson,ab8500";
161 reg = <5>; /* mailbox 5 is i2c */
162 interrupts = <0 40 0x4>;
163 };
164 };
165
166 i2c@80004000 {
167 compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
168 reg = <0x80004000 0x1000>;
169 interrupts = <0 21 0x4>;
170 #address-cells = <1>;
171 #size-cells = <0>;
172 };
173
174 i2c@80122000 {
175 compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
176 reg = <0x80122000 0x1000>;
177 interrupts = <0 22 0x4>;
178 #address-cells = <1>;
179 #size-cells = <0>;
180 };
181
182 i2c@80128000 {
183 compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
184 reg = <0x80128000 0x1000>;
185 interrupts = <0 55 0x4>;
186 #address-cells = <1>;
187 #size-cells = <0>;
188 };
189
190 i2c@80110000 {
191 compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
192 reg = <0x80110000 0x1000>;
193 interrupts = <0 12 0x4>;
194 #address-cells = <1>;
195 #size-cells = <0>;
196 };
197
198 i2c@8012a000 {
199 compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
200 reg = <0x8012a000 0x1000>;
201 interrupts = <0 51 0x4>;
202 #address-cells = <1>;
203 #size-cells = <0>;
204 };
205
206 ssp@80002000 {
207 compatible = "arm,pl022", "arm,primecell";
208 reg = <80002000 0x1000>;
209 interrupts = <0 14 0x4>;
210 #address-cells = <1>;
211 #size-cells = <0>;
212 status = "disabled";
213
214 // Add one of these for each child device
215 cs-gpios = <&gpio0 31 &gpio4 14 &gpio4 16 &gpio6 22 &gpio7 0>;
216
217 };
218
219 uart@80120000 {
220 compatible = "arm,pl011", "arm,primecell";
221 reg = <0x80120000 0x1000>;
222 interrupts = <0 11 0x4>;
223 status = "disabled";
224 };
225 uart@80121000 {
226 compatible = "arm,pl011", "arm,primecell";
227 reg = <0x80121000 0x1000>;
228 interrupts = <0 19 0x4>;
229 status = "disabled";
230 };
231 uart@80007000 {
232 compatible = "arm,pl011", "arm,primecell";
233 reg = <0x80007000 0x1000>;
234 interrupts = <0 26 0x4>;
235 status = "disabled";
236 };
237
238 sdi@80126000 {
239 compatible = "arm,pl18x", "arm,primecell";
240 reg = <0x80126000 0x1000>;
241 interrupts = <0 60 0x4>;
242 status = "disabled";
243 };
244 sdi@80118000 {
245 compatible = "arm,pl18x", "arm,primecell";
246 reg = <0x80118000 0x1000>;
247 interrupts = <0 50 0x4>;
248 status = "disabled";
249 };
250 sdi@80005000 {
251 compatible = "arm,pl18x", "arm,primecell";
252 reg = <0x80005000 0x1000>;
253 interrupts = <0 41 0x4>;
254 status = "disabled";
255 };
256 sdi@80119000 {
257 compatible = "arm,pl18x", "arm,primecell";
258 reg = <0x80119000 0x1000>;
259 interrupts = <0 59 0x4>;
260 status = "disabled";
261 };
262 sdi@80114000 {
263 compatible = "arm,pl18x", "arm,primecell";
264 reg = <0x80114000 0x1000>;
265 interrupts = <0 99 0x4>;
266 status = "disabled";
267 };
268 sdi@80008000 {
269 compatible = "arm,pl18x", "arm,primecell";
270 reg = <0x80114000 0x1000>;
271 interrupts = <0 100 0x4>;
272 status = "disabled";
273 };
274 };
275};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
new file mode 100644
index 000000000000..399d17b231d2
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -0,0 +1,26 @@
1/*
2 * SAMSUNG SMDK5250 board device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/dts-v1/;
13/include/ "exynos5250.dtsi"
14
15/ {
16 model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
17 compatible = "samsung,smdk5250", "samsung,exynos5250";
18
19 memory {
20 reg = <0x40000000 0x80000000>;
21 };
22
23 chosen {
24 bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
25 };
26};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
new file mode 100644
index 000000000000..dfc433599436
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -0,0 +1,413 @@
1/*
2 * SAMSUNG EXYNOS5250 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20/include/ "skeleton.dtsi"
21
22/ {
23 compatible = "samsung,exynos5250";
24 interrupt-parent = <&gic>;
25
26 gic:interrupt-controller@10490000 {
27 compatible = "arm,cortex-a9-gic";
28 #interrupt-cells = <3>;
29 interrupt-controller;
30 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
31 };
32
33 watchdog {
34 compatible = "samsung,s3c2410-wdt";
35 reg = <0x101D0000 0x100>;
36 interrupts = <0 42 0>;
37 };
38
39 rtc {
40 compatible = "samsung,s3c6410-rtc";
41 reg = <0x101E0000 0x100>;
42 interrupts = <0 43 0>, <0 44 0>;
43 };
44
45 sdhci@12200000 {
46 compatible = "samsung,exynos4210-sdhci";
47 reg = <0x12200000 0x100>;
48 interrupts = <0 75 0>;
49 };
50
51 sdhci@12210000 {
52 compatible = "samsung,exynos4210-sdhci";
53 reg = <0x12210000 0x100>;
54 interrupts = <0 76 0>;
55 };
56
57 sdhci@12220000 {
58 compatible = "samsung,exynos4210-sdhci";
59 reg = <0x12220000 0x100>;
60 interrupts = <0 77 0>;
61 };
62
63 sdhci@12230000 {
64 compatible = "samsung,exynos4210-sdhci";
65 reg = <0x12230000 0x100>;
66 interrupts = <0 78 0>;
67 };
68
69 serial@12C00000 {
70 compatible = "samsung,exynos4210-uart";
71 reg = <0x12C00000 0x100>;
72 interrupts = <0 51 0>;
73 };
74
75 serial@12C10000 {
76 compatible = "samsung,exynos4210-uart";
77 reg = <0x12C10000 0x100>;
78 interrupts = <0 52 0>;
79 };
80
81 serial@12C20000 {
82 compatible = "samsung,exynos4210-uart";
83 reg = <0x12C20000 0x100>;
84 interrupts = <0 53 0>;
85 };
86
87 serial@12C30000 {
88 compatible = "samsung,exynos4210-uart";
89 reg = <0x12C30000 0x100>;
90 interrupts = <0 54 0>;
91 };
92
93 i2c@12C60000 {
94 compatible = "samsung,s3c2440-i2c";
95 reg = <0x12C60000 0x100>;
96 interrupts = <0 56 0>;
97 };
98
99 i2c@12C70000 {
100 compatible = "samsung,s3c2440-i2c";
101 reg = <0x12C70000 0x100>;
102 interrupts = <0 57 0>;
103 };
104
105 i2c@12C80000 {
106 compatible = "samsung,s3c2440-i2c";
107 reg = <0x12C80000 0x100>;
108 interrupts = <0 58 0>;
109 };
110
111 i2c@12C90000 {
112 compatible = "samsung,s3c2440-i2c";
113 reg = <0x12C90000 0x100>;
114 interrupts = <0 59 0>;
115 };
116
117 i2c@12CA0000 {
118 compatible = "samsung,s3c2440-i2c";
119 reg = <0x12CA0000 0x100>;
120 interrupts = <0 60 0>;
121 };
122
123 i2c@12CB0000 {
124 compatible = "samsung,s3c2440-i2c";
125 reg = <0x12CB0000 0x100>;
126 interrupts = <0 61 0>;
127 };
128
129 i2c@12CC0000 {
130 compatible = "samsung,s3c2440-i2c";
131 reg = <0x12CC0000 0x100>;
132 interrupts = <0 62 0>;
133 };
134
135 i2c@12CD0000 {
136 compatible = "samsung,s3c2440-i2c";
137 reg = <0x12CD0000 0x100>;
138 interrupts = <0 63 0>;
139 };
140
141 amba {
142 #address-cells = <1>;
143 #size-cells = <1>;
144 compatible = "arm,amba-bus";
145 interrupt-parent = <&gic>;
146 ranges;
147
148 pdma0: pdma@121A0000 {
149 compatible = "arm,pl330", "arm,primecell";
150 reg = <0x121A0000 0x1000>;
151 interrupts = <0 34 0>;
152 };
153
154 pdma1: pdma@121B0000 {
155 compatible = "arm,pl330", "arm,primecell";
156 reg = <0x121B0000 0x1000>;
157 interrupts = <0 35 0>;
158 };
159
160 mdma0: pdma@10800000 {
161 compatible = "arm,pl330", "arm,primecell";
162 reg = <0x10800000 0x1000>;
163 interrupts = <0 33 0>;
164 };
165
166 mdma1: pdma@11C10000 {
167 compatible = "arm,pl330", "arm,primecell";
168 reg = <0x11C10000 0x1000>;
169 interrupts = <0 124 0>;
170 };
171 };
172
173 gpio-controllers {
174 #address-cells = <1>;
175 #size-cells = <1>;
176 gpio-controller;
177 ranges;
178
179 gpa0: gpio-controller@11400000 {
180 compatible = "samsung,exynos4-gpio";
181 reg = <0x11400000 0x20>;
182 #gpio-cells = <4>;
183 };
184
185 gpa1: gpio-controller@11400020 {
186 compatible = "samsung,exynos4-gpio";
187 reg = <0x11400020 0x20>;
188 #gpio-cells = <4>;
189 };
190
191 gpa2: gpio-controller@11400040 {
192 compatible = "samsung,exynos4-gpio";
193 reg = <0x11400040 0x20>;
194 #gpio-cells = <4>;
195 };
196
197 gpb0: gpio-controller@11400060 {
198 compatible = "samsung,exynos4-gpio";
199 reg = <0x11400060 0x20>;
200 #gpio-cells = <4>;
201 };
202
203 gpb1: gpio-controller@11400080 {
204 compatible = "samsung,exynos4-gpio";
205 reg = <0x11400080 0x20>;
206 #gpio-cells = <4>;
207 };
208
209 gpb2: gpio-controller@114000A0 {
210 compatible = "samsung,exynos4-gpio";
211 reg = <0x114000A0 0x20>;
212 #gpio-cells = <4>;
213 };
214
215 gpb3: gpio-controller@114000C0 {
216 compatible = "samsung,exynos4-gpio";
217 reg = <0x114000C0 0x20>;
218 #gpio-cells = <4>;
219 };
220
221 gpc0: gpio-controller@114000E0 {
222 compatible = "samsung,exynos4-gpio";
223 reg = <0x114000E0 0x20>;
224 #gpio-cells = <4>;
225 };
226
227 gpc1: gpio-controller@11400100 {
228 compatible = "samsung,exynos4-gpio";
229 reg = <0x11400100 0x20>;
230 #gpio-cells = <4>;
231 };
232
233 gpc2: gpio-controller@11400120 {
234 compatible = "samsung,exynos4-gpio";
235 reg = <0x11400120 0x20>;
236 #gpio-cells = <4>;
237 };
238
239 gpc3: gpio-controller@11400140 {
240 compatible = "samsung,exynos4-gpio";
241 reg = <0x11400140 0x20>;
242 #gpio-cells = <4>;
243 };
244
245 gpd0: gpio-controller@11400160 {
246 compatible = "samsung,exynos4-gpio";
247 reg = <0x11400160 0x20>;
248 #gpio-cells = <4>;
249 };
250
251 gpd1: gpio-controller@11400180 {
252 compatible = "samsung,exynos4-gpio";
253 reg = <0x11400180 0x20>;
254 #gpio-cells = <4>;
255 };
256
257 gpy0: gpio-controller@114001A0 {
258 compatible = "samsung,exynos4-gpio";
259 reg = <0x114001A0 0x20>;
260 #gpio-cells = <4>;
261 };
262
263 gpy1: gpio-controller@114001C0 {
264 compatible = "samsung,exynos4-gpio";
265 reg = <0x114001C0 0x20>;
266 #gpio-cells = <4>;
267 };
268
269 gpy2: gpio-controller@114001E0 {
270 compatible = "samsung,exynos4-gpio";
271 reg = <0x114001E0 0x20>;
272 #gpio-cells = <4>;
273 };
274
275 gpy3: gpio-controller@11400200 {
276 compatible = "samsung,exynos4-gpio";
277 reg = <0x11400200 0x20>;
278 #gpio-cells = <4>;
279 };
280
281 gpy4: gpio-controller@11400220 {
282 compatible = "samsung,exynos4-gpio";
283 reg = <0x11400220 0x20>;
284 #gpio-cells = <4>;
285 };
286
287 gpy5: gpio-controller@11400240 {
288 compatible = "samsung,exynos4-gpio";
289 reg = <0x11400240 0x20>;
290 #gpio-cells = <4>;
291 };
292
293 gpy6: gpio-controller@11400260 {
294 compatible = "samsung,exynos4-gpio";
295 reg = <0x11400260 0x20>;
296 #gpio-cells = <4>;
297 };
298
299 gpx0: gpio-controller@11400C00 {
300 compatible = "samsung,exynos4-gpio";
301 reg = <0x11400C00 0x20>;
302 #gpio-cells = <4>;
303 };
304
305 gpx1: gpio-controller@11400C20 {
306 compatible = "samsung,exynos4-gpio";
307 reg = <0x11400C20 0x20>;
308 #gpio-cells = <4>;
309 };
310
311 gpx2: gpio-controller@11400C40 {
312 compatible = "samsung,exynos4-gpio";
313 reg = <0x11400C40 0x20>;
314 #gpio-cells = <4>;
315 };
316
317 gpx3: gpio-controller@11400C60 {
318 compatible = "samsung,exynos4-gpio";
319 reg = <0x11400C60 0x20>;
320 #gpio-cells = <4>;
321 };
322
323 gpe0: gpio-controller@13400000 {
324 compatible = "samsung,exynos4-gpio";
325 reg = <0x13400000 0x20>;
326 #gpio-cells = <4>;
327 };
328
329 gpe1: gpio-controller@13400020 {
330 compatible = "samsung,exynos4-gpio";
331 reg = <0x13400020 0x20>;
332 #gpio-cells = <4>;
333 };
334
335 gpf0: gpio-controller@13400040 {
336 compatible = "samsung,exynos4-gpio";
337 reg = <0x13400040 0x20>;
338 #gpio-cells = <4>;
339 };
340
341 gpf1: gpio-controller@13400060 {
342 compatible = "samsung,exynos4-gpio";
343 reg = <0x13400060 0x20>;
344 #gpio-cells = <4>;
345 };
346
347 gpg0: gpio-controller@13400080 {
348 compatible = "samsung,exynos4-gpio";
349 reg = <0x13400080 0x20>;
350 #gpio-cells = <4>;
351 };
352
353 gpg1: gpio-controller@134000A0 {
354 compatible = "samsung,exynos4-gpio";
355 reg = <0x134000A0 0x20>;
356 #gpio-cells = <4>;
357 };
358
359 gpg2: gpio-controller@134000C0 {
360 compatible = "samsung,exynos4-gpio";
361 reg = <0x134000C0 0x20>;
362 #gpio-cells = <4>;
363 };
364
365 gph0: gpio-controller@134000E0 {
366 compatible = "samsung,exynos4-gpio";
367 reg = <0x134000E0 0x20>;
368 #gpio-cells = <4>;
369 };
370
371 gph1: gpio-controller@13400100 {
372 compatible = "samsung,exynos4-gpio";
373 reg = <0x13400100 0x20>;
374 #gpio-cells = <4>;
375 };
376
377 gpv0: gpio-controller@10D10000 {
378 compatible = "samsung,exynos4-gpio";
379 reg = <0x10D10000 0x20>;
380 #gpio-cells = <4>;
381 };
382
383 gpv1: gpio-controller@10D10020 {
384 compatible = "samsung,exynos4-gpio";
385 reg = <0x10D10020 0x20>;
386 #gpio-cells = <4>;
387 };
388
389 gpv2: gpio-controller@10D10040 {
390 compatible = "samsung,exynos4-gpio";
391 reg = <0x10D10040 0x20>;
392 #gpio-cells = <4>;
393 };
394
395 gpv3: gpio-controller@10D10060 {
396 compatible = "samsung,exynos4-gpio";
397 reg = <0x10D10060 0x20>;
398 #gpio-cells = <4>;
399 };
400
401 gpv4: gpio-controller@10D10080 {
402 compatible = "samsung,exynos4-gpio";
403 reg = <0x10D10080 0x20>;
404 #gpio-cells = <4>;
405 };
406
407 gpz: gpio-controller@03860000 {
408 compatible = "samsung,exynos4-gpio";
409 reg = <0x03860000 0x20>;
410 #gpio-cells = <4>;
411 };
412 };
413};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 305635bd45c0..37c0ff9c8b90 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -72,15 +72,15 @@
72 ranges; 72 ranges;
73 73
74 timer@fff10600 { 74 timer@fff10600 {
75 compatible = "arm,smp-twd"; 75 compatible = "arm,cortex-a9-twd-timer";
76 reg = <0xfff10600 0x20>; 76 reg = <0xfff10600 0x20>;
77 interrupts = <1 13 0xf04>; 77 interrupts = <1 13 0xf01>;
78 }; 78 };
79 79
80 watchdog@fff10620 { 80 watchdog@fff10620 {
81 compatible = "arm,cortex-a9-wdt"; 81 compatible = "arm,cortex-a9-twd-wdt";
82 reg = <0xfff10620 0x20>; 82 reg = <0xfff10620 0x20>;
83 interrupts = <1 14 0xf04>; 83 interrupts = <1 14 0xf01>;
84 }; 84 };
85 85
86 intc: interrupt-controller@fff11000 { 86 intc: interrupt-controller@fff11000 {
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
new file mode 100644
index 000000000000..a51a08fc2af9
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -0,0 +1,76 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx27.dtsi"
14
15/ {
16 model = "Phytec pcm038";
17 compatible = "phytec,imx27-pcm038", "fsl,imx27";
18
19 memory {
20 reg = <0x0 0x0>;
21 };
22
23 soc {
24 aipi@10000000 { /* aipi */
25
26 wdog@10002000 {
27 status = "okay";
28 };
29
30 uart@1000a000 {
31 fsl,uart-has-rtscts;
32 status = "okay";
33 };
34
35 uart@1000b000 {
36 fsl,uart-has-rtscts;
37 status = "okay";
38 };
39
40 uart@1000c000 {
41 fsl,uart-has-rtscts;
42 status = "okay";
43 };
44
45 fec@1002b000 {
46 status = "okay";
47 };
48
49 i2c@1001d000 {
50 clock-frequency = <400000>;
51 status = "okay";
52 at24@4c {
53 compatible = "at,24c32";
54 pagesize = <32>;
55 reg = <0x52>;
56 };
57 pcf8563@51 {
58 compatible = "nxp,pcf8563";
59 reg = <0x51>;
60 };
61 lm75@4a {
62 compatible = "national,lm75";
63 reg = <0x4a>;
64 };
65 };
66 };
67 };
68
69 nor_flash@c0000000 {
70 compatible = "cfi-flash";
71 bank-width = <2>;
72 reg = <0xc0000000 0x02000000>;
73 #address-cells = <1>;
74 #size-cells = <1>;
75 };
76};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
new file mode 100644
index 000000000000..bc5e7d5ddd54
--- /dev/null
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -0,0 +1,217 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 aliases {
16 serial0 = &uart1;
17 serial1 = &uart2;
18 serial2 = &uart3;
19 serial3 = &uart4;
20 serial4 = &uart5;
21 serial5 = &uart6;
22 };
23
24 avic: avic-interrupt-controller@e0000000 {
25 compatible = "fsl,imx27-avic", "fsl,avic";
26 interrupt-controller;
27 #interrupt-cells = <1>;
28 reg = <0x10040000 0x1000>;
29 };
30
31 clocks {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 osc26m {
36 compatible = "fsl,imx-osc26m", "fixed-clock";
37 clock-frequency = <26000000>;
38 };
39 };
40
41 soc {
42 #address-cells = <1>;
43 #size-cells = <1>;
44 compatible = "simple-bus";
45 interrupt-parent = <&avic>;
46 ranges;
47
48 aipi@10000000 { /* AIPI1 */
49 compatible = "fsl,aipi-bus", "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 reg = <0x10000000 0x10000000>;
53 ranges;
54
55 wdog@10002000 {
56 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
57 reg = <0x10002000 0x4000>;
58 interrupts = <27>;
59 status = "disabled";
60 };
61
62 uart1: uart@1000a000 {
63 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
64 reg = <0x1000a000 0x1000>;
65 interrupts = <20>;
66 status = "disabled";
67 };
68
69 uart2: uart@1000b000 {
70 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
71 reg = <0x1000b000 0x1000>;
72 interrupts = <19>;
73 status = "disabled";
74 };
75
76 uart3: uart@1000c000 {
77 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
78 reg = <0x1000c000 0x1000>;
79 interrupts = <18>;
80 status = "disabled";
81 };
82
83 uart4: uart@1000d000 {
84 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
85 reg = <0x1000d000 0x1000>;
86 interrupts = <17>;
87 status = "disabled";
88 };
89
90 cspi1: cspi@1000e000 {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 compatible = "fsl,imx27-cspi";
94 reg = <0x1000e000 0x1000>;
95 interrupts = <16>;
96 status = "disabled";
97 };
98
99 cspi2: cspi@1000f000 {
100 #address-cells = <1>;
101 #size-cells = <0>;
102 compatible = "fsl,imx27-cspi";
103 reg = <0x1000f000 0x1000>;
104 interrupts = <15>;
105 status = "disabled";
106 };
107
108 i2c1: i2c@10012000 {
109 #address-cells = <1>;
110 #size-cells = <0>;
111 compatible = "fsl,imx27-i2c", "fsl,imx1-i2c";
112 reg = <0x10012000 0x1000>;
113 interrupts = <12>;
114 status = "disabled";
115 };
116
117 gpio1: gpio@10015000 {
118 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
119 reg = <0x10015000 0x100>;
120 interrupts = <8>;
121 gpio-controller;
122 #gpio-cells = <2>;
123 interrupt-controller;
124 #interrupt-cells = <1>;
125 };
126
127 gpio2: gpio@10015100 {
128 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
129 reg = <0x10015100 0x100>;
130 interrupts = <8>;
131 gpio-controller;
132 #gpio-cells = <2>;
133 interrupt-controller;
134 #interrupt-cells = <1>;
135 };
136
137 gpio3: gpio@10015200 {
138 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
139 reg = <0x10015200 0x100>;
140 interrupts = <8>;
141 gpio-controller;
142 #gpio-cells = <2>;
143 interrupt-controller;
144 #interrupt-cells = <1>;
145 };
146
147 gpio4: gpio@10015300 {
148 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
149 reg = <0x10015300 0x100>;
150 interrupts = <8>;
151 gpio-controller;
152 #gpio-cells = <2>;
153 interrupt-controller;
154 #interrupt-cells = <1>;
155 };
156
157 gpio5: gpio@10015400 {
158 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
159 reg = <0x10015400 0x100>;
160 interrupts = <8>;
161 gpio-controller;
162 #gpio-cells = <2>;
163 interrupt-controller;
164 #interrupt-cells = <1>;
165 };
166
167 gpio6: gpio@10015500 {
168 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
169 reg = <0x10015500 0x100>;
170 interrupts = <8>;
171 gpio-controller;
172 #gpio-cells = <2>;
173 interrupt-controller;
174 #interrupt-cells = <1>;
175 };
176
177 cspi3: cspi@10017000 {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 compatible = "fsl,imx27-cspi";
181 reg = <0x10017000 0x1000>;
182 interrupts = <6>;
183 status = "disabled";
184 };
185
186 uart5: uart@1001b000 {
187 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
188 reg = <0x1001b000 0x1000>;
189 interrupts = <49>;
190 status = "disabled";
191 };
192
193 uart6: uart@1001c000 {
194 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
195 reg = <0x1001c000 0x1000>;
196 interrupts = <48>;
197 status = "disabled";
198 };
199
200 i2c2: i2c@1001d000 {
201 #address-cells = <1>;
202 #size-cells = <0>;
203 compatible = "fsl,imx27-i2c", "fsl,imx1-i2c";
204 reg = <0x1001d000 0x1000>;
205 interrupts = <1>;
206 status = "disabled";
207 };
208
209 fec: fec@1002b000 {
210 compatible = "fsl,imx27-fec";
211 reg = <0x1002b000 0x4000>;
212 interrupts = <50>;
213 status = "disabled";
214 };
215 };
216 };
217};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 564cb8c19f15..9949e6060dee 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -56,8 +56,95 @@
56 compatible = "fsl,mc13892"; 56 compatible = "fsl,mc13892";
57 spi-max-frequency = <6000000>; 57 spi-max-frequency = <6000000>;
58 reg = <0>; 58 reg = <0>;
59 mc13xxx-irq-gpios = <&gpio1 8 0>; 59 interrupt-parent = <&gpio1>;
60 fsl,mc13xxx-uses-regulator; 60 interrupts = <8>;
61
62 regulators {
63 sw1_reg: sw1 {
64 regulator-min-microvolt = <600000>;
65 regulator-max-microvolt = <1375000>;
66 regulator-boot-on;
67 regulator-always-on;
68 };
69
70 sw2_reg: sw2 {
71 regulator-min-microvolt = <900000>;
72 regulator-max-microvolt = <1850000>;
73 regulator-boot-on;
74 regulator-always-on;
75 };
76
77 sw3_reg: sw3 {
78 regulator-min-microvolt = <1100000>;
79 regulator-max-microvolt = <1850000>;
80 regulator-boot-on;
81 regulator-always-on;
82 };
83
84 sw4_reg: sw4 {
85 regulator-min-microvolt = <1100000>;
86 regulator-max-microvolt = <1850000>;
87 regulator-boot-on;
88 regulator-always-on;
89 };
90
91 vpll_reg: vpll {
92 regulator-min-microvolt = <1050000>;
93 regulator-max-microvolt = <1800000>;
94 regulator-boot-on;
95 regulator-always-on;
96 };
97
98 vdig_reg: vdig {
99 regulator-min-microvolt = <1650000>;
100 regulator-max-microvolt = <1650000>;
101 regulator-boot-on;
102 };
103
104 vsd_reg: vsd {
105 regulator-min-microvolt = <1800000>;
106 regulator-max-microvolt = <3150000>;
107 };
108
109 vusb2_reg: vusb2 {
110 regulator-min-microvolt = <2400000>;
111 regulator-max-microvolt = <2775000>;
112 regulator-boot-on;
113 regulator-always-on;
114 };
115
116 vvideo_reg: vvideo {
117 regulator-min-microvolt = <2775000>;
118 regulator-max-microvolt = <2775000>;
119 };
120
121 vaudio_reg: vaudio {
122 regulator-min-microvolt = <2300000>;
123 regulator-max-microvolt = <3000000>;
124 };
125
126 vcam_reg: vcam {
127 regulator-min-microvolt = <2500000>;
128 regulator-max-microvolt = <3000000>;
129 };
130
131 vgen1_reg: vgen1 {
132 regulator-min-microvolt = <1200000>;
133 regulator-max-microvolt = <1200000>;
134 };
135
136 vgen2_reg: vgen2 {
137 regulator-min-microvolt = <1200000>;
138 regulator-max-microvolt = <3150000>;
139 regulator-always-on;
140 };
141
142 vgen3_reg: vgen3 {
143 regulator-min-microvolt = <1800000>;
144 regulator-max-microvolt = <2900000>;
145 regulator-always-on;
146 };
147 };
61 }; 148 };
62 149
63 flash: at45db321d@1 { 150 flash: at45db321d@1 {
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index c3977e0478b9..ce1c8238c897 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -36,11 +36,13 @@
36 usdhc@02198000 { /* uSDHC3 */ 36 usdhc@02198000 { /* uSDHC3 */
37 cd-gpios = <&gpio6 11 0>; 37 cd-gpios = <&gpio6 11 0>;
38 wp-gpios = <&gpio6 14 0>; 38 wp-gpios = <&gpio6 14 0>;
39 vmmc-supply = <&reg_3p3v>;
39 status = "okay"; 40 status = "okay";
40 }; 41 };
41 42
42 usdhc@0219c000 { /* uSDHC4 */ 43 usdhc@0219c000 { /* uSDHC4 */
43 fsl,card-wired; 44 fsl,card-wired;
45 vmmc-supply = <&reg_3p3v>;
44 status = "okay"; 46 status = "okay";
45 }; 47 };
46 48
@@ -50,6 +52,18 @@
50 }; 52 };
51 }; 53 };
52 54
55 regulators {
56 compatible = "simple-bus";
57
58 reg_3p3v: 3p3v {
59 compatible = "regulator-fixed";
60 regulator-name = "3P3V";
61 regulator-min-microvolt = <3300000>;
62 regulator-max-microvolt = <3300000>;
63 regulator-always-on;
64 };
65 };
66
53 leds { 67 leds {
54 compatible = "gpio-leds"; 68 compatible = "gpio-leds";
55 69
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 08d920de7286..4663a4e5a285 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -32,18 +32,52 @@
32 usdhc@02198000 { /* uSDHC3 */ 32 usdhc@02198000 { /* uSDHC3 */
33 cd-gpios = <&gpio7 0 0>; 33 cd-gpios = <&gpio7 0 0>;
34 wp-gpios = <&gpio7 1 0>; 34 wp-gpios = <&gpio7 1 0>;
35 vmmc-supply = <&reg_3p3v>;
35 status = "okay"; 36 status = "okay";
36 }; 37 };
37 38
38 usdhc@0219c000 { /* uSDHC4 */ 39 usdhc@0219c000 { /* uSDHC4 */
39 cd-gpios = <&gpio2 6 0>; 40 cd-gpios = <&gpio2 6 0>;
40 wp-gpios = <&gpio2 7 0>; 41 wp-gpios = <&gpio2 7 0>;
42 vmmc-supply = <&reg_3p3v>;
41 status = "okay"; 43 status = "okay";
42 }; 44 };
43 45
44 uart2: uart@021e8000 { 46 uart2: uart@021e8000 {
45 status = "okay"; 47 status = "okay";
46 }; 48 };
49
50 i2c@021a0000 { /* I2C1 */
51 status = "okay";
52 clock-frequency = <100000>;
53
54 codec: sgtl5000@0a {
55 compatible = "fsl,sgtl5000";
56 reg = <0x0a>;
57 VDDA-supply = <&reg_2p5v>;
58 VDDIO-supply = <&reg_3p3v>;
59 };
60 };
61 };
62 };
63
64 regulators {
65 compatible = "simple-bus";
66
67 reg_2p5v: 2p5v {
68 compatible = "regulator-fixed";
69 regulator-name = "2P5V";
70 regulator-min-microvolt = <2500000>;
71 regulator-max-microvolt = <2500000>;
72 regulator-always-on;
73 };
74
75 reg_3p3v: 3p3v {
76 compatible = "regulator-fixed";
77 regulator-name = "3P3V";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
80 regulator-always-on;
47 }; 81 };
48 }; 82 };
49}; 83};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 263e8f3664b5..4905f51a106f 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -88,9 +88,9 @@
88 ranges; 88 ranges;
89 89
90 timer@00a00600 { 90 timer@00a00600 {
91 compatible = "arm,smp-twd"; 91 compatible = "arm,cortex-a9-twd-timer";
92 reg = <0x00a00600 0x100>; 92 reg = <0x00a00600 0x20>;
93 interrupts = <1 13 0xf4>; 93 interrupts = <1 13 0xf01>;
94 }; 94 };
95 95
96 L2: l2-cache@00a02000 { 96 L2: l2-cache@00a02000 {
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
new file mode 100644
index 000000000000..a5376b84227f
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -0,0 +1,24 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4
5/ {
6 model = "Globalscale Technologies Dreamplug";
7 compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x20000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200n8 earlyprintk";
16 };
17
18 ocp@f1000000 {
19 serial@12000 {
20 clock-frequency = <200000000>;
21 status = "ok";
22 };
23 };
24};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
new file mode 100644
index 000000000000..3474ef890945
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -0,0 +1,36 @@
1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "mrvl,kirkwood";
5
6 ocp@f1000000 {
7 compatible = "simple-bus";
8 ranges = <0 0xf1000000 0x1000000>;
9 #address-cells = <1>;
10 #size-cells = <1>;
11
12 serial@12000 {
13 compatible = "ns16550a";
14 reg = <0x12000 0x100>;
15 reg-shift = <2>;
16 interrupts = <33>;
17 /* set clock-frequency in board dts */
18 status = "disabled";
19 };
20
21 serial@12100 {
22 compatible = "ns16550a";
23 reg = <0x12100 0x100>;
24 reg-shift = <2>;
25 interrupts = <34>;
26 /* set clock-frequency in board dts */
27 status = "disabled";
28 };
29
30 rtc@10300 {
31 compatible = "mrvl,kirkwood-rtc", "mrvl,orion-rtc";
32 reg = <0x10300 0x20>;
33 interrupts = <53>;
34 };
35 };
36};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 9486be62bcdd..9f72cd4cf308 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -13,15 +13,6 @@
13 model = "TI OMAP3 BeagleBoard"; 13 model = "TI OMAP3 BeagleBoard";
14 compatible = "ti,omap3-beagle", "ti,omap3"; 14 compatible = "ti,omap3-beagle", "ti,omap3";
15 15
16 /*
17 * Since the initial device tree board file does not create any
18 * devices (MMC, network...), the only way to boot is to provide a
19 * ramdisk.
20 */
21 chosen {
22 bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug earlyprintk";
23 };
24
25 memory { 16 memory {
26 device_type = "memory"; 17 device_type = "memory";
27 reg = <0x80000000 0x20000000>; /* 512 MB */ 18 reg = <0x80000000 0x20000000>; /* 512 MB */
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
new file mode 100644
index 000000000000..2eee16ec59b4
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -0,0 +1,20 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap3.dtsi"
11
12/ {
13 model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)";
14 compatible = "ti,omap3-evm", "ti,omap3";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 };
20};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 216c3317461d..c6121357c1eb 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -61,34 +61,57 @@
61 ranges; 61 ranges;
62 ti,hwmods = "l3_main"; 62 ti,hwmods = "l3_main";
63 63
64 intc: interrupt-controller@1 { 64 intc: interrupt-controller@48200000 {
65 compatible = "ti,omap3-intc"; 65 compatible = "ti,omap2-intc";
66 interrupt-controller; 66 interrupt-controller;
67 #interrupt-cells = <1>; 67 #interrupt-cells = <1>;
68 ti,intc-size = <96>;
69 reg = <0x48200000 0x1000>;
68 }; 70 };
69 71
70 uart1: serial@0x4806a000 { 72 uart1: serial@4806a000 {
71 compatible = "ti,omap3-uart"; 73 compatible = "ti,omap3-uart";
72 ti,hwmods = "uart1"; 74 ti,hwmods = "uart1";
73 clock-frequency = <48000000>; 75 clock-frequency = <48000000>;
74 }; 76 };
75 77
76 uart2: serial@0x4806c000 { 78 uart2: serial@4806c000 {
77 compatible = "ti,omap3-uart"; 79 compatible = "ti,omap3-uart";
78 ti,hwmods = "uart2"; 80 ti,hwmods = "uart2";
79 clock-frequency = <48000000>; 81 clock-frequency = <48000000>;
80 }; 82 };
81 83
82 uart3: serial@0x49020000 { 84 uart3: serial@49020000 {
83 compatible = "ti,omap3-uart"; 85 compatible = "ti,omap3-uart";
84 ti,hwmods = "uart3"; 86 ti,hwmods = "uart3";
85 clock-frequency = <48000000>; 87 clock-frequency = <48000000>;
86 }; 88 };
87 89
88 uart4: serial@0x49042000 { 90 uart4: serial@49042000 {
89 compatible = "ti,omap3-uart"; 91 compatible = "ti,omap3-uart";
90 ti,hwmods = "uart4"; 92 ti,hwmods = "uart4";
91 clock-frequency = <48000000>; 93 clock-frequency = <48000000>;
92 }; 94 };
95
96 i2c1: i2c@48070000 {
97 compatible = "ti,omap3-i2c";
98 #address-cells = <1>;
99 #size-cells = <0>;
100 ti,hwmods = "i2c1";
101 };
102
103 i2c2: i2c@48072000 {
104 compatible = "ti,omap3-i2c";
105 #address-cells = <1>;
106 #size-cells = <0>;
107 ti,hwmods = "i2c2";
108 };
109
110 i2c3: i2c@48060000 {
111 compatible = "ti,omap3-i2c";
112 #address-cells = <1>;
113 #size-cells = <0>;
114 ti,hwmods = "i2c3";
115 };
93 }; 116 };
94}; 117};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index c7026578ce7d..9755ad5917f8 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -13,15 +13,6 @@
13 model = "TI OMAP4 PandaBoard"; 13 model = "TI OMAP4 PandaBoard";
14 compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; 14 compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
15 15
16 /*
17 * Since the initial device tree board file does not create any
18 * devices (MMC, network...), the only way to boot is to provide a
19 * ramdisk.
20 */
21 chosen {
22 bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
23 };
24
25 memory { 16 memory {
26 device_type = "memory"; 17 device_type = "memory";
27 reg = <0x80000000 0x40000000>; /* 1 GB */ 18 reg = <0x80000000 0x40000000>; /* 1 GB */
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 066e28c90328..63c6b2b2bf42 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -13,15 +13,6 @@
13 model = "TI OMAP4 SDP board"; 13 model = "TI OMAP4 SDP board";
14 compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4"; 14 compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
15 15
16 /*
17 * Since the initial device tree board file does not create any
18 * devices (MMC, network...), the only way to boot is to provide a
19 * ramdisk.
20 */
21 chosen {
22 bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
23 };
24
25 memory { 16 memory {
26 device_type = "memory"; 17 device_type = "memory";
27 reg = <0x80000000 0x40000000>; /* 1 GB */ 18 reg = <0x80000000 0x40000000>; /* 1 GB */
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index e8fe75fac7c5..3d35559e77bc 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -99,33 +99,61 @@
99 gic: interrupt-controller@48241000 { 99 gic: interrupt-controller@48241000 {
100 compatible = "arm,cortex-a9-gic"; 100 compatible = "arm,cortex-a9-gic";
101 interrupt-controller; 101 interrupt-controller;
102 #interrupt-cells = <1>; 102 #interrupt-cells = <3>;
103 reg = <0x48241000 0x1000>, 103 reg = <0x48241000 0x1000>,
104 <0x48240100 0x0100>; 104 <0x48240100 0x0100>;
105 }; 105 };
106 106
107 uart1: serial@0x4806a000 { 107 uart1: serial@4806a000 {
108 compatible = "ti,omap4-uart"; 108 compatible = "ti,omap4-uart";
109 ti,hwmods = "uart1"; 109 ti,hwmods = "uart1";
110 clock-frequency = <48000000>; 110 clock-frequency = <48000000>;
111 }; 111 };
112 112
113 uart2: serial@0x4806c000 { 113 uart2: serial@4806c000 {
114 compatible = "ti,omap4-uart"; 114 compatible = "ti,omap4-uart";
115 ti,hwmods = "uart2"; 115 ti,hwmods = "uart2";
116 clock-frequency = <48000000>; 116 clock-frequency = <48000000>;
117 }; 117 };
118 118
119 uart3: serial@0x48020000 { 119 uart3: serial@48020000 {
120 compatible = "ti,omap4-uart"; 120 compatible = "ti,omap4-uart";
121 ti,hwmods = "uart3"; 121 ti,hwmods = "uart3";
122 clock-frequency = <48000000>; 122 clock-frequency = <48000000>;
123 }; 123 };
124 124
125 uart4: serial@0x4806e000 { 125 uart4: serial@4806e000 {
126 compatible = "ti,omap4-uart"; 126 compatible = "ti,omap4-uart";
127 ti,hwmods = "uart4"; 127 ti,hwmods = "uart4";
128 clock-frequency = <48000000>; 128 clock-frequency = <48000000>;
129 }; 129 };
130
131 i2c1: i2c@48070000 {
132 compatible = "ti,omap4-i2c";
133 #address-cells = <1>;
134 #size-cells = <0>;
135 ti,hwmods = "i2c1";
136 };
137
138 i2c2: i2c@48072000 {
139 compatible = "ti,omap4-i2c";
140 #address-cells = <1>;
141 #size-cells = <0>;
142 ti,hwmods = "i2c2";
143 };
144
145 i2c3: i2c@48060000 {
146 compatible = "ti,omap4-i2c";
147 #address-cells = <1>;
148 #size-cells = <0>;
149 ti,hwmods = "i2c3";
150 };
151
152 i2c4: i2c@48350000 {
153 compatible = "ti,omap4-i2c";
154 #address-cells = <1>;
155 #size-cells = <0>;
156 ti,hwmods = "i2c4";
157 };
130 }; 158 };
131}; 159};
diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/pxa168-aspenite.dts
new file mode 100644
index 000000000000..e762facb3fa4
--- /dev/null
+++ b/arch/arm/boot/dts/pxa168-aspenite.dts
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/dts-v1/;
11/include/ "pxa168.dtsi"
12
13/ {
14 model = "Marvell PXA168 Aspenite Development Board";
15 compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
16
17 chosen {
18 bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
19 };
20
21 memory {
22 reg = <0x00000000 0x04000000>;
23 };
24
25 soc {
26 apb@d4000000 {
27 uart1: uart@d4017000 {
28 status = "okay";
29 };
30 twsi1: i2c@d4011000 {
31 status = "okay";
32 };
33 rtc: rtc@d4010000 {
34 status = "okay";
35 };
36 };
37 };
38};
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
new file mode 100644
index 000000000000..d32d5128f225
--- /dev/null
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -0,0 +1,98 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 aliases {
14 serial0 = &uart1;
15 serial1 = &uart2;
16 serial2 = &uart3;
17 i2c0 = &twsi1;
18 i2c1 = &twsi2;
19 };
20
21 intc: intc-interrupt-controller@d4282000 {
22 compatible = "mrvl,mmp-intc", "mrvl,intc";
23 interrupt-controller;
24 #interrupt-cells = <1>;
25 reg = <0xd4282000 0x1000>;
26 };
27
28 soc {
29 #address-cells = <1>;
30 #size-cells = <1>;
31 compatible = "simple-bus";
32 interrupt-parent = <&intc>;
33 ranges;
34
35 apb@d4000000 { /* APB */
36 compatible = "mrvl,apb-bus", "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0xd4000000 0x00200000>;
40 ranges;
41
42 uart1: uart@d4017000 {
43 compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
44 reg = <0xd4017000 0x1000>;
45 interrupts = <27>;
46 status = "disabled";
47 };
48
49 uart2: uart@d4018000 {
50 compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
51 reg = <0xd4018000 0x1000>;
52 interrupts = <28>;
53 status = "disabled";
54 };
55
56 uart3: uart@d4026000 {
57 compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
58 reg = <0xd4026000 0x1000>;
59 interrupts = <29>;
60 status = "disabled";
61 };
62
63 gpio: gpio@d4019000 {
64 compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
65 reg = <0xd4019000 0x1000>;
66 interrupts = <49>;
67 interrupt-names = "gpio_mux";
68 gpio-controller;
69 #gpio-cells = <1>;
70 interrupt-controller;
71 #interrupt-cells = <1>;
72 };
73
74 twsi1: i2c@d4011000 {
75 compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
76 reg = <0xd4011000 0x1000>;
77 interrupts = <7>;
78 mrvl,i2c-fast-mode;
79 status = "disabled";
80 };
81
82 twsi2: i2c@d4025000 {
83 compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
84 reg = <0xd4025000 0x1000>;
85 interrupts = <58>;
86 status = "disabled";
87 };
88
89 rtc: rtc@d4010000 {
90 compatible = "mrvl,mmp-rtc";
91 reg = <0xd4010000 0x1000>;
92 interrupts = <5 6>;
93 interrupt-names = "rtc 1Hz", "rtc alarm";
94 status = "disabled";
95 };
96 };
97 };
98};
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
new file mode 100644
index 000000000000..359c6d679156
--- /dev/null
+++ b/arch/arm/boot/dts/snowball.dts
@@ -0,0 +1,139 @@
1/*
2 * Copyright 2011 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "db8500.dtsi"
14
15/ {
16 model = "Calao Systems Snowball platform with device tree";
17 compatible = "calaosystems,snowball-a9500";
18
19 memory {
20 reg = <0x00000000 0x20000000>;
21 };
22
23 gpio_keys {
24 compatible = "gpio-keys";
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 button@1 {
29 debounce_interval = <50>;
30 wakeup = <1>;
31 linux,code = <2>;
32 label = "userpb";
33 gpios = <&gpio1 0>;
34 };
35 button@2 {
36 debounce_interval = <50>;
37 wakeup = <1>;
38 linux,code = <3>;
39 label = "userpb";
40 gpios = <&gpio4 23>;
41 };
42 button@3 {
43 debounce_interval = <50>;
44 wakeup = <1>;
45 linux,code = <4>;
46 label = "userpb";
47 gpios = <&gpio4 23>;
48 };
49 button@4 {
50 debounce_interval = <50>;
51 wakeup = <1>;
52 linux,code = <5>;
53 label = "userpb";
54 gpios = <&gpio5 1>;
55 };
56 button@5 {
57 debounce_interval = <50>;
58 wakeup = <1>;
59 linux,code = <6>;
60 label = "userpb";
61 gpios = <&gpio5 2>;
62 };
63 };
64
65 leds {
66 compatible = "gpio-leds";
67 used-led {
68 label = "user_led";
69 gpios = <&gpio4 14>;
70 };
71 };
72
73 soc-u9500 {
74
75 external-bus@50000000 {
76 compatible = "simple-bus";
77 reg = <0x50000000 0x10000000>;
78 #address-cells = <1>;
79 #size-cells = <1>;
80 ranges;
81
82 ethernet@50000000 {
83 compatible = "smsc,9111";
84 reg = <0x50000000 0x10000>;
85 interrupts = <12>;
86 interrupt-parent = <&gpio4>;
87 };
88 };
89
90 sdi@80126000 {
91 status = "enabled";
92 cd-gpios = <&gpio6 26>;
93 };
94
95 sdi@80114000 {
96 status = "enabled";
97 };
98
99 uart@80120000 {
100 status = "okay";
101 };
102
103 uart@80121000 {
104 status = "okay";
105 };
106
107 uart@80007000 {
108 status = "okay";
109 };
110
111 i2c@80004000 {
112 tc3589x@42 {
113 //compatible = "tc3589x";
114 reg = <0x42>;
115 interrupts = <25>;
116 interrupt-parent = <&gpio6>;
117 };
118 tps61052@33 {
119 //compatible = "tps61052";
120 reg = <0x33>;
121 };
122 };
123
124 i2c@80128000 {
125 lp5521@0x33 {
126 // compatible = "lp5521";
127 reg = <0x33>;
128 };
129 lp5521@0x34 {
130 // compatible = "lp5521";
131 reg = <0x34>;
132 };
133 bh1780@0x29 {
134 // compatible = "rohm,bh1780gli";
135 reg = <0x33>;
136 };
137 };
138 };
139};
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
new file mode 100644
index 000000000000..636292e18c90
--- /dev/null
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -0,0 +1,47 @@
1/*
2 * Copyright 2012 Stefan Roese <sr@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "spear600.dtsi"
14
15/ {
16 model = "ST SPEAr600 Evaluation Board";
17 compatible = "st,spear600-evb", "st,spear600";
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 memory {
22 device_type = "memory";
23 reg = <0 0x10000000>;
24 };
25
26 ahb {
27 gmac: ethernet@e0800000 {
28 phy-mode = "gmii";
29 status = "okay";
30 };
31
32 apb {
33 serial@d0000000 {
34 status = "okay";
35 };
36
37 serial@d0080000 {
38 status = "okay";
39 };
40
41 i2c@d0200000 {
42 clock-frequency = <400000>;
43 status = "okay";
44 };
45 };
46 };
47};
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
new file mode 100644
index 000000000000..ebe0885a2b98
--- /dev/null
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -0,0 +1,174 @@
1/*
2 * Copyright 2012 Stefan Roese <sr@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 compatible = "st,spear600";
16
17 cpus {
18 cpu@0 {
19 compatible = "arm,arm926ejs";
20 };
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0 0x40000000>;
26 };
27
28 ahb {
29 #address-cells = <1>;
30 #size-cells = <1>;
31 compatible = "simple-bus";
32 ranges = <0xd0000000 0xd0000000 0x30000000>;
33
34 vic0: interrupt-controller@f1100000 {
35 compatible = "arm,pl190-vic";
36 interrupt-controller;
37 reg = <0xf1100000 0x1000>;
38 #interrupt-cells = <1>;
39 };
40
41 vic1: interrupt-controller@f1000000 {
42 compatible = "arm,pl190-vic";
43 interrupt-controller;
44 reg = <0xf1000000 0x1000>;
45 #interrupt-cells = <1>;
46 };
47
48 gmac: ethernet@e0800000 {
49 compatible = "st,spear600-gmac";
50 reg = <0xe0800000 0x8000>;
51 interrupt-parent = <&vic1>;
52 interrupts = <24 23>;
53 interrupt-names = "macirq", "eth_wake_irq";
54 status = "disabled";
55 };
56
57 fsmc: flash@d1800000 {
58 compatible = "st,spear600-fsmc-nand";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 reg = <0xd1800000 0x1000 /* FSMC Register */
62 0xd2000000 0x4000>; /* NAND Base */
63 reg-names = "fsmc_regs", "nand_data";
64 st,ale-off = <0x20000>;
65 st,cle-off = <0x10000>;
66 status = "disabled";
67 };
68
69 smi: flash@fc000000 {
70 compatible = "st,spear600-smi";
71 #address-cells = <1>;
72 #size-cells = <1>;
73 reg = <0xfc000000 0x1000>;
74 interrupt-parent = <&vic1>;
75 interrupts = <12>;
76 status = "disabled";
77 };
78
79 ehci@e1800000 {
80 compatible = "st,spear600-ehci", "usb-ehci";
81 reg = <0xe1800000 0x1000>;
82 interrupt-parent = <&vic1>;
83 interrupts = <27>;
84 status = "disabled";
85 };
86
87 ehci@e2000000 {
88 compatible = "st,spear600-ehci", "usb-ehci";
89 reg = <0xe2000000 0x1000>;
90 interrupt-parent = <&vic1>;
91 interrupts = <29>;
92 status = "disabled";
93 };
94
95 ohci@e1900000 {
96 compatible = "st,spear600-ohci", "usb-ohci";
97 reg = <0xe1900000 0x1000>;
98 interrupt-parent = <&vic1>;
99 interrupts = <26>;
100 status = "disabled";
101 };
102
103 ohci@e2100000 {
104 compatible = "st,spear600-ohci", "usb-ohci";
105 reg = <0xe2100000 0x1000>;
106 interrupt-parent = <&vic1>;
107 interrupts = <28>;
108 status = "disabled";
109 };
110
111 apb {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "simple-bus";
115 ranges = <0xd0000000 0xd0000000 0x30000000>;
116
117 serial@d0000000 {
118 compatible = "arm,pl011", "arm,primecell";
119 reg = <0xd0000000 0x1000>;
120 interrupt-parent = <&vic0>;
121 interrupts = <24>;
122 status = "disabled";
123 };
124
125 serial@d0080000 {
126 compatible = "arm,pl011", "arm,primecell";
127 reg = <0xd0080000 0x1000>;
128 interrupt-parent = <&vic0>;
129 interrupts = <25>;
130 status = "disabled";
131 };
132
133 /* local/cpu GPIO */
134 gpio0: gpio@f0100000 {
135 #gpio-cells = <2>;
136 compatible = "arm,pl061", "arm,primecell";
137 gpio-controller;
138 reg = <0xf0100000 0x1000>;
139 interrupt-parent = <&vic0>;
140 interrupts = <18>;
141 };
142
143 /* basic GPIO */
144 gpio1: gpio@fc980000 {
145 #gpio-cells = <2>;
146 compatible = "arm,pl061", "arm,primecell";
147 gpio-controller;
148 reg = <0xfc980000 0x1000>;
149 interrupt-parent = <&vic1>;
150 interrupts = <19>;
151 };
152
153 /* appl GPIO */
154 gpio2: gpio@d8100000 {
155 #gpio-cells = <2>;
156 compatible = "arm,pl061", "arm,primecell";
157 gpio-controller;
158 reg = <0xd8100000 0x1000>;
159 interrupt-parent = <&vic1>;
160 interrupts = <4>;
161 };
162
163 i2c@d0200000 {
164 #address-cells = <1>;
165 #size-cells = <0>;
166 compatible = "snps,designware-i2c";
167 reg = <0xd0200000 0x1000>;
168 interrupt-parent = <&vic0>;
169 interrupts = <28>;
170 status = "disabled";
171 };
172 };
173 };
174};
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index 70c41fc897d7..ac3fb7558459 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -14,6 +14,22 @@
14 clock-frequency = < 408000000 >; 14 clock-frequency = < 408000000 >;
15 }; 15 };
16 16
17 serial@70006040 {
18 status = "disable";
19 };
20
21 serial@70006200 {
22 status = "disable";
23 };
24
25 serial@70006300 {
26 status = "disable";
27 };
28
29 serial@70006400 {
30 status = "disable";
31 };
32
17 i2c@7000c000 { 33 i2c@7000c000 {
18 clock-frequency = <100000>; 34 clock-frequency = <100000>;
19 }; 35 };
@@ -33,4 +49,22 @@
33 i2c@7000d000 { 49 i2c@7000d000 {
34 clock-frequency = <100000>; 50 clock-frequency = <100000>;
35 }; 51 };
52
53 sdhci@78000000 {
54 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
55 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
56 power-gpios = <&gpio 31 0>; /* gpio PD7 */
57 };
58
59 sdhci@78000200 {
60 status = "disable";
61 };
62
63 sdhci@78000400 {
64 status = "disable";
65 };
66
67 sdhci@78000400 {
68 support-8bit;
69 };
36}; 70};
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 80afa1b70b80..6e8447dc0202 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -10,19 +10,25 @@
10 reg = < 0x00000000 0x40000000 >; 10 reg = < 0x00000000 0x40000000 >;
11 }; 11 };
12 12
13 pmc@7000f400 {
14 nvidia,invert-interrupt;
15 };
16
13 i2c@7000c000 { 17 i2c@7000c000 {
14 clock-frequency = <400000>; 18 clock-frequency = <400000>;
15 19
16 codec: wm8903@1a { 20 wm8903: wm8903@1a {
17 compatible = "wlf,wm8903"; 21 compatible = "wlf,wm8903";
18 reg = <0x1a>; 22 reg = <0x1a>;
19 interrupts = < 347 >; 23 interrupt-parent = <&gpio>;
24 interrupts = < 187 0x04 >;
20 25
21 gpio-controller; 26 gpio-controller;
22 #gpio-cells = <2>; 27 #gpio-cells = <2>;
23 28
24 /* 0x8000 = Not configured */ 29 micdet-cfg = <0>;
25 gpio-cfg = < 0x8000 0x8000 0 0x8000 0x8000 >; 30 micdet-delay = <100>;
31 gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
26 }; 32 };
27 }; 33 };
28 34
@@ -38,13 +44,32 @@
38 clock-frequency = <400000>; 44 clock-frequency = <400000>;
39 }; 45 };
40 46
41 sound { 47 i2s@70002a00 {
42 compatible = "nvidia,harmony-sound", "nvidia,tegra-wm8903"; 48 status = "disable";
49 };
43 50
44 spkr-en-gpios = <&codec 2 0>; 51 sound {
45 hp-det-gpios = <&gpio 178 0>; 52 compatible = "nvidia,tegra-audio-wm8903-harmony",
46 int-mic-en-gpios = <&gpio 184 0>; 53 "nvidia,tegra-audio-wm8903";
47 ext-mic-en-gpios = <&gpio 185 0>; 54 nvidia,model = "NVIDIA Tegra Harmony";
55
56 nvidia,audio-routing =
57 "Headphone Jack", "HPOUTR",
58 "Headphone Jack", "HPOUTL",
59 "Int Spk", "ROP",
60 "Int Spk", "RON",
61 "Int Spk", "LOP",
62 "Int Spk", "LON",
63 "Mic Jack", "MICBIAS",
64 "IN1L", "Mic Jack";
65
66 nvidia,i2s-controller = <&tegra_i2s1>;
67 nvidia,audio-codec = <&wm8903>;
68
69 nvidia,spkr-en-gpios = <&wm8903 2 0>;
70 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
71 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
72 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
48 }; 73 };
49 74
50 serial@70006000 { 75 serial@70006000 {
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 825d2957da0b..6c02abb469d4 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -12,6 +12,13 @@
12 12
13 i2c@7000c000 { 13 i2c@7000c000 {
14 clock-frequency = <400000>; 14 clock-frequency = <400000>;
15
16 alc5632: alc5632@1e {
17 compatible = "realtek,alc5632";
18 reg = <0x1e>;
19 gpio-controller;
20 #gpio-cells = <2>;
21 };
15 }; 22 };
16 23
17 i2c@7000c400 { 24 i2c@7000c400 {
@@ -35,6 +42,35 @@
35 42
36 i2c@7000d000 { 43 i2c@7000d000 {
37 clock-frequency = <400000>; 44 clock-frequency = <400000>;
45
46 adt7461@4c {
47 compatible = "adi,adt7461";
48 reg = <0x4c>;
49 };
50 };
51
52 i2s@70002a00 {
53 status = "disable";
54 };
55
56 sound {
57 compatible = "nvidia,tegra-audio-alc5632-paz00",
58 "nvidia,tegra-audio-alc5632";
59
60 nvidia,model = "Compal PAZ00";
61
62 nvidia,audio-routing =
63 "Int Spk", "SPKOUT",
64 "Int Spk", "SPKOUTN",
65 "Headset Mic", "MICBIAS1",
66 "MIC1", "Headset Mic",
67 "Headset Stereophone", "HPR",
68 "Headset Stereophone", "HPL",
69 "DMICDAT", "Digital Mic";
70
71 nvidia,audio-codec = <&alc5632>;
72 nvidia,i2s-controller = <&tegra_i2s1>;
73 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
38 }; 74 };
39 75
40 serial@70006000 { 76 serial@70006000 {
@@ -74,4 +110,25 @@
74 sdhci@c8000600 { 110 sdhci@c8000600 {
75 support-8bit; 111 support-8bit;
76 }; 112 };
113
114 gpio-keys {
115 compatible = "gpio-keys";
116
117 power {
118 label = "Power";
119 gpios = <&gpio 79 1>; /* gpio PJ7, active low */
120 linux,code = <116>; /* KEY_POWER */
121 gpio-key,wakeup;
122 };
123 };
124
125 gpio-leds {
126 compatible = "gpio-leds";
127
128 wifi {
129 label = "wifi-led";
130 gpios = <&gpio 24 0>;
131 linux,default-trigger = "rfkill0";
132 };
133 };
77}; 134};
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index b55a02e34ba7..dbf1c5a171c2 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -13,6 +13,20 @@
13 13
14 i2c@7000c000 { 14 i2c@7000c000 {
15 clock-frequency = <400000>; 15 clock-frequency = <400000>;
16
17 wm8903: wm8903@1a {
18 compatible = "wlf,wm8903";
19 reg = <0x1a>;
20 interrupt-parent = <&gpio>;
21 interrupts = < 187 0x04 >;
22
23 gpio-controller;
24 #gpio-cells = <2>;
25
26 micdet-cfg = <0>;
27 micdet-delay = <100>;
28 gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
29 };
16 }; 30 };
17 31
18 i2c@7000c400 { 32 i2c@7000c400 {
@@ -32,6 +46,32 @@
32 }; 46 };
33 }; 47 };
34 48
49 i2s@70002a00 {
50 status = "disable";
51 };
52
53 sound {
54 compatible = "nvidia,tegra-audio-wm8903-seaboard",
55 "nvidia,tegra-audio-wm8903";
56 nvidia,model = "NVIDIA Tegra Seaboard";
57
58 nvidia,audio-routing =
59 "Headphone Jack", "HPOUTR",
60 "Headphone Jack", "HPOUTL",
61 "Int Spk", "ROP",
62 "Int Spk", "RON",
63 "Int Spk", "LOP",
64 "Int Spk", "LON",
65 "Mic Jack", "MICBIAS",
66 "IN1R", "Mic Jack";
67
68 nvidia,i2s-controller = <&tegra_i2s1>;
69 nvidia,audio-codec = <&wm8903>;
70
71 nvidia,spkr-en-gpios = <&wm8903 2 0>;
72 nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
73 };
74
35 serial@70006000 { 75 serial@70006000 {
36 status = "disable"; 76 status = "disable";
37 }; 77 };
@@ -72,6 +112,7 @@
72 112
73 usb@c5000000 { 113 usb@c5000000 {
74 nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ 114 nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
115 dr_mode = "otg";
75 }; 116 };
76 117
77 gpio-keys { 118 gpio-keys {
@@ -93,4 +134,42 @@
93 gpio-key,wakeup; 134 gpio-key,wakeup;
94 }; 135 };
95 }; 136 };
137
138 emc@7000f400 {
139 emc-table@190000 {
140 reg = < 190000 >;
141 compatible = "nvidia,tegra20-emc-table";
142 clock-frequency = < 190000 >;
143 nvidia,emc-registers = < 0x0000000c 0x00000026
144 0x00000009 0x00000003 0x00000004 0x00000004
145 0x00000002 0x0000000c 0x00000003 0x00000003
146 0x00000002 0x00000001 0x00000004 0x00000005
147 0x00000004 0x00000009 0x0000000d 0x0000059f
148 0x00000000 0x00000003 0x00000003 0x00000003
149 0x00000003 0x00000001 0x0000000b 0x000000c8
150 0x00000003 0x00000007 0x00000004 0x0000000f
151 0x00000002 0x00000000 0x00000000 0x00000002
152 0x00000000 0x00000000 0x00000083 0xa06204ae
153 0x007dc010 0x00000000 0x00000000 0x00000000
154 0x00000000 0x00000000 0x00000000 0x00000000 >;
155 };
156
157 emc-table@380000 {
158 reg = < 380000 >;
159 compatible = "nvidia,tegra20-emc-table";
160 clock-frequency = < 380000 >;
161 nvidia,emc-registers = < 0x00000017 0x0000004b
162 0x00000012 0x00000006 0x00000004 0x00000005
163 0x00000003 0x0000000c 0x00000006 0x00000006
164 0x00000003 0x00000001 0x00000004 0x00000005
165 0x00000004 0x00000009 0x0000000d 0x00000b5f
166 0x00000000 0x00000003 0x00000003 0x00000006
167 0x00000006 0x00000001 0x00000011 0x000000c8
168 0x00000003 0x0000000e 0x00000007 0x0000000f
169 0x00000002 0x00000000 0x00000000 0x00000002
170 0x00000000 0x00000000 0x00000083 0xe044048b
171 0x007d8010 0x00000000 0x00000000 0x00000000
172 0x00000000 0x00000000 0x00000000 0x00000000 >;
173 };
174 };
96}; 175};
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
index 3b3ee7db99f3..252476867b54 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -26,6 +26,18 @@
26 status = "disable"; 26 status = "disable";
27 }; 27 };
28 28
29 i2s@70002800 {
30 status = "disable";
31 };
32
33 i2s@70002a00 {
34 status = "disable";
35 };
36
37 das@70000c00 {
38 status = "disable";
39 };
40
29 serial@70006000 { 41 serial@70006000 {
30 clock-frequency = < 216000000 >; 42 clock-frequency = < 216000000 >;
31 }; 43 };
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index c7d3b87f29df..2dcff8728e90 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -12,6 +12,20 @@
12 12
13 i2c@7000c000 { 13 i2c@7000c000 {
14 clock-frequency = <400000>; 14 clock-frequency = <400000>;
15
16 wm8903: wm8903@1a {
17 compatible = "wlf,wm8903";
18 reg = <0x1a>;
19 interrupt-parent = <&gpio>;
20 interrupts = < 187 0x04 >;
21
22 gpio-controller;
23 #gpio-cells = <2>;
24
25 micdet-cfg = <0>;
26 micdet-delay = <100>;
27 gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
28 };
15 }; 29 };
16 30
17 i2c@7000c400 { 31 i2c@7000c400 {
@@ -26,6 +40,34 @@
26 clock-frequency = <400000>; 40 clock-frequency = <400000>;
27 }; 41 };
28 42
43 i2s@70002a00 {
44 status = "disable";
45 };
46
47 sound {
48 compatible = "nvidia,tegra-audio-wm8903-ventana",
49 "nvidia,tegra-audio-wm8903";
50 nvidia,model = "NVIDIA Tegra Ventana";
51
52 nvidia,audio-routing =
53 "Headphone Jack", "HPOUTR",
54 "Headphone Jack", "HPOUTL",
55 "Int Spk", "ROP",
56 "Int Spk", "RON",
57 "Int Spk", "LOP",
58 "Int Spk", "LON",
59 "Mic Jack", "MICBIAS",
60 "IN1L", "Mic Jack";
61
62 nvidia,i2s-controller = <&tegra_i2s1>;
63 nvidia,audio-codec = <&wm8903>;
64
65 nvidia,spkr-en-gpios = <&wm8903 2 0>;
66 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
67 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
68 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
69 };
70
29 serial@70006000 { 71 serial@70006000 {
30 status = "disable"; 72 status = "disable";
31 }; 73 };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 3da7afd45322..108e894a8926 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,11 @@
4 compatible = "nvidia,tegra20"; 4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 pmc@7000f400 {
8 compatible = "nvidia,tegra20-pmc";
9 reg = <0x7000e400 0x400>;
10 };
11
7 intc: interrupt-controller@50041000 { 12 intc: interrupt-controller@50041000 {
8 compatible = "arm,cortex-a9-gic"; 13 compatible = "arm,cortex-a9-gic";
9 interrupt-controller; 14 interrupt-controller;
@@ -12,6 +17,33 @@
12 < 0x50040100 0x0100 >; 17 < 0x50040100 0x0100 >;
13 }; 18 };
14 19
20 pmu {
21 compatible = "arm,cortex-a9-pmu";
22 interrupts = <0 56 0x04
23 0 57 0x04>;
24 };
25
26 apbdma: dma@6000a000 {
27 compatible = "nvidia,tegra20-apbdma";
28 reg = <0x6000a000 0x1200>;
29 interrupts = < 0 104 0x04
30 0 105 0x04
31 0 106 0x04
32 0 107 0x04
33 0 108 0x04
34 0 109 0x04
35 0 110 0x04
36 0 111 0x04
37 0 112 0x04
38 0 113 0x04
39 0 114 0x04
40 0 115 0x04
41 0 116 0x04
42 0 117 0x04
43 0 118 0x04
44 0 119 0x04 >;
45 };
46
15 i2c@7000c000 { 47 i2c@7000c000 {
16 #address-cells = <1>; 48 #address-cells = <1>;
17 #size-cells = <0>; 49 #size-cells = <0>;
@@ -44,18 +76,18 @@
44 interrupts = < 0 53 0x04 >; 76 interrupts = < 0 53 0x04 >;
45 }; 77 };
46 78
47 i2s@70002800 { 79 tegra_i2s1: i2s@70002800 {
48 compatible = "nvidia,tegra20-i2s"; 80 compatible = "nvidia,tegra20-i2s";
49 reg = <0x70002800 0x200>; 81 reg = <0x70002800 0x200>;
50 interrupts = < 0 13 0x04 >; 82 interrupts = < 0 13 0x04 >;
51 dma-channel = < 2 >; 83 nvidia,dma-request-selector = < &apbdma 2 >;
52 }; 84 };
53 85
54 i2s@70002a00 { 86 tegra_i2s2: i2s@70002a00 {
55 compatible = "nvidia,tegra20-i2s"; 87 compatible = "nvidia,tegra20-i2s";
56 reg = <0x70002a00 0x200>; 88 reg = <0x70002a00 0x200>;
57 interrupts = < 0 3 0x04 >; 89 interrupts = < 0 3 0x04 >;
58 dma-channel = < 1 >; 90 nvidia,dma-request-selector = < &apbdma 1 >;
59 }; 91 };
60 92
61 das@70000c00 { 93 das@70000c00 {
@@ -75,6 +107,8 @@
75 0 89 0x04 >; 107 0 89 0x04 >;
76 #gpio-cells = <2>; 108 #gpio-cells = <2>;
77 gpio-controller; 109 gpio-controller;
110 #interrupt-cells = <2>;
111 interrupt-controller;
78 }; 112 };
79 113
80 pinmux: pinmux@70000000 { 114 pinmux: pinmux@70000000 {
@@ -120,6 +154,13 @@
120 interrupts = < 0 91 0x04 >; 154 interrupts = < 0 91 0x04 >;
121 }; 155 };
122 156
157 emc@7000f400 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "nvidia,tegra20-emc";
161 reg = <0x7000f400 0x200>;
162 };
163
123 sdhci@c8000000 { 164 sdhci@c8000000 {
124 compatible = "nvidia,tegra20-sdhci"; 165 compatible = "nvidia,tegra20-sdhci";
125 reg = <0xc8000000 0x200>; 166 reg = <0xc8000000 0x200>;
@@ -149,6 +190,7 @@
149 reg = <0xc5000000 0x4000>; 190 reg = <0xc5000000 0x4000>;
150 interrupts = < 0 20 0x04 >; 191 interrupts = < 0 20 0x04 >;
151 phy_type = "utmi"; 192 phy_type = "utmi";
193 nvidia,has-legacy-mode;
152 }; 194 };
153 195
154 usb@c5004000 { 196 usb@c5004000 {
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index ee7db9892e02..62a7b39f1c9a 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,11 @@
4 compatible = "nvidia,tegra30"; 4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 pmc@7000f400 {
8 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
9 reg = <0x7000e400 0x400>;
10 };
11
7 intc: interrupt-controller@50041000 { 12 intc: interrupt-controller@50041000 {
8 compatible = "arm,cortex-a9-gic"; 13 compatible = "arm,cortex-a9-gic";
9 interrupt-controller; 14 interrupt-controller;
@@ -12,6 +17,51 @@
12 < 0x50040100 0x0100 >; 17 < 0x50040100 0x0100 >;
13 }; 18 };
14 19
20 pmu {
21 compatible = "arm,cortex-a9-pmu";
22 interrupts = <0 144 0x04
23 0 145 0x04
24 0 146 0x04
25 0 147 0x04>;
26 };
27
28 apbdma: dma@6000a000 {
29 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
30 reg = <0x6000a000 0x1400>;
31 interrupts = < 0 104 0x04
32 0 105 0x04
33 0 106 0x04
34 0 107 0x04
35 0 108 0x04
36 0 109 0x04
37 0 110 0x04
38 0 111 0x04
39 0 112 0x04
40 0 113 0x04
41 0 114 0x04
42 0 115 0x04
43 0 116 0x04
44 0 117 0x04
45 0 118 0x04
46 0 119 0x04
47 0 128 0x04
48 0 129 0x04
49 0 130 0x04
50 0 131 0x04
51 0 132 0x04
52 0 133 0x04
53 0 134 0x04
54 0 135 0x04
55 0 136 0x04
56 0 137 0x04
57 0 138 0x04
58 0 139 0x04
59 0 140 0x04
60 0 141 0x04
61 0 142 0x04
62 0 143 0x04 >;
63 };
64
15 i2c@7000c000 { 65 i2c@7000c000 {
16 #address-cells = <1>; 66 #address-cells = <1>;
17 #size-cells = <0>; 67 #size-cells = <0>;
@@ -55,9 +105,18 @@
55 gpio: gpio@6000d000 { 105 gpio: gpio@6000d000 {
56 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; 106 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
57 reg = < 0x6000d000 0x1000 >; 107 reg = < 0x6000d000 0x1000 >;
58 interrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >; 108 interrupts = < 0 32 0x04
109 0 33 0x04
110 0 34 0x04
111 0 35 0x04
112 0 55 0x04
113 0 87 0x04
114 0 89 0x04
115 0 125 0x04 >;
59 #gpio-cells = <2>; 116 #gpio-cells = <2>;
60 gpio-controller; 117 gpio-controller;
118 #interrupt-cells = <2>;
119 interrupt-controller;
61 }; 120 };
62 121
63 serial@70006000 { 122 serial@70006000 {
diff --git a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
new file mode 100644
index 000000000000..ad3eca17c436
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
@@ -0,0 +1,96 @@
1/*
2 * calao-dab-mmx.dtsi - Device Tree Include file for Calao DAB-MMX Daughter Board
3 *
4 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/ {
10 ahb {
11 apb {
12 usart1: serial@fffb4000 {
13 status = "okay";
14 };
15
16 usart3: serial@fffd0000 {
17 status = "okay";
18 };
19 };
20 };
21
22 i2c-gpio@0 {
23 status = "okay";
24 };
25
26 leds {
27 compatible = "gpio-leds";
28
29 user_led1 {
30 label = "user_led1";
31 gpios = <&pioB 20 1>;
32 };
33
34/*
35* led already used by mother board but active as high
36* user_led2 {
37* label = "user_led2";
38* gpios = <&pioB 21 1>;
39* };
40*/
41 user_led3 {
42 label = "user_led3";
43 gpios = <&pioB 22 1>;
44 };
45
46 user_led4 {
47 label = "user_led4";
48 gpios = <&pioB 23 1>;
49 };
50
51 red {
52 label = "red";
53 gpios = <&pioB 24 1>;
54 };
55
56 orange {
57 label = "orange";
58 gpios = <&pioB 30 1>;
59 };
60
61 green {
62 label = "green";
63 gpios = <&pioB 31 1>;
64 };
65 };
66
67 gpio_keys {
68 compatible = "gpio-keys";
69 #address-cells = <1>;
70 #size-cells = <0>;
71
72 user_pb1 {
73 label = "user_pb1";
74 gpios = <&pioB 25 1>;
75 linux,code = <0x100>;
76 };
77
78 user_pb2 {
79 label = "user_pb2";
80 gpios = <&pioB 13 1>;
81 linux,code = <0x101>;
82 };
83
84 user_pb3 {
85 label = "user_pb3";
86 gpios = <&pioA 26 1>;
87 linux,code = <0x102>;
88 };
89
90 user_pb4 {
91 label = "user_pb4";
92 gpios = <&pioC 9 1>;
93 linux,code = <0x103>;
94 };
95 };
96};
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index f04b535477f5..3b3c4e0fa79f 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -13,13 +13,24 @@
13 compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; 13 compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
14 14
15 chosen { 15 chosen {
16 bootargs = "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),4M(kernel),120M(rootfs),-(data) root=/dev/mtdblock5 rw rootfstype=ubifs"; 16 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
17 }; 17 };
18 18
19 memory@20000000 { 19 memory@20000000 {
20 reg = <0x20000000 0x4000000>; 20 reg = <0x20000000 0x4000000>;
21 }; 21 };
22 22
23 clocks {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 main_clock: clock@0 {
29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <12000000>;
31 };
32 };
33
23 ahb { 34 ahb {
24 apb { 35 apb {
25 dbgu: serial@fffff200 { 36 dbgu: serial@fffff200 {
@@ -30,6 +41,90 @@
30 phy-mode = "rmii"; 41 phy-mode = "rmii";
31 status = "okay"; 42 status = "okay";
32 }; 43 };
44
45 usb1: gadget@fffa4000 {
46 atmel,vbus-gpio = <&pioC 5 0>;
47 status = "okay";
48 };
49 };
50
51 nand0: nand@40000000 {
52 nand-bus-width = <8>;
53 nand-ecc-mode = "soft";
54 nand-on-flash-bbt;
55 status = "okay";
56
57 at91bootstrap@0 {
58 label = "at91bootstrap";
59 reg = <0x0 0x20000>;
60 };
61
62 barebox@20000 {
63 label = "barebox";
64 reg = <0x20000 0x40000>;
65 };
66
67 bareboxenv@60000 {
68 label = "bareboxenv";
69 reg = <0x60000 0x20000>;
70 };
71
72 bareboxenv2@80000 {
73 label = "bareboxenv2";
74 reg = <0x80000 0x20000>;
75 };
76
77 kernel@a0000 {
78 label = "kernel";
79 reg = <0xa0000 0x400000>;
80 };
81
82 rootfs@4a0000 {
83 label = "rootfs";
84 reg = <0x4a0000 0x7800000>;
85 };
86
87 data@7ca0000 {
88 label = "data";
89 reg = <0x7ca0000 0x8360000>;
90 };
91 };
92
93 usb0: ohci@00500000 {
94 num-ports = <2>;
95 status = "okay";
96 };
97 };
98
99 leds {
100 compatible = "gpio-leds";
101
102 user_led {
103 label = "user_led";
104 gpios = <&pioB 21 1>;
105 linux,default-trigger = "heartbeat";
106 };
107 };
108
109 gpio_keys {
110 compatible = "gpio-keys";
111 #address-cells = <1>;
112 #size-cells = <0>;
113
114 user_pb {
115 label = "user_pb";
116 gpios = <&pioB 10 1>;
117 linux,code = <28>;
118 gpio-key,wakeup;
119 };
120 };
121
122 i2c@0 {
123 status = "okay";
124
125 rv3029c2@56 {
126 compatible = "rv3029c2";
127 reg = <0x56>;
33 }; 128 };
34 }; 129 };
35}; 130};
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
new file mode 100644
index 000000000000..16076e2d0934
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -0,0 +1,201 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * Motherboard Express uATX
5 * V2M-P1
6 *
7 * HBI-0190D
8 *
9 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
10 * Technical Reference Manual)
11 *
12 * WARNING! The hardware described in this file is independent from the
13 * original variant (vexpress-v2m.dtsi), but there is a strong
14 * correspondence between the two configurations.
15 *
16 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
17 * CHANGES TO vexpress-v2m.dtsi!
18 */
19
20/ {
21 aliases {
22 arm,v2m_timer = &v2m_timer01;
23 };
24
25 motherboard {
26 compatible = "simple-bus";
27 arm,v2m-memory-map = "rs1";
28 #address-cells = <2>; /* SMB chipselect number and offset */
29 #size-cells = <1>;
30 #interrupt-cells = <1>;
31
32 flash@0,00000000 {
33 compatible = "arm,vexpress-flash", "cfi-flash";
34 reg = <0 0x00000000 0x04000000>,
35 <4 0x00000000 0x04000000>;
36 bank-width = <4>;
37 };
38
39 psram@1,00000000 {
40 compatible = "arm,vexpress-psram", "mtd-ram";
41 reg = <1 0x00000000 0x02000000>;
42 bank-width = <4>;
43 };
44
45 vram@2,00000000 {
46 compatible = "arm,vexpress-vram";
47 reg = <2 0x00000000 0x00800000>;
48 };
49
50 ethernet@2,02000000 {
51 compatible = "smsc,lan9118", "smsc,lan9115";
52 reg = <2 0x02000000 0x10000>;
53 interrupts = <15>;
54 phy-mode = "mii";
55 reg-io-width = <4>;
56 smsc,irq-active-high;
57 smsc,irq-push-pull;
58 };
59
60 usb@2,03000000 {
61 compatible = "nxp,usb-isp1761";
62 reg = <2 0x03000000 0x20000>;
63 interrupts = <16>;
64 port1-otg;
65 };
66
67 iofpga@3,00000000 {
68 compatible = "arm,amba-bus", "simple-bus";
69 #address-cells = <1>;
70 #size-cells = <1>;
71 ranges = <0 3 0 0x200000>;
72
73 sysreg@010000 {
74 compatible = "arm,vexpress-sysreg";
75 reg = <0x010000 0x1000>;
76 };
77
78 sysctl@020000 {
79 compatible = "arm,sp810", "arm,primecell";
80 reg = <0x020000 0x1000>;
81 };
82
83 /* PCI-E I2C bus */
84 v2m_i2c_pcie: i2c@030000 {
85 compatible = "arm,versatile-i2c";
86 reg = <0x030000 0x1000>;
87
88 #address-cells = <1>;
89 #size-cells = <0>;
90
91 pcie-switch@60 {
92 compatible = "idt,89hpes32h8";
93 reg = <0x60>;
94 };
95 };
96
97 aaci@040000 {
98 compatible = "arm,pl041", "arm,primecell";
99 reg = <0x040000 0x1000>;
100 interrupts = <11>;
101 };
102
103 mmci@050000 {
104 compatible = "arm,pl180", "arm,primecell";
105 reg = <0x050000 0x1000>;
106 interrupts = <9 10>;
107 };
108
109 kmi@060000 {
110 compatible = "arm,pl050", "arm,primecell";
111 reg = <0x060000 0x1000>;
112 interrupts = <12>;
113 };
114
115 kmi@070000 {
116 compatible = "arm,pl050", "arm,primecell";
117 reg = <0x070000 0x1000>;
118 interrupts = <13>;
119 };
120
121 v2m_serial0: uart@090000 {
122 compatible = "arm,pl011", "arm,primecell";
123 reg = <0x090000 0x1000>;
124 interrupts = <5>;
125 };
126
127 v2m_serial1: uart@0a0000 {
128 compatible = "arm,pl011", "arm,primecell";
129 reg = <0x0a0000 0x1000>;
130 interrupts = <6>;
131 };
132
133 v2m_serial2: uart@0b0000 {
134 compatible = "arm,pl011", "arm,primecell";
135 reg = <0x0b0000 0x1000>;
136 interrupts = <7>;
137 };
138
139 v2m_serial3: uart@0c0000 {
140 compatible = "arm,pl011", "arm,primecell";
141 reg = <0x0c0000 0x1000>;
142 interrupts = <8>;
143 };
144
145 wdt@0f0000 {
146 compatible = "arm,sp805", "arm,primecell";
147 reg = <0x0f0000 0x1000>;
148 interrupts = <0>;
149 };
150
151 v2m_timer01: timer@110000 {
152 compatible = "arm,sp804", "arm,primecell";
153 reg = <0x110000 0x1000>;
154 interrupts = <2>;
155 };
156
157 v2m_timer23: timer@120000 {
158 compatible = "arm,sp804", "arm,primecell";
159 reg = <0x120000 0x1000>;
160 };
161
162 /* DVI I2C bus */
163 v2m_i2c_dvi: i2c@160000 {
164 compatible = "arm,versatile-i2c";
165 reg = <0x160000 0x1000>;
166
167 #address-cells = <1>;
168 #size-cells = <0>;
169
170 dvi-transmitter@39 {
171 compatible = "sil,sii9022-tpi", "sil,sii9022";
172 reg = <0x39>;
173 };
174
175 dvi-transmitter@60 {
176 compatible = "sil,sii9022-cpi", "sil,sii9022";
177 reg = <0x60>;
178 };
179 };
180
181 rtc@170000 {
182 compatible = "arm,pl031", "arm,primecell";
183 reg = <0x170000 0x1000>;
184 interrupts = <4>;
185 };
186
187 compact-flash@1a0000 {
188 compatible = "arm,vexpress-cf", "ata-generic";
189 reg = <0x1a0000 0x100
190 0x1a0100 0xf00>;
191 reg-shift = <2>;
192 };
193
194 clcd@1f0000 {
195 compatible = "arm,pl111", "arm,primecell";
196 reg = <0x1f0000 0x1000>;
197 interrupts = <14>;
198 };
199 };
200 };
201};
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
new file mode 100644
index 000000000000..a6c9c7c82d53
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -0,0 +1,200 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * Motherboard Express uATX
5 * V2M-P1
6 *
7 * HBI-0190D
8 *
9 * Original memory map ("Legacy memory map" in the board's
10 * Technical Reference Manual)
11 *
12 * WARNING! The hardware described in this file is independent from the
13 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
14 * correspondence between the two configurations.
15 *
16 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
17 * CHANGES TO vexpress-v2m-rs1.dtsi!
18 */
19
20/ {
21 aliases {
22 arm,v2m_timer = &v2m_timer01;
23 };
24
25 motherboard {
26 compatible = "simple-bus";
27 #address-cells = <2>; /* SMB chipselect number and offset */
28 #size-cells = <1>;
29 #interrupt-cells = <1>;
30
31 flash@0,00000000 {
32 compatible = "arm,vexpress-flash", "cfi-flash";
33 reg = <0 0x00000000 0x04000000>,
34 <1 0x00000000 0x04000000>;
35 bank-width = <4>;
36 };
37
38 psram@2,00000000 {
39 compatible = "arm,vexpress-psram", "mtd-ram";
40 reg = <2 0x00000000 0x02000000>;
41 bank-width = <4>;
42 };
43
44 vram@3,00000000 {
45 compatible = "arm,vexpress-vram";
46 reg = <3 0x00000000 0x00800000>;
47 };
48
49 ethernet@3,02000000 {
50 compatible = "smsc,lan9118", "smsc,lan9115";
51 reg = <3 0x02000000 0x10000>;
52 interrupts = <15>;
53 phy-mode = "mii";
54 reg-io-width = <4>;
55 smsc,irq-active-high;
56 smsc,irq-push-pull;
57 };
58
59 usb@3,03000000 {
60 compatible = "nxp,usb-isp1761";
61 reg = <3 0x03000000 0x20000>;
62 interrupts = <16>;
63 port1-otg;
64 };
65
66 iofpga@7,00000000 {
67 compatible = "arm,amba-bus", "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <1>;
70 ranges = <0 7 0 0x20000>;
71
72 sysreg@00000 {
73 compatible = "arm,vexpress-sysreg";
74 reg = <0x00000 0x1000>;
75 };
76
77 sysctl@01000 {
78 compatible = "arm,sp810", "arm,primecell";
79 reg = <0x01000 0x1000>;
80 };
81
82 /* PCI-E I2C bus */
83 v2m_i2c_pcie: i2c@02000 {
84 compatible = "arm,versatile-i2c";
85 reg = <0x02000 0x1000>;
86
87 #address-cells = <1>;
88 #size-cells = <0>;
89
90 pcie-switch@60 {
91 compatible = "idt,89hpes32h8";
92 reg = <0x60>;
93 };
94 };
95
96 aaci@04000 {
97 compatible = "arm,pl041", "arm,primecell";
98 reg = <0x04000 0x1000>;
99 interrupts = <11>;
100 };
101
102 mmci@05000 {
103 compatible = "arm,pl180", "arm,primecell";
104 reg = <0x05000 0x1000>;
105 interrupts = <9 10>;
106 };
107
108 kmi@06000 {
109 compatible = "arm,pl050", "arm,primecell";
110 reg = <0x06000 0x1000>;
111 interrupts = <12>;
112 };
113
114 kmi@07000 {
115 compatible = "arm,pl050", "arm,primecell";
116 reg = <0x07000 0x1000>;
117 interrupts = <13>;
118 };
119
120 v2m_serial0: uart@09000 {
121 compatible = "arm,pl011", "arm,primecell";
122 reg = <0x09000 0x1000>;
123 interrupts = <5>;
124 };
125
126 v2m_serial1: uart@0a000 {
127 compatible = "arm,pl011", "arm,primecell";
128 reg = <0x0a000 0x1000>;
129 interrupts = <6>;
130 };
131
132 v2m_serial2: uart@0b000 {
133 compatible = "arm,pl011", "arm,primecell";
134 reg = <0x0b000 0x1000>;
135 interrupts = <7>;
136 };
137
138 v2m_serial3: uart@0c000 {
139 compatible = "arm,pl011", "arm,primecell";
140 reg = <0x0c000 0x1000>;
141 interrupts = <8>;
142 };
143
144 wdt@0f000 {
145 compatible = "arm,sp805", "arm,primecell";
146 reg = <0x0f000 0x1000>;
147 interrupts = <0>;
148 };
149
150 v2m_timer01: timer@11000 {
151 compatible = "arm,sp804", "arm,primecell";
152 reg = <0x11000 0x1000>;
153 interrupts = <2>;
154 };
155
156 v2m_timer23: timer@12000 {
157 compatible = "arm,sp804", "arm,primecell";
158 reg = <0x12000 0x1000>;
159 };
160
161 /* DVI I2C bus */
162 v2m_i2c_dvi: i2c@16000 {
163 compatible = "arm,versatile-i2c";
164 reg = <0x16000 0x1000>;
165
166 #address-cells = <1>;
167 #size-cells = <0>;
168
169 dvi-transmitter@39 {
170 compatible = "sil,sii9022-tpi", "sil,sii9022";
171 reg = <0x39>;
172 };
173
174 dvi-transmitter@60 {
175 compatible = "sil,sii9022-cpi", "sil,sii9022";
176 reg = <0x60>;
177 };
178 };
179
180 rtc@17000 {
181 compatible = "arm,pl031", "arm,primecell";
182 reg = <0x17000 0x1000>;
183 interrupts = <4>;
184 };
185
186 compact-flash@1a000 {
187 compatible = "arm,vexpress-cf", "ata-generic";
188 reg = <0x1a000 0x100
189 0x1a100 0xf00>;
190 reg-shift = <2>;
191 };
192
193 clcd@1f000 {
194 compatible = "arm,pl111", "arm,primecell";
195 reg = <0x1f000 0x1000>;
196 interrupts = <14>;
197 };
198 };
199 };
200};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
new file mode 100644
index 000000000000..941b161ab78c
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -0,0 +1,157 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A15x2 (version with Test Chip 1)
5 * Cortex-A15 MPCore (V2P-CA15)
6 *
7 * HBI-0237A
8 */
9
10/dts-v1/;
11
12/ {
13 model = "V2P-CA15";
14 arm,hbi = <0x237>;
15 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 chosen { };
21
22 aliases {
23 serial0 = &v2m_serial0;
24 serial1 = &v2m_serial1;
25 serial2 = &v2m_serial2;
26 serial3 = &v2m_serial3;
27 i2c0 = &v2m_i2c_dvi;
28 i2c1 = &v2m_i2c_pcie;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a15";
38 reg = <0>;
39 };
40
41 cpu@1 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a15";
44 reg = <1>;
45 };
46 };
47
48 memory@80000000 {
49 device_type = "memory";
50 reg = <0x80000000 0x40000000>;
51 };
52
53 hdlcd@2b000000 {
54 compatible = "arm,hdlcd";
55 reg = <0x2b000000 0x1000>;
56 interrupts = <0 85 4>;
57 };
58
59 memory-controller@2b0a0000 {
60 compatible = "arm,pl341", "arm,primecell";
61 reg = <0x2b0a0000 0x1000>;
62 };
63
64 wdt@2b060000 {
65 compatible = "arm,sp805", "arm,primecell";
66 reg = <0x2b060000 0x1000>;
67 interrupts = <98>;
68 };
69
70 gic: interrupt-controller@2c001000 {
71 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
72 #interrupt-cells = <3>;
73 #address-cells = <0>;
74 interrupt-controller;
75 reg = <0x2c001000 0x1000>,
76 <0x2c002000 0x100>;
77 };
78
79 memory-controller@7ffd0000 {
80 compatible = "arm,pl354", "arm,primecell";
81 reg = <0x7ffd0000 0x1000>;
82 interrupts = <0 86 4>,
83 <0 87 4>;
84 };
85
86 dma@7ffb0000 {
87 compatible = "arm,pl330", "arm,primecell";
88 reg = <0x7ffb0000 0x1000>;
89 interrupts = <0 92 4>,
90 <0 88 4>,
91 <0 89 4>,
92 <0 90 4>,
93 <0 91 4>;
94 };
95
96 pmu {
97 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
98 interrupts = <0 68 4>,
99 <0 69 4>;
100 };
101
102 motherboard {
103 ranges = <0 0 0x08000000 0x04000000>,
104 <1 0 0x14000000 0x04000000>,
105 <2 0 0x18000000 0x04000000>,
106 <3 0 0x1c000000 0x04000000>,
107 <4 0 0x0c000000 0x04000000>,
108 <5 0 0x10000000 0x04000000>;
109
110 interrupt-map-mask = <0 0 63>;
111 interrupt-map = <0 0 0 &gic 0 0 4>,
112 <0 0 1 &gic 0 1 4>,
113 <0 0 2 &gic 0 2 4>,
114 <0 0 3 &gic 0 3 4>,
115 <0 0 4 &gic 0 4 4>,
116 <0 0 5 &gic 0 5 4>,
117 <0 0 6 &gic 0 6 4>,
118 <0 0 7 &gic 0 7 4>,
119 <0 0 8 &gic 0 8 4>,
120 <0 0 9 &gic 0 9 4>,
121 <0 0 10 &gic 0 10 4>,
122 <0 0 11 &gic 0 11 4>,
123 <0 0 12 &gic 0 12 4>,
124 <0 0 13 &gic 0 13 4>,
125 <0 0 14 &gic 0 14 4>,
126 <0 0 15 &gic 0 15 4>,
127 <0 0 16 &gic 0 16 4>,
128 <0 0 17 &gic 0 17 4>,
129 <0 0 18 &gic 0 18 4>,
130 <0 0 19 &gic 0 19 4>,
131 <0 0 20 &gic 0 20 4>,
132 <0 0 21 &gic 0 21 4>,
133 <0 0 22 &gic 0 22 4>,
134 <0 0 23 &gic 0 23 4>,
135 <0 0 24 &gic 0 24 4>,
136 <0 0 25 &gic 0 25 4>,
137 <0 0 26 &gic 0 26 4>,
138 <0 0 27 &gic 0 27 4>,
139 <0 0 28 &gic 0 28 4>,
140 <0 0 29 &gic 0 29 4>,
141 <0 0 30 &gic 0 30 4>,
142 <0 0 31 &gic 0 31 4>,
143 <0 0 32 &gic 0 32 4>,
144 <0 0 33 &gic 0 33 4>,
145 <0 0 34 &gic 0 34 4>,
146 <0 0 35 &gic 0 35 4>,
147 <0 0 36 &gic 0 36 4>,
148 <0 0 37 &gic 0 37 4>,
149 <0 0 38 &gic 0 38 4>,
150 <0 0 39 &gic 0 39 4>,
151 <0 0 40 &gic 0 40 4>,
152 <0 0 41 &gic 0 41 4>,
153 <0 0 42 &gic 0 42 4>;
154 };
155};
156
157/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
new file mode 100644
index 000000000000..6905e66d4748
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -0,0 +1,162 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A5x2
5 * Cortex-A5 MPCore (V2P-CA5s)
6 *
7 * HBI-0225B
8 */
9
10/dts-v1/;
11
12/ {
13 model = "V2P-CA5s";
14 arm,hbi = <0x225>;
15 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 chosen { };
21
22 aliases {
23 serial0 = &v2m_serial0;
24 serial1 = &v2m_serial1;
25 serial2 = &v2m_serial2;
26 serial3 = &v2m_serial3;
27 i2c0 = &v2m_i2c_dvi;
28 i2c1 = &v2m_i2c_pcie;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a5";
38 reg = <0>;
39 next-level-cache = <&L2>;
40 };
41
42 cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a5";
45 reg = <1>;
46 next-level-cache = <&L2>;
47 };
48 };
49
50 memory@80000000 {
51 device_type = "memory";
52 reg = <0x80000000 0x40000000>;
53 };
54
55 hdlcd@2a110000 {
56 compatible = "arm,hdlcd";
57 reg = <0x2a110000 0x1000>;
58 interrupts = <0 85 4>;
59 };
60
61 memory-controller@2a150000 {
62 compatible = "arm,pl341", "arm,primecell";
63 reg = <0x2a150000 0x1000>;
64 };
65
66 memory-controller@2a190000 {
67 compatible = "arm,pl354", "arm,primecell";
68 reg = <0x2a190000 0x1000>;
69 interrupts = <0 86 4>,
70 <0 87 4>;
71 };
72
73 scu@2c000000 {
74 compatible = "arm,cortex-a5-scu";
75 reg = <0x2c000000 0x58>;
76 };
77
78 timer@2c000600 {
79 compatible = "arm,cortex-a5-twd-timer";
80 reg = <0x2c000600 0x38>;
81 interrupts = <1 2 0x304>,
82 <1 3 0x304>;
83 };
84
85 gic: interrupt-controller@2c001000 {
86 compatible = "arm,corex-a5-gic", "arm,cortex-a9-gic";
87 #interrupt-cells = <3>;
88 #address-cells = <0>;
89 interrupt-controller;
90 reg = <0x2c001000 0x1000>,
91 <0x2c000100 0x100>;
92 };
93
94 L2: cache-controller@2c0f0000 {
95 compatible = "arm,pl310-cache";
96 reg = <0x2c0f0000 0x1000>;
97 interrupts = <0 84 4>;
98 cache-level = <2>;
99 };
100
101 pmu {
102 compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu";
103 interrupts = <0 68 4>,
104 <0 69 4>;
105 };
106
107 motherboard {
108 ranges = <0 0 0x08000000 0x04000000>,
109 <1 0 0x14000000 0x04000000>,
110 <2 0 0x18000000 0x04000000>,
111 <3 0 0x1c000000 0x04000000>,
112 <4 0 0x0c000000 0x04000000>,
113 <5 0 0x10000000 0x04000000>;
114
115 interrupt-map-mask = <0 0 63>;
116 interrupt-map = <0 0 0 &gic 0 0 4>,
117 <0 0 1 &gic 0 1 4>,
118 <0 0 2 &gic 0 2 4>,
119 <0 0 3 &gic 0 3 4>,
120 <0 0 4 &gic 0 4 4>,
121 <0 0 5 &gic 0 5 4>,
122 <0 0 6 &gic 0 6 4>,
123 <0 0 7 &gic 0 7 4>,
124 <0 0 8 &gic 0 8 4>,
125 <0 0 9 &gic 0 9 4>,
126 <0 0 10 &gic 0 10 4>,
127 <0 0 11 &gic 0 11 4>,
128 <0 0 12 &gic 0 12 4>,
129 <0 0 13 &gic 0 13 4>,
130 <0 0 14 &gic 0 14 4>,
131 <0 0 15 &gic 0 15 4>,
132 <0 0 16 &gic 0 16 4>,
133 <0 0 17 &gic 0 17 4>,
134 <0 0 18 &gic 0 18 4>,
135 <0 0 19 &gic 0 19 4>,
136 <0 0 20 &gic 0 20 4>,
137 <0 0 21 &gic 0 21 4>,
138 <0 0 22 &gic 0 22 4>,
139 <0 0 23 &gic 0 23 4>,
140 <0 0 24 &gic 0 24 4>,
141 <0 0 25 &gic 0 25 4>,
142 <0 0 26 &gic 0 26 4>,
143 <0 0 27 &gic 0 27 4>,
144 <0 0 28 &gic 0 28 4>,
145 <0 0 29 &gic 0 29 4>,
146 <0 0 30 &gic 0 30 4>,
147 <0 0 31 &gic 0 31 4>,
148 <0 0 32 &gic 0 32 4>,
149 <0 0 33 &gic 0 33 4>,
150 <0 0 34 &gic 0 34 4>,
151 <0 0 35 &gic 0 35 4>,
152 <0 0 36 &gic 0 36 4>,
153 <0 0 37 &gic 0 37 4>,
154 <0 0 38 &gic 0 38 4>,
155 <0 0 39 &gic 0 39 4>,
156 <0 0 40 &gic 0 40 4>,
157 <0 0 41 &gic 0 41 4>,
158 <0 0 42 &gic 0 42 4>;
159 };
160};
161
162/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
new file mode 100644
index 000000000000..da778693be54
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -0,0 +1,192 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A9x4
5 * Cortex-A9 MPCore (V2P-CA9)
6 *
7 * HBI-0191B
8 */
9
10/dts-v1/;
11
12/ {
13 model = "V2P-CA9";
14 arm,hbi = <0x191>;
15 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 chosen { };
21
22 aliases {
23 serial0 = &v2m_serial0;
24 serial1 = &v2m_serial1;
25 serial2 = &v2m_serial2;
26 serial3 = &v2m_serial3;
27 i2c0 = &v2m_i2c_dvi;
28 i2c1 = &v2m_i2c_pcie;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a9";
38 reg = <0>;
39 next-level-cache = <&L2>;
40 };
41
42 cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a9";
45 reg = <1>;
46 next-level-cache = <&L2>;
47 };
48
49 cpu@2 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a9";
52 reg = <2>;
53 next-level-cache = <&L2>;
54 };
55
56 cpu@3 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a9";
59 reg = <3>;
60 next-level-cache = <&L2>;
61 };
62 };
63
64 memory@60000000 {
65 device_type = "memory";
66 reg = <0x60000000 0x40000000>;
67 };
68
69 clcd@10020000 {
70 compatible = "arm,pl111", "arm,primecell";
71 reg = <0x10020000 0x1000>;
72 interrupts = <0 44 4>;
73 };
74
75 memory-controller@100e0000 {
76 compatible = "arm,pl341", "arm,primecell";
77 reg = <0x100e0000 0x1000>;
78 };
79
80 memory-controller@100e1000 {
81 compatible = "arm,pl354", "arm,primecell";
82 reg = <0x100e1000 0x1000>;
83 interrupts = <0 45 4>,
84 <0 46 4>;
85 };
86
87 timer@100e4000 {
88 compatible = "arm,sp804", "arm,primecell";
89 reg = <0x100e4000 0x1000>;
90 interrupts = <0 48 4>,
91 <0 49 4>;
92 };
93
94 watchdog@100e5000 {
95 compatible = "arm,sp805", "arm,primecell";
96 reg = <0x100e5000 0x1000>;
97 interrupts = <0 51 4>;
98 };
99
100 scu@1e000000 {
101 compatible = "arm,cortex-a9-scu";
102 reg = <0x1e000000 0x58>;
103 };
104
105 timer@1e000600 {
106 compatible = "arm,cortex-a9-twd-timer";
107 reg = <0x1e000600 0x20>;
108 interrupts = <1 2 0xf04>,
109 <1 3 0xf04>;
110 };
111
112 gic: interrupt-controller@1e001000 {
113 compatible = "arm,cortex-a9-gic";
114 #interrupt-cells = <3>;
115 #address-cells = <0>;
116 interrupt-controller;
117 reg = <0x1e001000 0x1000>,
118 <0x1e000100 0x100>;
119 };
120
121 L2: cache-controller@1e00a000 {
122 compatible = "arm,pl310-cache";
123 reg = <0x1e00a000 0x1000>;
124 interrupts = <0 43 4>;
125 cache-level = <2>;
126 arm,data-latency = <1 1 1>;
127 arm,tag-latency = <1 1 1>;
128 };
129
130 pmu {
131 compatible = "arm,cortex-a9-pmu";
132 interrupts = <0 60 4>,
133 <0 61 4>,
134 <0 62 4>,
135 <0 63 4>;
136 };
137
138 motherboard {
139 ranges = <0 0 0x40000000 0x04000000>,
140 <1 0 0x44000000 0x04000000>,
141 <2 0 0x48000000 0x04000000>,
142 <3 0 0x4c000000 0x04000000>,
143 <7 0 0x10000000 0x00020000>;
144
145 interrupt-map-mask = <0 0 63>;
146 interrupt-map = <0 0 0 &gic 0 0 4>,
147 <0 0 1 &gic 0 1 4>,
148 <0 0 2 &gic 0 2 4>,
149 <0 0 3 &gic 0 3 4>,
150 <0 0 4 &gic 0 4 4>,
151 <0 0 5 &gic 0 5 4>,
152 <0 0 6 &gic 0 6 4>,
153 <0 0 7 &gic 0 7 4>,
154 <0 0 8 &gic 0 8 4>,
155 <0 0 9 &gic 0 9 4>,
156 <0 0 10 &gic 0 10 4>,
157 <0 0 11 &gic 0 11 4>,
158 <0 0 12 &gic 0 12 4>,
159 <0 0 13 &gic 0 13 4>,
160 <0 0 14 &gic 0 14 4>,
161 <0 0 15 &gic 0 15 4>,
162 <0 0 16 &gic 0 16 4>,
163 <0 0 17 &gic 0 17 4>,
164 <0 0 18 &gic 0 18 4>,
165 <0 0 19 &gic 0 19 4>,
166 <0 0 20 &gic 0 20 4>,
167 <0 0 21 &gic 0 21 4>,
168 <0 0 22 &gic 0 22 4>,
169 <0 0 23 &gic 0 23 4>,
170 <0 0 24 &gic 0 24 4>,
171 <0 0 25 &gic 0 25 4>,
172 <0 0 26 &gic 0 26 4>,
173 <0 0 27 &gic 0 27 4>,
174 <0 0 28 &gic 0 28 4>,
175 <0 0 29 &gic 0 29 4>,
176 <0 0 30 &gic 0 30 4>,
177 <0 0 31 &gic 0 31 4>,
178 <0 0 32 &gic 0 32 4>,
179 <0 0 33 &gic 0 33 4>,
180 <0 0 34 &gic 0 34 4>,
181 <0 0 35 &gic 0 35 4>,
182 <0 0 36 &gic 0 36 4>,
183 <0 0 37 &gic 0 37 4>,
184 <0 0 38 &gic 0 38 4>,
185 <0 0 39 &gic 0 39 4>,
186 <0 0 40 &gic 0 40 4>,
187 <0 0 41 &gic 0 41 4>,
188 <0 0 42 &gic 0 42 4>;
189 };
190};
191
192/include/ "vexpress-v2m.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-06 22:04:03 -0500