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-rw-r--r--arch/arm/boot/compressed/.gitignore1
-rw-r--r--arch/arm/boot/compressed/Makefile13
-rw-r--r--arch/arm/boot/compressed/head.S93
3 files changed, 100 insertions, 7 deletions
diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore
index aefee20cbf98..b15f927a5926 100644
--- a/arch/arm/boot/compressed/.gitignore
+++ b/arch/arm/boot/compressed/.gitignore
@@ -1 +1,2 @@
1piggy.gz 1piggy.gz
2font.c
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index adddc7131685..a1f1691b67fe 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -6,15 +6,13 @@
6 6
7HEAD = head.o 7HEAD = head.o
8OBJS = misc.o 8OBJS = misc.o
9FONTC = drivers/video/console/font_acorn_8x8.c 9FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c
10
11FONT = $(addprefix ../../../../drivers/video/console/, font_acorn_8x8.o)
12 10
13# 11#
14# Architecture dependencies 12# Architecture dependencies
15# 13#
16ifeq ($(CONFIG_ARCH_ACORN),y) 14ifeq ($(CONFIG_ARCH_ACORN),y)
17OBJS += ll_char_wr.o $(FONT) 15OBJS += ll_char_wr.o font.o
18endif 16endif
19 17
20ifeq ($(CONFIG_ARCH_SHARK),y) 18ifeq ($(CONFIG_ARCH_SHARK),y)
@@ -73,7 +71,7 @@ endif
73 71
74SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/ 72SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/
75 73
76targets := vmlinux vmlinux.lds piggy.gz piggy.o $(FONT) \ 74targets := vmlinux vmlinux.lds piggy.gz piggy.o font.o font.c \
77 head.o misc.o $(OBJS) 75 head.o misc.o $(OBJS)
78EXTRA_CFLAGS := -fpic 76EXTRA_CFLAGS := -fpic
79EXTRA_AFLAGS := 77EXTRA_AFLAGS :=
@@ -105,7 +103,10 @@ $(obj)/piggy.gz: $(obj)/../Image FORCE
105 103
106$(obj)/piggy.o: $(obj)/piggy.gz FORCE 104$(obj)/piggy.o: $(obj)/piggy.gz FORCE
107 105
108CFLAGS_font_acorn_8x8.o := -Dstatic= 106CFLAGS_font.o := -Dstatic=
107
108$(obj)/font.c: $(FONTC)
109 $(call cmd,shipped)
109 110
110$(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile .config 111$(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile .config
111 @sed "$(SEDFLAGS)" < $< > $@ 112 @sed "$(SEDFLAGS)" < $< > $@
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 680ea6ed77b8..d7fb5ee1637e 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -436,6 +436,28 @@ __armv4_mmu_cache_on:
436 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 436 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
437 mov pc, r12 437 mov pc, r12
438 438
439__armv7_mmu_cache_on:
440 mov r12, lr
441 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
442 tst r11, #0xf @ VMSA
443 blne __setup_mmu
444 mov r0, #0
445 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
446 tst r11, #0xf @ VMSA
447 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
448 mrc p15, 0, r0, c1, c0, 0 @ read control reg
449 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
450 orr r0, r0, #0x003c @ write buffer
451 orrne r0, r0, #1 @ MMU enabled
452 movne r1, #-1
453 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
454 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
455 mcr p15, 0, r0, c1, c0, 0 @ load control register
456 mrc p15, 0, r0, c1, c0, 0 @ and read it back
457 mov r0, #0
458 mcr p15, 0, r0, c7, c5, 4 @ ISB
459 mov pc, r12
460
439__arm6_mmu_cache_on: 461__arm6_mmu_cache_on:
440 mov r12, lr 462 mov r12, lr
441 bl __setup_mmu 463 bl __setup_mmu
@@ -622,11 +644,17 @@ proc_types:
622 b __armv4_mmu_cache_flush 644 b __armv4_mmu_cache_flush
623 645
624 .word 0x0007b000 @ ARMv6 646 .word 0x0007b000 @ ARMv6
625 .word 0x0007f000 647 .word 0x000ff000
626 b __armv4_mmu_cache_on 648 b __armv4_mmu_cache_on
627 b __armv4_mmu_cache_off 649 b __armv4_mmu_cache_off
628 b __armv6_mmu_cache_flush 650 b __armv6_mmu_cache_flush
629 651
652 .word 0x000f0000 @ new CPU Id
653 .word 0x000f0000
654 b __armv7_mmu_cache_on
655 b __armv7_mmu_cache_off
656 b __armv7_mmu_cache_flush
657
630 .word 0 @ unrecognised type 658 .word 0 @ unrecognised type
631 .word 0 659 .word 0
632 mov pc, lr 660 mov pc, lr
@@ -674,6 +702,16 @@ __armv4_mmu_cache_off:
674 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 702 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
675 mov pc, lr 703 mov pc, lr
676 704
705__armv7_mmu_cache_off:
706 mrc p15, 0, r0, c1, c0
707 bic r0, r0, #0x000d
708 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
709 mov r12, lr
710 bl __armv7_mmu_cache_flush
711 mov r0, #0
712 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
713 mov pc, r12
714
677__arm6_mmu_cache_off: 715__arm6_mmu_cache_off:
678 mov r0, #0x00000030 @ ARM6 control reg. 716 mov r0, #0x00000030 @ ARM6 control reg.
679 b __armv3_mmu_cache_off 717 b __armv3_mmu_cache_off
@@ -730,6 +768,59 @@ __armv6_mmu_cache_flush:
730 mcr p15, 0, r1, c7, c10, 4 @ drain WB 768 mcr p15, 0, r1, c7, c10, 4 @ drain WB
731 mov pc, lr 769 mov pc, lr
732 770
771__armv7_mmu_cache_flush:
772 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
773 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
774 beq hierarchical
775 mov r10, #0
776 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
777 b iflush
778hierarchical:
779 stmfd sp!, {r0-r5, r7, r9-r11}
780 mrc p15, 1, r0, c0, c0, 1 @ read clidr
781 ands r3, r0, #0x7000000 @ extract loc from clidr
782 mov r3, r3, lsr #23 @ left align loc bit field
783 beq finished @ if loc is 0, then no need to clean
784 mov r10, #0 @ start clean at cache level 0
785loop1:
786 add r2, r10, r10, lsr #1 @ work out 3x current cache level
787 mov r1, r0, lsr r2 @ extract cache type bits from clidr
788 and r1, r1, #7 @ mask of the bits for current cache only
789 cmp r1, #2 @ see what cache we have at this level
790 blt skip @ skip if no cache, or just i-cache
791 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
792 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
793 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
794 and r2, r1, #7 @ extract the length of the cache lines
795 add r2, r2, #4 @ add 4 (line length offset)
796 ldr r4, =0x3ff
797 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
798 .word 0xe16f5f14 @ clz r5, r4 - find bit position of way size increment
799 ldr r7, =0x7fff
800 ands r7, r7, r1, lsr #13 @ extract max number of the index size
801loop2:
802 mov r9, r4 @ create working copy of max way size
803loop3:
804 orr r11, r10, r9, lsl r5 @ factor way and cache number into r11
805 orr r11, r11, r7, lsl r2 @ factor index number into r11
806 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
807 subs r9, r9, #1 @ decrement the way
808 bge loop3
809 subs r7, r7, #1 @ decrement the index
810 bge loop2
811skip:
812 add r10, r10, #2 @ increment cache number
813 cmp r3, r10
814 bgt loop1
815finished:
816 mov r10, #0 @ swith back to cache level 0
817 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
818 ldmfd sp!, {r0-r5, r7, r9-r11}
819iflush:
820 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
821 mcr p15, 0, r10, c7, c10, 4 @ drain WB
822 mov pc, lr
823
733__armv4_mmu_cache_flush: 824__armv4_mmu_cache_flush:
734 mov r2, #64*1024 @ default: 32K dcache size (*2) 825 mov r2, #64*1024 @ default: 32K dcache size (*2)
735 mov r11, #32 @ default: 32 byte line size 826 mov r11, #32 @ default: 32 byte line size
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 13:11:18 -0500