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-rw-r--r--arch/arm/boot/dts/at91sam9g20.dtsi7
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi7
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts5
-rw-r--r--arch/arm/boot/dts/exynos4210-origen.dts137
-rw-r--r--arch/arm/boot/dts/exynos4210-smdkv310.dts182
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi397
-rw-r--r--arch/arm/boot/dts/highbank.dts12
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts17
-rw-r--r--arch/arm/boot/dts/imx51.dtsi20
-rw-r--r--arch/arm/boot/dts/imx53-ard.dts18
-rw-r--r--arch/arm/boot/dts/imx53-evk.dts17
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts18
-rw-r--r--arch/arm/boot/dts/imx53-smd.dts19
-rw-r--r--arch/arm/boot/dts/imx53.dtsi34
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts (renamed from arch/arm/boot/dts/imx6q-sabreauto.dts)12
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts49
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi34
-rw-r--r--arch/arm/boot/dts/omap2.dtsi67
-rw-r--r--arch/arm/boot/dts/omap3.dtsi31
-rw-r--r--arch/arm/boot/dts/omap4.dtsi28
-rw-r--r--arch/arm/boot/dts/tegra-cardhu.dts36
-rw-r--r--arch/arm/boot/dts/tegra-harmony.dts29
-rw-r--r--arch/arm/boot/dts/tegra-paz00.dts77
-rw-r--r--arch/arm/boot/dts/tegra-seaboard.dts74
-rw-r--r--arch/arm/boot/dts/tegra-trimslice.dts65
-rw-r--r--arch/arm/boot/dts/tegra-ventana.dts45
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi71
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi127
-rw-r--r--arch/arm/boot/dts/testcases/tests-phandle.dtsi37
-rw-r--r--arch/arm/boot/dts/testcases/tests.dtsi1
-rw-r--r--arch/arm/boot/dts/usb_a9g20.dts5
-rw-r--r--arch/arm/boot/dts/versatile-pb.dts2
32 files changed, 1544 insertions, 136 deletions
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index aeef04269cf8..07603b8c9503 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -114,6 +114,13 @@
114 atmel,use-dma-tx; 114 atmel,use-dma-tx;
115 status = "disabled"; 115 status = "disabled";
116 }; 116 };
117
118 macb0: ethernet@fffc4000 {
119 compatible = "cdns,at32ap7000-macb", "cdns,macb";
120 reg = <0xfffc4000 0x100>;
121 interrupts = <21>;
122 status = "disabled";
123 };
117 }; 124 };
118 }; 125 };
119}; 126};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index db6a45202f26..fffa005300a4 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -101,6 +101,13 @@
101 atmel,use-dma-tx; 101 atmel,use-dma-tx;
102 status = "disabled"; 102 status = "disabled";
103 }; 103 };
104
105 macb0: ethernet@fffbc000 {
106 compatible = "cdns,at32ap7000-macb", "cdns,macb";
107 reg = <0xfffbc000 0x100>;
108 interrupts = <25>;
109 status = "disabled";
110 };
104 }; 111 };
105 }; 112 };
106}; 113};
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 85b34f59cd82..a387e7704ce1 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -30,6 +30,11 @@
30 usart1: serial@fff90000 { 30 usart1: serial@fff90000 {
31 status = "okay"; 31 status = "okay";
32 }; 32 };
33
34 macb0: ethernet@fffbc000 {
35 phy-mode = "rmii";
36 status = "okay";
37 };
33 }; 38 };
34 }; 39 };
35}; 40};
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
new file mode 100644
index 000000000000..b8c476384eef
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -0,0 +1,137 @@
1/*
2 * Samsung's Exynos4210 based Origen board device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Device tree source file for Insignal's Origen board which is based on
10 * Samsung's Exynos4210 SoC.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17/dts-v1/;
18/include/ "exynos4210.dtsi"
19
20/ {
21 model = "Insignal Origen evaluation board based on Exynos4210";
22 compatible = "insignal,origen", "samsung,exynos4210";
23
24 memory {
25 reg = <0x40000000 0x40000000>;
26 };
27
28 chosen {
29 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
30 };
31
32 sdhci@12530000 {
33 samsung,sdhci-bus-width = <4>;
34 linux,mmc_cap_4_bit_data;
35 samsung,sdhci-cd-internal;
36 gpio-cd = <&gpk2 2 2 3 3>;
37 gpios = <&gpk2 0 2 0 3>,
38 <&gpk2 1 2 0 3>,
39 <&gpk2 3 2 3 3>,
40 <&gpk2 4 2 3 3>,
41 <&gpk2 5 2 3 3>,
42 <&gpk2 6 2 3 3>;
43 };
44
45 sdhci@12510000 {
46 samsung,sdhci-bus-width = <4>;
47 linux,mmc_cap_4_bit_data;
48 samsung,sdhci-cd-internal;
49 gpio-cd = <&gpk0 2 2 3 3>;
50 gpios = <&gpk0 0 2 0 3>,
51 <&gpk0 1 2 0 3>,
52 <&gpk0 3 2 3 3>,
53 <&gpk0 4 2 3 3>,
54 <&gpk0 5 2 3 3>,
55 <&gpk0 6 2 3 3>;
56 };
57
58 gpio_keys {
59 compatible = "gpio-keys";
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 up {
64 label = "Up";
65 gpios = <&gpx2 0 0 0 2>;
66 linux,code = <103>;
67 };
68
69 down {
70 label = "Down";
71 gpios = <&gpx2 1 0 0 2>;
72 linux,code = <108>;
73 };
74
75 back {
76 label = "Back";
77 gpios = <&gpx1 7 0 0 2>;
78 linux,code = <158>;
79 };
80
81 home {
82 label = "Home";
83 gpios = <&gpx1 6 0 0 2>;
84 linux,code = <102>;
85 };
86
87 menu {
88 label = "Menu";
89 gpios = <&gpx1 5 0 0 2>;
90 linux,code = <139>;
91 };
92 };
93
94 keypad@100A0000 {
95 status = "disabled";
96 };
97
98 sdhci@12520000 {
99 status = "disabled";
100 };
101
102 sdhci@12540000 {
103 status = "disabled";
104 };
105
106 i2c@13860000 {
107 status = "disabled";
108 };
109
110 i2c@13870000 {
111 status = "disabled";
112 };
113
114 i2c@13880000 {
115 status = "disabled";
116 };
117
118 i2c@13890000 {
119 status = "disabled";
120 };
121
122 i2c@138A0000 {
123 status = "disabled";
124 };
125
126 i2c@138B0000 {
127 status = "disabled";
128 };
129
130 i2c@138C0000 {
131 status = "disabled";
132 };
133
134 i2c@138D0000 {
135 status = "disabled";
136 };
137};
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
new file mode 100644
index 000000000000..27afc8e535ca
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -0,0 +1,182 @@
1/*
2 * Samsung's Exynos4210 based SMDKV310 board device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Device tree source file for Samsung's SMDKV310 board which is based on
10 * Samsung's Exynos4210 SoC.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17/dts-v1/;
18/include/ "exynos4210.dtsi"
19
20/ {
21 model = "Samsung smdkv310 evaluation board based on Exynos4210";
22 compatible = "samsung,smdkv310", "samsung,exynos4210";
23
24 memory {
25 reg = <0x40000000 0x80000000>;
26 };
27
28 chosen {
29 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
30 };
31
32 sdhci@12530000 {
33 samsung,sdhci-bus-width = <4>;
34 linux,mmc_cap_4_bit_data;
35 samsung,sdhci-cd-internal;
36 gpio-cd = <&gpk2 2 2 3 3>;
37 gpios = <&gpk2 0 2 0 3>,
38 <&gpk2 1 2 0 3>,
39 <&gpk2 3 2 3 3>,
40 <&gpk2 4 2 3 3>,
41 <&gpk2 5 2 3 3>,
42 <&gpk2 6 2 3 3>;
43 };
44
45 keypad@100A0000 {
46 samsung,keypad-num-rows = <2>;
47 samsung,keypad-num-columns = <8>;
48 linux,keypad-no-autorepeat;
49 linux,keypad-wakeup;
50
51 row-gpios = <&gpx2 0 3 3 0>,
52 <&gpx2 1 3 3 0>;
53
54 col-gpios = <&gpx1 0 3 0 0>,
55 <&gpx1 1 3 0 0>,
56 <&gpx1 2 3 0 0>,
57 <&gpx1 3 3 0 0>,
58 <&gpx1 4 3 0 0>,
59 <&gpx1 5 3 0 0>,
60 <&gpx1 6 3 0 0>,
61 <&gpx1 7 3 0 0>;
62
63 key_1 {
64 keypad,row = <0>;
65 keypad,column = <3>;
66 linux,code = <2>;
67 };
68
69 key_2 {
70 keypad,row = <0>;
71 keypad,column = <4>;
72 linux,code = <3>;
73 };
74
75 key_3 {
76 keypad,row = <0>;
77 keypad,column = <5>;
78 linux,code = <4>;
79 };
80
81 key_4 {
82 keypad,row = <0>;
83 keypad,column = <6>;
84 linux,code = <5>;
85 };
86
87 key_5 {
88 keypad,row = <0>;
89 keypad,column = <7>;
90 linux,code = <6>;
91 };
92
93 key_a {
94 keypad,row = <1>;
95 keypad,column = <3>;
96 linux,code = <30>;
97 };
98
99 key_b {
100 keypad,row = <1>;
101 keypad,column = <4>;
102 linux,code = <48>;
103 };
104
105 key_c {
106 keypad,row = <1>;
107 keypad,column = <5>;
108 linux,code = <46>;
109 };
110
111 key_d {
112 keypad,row = <1>;
113 keypad,column = <6>;
114 linux,code = <32>;
115 };
116
117 key_e {
118 keypad,row = <1>;
119 keypad,column = <7>;
120 linux,code = <18>;
121 };
122 };
123
124 i2c@13860000 {
125 #address-cells = <1>;
126 #size-cells = <0>;
127 samsung,i2c-sda-delay = <100>;
128 samsung,i2c-max-bus-freq = <20000>;
129 gpios = <&gpd1 0 2 3 0>,
130 <&gpd1 1 2 3 0>;
131
132 eeprom@50 {
133 compatible = "samsung,24ad0xd1";
134 reg = <0x50>;
135 };
136
137 eeprom@52 {
138 compatible = "samsung,24ad0xd1";
139 reg = <0x52>;
140 };
141 };
142
143 sdhci@12510000 {
144 status = "disabled";
145 };
146
147 sdhci@12520000 {
148 status = "disabled";
149 };
150
151 sdhci@12540000 {
152 status = "disabled";
153 };
154
155 i2c@13870000 {
156 status = "disabled";
157 };
158
159 i2c@13880000 {
160 status = "disabled";
161 };
162
163 i2c@13890000 {
164 status = "disabled";
165 };
166
167 i2c@138A0000 {
168 status = "disabled";
169 };
170
171 i2c@138B0000 {
172 status = "disabled";
173 };
174
175 i2c@138C0000 {
176 status = "disabled";
177 };
178
179 i2c@138D0000 {
180 status = "disabled";
181 };
182};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
new file mode 100644
index 000000000000..63d7578856c1
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -0,0 +1,397 @@
1/*
2 * Samsung's Exynos4210 SoC device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
10 * based board files can include this file and provide values for board specfic
11 * bindings.
12 *
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
15 * nodes can be added to this file.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20*/
21
22/include/ "skeleton.dtsi"
23
24/ {
25 compatible = "samsung,exynos4210";
26 interrupt-parent = <&gic>;
27
28 gic:interrupt-controller@10490000 {
29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>;
31 interrupt-controller;
32 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
33 };
34
35 watchdog@10060000 {
36 compatible = "samsung,s3c2410-wdt";
37 reg = <0x10060000 0x100>;
38 interrupts = <0 43 0>;
39 };
40
41 rtc@10070000 {
42 compatible = "samsung,s3c6410-rtc";
43 reg = <0x10070000 0x100>;
44 interrupts = <0 44 0>, <0 45 0>;
45 };
46
47 keypad@100A0000 {
48 compatible = "samsung,s5pv210-keypad";
49 reg = <0x100A0000 0x100>;
50 interrupts = <0 109 0>;
51 };
52
53 sdhci@12510000 {
54 compatible = "samsung,exynos4210-sdhci";
55 reg = <0x12510000 0x100>;
56 interrupts = <0 73 0>;
57 };
58
59 sdhci@12520000 {
60 compatible = "samsung,exynos4210-sdhci";
61 reg = <0x12520000 0x100>;
62 interrupts = <0 74 0>;
63 };
64
65 sdhci@12530000 {
66 compatible = "samsung,exynos4210-sdhci";
67 reg = <0x12530000 0x100>;
68 interrupts = <0 75 0>;
69 };
70
71 sdhci@12540000 {
72 compatible = "samsung,exynos4210-sdhci";
73 reg = <0x12540000 0x100>;
74 interrupts = <0 76 0>;
75 };
76
77 serial@13800000 {
78 compatible = "samsung,exynos4210-uart";
79 reg = <0x13800000 0x100>;
80 interrupts = <0 52 0>;
81 };
82
83 serial@13810000 {
84 compatible = "samsung,exynos4210-uart";
85 reg = <0x13810000 0x100>;
86 interrupts = <0 53 0>;
87 };
88
89 serial@13820000 {
90 compatible = "samsung,exynos4210-uart";
91 reg = <0x13820000 0x100>;
92 interrupts = <0 54 0>;
93 };
94
95 serial@13830000 {
96 compatible = "samsung,exynos4210-uart";
97 reg = <0x13830000 0x100>;
98 interrupts = <0 55 0>;
99 };
100
101 i2c@13860000 {
102 compatible = "samsung,s3c2440-i2c";
103 reg = <0x13860000 0x100>;
104 interrupts = <0 58 0>;
105 };
106
107 i2c@13870000 {
108 compatible = "samsung,s3c2440-i2c";
109 reg = <0x13870000 0x100>;
110 interrupts = <0 59 0>;
111 };
112
113 i2c@13880000 {
114 compatible = "samsung,s3c2440-i2c";
115 reg = <0x13880000 0x100>;
116 interrupts = <0 60 0>;
117 };
118
119 i2c@13890000 {
120 compatible = "samsung,s3c2440-i2c";
121 reg = <0x13890000 0x100>;
122 interrupts = <0 61 0>;
123 };
124
125 i2c@138A0000 {
126 compatible = "samsung,s3c2440-i2c";
127 reg = <0x138A0000 0x100>;
128 interrupts = <0 62 0>;
129 };
130
131 i2c@138B0000 {
132 compatible = "samsung,s3c2440-i2c";
133 reg = <0x138B0000 0x100>;
134 interrupts = <0 63 0>;
135 };
136
137 i2c@138C0000 {
138 compatible = "samsung,s3c2440-i2c";
139 reg = <0x138C0000 0x100>;
140 interrupts = <0 64 0>;
141 };
142
143 i2c@138D0000 {
144 compatible = "samsung,s3c2440-i2c";
145 reg = <0x138D0000 0x100>;
146 interrupts = <0 65 0>;
147 };
148
149 amba {
150 #address-cells = <1>;
151 #size-cells = <1>;
152 compatible = "arm,amba-bus";
153 interrupt-parent = <&gic>;
154 ranges;
155
156 pdma0: pdma@12680000 {
157 compatible = "arm,pl330", "arm,primecell";
158 reg = <0x12680000 0x1000>;
159 interrupts = <0 35 0>;
160 };
161
162 pdma1: pdma@12690000 {
163 compatible = "arm,pl330", "arm,primecell";
164 reg = <0x12690000 0x1000>;
165 interrupts = <0 36 0>;
166 };
167 };
168
169 gpio-controllers {
170 #address-cells = <1>;
171 #size-cells = <1>;
172 gpio-controller;
173 ranges;
174
175 gpa0: gpio-controller@11400000 {
176 compatible = "samsung,exynos4-gpio";
177 reg = <0x11400000 0x20>;
178 #gpio-cells = <4>;
179 };
180
181 gpa1: gpio-controller@11400020 {
182 compatible = "samsung,exynos4-gpio";
183 reg = <0x11400020 0x20>;
184 #gpio-cells = <4>;
185 };
186
187 gpb: gpio-controller@11400040 {
188 compatible = "samsung,exynos4-gpio";
189 reg = <0x11400040 0x20>;
190 #gpio-cells = <4>;
191 };
192
193 gpc0: gpio-controller@11400060 {
194 compatible = "samsung,exynos4-gpio";
195 reg = <0x11400060 0x20>;
196 #gpio-cells = <4>;
197 };
198
199 gpc1: gpio-controller@11400080 {
200 compatible = "samsung,exynos4-gpio";
201 reg = <0x11400080 0x20>;
202 #gpio-cells = <4>;
203 };
204
205 gpd0: gpio-controller@114000A0 {
206 compatible = "samsung,exynos4-gpio";
207 reg = <0x114000A0 0x20>;
208 #gpio-cells = <4>;
209 };
210
211 gpd1: gpio-controller@114000C0 {
212 compatible = "samsung,exynos4-gpio";
213 reg = <0x114000C0 0x20>;
214 #gpio-cells = <4>;
215 };
216
217 gpe0: gpio-controller@114000E0 {
218 compatible = "samsung,exynos4-gpio";
219 reg = <0x114000E0 0x20>;
220 #gpio-cells = <4>;
221 };
222
223 gpe1: gpio-controller@11400100 {
224 compatible = "samsung,exynos4-gpio";
225 reg = <0x11400100 0x20>;
226 #gpio-cells = <4>;
227 };
228
229 gpe2: gpio-controller@11400120 {
230 compatible = "samsung,exynos4-gpio";
231 reg = <0x11400120 0x20>;
232 #gpio-cells = <4>;
233 };
234
235 gpe3: gpio-controller@11400140 {
236 compatible = "samsung,exynos4-gpio";
237 reg = <0x11400140 0x20>;
238 #gpio-cells = <4>;
239 };
240
241 gpe4: gpio-controller@11400160 {
242 compatible = "samsung,exynos4-gpio";
243 reg = <0x11400160 0x20>;
244 #gpio-cells = <4>;
245 };
246
247 gpf0: gpio-controller@11400180 {
248 compatible = "samsung,exynos4-gpio";
249 reg = <0x11400180 0x20>;
250 #gpio-cells = <4>;
251 };
252
253 gpf1: gpio-controller@114001A0 {
254 compatible = "samsung,exynos4-gpio";
255 reg = <0x114001A0 0x20>;
256 #gpio-cells = <4>;
257 };
258
259 gpf2: gpio-controller@114001C0 {
260 compatible = "samsung,exynos4-gpio";
261 reg = <0x114001C0 0x20>;
262 #gpio-cells = <4>;
263 };
264
265 gpf3: gpio-controller@114001E0 {
266 compatible = "samsung,exynos4-gpio";
267 reg = <0x114001E0 0x20>;
268 #gpio-cells = <4>;
269 };
270
271 gpj0: gpio-controller@11000000 {
272 compatible = "samsung,exynos4-gpio";
273 reg = <0x11000000 0x20>;
274 #gpio-cells = <4>;
275 };
276
277 gpj1: gpio-controller@11000020 {
278 compatible = "samsung,exynos4-gpio";
279 reg = <0x11000020 0x20>;
280 #gpio-cells = <4>;
281 };
282
283 gpk0: gpio-controller@11000040 {
284 compatible = "samsung,exynos4-gpio";
285 reg = <0x11000040 0x20>;
286 #gpio-cells = <4>;
287 };
288
289 gpk1: gpio-controller@11000060 {
290 compatible = "samsung,exynos4-gpio";
291 reg = <0x11000060 0x20>;
292 #gpio-cells = <4>;
293 };
294
295 gpk2: gpio-controller@11000080 {
296 compatible = "samsung,exynos4-gpio";
297 reg = <0x11000080 0x20>;
298 #gpio-cells = <4>;
299 };
300
301 gpk3: gpio-controller@110000A0 {
302 compatible = "samsung,exynos4-gpio";
303 reg = <0x110000A0 0x20>;
304 #gpio-cells = <4>;
305 };
306
307 gpl0: gpio-controller@110000C0 {
308 compatible = "samsung,exynos4-gpio";
309 reg = <0x110000C0 0x20>;
310 #gpio-cells = <4>;
311 };
312
313 gpl1: gpio-controller@110000E0 {
314 compatible = "samsung,exynos4-gpio";
315 reg = <0x110000E0 0x20>;
316 #gpio-cells = <4>;
317 };
318
319 gpl2: gpio-controller@11000100 {
320 compatible = "samsung,exynos4-gpio";
321 reg = <0x11000100 0x20>;
322 #gpio-cells = <4>;
323 };
324
325 gpy0: gpio-controller@11000120 {
326 compatible = "samsung,exynos4-gpio";
327 reg = <0x11000120 0x20>;
328 #gpio-cells = <4>;
329 };
330
331 gpy1: gpio-controller@11000140 {
332 compatible = "samsung,exynos4-gpio";
333 reg = <0x11000140 0x20>;
334 #gpio-cells = <4>;
335 };
336
337 gpy2: gpio-controller@11000160 {
338 compatible = "samsung,exynos4-gpio";
339 reg = <0x11000160 0x20>;
340 #gpio-cells = <4>;
341 };
342
343 gpy3: gpio-controller@11000180 {
344 compatible = "samsung,exynos4-gpio";
345 reg = <0x11000180 0x20>;
346 #gpio-cells = <4>;
347 };
348
349 gpy4: gpio-controller@110001A0 {
350 compatible = "samsung,exynos4-gpio";
351 reg = <0x110001A0 0x20>;
352 #gpio-cells = <4>;
353 };
354
355 gpy5: gpio-controller@110001C0 {
356 compatible = "samsung,exynos4-gpio";
357 reg = <0x110001C0 0x20>;
358 #gpio-cells = <4>;
359 };
360
361 gpy6: gpio-controller@110001E0 {
362 compatible = "samsung,exynos4-gpio";
363 reg = <0x110001E0 0x20>;
364 #gpio-cells = <4>;
365 };
366
367 gpx0: gpio-controller@11000C00 {
368 compatible = "samsung,exynos4-gpio";
369 reg = <0x11000C00 0x20>;
370 #gpio-cells = <4>;
371 };
372
373 gpx1: gpio-controller@11000C20 {
374 compatible = "samsung,exynos4-gpio";
375 reg = <0x11000C20 0x20>;
376 #gpio-cells = <4>;
377 };
378
379 gpx2: gpio-controller@11000C40 {
380 compatible = "samsung,exynos4-gpio";
381 reg = <0x11000C40 0x20>;
382 #gpio-cells = <4>;
383 };
384
385 gpx3: gpio-controller@11000C60 {
386 compatible = "samsung,exynos4-gpio";
387 reg = <0x11000C60 0x20>;
388 #gpio-cells = <4>;
389 };
390
391 gpz: gpio-controller@03860000 {
392 compatible = "samsung,exynos4-gpio";
393 reg = <0x03860000 0x20>;
394 #gpio-cells = <4>;
395 };
396 };
397};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index aeb1a7578fad..305635bd45c0 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -194,5 +194,17 @@
194 reg = <0xfff3d000 0x1000>; 194 reg = <0xfff3d000 0x1000>;
195 interrupts = <0 92 4>; 195 interrupts = <0 92 4>;
196 }; 196 };
197
198 ethernet@fff50000 {
199 compatible = "calxeda,hb-xgmac";
200 reg = <0xfff50000 0x1000>;
201 interrupts = <0 77 4 0 78 4 0 79 4>;
202 };
203
204 ethernet@fff51000 {
205 compatible = "calxeda,hb-xgmac";
206 reg = <0xfff51000 0x1000>;
207 interrupts = <0 80 4 0 81 4 0 82 4>;
208 };
197 }; 209 };
198}; 210};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index f8766af11215..564cb8c19f15 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -35,20 +35,19 @@
35 }; 35 };
36 36
37 esdhc@70008000 { /* ESDHC2 */ 37 esdhc@70008000 { /* ESDHC2 */
38 cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */ 38 cd-gpios = <&gpio1 6 0>;
39 wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */ 39 wp-gpios = <&gpio1 5 0>;
40 status = "okay"; 40 status = "okay";
41 }; 41 };
42 42
43 uart2: uart@7000c000 { /* UART3 */ 43 uart3: uart@7000c000 {
44 fsl,uart-has-rtscts; 44 fsl,uart-has-rtscts;
45 status = "okay"; 45 status = "okay";
46 }; 46 };
47 47
48 ecspi@70010000 { /* ECSPI1 */ 48 ecspi@70010000 { /* ECSPI1 */
49 fsl,spi-num-chipselects = <2>; 49 fsl,spi-num-chipselects = <2>;
50 cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */ 50 cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
51 <&gpio3 25 0>; /* GPIO4_25 */
52 status = "okay"; 51 status = "okay";
53 52
54 pmic: mc13892@0 { 53 pmic: mc13892@0 {
@@ -57,7 +56,7 @@
57 compatible = "fsl,mc13892"; 56 compatible = "fsl,mc13892";
58 spi-max-frequency = <6000000>; 57 spi-max-frequency = <6000000>;
59 reg = <0>; 58 reg = <0>;
60 mc13xxx-irq-gpios = <&gpio0 8 0>; /* GPIO1_8 */ 59 mc13xxx-irq-gpios = <&gpio1 8 0>;
61 fsl,mc13xxx-uses-regulator; 60 fsl,mc13xxx-uses-regulator;
62 }; 61 };
63 62
@@ -91,12 +90,12 @@
91 reg = <0x73fa8000 0x4000>; 90 reg = <0x73fa8000 0x4000>;
92 }; 91 };
93 92
94 uart0: uart@73fbc000 { 93 uart1: uart@73fbc000 {
95 fsl,uart-has-rtscts; 94 fsl,uart-has-rtscts;
96 status = "okay"; 95 status = "okay";
97 }; 96 };
98 97
99 uart1: uart@73fc0000 { 98 uart2: uart@73fc0000 {
100 status = "okay"; 99 status = "okay";
101 }; 100 };
102 }; 101 };
@@ -127,7 +126,7 @@
127 126
128 power { 127 power {
129 label = "Power Button"; 128 label = "Power Button";
130 gpios = <&gpio1 21 0>; 129 gpios = <&gpio2 21 0>;
131 linux,code = <116>; /* KEY_POWER */ 130 linux,code = <116>; /* KEY_POWER */
132 gpio-key,wakeup; 131 gpio-key,wakeup;
133 }; 132 };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 327ab8e3a4c8..6663986fe1c8 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -14,9 +14,9 @@
14 14
15/ { 15/ {
16 aliases { 16 aliases {
17 serial0 = &uart0; 17 serial0 = &uart1;
18 serial1 = &uart1; 18 serial1 = &uart2;
19 serial2 = &uart2; 19 serial2 = &uart3;
20 }; 20 };
21 21
22 tzic: tz-interrupt-controller@e0000000 { 22 tzic: tz-interrupt-controller@e0000000 {
@@ -86,7 +86,7 @@
86 status = "disabled"; 86 status = "disabled";
87 }; 87 };
88 88
89 uart2: uart@7000c000 { /* UART3 */ 89 uart3: uart@7000c000 {
90 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 90 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
91 reg = <0x7000c000 0x4000>; 91 reg = <0x7000c000 0x4000>;
92 interrupts = <33>; 92 interrupts = <33>;
@@ -117,7 +117,7 @@
117 }; 117 };
118 }; 118 };
119 119
120 gpio0: gpio@73f84000 { /* GPIO1 */ 120 gpio1: gpio@73f84000 {
121 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 121 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
122 reg = <0x73f84000 0x4000>; 122 reg = <0x73f84000 0x4000>;
123 interrupts = <50 51>; 123 interrupts = <50 51>;
@@ -127,7 +127,7 @@
127 #interrupt-cells = <1>; 127 #interrupt-cells = <1>;
128 }; 128 };
129 129
130 gpio1: gpio@73f88000 { /* GPIO2 */ 130 gpio2: gpio@73f88000 {
131 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 131 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
132 reg = <0x73f88000 0x4000>; 132 reg = <0x73f88000 0x4000>;
133 interrupts = <52 53>; 133 interrupts = <52 53>;
@@ -137,7 +137,7 @@
137 #interrupt-cells = <1>; 137 #interrupt-cells = <1>;
138 }; 138 };
139 139
140 gpio2: gpio@73f8c000 { /* GPIO3 */ 140 gpio3: gpio@73f8c000 {
141 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 141 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
142 reg = <0x73f8c000 0x4000>; 142 reg = <0x73f8c000 0x4000>;
143 interrupts = <54 55>; 143 interrupts = <54 55>;
@@ -147,7 +147,7 @@
147 #interrupt-cells = <1>; 147 #interrupt-cells = <1>;
148 }; 148 };
149 149
150 gpio3: gpio@73f90000 { /* GPIO4 */ 150 gpio4: gpio@73f90000 {
151 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 151 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
152 reg = <0x73f90000 0x4000>; 152 reg = <0x73f90000 0x4000>;
153 interrupts = <56 57>; 153 interrupts = <56 57>;
@@ -171,14 +171,14 @@
171 status = "disabled"; 171 status = "disabled";
172 }; 172 };
173 173
174 uart0: uart@73fbc000 { 174 uart1: uart@73fbc000 {
175 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 175 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
176 reg = <0x73fbc000 0x4000>; 176 reg = <0x73fbc000 0x4000>;
177 interrupts = <31>; 177 interrupts = <31>;
178 status = "disabled"; 178 status = "disabled";
179 }; 179 };
180 180
181 uart1: uart@73fc0000 { 181 uart2: uart@73fc0000 {
182 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 182 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
183 reg = <0x73fc0000 0x4000>; 183 reg = <0x73fc0000 0x4000>;
184 interrupts = <32>; 184 interrupts = <32>;
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 2ab7f80a0a35..2dccce46ed81 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -29,8 +29,8 @@
29 aips@50000000 { /* AIPS1 */ 29 aips@50000000 { /* AIPS1 */
30 spba@50000000 { 30 spba@50000000 {
31 esdhc@50004000 { /* ESDHC1 */ 31 esdhc@50004000 { /* ESDHC1 */
32 cd-gpios = <&gpio0 1 0>; /* GPIO1_1 */ 32 cd-gpios = <&gpio1 1 0>;
33 wp-gpios = <&gpio0 9 0>; /* GPIO1_9 */ 33 wp-gpios = <&gpio1 9 0>;
34 status = "okay"; 34 status = "okay";
35 }; 35 };
36 }; 36 };
@@ -44,7 +44,7 @@
44 reg = <0x53fa8000 0x4000>; 44 reg = <0x53fa8000 0x4000>;
45 }; 45 };
46 46
47 uart0: uart@53fbc000 { /* UART1 */ 47 uart1: uart@53fbc000 {
48 status = "okay"; 48 status = "okay";
49 }; 49 };
50 }; 50 };
@@ -67,7 +67,7 @@
67 compatible = "smsc,lan9220", "smsc,lan9115"; 67 compatible = "smsc,lan9220", "smsc,lan9115";
68 reg = <0xf4000000 0x2000000>; 68 reg = <0xf4000000 0x2000000>;
69 phy-mode = "mii"; 69 phy-mode = "mii";
70 interrupt-parent = <&gpio1>; 70 interrupt-parent = <&gpio2>;
71 interrupts = <31>; 71 interrupts = <31>;
72 reg-io-width = <4>; 72 reg-io-width = <4>;
73 smsc,irq-push-pull; 73 smsc,irq-push-pull;
@@ -79,34 +79,34 @@
79 79
80 home { 80 home {
81 label = "Home"; 81 label = "Home";
82 gpios = <&gpio4 10 0>; /* GPIO5_10 */ 82 gpios = <&gpio5 10 0>;
83 linux,code = <102>; /* KEY_HOME */ 83 linux,code = <102>; /* KEY_HOME */
84 gpio-key,wakeup; 84 gpio-key,wakeup;
85 }; 85 };
86 86
87 back { 87 back {
88 label = "Back"; 88 label = "Back";
89 gpios = <&gpio4 11 0>; /* GPIO5_11 */ 89 gpios = <&gpio5 11 0>;
90 linux,code = <158>; /* KEY_BACK */ 90 linux,code = <158>; /* KEY_BACK */
91 gpio-key,wakeup; 91 gpio-key,wakeup;
92 }; 92 };
93 93
94 program { 94 program {
95 label = "Program"; 95 label = "Program";
96 gpios = <&gpio4 12 0>; /* GPIO5_12 */ 96 gpios = <&gpio5 12 0>;
97 linux,code = <362>; /* KEY_PROGRAM */ 97 linux,code = <362>; /* KEY_PROGRAM */
98 gpio-key,wakeup; 98 gpio-key,wakeup;
99 }; 99 };
100 100
101 volume-up { 101 volume-up {
102 label = "Volume Up"; 102 label = "Volume Up";
103 gpios = <&gpio4 13 0>; /* GPIO5_13 */ 103 gpios = <&gpio5 13 0>;
104 linux,code = <115>; /* KEY_VOLUMEUP */ 104 linux,code = <115>; /* KEY_VOLUMEUP */
105 }; 105 };
106 106
107 volume-down { 107 volume-down {
108 label = "Volume Down"; 108 label = "Volume Down";
109 gpios = <&gpio3 0 0>; /* GPIO4_0 */ 109 gpios = <&gpio4 0 0>;
110 linux,code = <114>; /* KEY_VOLUMEDOWN */ 110 linux,code = <114>; /* KEY_VOLUMEDOWN */
111 }; 111 };
112 }; 112 };
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 3f3a88185ff8..5bac4aa4800b 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -29,15 +29,14 @@
29 aips@50000000 { /* AIPS1 */ 29 aips@50000000 { /* AIPS1 */
30 spba@50000000 { 30 spba@50000000 {
31 esdhc@50004000 { /* ESDHC1 */ 31 esdhc@50004000 { /* ESDHC1 */
32 cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */ 32 cd-gpios = <&gpio3 13 0>;
33 wp-gpios = <&gpio2 14 0>; /* GPIO3_14 */ 33 wp-gpios = <&gpio3 14 0>;
34 status = "okay"; 34 status = "okay";
35 }; 35 };
36 36
37 ecspi@50010000 { /* ECSPI1 */ 37 ecspi@50010000 { /* ECSPI1 */
38 fsl,spi-num-chipselects = <2>; 38 fsl,spi-num-chipselects = <2>;
39 cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */ 39 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
40 <&gpio2 19 0>; /* GPIO3_19 */
41 status = "okay"; 40 status = "okay";
42 41
43 flash: at45db321d@1 { 42 flash: at45db321d@1 {
@@ -61,8 +60,8 @@
61 }; 60 };
62 61
63 esdhc@50020000 { /* ESDHC3 */ 62 esdhc@50020000 { /* ESDHC3 */
64 cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */ 63 cd-gpios = <&gpio3 11 0>;
65 wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */ 64 wp-gpios = <&gpio3 12 0>;
66 status = "okay"; 65 status = "okay";
67 }; 66 };
68 }; 67 };
@@ -76,7 +75,7 @@
76 reg = <0x53fa8000 0x4000>; 75 reg = <0x53fa8000 0x4000>;
77 }; 76 };
78 77
79 uart0: uart@53fbc000 { /* UART1 */ 78 uart1: uart@53fbc000 {
80 status = "okay"; 79 status = "okay";
81 }; 80 };
82 }; 81 };
@@ -102,7 +101,7 @@
102 101
103 fec@63fec000 { 102 fec@63fec000 {
104 phy-mode = "rmii"; 103 phy-mode = "rmii";
105 phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */ 104 phy-reset-gpios = <&gpio7 6 0>;
106 status = "okay"; 105 status = "okay";
107 }; 106 };
108 }; 107 };
@@ -113,7 +112,7 @@
113 112
114 green { 113 green {
115 label = "Heartbeat"; 114 label = "Heartbeat";
116 gpios = <&gpio6 7 0>; /* GPIO7_7 */ 115 gpios = <&gpio7 7 0>;
117 linux,default-trigger = "heartbeat"; 116 linux,default-trigger = "heartbeat";
118 }; 117 };
119 }; 118 };
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index ae6de6d0c3f1..5c57c8672c36 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -29,13 +29,13 @@
29 aips@50000000 { /* AIPS1 */ 29 aips@50000000 { /* AIPS1 */
30 spba@50000000 { 30 spba@50000000 {
31 esdhc@50004000 { /* ESDHC1 */ 31 esdhc@50004000 { /* ESDHC1 */
32 cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */ 32 cd-gpios = <&gpio3 13 0>;
33 status = "okay"; 33 status = "okay";
34 }; 34 };
35 35
36 esdhc@50020000 { /* ESDHC3 */ 36 esdhc@50020000 { /* ESDHC3 */
37 cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */ 37 cd-gpios = <&gpio3 11 0>;
38 wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */ 38 wp-gpios = <&gpio3 12 0>;
39 status = "okay"; 39 status = "okay";
40 }; 40 };
41 }; 41 };
@@ -49,7 +49,7 @@
49 reg = <0x53fa8000 0x4000>; 49 reg = <0x53fa8000 0x4000>;
50 }; 50 };
51 51
52 uart0: uart@53fbc000 { /* UART1 */ 52 uart1: uart@53fbc000 {
53 status = "okay"; 53 status = "okay";
54 }; 54 };
55 }; 55 };
@@ -84,7 +84,7 @@
84 84
85 fec@63fec000 { 85 fec@63fec000 {
86 phy-mode = "rmii"; 86 phy-mode = "rmii";
87 phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */ 87 phy-reset-gpios = <&gpio7 6 0>;
88 status = "okay"; 88 status = "okay";
89 }; 89 };
90 }; 90 };
@@ -95,20 +95,20 @@
95 95
96 power { 96 power {
97 label = "Power Button"; 97 label = "Power Button";
98 gpios = <&gpio0 8 0>; /* GPIO1_8 */ 98 gpios = <&gpio1 8 0>;
99 linux,code = <116>; /* KEY_POWER */ 99 linux,code = <116>; /* KEY_POWER */
100 gpio-key,wakeup; 100 gpio-key,wakeup;
101 }; 101 };
102 102
103 volume-up { 103 volume-up {
104 label = "Volume Up"; 104 label = "Volume Up";
105 gpios = <&gpio1 14 0>; /* GPIO2_14 */ 105 gpios = <&gpio2 14 0>;
106 linux,code = <115>; /* KEY_VOLUMEUP */ 106 linux,code = <115>; /* KEY_VOLUMEUP */
107 }; 107 };
108 108
109 volume-down { 109 volume-down {
110 label = "Volume Down"; 110 label = "Volume Down";
111 gpios = <&gpio1 15 0>; /* GPIO2_15 */ 111 gpios = <&gpio2 15 0>;
112 linux,code = <114>; /* KEY_VOLUMEDOWN */ 112 linux,code = <114>; /* KEY_VOLUMEDOWN */
113 }; 113 };
114 }; 114 };
@@ -118,7 +118,7 @@
118 118
119 user { 119 user {
120 label = "Heartbeat"; 120 label = "Heartbeat";
121 gpios = <&gpio6 7 0>; /* GPIO7_7 */ 121 gpios = <&gpio7 7 0>;
122 linux,default-trigger = "heartbeat"; 122 linux,default-trigger = "heartbeat";
123 }; 123 };
124 }; 124 };
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index b1c062eea715..c7ee86c2dfb5 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -29,8 +29,8 @@
29 aips@50000000 { /* AIPS1 */ 29 aips@50000000 { /* AIPS1 */
30 spba@50000000 { 30 spba@50000000 {
31 esdhc@50004000 { /* ESDHC1 */ 31 esdhc@50004000 { /* ESDHC1 */
32 cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */ 32 cd-gpios = <&gpio3 13 0>;
33 wp-gpios = <&gpio3 11 0>; /* GPIO4_11 */ 33 wp-gpios = <&gpio4 11 0>;
34 status = "okay"; 34 status = "okay";
35 }; 35 };
36 36
@@ -39,15 +39,14 @@
39 status = "okay"; 39 status = "okay";
40 }; 40 };
41 41
42 uart2: uart@5000c000 { /* UART3 */ 42 uart3: uart@5000c000 {
43 fsl,uart-has-rtscts; 43 fsl,uart-has-rtscts;
44 status = "okay"; 44 status = "okay";
45 }; 45 };
46 46
47 ecspi@50010000 { /* ECSPI1 */ 47 ecspi@50010000 { /* ECSPI1 */
48 fsl,spi-num-chipselects = <2>; 48 fsl,spi-num-chipselects = <2>;
49 cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */ 49 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
50 <&gpio2 19 0>; /* GPIO3_19 */
51 status = "okay"; 50 status = "okay";
52 51
53 zigbee: mc1323@0 { 52 zigbee: mc1323@0 {
@@ -91,11 +90,11 @@
91 reg = <0x53fa8000 0x4000>; 90 reg = <0x53fa8000 0x4000>;
92 }; 91 };
93 92
94 uart0: uart@53fbc000 { /* UART1 */ 93 uart1: uart@53fbc000 {
95 status = "okay"; 94 status = "okay";
96 }; 95 };
97 96
98 uart1: uart@53fc0000 { /* UART2 */ 97 uart2: uart@53fc0000 {
99 status = "okay"; 98 status = "okay";
100 }; 99 };
101 }; 100 };
@@ -145,7 +144,7 @@
145 144
146 fec@63fec000 { 145 fec@63fec000 {
147 phy-mode = "rmii"; 146 phy-mode = "rmii";
148 phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */ 147 phy-reset-gpios = <&gpio7 6 0>;
149 status = "okay"; 148 status = "okay";
150 }; 149 };
151 }; 150 };
@@ -156,13 +155,13 @@
156 155
157 volume-up { 156 volume-up {
158 label = "Volume Up"; 157 label = "Volume Up";
159 gpios = <&gpio1 14 0>; /* GPIO2_14 */ 158 gpios = <&gpio2 14 0>;
160 linux,code = <115>; /* KEY_VOLUMEUP */ 159 linux,code = <115>; /* KEY_VOLUMEUP */
161 }; 160 };
162 161
163 volume-down { 162 volume-down {
164 label = "Volume Down"; 163 label = "Volume Down";
165 gpios = <&gpio1 15 0>; /* GPIO2_15 */ 164 gpios = <&gpio2 15 0>;
166 linux,code = <114>; /* KEY_VOLUMEDOWN */ 165 linux,code = <114>; /* KEY_VOLUMEDOWN */
167 }; 166 };
168 }; 167 };
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 099cd84ee372..5dd91b942c91 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -14,11 +14,11 @@
14 14
15/ { 15/ {
16 aliases { 16 aliases {
17 serial0 = &uart0; 17 serial0 = &uart1;
18 serial1 = &uart1; 18 serial1 = &uart2;
19 serial2 = &uart2; 19 serial2 = &uart3;
20 serial3 = &uart3; 20 serial3 = &uart4;
21 serial4 = &uart4; 21 serial4 = &uart5;
22 }; 22 };
23 23
24 tzic: tz-interrupt-controller@0fffc000 { 24 tzic: tz-interrupt-controller@0fffc000 {
@@ -88,7 +88,7 @@
88 status = "disabled"; 88 status = "disabled";
89 }; 89 };
90 90
91 uart2: uart@5000c000 { /* UART3 */ 91 uart3: uart@5000c000 {
92 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 92 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
93 reg = <0x5000c000 0x4000>; 93 reg = <0x5000c000 0x4000>;
94 interrupts = <33>; 94 interrupts = <33>;
@@ -119,7 +119,7 @@
119 }; 119 };
120 }; 120 };
121 121
122 gpio0: gpio@53f84000 { /* GPIO1 */ 122 gpio1: gpio@53f84000 {
123 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; 123 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
124 reg = <0x53f84000 0x4000>; 124 reg = <0x53f84000 0x4000>;
125 interrupts = <50 51>; 125 interrupts = <50 51>;
@@ -129,7 +129,7 @@
129 #interrupt-cells = <1>; 129 #interrupt-cells = <1>;
130 }; 130 };
131 131
132 gpio1: gpio@53f88000 { /* GPIO2 */ 132 gpio2: gpio@53f88000 {
133 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; 133 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
134 reg = <0x53f88000 0x4000>; 134 reg = <0x53f88000 0x4000>;
135 interrupts = <52 53>; 135 interrupts = <52 53>;
@@ -139,7 +139,7 @@
139 #interrupt-cells = <1>; 139 #interrupt-cells = <1>;
140 }; 140 };
141 141
142 gpio2: gpio@53f8c000 { /* GPIO3 */ 142 gpio3: gpio@53f8c000 {
143 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; 143 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
144 reg = <0x53f8c000 0x4000>; 144 reg = <0x53f8c000 0x4000>;
145 interrupts = <54 55>; 145 interrupts = <54 55>;
@@ -149,7 +149,7 @@
149 #interrupt-cells = <1>; 149 #interrupt-cells = <1>;
150 }; 150 };
151 151
152 gpio3: gpio@53f90000 { /* GPIO4 */ 152 gpio4: gpio@53f90000 {
153 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; 153 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
154 reg = <0x53f90000 0x4000>; 154 reg = <0x53f90000 0x4000>;
155 interrupts = <56 57>; 155 interrupts = <56 57>;
@@ -173,21 +173,21 @@
173 status = "disabled"; 173 status = "disabled";
174 }; 174 };
175 175
176 uart0: uart@53fbc000 { /* UART1 */ 176 uart1: uart@53fbc000 {
177 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 177 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
178 reg = <0x53fbc000 0x4000>; 178 reg = <0x53fbc000 0x4000>;
179 interrupts = <31>; 179 interrupts = <31>;
180 status = "disabled"; 180 status = "disabled";
181 }; 181 };
182 182
183 uart1: uart@53fc0000 { /* UART2 */ 183 uart2: uart@53fc0000 {
184 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 184 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
185 reg = <0x53fc0000 0x4000>; 185 reg = <0x53fc0000 0x4000>;
186 interrupts = <32>; 186 interrupts = <32>;
187 status = "disabled"; 187 status = "disabled";
188 }; 188 };
189 189
190 gpio4: gpio@53fdc000 { /* GPIO5 */ 190 gpio5: gpio@53fdc000 {
191 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; 191 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
192 reg = <0x53fdc000 0x4000>; 192 reg = <0x53fdc000 0x4000>;
193 interrupts = <103 104>; 193 interrupts = <103 104>;
@@ -197,7 +197,7 @@
197 #interrupt-cells = <1>; 197 #interrupt-cells = <1>;
198 }; 198 };
199 199
200 gpio5: gpio@53fe0000 { /* GPIO6 */ 200 gpio6: gpio@53fe0000 {
201 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; 201 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
202 reg = <0x53fe0000 0x4000>; 202 reg = <0x53fe0000 0x4000>;
203 interrupts = <105 106>; 203 interrupts = <105 106>;
@@ -207,7 +207,7 @@
207 #interrupt-cells = <1>; 207 #interrupt-cells = <1>;
208 }; 208 };
209 209
210 gpio6: gpio@53fe4000 { /* GPIO7 */ 210 gpio7: gpio@53fe4000 {
211 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; 211 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
212 reg = <0x53fe4000 0x4000>; 212 reg = <0x53fe4000 0x4000>;
213 interrupts = <107 108>; 213 interrupts = <107 108>;
@@ -226,7 +226,7 @@
226 status = "disabled"; 226 status = "disabled";
227 }; 227 };
228 228
229 uart3: uart@53ff0000 { /* UART4 */ 229 uart4: uart@53ff0000 {
230 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 230 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
231 reg = <0x53ff0000 0x4000>; 231 reg = <0x53ff0000 0x4000>;
232 interrupts = <13>; 232 interrupts = <13>;
@@ -241,7 +241,7 @@
241 reg = <0x60000000 0x10000000>; 241 reg = <0x60000000 0x10000000>;
242 ranges; 242 ranges;
243 243
244 uart4: uart@63f90000 { /* UART5 */ 244 uart5: uart@63f90000 {
245 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 245 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
246 reg = <0x63f90000 0x4000>; 246 reg = <0x63f90000 0x4000>;
247 interrupts = <86>; 247 interrupts = <86>;
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 072974e443f2..c3977e0478b9 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -14,8 +14,8 @@
14/include/ "imx6q.dtsi" 14/include/ "imx6q.dtsi"
15 15
16/ { 16/ {
17 model = "Freescale i.MX6 Quad SABRE Automotive Board"; 17 model = "Freescale i.MX6 Quad Armadillo2 Board";
18 compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; 18 compatible = "fsl,imx6q-arm2", "fsl,imx6q";
19 19
20 chosen { 20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait"; 21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait";
@@ -34,8 +34,8 @@
34 }; 34 };
35 35
36 usdhc@02198000 { /* uSDHC3 */ 36 usdhc@02198000 { /* uSDHC3 */
37 cd-gpios = <&gpio5 11 0>; /* GPIO6_11 */ 37 cd-gpios = <&gpio6 11 0>;
38 wp-gpios = <&gpio5 14 0>; /* GPIO6_14 */ 38 wp-gpios = <&gpio6 14 0>;
39 status = "okay"; 39 status = "okay";
40 }; 40 };
41 41
@@ -44,7 +44,7 @@
44 status = "okay"; 44 status = "okay";
45 }; 45 };
46 46
47 uart3: uart@021f0000 { /* UART4 */ 47 uart4: uart@021f0000 {
48 status = "okay"; 48 status = "okay";
49 }; 49 };
50 }; 50 };
@@ -55,7 +55,7 @@
55 55
56 debug-led { 56 debug-led {
57 label = "Heartbeat"; 57 label = "Heartbeat";
58 gpios = <&gpio2 25 0>; /* GPIO3_25 */ 58 gpios = <&gpio3 25 0>;
59 linux,default-trigger = "heartbeat"; 59 linux,default-trigger = "heartbeat";
60 }; 60 };
61 }; 61 };
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
new file mode 100644
index 000000000000..08d920de7286
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -0,0 +1,49 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx6q.dtsi"
15
16/ {
17 model = "Freescale i.MX6 Quad SABRE Lite Board";
18 compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
19
20 memory {
21 reg = <0x10000000 0x40000000>;
22 };
23
24 soc {
25 aips-bus@02100000 { /* AIPS2 */
26 enet@02188000 {
27 phy-mode = "rgmii";
28 phy-reset-gpios = <&gpio3 23 0>;
29 status = "okay";
30 };
31
32 usdhc@02198000 { /* uSDHC3 */
33 cd-gpios = <&gpio7 0 0>;
34 wp-gpios = <&gpio7 1 0>;
35 status = "okay";
36 };
37
38 usdhc@0219c000 { /* uSDHC4 */
39 cd-gpios = <&gpio2 6 0>;
40 wp-gpios = <&gpio2 7 0>;
41 status = "okay";
42 };
43
44 uart2: uart@021e8000 {
45 status = "okay";
46 };
47 };
48 };
49};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 7dda599558cc..263e8f3664b5 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -14,11 +14,11 @@
14 14
15/ { 15/ {
16 aliases { 16 aliases {
17 serial0 = &uart0; 17 serial0 = &uart1;
18 serial1 = &uart1; 18 serial1 = &uart2;
19 serial2 = &uart2; 19 serial2 = &uart3;
20 serial3 = &uart3; 20 serial3 = &uart4;
21 serial4 = &uart4; 21 serial4 = &uart5;
22 }; 22 };
23 23
24 cpus { 24 cpus {
@@ -165,7 +165,7 @@
165 status = "disabled"; 165 status = "disabled";
166 }; 166 };
167 167
168 uart0: uart@02020000 { /* UART1 */ 168 uart1: uart@02020000 {
169 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 169 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
170 reg = <0x02020000 0x4000>; 170 reg = <0x02020000 0x4000>;
171 interrupts = <0 26 0x04>; 171 interrupts = <0 26 0x04>;
@@ -247,7 +247,7 @@
247 interrupts = <0 55 0x04>; 247 interrupts = <0 55 0x04>;
248 }; 248 };
249 249
250 gpio0: gpio@0209c000 { /* GPIO1 */ 250 gpio1: gpio@0209c000 {
251 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; 251 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
252 reg = <0x0209c000 0x4000>; 252 reg = <0x0209c000 0x4000>;
253 interrupts = <0 66 0x04 0 67 0x04>; 253 interrupts = <0 66 0x04 0 67 0x04>;
@@ -257,7 +257,7 @@
257 #interrupt-cells = <1>; 257 #interrupt-cells = <1>;
258 }; 258 };
259 259
260 gpio1: gpio@020a0000 { /* GPIO2 */ 260 gpio2: gpio@020a0000 {
261 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; 261 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
262 reg = <0x020a0000 0x4000>; 262 reg = <0x020a0000 0x4000>;
263 interrupts = <0 68 0x04 0 69 0x04>; 263 interrupts = <0 68 0x04 0 69 0x04>;
@@ -267,7 +267,7 @@
267 #interrupt-cells = <1>; 267 #interrupt-cells = <1>;
268 }; 268 };
269 269
270 gpio2: gpio@020a4000 { /* GPIO3 */ 270 gpio3: gpio@020a4000 {
271 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; 271 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
272 reg = <0x020a4000 0x4000>; 272 reg = <0x020a4000 0x4000>;
273 interrupts = <0 70 0x04 0 71 0x04>; 273 interrupts = <0 70 0x04 0 71 0x04>;
@@ -277,7 +277,7 @@
277 #interrupt-cells = <1>; 277 #interrupt-cells = <1>;
278 }; 278 };
279 279
280 gpio3: gpio@020a8000 { /* GPIO4 */ 280 gpio4: gpio@020a8000 {
281 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; 281 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
282 reg = <0x020a8000 0x4000>; 282 reg = <0x020a8000 0x4000>;
283 interrupts = <0 72 0x04 0 73 0x04>; 283 interrupts = <0 72 0x04 0 73 0x04>;
@@ -287,7 +287,7 @@
287 #interrupt-cells = <1>; 287 #interrupt-cells = <1>;
288 }; 288 };
289 289
290 gpio4: gpio@020ac000 { /* GPIO5 */ 290 gpio5: gpio@020ac000 {
291 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; 291 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
292 reg = <0x020ac000 0x4000>; 292 reg = <0x020ac000 0x4000>;
293 interrupts = <0 74 0x04 0 75 0x04>; 293 interrupts = <0 74 0x04 0 75 0x04>;
@@ -297,7 +297,7 @@
297 #interrupt-cells = <1>; 297 #interrupt-cells = <1>;
298 }; 298 };
299 299
300 gpio5: gpio@020b0000 { /* GPIO6 */ 300 gpio6: gpio@020b0000 {
301 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; 301 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
302 reg = <0x020b0000 0x4000>; 302 reg = <0x020b0000 0x4000>;
303 interrupts = <0 76 0x04 0 77 0x04>; 303 interrupts = <0 76 0x04 0 77 0x04>;
@@ -307,7 +307,7 @@
307 #interrupt-cells = <1>; 307 #interrupt-cells = <1>;
308 }; 308 };
309 309
310 gpio6: gpio@020b4000 { /* GPIO7 */ 310 gpio7: gpio@020b4000 {
311 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; 311 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
312 reg = <0x020b4000 0x4000>; 312 reg = <0x020b4000 0x4000>;
313 interrupts = <0 78 0x04 0 79 0x04>; 313 interrupts = <0 78 0x04 0 79 0x04>;
@@ -543,28 +543,28 @@
543 interrupts = <0 18 0x04>; 543 interrupts = <0 18 0x04>;
544 }; 544 };
545 545
546 uart1: uart@021e8000 { /* UART2 */ 546 uart2: uart@021e8000 {
547 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 547 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
548 reg = <0x021e8000 0x4000>; 548 reg = <0x021e8000 0x4000>;
549 interrupts = <0 27 0x04>; 549 interrupts = <0 27 0x04>;
550 status = "disabled"; 550 status = "disabled";
551 }; 551 };
552 552
553 uart2: uart@021ec000 { /* UART3 */ 553 uart3: uart@021ec000 {
554 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 554 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
555 reg = <0x021ec000 0x4000>; 555 reg = <0x021ec000 0x4000>;
556 interrupts = <0 28 0x04>; 556 interrupts = <0 28 0x04>;
557 status = "disabled"; 557 status = "disabled";
558 }; 558 };
559 559
560 uart3: uart@021f0000 { /* UART4 */ 560 uart4: uart@021f0000 {
561 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 561 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
562 reg = <0x021f0000 0x4000>; 562 reg = <0x021f0000 0x4000>;
563 interrupts = <0 29 0x04>; 563 interrupts = <0 29 0x04>;
564 status = "disabled"; 564 status = "disabled";
565 }; 565 };
566 566
567 uart4: uart@021f4000 { /* UART5 */ 567 uart5: uart@021f4000 {
568 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 568 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
569 reg = <0x021f4000 0x4000>; 569 reg = <0x021f4000 0x4000>;
570 interrupts = <0 30 0x04>; 570 interrupts = <0 30 0x04>;
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
new file mode 100644
index 000000000000..f2ab4ea7cc0e
--- /dev/null
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -0,0 +1,67 @@
1/*
2 * Device Tree Source for OMAP2 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
15
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 };
21
22 cpus {
23 cpu@0 {
24 compatible = "arm,arm1136jf-s";
25 };
26 };
27
28 soc {
29 compatible = "ti,omap-infra";
30 mpu {
31 compatible = "ti,omap2-mpu";
32 ti,hwmods = "mpu";
33 };
34 };
35
36 ocp {
37 compatible = "simple-bus";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 ranges;
41 ti,hwmods = "l3_main";
42
43 intc: interrupt-controller@1 {
44 compatible = "ti,omap2-intc";
45 interrupt-controller;
46 #interrupt-cells = <1>;
47 };
48
49 uart1: serial@4806a000 {
50 compatible = "ti,omap2-uart";
51 ti,hwmods = "uart1";
52 clock-frequency = <48000000>;
53 };
54
55 uart2: serial@4806c000 {
56 compatible = "ti,omap2-uart";
57 ti,hwmods = "uart2";
58 clock-frequency = <48000000>;
59 };
60
61 uart3: serial@4806e000 {
62 compatible = "ti,omap2-uart";
63 ti,hwmods = "uart3";
64 clock-frequency = <48000000>;
65 };
66 };
67};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index d202bb5ec7ef..216c3317461d 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -13,6 +13,13 @@
13/ { 13/ {
14 compatible = "ti,omap3430", "ti,omap3"; 14 compatible = "ti,omap3430", "ti,omap3";
15 15
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 };
22
16 cpus { 23 cpus {
17 cpu@0 { 24 cpu@0 {
18 compatible = "arm,cortex-a8"; 25 compatible = "arm,cortex-a8";
@@ -59,5 +66,29 @@
59 interrupt-controller; 66 interrupt-controller;
60 #interrupt-cells = <1>; 67 #interrupt-cells = <1>;
61 }; 68 };
69
70 uart1: serial@0x4806a000 {
71 compatible = "ti,omap3-uart";
72 ti,hwmods = "uart1";
73 clock-frequency = <48000000>;
74 };
75
76 uart2: serial@0x4806c000 {
77 compatible = "ti,omap3-uart";
78 ti,hwmods = "uart2";
79 clock-frequency = <48000000>;
80 };
81
82 uart3: serial@0x49020000 {
83 compatible = "ti,omap3-uart";
84 ti,hwmods = "uart3";
85 clock-frequency = <48000000>;
86 };
87
88 uart4: serial@0x49042000 {
89 compatible = "ti,omap3-uart";
90 ti,hwmods = "uart4";
91 clock-frequency = <48000000>;
92 };
62 }; 93 };
63}; 94};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 4c61c829043a..e8fe75fac7c5 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -21,6 +21,10 @@
21 interrupt-parent = <&gic>; 21 interrupt-parent = <&gic>;
22 22
23 aliases { 23 aliases {
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
24 }; 28 };
25 29
26 cpus { 30 cpus {
@@ -99,5 +103,29 @@
99 reg = <0x48241000 0x1000>, 103 reg = <0x48241000 0x1000>,
100 <0x48240100 0x0100>; 104 <0x48240100 0x0100>;
101 }; 105 };
106
107 uart1: serial@0x4806a000 {
108 compatible = "ti,omap4-uart";
109 ti,hwmods = "uart1";
110 clock-frequency = <48000000>;
111 };
112
113 uart2: serial@0x4806c000 {
114 compatible = "ti,omap4-uart";
115 ti,hwmods = "uart2";
116 clock-frequency = <48000000>;
117 };
118
119 uart3: serial@0x48020000 {
120 compatible = "ti,omap4-uart";
121 ti,hwmods = "uart3";
122 clock-frequency = <48000000>;
123 };
124
125 uart4: serial@0x4806e000 {
126 compatible = "ti,omap4-uart";
127 ti,hwmods = "uart4";
128 clock-frequency = <48000000>;
129 };
102 }; 130 };
103}; 131};
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
new file mode 100644
index 000000000000..70c41fc897d7
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -0,0 +1,36 @@
1/dts-v1/;
2
3/include/ "tegra30.dtsi"
4
5/ {
6 model = "NVIDIA Tegra30 Cardhu evaluation board";
7 compatible = "nvidia,cardhu", "nvidia,tegra30";
8
9 memory {
10 reg = < 0x80000000 0x40000000 >;
11 };
12
13 serial@70006000 {
14 clock-frequency = < 408000000 >;
15 };
16
17 i2c@7000c000 {
18 clock-frequency = <100000>;
19 };
20
21 i2c@7000c400 {
22 clock-frequency = <100000>;
23 };
24
25 i2c@7000c500 {
26 clock-frequency = <100000>;
27 };
28
29 i2c@7000c700 {
30 clock-frequency = <100000>;
31 };
32
33 i2c@7000d000 {
34 clock-frequency = <100000>;
35 };
36};
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 0e225b86b652..80afa1b70b80 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -1,16 +1,11 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/memreserve/ 0x1c000000 0x04000000;
4/include/ "tegra20.dtsi" 3/include/ "tegra20.dtsi"
5 4
6/ { 5/ {
7 model = "NVIDIA Tegra2 Harmony evaluation board"; 6 model = "NVIDIA Tegra2 Harmony evaluation board";
8 compatible = "nvidia,harmony", "nvidia,tegra20"; 7 compatible = "nvidia,harmony", "nvidia,tegra20";
9 8
10 chosen {
11 bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootwait";
12 };
13
14 memory@0 { 9 memory@0 {
15 reg = < 0x00000000 0x40000000 >; 10 reg = < 0x00000000 0x40000000 >;
16 }; 11 };
@@ -52,16 +47,40 @@
52 ext-mic-en-gpios = <&gpio 185 0>; 47 ext-mic-en-gpios = <&gpio 185 0>;
53 }; 48 };
54 49
50 serial@70006000 {
51 status = "disable";
52 };
53
54 serial@70006040 {
55 status = "disable";
56 };
57
58 serial@70006200 {
59 status = "disable";
60 };
61
55 serial@70006300 { 62 serial@70006300 {
56 clock-frequency = < 216000000 >; 63 clock-frequency = < 216000000 >;
57 }; 64 };
58 65
66 serial@70006400 {
67 status = "disable";
68 };
69
70 sdhci@c8000000 {
71 status = "disable";
72 };
73
59 sdhci@c8000200 { 74 sdhci@c8000200 {
60 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 75 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
61 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 76 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
62 power-gpios = <&gpio 155 0>; /* gpio PT3 */ 77 power-gpios = <&gpio 155 0>; /* gpio PT3 */
63 }; 78 };
64 79
80 sdhci@c8000400 {
81 status = "disable";
82 };
83
65 sdhci@c8000600 { 84 sdhci@c8000600 {
66 cd-gpios = <&gpio 58 0>; /* gpio PH2 */ 85 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
67 wp-gpios = <&gpio 59 0>; /* gpio PH3 */ 86 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
new file mode 100644
index 000000000000..1a1d7023b69b
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -0,0 +1,77 @@
1/dts-v1/;
2
3/include/ "tegra20.dtsi"
4
5/ {
6 model = "Toshiba AC100 / Dynabook AZ";
7 compatible = "compal,paz00", "nvidia,tegra20";
8
9 memory@0 {
10 reg = <0x00000000 0x20000000>;
11 };
12
13 i2c@7000c000 {
14 clock-frequency = <400000>;
15 };
16
17 i2c@7000c400 {
18 clock-frequency = <400000>;
19 };
20
21 i2c@7000c500 {
22 status = "disable";
23 };
24
25 nvec@7000c500 {
26 #address-cells = <1>;
27 #size-cells = <0>;
28 compatible = "nvidia,nvec";
29 reg = <0x7000C500 0x100>;
30 interrupts = <0 92 0x04>;
31 clock-frequency = <80000>;
32 request-gpios = <&gpio 170 0>;
33 slave-addr = <138>;
34 };
35
36 i2c@7000d000 {
37 clock-frequency = <400000>;
38 };
39
40 serial@70006000 {
41 clock-frequency = <216000000>;
42 };
43
44 serial@70006040 {
45 status = "disable";
46 };
47
48 serial@70006200 {
49 status = "disable";
50 };
51
52 serial@70006300 {
53 clock-frequency = <216000000>;
54 };
55
56 serial@70006400 {
57 status = "disable";
58 };
59
60 sdhci@c8000000 {
61 cd-gpios = <&gpio 173 0>; /* gpio PV5 */
62 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
63 power-gpios = <&gpio 155 0>; /* gpio PT3 */
64 };
65
66 sdhci@c8000200 {
67 status = "disable";
68 };
69
70 sdhci@c8000400 {
71 status = "disable";
72 };
73
74 sdhci@c8000600 {
75 support-8bit;
76 };
77};
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index a72299b8e668..b55a02e34ba7 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -1,25 +1,65 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/memreserve/ 0x1c000000 0x04000000;
4/include/ "tegra20.dtsi" 3/include/ "tegra20.dtsi"
5 4
6/ { 5/ {
7 model = "NVIDIA Seaboard"; 6 model = "NVIDIA Seaboard";
8 compatible = "nvidia,seaboard", "nvidia,tegra20"; 7 compatible = "nvidia,seaboard", "nvidia,tegra20";
9 8
10 chosen {
11 bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
12 };
13
14 memory { 9 memory {
15 device_type = "memory"; 10 device_type = "memory";
16 reg = < 0x00000000 0x40000000 >; 11 reg = < 0x00000000 0x40000000 >;
17 }; 12 };
18 13
14 i2c@7000c000 {
15 clock-frequency = <400000>;
16 };
17
18 i2c@7000c400 {
19 clock-frequency = <400000>;
20 };
21
22 i2c@7000c500 {
23 clock-frequency = <400000>;
24 };
25
26 i2c@7000d000 {
27 clock-frequency = <400000>;
28
29 adt7461@4c {
30 compatible = "adt7461";
31 reg = <0x4c>;
32 };
33 };
34
35 serial@70006000 {
36 status = "disable";
37 };
38
39 serial@70006040 {
40 status = "disable";
41 };
42
43 serial@70006200 {
44 status = "disable";
45 };
46
19 serial@70006300 { 47 serial@70006300 {
20 clock-frequency = < 216000000 >; 48 clock-frequency = < 216000000 >;
21 }; 49 };
22 50
51 serial@70006400 {
52 status = "disable";
53 };
54
55 sdhci@c8000000 {
56 status = "disable";
57 };
58
59 sdhci@c8000200 {
60 status = "disable";
61 };
62
23 sdhci@c8000400 { 63 sdhci@c8000400 {
24 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 64 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
25 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 65 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
@@ -29,4 +69,28 @@
29 sdhci@c8000600 { 69 sdhci@c8000600 {
30 support-8bit; 70 support-8bit;
31 }; 71 };
72
73 usb@c5000000 {
74 nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
75 };
76
77 gpio-keys {
78 compatible = "gpio-keys";
79
80 power {
81 label = "Power";
82 gpios = <&gpio 170 1>; /* gpio PV2, active low */
83 linux,code = <116>; /* KEY_POWER */
84 gpio-key,wakeup;
85 };
86
87 lid {
88 label = "Lid";
89 gpios = <&gpio 23 0>; /* gpio PC7 */
90 linux,input-type = <5>; /* EV_SW */
91 linux,code = <0>; /* SW_LID */
92 debounce-interval = <1>;
93 gpio-key,wakeup;
94 };
95 };
32}; 96};
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
new file mode 100644
index 000000000000..3b3ee7db99f3
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -0,0 +1,65 @@
1/dts-v1/;
2
3/include/ "tegra20.dtsi"
4
5/ {
6 model = "Compulab TrimSlice board";
7 compatible = "compulab,trimslice", "nvidia,tegra20";
8
9 memory@0 {
10 reg = < 0x00000000 0x40000000 >;
11 };
12
13 i2c@7000c000 {
14 clock-frequency = <400000>;
15 };
16
17 i2c@7000c400 {
18 clock-frequency = <400000>;
19 };
20
21 i2c@7000c500 {
22 clock-frequency = <400000>;
23 };
24
25 i2c@7000d000 {
26 status = "disable";
27 };
28
29 serial@70006000 {
30 clock-frequency = < 216000000 >;
31 };
32
33 serial@70006040 {
34 status = "disable";
35 };
36
37 serial@70006200 {
38 status = "disable";
39 };
40
41 serial@70006300 {
42 status = "disable";
43 };
44
45 serial@70006400 {
46 status = "disable";
47 };
48
49 sdhci@c8000000 {
50 status = "disable";
51 };
52
53 sdhci@c8000200 {
54 status = "disable";
55 };
56
57 sdhci@c8000400 {
58 status = "disable";
59 };
60
61 sdhci@c8000600 {
62 cd-gpios = <&gpio 121 0>;
63 wp-gpios = <&gpio 122 0>;
64 };
65};
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index 3f9abd6b6964..c7d3b87f29df 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -1,24 +1,59 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/memreserve/ 0x1c000000 0x04000000;
4/include/ "tegra20.dtsi" 3/include/ "tegra20.dtsi"
5 4
6/ { 5/ {
7 model = "NVIDIA Tegra2 Ventana evaluation board"; 6 model = "NVIDIA Tegra2 Ventana evaluation board";
8 compatible = "nvidia,ventana", "nvidia,tegra20"; 7 compatible = "nvidia,ventana", "nvidia,tegra20";
9 8
10 chosen {
11 bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/ram rdinit=/sbin/init";
12 };
13
14 memory { 9 memory {
15 reg = < 0x00000000 0x40000000 >; 10 reg = < 0x00000000 0x40000000 >;
16 }; 11 };
17 12
13 i2c@7000c000 {
14 clock-frequency = <400000>;
15 };
16
17 i2c@7000c400 {
18 clock-frequency = <400000>;
19 };
20
21 i2c@7000c500 {
22 clock-frequency = <400000>;
23 };
24
25 i2c@7000d000 {
26 clock-frequency = <400000>;
27 };
28
29 serial@70006000 {
30 status = "disable";
31 };
32
33 serial@70006040 {
34 status = "disable";
35 };
36
37 serial@70006200 {
38 status = "disable";
39 };
40
18 serial@70006300 { 41 serial@70006300 {
19 clock-frequency = < 216000000 >; 42 clock-frequency = < 216000000 >;
20 }; 43 };
21 44
45 serial@70006400 {
46 status = "disable";
47 };
48
49 sdhci@c8000000 {
50 status = "disable";
51 };
52
53 sdhci@c8000200 {
54 status = "disable";
55 };
56
22 sdhci@c8000400 { 57 sdhci@c8000400 {
23 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 58 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
24 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 59 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 65d7e6a333eb..3da7afd45322 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -5,9 +5,9 @@
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 intc: interrupt-controller@50041000 { 7 intc: interrupt-controller@50041000 {
8 compatible = "nvidia,tegra20-gic"; 8 compatible = "arm,cortex-a9-gic";
9 interrupt-controller; 9 interrupt-controller;
10 #interrupt-cells = <1>; 10 #interrupt-cells = <3>;
11 reg = < 0x50041000 0x1000 >, 11 reg = < 0x50041000 0x1000 >,
12 < 0x50040100 0x0100 >; 12 < 0x50040100 0x0100 >;
13 }; 13 };
@@ -17,7 +17,7 @@
17 #size-cells = <0>; 17 #size-cells = <0>;
18 compatible = "nvidia,tegra20-i2c"; 18 compatible = "nvidia,tegra20-i2c";
19 reg = <0x7000C000 0x100>; 19 reg = <0x7000C000 0x100>;
20 interrupts = < 70 >; 20 interrupts = < 0 38 0x04 >;
21 }; 21 };
22 22
23 i2c@7000c400 { 23 i2c@7000c400 {
@@ -25,7 +25,7 @@
25 #size-cells = <0>; 25 #size-cells = <0>;
26 compatible = "nvidia,tegra20-i2c"; 26 compatible = "nvidia,tegra20-i2c";
27 reg = <0x7000C400 0x100>; 27 reg = <0x7000C400 0x100>;
28 interrupts = < 116 >; 28 interrupts = < 0 84 0x04 >;
29 }; 29 };
30 30
31 i2c@7000c500 { 31 i2c@7000c500 {
@@ -33,38 +33,32 @@
33 #size-cells = <0>; 33 #size-cells = <0>;
34 compatible = "nvidia,tegra20-i2c"; 34 compatible = "nvidia,tegra20-i2c";
35 reg = <0x7000C500 0x100>; 35 reg = <0x7000C500 0x100>;
36 interrupts = < 124 >; 36 interrupts = < 0 92 0x04 >;
37 }; 37 };
38 38
39 i2c@7000d000 { 39 i2c@7000d000 {
40 #address-cells = <1>; 40 #address-cells = <1>;
41 #size-cells = <0>; 41 #size-cells = <0>;
42 compatible = "nvidia,tegra20-i2c"; 42 compatible = "nvidia,tegra20-i2c-dvc";
43 reg = <0x7000D000 0x200>; 43 reg = <0x7000D000 0x200>;
44 interrupts = < 85 >; 44 interrupts = < 0 53 0x04 >;
45 }; 45 };
46 46
47 i2s@70002800 { 47 i2s@70002800 {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 compatible = "nvidia,tegra20-i2s"; 48 compatible = "nvidia,tegra20-i2s";
51 reg = <0x70002800 0x200>; 49 reg = <0x70002800 0x200>;
52 interrupts = < 45 >; 50 interrupts = < 0 13 0x04 >;
53 dma-channel = < 2 >; 51 dma-channel = < 2 >;
54 }; 52 };
55 53
56 i2s@70002a00 { 54 i2s@70002a00 {
57 #address-cells = <1>;
58 #size-cells = <0>;
59 compatible = "nvidia,tegra20-i2s"; 55 compatible = "nvidia,tegra20-i2s";
60 reg = <0x70002a00 0x200>; 56 reg = <0x70002a00 0x200>;
61 interrupts = < 35 >; 57 interrupts = < 0 3 0x04 >;
62 dma-channel = < 1 >; 58 dma-channel = < 1 >;
63 }; 59 };
64 60
65 das@70000c00 { 61 das@70000c00 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 compatible = "nvidia,tegra20-das"; 62 compatible = "nvidia,tegra20-das";
69 reg = <0x70000c00 0x80>; 63 reg = <0x70000c00 0x80>;
70 }; 64 };
@@ -72,7 +66,13 @@
72 gpio: gpio@6000d000 { 66 gpio: gpio@6000d000 {
73 compatible = "nvidia,tegra20-gpio"; 67 compatible = "nvidia,tegra20-gpio";
74 reg = < 0x6000d000 0x1000 >; 68 reg = < 0x6000d000 0x1000 >;
75 interrupts = < 64 65 66 67 87 119 121 >; 69 interrupts = < 0 32 0x04
70 0 33 0x04
71 0 34 0x04
72 0 35 0x04
73 0 55 0x04
74 0 87 0x04
75 0 89 0x04 >;
76 #gpio-cells = <2>; 76 #gpio-cells = <2>;
77 gpio-controller; 77 gpio-controller;
78 }; 78 };
@@ -89,59 +89,80 @@
89 compatible = "nvidia,tegra20-uart"; 89 compatible = "nvidia,tegra20-uart";
90 reg = <0x70006000 0x40>; 90 reg = <0x70006000 0x40>;
91 reg-shift = <2>; 91 reg-shift = <2>;
92 interrupts = < 68 >; 92 interrupts = < 0 36 0x04 >;
93 }; 93 };
94 94
95 serial@70006040 { 95 serial@70006040 {
96 compatible = "nvidia,tegra20-uart"; 96 compatible = "nvidia,tegra20-uart";
97 reg = <0x70006040 0x40>; 97 reg = <0x70006040 0x40>;
98 reg-shift = <2>; 98 reg-shift = <2>;
99 interrupts = < 69 >; 99 interrupts = < 0 37 0x04 >;
100 }; 100 };
101 101
102 serial@70006200 { 102 serial@70006200 {
103 compatible = "nvidia,tegra20-uart"; 103 compatible = "nvidia,tegra20-uart";
104 reg = <0x70006200 0x100>; 104 reg = <0x70006200 0x100>;
105 reg-shift = <2>; 105 reg-shift = <2>;
106 interrupts = < 78 >; 106 interrupts = < 0 46 0x04 >;
107 }; 107 };
108 108
109 serial@70006300 { 109 serial@70006300 {
110 compatible = "nvidia,tegra20-uart"; 110 compatible = "nvidia,tegra20-uart";
111 reg = <0x70006300 0x100>; 111 reg = <0x70006300 0x100>;
112 reg-shift = <2>; 112 reg-shift = <2>;
113 interrupts = < 122 >; 113 interrupts = < 0 90 0x04 >;
114 }; 114 };
115 115
116 serial@70006400 { 116 serial@70006400 {
117 compatible = "nvidia,tegra20-uart"; 117 compatible = "nvidia,tegra20-uart";
118 reg = <0x70006400 0x100>; 118 reg = <0x70006400 0x100>;
119 reg-shift = <2>; 119 reg-shift = <2>;
120 interrupts = < 123 >; 120 interrupts = < 0 91 0x04 >;
121 }; 121 };
122 122
123 sdhci@c8000000 { 123 sdhci@c8000000 {
124 compatible = "nvidia,tegra20-sdhci"; 124 compatible = "nvidia,tegra20-sdhci";
125 reg = <0xc8000000 0x200>; 125 reg = <0xc8000000 0x200>;
126 interrupts = < 46 >; 126 interrupts = < 0 14 0x04 >;
127 }; 127 };
128 128
129 sdhci@c8000200 { 129 sdhci@c8000200 {
130 compatible = "nvidia,tegra20-sdhci"; 130 compatible = "nvidia,tegra20-sdhci";
131 reg = <0xc8000200 0x200>; 131 reg = <0xc8000200 0x200>;
132 interrupts = < 47 >; 132 interrupts = < 0 15 0x04 >;
133 }; 133 };
134 134
135 sdhci@c8000400 { 135 sdhci@c8000400 {
136 compatible = "nvidia,tegra20-sdhci"; 136 compatible = "nvidia,tegra20-sdhci";
137 reg = <0xc8000400 0x200>; 137 reg = <0xc8000400 0x200>;
138 interrupts = < 51 >; 138 interrupts = < 0 19 0x04 >;
139 }; 139 };
140 140
141 sdhci@c8000600 { 141 sdhci@c8000600 {
142 compatible = "nvidia,tegra20-sdhci"; 142 compatible = "nvidia,tegra20-sdhci";
143 reg = <0xc8000600 0x200>; 143 reg = <0xc8000600 0x200>;
144 interrupts = < 63 >; 144 interrupts = < 0 31 0x04 >;
145 };
146
147 usb@c5000000 {
148 compatible = "nvidia,tegra20-ehci", "usb-ehci";
149 reg = <0xc5000000 0x4000>;
150 interrupts = < 0 20 0x04 >;
151 phy_type = "utmi";
152 };
153
154 usb@c5004000 {
155 compatible = "nvidia,tegra20-ehci", "usb-ehci";
156 reg = <0xc5004000 0x4000>;
157 interrupts = < 0 21 0x04 >;
158 phy_type = "ulpi";
159 };
160
161 usb@c5008000 {
162 compatible = "nvidia,tegra20-ehci", "usb-ehci";
163 reg = <0xc5008000 0x4000>;
164 interrupts = < 0 97 0x04 >;
165 phy_type = "utmi";
145 }; 166 };
146}; 167};
147 168
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
new file mode 100644
index 000000000000..ee7db9892e02
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -0,0 +1,127 @@
1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>;
6
7 intc: interrupt-controller@50041000 {
8 compatible = "arm,cortex-a9-gic";
9 interrupt-controller;
10 #interrupt-cells = <3>;
11 reg = < 0x50041000 0x1000 >,
12 < 0x50040100 0x0100 >;
13 };
14
15 i2c@7000c000 {
16 #address-cells = <1>;
17 #size-cells = <0>;
18 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
19 reg = <0x7000C000 0x100>;
20 interrupts = < 0 38 0x04 >;
21 };
22
23 i2c@7000c400 {
24 #address-cells = <1>;
25 #size-cells = <0>;
26 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
27 reg = <0x7000C400 0x100>;
28 interrupts = < 0 84 0x04 >;
29 };
30
31 i2c@7000c500 {
32 #address-cells = <1>;
33 #size-cells = <0>;
34 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
35 reg = <0x7000C500 0x100>;
36 interrupts = < 0 92 0x04 >;
37 };
38
39 i2c@7000c700 {
40 #address-cells = <1>;
41 #size-cells = <0>;
42 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
43 reg = <0x7000c700 0x100>;
44 interrupts = < 0 120 0x04 >;
45 };
46
47 i2c@7000d000 {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
51 reg = <0x7000D000 0x100>;
52 interrupts = < 0 53 0x04 >;
53 };
54
55 gpio: gpio@6000d000 {
56 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
57 reg = < 0x6000d000 0x1000 >;
58 interrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >;
59 #gpio-cells = <2>;
60 gpio-controller;
61 };
62
63 serial@70006000 {
64 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
65 reg = <0x70006000 0x40>;
66 reg-shift = <2>;
67 interrupts = < 0 36 0x04 >;
68 };
69
70 serial@70006040 {
71 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
72 reg = <0x70006040 0x40>;
73 reg-shift = <2>;
74 interrupts = < 0 37 0x04 >;
75 };
76
77 serial@70006200 {
78 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
79 reg = <0x70006200 0x100>;
80 reg-shift = <2>;
81 interrupts = < 0 46 0x04 >;
82 };
83
84 serial@70006300 {
85 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
86 reg = <0x70006300 0x100>;
87 reg-shift = <2>;
88 interrupts = < 0 90 0x04 >;
89 };
90
91 serial@70006400 {
92 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
93 reg = <0x70006400 0x100>;
94 reg-shift = <2>;
95 interrupts = < 0 91 0x04 >;
96 };
97
98 sdhci@78000000 {
99 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
100 reg = <0x78000000 0x200>;
101 interrupts = < 0 14 0x04 >;
102 };
103
104 sdhci@78000200 {
105 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
106 reg = <0x78000200 0x200>;
107 interrupts = < 0 15 0x04 >;
108 };
109
110 sdhci@78000400 {
111 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
112 reg = <0x78000400 0x200>;
113 interrupts = < 0 19 0x04 >;
114 };
115
116 sdhci@78000600 {
117 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
118 reg = <0x78000600 0x200>;
119 interrupts = < 0 31 0x04 >;
120 };
121
122 pinmux: pinmux@70000000 {
123 compatible = "nvidia,tegra30-pinmux";
124 reg = < 0x70000868 0xd0 /* Pad control registers */
125 0x70003000 0x3e0 >; /* Mux registers */
126 };
127};
diff --git a/arch/arm/boot/dts/testcases/tests-phandle.dtsi b/arch/arm/boot/dts/testcases/tests-phandle.dtsi
new file mode 100644
index 000000000000..ec0c4e6212c9
--- /dev/null
+++ b/arch/arm/boot/dts/testcases/tests-phandle.dtsi
@@ -0,0 +1,37 @@
1
2/ {
3 testcase-data {
4 phandle-tests {
5 provider0: provider0 {
6 #phandle-cells = <0>;
7 };
8
9 provider1: provider1 {
10 #phandle-cells = <1>;
11 };
12
13 provider2: provider2 {
14 #phandle-cells = <2>;
15 };
16
17 provider3: provider3 {
18 #phandle-cells = <3>;
19 };
20
21 consumer-a {
22 phandle-list = <&provider1 1>,
23 <&provider2 2 0>,
24 <0>,
25 <&provider3 4 4 3>,
26 <&provider2 5 100>,
27 <&provider0>,
28 <&provider1 7>;
29 phandle-list-names = "first", "second", "third";
30
31 phandle-list-bad-phandle = <12345678 0 0>;
32 phandle-list-bad-args = <&provider2 1 0>,
33 <&provider3 0>;
34 };
35 };
36 };
37};
diff --git a/arch/arm/boot/dts/testcases/tests.dtsi b/arch/arm/boot/dts/testcases/tests.dtsi
new file mode 100644
index 000000000000..a7c5067622e8
--- /dev/null
+++ b/arch/arm/boot/dts/testcases/tests.dtsi
@@ -0,0 +1 @@
/include/ "tests-phandle.dtsi"
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index d66e2c00ac35..f04b535477f5 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -25,6 +25,11 @@
25 dbgu: serial@fffff200 { 25 dbgu: serial@fffff200 {
26 status = "okay"; 26 status = "okay";
27 }; 27 };
28
29 macb0: ethernet@fffc4000 {
30 phy-mode = "rmii";
31 status = "okay";
32 };
28 }; 33 };
29 }; 34 };
30}; 35};
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
index 8a614e398004..166461073b78 100644
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -46,3 +46,5 @@
46 }; 46 };
47 }; 47 };
48}; 48};
49
50/include/ "testcases/tests.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 14:49:56 -0500