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-rw-r--r--arch/arm/boot/dts/am335x-bone.dts60
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts100
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi71
-rw-r--r--arch/arm/boot/dts/dbx5x0.dtsi (renamed from arch/arm/boot/dts/db8500.dtsi)71
-rw-r--r--arch/arm/boot/dts/ea3250.dts109
-rw-r--r--arch/arm/boot/dts/elpida_ecb240abacn.dtsi67
-rw-r--r--arch/arm/boot/dts/hrefv60plus.dts95
-rw-r--r--arch/arm/boot/dts/imx23-evk.dts3
-rw-r--r--arch/arm/boot/dts/imx23-olinuxino.dts57
-rw-r--r--arch/arm/boot/dts/imx23-stmp378x_devb.dts2
-rw-r--r--arch/arm/boot/dts/imx23.dtsi38
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore.dts4
-rw-r--r--arch/arm/boot/dts/imx27.dtsi1
-rw-r--r--arch/arm/boot/dts/imx28-apx4devkit.dts2
-rw-r--r--arch/arm/boot/dts/imx28-cfa10049.dts99
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts29
-rw-r--r--arch/arm/boot/dts/imx28-m28evk.dts83
-rw-r--r--arch/arm/boot/dts/imx28-tx28.dts23
-rw-r--r--arch/arm/boot/dts/imx28.dtsi123
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts44
-rw-r--r--arch/arm/boot/dts/imx51.dtsi146
-rw-r--r--arch/arm/boot/dts/imx53-ard.dts59
-rw-r--r--arch/arm/boot/dts/imx53-evk.dts39
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts42
-rw-r--r--arch/arm/boot/dts/imx53-smd.dts46
-rw-r--r--arch/arm/boot/dts/imx53.dtsi199
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts21
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts31
-rw-r--r--arch/arm/boot/dts/imx6q-sabresd.dts25
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi316
-rw-r--r--arch/arm/boot/dts/mmp2.dtsi5
-rw-r--r--arch/arm/boot/dts/msm8660-surf.dts19
-rw-r--r--arch/arm/boot/dts/msm8960-cdp.dts41
-rw-r--r--arch/arm/boot/dts/omap2420-h4.dts2
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi48
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi92
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts (renamed from arch/arm/boot/dts/omap3-beagle.dts)54
-rw-r--r--arch/arm/boot/dts/omap3-evm.dts13
-rw-r--r--arch/arm/boot/dts/omap3-overo.dtsi57
-rw-r--r--arch/arm/boot/dts/omap3-tobi.dts35
-rw-r--r--arch/arm/boot/dts/omap3.dtsi94
-rw-r--r--arch/arm/boot/dts/omap36xx.dtsi25
-rw-r--r--arch/arm/boot/dts/omap4-panda.dts11
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts127
-rw-r--r--arch/arm/boot/dts/omap4.dtsi195
-rw-r--r--arch/arm/boot/dts/omap5-evm.dts64
-rw-r--r--arch/arm/boot/dts/omap5.dtsi139
-rw-r--r--arch/arm/boot/dts/phy3250.dts16
-rw-r--r--arch/arm/boot/dts/prima2-cb.dts424
-rw-r--r--arch/arm/boot/dts/prima2-evb.dts37
-rw-r--r--arch/arm/boot/dts/prima2.dtsi640
-rw-r--r--arch/arm/boot/dts/pxa27x.dtsi14
-rw-r--r--arch/arm/boot/dts/pxa2xx.dtsi132
-rw-r--r--arch/arm/boot/dts/pxa3xx.dtsi32
-rw-r--r--arch/arm/boot/dts/pxa910.dtsi5
-rw-r--r--arch/arm/boot/dts/snowball.dts19
-rw-r--r--arch/arm/boot/dts/tegra20-medcom-wide.dts58
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts173
-rw-r--r--arch/arm/boot/dts/tegra20-plutux.dts50
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts186
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi449
-rw-r--r--arch/arm/boot/dts/tegra20-tec.dts53
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts206
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts295
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a02.dts87
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a04.dts98
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dts171
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi475
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi2
-rw-r--r--arch/arm/boot/dts/tps65217.dtsi56
-rw-r--r--arch/arm/boot/dts/tps65910.dtsi86
-rw-r--r--arch/arm/boot/dts/twl4030.dtsi6
-rw-r--r--arch/arm/boot/dts/twl6030.dtsi26
-rw-r--r--arch/arm/boot/dts/vt8500-bv07.dts36
-rw-r--r--arch/arm/boot/dts/vt8500.dtsi116
-rw-r--r--arch/arm/boot/dts/wm8505-ref.dts36
-rw-r--r--arch/arm/boot/dts/wm8505.dtsi143
-rw-r--r--arch/arm/boot/dts/wm8650-mid.dts36
-rw-r--r--arch/arm/boot/dts/wm8650.dtsi147
80 files changed, 6495 insertions, 843 deletions
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index a9af4db7234c..c634f87e230e 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -17,4 +17,64 @@
17 device_type = "memory"; 17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */ 18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 }; 19 };
20
21 ocp {
22 uart1: serial@44e09000 {
23 status = "okay";
24 };
25
26 i2c1: i2c@44e0b000 {
27 status = "okay";
28 clock-frequency = <400000>;
29
30 tps: tps@24 {
31 reg = <0x24>;
32 };
33
34 };
35 };
36};
37
38/include/ "tps65217.dtsi"
39
40&tps {
41 regulators {
42 dcdc1_reg: regulator@0 {
43 regulator-always-on;
44 };
45
46 dcdc2_reg: regulator@1 {
47 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
48 regulator-name = "vdd_mpu";
49 regulator-min-microvolt = <925000>;
50 regulator-max-microvolt = <1325000>;
51 regulator-boot-on;
52 regulator-always-on;
53 };
54
55 dcdc3_reg: regulator@2 {
56 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
57 regulator-name = "vdd_core";
58 regulator-min-microvolt = <925000>;
59 regulator-max-microvolt = <1150000>;
60 regulator-boot-on;
61 regulator-always-on;
62 };
63
64 ldo1_reg: regulator@3 {
65 regulator-always-on;
66 };
67
68 ldo2_reg: regulator@4 {
69 regulator-always-on;
70 };
71
72 ldo3_reg: regulator@5 {
73 regulator-always-on;
74 };
75
76 ldo4_reg: regulator@6 {
77 regulator-always-on;
78 };
79 };
20}; 80};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d6a97d9eff72..185d6325a458 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -17,4 +17,104 @@
17 device_type = "memory"; 17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */ 18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 }; 19 };
20
21 ocp {
22 uart1: serial@44e09000 {
23 status = "okay";
24 };
25
26 i2c1: i2c@44e0b000 {
27 status = "okay";
28 clock-frequency = <400000>;
29
30 tps: tps@2d {
31 reg = <0x2d>;
32 };
33 };
34 };
35
36 vbat: fixedregulator@0 {
37 compatible = "regulator-fixed";
38 regulator-name = "vbat";
39 regulator-min-microvolt = <5000000>;
40 regulator-max-microvolt = <5000000>;
41 regulator-boot-on;
42 };
43};
44
45/include/ "tps65910.dtsi"
46
47&tps {
48 vcc1-supply = <&vbat>;
49 vcc2-supply = <&vbat>;
50 vcc3-supply = <&vbat>;
51 vcc4-supply = <&vbat>;
52 vcc5-supply = <&vbat>;
53 vcc6-supply = <&vbat>;
54 vcc7-supply = <&vbat>;
55 vccio-supply = <&vbat>;
56
57 regulators {
58 vrtc_reg: regulator@0 {
59 regulator-always-on;
60 };
61
62 vio_reg: regulator@1 {
63 regulator-always-on;
64 };
65
66 vdd1_reg: regulator@2 {
67 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
68 regulator-name = "vdd_mpu";
69 regulator-min-microvolt = <912500>;
70 regulator-max-microvolt = <1312500>;
71 regulator-boot-on;
72 regulator-always-on;
73 };
74
75 vdd2_reg: regulator@3 {
76 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
77 regulator-name = "vdd_core";
78 regulator-min-microvolt = <912500>;
79 regulator-max-microvolt = <1150000>;
80 regulator-boot-on;
81 regulator-always-on;
82 };
83
84 vdd3_reg: regulator@4 {
85 regulator-always-on;
86 };
87
88 vdig1_reg: regulator@5 {
89 regulator-always-on;
90 };
91
92 vdig2_reg: regulator@6 {
93 regulator-always-on;
94 };
95
96 vpll_reg: regulator@7 {
97 regulator-always-on;
98 };
99
100 vdac_reg: regulator@8 {
101 regulator-always-on;
102 };
103
104 vaux1_reg: regulator@9 {
105 regulator-always-on;
106 };
107
108 vaux2_reg: regulator@10 {
109 regulator-always-on;
110 };
111
112 vaux33_reg: regulator@11 {
113 regulator-always-on;
114 };
115
116 vmmc_reg: regulator@12 {
117 regulator-always-on;
118 };
119 };
20}; 120};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bd0cff3f808c..bb31bff01998 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -69,95 +69,146 @@
69 #gpio-cells = <2>; 69 #gpio-cells = <2>;
70 interrupt-controller; 70 interrupt-controller;
71 #interrupt-cells = <1>; 71 #interrupt-cells = <1>;
72 reg = <0x44e07000 0x1000>;
73 interrupt-parent = <&intc>;
74 interrupts = <96>;
72 }; 75 };
73 76
74 gpio2: gpio@4804C000 { 77 gpio2: gpio@4804c000 {
75 compatible = "ti,omap4-gpio"; 78 compatible = "ti,omap4-gpio";
76 ti,hwmods = "gpio2"; 79 ti,hwmods = "gpio2";
77 gpio-controller; 80 gpio-controller;
78 #gpio-cells = <2>; 81 #gpio-cells = <2>;
79 interrupt-controller; 82 interrupt-controller;
80 #interrupt-cells = <1>; 83 #interrupt-cells = <1>;
84 reg = <0x4804c000 0x1000>;
85 interrupt-parent = <&intc>;
86 interrupts = <98>;
81 }; 87 };
82 88
83 gpio3: gpio@481AC000 { 89 gpio3: gpio@481ac000 {
84 compatible = "ti,omap4-gpio"; 90 compatible = "ti,omap4-gpio";
85 ti,hwmods = "gpio3"; 91 ti,hwmods = "gpio3";
86 gpio-controller; 92 gpio-controller;
87 #gpio-cells = <2>; 93 #gpio-cells = <2>;
88 interrupt-controller; 94 interrupt-controller;
89 #interrupt-cells = <1>; 95 #interrupt-cells = <1>;
96 reg = <0x481ac000 0x1000>;
97 interrupt-parent = <&intc>;
98 interrupts = <32>;
90 }; 99 };
91 100
92 gpio4: gpio@481AE000 { 101 gpio4: gpio@481ae000 {
93 compatible = "ti,omap4-gpio"; 102 compatible = "ti,omap4-gpio";
94 ti,hwmods = "gpio4"; 103 ti,hwmods = "gpio4";
95 gpio-controller; 104 gpio-controller;
96 #gpio-cells = <2>; 105 #gpio-cells = <2>;
97 interrupt-controller; 106 interrupt-controller;
98 #interrupt-cells = <1>; 107 #interrupt-cells = <1>;
108 reg = <0x481ae000 0x1000>;
109 interrupt-parent = <&intc>;
110 interrupts = <62>;
99 }; 111 };
100 112
101 uart1: serial@44E09000 { 113 uart1: serial@44e09000 {
102 compatible = "ti,omap3-uart"; 114 compatible = "ti,omap3-uart";
103 ti,hwmods = "uart1"; 115 ti,hwmods = "uart1";
104 clock-frequency = <48000000>; 116 clock-frequency = <48000000>;
117 reg = <0x44e09000 0x2000>;
118 interrupt-parent = <&intc>;
119 interrupts = <72>;
120 status = "disabled";
105 }; 121 };
106 122
107 uart2: serial@48022000 { 123 uart2: serial@48022000 {
108 compatible = "ti,omap3-uart"; 124 compatible = "ti,omap3-uart";
109 ti,hwmods = "uart2"; 125 ti,hwmods = "uart2";
110 clock-frequency = <48000000>; 126 clock-frequency = <48000000>;
127 reg = <0x48022000 0x2000>;
128 interrupt-parent = <&intc>;
129 interrupts = <73>;
130 status = "disabled";
111 }; 131 };
112 132
113 uart3: serial@48024000 { 133 uart3: serial@48024000 {
114 compatible = "ti,omap3-uart"; 134 compatible = "ti,omap3-uart";
115 ti,hwmods = "uart3"; 135 ti,hwmods = "uart3";
116 clock-frequency = <48000000>; 136 clock-frequency = <48000000>;
137 reg = <0x48024000 0x2000>;
138 interrupt-parent = <&intc>;
139 interrupts = <74>;
140 status = "disabled";
117 }; 141 };
118 142
119 uart4: serial@481A6000 { 143 uart4: serial@481a6000 {
120 compatible = "ti,omap3-uart"; 144 compatible = "ti,omap3-uart";
121 ti,hwmods = "uart4"; 145 ti,hwmods = "uart4";
122 clock-frequency = <48000000>; 146 clock-frequency = <48000000>;
147 reg = <0x481a6000 0x2000>;
148 interrupt-parent = <&intc>;
149 interrupts = <44>;
150 status = "disabled";
123 }; 151 };
124 152
125 uart5: serial@481A8000 { 153 uart5: serial@481a8000 {
126 compatible = "ti,omap3-uart"; 154 compatible = "ti,omap3-uart";
127 ti,hwmods = "uart5"; 155 ti,hwmods = "uart5";
128 clock-frequency = <48000000>; 156 clock-frequency = <48000000>;
157 reg = <0x481a8000 0x2000>;
158 interrupt-parent = <&intc>;
159 interrupts = <45>;
160 status = "disabled";
129 }; 161 };
130 162
131 uart6: serial@481AA000 { 163 uart6: serial@481aa000 {
132 compatible = "ti,omap3-uart"; 164 compatible = "ti,omap3-uart";
133 ti,hwmods = "uart6"; 165 ti,hwmods = "uart6";
134 clock-frequency = <48000000>; 166 clock-frequency = <48000000>;
167 reg = <0x481aa000 0x2000>;
168 interrupt-parent = <&intc>;
169 interrupts = <46>;
170 status = "disabled";
135 }; 171 };
136 172
137 i2c1: i2c@44E0B000 { 173 i2c1: i2c@44e0b000 {
138 compatible = "ti,omap4-i2c"; 174 compatible = "ti,omap4-i2c";
139 #address-cells = <1>; 175 #address-cells = <1>;
140 #size-cells = <0>; 176 #size-cells = <0>;
141 ti,hwmods = "i2c1"; 177 ti,hwmods = "i2c1";
178 reg = <0x44e0b000 0x1000>;
179 interrupt-parent = <&intc>;
180 interrupts = <70>;
181 status = "disabled";
142 }; 182 };
143 183
144 i2c2: i2c@4802A000 { 184 i2c2: i2c@4802a000 {
145 compatible = "ti,omap4-i2c"; 185 compatible = "ti,omap4-i2c";
146 #address-cells = <1>; 186 #address-cells = <1>;
147 #size-cells = <0>; 187 #size-cells = <0>;
148 ti,hwmods = "i2c2"; 188 ti,hwmods = "i2c2";
189 reg = <0x4802a000 0x1000>;
190 interrupt-parent = <&intc>;
191 interrupts = <71>;
192 status = "disabled";
149 }; 193 };
150 194
151 i2c3: i2c@4819C000 { 195 i2c3: i2c@4819c000 {
152 compatible = "ti,omap4-i2c"; 196 compatible = "ti,omap4-i2c";
153 #address-cells = <1>; 197 #address-cells = <1>;
154 #size-cells = <0>; 198 #size-cells = <0>;
155 ti,hwmods = "i2c3"; 199 ti,hwmods = "i2c3";
200 reg = <0x4819c000 0x1000>;
201 interrupt-parent = <&intc>;
202 interrupts = <30>;
203 status = "disabled";
156 }; 204 };
157 205
158 wdt2: wdt@44e35000 { 206 wdt2: wdt@44e35000 {
159 compatible = "ti,omap3-wdt"; 207 compatible = "ti,omap3-wdt";
160 ti,hwmods = "wd_timer2"; 208 ti,hwmods = "wd_timer2";
209 reg = <0x44e35000 0x1000>;
210 interrupt-parent = <&intc>;
211 interrupts = <91>;
161 }; 212 };
162 }; 213 };
163}; 214};
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 3180a9c588b9..748ba7aa746c 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -194,6 +194,8 @@
194 interrupts = <0 47 0x4>; 194 interrupts = <0 47 0x4>;
195 #address-cells = <1>; 195 #address-cells = <1>;
196 #size-cells = <1>; 196 #size-cells = <1>;
197 interrupt-controller;
198 #interrupt-cells = <2>;
197 ranges; 199 ranges;
198 200
199 prcmu-timer-4@80157450 { 201 prcmu-timer-4@80157450 {
@@ -330,6 +332,7 @@
330 ab8500@5 { 332 ab8500@5 {
331 compatible = "stericsson,ab8500"; 333 compatible = "stericsson,ab8500";
332 reg = <5>; /* mailbox 5 is i2c */ 334 reg = <5>; /* mailbox 5 is i2c */
335 interrupt-parent = <&intc>;
333 interrupts = <0 40 0x4>; 336 interrupts = <0 40 0x4>;
334 interrupt-controller; 337 interrupt-controller;
335 #interrupt-cells = <2>; 338 #interrupt-cells = <2>;
@@ -371,7 +374,7 @@
371 }; 374 };
372 375
373 ab8500-ponkey { 376 ab8500-ponkey {
374 compatible = "stericsson,ab8500-ponkey"; 377 compatible = "stericsson,ab8500-poweron-key";
375 interrupts = <6 0x4 378 interrupts = <6 0x4
376 7 0x4>; 379 7 0x4>;
377 interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; 380 interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
@@ -389,6 +392,12 @@
389 compatible = "stericsson,ab8500-debug"; 392 compatible = "stericsson,ab8500-debug";
390 }; 393 };
391 394
395 codec: ab8500-codec {
396 compatible = "stericsson,ab8500-codec";
397
398 stericsson,earpeice-cmv = <950>; /* Units in mV. */
399 };
400
392 ab8500-regulators { 401 ab8500-regulators {
393 compatible = "stericsson,ab8500-regulator"; 402 compatible = "stericsson,ab8500-regulator";
394 403
@@ -471,48 +480,63 @@
471 }; 480 };
472 481
473 i2c@80004000 { 482 i2c@80004000 {
474 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; 483 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
475 reg = <0x80004000 0x1000>; 484 reg = <0x80004000 0x1000>;
476 interrupts = <0 21 0x4>; 485 interrupts = <0 21 0x4>;
477 #address-cells = <1>; 486 #address-cells = <1>;
478 #size-cells = <0>; 487 #size-cells = <0>;
488 v-i2c-supply = <&db8500_vape_reg>;
489
490 clock-frequency = <400000>;
479 }; 491 };
480 492
481 i2c@80122000 { 493 i2c@80122000 {
482 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; 494 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
483 reg = <0x80122000 0x1000>; 495 reg = <0x80122000 0x1000>;
484 interrupts = <0 22 0x4>; 496 interrupts = <0 22 0x4>;
485 #address-cells = <1>; 497 #address-cells = <1>;
486 #size-cells = <0>; 498 #size-cells = <0>;
499 v-i2c-supply = <&db8500_vape_reg>;
500
501 clock-frequency = <400000>;
487 }; 502 };
488 503
489 i2c@80128000 { 504 i2c@80128000 {
490 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; 505 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
491 reg = <0x80128000 0x1000>; 506 reg = <0x80128000 0x1000>;
492 interrupts = <0 55 0x4>; 507 interrupts = <0 55 0x4>;
493 #address-cells = <1>; 508 #address-cells = <1>;
494 #size-cells = <0>; 509 #size-cells = <0>;
510 v-i2c-supply = <&db8500_vape_reg>;
511
512 clock-frequency = <400000>;
495 }; 513 };
496 514
497 i2c@80110000 { 515 i2c@80110000 {
498 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; 516 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
499 reg = <0x80110000 0x1000>; 517 reg = <0x80110000 0x1000>;
500 interrupts = <0 12 0x4>; 518 interrupts = <0 12 0x4>;
501 #address-cells = <1>; 519 #address-cells = <1>;
502 #size-cells = <0>; 520 #size-cells = <0>;
521 v-i2c-supply = <&db8500_vape_reg>;
522
523 clock-frequency = <400000>;
503 }; 524 };
504 525
505 i2c@8012a000 { 526 i2c@8012a000 {
506 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; 527 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
507 reg = <0x8012a000 0x1000>; 528 reg = <0x8012a000 0x1000>;
508 interrupts = <0 51 0x4>; 529 interrupts = <0 51 0x4>;
509 #address-cells = <1>; 530 #address-cells = <1>;
510 #size-cells = <0>; 531 #size-cells = <0>;
532 v-i2c-supply = <&db8500_vape_reg>;
533
534 clock-frequency = <400000>;
511 }; 535 };
512 536
513 ssp@80002000 { 537 ssp@80002000 {
514 compatible = "arm,pl022", "arm,primecell"; 538 compatible = "arm,pl022", "arm,primecell";
515 reg = <80002000 0x1000>; 539 reg = <0x80002000 0x1000>;
516 interrupts = <0 14 0x4>; 540 interrupts = <0 14 0x4>;
517 #address-cells = <1>; 541 #address-cells = <1>;
518 #size-cells = <0>; 542 #size-cells = <0>;
@@ -580,6 +604,39 @@
580 status = "disabled"; 604 status = "disabled";
581 }; 605 };
582 606
607 msp0: msp@80123000 {
608 compatible = "stericsson,ux500-msp-i2s";
609 reg = <0x80123000 0x1000>;
610 interrupts = <0 31 0x4>;
611 v-ape-supply = <&db8500_vape_reg>;
612 status = "disabled";
613 };
614
615 msp1: msp@80124000 {
616 compatible = "stericsson,ux500-msp-i2s";
617 reg = <0x80124000 0x1000>;
618 interrupts = <0 62 0x4>;
619 v-ape-supply = <&db8500_vape_reg>;
620 status = "disabled";
621 };
622
623 // HDMI sound
624 msp2: msp@80117000 {
625 compatible = "stericsson,ux500-msp-i2s";
626 reg = <0x80117000 0x1000>;
627 interrupts = <0 98 0x4>;
628 v-ape-supply = <&db8500_vape_reg>;
629 status = "disabled";
630 };
631
632 msp3: msp@80125000 {
633 compatible = "stericsson,ux500-msp-i2s";
634 reg = <0x80125000 0x1000>;
635 interrupts = <0 62 0x4>;
636 v-ape-supply = <&db8500_vape_reg>;
637 status = "disabled";
638 };
639
583 external-bus@50000000 { 640 external-bus@50000000 {
584 compatible = "simple-bus"; 641 compatible = "simple-bus";
585 reg = <0x50000000 0x4000000>; 642 reg = <0x50000000 0x4000000>;
diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts
index d79b28d9c963..a4ba31b23c88 100644
--- a/arch/arm/boot/dts/ea3250.dts
+++ b/arch/arm/boot/dts/ea3250.dts
@@ -166,9 +166,116 @@
166 #size-cells = <0>; 166 #size-cells = <0>;
167 autorepeat; 167 autorepeat;
168 button@21 { 168 button@21 {
169 label = "GPIO Key UP"; 169 label = "Interrupt Key";
170 linux,code = <103>; 170 linux,code = <103>;
171 gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ 171 gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
172 }; 172 };
173 key1 {
174 label = "KEY1";
175 linux,code = <1>;
176 gpios = <&pca9532 0 0>;
177 };
178 key2 {
179 label = "KEY2";
180 linux,code = <2>;
181 gpios = <&pca9532 1 0>;
182 };
183 key3 {
184 label = "KEY3";
185 linux,code = <3>;
186 gpios = <&pca9532 2 0>;
187 };
188 key4 {
189 label = "KEY4";
190 linux,code = <4>;
191 gpios = <&pca9532 3 0>;
192 };
193 joy0 {
194 label = "Joystick Key 0";
195 linux,code = <10>;
196 gpios = <&gpio 2 0 0>; /* P2.0 */
197 };
198 joy1 {
199 label = "Joystick Key 1";
200 linux,code = <11>;
201 gpios = <&gpio 2 1 0>; /* P2.1 */
202 };
203 joy2 {
204 label = "Joystick Key 2";
205 linux,code = <12>;
206 gpios = <&gpio 2 2 0>; /* P2.2 */
207 };
208 joy3 {
209 label = "Joystick Key 3";
210 linux,code = <13>;
211 gpios = <&gpio 2 3 0>; /* P2.3 */
212 };
213 joy4 {
214 label = "Joystick Key 4";
215 linux,code = <14>;
216 gpios = <&gpio 2 4 0>; /* P2.4 */
217 };
218 };
219
220 leds {
221 compatible = "gpio-leds";
222
223 /* LEDs on OEM Board */
224
225 led1 {
226 gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
227 linux,default-trigger = "timer";
228 default-state = "off";
229 };
230
231 led2 {
232 gpios = <&gpio 2 10 1>; /* P2.10, active low */
233 default-state = "off";
234 };
235
236 led3 {
237 gpios = <&gpio 2 11 1>; /* P2.11, active low */
238 default-state = "off";
239 };
240
241 led4 {
242 gpios = <&gpio 2 12 1>; /* P2.12, active low */
243 default-state = "off";
244 };
245
246 /* LEDs on Base Board */
247
248 lede1 {
249 gpios = <&pca9532 8 0>;
250 default-state = "off";
251 };
252 lede2 {
253 gpios = <&pca9532 9 0>;
254 default-state = "off";
255 };
256 lede3 {
257 gpios = <&pca9532 10 0>;
258 default-state = "off";
259 };
260 lede4 {
261 gpios = <&pca9532 11 0>;
262 default-state = "off";
263 };
264 lede5 {
265 gpios = <&pca9532 12 0>;
266 default-state = "off";
267 };
268 lede6 {
269 gpios = <&pca9532 13 0>;
270 default-state = "off";
271 };
272 lede7 {
273 gpios = <&pca9532 14 0>;
274 default-state = "off";
275 };
276 lede8 {
277 gpios = <&pca9532 15 0>;
278 default-state = "off";
279 };
173 }; 280 };
174}; 281};
diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
new file mode 100644
index 000000000000..f97f70f83374
--- /dev/null
+++ b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
@@ -0,0 +1,67 @@
1/*
2 * Common devices used in different OMAP boards
3 */
4
5/ {
6 elpida_ECB240ABACN: lpddr2 {
7 compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
8 density = <2048>;
9 io-width = <32>;
10
11 tRPab-min-tck = <3>;
12 tRCD-min-tck = <3>;
13 tWR-min-tck = <3>;
14 tRASmin-min-tck = <3>;
15 tRRD-min-tck = <2>;
16 tWTR-min-tck = <2>;
17 tXP-min-tck = <2>;
18 tRTP-min-tck = <2>;
19 tCKE-min-tck = <3>;
20 tCKESR-min-tck = <3>;
21 tFAW-min-tck = <8>;
22
23 timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
24 compatible = "jedec,lpddr2-timings";
25 min-freq = <10000000>;
26 max-freq = <400000000>;
27 tRPab = <21000>;
28 tRCD = <18000>;
29 tWR = <15000>;
30 tRAS-min = <42000>;
31 tRRD = <10000>;
32 tWTR = <7500>;
33 tXP = <7500>;
34 tRTP = <7500>;
35 tCKESR = <15000>;
36 tDQSCK-max = <5500>;
37 tFAW = <50000>;
38 tZQCS = <90000>;
39 tZQCL = <360000>;
40 tZQinit = <1000000>;
41 tRAS-max-ns = <70000>;
42 tDQSCK-max-derated = <6000>;
43 };
44
45 timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
46 compatible = "jedec,lpddr2-timings";
47 min-freq = <10000000>;
48 max-freq = <200000000>;
49 tRPab = <21000>;
50 tRCD = <18000>;
51 tWR = <15000>;
52 tRAS-min = <42000>;
53 tRRD = <10000>;
54 tWTR = <10000>;
55 tXP = <7500>;
56 tRTP = <7500>;
57 tCKESR = <15000>;
58 tDQSCK-max = <5500>;
59 tFAW = <50000>;
60 tZQCS = <90000>;
61 tZQCL = <360000>;
62 tZQinit = <1000000>;
63 tRAS-max-ns = <70000>;
64 tDQSCK-max-derated = <6000>;
65 };
66 };
67};
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts
new file mode 100644
index 000000000000..2131d77dc9c9
--- /dev/null
+++ b/arch/arm/boot/dts/hrefv60plus.dts
@@ -0,0 +1,95 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "dbx5x0.dtsi"
14
15/ {
16 model = "ST-Ericsson HREF platform with Device Tree";
17 compatible = "st-ericsson,hrefv60+";
18
19 memory {
20 reg = <0x00000000 0x20000000>;
21 };
22
23 soc-u9500 {
24 uart@80120000 {
25 status = "okay";
26 };
27
28 uart@80121000 {
29 status = "okay";
30 };
31
32 uart@80007000 {
33 status = "okay";
34 };
35
36 i2c@80004000 {
37 tc3589x@42 {
38 compatible = "tc3589x";
39 reg = <0x42>;
40 interrupt-parent = <&gpio6>;
41 interrupts = <25 0x1>;
42
43 interrupt-controller;
44 #interrupt-cells = <2>;
45
46 tc3589x_gpio: tc3589x_gpio {
47 compatible = "tc3589x-gpio";
48 interrupts = <0 0x1>;
49
50 interrupt-controller;
51 #interrupt-cells = <2>;
52 gpio-controller;
53 #gpio-cells = <2>;
54 };
55 };
56
57 tps61052@33 {
58 compatible = "tps61052";
59 reg = <0x33>;
60 };
61 };
62
63 i2c@80128000 {
64 lp5521@0x33 {
65 compatible = "lp5521";
66 reg = <0x33>;
67 };
68
69 lp5521@0x34 {
70 compatible = "lp5521";
71 reg = <0x34>;
72 };
73
74 bh1780@0x29 {
75 compatible = "rohm,bh1780gli";
76 reg = <0x33>;
77 };
78 };
79
80 sound {
81 compatible = "stericsson,snd-soc-mop500";
82
83 stericsson,cpu-dai = <&msp1 &msp3>;
84 stericsson,audio-codec = <&codec>;
85 };
86
87 msp1: msp@80124000 {
88 status = "okay";
89 };
90
91 msp3: msp@80125000 {
92 status = "okay";
93 };
94 };
95};
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index e3486f486b40..035c13f9d3c0 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -42,12 +42,13 @@
42 pinctrl-names = "default"; 42 pinctrl-names = "default";
43 pinctrl-0 = <&hog_pins_a>; 43 pinctrl-0 = <&hog_pins_a>;
44 44
45 hog_pins_a: hog-gpios@0 { 45 hog_pins_a: hog@0 {
46 reg = <0>; 46 reg = <0>;
47 fsl,pinmux-ids = < 47 fsl,pinmux-ids = <
48 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */ 48 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */
49 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ 49 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
50 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ 50 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
51 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
51 >; 52 >;
52 fsl,drive-strength = <0>; 53 fsl,drive-strength = <0>;
53 fsl,voltage = <1>; 54 fsl,voltage = <1>;
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index 20912b1d8893..384d8b66f337 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -31,6 +31,22 @@
31 bus-width = <4>; 31 bus-width = <4>;
32 status = "okay"; 32 status = "okay";
33 }; 33 };
34
35 pinctrl@80018000 {
36 pinctrl-names = "default";
37 pinctrl-0 = <&hog_pins_a>;
38
39 hog_pins_a: hog@0 {
40 reg = <0>;
41 fsl,pinmux-ids = <
42 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
43 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
44 >;
45 fsl,drive-strength = <0>;
46 fsl,voltage = <1>;
47 fsl,pull-up = <0>;
48 };
49 };
34 }; 50 };
35 51
36 apbx@80040000 { 52 apbx@80040000 {
@@ -39,6 +55,47 @@
39 pinctrl-0 = <&duart_pins_a>; 55 pinctrl-0 = <&duart_pins_a>;
40 status = "okay"; 56 status = "okay";
41 }; 57 };
58
59 auart0: serial@8006c000 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&auart0_2pins_a>;
62 status = "okay";
63 };
64
65 usbphy0: usbphy@8007c000 {
66 status = "okay";
67 };
68 };
69 };
70
71 ahb@80080000 {
72 usb0: usb@80080000 {
73 vbus-supply = <&reg_usb0_vbus>;
74 status = "okay";
75 };
76 };
77
78 regulators {
79 compatible = "simple-bus";
80
81 reg_usb0_vbus: usb0_vbus {
82 compatible = "regulator-fixed";
83 regulator-name = "usb0_vbus";
84 regulator-min-microvolt = <5000000>;
85 regulator-max-microvolt = <5000000>;
86 enable-active-high;
87 startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */
88 gpio = <&gpio0 17 0>;
89 };
90 };
91
92 leds {
93 compatible = "gpio-leds";
94
95 user {
96 label = "green";
97 gpios = <&gpio2 1 0>;
98 linux,default-trigger = "default-on";
42 }; 99 };
43 }; 100 };
44}; 101};
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
index 757a327ff3e8..85c3864b6a56 100644
--- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -36,7 +36,7 @@
36 pinctrl-names = "default"; 36 pinctrl-names = "default";
37 pinctrl-0 = <&hog_pins_a>; 37 pinctrl-0 = <&hog_pins_a>;
38 38
39 hog_pins_a: hog-gpios@0 { 39 hog_pins_a: hog@0 {
40 reg = <0>; 40 reg = <0>;
41 fsl,pinmux-ids = < 41 fsl,pinmux-ids = <
42 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ 42 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index e6138310e5ce..3f3b6fc229b3 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -52,6 +52,7 @@
52 dma-apbh@80004000 { 52 dma-apbh@80004000 {
53 compatible = "fsl,imx23-dma-apbh"; 53 compatible = "fsl,imx23-dma-apbh";
54 reg = <0x80004000 0x2000>; 54 reg = <0x80004000 0x2000>;
55 clocks = <&clks 15>;
55 }; 56 };
56 57
57 ecc@80008000 { 58 ecc@80008000 {
@@ -67,6 +68,7 @@
67 reg-names = "gpmi-nand", "bch"; 68 reg-names = "gpmi-nand", "bch";
68 interrupts = <13>, <56>; 69 interrupts = <13>, <56>;
69 interrupt-names = "gpmi-dma", "bch"; 70 interrupt-names = "gpmi-dma", "bch";
71 clocks = <&clks 34>;
70 fsl,gpmi-dma-channel = <4>; 72 fsl,gpmi-dma-channel = <4>;
71 status = "disabled"; 73 status = "disabled";
72 }; 74 };
@@ -74,6 +76,7 @@
74 ssp0: ssp@80010000 { 76 ssp0: ssp@80010000 {
75 reg = <0x80010000 0x2000>; 77 reg = <0x80010000 0x2000>;
76 interrupts = <15 14>; 78 interrupts = <15 14>;
79 clocks = <&clks 33>;
77 fsl,ssp-dma-channel = <1>; 80 fsl,ssp-dma-channel = <1>;
78 status = "disabled"; 81 status = "disabled";
79 }; 82 };
@@ -140,6 +143,17 @@
140 fsl,pull-up = <0>; 143 fsl,pull-up = <0>;
141 }; 144 };
142 145
146 auart0_2pins_a: auart0-2pins@0 {
147 reg = <0>;
148 fsl,pinmux-ids = <
149 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */
150 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */
151 >;
152 fsl,drive-strength = <0>;
153 fsl,voltage = <1>;
154 fsl,pull-up = <0>;
155 };
156
143 gpmi_pins_a: gpmi-nand@0 { 157 gpmi_pins_a: gpmi-nand@0 {
144 reg = <0>; 158 reg = <0>;
145 fsl,pinmux-ids = < 159 fsl,pinmux-ids = <
@@ -183,7 +197,6 @@
183 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ 197 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
184 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ 198 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
185 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ 199 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
186 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
187 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ 200 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
188 >; 201 >;
189 fsl,drive-strength = <1>; 202 fsl,drive-strength = <1>;
@@ -280,6 +293,7 @@
280 dma-apbx@80024000 { 293 dma-apbx@80024000 {
281 compatible = "fsl,imx23-dma-apbx"; 294 compatible = "fsl,imx23-dma-apbx";
282 reg = <0x80024000 0x2000>; 295 reg = <0x80024000 0x2000>;
296 clocks = <&clks 16>;
283 }; 297 };
284 298
285 dcp@80028000 { 299 dcp@80028000 {
@@ -306,12 +320,14 @@
306 compatible = "fsl,imx23-lcdif"; 320 compatible = "fsl,imx23-lcdif";
307 reg = <0x80030000 2000>; 321 reg = <0x80030000 2000>;
308 interrupts = <46 45>; 322 interrupts = <46 45>;
323 clocks = <&clks 38>;
309 status = "disabled"; 324 status = "disabled";
310 }; 325 };
311 326
312 ssp1: ssp@80034000 { 327 ssp1: ssp@80034000 {
313 reg = <0x80034000 0x2000>; 328 reg = <0x80034000 0x2000>;
314 interrupts = <2 20>; 329 interrupts = <2 20>;
330 clocks = <&clks 33>;
315 fsl,ssp-dma-channel = <2>; 331 fsl,ssp-dma-channel = <2>;
316 status = "disabled"; 332 status = "disabled";
317 }; 333 };
@@ -329,9 +345,10 @@
329 reg = <0x80040000 0x40000>; 345 reg = <0x80040000 0x40000>;
330 ranges; 346 ranges;
331 347
332 clkctl@80040000 { 348 clks: clkctrl@80040000 {
349 compatible = "fsl,imx23-clkctrl";
333 reg = <0x80040000 0x2000>; 350 reg = <0x80040000 0x2000>;
334 status = "disabled"; 351 #clock-cells = <1>;
335 }; 352 };
336 353
337 saif0: saif@80042000 { 354 saif0: saif@80042000 {
@@ -383,6 +400,7 @@
383 pwm: pwm@80064000 { 400 pwm: pwm@80064000 {
384 compatible = "fsl,imx23-pwm"; 401 compatible = "fsl,imx23-pwm";
385 reg = <0x80064000 0x2000>; 402 reg = <0x80064000 0x2000>;
403 clocks = <&clks 30>;
386 #pwm-cells = <2>; 404 #pwm-cells = <2>;
387 fsl,pwm-number = <5>; 405 fsl,pwm-number = <5>;
388 status = "disabled"; 406 status = "disabled";
@@ -397,6 +415,7 @@
397 compatible = "fsl,imx23-auart"; 415 compatible = "fsl,imx23-auart";
398 reg = <0x8006c000 0x2000>; 416 reg = <0x8006c000 0x2000>;
399 interrupts = <24 25 23>; 417 interrupts = <24 25 23>;
418 clocks = <&clks 32>;
400 status = "disabled"; 419 status = "disabled";
401 }; 420 };
402 421
@@ -404,6 +423,7 @@
404 compatible = "fsl,imx23-auart"; 423 compatible = "fsl,imx23-auart";
405 reg = <0x8006e000 0x2000>; 424 reg = <0x8006e000 0x2000>;
406 interrupts = <59 60 58>; 425 interrupts = <59 60 58>;
426 clocks = <&clks 32>;
407 status = "disabled"; 427 status = "disabled";
408 }; 428 };
409 429
@@ -411,11 +431,15 @@
411 compatible = "arm,pl011", "arm,primecell"; 431 compatible = "arm,pl011", "arm,primecell";
412 reg = <0x80070000 0x2000>; 432 reg = <0x80070000 0x2000>;
413 interrupts = <0>; 433 interrupts = <0>;
434 clocks = <&clks 32>, <&clks 16>;
435 clock-names = "uart", "apb_pclk";
414 status = "disabled"; 436 status = "disabled";
415 }; 437 };
416 438
417 usbphy@8007c000 { 439 usbphy0: usbphy@8007c000 {
440 compatible = "fsl,imx23-usbphy";
418 reg = <0x8007c000 0x2000>; 441 reg = <0x8007c000 0x2000>;
442 clocks = <&clks 41>;
419 status = "disabled"; 443 status = "disabled";
420 }; 444 };
421 }; 445 };
@@ -428,8 +452,12 @@
428 reg = <0x80080000 0x80000>; 452 reg = <0x80080000 0x80000>;
429 ranges; 453 ranges;
430 454
431 usbctrl@80080000 { 455 usb0: usb@80080000 {
456 compatible = "fsl,imx23-usb", "fsl,imx27-usb";
432 reg = <0x80080000 0x40000>; 457 reg = <0x80080000 0x40000>;
458 interrupts = <11>;
459 fsl,usbphy = <&usbphy0>;
460 clocks = <&clks 40>;
433 status = "disabled"; 461 status = "disabled";
434 }; 462 };
435 }; 463 };
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index 2acc86cfdd05..af50469e34b2 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -23,10 +23,6 @@
23 soc { 23 soc {
24 aipi@10000000 { /* aipi */ 24 aipi@10000000 { /* aipi */
25 25
26 wdog@10002000 {
27 status = "okay";
28 };
29
30 serial@1000a000 { 26 serial@1000a000 {
31 fsl,uart-has-rtscts; 27 fsl,uart-has-rtscts;
32 status = "okay"; 28 status = "okay";
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 5303ab680a34..3e54f1498841 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -62,7 +62,6 @@
62 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; 62 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
63 reg = <0x10002000 0x4000>; 63 reg = <0x10002000 0x4000>;
64 interrupts = <27>; 64 interrupts = <27>;
65 status = "disabled";
66 }; 65 };
67 66
68 uart1: serial@1000a000 { 67 uart1: serial@1000a000 {
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index b383417a558f..5171667a7763 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -37,7 +37,7 @@
37 pinctrl-names = "default"; 37 pinctrl-names = "default";
38 pinctrl-0 = <&hog_pins_a>; 38 pinctrl-0 = <&hog_pins_a>;
39 39
40 hog_pins_a: hog-gpios@0 { 40 hog_pins_a: hog@0 {
41 reg = <0>; 41 reg = <0>;
42 fsl,pinmux-ids = < 42 fsl,pinmux-ids = <
43 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ 43 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
new file mode 100644
index 000000000000..05c892e931e3
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -0,0 +1,99 @@
1/*
2 * Copyright 2012 Free Electrons
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/*
13 * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
14 * need to include the CFA-10036 DTS.
15 */
16/include/ "imx28-cfa10036.dts"
17
18/ {
19 model = "Crystalfontz CFA-10049 Board";
20 compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
21
22 apb@80000000 {
23 apbh@80000000 {
24 pinctrl@80018000 {
25 spi3_pins_cfa10049: spi3-cfa10049@0 {
26 reg = <0>;
27 fsl,pinmux-ids = <
28 0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */
29 0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */
30 0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */
31 0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */
32 >;
33 fsl,drive-strength = <1>;
34 fsl,voltage = <1>;
35 fsl,pull-up = <1>;
36 };
37 };
38
39 ssp3: ssp@80016000 {
40 compatible = "fsl,imx28-spi";
41 pinctrl-names = "default";
42 pinctrl-0 = <&spi3_pins_cfa10049>;
43 status = "okay";
44
45 gpio5: gpio5@0 {
46 compatible = "fairchild,74hc595";
47 gpio-controller;
48 #gpio-cells = <2>;
49 reg = <0>;
50 registers-number = <2>;
51 spi-max-frequency = <100000>;
52 };
53
54 gpio6: gpio6@1 {
55 compatible = "fairchild,74hc595";
56 gpio-controller;
57 #gpio-cells = <2>;
58 reg = <1>;
59 registers-number = <4>;
60 spi-max-frequency = <100000>;
61 };
62
63 };
64 };
65
66 apbx@80040000 {
67 i2c1: i2c@8005a000 {
68 pinctrl-names = "default";
69 pinctrl-0 = <&i2c1_pins_a>;
70 status = "okay";
71 };
72
73 usbphy1: usbphy@8007e000 {
74 status = "okay";
75 };
76 };
77 };
78
79 ahb@80080000 {
80 usb1: usb@80090000 {
81 vbus-supply = <&reg_usb1_vbus>;
82 pinctrl-0 = <&usbphy1_pins_a>;
83 pinctrl-names = "default";
84 status = "okay";
85 };
86 };
87
88 regulators {
89 compatible = "simple-bus";
90
91 reg_usb1_vbus: usb1_vbus {
92 compatible = "regulator-fixed";
93 regulator-name = "usb1_vbus";
94 regulator-min-microvolt = <5000000>;
95 regulator-max-microvolt = <5000000>;
96 gpio = <&gpio0 7 1>;
97 };
98 };
99};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 773c0e84d1fb..a0ad71ca3a44 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -46,11 +46,28 @@
46 wp-gpios = <&gpio0 28 0>; 46 wp-gpios = <&gpio0 28 0>;
47 }; 47 };
48 48
49 ssp2: ssp@80014000 {
50 #address-cells = <1>;
51 #size-cells = <0>;
52 compatible = "fsl,imx28-spi";
53 pinctrl-names = "default";
54 pinctrl-0 = <&spi2_pins_a>;
55 status = "okay";
56
57 flash: m25p80@0 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "sst,sst25vf016b";
61 spi-max-frequency = <40000000>;
62 reg = <0>;
63 };
64 };
65
49 pinctrl@80018000 { 66 pinctrl@80018000 {
50 pinctrl-names = "default"; 67 pinctrl-names = "default";
51 pinctrl-0 = <&hog_pins_a>; 68 pinctrl-0 = <&hog_pins_a>;
52 69
53 hog_pins_a: hog-gpios@0 { 70 hog_pins_a: hog@0 {
54 reg = <0>; 71 reg = <0>;
55 fsl,pinmux-ids = < 72 fsl,pinmux-ids = <
56 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */ 73 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */
@@ -128,6 +145,10 @@
128 status = "okay"; 145 status = "okay";
129 }; 146 };
130 147
148 lradc@80050000 {
149 status = "okay";
150 };
151
131 i2c0: i2c@80058000 { 152 i2c0: i2c@80058000 {
132 pinctrl-names = "default"; 153 pinctrl-names = "default";
133 pinctrl-0 = <&i2c0_pins_a>; 154 pinctrl-0 = <&i2c0_pins_a>;
@@ -140,6 +161,12 @@
140 VDDIO-supply = <&reg_3p3v>; 161 VDDIO-supply = <&reg_3p3v>;
141 162
142 }; 163 };
164
165 at24@51 {
166 compatible = "at24,24c32";
167 pagesize = <32>;
168 reg = <0x51>;
169 };
143 }; 170 };
144 171
145 pwm: pwm@80064000 { 172 pwm: pwm@80064000 {
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 183a3fd2d859..3bab6b00c52d 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -23,6 +23,8 @@
23 apb@80000000 { 23 apb@80000000 {
24 apbh@80000000 { 24 apbh@80000000 {
25 gpmi-nand@8000c000 { 25 gpmi-nand@8000c000 {
26 #address-cells = <1>;
27 #size-cells = <1>;
26 pinctrl-names = "default"; 28 pinctrl-names = "default";
27 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; 29 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
28 status = "okay"; 30 status = "okay";
@@ -61,19 +63,40 @@
61 &mmc0_cd_cfg 63 &mmc0_cd_cfg
62 &mmc0_sck_cfg>; 64 &mmc0_sck_cfg>;
63 bus-width = <8>; 65 bus-width = <8>;
64 wp-gpios = <&gpio3 10 1>; 66 wp-gpios = <&gpio3 10 0>;
67 vmmc-supply = <&reg_vddio_sd0>;
65 status = "okay"; 68 status = "okay";
66 }; 69 };
67 70
71 ssp2: ssp@80014000 {
72 #address-cells = <1>;
73 #size-cells = <0>;
74 compatible = "fsl,imx28-spi";
75 pinctrl-names = "default";
76 pinctrl-0 = <&spi2_pins_a>;
77 status = "okay";
78
79 flash: m25p80@0 {
80 #address-cells = <1>;
81 #size-cells = <1>;
82 compatible = "m25p80";
83 spi-max-frequency = <40000000>;
84 reg = <0>;
85 };
86 };
87
68 pinctrl@80018000 { 88 pinctrl@80018000 {
69 pinctrl-names = "default"; 89 pinctrl-names = "default";
70 pinctrl-0 = <&hog_pins_a>; 90 pinctrl-0 = <&hog_pins_a>;
71 91
72 hog_pins_a: hog-gpios@0 { 92 hog_pins_a: hog@0 {
73 reg = <0>; 93 reg = <0>;
74 fsl,pinmux-ids = < 94 fsl,pinmux-ids = <
95 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
75 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ 96 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
76 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */ 97 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */
98 0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */
99 0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */
77 >; 100 >;
78 fsl,drive-strength = <0>; 101 fsl,drive-strength = <0>;
79 fsl,voltage = <1>; 102 fsl,voltage = <1>;
@@ -129,6 +152,7 @@
129 i2c0: i2c@80058000 { 152 i2c0: i2c@80058000 {
130 pinctrl-names = "default"; 153 pinctrl-names = "default";
131 pinctrl-0 = <&i2c0_pins_a>; 154 pinctrl-0 = <&i2c0_pins_a>;
155 clock-frequency = <400000>;
132 status = "okay"; 156 status = "okay";
133 157
134 sgtl5000: codec@0a { 158 sgtl5000: codec@0a {
@@ -151,32 +175,51 @@
151 }; 175 };
152 }; 176 };
153 177
178 lradc@80050000 {
179 status = "okay";
180 };
181
154 duart: serial@80074000 { 182 duart: serial@80074000 {
155 pinctrl-names = "default"; 183 pinctrl-names = "default";
156 pinctrl-0 = <&duart_pins_a>; 184 pinctrl-0 = <&duart_pins_a>;
157 status = "okay"; 185 status = "okay";
158 }; 186 };
159 187
160 auart0: serial@8006a000 { 188 usbphy0: usbphy@8007c000 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&auart0_2pins_a>;
163 status = "okay"; 189 status = "okay";
164 }; 190 };
165 191
166 auart3: serial@80070000 { 192 usbphy1: usbphy@8007e000 {
193 status = "okay";
194 };
195
196 auart0: serial@8006a000 {
167 pinctrl-names = "default"; 197 pinctrl-names = "default";
168 pinctrl-0 = <&auart3_pins_a>; 198 pinctrl-0 = <&auart0_2pins_a>;
169 status = "okay"; 199 status = "okay";
170 }; 200 };
171 }; 201 };
172 }; 202 };
173 203
174 ahb@80080000 { 204 ahb@80080000 {
205 usb0: usb@80080000 {
206 vbus-supply = <&reg_usb0_vbus>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&usbphy0_pins_a>;
209 status = "okay";
210 };
211
212 usb1: usb@80090000 {
213 vbus-supply = <&reg_usb1_vbus>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&usbphy1_pins_a>;
216 status = "okay";
217 };
218
175 mac0: ethernet@800f0000 { 219 mac0: ethernet@800f0000 {
176 phy-mode = "rmii"; 220 phy-mode = "rmii";
177 pinctrl-names = "default"; 221 pinctrl-names = "default";
178 pinctrl-0 = <&mac0_pins_a>; 222 pinctrl-0 = <&mac0_pins_a>;
179 phy-reset-gpios = <&gpio3 11 0>;
180 status = "okay"; 223 status = "okay";
181 }; 224 };
182 225
@@ -198,6 +241,30 @@
198 regulator-max-microvolt = <3300000>; 241 regulator-max-microvolt = <3300000>;
199 regulator-always-on; 242 regulator-always-on;
200 }; 243 };
244
245 reg_vddio_sd0: vddio-sd0 {
246 compatible = "regulator-fixed";
247 regulator-name = "vddio-sd0";
248 regulator-min-microvolt = <3300000>;
249 regulator-max-microvolt = <3300000>;
250 gpio = <&gpio3 28 0>;
251 };
252
253 reg_usb0_vbus: usb0_vbus {
254 compatible = "regulator-fixed";
255 regulator-name = "usb0_vbus";
256 regulator-min-microvolt = <5000000>;
257 regulator-max-microvolt = <5000000>;
258 gpio = <&gpio3 12 0>;
259 };
260
261 reg_usb1_vbus: usb1_vbus {
262 compatible = "regulator-fixed";
263 regulator-name = "usb1_vbus";
264 regulator-min-microvolt = <5000000>;
265 regulator-max-microvolt = <5000000>;
266 gpio = <&gpio3 13 0>;
267 };
201 }; 268 };
202 269
203 sound { 270 sound {
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index 62bf767409a6..37be532f0055 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -25,7 +25,7 @@
25 pinctrl-names = "default"; 25 pinctrl-names = "default";
26 pinctrl-0 = <&hog_pins_a>; 26 pinctrl-0 = <&hog_pins_a>;
27 27
28 hog_pins_a: hog-gpios@0 { 28 hog_pins_a: hog@0 {
29 reg = <0>; 29 reg = <0>;
30 fsl,pinmux-ids = < 30 fsl,pinmux-ids = <
31 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ 31 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */
@@ -34,6 +34,24 @@
34 fsl,voltage = <1>; 34 fsl,voltage = <1>;
35 fsl,pull-up = <0>; 35 fsl,pull-up = <0>;
36 }; 36 };
37
38 mac0_pins_gpio: mac0-gpio-mode@0 {
39 reg = <0>;
40 fsl,pinmux-ids = <
41 0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */
42 0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */
43 0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */
44 0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */
45 0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */
46 0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */
47 0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */
48 0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */
49 0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */
50 >;
51 fsl,drive-strength = <0>;
52 fsl,voltage = <1>;
53 fsl,pull-up = <0>;
54 };
37 }; 55 };
38 }; 56 };
39 57
@@ -72,8 +90,9 @@
72 ahb@80080000 { 90 ahb@80080000 {
73 mac0: ethernet@800f0000 { 91 mac0: ethernet@800f0000 {
74 phy-mode = "rmii"; 92 phy-mode = "rmii";
75 pinctrl-names = "default"; 93 pinctrl-names = "default", "gpio_mode";
76 pinctrl-0 = <&mac0_pins_a>; 94 pinctrl-0 = <&mac0_pins_a>;
95 pinctrl-1 = <&mac0_pins_gpio>;
77 status = "okay"; 96 status = "okay";
78 }; 97 };
79 }; 98 };
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 3fa6d190fab4..724147eab84b 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -27,6 +27,8 @@
27 serial2 = &auart2; 27 serial2 = &auart2;
28 serial3 = &auart3; 28 serial3 = &auart3;
29 serial4 = &auart4; 29 serial4 = &auart4;
30 ethernet0 = &mac0;
31 ethernet1 = &mac1;
30 }; 32 };
31 33
32 cpus { 34 cpus {
@@ -65,6 +67,7 @@
65 dma-apbh@80004000 { 67 dma-apbh@80004000 {
66 compatible = "fsl,imx28-dma-apbh"; 68 compatible = "fsl,imx28-dma-apbh";
67 reg = <0x80004000 0x2000>; 69 reg = <0x80004000 0x2000>;
70 clocks = <&clks 25>;
68 }; 71 };
69 72
70 perfmon@80006000 { 73 perfmon@80006000 {
@@ -81,34 +84,47 @@
81 reg-names = "gpmi-nand", "bch"; 84 reg-names = "gpmi-nand", "bch";
82 interrupts = <88>, <41>; 85 interrupts = <88>, <41>;
83 interrupt-names = "gpmi-dma", "bch"; 86 interrupt-names = "gpmi-dma", "bch";
87 clocks = <&clks 50>;
84 fsl,gpmi-dma-channel = <4>; 88 fsl,gpmi-dma-channel = <4>;
85 status = "disabled"; 89 status = "disabled";
86 }; 90 };
87 91
88 ssp0: ssp@80010000 { 92 ssp0: ssp@80010000 {
93 #address-cells = <1>;
94 #size-cells = <0>;
89 reg = <0x80010000 0x2000>; 95 reg = <0x80010000 0x2000>;
90 interrupts = <96 82>; 96 interrupts = <96 82>;
97 clocks = <&clks 46>;
91 fsl,ssp-dma-channel = <0>; 98 fsl,ssp-dma-channel = <0>;
92 status = "disabled"; 99 status = "disabled";
93 }; 100 };
94 101
95 ssp1: ssp@80012000 { 102 ssp1: ssp@80012000 {
103 #address-cells = <1>;
104 #size-cells = <0>;
96 reg = <0x80012000 0x2000>; 105 reg = <0x80012000 0x2000>;
97 interrupts = <97 83>; 106 interrupts = <97 83>;
107 clocks = <&clks 47>;
98 fsl,ssp-dma-channel = <1>; 108 fsl,ssp-dma-channel = <1>;
99 status = "disabled"; 109 status = "disabled";
100 }; 110 };
101 111
102 ssp2: ssp@80014000 { 112 ssp2: ssp@80014000 {
113 #address-cells = <1>;
114 #size-cells = <0>;
103 reg = <0x80014000 0x2000>; 115 reg = <0x80014000 0x2000>;
104 interrupts = <98 84>; 116 interrupts = <98 84>;
117 clocks = <&clks 48>;
105 fsl,ssp-dma-channel = <2>; 118 fsl,ssp-dma-channel = <2>;
106 status = "disabled"; 119 status = "disabled";
107 }; 120 };
108 121
109 ssp3: ssp@80016000 { 122 ssp3: ssp@80016000 {
123 #address-cells = <1>;
124 #size-cells = <0>;
110 reg = <0x80016000 0x2000>; 125 reg = <0x80016000 0x2000>;
111 interrupts = <99 85>; 126 interrupts = <99 85>;
127 clocks = <&clks 49>;
112 fsl,ssp-dma-channel = <3>; 128 fsl,ssp-dma-channel = <3>;
113 status = "disabled"; 129 status = "disabled";
114 }; 130 };
@@ -410,6 +426,28 @@
410 fsl,pull-up = <1>; 426 fsl,pull-up = <1>;
411 }; 427 };
412 428
429 i2c0_pins_b: i2c0@1 {
430 reg = <1>;
431 fsl,pinmux-ids = <
432 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
433 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
434 >;
435 fsl,drive-strength = <1>;
436 fsl,voltage = <1>;
437 fsl,pull-up = <1>;
438 };
439
440 i2c1_pins_a: i2c1@0 {
441 reg = <0>;
442 fsl,pinmux-ids = <
443 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
444 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
445 >;
446 fsl,drive-strength = <1>;
447 fsl,voltage = <1>;
448 fsl,pull-up = <1>;
449 };
450
413 saif0_pins_a: saif0@0 { 451 saif0_pins_a: saif0@0 {
414 reg = <0>; 452 reg = <0>;
415 fsl,pinmux-ids = < 453 fsl,pinmux-ids = <
@@ -453,6 +491,16 @@
453 fsl,pull-up = <0>; 491 fsl,pull-up = <0>;
454 }; 492 };
455 493
494 pwm4_pins_a: pwm4@0 {
495 reg = <0>;
496 fsl,pinmux-ids = <
497 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
498 >;
499 fsl,drive-strength = <0>;
500 fsl,voltage = <1>;
501 fsl,pull-up = <0>;
502 };
503
456 lcdif_24bit_pins_a: lcdif-24bit@0 { 504 lcdif_24bit_pins_a: lcdif-24bit@0 {
457 reg = <0>; 505 reg = <0>;
458 fsl,pinmux-ids = < 506 fsl,pinmux-ids = <
@@ -507,6 +555,49 @@
507 fsl,voltage = <1>; 555 fsl,voltage = <1>;
508 fsl,pull-up = <0>; 556 fsl,pull-up = <0>;
509 }; 557 };
558
559 spi2_pins_a: spi2@0 {
560 reg = <0>;
561 fsl,pinmux-ids = <
562 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
563 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
564 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
565 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
566 >;
567 fsl,drive-strength = <1>;
568 fsl,voltage = <1>;
569 fsl,pull-up = <1>;
570 };
571
572 usbphy0_pins_a: usbphy0@0 {
573 reg = <0>;
574 fsl,pinmux-ids = <
575 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
576 >;
577 fsl,drive-strength = <2>;
578 fsl,voltage = <1>;
579 fsl,pull-up = <0>;
580 };
581
582 usbphy0_pins_b: usbphy0@1 {
583 reg = <1>;
584 fsl,pinmux-ids = <
585 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
586 >;
587 fsl,drive-strength = <2>;
588 fsl,voltage = <1>;
589 fsl,pull-up = <0>;
590 };
591
592 usbphy1_pins_a: usbphy1@0 {
593 reg = <0>;
594 fsl,pinmux-ids = <
595 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
596 >;
597 fsl,drive-strength = <2>;
598 fsl,voltage = <1>;
599 fsl,pull-up = <0>;
600 };
510 }; 601 };
511 602
512 digctl@8001c000 { 603 digctl@8001c000 {
@@ -523,6 +614,7 @@
523 dma-apbx@80024000 { 614 dma-apbx@80024000 {
524 compatible = "fsl,imx28-dma-apbx"; 615 compatible = "fsl,imx28-dma-apbx";
525 reg = <0x80024000 0x2000>; 616 reg = <0x80024000 0x2000>;
617 clocks = <&clks 26>;
526 }; 618 };
527 619
528 dcp@80028000 { 620 dcp@80028000 {
@@ -551,6 +643,7 @@
551 compatible = "fsl,imx28-lcdif"; 643 compatible = "fsl,imx28-lcdif";
552 reg = <0x80030000 0x2000>; 644 reg = <0x80030000 0x2000>;
553 interrupts = <38 86>; 645 interrupts = <38 86>;
646 clocks = <&clks 55>;
554 status = "disabled"; 647 status = "disabled";
555 }; 648 };
556 649
@@ -558,6 +651,8 @@
558 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; 651 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
559 reg = <0x80032000 0x2000>; 652 reg = <0x80032000 0x2000>;
560 interrupts = <8>; 653 interrupts = <8>;
654 clocks = <&clks 58>, <&clks 58>;
655 clock-names = "ipg", "per";
561 status = "disabled"; 656 status = "disabled";
562 }; 657 };
563 658
@@ -565,6 +660,8 @@
565 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; 660 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
566 reg = <0x80034000 0x2000>; 661 reg = <0x80034000 0x2000>;
567 interrupts = <9>; 662 interrupts = <9>;
663 clocks = <&clks 59>, <&clks 59>;
664 clock-names = "ipg", "per";
568 status = "disabled"; 665 status = "disabled";
569 }; 666 };
570 667
@@ -611,15 +708,17 @@
611 reg = <0x80040000 0x40000>; 708 reg = <0x80040000 0x40000>;
612 ranges; 709 ranges;
613 710
614 clkctl@80040000 { 711 clks: clkctrl@80040000 {
712 compatible = "fsl,imx28-clkctrl";
615 reg = <0x80040000 0x2000>; 713 reg = <0x80040000 0x2000>;
616 status = "disabled"; 714 #clock-cells = <1>;
617 }; 715 };
618 716
619 saif0: saif@80042000 { 717 saif0: saif@80042000 {
620 compatible = "fsl,imx28-saif"; 718 compatible = "fsl,imx28-saif";
621 reg = <0x80042000 0x2000>; 719 reg = <0x80042000 0x2000>;
622 interrupts = <59 80>; 720 interrupts = <59 80>;
721 clocks = <&clks 53>;
623 fsl,saif-dma-channel = <4>; 722 fsl,saif-dma-channel = <4>;
624 status = "disabled"; 723 status = "disabled";
625 }; 724 };
@@ -633,12 +732,16 @@
633 compatible = "fsl,imx28-saif"; 732 compatible = "fsl,imx28-saif";
634 reg = <0x80046000 0x2000>; 733 reg = <0x80046000 0x2000>;
635 interrupts = <58 81>; 734 interrupts = <58 81>;
735 clocks = <&clks 54>;
636 fsl,saif-dma-channel = <5>; 736 fsl,saif-dma-channel = <5>;
637 status = "disabled"; 737 status = "disabled";
638 }; 738 };
639 739
640 lradc@80050000 { 740 lradc@80050000 {
741 compatible = "fsl,imx28-lradc";
641 reg = <0x80050000 0x2000>; 742 reg = <0x80050000 0x2000>;
743 interrupts = <10 14 15 16 17 18 19
744 20 21 22 23 24 25>;
642 status = "disabled"; 745 status = "disabled";
643 }; 746 };
644 747
@@ -677,6 +780,7 @@
677 pwm: pwm@80064000 { 780 pwm: pwm@80064000 {
678 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; 781 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
679 reg = <0x80064000 0x2000>; 782 reg = <0x80064000 0x2000>;
783 clocks = <&clks 44>;
680 #pwm-cells = <2>; 784 #pwm-cells = <2>;
681 fsl,pwm-number = <8>; 785 fsl,pwm-number = <8>;
682 status = "disabled"; 786 status = "disabled";
@@ -691,6 +795,7 @@
691 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 795 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
692 reg = <0x8006a000 0x2000>; 796 reg = <0x8006a000 0x2000>;
693 interrupts = <112 70 71>; 797 interrupts = <112 70 71>;
798 clocks = <&clks 45>;
694 status = "disabled"; 799 status = "disabled";
695 }; 800 };
696 801
@@ -698,6 +803,7 @@
698 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 803 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
699 reg = <0x8006c000 0x2000>; 804 reg = <0x8006c000 0x2000>;
700 interrupts = <113 72 73>; 805 interrupts = <113 72 73>;
806 clocks = <&clks 45>;
701 status = "disabled"; 807 status = "disabled";
702 }; 808 };
703 809
@@ -705,6 +811,7 @@
705 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 811 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
706 reg = <0x8006e000 0x2000>; 812 reg = <0x8006e000 0x2000>;
707 interrupts = <114 74 75>; 813 interrupts = <114 74 75>;
814 clocks = <&clks 45>;
708 status = "disabled"; 815 status = "disabled";
709 }; 816 };
710 817
@@ -712,6 +819,7 @@
712 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 819 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
713 reg = <0x80070000 0x2000>; 820 reg = <0x80070000 0x2000>;
714 interrupts = <115 76 77>; 821 interrupts = <115 76 77>;
822 clocks = <&clks 45>;
715 status = "disabled"; 823 status = "disabled";
716 }; 824 };
717 825
@@ -719,6 +827,7 @@
719 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 827 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
720 reg = <0x80072000 0x2000>; 828 reg = <0x80072000 0x2000>;
721 interrupts = <116 78 79>; 829 interrupts = <116 78 79>;
830 clocks = <&clks 45>;
722 status = "disabled"; 831 status = "disabled";
723 }; 832 };
724 833
@@ -726,18 +835,22 @@
726 compatible = "arm,pl011", "arm,primecell"; 835 compatible = "arm,pl011", "arm,primecell";
727 reg = <0x80074000 0x1000>; 836 reg = <0x80074000 0x1000>;
728 interrupts = <47>; 837 interrupts = <47>;
838 clocks = <&clks 45>, <&clks 26>;
839 clock-names = "uart", "apb_pclk";
729 status = "disabled"; 840 status = "disabled";
730 }; 841 };
731 842
732 usbphy0: usbphy@8007c000 { 843 usbphy0: usbphy@8007c000 {
733 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; 844 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
734 reg = <0x8007c000 0x2000>; 845 reg = <0x8007c000 0x2000>;
846 clocks = <&clks 62>;
735 status = "disabled"; 847 status = "disabled";
736 }; 848 };
737 849
738 usbphy1: usbphy@8007e000 { 850 usbphy1: usbphy@8007e000 {
739 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; 851 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
740 reg = <0x8007e000 0x2000>; 852 reg = <0x8007e000 0x2000>;
853 clocks = <&clks 63>;
741 status = "disabled"; 854 status = "disabled";
742 }; 855 };
743 }; 856 };
@@ -754,6 +867,7 @@
754 compatible = "fsl,imx28-usb", "fsl,imx27-usb"; 867 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
755 reg = <0x80080000 0x10000>; 868 reg = <0x80080000 0x10000>;
756 interrupts = <93>; 869 interrupts = <93>;
870 clocks = <&clks 60>;
757 fsl,usbphy = <&usbphy0>; 871 fsl,usbphy = <&usbphy0>;
758 status = "disabled"; 872 status = "disabled";
759 }; 873 };
@@ -762,6 +876,7 @@
762 compatible = "fsl,imx28-usb", "fsl,imx27-usb"; 876 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
763 reg = <0x80090000 0x10000>; 877 reg = <0x80090000 0x10000>;
764 interrupts = <92>; 878 interrupts = <92>;
879 clocks = <&clks 61>;
765 fsl,usbphy = <&usbphy1>; 880 fsl,usbphy = <&usbphy1>;
766 status = "disabled"; 881 status = "disabled";
767 }; 882 };
@@ -775,6 +890,8 @@
775 compatible = "fsl,imx28-fec"; 890 compatible = "fsl,imx28-fec";
776 reg = <0x800f0000 0x4000>; 891 reg = <0x800f0000 0x4000>;
777 interrupts = <101>; 892 interrupts = <101>;
893 clocks = <&clks 57>, <&clks 57>;
894 clock-names = "ipg", "ahb";
778 status = "disabled"; 895 status = "disabled";
779 }; 896 };
780 897
@@ -782,6 +899,8 @@
782 compatible = "fsl,imx28-fec"; 899 compatible = "fsl,imx28-fec";
783 reg = <0x800f4000 0x4000>; 900 reg = <0x800f4000 0x4000>;
784 interrupts = <102>; 901 interrupts = <102>;
902 clocks = <&clks 57>, <&clks 57>;
903 clock-names = "ipg", "ahb";
785 status = "disabled"; 904 status = "disabled";
786 }; 905 };
787 906
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 59d9789e5508..cbd2b1c7487b 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -25,23 +25,31 @@
25 aips@70000000 { /* aips-1 */ 25 aips@70000000 { /* aips-1 */
26 spba@70000000 { 26 spba@70000000 {
27 esdhc@70004000 { /* ESDHC1 */ 27 esdhc@70004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_1>;
28 fsl,cd-controller; 30 fsl,cd-controller;
29 fsl,wp-controller; 31 fsl,wp-controller;
30 status = "okay"; 32 status = "okay";
31 }; 33 };
32 34
33 esdhc@70008000 { /* ESDHC2 */ 35 esdhc@70008000 { /* ESDHC2 */
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_esdhc2_1>;
34 cd-gpios = <&gpio1 6 0>; 38 cd-gpios = <&gpio1 6 0>;
35 wp-gpios = <&gpio1 5 0>; 39 wp-gpios = <&gpio1 5 0>;
36 status = "okay"; 40 status = "okay";
37 }; 41 };
38 42
39 uart3: serial@7000c000 { 43 uart3: serial@7000c000 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_uart3_1>;
40 fsl,uart-has-rtscts; 46 fsl,uart-has-rtscts;
41 status = "okay"; 47 status = "okay";
42 }; 48 };
43 49
44 ecspi@70010000 { /* ECSPI1 */ 50 ecspi@70010000 { /* ECSPI1 */
51 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_ecspi1_1>;
45 fsl,spi-num-chipselects = <2>; 53 fsl,spi-num-chipselects = <2>;
46 cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; 54 cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
47 status = "okay"; 55 status = "okay";
@@ -169,31 +177,43 @@
169 }; 177 };
170 }; 178 };
171 179
172 wdog@73f98000 { /* WDOG1 */
173 status = "okay";
174 };
175
176 iomuxc@73fa8000 { 180 iomuxc@73fa8000 {
177 compatible = "fsl,imx51-iomuxc-babbage"; 181 pinctrl-names = "default";
178 reg = <0x73fa8000 0x4000>; 182 pinctrl-0 = <&pinctrl_hog>;
183
184 hog {
185 pinctrl_hog: hoggrp {
186 fsl,pins = <
187 694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
188 697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
189 737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
190 740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
191 121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
192 402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
193 405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
194 >;
195 };
196 };
179 }; 197 };
180 198
181 uart1: serial@73fbc000 { 199 uart1: serial@73fbc000 {
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_uart1_1>;
182 fsl,uart-has-rtscts; 202 fsl,uart-has-rtscts;
183 status = "okay"; 203 status = "okay";
184 }; 204 };
185 205
186 uart2: serial@73fc0000 { 206 uart2: serial@73fc0000 {
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_uart2_1>;
187 status = "okay"; 209 status = "okay";
188 }; 210 };
189 }; 211 };
190 212
191 aips@80000000 { /* aips-2 */ 213 aips@80000000 { /* aips-2 */
192 sdma@83fb0000 {
193 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
194 };
195
196 i2c@83fc4000 { /* I2C2 */ 214 i2c@83fc4000 { /* I2C2 */
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_i2c2_1>;
197 status = "okay"; 217 status = "okay";
198 218
199 sgtl5000: codec@0a { 219 sgtl5000: codec@0a {
@@ -206,10 +226,14 @@
206 }; 226 };
207 227
208 audmux@83fd0000 { 228 audmux@83fd0000 {
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_audmux_1>;
209 status = "okay"; 231 status = "okay";
210 }; 232 };
211 233
212 ethernet@83fec000 { 234 ethernet@83fec000 {
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_fec_1>;
213 phy-mode = "mii"; 237 phy-mode = "mii";
214 status = "okay"; 238 status = "okay";
215 }; 239 };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index aba28dc87fc8..2f71a91ca98e 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -130,6 +130,34 @@
130 }; 130 };
131 }; 131 };
132 132
133 usb@73f80000 {
134 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
135 reg = <0x73f80000 0x0200>;
136 interrupts = <18>;
137 status = "disabled";
138 };
139
140 usb@73f80200 {
141 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
142 reg = <0x73f80200 0x0200>;
143 interrupts = <14>;
144 status = "disabled";
145 };
146
147 usb@73f80400 {
148 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
149 reg = <0x73f80400 0x0200>;
150 interrupts = <16>;
151 status = "disabled";
152 };
153
154 usb@73f80600 {
155 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
156 reg = <0x73f80600 0x0200>;
157 interrupts = <17>;
158 status = "disabled";
159 };
160
133 gpio1: gpio@73f84000 { 161 gpio1: gpio@73f84000 {
134 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 162 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
135 reg = <0x73f84000 0x4000>; 163 reg = <0x73f84000 0x4000>;
@@ -174,7 +202,6 @@
174 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 202 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
175 reg = <0x73f98000 0x4000>; 203 reg = <0x73f98000 0x4000>;
176 interrupts = <58>; 204 interrupts = <58>;
177 status = "disabled";
178 }; 205 };
179 206
180 wdog@73f9c000 { /* WDOG2 */ 207 wdog@73f9c000 { /* WDOG2 */
@@ -184,6 +211,122 @@
184 status = "disabled"; 211 status = "disabled";
185 }; 212 };
186 213
214 iomuxc@73fa8000 {
215 compatible = "fsl,imx51-iomuxc";
216 reg = <0x73fa8000 0x4000>;
217
218 audmux {
219 pinctrl_audmux_1: audmuxgrp-1 {
220 fsl,pins = <
221 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
222 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
223 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
224 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
225 >;
226 };
227 };
228
229 fec {
230 pinctrl_fec_1: fecgrp-1 {
231 fsl,pins = <
232 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
233 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
234 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
235 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
236 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
237 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
238 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
239 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
240 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
241 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
242 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
243 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
244 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
245 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
246 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
247 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
248 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
249 >;
250 };
251 };
252
253 ecspi1 {
254 pinctrl_ecspi1_1: ecspi1grp-1 {
255 fsl,pins = <
256 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
257 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
258 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
259 >;
260 };
261 };
262
263 esdhc1 {
264 pinctrl_esdhc1_1: esdhc1grp-1 {
265 fsl,pins = <
266 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
267 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
268 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
269 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
270 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
271 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
272 >;
273 };
274 };
275
276 esdhc2 {
277 pinctrl_esdhc2_1: esdhc2grp-1 {
278 fsl,pins = <
279 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
280 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
281 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
282 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
283 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
284 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
285 >;
286 };
287 };
288
289 i2c2 {
290 pinctrl_i2c2_1: i2c2grp-1 {
291 fsl,pins = <
292 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
293 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
294 >;
295 };
296 };
297
298 uart1 {
299 pinctrl_uart1_1: uart1grp-1 {
300 fsl,pins = <
301 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
302 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
303 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
304 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
305 >;
306 };
307 };
308
309 uart2 {
310 pinctrl_uart2_1: uart2grp-1 {
311 fsl,pins = <
312 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
313 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
314 >;
315 };
316 };
317
318 uart3 {
319 pinctrl_uart3_1: uart3grp-1 {
320 fsl,pins = <
321 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
322 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
323 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
324 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
325 >;
326 };
327 };
328 };
329
187 uart1: serial@73fbc000 { 330 uart1: serial@73fbc000 {
188 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 331 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
189 reg = <0x73fbc000 0x4000>; 332 reg = <0x73fbc000 0x4000>;
@@ -219,6 +362,7 @@
219 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 362 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
220 reg = <0x83fb0000 0x4000>; 363 reg = <0x83fb0000 0x4000>;
221 interrupts = <6>; 364 interrupts = <6>;
365 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
222 }; 366 };
223 367
224 cspi@83fc0000 { 368 cspi@83fc0000 {
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index da895e93a999..4be76f223526 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -25,31 +25,66 @@
25 aips@50000000 { /* AIPS1 */ 25 aips@50000000 { /* AIPS1 */
26 spba@50000000 { 26 spba@50000000 {
27 esdhc@50004000 { /* ESDHC1 */ 27 esdhc@50004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_2>;
28 cd-gpios = <&gpio1 1 0>; 30 cd-gpios = <&gpio1 1 0>;
29 wp-gpios = <&gpio1 9 0>; 31 wp-gpios = <&gpio1 9 0>;
30 status = "okay"; 32 status = "okay";
31 }; 33 };
32 }; 34 };
33 35
34 wdog@53f98000 { /* WDOG1 */
35 status = "okay";
36 };
37
38 iomuxc@53fa8000 { 36 iomuxc@53fa8000 {
39 compatible = "fsl,imx53-iomuxc-ard"; 37 pinctrl-names = "default";
40 reg = <0x53fa8000 0x4000>; 38 pinctrl-0 = <&pinctrl_hog>;
39
40 hog {
41 pinctrl_hog: hoggrp {
42 fsl,pins = <
43 1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
44 1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
45 486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
46 739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
47 218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
48 226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
49 233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
50 241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
51 429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
52 435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
53 441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
54 448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
55 456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
56 464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
57 471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
58 477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
59 492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
60 500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
61 508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
62 516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
63 524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
64 532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
65 540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
66 548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
67 637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
68 642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
69 647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
70 652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
71 657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
72 662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
73 667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
74 611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
75 616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
76 607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
77 >;
78 };
79 };
41 }; 80 };
42 81
43 uart1: serial@53fbc000 { 82 uart1: serial@53fbc000 {
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_uart1_2>;
44 status = "okay"; 85 status = "okay";
45 }; 86 };
46 }; 87 };
47
48 aips@60000000 { /* AIPS2 */
49 sdma@63fb0000 {
50 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
51 };
52 };
53 }; 88 };
54 89
55 eim-cs1@f4000000 { 90 eim-cs1@f4000000 {
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 9c798034675e..a124d1e25258 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -25,12 +25,16 @@
25 aips@50000000 { /* AIPS1 */ 25 aips@50000000 { /* AIPS1 */
26 spba@50000000 { 26 spba@50000000 {
27 esdhc@50004000 { /* ESDHC1 */ 27 esdhc@50004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_1>;
28 cd-gpios = <&gpio3 13 0>; 30 cd-gpios = <&gpio3 13 0>;
29 wp-gpios = <&gpio3 14 0>; 31 wp-gpios = <&gpio3 14 0>;
30 status = "okay"; 32 status = "okay";
31 }; 33 };
32 34
33 ecspi@50010000 { /* ECSPI1 */ 35 ecspi@50010000 { /* ECSPI1 */
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_ecspi1_1>;
34 fsl,spi-num-chipselects = <2>; 38 fsl,spi-num-chipselects = <2>;
35 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; 39 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
36 status = "okay"; 40 status = "okay";
@@ -56,32 +60,45 @@
56 }; 60 };
57 61
58 esdhc@50020000 { /* ESDHC3 */ 62 esdhc@50020000 { /* ESDHC3 */
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_esdhc3_1>;
59 cd-gpios = <&gpio3 11 0>; 65 cd-gpios = <&gpio3 11 0>;
60 wp-gpios = <&gpio3 12 0>; 66 wp-gpios = <&gpio3 12 0>;
61 status = "okay"; 67 status = "okay";
62 }; 68 };
63 }; 69 };
64 70
65 wdog@53f98000 { /* WDOG1 */
66 status = "okay";
67 };
68
69 iomuxc@53fa8000 { 71 iomuxc@53fa8000 {
70 compatible = "fsl,imx53-iomuxc-evk"; 72 pinctrl-names = "default";
71 reg = <0x53fa8000 0x4000>; 73 pinctrl-0 = <&pinctrl_hog>;
74
75 hog {
76 pinctrl_hog: hoggrp {
77 fsl,pins = <
78 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
79 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
80 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
81 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
82 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
83 705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
84 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
85 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
86 >;
87 };
88 };
72 }; 89 };
73 90
74 uart1: serial@53fbc000 { 91 uart1: serial@53fbc000 {
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_uart1_1>;
75 status = "okay"; 94 status = "okay";
76 }; 95 };
77 }; 96 };
78 97
79 aips@60000000 { /* AIPS2 */ 98 aips@60000000 { /* AIPS2 */
80 sdma@63fb0000 {
81 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
82 };
83
84 i2c@63fc4000 { /* I2C2 */ 99 i2c@63fc4000 { /* I2C2 */
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_i2c2_1>;
85 status = "okay"; 102 status = "okay";
86 103
87 pmic: mc13892@08 { 104 pmic: mc13892@08 {
@@ -96,6 +113,8 @@
96 }; 113 };
97 114
98 ethernet@63fec000 { 115 ethernet@63fec000 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_fec_1>;
99 phy-mode = "rmii"; 118 phy-mode = "rmii";
100 phy-reset-gpios = <&gpio7 6 0>; 119 phy-reset-gpios = <&gpio7 6 0>;
101 status = "okay"; 120 status = "okay";
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 2d803a9a6949..08948af86d1a 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -25,6 +25,8 @@
25 aips@50000000 { /* AIPS1 */ 25 aips@50000000 { /* AIPS1 */
26 spba@50000000 { 26 spba@50000000 {
27 esdhc@50004000 { /* ESDHC1 */ 27 esdhc@50004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_1>;
28 cd-gpios = <&gpio3 13 0>; 30 cd-gpios = <&gpio3 13 0>;
29 status = "okay"; 31 status = "okay";
30 }; 32 };
@@ -35,32 +37,46 @@
35 }; 37 };
36 38
37 esdhc@50020000 { /* ESDHC3 */ 39 esdhc@50020000 { /* ESDHC3 */
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_esdhc3_1>;
38 cd-gpios = <&gpio3 11 0>; 42 cd-gpios = <&gpio3 11 0>;
39 wp-gpios = <&gpio3 12 0>; 43 wp-gpios = <&gpio3 12 0>;
40 status = "okay"; 44 status = "okay";
41 }; 45 };
42 }; 46 };
43 47
44 wdog@53f98000 { /* WDOG1 */
45 status = "okay";
46 };
47
48 iomuxc@53fa8000 { 48 iomuxc@53fa8000 {
49 compatible = "fsl,imx53-iomuxc-qsb"; 49 pinctrl-names = "default";
50 reg = <0x53fa8000 0x4000>; 50 pinctrl-0 = <&pinctrl_hog>;
51
52 hog {
53 pinctrl_hog: hoggrp {
54 fsl,pins = <
55 1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
56 1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
57 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
58 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
59 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
60 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
61 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
62 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
63 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
64 >;
65 };
66 };
51 }; 67 };
52 68
53 uart1: serial@53fbc000 { 69 uart1: serial@53fbc000 {
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_uart1_1>;
54 status = "okay"; 72 status = "okay";
55 }; 73 };
56 }; 74 };
57 75
58 aips@60000000 { /* AIPS2 */ 76 aips@60000000 { /* AIPS2 */
59 sdma@63fb0000 {
60 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
61 };
62
63 i2c@63fc4000 { /* I2C2 */ 77 i2c@63fc4000 { /* I2C2 */
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_i2c2_1>;
64 status = "okay"; 80 status = "okay";
65 81
66 sgtl5000: codec@0a { 82 sgtl5000: codec@0a {
@@ -72,6 +88,8 @@
72 }; 88 };
73 89
74 i2c@63fc8000 { /* I2C1 */ 90 i2c@63fc8000 { /* I2C1 */
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_i2c1_1>;
75 status = "okay"; 93 status = "okay";
76 94
77 accelerometer: mma8450@1c { 95 accelerometer: mma8450@1c {
@@ -158,10 +176,14 @@
158 }; 176 };
159 177
160 audmux@63fd0000 { 178 audmux@63fd0000 {
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_audmux_1>;
161 status = "okay"; 181 status = "okay";
162 }; 182 };
163 183
164 ethernet@63fec000 { 184 ethernet@63fec000 {
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_fec_1>;
165 phy-mode = "rmii"; 187 phy-mode = "rmii";
166 phy-reset-gpios = <&gpio7 6 0>; 188 phy-reset-gpios = <&gpio7 6 0>;
167 status = "okay"; 189 status = "okay";
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 08091029168e..06c68580c842 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -25,22 +25,30 @@
25 aips@50000000 { /* AIPS1 */ 25 aips@50000000 { /* AIPS1 */
26 spba@50000000 { 26 spba@50000000 {
27 esdhc@50004000 { /* ESDHC1 */ 27 esdhc@50004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_1>;
28 cd-gpios = <&gpio3 13 0>; 30 cd-gpios = <&gpio3 13 0>;
29 wp-gpios = <&gpio4 11 0>; 31 wp-gpios = <&gpio4 11 0>;
30 status = "okay"; 32 status = "okay";
31 }; 33 };
32 34
33 esdhc@50008000 { /* ESDHC2 */ 35 esdhc@50008000 { /* ESDHC2 */
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_esdhc2_1>;
34 non-removable; 38 non-removable;
35 status = "okay"; 39 status = "okay";
36 }; 40 };
37 41
38 uart3: serial@5000c000 { 42 uart3: serial@5000c000 {
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_uart3_1>;
39 fsl,uart-has-rtscts; 45 fsl,uart-has-rtscts;
40 status = "okay"; 46 status = "okay";
41 }; 47 };
42 48
43 ecspi@50010000 { /* ECSPI1 */ 49 ecspi@50010000 { /* ECSPI1 */
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_ecspi1_1>;
44 fsl,spi-num-chipselects = <2>; 52 fsl,spi-num-chipselects = <2>;
45 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; 53 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
46 status = "okay"; 54 status = "okay";
@@ -72,35 +80,49 @@
72 }; 80 };
73 81
74 esdhc@50020000 { /* ESDHC3 */ 82 esdhc@50020000 { /* ESDHC3 */
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_esdhc3_1>;
75 non-removable; 85 non-removable;
76 status = "okay"; 86 status = "okay";
77 }; 87 };
78 }; 88 };
79 89
80 wdog@53f98000 { /* WDOG1 */
81 status = "okay";
82 };
83
84 iomuxc@53fa8000 { 90 iomuxc@53fa8000 {
85 compatible = "fsl,imx53-iomuxc-smd"; 91 pinctrl-names = "default";
86 reg = <0x53fa8000 0x4000>; 92 pinctrl-0 = <&pinctrl_hog>;
93
94 hog {
95 pinctrl_hog: hoggrp {
96 fsl,pins = <
97 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
98 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
99 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
100 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
101 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
102 43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
103 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
104 >;
105 };
106 };
87 }; 107 };
88 108
89 uart1: serial@53fbc000 { 109 uart1: serial@53fbc000 {
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_uart1_1>;
90 status = "okay"; 112 status = "okay";
91 }; 113 };
92 114
93 uart2: serial@53fc0000 { 115 uart2: serial@53fc0000 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_uart2_1>;
94 status = "okay"; 118 status = "okay";
95 }; 119 };
96 }; 120 };
97 121
98 aips@60000000 { /* AIPS2 */ 122 aips@60000000 { /* AIPS2 */
99 sdma@63fb0000 {
100 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
101 };
102
103 i2c@63fc4000 { /* I2C2 */ 123 i2c@63fc4000 { /* I2C2 */
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_i2c2_1>;
104 status = "okay"; 126 status = "okay";
105 127
106 codec: sgtl5000@0a { 128 codec: sgtl5000@0a {
@@ -120,6 +142,8 @@
120 }; 142 };
121 143
122 i2c@63fc8000 { /* I2C1 */ 144 i2c@63fc8000 { /* I2C1 */
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_i2c1_1>;
123 status = "okay"; 147 status = "okay";
124 148
125 accelerometer: mma8450@1c { 149 accelerometer: mma8450@1c {
@@ -139,6 +163,8 @@
139 }; 163 };
140 164
141 ethernet@63fec000 { 165 ethernet@63fec000 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_fec_1>;
142 phy-mode = "rmii"; 168 phy-mode = "rmii";
143 phy-reset-gpios = <&gpio7 6 0>; 169 phy-reset-gpios = <&gpio7 6 0>;
144 status = "okay"; 170 status = "okay";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index cd37165edce5..221cf3321b0a 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -135,6 +135,34 @@
135 }; 135 };
136 }; 136 };
137 137
138 usb@53f80000 {
139 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
140 reg = <0x53f80000 0x0200>;
141 interrupts = <18>;
142 status = "disabled";
143 };
144
145 usb@53f80200 {
146 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
147 reg = <0x53f80200 0x0200>;
148 interrupts = <14>;
149 status = "disabled";
150 };
151
152 usb@53f80400 {
153 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
154 reg = <0x53f80400 0x0200>;
155 interrupts = <16>;
156 status = "disabled";
157 };
158
159 usb@53f80600 {
160 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
161 reg = <0x53f80600 0x0200>;
162 interrupts = <17>;
163 status = "disabled";
164 };
165
138 gpio1: gpio@53f84000 { 166 gpio1: gpio@53f84000 {
139 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 167 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
140 reg = <0x53f84000 0x4000>; 168 reg = <0x53f84000 0x4000>;
@@ -179,7 +207,6 @@
179 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 207 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
180 reg = <0x53f98000 0x4000>; 208 reg = <0x53f98000 0x4000>;
181 interrupts = <58>; 209 interrupts = <58>;
182 status = "disabled";
183 }; 210 };
184 211
185 wdog@53f9c000 { /* WDOG2 */ 212 wdog@53f9c000 { /* WDOG2 */
@@ -189,6 +216,161 @@
189 status = "disabled"; 216 status = "disabled";
190 }; 217 };
191 218
219 iomuxc@53fa8000 {
220 compatible = "fsl,imx53-iomuxc";
221 reg = <0x53fa8000 0x4000>;
222
223 audmux {
224 pinctrl_audmux_1: audmuxgrp-1 {
225 fsl,pins = <
226 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
227 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
228 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
229 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
230 >;
231 };
232 };
233
234 fec {
235 pinctrl_fec_1: fecgrp-1 {
236 fsl,pins = <
237 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
238 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
239 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
240 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
241 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
242 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
243 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
244 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
245 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
246 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
247 >;
248 };
249 };
250
251 ecspi1 {
252 pinctrl_ecspi1_1: ecspi1grp-1 {
253 fsl,pins = <
254 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
255 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
256 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
257 >;
258 };
259 };
260
261 esdhc1 {
262 pinctrl_esdhc1_1: esdhc1grp-1 {
263 fsl,pins = <
264 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
265 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
266 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
267 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
268 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
269 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
270 >;
271 };
272
273 pinctrl_esdhc1_2: esdhc1grp-2 {
274 fsl,pins = <
275 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
276 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
277 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
278 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
279 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
280 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
281 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
282 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
283 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
284 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
285 >;
286 };
287 };
288
289 esdhc2 {
290 pinctrl_esdhc2_1: esdhc2grp-1 {
291 fsl,pins = <
292 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
293 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
294 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
295 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
296 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
297 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
298 >;
299 };
300 };
301
302 esdhc3 {
303 pinctrl_esdhc3_1: esdhc3grp-1 {
304 fsl,pins = <
305 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
306 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
307 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
308 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
309 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
310 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
311 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
312 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
313 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
314 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
315 >;
316 };
317 };
318
319 i2c1 {
320 pinctrl_i2c1_1: i2c1grp-1 {
321 fsl,pins = <
322 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
323 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
324 >;
325 };
326 };
327
328 i2c2 {
329 pinctrl_i2c2_1: i2c2grp-1 {
330 fsl,pins = <
331 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
332 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
333 >;
334 };
335 };
336
337 uart1 {
338 pinctrl_uart1_1: uart1grp-1 {
339 fsl,pins = <
340 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
341 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
342 >;
343 };
344
345 pinctrl_uart1_2: uart1grp-2 {
346 fsl,pins = <
347 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
348 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
349 >;
350 };
351 };
352
353 uart2 {
354 pinctrl_uart2_1: uart2grp-1 {
355 fsl,pins = <
356 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
357 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
358 >;
359 };
360 };
361
362 uart3 {
363 pinctrl_uart3_1: uart3grp-1 {
364 fsl,pins = <
365 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
366 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
367 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
368 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
369 >;
370 };
371 };
372 };
373
192 uart1: serial@53fbc000 { 374 uart1: serial@53fbc000 {
193 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 375 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
194 reg = <0x53fbc000 0x4000>; 376 reg = <0x53fbc000 0x4000>;
@@ -203,6 +385,20 @@
203 status = "disabled"; 385 status = "disabled";
204 }; 386 };
205 387
388 can1: can@53fc8000 {
389 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
390 reg = <0x53fc8000 0x4000>;
391 interrupts = <82>;
392 status = "disabled";
393 };
394
395 can2: can@53fcc000 {
396 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
397 reg = <0x53fcc000 0x4000>;
398 interrupts = <83>;
399 status = "disabled";
400 };
401
206 gpio5: gpio@53fdc000 { 402 gpio5: gpio@53fdc000 {
207 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 403 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
208 reg = <0x53fdc000 0x4000>; 404 reg = <0x53fdc000 0x4000>;
@@ -277,6 +473,7 @@
277 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; 473 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
278 reg = <0x63fb0000 0x4000>; 474 reg = <0x63fb0000 0x4000>;
279 interrupts = <6>; 475 interrupts = <6>;
476 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
280 }; 477 };
281 478
282 cspi@63fc0000 { 479 cspi@63fc0000 {
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index d792581672cc..15df4c105e89 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -28,8 +28,27 @@
28 status = "disabled"; /* gpmi nand conflicts with SD */ 28 status = "disabled"; /* gpmi nand conflicts with SD */
29 }; 29 };
30 30
31 aips-bus@02000000 { /* AIPS1 */
32 iomuxc@020e0000 {
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_hog>;
35
36 hog {
37 pinctrl_hog: hoggrp {
38 fsl,pins = <
39 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
40 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
41 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
42 >;
43 };
44 };
45 };
46 };
47
31 aips-bus@02100000 { /* AIPS2 */ 48 aips-bus@02100000 { /* AIPS2 */
32 ethernet@02188000 { 49 ethernet@02188000 {
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_enet_2>;
33 phy-mode = "rgmii"; 52 phy-mode = "rgmii";
34 status = "okay"; 53 status = "okay";
35 }; 54 };
@@ -52,6 +71,8 @@
52 }; 71 };
53 72
54 uart4: serial@021f0000 { 73 uart4: serial@021f0000 {
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_uart4_1>;
55 status = "okay"; 76 status = "okay";
56 }; 77 };
57 }; 78 };
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 72f30f3e6171..d152328285a1 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -46,15 +46,20 @@
46 46
47 iomuxc@020e0000 { 47 iomuxc@020e0000 {
48 pinctrl-names = "default"; 48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_gpio_hog>; 49 pinctrl-0 = <&pinctrl_hog>;
50 50
51 gpios { 51 hog {
52 pinctrl_gpio_hog: gpiohog { 52 pinctrl_hog: hoggrp {
53 fsl,pins = < 53 fsl,pins = <
54 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ 54 1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
55 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ 55 1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
56 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */ 56 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
57 >; 57 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
58 152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
59 1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
60 1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
61 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
62 >;
58 }; 63 };
59 }; 64 };
60 }; 65 };
@@ -63,6 +68,9 @@
63 aips-bus@02100000 { /* AIPS2 */ 68 aips-bus@02100000 { /* AIPS2 */
64 usb@02184000 { /* USB OTG */ 69 usb@02184000 { /* USB OTG */
65 vbus-supply = <&reg_usb_otg_vbus>; 70 vbus-supply = <&reg_usb_otg_vbus>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_usbotg_1>;
73 disable-over-current;
66 status = "okay"; 74 status = "okay";
67 }; 75 };
68 76
@@ -71,12 +79,16 @@
71 }; 79 };
72 80
73 ethernet@02188000 { 81 ethernet@02188000 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_enet_1>;
74 phy-mode = "rgmii"; 84 phy-mode = "rgmii";
75 phy-reset-gpios = <&gpio3 23 0>; 85 phy-reset-gpios = <&gpio3 23 0>;
76 status = "okay"; 86 status = "okay";
77 }; 87 };
78 88
79 usdhc@02198000 { /* uSDHC3 */ 89 usdhc@02198000 { /* uSDHC3 */
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_usdhc3_2>;
80 cd-gpios = <&gpio7 0 0>; 92 cd-gpios = <&gpio7 0 0>;
81 wp-gpios = <&gpio7 1 0>; 93 wp-gpios = <&gpio7 1 0>;
82 vmmc-supply = <&reg_3p3v>; 94 vmmc-supply = <&reg_3p3v>;
@@ -84,6 +96,8 @@
84 }; 96 };
85 97
86 usdhc@0219c000 { /* uSDHC4 */ 98 usdhc@0219c000 { /* uSDHC4 */
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_usdhc4_2>;
87 cd-gpios = <&gpio2 6 0>; 101 cd-gpios = <&gpio2 6 0>;
88 wp-gpios = <&gpio2 7 0>; 102 wp-gpios = <&gpio2 7 0>;
89 vmmc-supply = <&reg_3p3v>; 103 vmmc-supply = <&reg_3p3v>;
@@ -99,7 +113,7 @@
99 uart2: serial@021e8000 { 113 uart2: serial@021e8000 {
100 status = "okay"; 114 status = "okay";
101 pinctrl-names = "default"; 115 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_serial2_1>; 116 pinctrl-0 = <&pinctrl_uart2_1>;
103 }; 117 };
104 118
105 i2c@021a0000 { /* I2C1 */ 119 i2c@021a0000 { /* I2C1 */
@@ -111,6 +125,7 @@
111 codec: sgtl5000@0a { 125 codec: sgtl5000@0a {
112 compatible = "fsl,sgtl5000"; 126 compatible = "fsl,sgtl5000";
113 reg = <0x0a>; 127 reg = <0x0a>;
128 clocks = <&clks 169>;
114 VDDA-supply = <&reg_2p5v>; 129 VDDA-supply = <&reg_2p5v>;
115 VDDIO-supply = <&reg_3p3v>; 130 VDDIO-supply = <&reg_3p3v>;
116 }; 131 };
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 07509a181178..e596c28c214d 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -22,28 +22,51 @@
22 }; 22 };
23 23
24 soc { 24 soc {
25
26 aips-bus@02000000 { /* AIPS1 */ 25 aips-bus@02000000 { /* AIPS1 */
27 spba-bus@02000000 { 26 spba-bus@02000000 {
28 uart1: serial@02020000 { 27 uart1: serial@02020000 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_uart1_1>;
29 status = "okay"; 30 status = "okay";
30 }; 31 };
31 }; 32 };
33
34 iomuxc@020e0000 {
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_hog>;
37
38 hog {
39 pinctrl_hog: hoggrp {
40 fsl,pins = <
41 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
42 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
43 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
44 1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
45 >;
46 };
47 };
48 };
32 }; 49 };
33 50
34 aips-bus@02100000 { /* AIPS2 */ 51 aips-bus@02100000 { /* AIPS2 */
35 ethernet@02188000 { 52 ethernet@02188000 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_enet_1>;
36 phy-mode = "rgmii"; 55 phy-mode = "rgmii";
37 status = "okay"; 56 status = "okay";
38 }; 57 };
39 58
40 usdhc@02194000 { /* uSDHC2 */ 59 usdhc@02194000 { /* uSDHC2 */
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_usdhc2_1>;
41 cd-gpios = <&gpio2 2 0>; 62 cd-gpios = <&gpio2 2 0>;
42 wp-gpios = <&gpio2 3 0>; 63 wp-gpios = <&gpio2 3 0>;
43 status = "okay"; 64 status = "okay";
44 }; 65 };
45 66
46 usdhc@02198000 { /* uSDHC3 */ 67 usdhc@02198000 { /* uSDHC3 */
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_usdhc3_1>;
47 cd-gpios = <&gpio2 0 0>; 70 cd-gpios = <&gpio2 0 0>;
48 wp-gpios = <&gpio2 1 0>; 71 wp-gpios = <&gpio2 1 0>;
49 status = "okay"; 72 status = "okay";
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index fd57079f71a9..35e5895ba3df 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -97,18 +97,23 @@
97 dma-apbh@00110000 { 97 dma-apbh@00110000 {
98 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 98 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
99 reg = <0x00110000 0x2000>; 99 reg = <0x00110000 0x2000>;
100 clocks = <&clks 106>;
100 }; 101 };
101 102
102 gpmi-nand@00112000 { 103 gpmi-nand@00112000 {
103 compatible = "fsl,imx6q-gpmi-nand"; 104 compatible = "fsl,imx6q-gpmi-nand";
104 #address-cells = <1>; 105 #address-cells = <1>;
105 #size-cells = <1>; 106 #size-cells = <1>;
106 reg = <0x00112000 0x2000>, <0x00114000 0x2000>; 107 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
107 reg-names = "gpmi-nand", "bch"; 108 reg-names = "gpmi-nand", "bch";
108 interrupts = <0 13 0x04>, <0 15 0x04>; 109 interrupts = <0 13 0x04>, <0 15 0x04>;
109 interrupt-names = "gpmi-dma", "bch"; 110 interrupt-names = "gpmi-dma", "bch";
110 fsl,gpmi-dma-channel = <0>; 111 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
111 status = "disabled"; 112 <&clks 150>, <&clks 149>;
113 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
114 "gpmi_bch_apb", "per1_bch";
115 fsl,gpmi-dma-channel = <0>;
116 status = "disabled";
112 }; 117 };
113 118
114 timer@00a00600 { 119 timer@00a00600 {
@@ -150,6 +155,8 @@
150 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 155 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
151 reg = <0x02008000 0x4000>; 156 reg = <0x02008000 0x4000>;
152 interrupts = <0 31 0x04>; 157 interrupts = <0 31 0x04>;
158 clocks = <&clks 112>, <&clks 112>;
159 clock-names = "ipg", "per";
153 status = "disabled"; 160 status = "disabled";
154 }; 161 };
155 162
@@ -159,6 +166,8 @@
159 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 166 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
160 reg = <0x0200c000 0x4000>; 167 reg = <0x0200c000 0x4000>;
161 interrupts = <0 32 0x04>; 168 interrupts = <0 32 0x04>;
169 clocks = <&clks 113>, <&clks 113>;
170 clock-names = "ipg", "per";
162 status = "disabled"; 171 status = "disabled";
163 }; 172 };
164 173
@@ -168,6 +177,8 @@
168 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
169 reg = <0x02010000 0x4000>; 178 reg = <0x02010000 0x4000>;
170 interrupts = <0 33 0x04>; 179 interrupts = <0 33 0x04>;
180 clocks = <&clks 114>, <&clks 114>;
181 clock-names = "ipg", "per";
171 status = "disabled"; 182 status = "disabled";
172 }; 183 };
173 184
@@ -177,6 +188,8 @@
177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 188 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
178 reg = <0x02014000 0x4000>; 189 reg = <0x02014000 0x4000>;
179 interrupts = <0 34 0x04>; 190 interrupts = <0 34 0x04>;
191 clocks = <&clks 115>, <&clks 115>;
192 clock-names = "ipg", "per";
180 status = "disabled"; 193 status = "disabled";
181 }; 194 };
182 195
@@ -186,6 +199,8 @@
186 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 199 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
187 reg = <0x02018000 0x4000>; 200 reg = <0x02018000 0x4000>;
188 interrupts = <0 35 0x04>; 201 interrupts = <0 35 0x04>;
202 clocks = <&clks 116>, <&clks 116>;
203 clock-names = "ipg", "per";
189 status = "disabled"; 204 status = "disabled";
190 }; 205 };
191 206
@@ -193,6 +208,8 @@
193 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 208 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
194 reg = <0x02020000 0x4000>; 209 reg = <0x02020000 0x4000>;
195 interrupts = <0 26 0x04>; 210 interrupts = <0 26 0x04>;
211 clocks = <&clks 160>, <&clks 161>;
212 clock-names = "ipg", "per";
196 status = "disabled"; 213 status = "disabled";
197 }; 214 };
198 215
@@ -205,6 +222,7 @@
205 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; 222 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
206 reg = <0x02028000 0x4000>; 223 reg = <0x02028000 0x4000>;
207 interrupts = <0 46 0x04>; 224 interrupts = <0 46 0x04>;
225 clocks = <&clks 178>;
208 fsl,fifo-depth = <15>; 226 fsl,fifo-depth = <15>;
209 fsl,ssi-dma-events = <38 37>; 227 fsl,ssi-dma-events = <38 37>;
210 status = "disabled"; 228 status = "disabled";
@@ -214,6 +232,7 @@
214 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; 232 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
215 reg = <0x0202c000 0x4000>; 233 reg = <0x0202c000 0x4000>;
216 interrupts = <0 47 0x04>; 234 interrupts = <0 47 0x04>;
235 clocks = <&clks 179>;
217 fsl,fifo-depth = <15>; 236 fsl,fifo-depth = <15>;
218 fsl,ssi-dma-events = <42 41>; 237 fsl,ssi-dma-events = <42 41>;
219 status = "disabled"; 238 status = "disabled";
@@ -223,6 +242,7 @@
223 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; 242 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
224 reg = <0x02030000 0x4000>; 243 reg = <0x02030000 0x4000>;
225 interrupts = <0 48 0x04>; 244 interrupts = <0 48 0x04>;
245 clocks = <&clks 180>;
226 fsl,fifo-depth = <15>; 246 fsl,fifo-depth = <15>;
227 fsl,ssi-dma-events = <46 45>; 247 fsl,ssi-dma-events = <46 45>;
228 status = "disabled"; 248 status = "disabled";
@@ -362,20 +382,22 @@
362 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 382 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
363 reg = <0x020bc000 0x4000>; 383 reg = <0x020bc000 0x4000>;
364 interrupts = <0 80 0x04>; 384 interrupts = <0 80 0x04>;
365 status = "disabled"; 385 clocks = <&clks 0>;
366 }; 386 };
367 387
368 wdog@020c0000 { /* WDOG2 */ 388 wdog@020c0000 { /* WDOG2 */
369 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 389 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
370 reg = <0x020c0000 0x4000>; 390 reg = <0x020c0000 0x4000>;
371 interrupts = <0 81 0x04>; 391 interrupts = <0 81 0x04>;
392 clocks = <&clks 0>;
372 status = "disabled"; 393 status = "disabled";
373 }; 394 };
374 395
375 ccm@020c4000 { 396 clks: ccm@020c4000 {
376 compatible = "fsl,imx6q-ccm"; 397 compatible = "fsl,imx6q-ccm";
377 reg = <0x020c4000 0x4000>; 398 reg = <0x020c4000 0x4000>;
378 interrupts = <0 87 0x04 0 88 0x04>; 399 interrupts = <0 87 0x04 0 88 0x04>;
400 #clock-cells = <1>;
379 }; 401 };
380 402
381 anatop@020c8000 { 403 anatop@020c8000 {
@@ -472,12 +494,14 @@
472 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 494 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
473 reg = <0x020c9000 0x1000>; 495 reg = <0x020c9000 0x1000>;
474 interrupts = <0 44 0x04>; 496 interrupts = <0 44 0x04>;
497 clocks = <&clks 182>;
475 }; 498 };
476 499
477 usbphy2: usbphy@020ca000 { 500 usbphy2: usbphy@020ca000 {
478 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 501 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
479 reg = <0x020ca000 0x1000>; 502 reg = <0x020ca000 0x1000>;
480 interrupts = <0 45 0x04>; 503 interrupts = <0 45 0x04>;
504 clocks = <&clks 183>;
481 }; 505 };
482 506
483 snvs@020cc000 { 507 snvs@020cc000 {
@@ -514,86 +538,207 @@
514 /* shared pinctrl settings */ 538 /* shared pinctrl settings */
515 audmux { 539 audmux {
516 pinctrl_audmux_1: audmux-1 { 540 pinctrl_audmux_1: audmux-1 {
517 fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ 541 fsl,pins = <
518 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ 542 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
519 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ 543 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
520 3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ 544 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
545 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
546 >;
547 };
548 };
549
550 ecspi1 {
551 pinctrl_ecspi1_1: ecspi1grp-1 {
552 fsl,pins = <
553 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
554 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
555 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
556 >;
557 };
558 };
559
560 enet {
561 pinctrl_enet_1: enetgrp-1 {
562 fsl,pins = <
563 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
564 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
565 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
566 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
567 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
568 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
569 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
570 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
571 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
572 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
573 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
574 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
575 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
576 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
577 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
578 >;
579 };
580
581 pinctrl_enet_2: enetgrp-2 {
582 fsl,pins = <
583 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
584 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
585 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
586 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
587 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
588 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
589 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
590 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
591 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
592 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
593 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
594 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
595 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
596 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
597 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
598 >;
521 }; 599 };
522 }; 600 };
523 601
524 gpmi-nand { 602 gpmi-nand {
525 pinctrl_gpmi_nand_1: gpmi-nand-1 { 603 pinctrl_gpmi_nand_1: gpmi-nand-1 {
526 fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ 604 fsl,pins = <
527 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ 605 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
528 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ 606 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
529 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ 607 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
530 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ 608 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
531 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ 609 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
532 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ 610 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
533 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ 611 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
534 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ 612 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
535 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ 613 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
536 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ 614 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
537 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ 615 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
538 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ 616 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
539 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ 617 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
540 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ 618 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
541 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ 619 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
542 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ 620 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
543 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ 621 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
544 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ 622 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
623 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
624 >;
545 }; 625 };
546 }; 626 };
547 627
548 i2c1 { 628 i2c1 {
549 pinctrl_i2c1_1: i2c1grp-1 { 629 pinctrl_i2c1_1: i2c1grp-1 {
550 fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ 630 fsl,pins = <
551 196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */ 631 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
632 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
633 >;
634 };
635 };
636
637 uart1 {
638 pinctrl_uart1_1: uart1grp-1 {
639 fsl,pins = <
640 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
641 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
642 >;
552 }; 643 };
553 }; 644 };
554 645
555 serial2 { 646 uart2 {
556 pinctrl_serial2_1: serial2grp-1 { 647 pinctrl_uart2_1: uart2grp-1 {
557 fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ 648 fsl,pins = <
558 191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */ 649 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
650 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
651 >;
652 };
653 };
654
655 uart4 {
656 pinctrl_uart4_1: uart4grp-1 {
657 fsl,pins = <
658 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
659 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
660 >;
661 };
662 };
663
664 usbotg {
665 pinctrl_usbotg_1: usbotggrp-1 {
666 fsl,pins = <
667 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
668 >;
669 };
670 };
671
672 usdhc2 {
673 pinctrl_usdhc2_1: usdhc2grp-1 {
674 fsl,pins = <
675 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
676 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
677 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
678 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
679 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
680 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
681 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
682 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
683 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
684 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
685 >;
559 }; 686 };
560 }; 687 };
561 688
562 usdhc3 { 689 usdhc3 {
563 pinctrl_usdhc3_1: usdhc3grp-1 { 690 pinctrl_usdhc3_1: usdhc3grp-1 {
564 fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ 691 fsl,pins = <
565 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ 692 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
566 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ 693 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
567 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ 694 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
568 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ 695 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
569 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ 696 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
570 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ 697 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
571 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ 698 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
572 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ 699 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
573 1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ 700 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
701 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
702 >;
703 };
704
705 pinctrl_usdhc3_2: usdhc3grp-2 {
706 fsl,pins = <
707 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
708 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
709 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
710 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
711 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
712 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
713 >;
574 }; 714 };
575 }; 715 };
576 716
577 usdhc4 { 717 usdhc4 {
578 pinctrl_usdhc4_1: usdhc4grp-1 { 718 pinctrl_usdhc4_1: usdhc4grp-1 {
579 fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ 719 fsl,pins = <
580 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ 720 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
581 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ 721 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
582 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ 722 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
583 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ 723 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
584 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ 724 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
585 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ 725 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
586 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ 726 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
587 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ 727 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
588 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ 728 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
729 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
730 >;
589 }; 731 };
590 };
591 732
592 ecspi1 { 733 pinctrl_usdhc4_2: usdhc4grp-2 {
593 pinctrl_ecspi1_1: ecspi1grp-1 { 734 fsl,pins = <
594 fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ 735 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
595 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ 736 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
596 94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ 737 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
738 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
739 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
740 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
741 >;
597 }; 742 };
598 }; 743 };
599 }; 744 };
@@ -612,6 +757,9 @@
612 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; 757 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
613 reg = <0x020ec000 0x4000>; 758 reg = <0x020ec000 0x4000>;
614 interrupts = <0 2 0x04>; 759 interrupts = <0 2 0x04>;
760 clocks = <&clks 155>, <&clks 155>;
761 clock-names = "ipg", "ahb";
762 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
615 }; 763 };
616 }; 764 };
617 765
@@ -635,7 +783,9 @@
635 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 783 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
636 reg = <0x02184000 0x200>; 784 reg = <0x02184000 0x200>;
637 interrupts = <0 43 0x04>; 785 interrupts = <0 43 0x04>;
786 clocks = <&clks 162>;
638 fsl,usbphy = <&usbphy1>; 787 fsl,usbphy = <&usbphy1>;
788 fsl,usbmisc = <&usbmisc 0>;
639 status = "disabled"; 789 status = "disabled";
640 }; 790 };
641 791
@@ -643,7 +793,9 @@
643 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 793 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
644 reg = <0x02184200 0x200>; 794 reg = <0x02184200 0x200>;
645 interrupts = <0 40 0x04>; 795 interrupts = <0 40 0x04>;
796 clocks = <&clks 162>;
646 fsl,usbphy = <&usbphy2>; 797 fsl,usbphy = <&usbphy2>;
798 fsl,usbmisc = <&usbmisc 1>;
647 status = "disabled"; 799 status = "disabled";
648 }; 800 };
649 801
@@ -651,6 +803,8 @@
651 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 803 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
652 reg = <0x02184400 0x200>; 804 reg = <0x02184400 0x200>;
653 interrupts = <0 41 0x04>; 805 interrupts = <0 41 0x04>;
806 clocks = <&clks 162>;
807 fsl,usbmisc = <&usbmisc 2>;
654 status = "disabled"; 808 status = "disabled";
655 }; 809 };
656 810
@@ -658,13 +812,24 @@
658 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 812 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
659 reg = <0x02184600 0x200>; 813 reg = <0x02184600 0x200>;
660 interrupts = <0 42 0x04>; 814 interrupts = <0 42 0x04>;
815 clocks = <&clks 162>;
816 fsl,usbmisc = <&usbmisc 3>;
661 status = "disabled"; 817 status = "disabled";
662 }; 818 };
663 819
820 usbmisc: usbmisc@02184800 {
821 #index-cells = <1>;
822 compatible = "fsl,imx6q-usbmisc";
823 reg = <0x02184800 0x200>;
824 clocks = <&clks 162>;
825 };
826
664 ethernet@02188000 { 827 ethernet@02188000 {
665 compatible = "fsl,imx6q-fec"; 828 compatible = "fsl,imx6q-fec";
666 reg = <0x02188000 0x4000>; 829 reg = <0x02188000 0x4000>;
667 interrupts = <0 118 0x04 0 119 0x04>; 830 interrupts = <0 118 0x04 0 119 0x04>;
831 clocks = <&clks 117>, <&clks 117>;
832 clock-names = "ipg", "ahb";
668 status = "disabled"; 833 status = "disabled";
669 }; 834 };
670 835
@@ -677,6 +842,8 @@
677 compatible = "fsl,imx6q-usdhc"; 842 compatible = "fsl,imx6q-usdhc";
678 reg = <0x02190000 0x4000>; 843 reg = <0x02190000 0x4000>;
679 interrupts = <0 22 0x04>; 844 interrupts = <0 22 0x04>;
845 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
846 clock-names = "ipg", "ahb", "per";
680 status = "disabled"; 847 status = "disabled";
681 }; 848 };
682 849
@@ -684,6 +851,8 @@
684 compatible = "fsl,imx6q-usdhc"; 851 compatible = "fsl,imx6q-usdhc";
685 reg = <0x02194000 0x4000>; 852 reg = <0x02194000 0x4000>;
686 interrupts = <0 23 0x04>; 853 interrupts = <0 23 0x04>;
854 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
855 clock-names = "ipg", "ahb", "per";
687 status = "disabled"; 856 status = "disabled";
688 }; 857 };
689 858
@@ -691,6 +860,8 @@
691 compatible = "fsl,imx6q-usdhc"; 860 compatible = "fsl,imx6q-usdhc";
692 reg = <0x02198000 0x4000>; 861 reg = <0x02198000 0x4000>;
693 interrupts = <0 24 0x04>; 862 interrupts = <0 24 0x04>;
863 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
864 clock-names = "ipg", "ahb", "per";
694 status = "disabled"; 865 status = "disabled";
695 }; 866 };
696 867
@@ -698,6 +869,8 @@
698 compatible = "fsl,imx6q-usdhc"; 869 compatible = "fsl,imx6q-usdhc";
699 reg = <0x0219c000 0x4000>; 870 reg = <0x0219c000 0x4000>;
700 interrupts = <0 25 0x04>; 871 interrupts = <0 25 0x04>;
872 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
873 clock-names = "ipg", "ahb", "per";
701 status = "disabled"; 874 status = "disabled";
702 }; 875 };
703 876
@@ -707,6 +880,7 @@
707 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; 880 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
708 reg = <0x021a0000 0x4000>; 881 reg = <0x021a0000 0x4000>;
709 interrupts = <0 36 0x04>; 882 interrupts = <0 36 0x04>;
883 clocks = <&clks 125>;
710 status = "disabled"; 884 status = "disabled";
711 }; 885 };
712 886
@@ -716,6 +890,7 @@
716 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; 890 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
717 reg = <0x021a4000 0x4000>; 891 reg = <0x021a4000 0x4000>;
718 interrupts = <0 37 0x04>; 892 interrupts = <0 37 0x04>;
893 clocks = <&clks 126>;
719 status = "disabled"; 894 status = "disabled";
720 }; 895 };
721 896
@@ -725,6 +900,7 @@
725 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; 900 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
726 reg = <0x021a8000 0x4000>; 901 reg = <0x021a8000 0x4000>;
727 interrupts = <0 38 0x04>; 902 interrupts = <0 38 0x04>;
903 clocks = <&clks 127>;
728 status = "disabled"; 904 status = "disabled";
729 }; 905 };
730 906
@@ -788,6 +964,8 @@
788 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 964 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
789 reg = <0x021e8000 0x4000>; 965 reg = <0x021e8000 0x4000>;
790 interrupts = <0 27 0x04>; 966 interrupts = <0 27 0x04>;
967 clocks = <&clks 160>, <&clks 161>;
968 clock-names = "ipg", "per";
791 status = "disabled"; 969 status = "disabled";
792 }; 970 };
793 971
@@ -795,6 +973,8 @@
795 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 973 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
796 reg = <0x021ec000 0x4000>; 974 reg = <0x021ec000 0x4000>;
797 interrupts = <0 28 0x04>; 975 interrupts = <0 28 0x04>;
976 clocks = <&clks 160>, <&clks 161>;
977 clock-names = "ipg", "per";
798 status = "disabled"; 978 status = "disabled";
799 }; 979 };
800 980
@@ -802,6 +982,8 @@
802 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 982 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
803 reg = <0x021f0000 0x4000>; 983 reg = <0x021f0000 0x4000>;
804 interrupts = <0 29 0x04>; 984 interrupts = <0 29 0x04>;
985 clocks = <&clks 160>, <&clks 161>;
986 clock-names = "ipg", "per";
805 status = "disabled"; 987 status = "disabled";
806 }; 988 };
807 989
@@ -809,6 +991,8 @@
809 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 991 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
810 reg = <0x021f4000 0x4000>; 992 reg = <0x021f4000 0x4000>;
811 interrupts = <0 30 0x04>; 993 interrupts = <0 30 0x04>;
994 clocks = <&clks 160>, <&clks 161>;
995 clock-names = "ipg", "per";
812 status = "disabled"; 996 status = "disabled";
813 }; 997 };
814 }; 998 };
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
index 80f74e256408..0514fb41627e 100644
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -26,6 +26,11 @@
26 interrupt-parent = <&intc>; 26 interrupt-parent = <&intc>;
27 ranges; 27 ranges;
28 28
29 L2: l2-cache {
30 compatible = "marvell,tauros2-cache";
31 marvell,tauros2-cache-features = <0x3>;
32 };
33
29 axi@d4200000 { /* AXI */ 34 axi@d4200000 { /* AXI */
30 compatible = "mrvl,axi-bus", "simple-bus"; 35 compatible = "mrvl,axi-bus", "simple-bus";
31 #address-cells = <1>; 36 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index 45bc4bb04e57..31f2157cd7d7 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -7,7 +7,7 @@
7 compatible = "qcom,msm8660-surf", "qcom,msm8660"; 7 compatible = "qcom,msm8660-surf", "qcom,msm8660";
8 interrupt-parent = <&intc>; 8 interrupt-parent = <&intc>;
9 9
10 intc: interrupt-controller@02080000 { 10 intc: interrupt-controller@2080000 {
11 compatible = "qcom,msm-8660-qgic"; 11 compatible = "qcom,msm-8660-qgic";
12 interrupt-controller; 12 interrupt-controller;
13 #interrupt-cells = <3>; 13 #interrupt-cells = <3>;
@@ -15,6 +15,23 @@
15 < 0x02081000 0x1000 >; 15 < 0x02081000 0x1000 >;
16 }; 16 };
17 17
18 timer@2000004 {
19 compatible = "qcom,msm-gpt", "qcom,msm-timer";
20 interrupts = <1 1 0x301>;
21 reg = <0x02000004 0x10>;
22 clock-frequency = <32768>;
23 cpu-offset = <0x40000>;
24 };
25
26 timer@2000024 {
27 compatible = "qcom,msm-dgt", "qcom,msm-timer";
28 interrupts = <1 0 0x301>;
29 reg = <0x02000024 0x10>,
30 <0x02000034 0x4>;
31 clock-frequency = <6750000>;
32 cpu-offset = <0x40000>;
33 };
34
18 serial@19c400000 { 35 serial@19c400000 {
19 compatible = "qcom,msm-hsuart", "qcom,msm-uart"; 36 compatible = "qcom,msm-hsuart", "qcom,msm-uart";
20 reg = <0x19c40000 0x1000>, 37 reg = <0x19c40000 0x1000>,
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts
new file mode 100644
index 000000000000..9e621b5ad3dd
--- /dev/null
+++ b/arch/arm/boot/dts/msm8960-cdp.dts
@@ -0,0 +1,41 @@
1/dts-v1/;
2
3/include/ "skeleton.dtsi"
4
5/ {
6 model = "Qualcomm MSM8960 CDP";
7 compatible = "qcom,msm8960-cdp", "qcom,msm8960";
8 interrupt-parent = <&intc>;
9
10 intc: interrupt-controller@2000000 {
11 compatible = "qcom,msm-qgic2";
12 interrupt-controller;
13 #interrupt-cells = <3>;
14 reg = < 0x02000000 0x1000 >,
15 < 0x02002000 0x1000 >;
16 };
17
18 timer@200a004 {
19 compatible = "qcom,msm-gpt", "qcom,msm-timer";
20 interrupts = <1 2 0x301>;
21 reg = <0x0200a004 0x10>;
22 clock-frequency = <32768>;
23 cpu-offset = <0x80000>;
24 };
25
26 timer@200a024 {
27 compatible = "qcom,msm-dgt", "qcom,msm-timer";
28 interrupts = <1 1 0x301>;
29 reg = <0x0200a024 0x10>,
30 <0x0200a034 0x4>;
31 clock-frequency = <6750000>;
32 cpu-offset = <0x80000>;
33 };
34
35 serial@19c400000 {
36 compatible = "qcom,msm-hsuart", "qcom,msm-uart";
37 reg = <0x16440000 0x1000>,
38 <0x16400000 0x1000>;
39 interrupts = <0 154 0x0>;
40 };
41};
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 25b50b759dec..77b84e17c477 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -7,7 +7,7 @@
7 */ 7 */
8/dts-v1/; 8/dts-v1/;
9 9
10/include/ "omap2.dtsi" 10/include/ "omap2420.dtsi"
11 11
12/ { 12/ {
13 model = "TI OMAP2420 H4 board"; 13 model = "TI OMAP2420 H4 board";
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
new file mode 100644
index 000000000000..bfd76b4a0ddc
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -0,0 +1,48 @@
1/*
2 * Device Tree Source for OMAP2420 SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "omap2.dtsi"
12
13/ {
14 compatible = "ti,omap2420", "ti,omap2";
15
16 ocp {
17 omap2420_pmx: pinmux@48000030 {
18 compatible = "ti,omap2420-padconf", "pinctrl-single";
19 reg = <0x48000030 0x0113>;
20 #address-cells = <1>;
21 #size-cells = <0>;
22 pinctrl-single,register-width = <8>;
23 pinctrl-single,function-mask = <0x3f>;
24 };
25
26 mcbsp1: mcbsp@48074000 {
27 compatible = "ti,omap2420-mcbsp";
28 reg = <0x48074000 0xff>;
29 reg-names = "mpu";
30 interrupts = <59>, /* TX interrupt */
31 <60>; /* RX interrupt */
32 interrupt-names = "tx", "rx";
33 interrupt-parent = <&intc>;
34 ti,hwmods = "mcbsp1";
35 };
36
37 mcbsp2: mcbsp@48076000 {
38 compatible = "ti,omap2420-mcbsp";
39 reg = <0x48076000 0xff>;
40 reg-names = "mpu";
41 interrupts = <62>, /* TX interrupt */
42 <63>; /* RX interrupt */
43 interrupt-names = "tx", "rx";
44 interrupt-parent = <&intc>;
45 ti,hwmods = "mcbsp2";
46 };
47 };
48};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
new file mode 100644
index 000000000000..4565d9750f4d
--- /dev/null
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -0,0 +1,92 @@
1/*
2 * Device Tree Source for OMAP243x SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "omap2.dtsi"
12
13/ {
14 compatible = "ti,omap2430", "ti,omap2";
15
16 ocp {
17 omap2430_pmx: pinmux@49002030 {
18 compatible = "ti,omap2430-padconf", "pinctrl-single";
19 reg = <0x49002030 0x0154>;
20 #address-cells = <1>;
21 #size-cells = <0>;
22 pinctrl-single,register-width = <8>;
23 pinctrl-single,function-mask = <0x3f>;
24 };
25
26 mcbsp1: mcbsp@48074000 {
27 compatible = "ti,omap2430-mcbsp";
28 reg = <0x48074000 0xff>;
29 reg-names = "mpu";
30 interrupts = <64>, /* OCP compliant interrupt */
31 <59>, /* TX interrupt */
32 <60>, /* RX interrupt */
33 <61>; /* RX overflow interrupt */
34 interrupt-names = "common", "tx", "rx", "rx_overflow";
35 interrupt-parent = <&intc>;
36 ti,buffer-size = <128>;
37 ti,hwmods = "mcbsp1";
38 };
39
40 mcbsp2: mcbsp@48076000 {
41 compatible = "ti,omap2430-mcbsp";
42 reg = <0x48076000 0xff>;
43 reg-names = "mpu";
44 interrupts = <16>, /* OCP compliant interrupt */
45 <62>, /* TX interrupt */
46 <63>; /* RX interrupt */
47 interrupt-names = "common", "tx", "rx";
48 interrupt-parent = <&intc>;
49 ti,buffer-size = <128>;
50 ti,hwmods = "mcbsp2";
51 };
52
53 mcbsp3: mcbsp@4808c000 {
54 compatible = "ti,omap2430-mcbsp";
55 reg = <0x4808c000 0xff>;
56 reg-names = "mpu";
57 interrupts = <17>, /* OCP compliant interrupt */
58 <89>, /* TX interrupt */
59 <90>; /* RX interrupt */
60 interrupt-names = "common", "tx", "rx";
61 interrupt-parent = <&intc>;
62 ti,buffer-size = <128>;
63 ti,hwmods = "mcbsp3";
64 };
65
66 mcbsp4: mcbsp@4808e000 {
67 compatible = "ti,omap2430-mcbsp";
68 reg = <0x4808e000 0xff>;
69 reg-names = "mpu";
70 interrupts = <18>, /* OCP compliant interrupt */
71 <54>, /* TX interrupt */
72 <55>; /* RX interrupt */
73 interrupt-names = "common", "tx", "rx";
74 interrupt-parent = <&intc>;
75 ti,buffer-size = <128>;
76 ti,hwmods = "mcbsp4";
77 };
78
79 mcbsp5: mcbsp@48096000 {
80 compatible = "ti,omap2430-mcbsp";
81 reg = <0x48096000 0xff>;
82 reg-names = "mpu";
83 interrupts = <19>, /* OCP compliant interrupt */
84 <81>, /* TX interrupt */
85 <82>; /* RX interrupt */
86 interrupt-names = "common", "tx", "rx";
87 interrupt-parent = <&intc>;
88 ti,buffer-size = <128>;
89 ti,hwmods = "mcbsp5";
90 };
91 };
92};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index cdcb98c7e075..c38cf76df81f 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -7,16 +7,44 @@
7 */ 7 */
8/dts-v1/; 8/dts-v1/;
9 9
10/include/ "omap3.dtsi" 10/include/ "omap36xx.dtsi"
11 11
12/ { 12/ {
13 model = "TI OMAP3 BeagleBoard"; 13 model = "TI OMAP3 BeagleBoard xM";
14 compatible = "ti,omap3-beagle", "ti,omap3"; 14 compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3";
15 15
16 memory { 16 memory {
17 device_type = "memory"; 17 device_type = "memory";
18 reg = <0x80000000 0x20000000>; /* 512 MB */ 18 reg = <0x80000000 0x20000000>; /* 512 MB */
19 }; 19 };
20
21 leds {
22 compatible = "gpio-leds";
23 pmu_stat {
24 label = "beagleboard::pmu_stat";
25 gpios = <&twl_gpio 19 0>; /* LEDB */
26 };
27
28 heartbeat {
29 label = "beagleboard::usr0";
30 gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
31 linux,default-trigger = "heartbeat";
32 };
33
34 mmc {
35 label = "beagleboard::usr1";
36 gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
37 linux,default-trigger = "mmc0";
38 };
39 };
40
41 sound {
42 compatible = "ti,omap-twl4030";
43 ti,model = "omap3beagle";
44
45 ti,mcbsp = <&mcbsp2>;
46 ti,codec = <&twl_audio>;
47 };
20}; 48};
21 49
22&i2c1 { 50&i2c1 {
@@ -27,11 +55,17 @@
27 interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 55 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
28 interrupt-parent = <&intc>; 56 interrupt-parent = <&intc>;
29 57
30 vsim: regulator@10 { 58 vsim: regulator-vsim {
31 compatible = "ti,twl4030-vsim"; 59 compatible = "ti,twl4030-vsim";
32 regulator-min-microvolt = <1800000>; 60 regulator-min-microvolt = <1800000>;
33 regulator-max-microvolt = <3000000>; 61 regulator-max-microvolt = <3000000>;
34 }; 62 };
63
64 twl_audio: audio {
65 compatible = "ti,twl4030-audio";
66 codec {
67 };
68 };
35 }; 69 };
36}; 70};
37 71
@@ -67,3 +101,15 @@
67&mmc3 { 101&mmc3 {
68 status = "disabled"; 102 status = "disabled";
69}; 103};
104
105&twl_gpio {
106 ti,use-leds;
107 /* pullups: BIT(1) */
108 ti,pullups = <0x000002>;
109 /*
110 * pulldowns:
111 * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
112 * BIT(15), BIT(16), BIT(17)
113 */
114 ti,pulldowns = <0x03a1c4>;
115};
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index f349ee9182ce..e8ba1c247a39 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -17,6 +17,15 @@
17 device_type = "memory"; 17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */ 18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 }; 19 };
20
21 leds {
22 compatible = "gpio-leds";
23 ledb {
24 label = "omap3evm::ledb";
25 gpios = <&twl_gpio 19 0>; /* LEDB */
26 linux,default-trigger = "default-on";
27 };
28 };
20}; 29};
21 30
22&i2c1 { 31&i2c1 {
@@ -46,3 +55,7 @@
46 reg = <0x5c>; 55 reg = <0x5c>;
47 }; 56 };
48}; 57};
58
59&twl_gpio {
60 ti,use-leds;
61};
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
new file mode 100644
index 000000000000..89808ce01673
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -0,0 +1,57 @@
1/*
2 * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * The Gumstix Overo must be combined with an expansion board.
11 */
12/dts-v1/;
13
14/include/ "omap3.dtsi"
15
16/ {
17 leds {
18 compatible = "gpio-leds";
19 overo {
20 label = "overo:blue:COM";
21 gpios = <&twl_gpio 19 0>;
22 linux,default-trigger = "mmc0";
23 };
24 };
25};
26
27&i2c1 {
28 clock-frequency = <2600000>;
29
30 twl: twl@48 {
31 reg = <0x48>;
32 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
33 interrupt-parent = <&intc>;
34 };
35};
36
37/include/ "twl4030.dtsi"
38
39/* i2c2 pins are used for gpio */
40&i2c2 {
41 status = "disabled";
42};
43
44/* on board microSD slot */
45&mmc1 {
46 vmmc-supply = <&vmmc1>;
47 bus-width = <4>;
48};
49
50/* optional on board WiFi */
51&mmc2 {
52 bus-width = <4>;
53};
54
55&twl_gpio {
56 ti,use-leds;
57};
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
new file mode 100644
index 000000000000..a13d12de77ff
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -0,0 +1,35 @@
1/*
2 * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Tobi expansion board is manufactured by Gumstix Inc.
11 */
12
13/include/ "omap3-overo.dtsi"
14
15/ {
16 model = "TI OMAP3 Gumstix Overo on Tobi";
17 compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3";
18
19 leds {
20 compatible = "gpio-leds";
21 heartbeat {
22 label = "overo:red:gpio21";
23 gpios = <&gpio1 21 0>;
24 linux,default-trigger = "heartbeat";
25 };
26 };
27};
28
29&i2c3 {
30 clock-frequency = <100000>;
31};
32
33&mmc3 {
34 status = "disabled";
35};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 810947198208..f38ea8771b44 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -17,7 +17,6 @@
17 serial0 = &uart1; 17 serial0 = &uart1;
18 serial1 = &uart2; 18 serial1 = &uart2;
19 serial2 = &uart3; 19 serial2 = &uart3;
20 serial3 = &uart4;
21 }; 20 };
22 21
23 cpus { 22 cpus {
@@ -69,6 +68,24 @@
69 reg = <0x48200000 0x1000>; 68 reg = <0x48200000 0x1000>;
70 }; 69 };
71 70
71 omap3_pmx_core: pinmux@48002030 {
72 compatible = "ti,omap3-padconf", "pinctrl-single";
73 reg = <0x48002030 0x05cc>;
74 #address-cells = <1>;
75 #size-cells = <0>;
76 pinctrl-single,register-width = <16>;
77 pinctrl-single,function-mask = <0x7fff>;
78 };
79
80 omap3_pmx_wkup: pinmux@0x48002a58 {
81 compatible = "ti,omap3-padconf", "pinctrl-single";
82 reg = <0x48002a58 0x5c>;
83 #address-cells = <1>;
84 #size-cells = <0>;
85 pinctrl-single,register-width = <16>;
86 pinctrl-single,function-mask = <0x7fff>;
87 };
88
72 gpio1: gpio@48310000 { 89 gpio1: gpio@48310000 {
73 compatible = "ti,omap3-gpio"; 90 compatible = "ti,omap3-gpio";
74 ti,hwmods = "gpio1"; 91 ti,hwmods = "gpio1";
@@ -141,12 +158,6 @@
141 clock-frequency = <48000000>; 158 clock-frequency = <48000000>;
142 }; 159 };
143 160
144 uart4: serial@49042000 {
145 compatible = "ti,omap3-uart";
146 ti,hwmods = "uart4";
147 clock-frequency = <48000000>;
148 };
149
150 i2c1: i2c@48070000 { 161 i2c1: i2c@48070000 {
151 compatible = "ti,omap3-i2c"; 162 compatible = "ti,omap3-i2c";
152 #address-cells = <1>; 163 #address-cells = <1>;
@@ -220,5 +231,74 @@
220 compatible = "ti,omap3-wdt"; 231 compatible = "ti,omap3-wdt";
221 ti,hwmods = "wd_timer2"; 232 ti,hwmods = "wd_timer2";
222 }; 233 };
234
235 mcbsp1: mcbsp@48074000 {
236 compatible = "ti,omap3-mcbsp";
237 reg = <0x48074000 0xff>;
238 reg-names = "mpu";
239 interrupts = <16>, /* OCP compliant interrupt */
240 <59>, /* TX interrupt */
241 <60>; /* RX interrupt */
242 interrupt-names = "common", "tx", "rx";
243 interrupt-parent = <&intc>;
244 ti,buffer-size = <128>;
245 ti,hwmods = "mcbsp1";
246 };
247
248 mcbsp2: mcbsp@49022000 {
249 compatible = "ti,omap3-mcbsp";
250 reg = <0x49022000 0xff>,
251 <0x49028000 0xff>;
252 reg-names = "mpu", "sidetone";
253 interrupts = <17>, /* OCP compliant interrupt */
254 <62>, /* TX interrupt */
255 <63>, /* RX interrupt */
256 <4>; /* Sidetone */
257 interrupt-names = "common", "tx", "rx", "sidetone";
258 interrupt-parent = <&intc>;
259 ti,buffer-size = <1280>;
260 ti,hwmods = "mcbsp2";
261 };
262
263 mcbsp3: mcbsp@49024000 {
264 compatible = "ti,omap3-mcbsp";
265 reg = <0x49024000 0xff>,
266 <0x4902a000 0xff>;
267 reg-names = "mpu", "sidetone";
268 interrupts = <22>, /* OCP compliant interrupt */
269 <89>, /* TX interrupt */
270 <90>, /* RX interrupt */
271 <5>; /* Sidetone */
272 interrupt-names = "common", "tx", "rx", "sidetone";
273 interrupt-parent = <&intc>;
274 ti,buffer-size = <128>;
275 ti,hwmods = "mcbsp3";
276 };
277
278 mcbsp4: mcbsp@49026000 {
279 compatible = "ti,omap3-mcbsp";
280 reg = <0x49026000 0xff>;
281 reg-names = "mpu";
282 interrupts = <23>, /* OCP compliant interrupt */
283 <54>, /* TX interrupt */
284 <55>; /* RX interrupt */
285 interrupt-names = "common", "tx", "rx";
286 interrupt-parent = <&intc>;
287 ti,buffer-size = <128>;
288 ti,hwmods = "mcbsp4";
289 };
290
291 mcbsp5: mcbsp@48096000 {
292 compatible = "ti,omap3-mcbsp";
293 reg = <0x48096000 0xff>;
294 reg-names = "mpu";
295 interrupts = <27>, /* OCP compliant interrupt */
296 <81>, /* TX interrupt */
297 <82>; /* RX interrupt */
298 interrupt-names = "common", "tx", "rx";
299 interrupt-parent = <&intc>;
300 ti,buffer-size = <128>;
301 ti,hwmods = "mcbsp5";
302 };
223 }; 303 };
224}; 304};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
new file mode 100644
index 000000000000..96bf0287cb9f
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -0,0 +1,25 @@
1/*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "omap3.dtsi"
12
13/ {
14 aliases {
15 serial3 = &uart4;
16 };
17
18 ocp {
19 uart4: serial@49042000 {
20 compatible = "ti,omap3-uart";
21 ti,hwmods = "uart4";
22 clock-frequency = <48000000>;
23 };
24 };
25};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 9880c12877b3..20b966ee1bb3 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -8,6 +8,7 @@
8/dts-v1/; 8/dts-v1/;
9 9
10/include/ "omap4.dtsi" 10/include/ "omap4.dtsi"
11/include/ "elpida_ecb240abacn.dtsi"
11 12
12/ { 13/ {
13 model = "TI OMAP4 PandaBoard"; 14 model = "TI OMAP4 PandaBoard";
@@ -126,3 +127,13 @@
126 ti,non-removable; 127 ti,non-removable;
127 bus-width = <4>; 128 bus-width = <4>;
128}; 129};
130
131&emif1 {
132 cs1-used;
133 device-handle = <&elpida_ECB240ABACN>;
134};
135
136&emif2 {
137 cs1-used;
138 device-handle = <&elpida_ECB240ABACN>;
139};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 72216e932fc0..94a23b39033d 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -8,6 +8,7 @@
8/dts-v1/; 8/dts-v1/;
9 9
10/include/ "omap4.dtsi" 10/include/ "omap4.dtsi"
11/include/ "elpida_ecb240abacn.dtsi"
11 12
12/ { 13/ {
13 model = "TI OMAP4 SDP board"; 14 model = "TI OMAP4 SDP board";
@@ -18,7 +19,7 @@
18 reg = <0x80000000 0x40000000>; /* 1 GB */ 19 reg = <0x80000000 0x40000000>; /* 1 GB */
19 }; 20 };
20 21
21 vdd_eth: fixedregulator@0 { 22 vdd_eth: fixedregulator-vdd-eth {
22 compatible = "regulator-fixed"; 23 compatible = "regulator-fixed";
23 regulator-name = "VDD_ETH"; 24 regulator-name = "VDD_ETH";
24 regulator-min-microvolt = <3300000>; 25 regulator-min-microvolt = <3300000>;
@@ -28,7 +29,7 @@
28 regulator-boot-on; 29 regulator-boot-on;
29 }; 30 };
30 31
31 vbat: fixedregulator@2 { 32 vbat: fixedregulator-vbat {
32 compatible = "regulator-fixed"; 33 compatible = "regulator-fixed";
33 regulator-name = "VBAT"; 34 regulator-name = "VBAT";
34 regulator-min-microvolt = <3750000>; 35 regulator-min-microvolt = <3750000>;
@@ -115,6 +116,33 @@
115 }; 116 };
116}; 117};
117 118
119&omap4_pmx_core {
120 uart2_pins: pinmux_uart2_pins {
121 pinctrl-single,pins = <
122 0xd8 0x118 /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */
123 0xda 0 /* uart2_rts.uart2_rts OUTPUT | MODE0 */
124 0xdc 0x118 /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */
125 0xde 0 /* uart2_tx.uart2_tx OUTPUT | MODE0 */
126 >;
127 };
128
129 uart3_pins: pinmux_uart3_pins {
130 pinctrl-single,pins = <
131 0x100 0x118 /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */
132 0x102 0 /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */
133 0x104 0x100 /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */
134 0x106 0 /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
135 >;
136 };
137
138 uart4_pins: pinmux_uart4_pins {
139 pinctrl-single,pins = <
140 0x11c 0x100 /* uart4_rx.uart4_rx INPUT | MODE0 */
141 0x11e 0 /* uart4_tx.uart4_tx OUTPUT | MODE0 */
142 >;
143 };
144};
145
118&i2c1 { 146&i2c1 {
119 clock-frequency = <400000>; 147 clock-frequency = <400000>;
120 148
@@ -226,3 +254,98 @@
226 bus-width = <4>; 254 bus-width = <4>;
227 ti,non-removable; 255 ti,non-removable;
228}; 256};
257
258&emif1 {
259 cs1-used;
260 device-handle = <&elpida_ECB240ABACN>;
261};
262
263&emif2 {
264 cs1-used;
265 device-handle = <&elpida_ECB240ABACN>;
266};
267
268&keypad {
269 keypad,num-rows = <8>;
270 keypad,num-columns = <8>;
271 linux,keymap = <0x00000012 /* KEY_E */
272 0x00010013 /* KEY_R */
273 0x00020014 /* KEY_T */
274 0x00030066 /* KEY_HOME */
275 0x0004003f /* KEY_F5 */
276 0x000500f0 /* KEY_UNKNOWN */
277 0x00060017 /* KEY_I */
278 0x0007002a /* KEY_LEFTSHIFT */
279 0x01000020 /* KEY_D*/
280 0x01010021 /* KEY_F */
281 0x01020022 /* KEY_G */
282 0x010300e7 /* KEY_SEND */
283 0x01040040 /* KEY_F6 */
284 0x010500f0 /* KEY_UNKNOWN */
285 0x01060025 /* KEY_K */
286 0x0107001c /* KEY_ENTER */
287 0x0200002d /* KEY_X */
288 0x0201002e /* KEY_C */
289 0x0202002f /* KEY_V */
290 0x0203006b /* KEY_END */
291 0x02040041 /* KEY_F7 */
292 0x020500f0 /* KEY_UNKNOWN */
293 0x02060034 /* KEY_DOT */
294 0x0207003a /* KEY_CAPSLOCK */
295 0x0300002c /* KEY_Z */
296 0x0301004e /* KEY_KPLUS */
297 0x03020030 /* KEY_B */
298 0x0303003b /* KEY_F1 */
299 0x03040042 /* KEY_F8 */
300 0x030500f0 /* KEY_UNKNOWN */
301 0x03060018 /* KEY_O */
302 0x03070039 /* KEY_SPACE */
303 0x04000011 /* KEY_W */
304 0x04010015 /* KEY_Y */
305 0x04020016 /* KEY_U */
306 0x0403003c /* KEY_F2 */
307 0x04040073 /* KEY_VOLUMEUP */
308 0x040500f0 /* KEY_UNKNOWN */
309 0x04060026 /* KEY_L */
310 0x04070069 /* KEY_LEFT */
311 0x0500001f /* KEY_S */
312 0x05010023 /* KEY_H */
313 0x05020024 /* KEY_J */
314 0x0503003d /* KEY_F3 */
315 0x05040043 /* KEY_F9 */
316 0x05050072 /* KEY_VOLUMEDOWN */
317 0x05060032 /* KEY_M */
318 0x0507006a /* KEY_RIGHT */
319 0x06000010 /* KEY_Q */
320 0x0601001e /* KEY_A */
321 0x06020031 /* KEY_N */
322 0x0603009e /* KEY_BACK */
323 0x0604000e /* KEY_BACKSPACE */
324 0x060500f0 /* KEY_UNKNOWN */
325 0x06060019 /* KEY_P */
326 0x06070067 /* KEY_UP */
327 0x07000094 /* KEY_PROG1 */
328 0x07010095 /* KEY_PROG2 */
329 0x070200ca /* KEY_PROG3 */
330 0x070300cb /* KEY_PROG4 */
331 0x0704003e /* KEY_F4 */
332 0x070500f0 /* KEY_UNKNOWN */
333 0x07060160 /* KEY_OK */
334 0x0707006c>; /* KEY_DOWN */
335 linux,input-no-autorepeat;
336};
337
338&uart2 {
339 pinctrl-names = "default";
340 pinctrl-0 = <&uart2_pins>;
341};
342
343&uart3 {
344 pinctrl-names = "default";
345 pinctrl-0 = <&uart3_pins>;
346};
347
348&uart4 {
349 pinctrl-names = "default";
350 pinctrl-0 = <&uart4_pins>;
351};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 04cbbcb6ff91..5d1c48459e6e 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -30,12 +30,35 @@
30 cpus { 30 cpus {
31 cpu@0 { 31 cpu@0 {
32 compatible = "arm,cortex-a9"; 32 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
33 }; 34 };
34 cpu@1 { 35 cpu@1 {
35 compatible = "arm,cortex-a9"; 36 compatible = "arm,cortex-a9";
37 next-level-cache = <&L2>;
36 }; 38 };
37 }; 39 };
38 40
41 gic: interrupt-controller@48241000 {
42 compatible = "arm,cortex-a9-gic";
43 interrupt-controller;
44 #interrupt-cells = <3>;
45 reg = <0x48241000 0x1000>,
46 <0x48240100 0x0100>;
47 };
48
49 L2: l2-cache-controller@48242000 {
50 compatible = "arm,pl310-cache";
51 reg = <0x48242000 0x1000>;
52 cache-unified;
53 cache-level = <2>;
54 };
55
56 local-timer@0x48240600 {
57 compatible = "arm,cortex-a9-twd-timer";
58 reg = <0x48240600 0x20>;
59 interrupts = <1 13 0x304>;
60 };
61
39 /* 62 /*
40 * The soc node represents the soc top level view. It is uses for IPs 63 * The soc node represents the soc top level view. It is uses for IPs
41 * that are not memory mapped in the MPU view or for the MPU itself. 64 * that are not memory mapped in the MPU view or for the MPU itself.
@@ -61,30 +84,6 @@
61 /* 84 /*
62 * XXX: Use a flat representation of the OMAP4 interconnect. 85 * XXX: Use a flat representation of the OMAP4 interconnect.
63 * The real OMAP interconnect network is quite complex. 86 * The real OMAP interconnect network is quite complex.
64 *
65 * MPU -+-- MPU_PRIVATE - GIC, L2
66 * |
67 * +----------------+----------+
68 * | | |
69 * + +- EMIF - DDR |
70 * | | |
71 * | + +--------+
72 * | | |
73 * | +- L4_ABE - AESS, MCBSP, TIMERs...
74 * | |
75 * +- L3_MAIN --+- L4_CORE - IPs...
76 * |
77 * +- L4_PER - IPs...
78 * |
79 * +- L4_CFG -+- L4_WKUP - IPs...
80 * | |
81 * | +- IPs...
82 * +- IPU ----+
83 * | |
84 * +- DSP ----+
85 * | |
86 * +- DSS ----+
87 *
88 * Since that will not bring real advantage to represent that in DT for 87 * Since that will not bring real advantage to represent that in DT for
89 * the moment, just use a fake OCP bus entry to represent the whole bus 88 * the moment, just use a fake OCP bus entry to represent the whole bus
90 * hierarchy. 89 * hierarchy.
@@ -96,16 +95,27 @@
96 ranges; 95 ranges;
97 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; 96 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
98 97
99 gic: interrupt-controller@48241000 { 98 omap4_pmx_core: pinmux@4a100040 {
100 compatible = "arm,cortex-a9-gic"; 99 compatible = "ti,omap4-padconf", "pinctrl-single";
101 interrupt-controller; 100 reg = <0x4a100040 0x0196>;
102 #interrupt-cells = <3>; 101 #address-cells = <1>;
103 reg = <0x48241000 0x1000>, 102 #size-cells = <0>;
104 <0x48240100 0x0100>; 103 pinctrl-single,register-width = <16>;
104 pinctrl-single,function-mask = <0x7fff>;
105 };
106 omap4_pmx_wkup: pinmux@4a31e040 {
107 compatible = "ti,omap4-padconf", "pinctrl-single";
108 reg = <0x4a31e040 0x0038>;
109 #address-cells = <1>;
110 #size-cells = <0>;
111 pinctrl-single,register-width = <16>;
112 pinctrl-single,function-mask = <0x7fff>;
105 }; 113 };
106 114
107 gpio1: gpio@4a310000 { 115 gpio1: gpio@4a310000 {
108 compatible = "ti,omap4-gpio"; 116 compatible = "ti,omap4-gpio";
117 reg = <0x4a310000 0x200>;
118 interrupts = <0 29 0x4>;
109 ti,hwmods = "gpio1"; 119 ti,hwmods = "gpio1";
110 gpio-controller; 120 gpio-controller;
111 #gpio-cells = <2>; 121 #gpio-cells = <2>;
@@ -115,6 +125,8 @@
115 125
116 gpio2: gpio@48055000 { 126 gpio2: gpio@48055000 {
117 compatible = "ti,omap4-gpio"; 127 compatible = "ti,omap4-gpio";
128 reg = <0x48055000 0x200>;
129 interrupts = <0 30 0x4>;
118 ti,hwmods = "gpio2"; 130 ti,hwmods = "gpio2";
119 gpio-controller; 131 gpio-controller;
120 #gpio-cells = <2>; 132 #gpio-cells = <2>;
@@ -124,6 +136,8 @@
124 136
125 gpio3: gpio@48057000 { 137 gpio3: gpio@48057000 {
126 compatible = "ti,omap4-gpio"; 138 compatible = "ti,omap4-gpio";
139 reg = <0x48057000 0x200>;
140 interrupts = <0 31 0x4>;
127 ti,hwmods = "gpio3"; 141 ti,hwmods = "gpio3";
128 gpio-controller; 142 gpio-controller;
129 #gpio-cells = <2>; 143 #gpio-cells = <2>;
@@ -133,6 +147,8 @@
133 147
134 gpio4: gpio@48059000 { 148 gpio4: gpio@48059000 {
135 compatible = "ti,omap4-gpio"; 149 compatible = "ti,omap4-gpio";
150 reg = <0x48059000 0x200>;
151 interrupts = <0 32 0x4>;
136 ti,hwmods = "gpio4"; 152 ti,hwmods = "gpio4";
137 gpio-controller; 153 gpio-controller;
138 #gpio-cells = <2>; 154 #gpio-cells = <2>;
@@ -142,6 +158,8 @@
142 158
143 gpio5: gpio@4805b000 { 159 gpio5: gpio@4805b000 {
144 compatible = "ti,omap4-gpio"; 160 compatible = "ti,omap4-gpio";
161 reg = <0x4805b000 0x200>;
162 interrupts = <0 33 0x4>;
145 ti,hwmods = "gpio5"; 163 ti,hwmods = "gpio5";
146 gpio-controller; 164 gpio-controller;
147 #gpio-cells = <2>; 165 #gpio-cells = <2>;
@@ -151,6 +169,8 @@
151 169
152 gpio6: gpio@4805d000 { 170 gpio6: gpio@4805d000 {
153 compatible = "ti,omap4-gpio"; 171 compatible = "ti,omap4-gpio";
172 reg = <0x4805d000 0x200>;
173 interrupts = <0 34 0x4>;
154 ti,hwmods = "gpio6"; 174 ti,hwmods = "gpio6";
155 gpio-controller; 175 gpio-controller;
156 #gpio-cells = <2>; 176 #gpio-cells = <2>;
@@ -160,30 +180,40 @@
160 180
161 uart1: serial@4806a000 { 181 uart1: serial@4806a000 {
162 compatible = "ti,omap4-uart"; 182 compatible = "ti,omap4-uart";
183 reg = <0x4806a000 0x100>;
184 interrupts = <0 72 0x4>;
163 ti,hwmods = "uart1"; 185 ti,hwmods = "uart1";
164 clock-frequency = <48000000>; 186 clock-frequency = <48000000>;
165 }; 187 };
166 188
167 uart2: serial@4806c000 { 189 uart2: serial@4806c000 {
168 compatible = "ti,omap4-uart"; 190 compatible = "ti,omap4-uart";
191 reg = <0x4806c000 0x100>;
192 interrupts = <0 73 0x4>;
169 ti,hwmods = "uart2"; 193 ti,hwmods = "uart2";
170 clock-frequency = <48000000>; 194 clock-frequency = <48000000>;
171 }; 195 };
172 196
173 uart3: serial@48020000 { 197 uart3: serial@48020000 {
174 compatible = "ti,omap4-uart"; 198 compatible = "ti,omap4-uart";
199 reg = <0x48020000 0x100>;
200 interrupts = <0 74 0x4>;
175 ti,hwmods = "uart3"; 201 ti,hwmods = "uart3";
176 clock-frequency = <48000000>; 202 clock-frequency = <48000000>;
177 }; 203 };
178 204
179 uart4: serial@4806e000 { 205 uart4: serial@4806e000 {
180 compatible = "ti,omap4-uart"; 206 compatible = "ti,omap4-uart";
207 reg = <0x4806e000 0x100>;
208 interrupts = <0 70 0x4>;
181 ti,hwmods = "uart4"; 209 ti,hwmods = "uart4";
182 clock-frequency = <48000000>; 210 clock-frequency = <48000000>;
183 }; 211 };
184 212
185 i2c1: i2c@48070000 { 213 i2c1: i2c@48070000 {
186 compatible = "ti,omap4-i2c"; 214 compatible = "ti,omap4-i2c";
215 reg = <0x48070000 0x100>;
216 interrupts = <0 56 0x4>;
187 #address-cells = <1>; 217 #address-cells = <1>;
188 #size-cells = <0>; 218 #size-cells = <0>;
189 ti,hwmods = "i2c1"; 219 ti,hwmods = "i2c1";
@@ -191,6 +221,8 @@
191 221
192 i2c2: i2c@48072000 { 222 i2c2: i2c@48072000 {
193 compatible = "ti,omap4-i2c"; 223 compatible = "ti,omap4-i2c";
224 reg = <0x48072000 0x100>;
225 interrupts = <0 57 0x4>;
194 #address-cells = <1>; 226 #address-cells = <1>;
195 #size-cells = <0>; 227 #size-cells = <0>;
196 ti,hwmods = "i2c2"; 228 ti,hwmods = "i2c2";
@@ -198,6 +230,8 @@
198 230
199 i2c3: i2c@48060000 { 231 i2c3: i2c@48060000 {
200 compatible = "ti,omap4-i2c"; 232 compatible = "ti,omap4-i2c";
233 reg = <0x48060000 0x100>;
234 interrupts = <0 61 0x4>;
201 #address-cells = <1>; 235 #address-cells = <1>;
202 #size-cells = <0>; 236 #size-cells = <0>;
203 ti,hwmods = "i2c3"; 237 ti,hwmods = "i2c3";
@@ -205,6 +239,8 @@
205 239
206 i2c4: i2c@48350000 { 240 i2c4: i2c@48350000 {
207 compatible = "ti,omap4-i2c"; 241 compatible = "ti,omap4-i2c";
242 reg = <0x48350000 0x100>;
243 interrupts = <0 62 0x4>;
208 #address-cells = <1>; 244 #address-cells = <1>;
209 #size-cells = <0>; 245 #size-cells = <0>;
210 ti,hwmods = "i2c4"; 246 ti,hwmods = "i2c4";
@@ -212,6 +248,8 @@
212 248
213 mcspi1: spi@48098000 { 249 mcspi1: spi@48098000 {
214 compatible = "ti,omap4-mcspi"; 250 compatible = "ti,omap4-mcspi";
251 reg = <0x48098000 0x200>;
252 interrupts = <0 65 0x4>;
215 #address-cells = <1>; 253 #address-cells = <1>;
216 #size-cells = <0>; 254 #size-cells = <0>;
217 ti,hwmods = "mcspi1"; 255 ti,hwmods = "mcspi1";
@@ -220,6 +258,8 @@
220 258
221 mcspi2: spi@4809a000 { 259 mcspi2: spi@4809a000 {
222 compatible = "ti,omap4-mcspi"; 260 compatible = "ti,omap4-mcspi";
261 reg = <0x4809a000 0x200>;
262 interrupts = <0 66 0x4>;
223 #address-cells = <1>; 263 #address-cells = <1>;
224 #size-cells = <0>; 264 #size-cells = <0>;
225 ti,hwmods = "mcspi2"; 265 ti,hwmods = "mcspi2";
@@ -228,6 +268,8 @@
228 268
229 mcspi3: spi@480b8000 { 269 mcspi3: spi@480b8000 {
230 compatible = "ti,omap4-mcspi"; 270 compatible = "ti,omap4-mcspi";
271 reg = <0x480b8000 0x200>;
272 interrupts = <0 91 0x4>;
231 #address-cells = <1>; 273 #address-cells = <1>;
232 #size-cells = <0>; 274 #size-cells = <0>;
233 ti,hwmods = "mcspi3"; 275 ti,hwmods = "mcspi3";
@@ -236,6 +278,8 @@
236 278
237 mcspi4: spi@480ba000 { 279 mcspi4: spi@480ba000 {
238 compatible = "ti,omap4-mcspi"; 280 compatible = "ti,omap4-mcspi";
281 reg = <0x480ba000 0x200>;
282 interrupts = <0 48 0x4>;
239 #address-cells = <1>; 283 #address-cells = <1>;
240 #size-cells = <0>; 284 #size-cells = <0>;
241 ti,hwmods = "mcspi4"; 285 ti,hwmods = "mcspi4";
@@ -244,6 +288,8 @@
244 288
245 mmc1: mmc@4809c000 { 289 mmc1: mmc@4809c000 {
246 compatible = "ti,omap4-hsmmc"; 290 compatible = "ti,omap4-hsmmc";
291 reg = <0x4809c000 0x400>;
292 interrupts = <0 83 0x4>;
247 ti,hwmods = "mmc1"; 293 ti,hwmods = "mmc1";
248 ti,dual-volt; 294 ti,dual-volt;
249 ti,needs-special-reset; 295 ti,needs-special-reset;
@@ -251,30 +297,40 @@
251 297
252 mmc2: mmc@480b4000 { 298 mmc2: mmc@480b4000 {
253 compatible = "ti,omap4-hsmmc"; 299 compatible = "ti,omap4-hsmmc";
300 reg = <0x480b4000 0x400>;
301 interrupts = <0 86 0x4>;
254 ti,hwmods = "mmc2"; 302 ti,hwmods = "mmc2";
255 ti,needs-special-reset; 303 ti,needs-special-reset;
256 }; 304 };
257 305
258 mmc3: mmc@480ad000 { 306 mmc3: mmc@480ad000 {
259 compatible = "ti,omap4-hsmmc"; 307 compatible = "ti,omap4-hsmmc";
308 reg = <0x480ad000 0x400>;
309 interrupts = <0 94 0x4>;
260 ti,hwmods = "mmc3"; 310 ti,hwmods = "mmc3";
261 ti,needs-special-reset; 311 ti,needs-special-reset;
262 }; 312 };
263 313
264 mmc4: mmc@480d1000 { 314 mmc4: mmc@480d1000 {
265 compatible = "ti,omap4-hsmmc"; 315 compatible = "ti,omap4-hsmmc";
316 reg = <0x480d1000 0x400>;
317 interrupts = <0 96 0x4>;
266 ti,hwmods = "mmc4"; 318 ti,hwmods = "mmc4";
267 ti,needs-special-reset; 319 ti,needs-special-reset;
268 }; 320 };
269 321
270 mmc5: mmc@480d5000 { 322 mmc5: mmc@480d5000 {
271 compatible = "ti,omap4-hsmmc"; 323 compatible = "ti,omap4-hsmmc";
324 reg = <0x480d5000 0x400>;
325 interrupts = <0 59 0x4>;
272 ti,hwmods = "mmc5"; 326 ti,hwmods = "mmc5";
273 ti,needs-special-reset; 327 ti,needs-special-reset;
274 }; 328 };
275 329
276 wdt2: wdt@4a314000 { 330 wdt2: wdt@4a314000 {
277 compatible = "ti,omap4-wdt", "ti,omap3-wdt"; 331 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
332 reg = <0x4a314000 0x80>;
333 interrupts = <0 80 0x4>;
278 ti,hwmods = "wd_timer2"; 334 ti,hwmods = "wd_timer2";
279 }; 335 };
280 336
@@ -282,6 +338,7 @@
282 compatible = "ti,omap4-mcpdm"; 338 compatible = "ti,omap4-mcpdm";
283 reg = <0x40132000 0x7f>, /* MPU private access */ 339 reg = <0x40132000 0x7f>, /* MPU private access */
284 <0x49032000 0x7f>; /* L3 Interconnect */ 340 <0x49032000 0x7f>; /* L3 Interconnect */
341 reg-names = "mpu", "dma";
285 interrupts = <0 112 0x4>; 342 interrupts = <0 112 0x4>;
286 interrupt-parent = <&gic>; 343 interrupt-parent = <&gic>;
287 ti,hwmods = "mcpdm"; 344 ti,hwmods = "mcpdm";
@@ -291,9 +348,87 @@
291 compatible = "ti,omap4-dmic"; 348 compatible = "ti,omap4-dmic";
292 reg = <0x4012e000 0x7f>, /* MPU private access */ 349 reg = <0x4012e000 0x7f>, /* MPU private access */
293 <0x4902e000 0x7f>; /* L3 Interconnect */ 350 <0x4902e000 0x7f>; /* L3 Interconnect */
351 reg-names = "mpu", "dma";
294 interrupts = <0 114 0x4>; 352 interrupts = <0 114 0x4>;
295 interrupt-parent = <&gic>; 353 interrupt-parent = <&gic>;
296 ti,hwmods = "dmic"; 354 ti,hwmods = "dmic";
297 }; 355 };
356
357 mcbsp1: mcbsp@40122000 {
358 compatible = "ti,omap4-mcbsp";
359 reg = <0x40122000 0xff>, /* MPU private access */
360 <0x49022000 0xff>; /* L3 Interconnect */
361 reg-names = "mpu", "dma";
362 interrupts = <0 17 0x4>;
363 interrupt-names = "common";
364 interrupt-parent = <&gic>;
365 ti,buffer-size = <128>;
366 ti,hwmods = "mcbsp1";
367 };
368
369 mcbsp2: mcbsp@40124000 {
370 compatible = "ti,omap4-mcbsp";
371 reg = <0x40124000 0xff>, /* MPU private access */
372 <0x49024000 0xff>; /* L3 Interconnect */
373 reg-names = "mpu", "dma";
374 interrupts = <0 22 0x4>;
375 interrupt-names = "common";
376 interrupt-parent = <&gic>;
377 ti,buffer-size = <128>;
378 ti,hwmods = "mcbsp2";
379 };
380
381 mcbsp3: mcbsp@40126000 {
382 compatible = "ti,omap4-mcbsp";
383 reg = <0x40126000 0xff>, /* MPU private access */
384 <0x49026000 0xff>; /* L3 Interconnect */
385 reg-names = "mpu", "dma";
386 interrupts = <0 23 0x4>;
387 interrupt-names = "common";
388 interrupt-parent = <&gic>;
389 ti,buffer-size = <128>;
390 ti,hwmods = "mcbsp3";
391 };
392
393 mcbsp4: mcbsp@48096000 {
394 compatible = "ti,omap4-mcbsp";
395 reg = <0x48096000 0xff>; /* L4 Interconnect */
396 reg-names = "mpu";
397 interrupts = <0 16 0x4>;
398 interrupt-names = "common";
399 interrupt-parent = <&gic>;
400 ti,buffer-size = <128>;
401 ti,hwmods = "mcbsp4";
402 };
403
404 keypad: keypad@4a31c000 {
405 compatible = "ti,omap4-keypad";
406 reg = <0x4a31c000 0x80>;
407 interrupts = <0 120 0x4>;
408 reg-names = "mpu";
409 ti,hwmods = "kbd";
410 };
411
412 emif1: emif@4c000000 {
413 compatible = "ti,emif-4d";
414 reg = <0x4c000000 0x100>;
415 interrupts = <0 110 0x4>;
416 ti,hwmods = "emif1";
417 phy-type = <1>;
418 hw-caps-read-idle-ctrl;
419 hw-caps-ll-interface;
420 hw-caps-temp-alert;
421 };
422
423 emif2: emif@4d000000 {
424 compatible = "ti,emif-4d";
425 reg = <0x4d000000 0x100>;
426 interrupts = <0 111 0x4>;
427 ti,hwmods = "emif2";
428 phy-type = <1>;
429 hw-caps-read-idle-ctrl;
430 hw-caps-ll-interface;
431 hw-caps-temp-alert;
432 };
298 }; 433 };
299}; 434};
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 200c39ad1c82..9c41a3f311aa 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -17,4 +17,68 @@
17 device_type = "memory"; 17 device_type = "memory";
18 reg = <0x80000000 0x40000000>; /* 1 GB */ 18 reg = <0x80000000 0x40000000>; /* 1 GB */
19 }; 19 };
20
21 vmmcsd_fixed: fixedregulator-mmcsd {
22 compatible = "regulator-fixed";
23 regulator-name = "vmmcsd_fixed";
24 regulator-min-microvolt = <3000000>;
25 regulator-max-microvolt = <3000000>;
26 };
27
28};
29
30&mmc1 {
31 vmmc-supply = <&vmmcsd_fixed>;
32 bus-width = <4>;
33};
34
35&mmc2 {
36 vmmc-supply = <&vmmcsd_fixed>;
37 bus-width = <8>;
38 ti,non-removable;
39};
40
41&mmc3 {
42 bus-width = <4>;
43 ti,non-removable;
44};
45
46&mmc4 {
47 status = "disabled";
48};
49
50&mmc5 {
51 status = "disabled";
52};
53
54&i2c2 {
55 clock-frequency = <400000>;
56
57 /* Pressure Sensor */
58 bmp085@77 {
59 compatible = "bosch,bmp085";
60 reg = <0x77>;
61 };
62};
63
64&i2c4 {
65 clock-frequency = <400000>;
66
67 /* Temperature Sensor */
68 tmp102@48{
69 compatible = "ti,tmp102";
70 reg = <0x48>;
71 };
72};
73
74&keypad {
75 keypad,num-rows = <8>;
76 keypad,num-columns = <8>;
77 linux,keymap = <0x02020073 /* VOLUP */
78 0x02030072 /* VOLDOWM */
79 0x020400e7 /* SEND */
80 0x02050066 /* HOME */
81 0x0206006b /* END */
82 0x020700d9>; /* SEARCH */
83 linux,input-no-autorepeat;
20}; 84};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 57e527083746..5db33f481a33 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -33,9 +33,21 @@
33 cpus { 33 cpus {
34 cpu@0 { 34 cpu@0 {
35 compatible = "arm,cortex-a15"; 35 compatible = "arm,cortex-a15";
36 timer {
37 compatible = "arm,armv7-timer";
38 /* 14th PPI IRQ, active low level-sensitive */
39 interrupts = <1 14 0x308>;
40 clock-frequency = <6144000>;
41 };
36 }; 42 };
37 cpu@1 { 43 cpu@1 {
38 compatible = "arm,cortex-a15"; 44 compatible = "arm,cortex-a15";
45 timer {
46 compatible = "arm,armv7-timer";
47 /* 14th PPI IRQ, active low level-sensitive */
48 interrupts = <1 14 0x308>;
49 clock-frequency = <6144000>;
50 };
39 }; 51 };
40 }; 52 };
41 53
@@ -145,6 +157,41 @@
145 #interrupt-cells = <1>; 157 #interrupt-cells = <1>;
146 }; 158 };
147 159
160 i2c1: i2c@48070000 {
161 compatible = "ti,omap4-i2c";
162 #address-cells = <1>;
163 #size-cells = <0>;
164 ti,hwmods = "i2c1";
165 };
166
167 i2c2: i2c@48072000 {
168 compatible = "ti,omap4-i2c";
169 #address-cells = <1>;
170 #size-cells = <0>;
171 ti,hwmods = "i2c2";
172 };
173
174 i2c3: i2c@48060000 {
175 compatible = "ti,omap4-i2c";
176 #address-cells = <1>;
177 #size-cells = <0>;
178 ti,hwmods = "i2c3";
179 };
180
181 i2c4: i2c@4807A000 {
182 compatible = "ti,omap4-i2c";
183 #address-cells = <1>;
184 #size-cells = <0>;
185 ti,hwmods = "i2c4";
186 };
187
188 i2c5: i2c@4807C000 {
189 compatible = "ti,omap4-i2c";
190 #address-cells = <1>;
191 #size-cells = <0>;
192 ti,hwmods = "i2c5";
193 };
194
148 uart1: serial@4806a000 { 195 uart1: serial@4806a000 {
149 compatible = "ti,omap4-uart"; 196 compatible = "ti,omap4-uart";
150 ti,hwmods = "uart1"; 197 ti,hwmods = "uart1";
@@ -180,5 +227,97 @@
180 ti,hwmods = "uart6"; 227 ti,hwmods = "uart6";
181 clock-frequency = <48000000>; 228 clock-frequency = <48000000>;
182 }; 229 };
230
231 mmc1: mmc@4809c000 {
232 compatible = "ti,omap4-hsmmc";
233 ti,hwmods = "mmc1";
234 ti,dual-volt;
235 ti,needs-special-reset;
236 };
237
238 mmc2: mmc@480b4000 {
239 compatible = "ti,omap4-hsmmc";
240 ti,hwmods = "mmc2";
241 ti,needs-special-reset;
242 };
243
244 mmc3: mmc@480ad000 {
245 compatible = "ti,omap4-hsmmc";
246 ti,hwmods = "mmc3";
247 ti,needs-special-reset;
248 };
249
250 mmc4: mmc@480d1000 {
251 compatible = "ti,omap4-hsmmc";
252 ti,hwmods = "mmc4";
253 ti,needs-special-reset;
254 };
255
256 mmc5: mmc@480d5000 {
257 compatible = "ti,omap4-hsmmc";
258 ti,hwmods = "mmc5";
259 ti,needs-special-reset;
260 };
261
262 keypad: keypad@4ae1c000 {
263 compatible = "ti,omap4-keypad";
264 ti,hwmods = "kbd";
265 };
266
267 mcpdm: mcpdm@40132000 {
268 compatible = "ti,omap4-mcpdm";
269 reg = <0x40132000 0x7f>, /* MPU private access */
270 <0x49032000 0x7f>; /* L3 Interconnect */
271 reg-names = "mpu", "dma";
272 interrupts = <0 112 0x4>;
273 interrupt-parent = <&gic>;
274 ti,hwmods = "mcpdm";
275 };
276
277 dmic: dmic@4012e000 {
278 compatible = "ti,omap4-dmic";
279 reg = <0x4012e000 0x7f>, /* MPU private access */
280 <0x4902e000 0x7f>; /* L3 Interconnect */
281 reg-names = "mpu", "dma";
282 interrupts = <0 114 0x4>;
283 interrupt-parent = <&gic>;
284 ti,hwmods = "dmic";
285 };
286
287 mcbsp1: mcbsp@40122000 {
288 compatible = "ti,omap4-mcbsp";
289 reg = <0x40122000 0xff>, /* MPU private access */
290 <0x49022000 0xff>; /* L3 Interconnect */
291 reg-names = "mpu", "dma";
292 interrupts = <0 17 0x4>;
293 interrupt-names = "common";
294 interrupt-parent = <&gic>;
295 ti,buffer-size = <128>;
296 ti,hwmods = "mcbsp1";
297 };
298
299 mcbsp2: mcbsp@40124000 {
300 compatible = "ti,omap4-mcbsp";
301 reg = <0x40124000 0xff>, /* MPU private access */
302 <0x49024000 0xff>; /* L3 Interconnect */
303 reg-names = "mpu", "dma";
304 interrupts = <0 22 0x4>;
305 interrupt-names = "common";
306 interrupt-parent = <&gic>;
307 ti,buffer-size = <128>;
308 ti,hwmods = "mcbsp2";
309 };
310
311 mcbsp3: mcbsp@40126000 {
312 compatible = "ti,omap4-mcbsp";
313 reg = <0x40126000 0xff>, /* MPU private access */
314 <0x49026000 0xff>; /* L3 Interconnect */
315 reg-names = "mpu", "dma";
316 interrupts = <0 23 0x4>;
317 interrupt-names = "common";
318 interrupt-parent = <&gic>;
319 ti,buffer-size = <128>;
320 ti,hwmods = "mcbsp3";
321 };
183 }; 322 };
184}; 323};
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
index 802ec5b2fd00..90fdbd77f274 100644
--- a/arch/arm/boot/dts/phy3250.dts
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -135,13 +135,11 @@
135 ssp0: ssp@20084000 { 135 ssp0: ssp@20084000 {
136 #address-cells = <1>; 136 #address-cells = <1>;
137 #size-cells = <0>; 137 #size-cells = <0>;
138 pl022,num-chipselects = <1>; 138 num-cs = <1>;
139 cs-gpios = <&gpio 3 5 0>; 139 cs-gpios = <&gpio 3 5 0>;
140 140
141 eeprom: at25@0 { 141 eeprom: at25@0 {
142 pl022,hierarchy = <0>;
143 pl022,interface = <0>; 142 pl022,interface = <0>;
144 pl022,slave-tx-disable = <0>;
145 pl022,com-mode = <0>; 143 pl022,com-mode = <0>;
146 pl022,rx-level-trig = <1>; 144 pl022,rx-level-trig = <1>;
147 pl022,tx-level-trig = <1>; 145 pl022,tx-level-trig = <1>;
@@ -191,16 +189,14 @@
191 leds { 189 leds {
192 compatible = "gpio-leds"; 190 compatible = "gpio-leds";
193 191
194 led0 { 192 led0 { /* red */
195 gpios = <&gpio 5 1 1>; /* GPO_P3 1, GPIO 80, active low */ 193 gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
196 linux,default-trigger = "heartbeat";
197 default-state = "off"; 194 default-state = "off";
198 }; 195 };
199 196
200 led1 { 197 led1 { /* green */
201 gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ 198 gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
202 linux,default-trigger = "timer"; 199 linux,default-trigger = "heartbeat";
203 default-state = "off";
204 }; 200 };
205 }; 201 };
206}; 202};
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts
deleted file mode 100644
index 34ae3a64ba25..000000000000
--- a/arch/arm/boot/dts/prima2-cb.dts
+++ /dev/null
@@ -1,424 +0,0 @@
1/dts-v1/;
2/ {
3 model = "SiRF Prima2 eVB";
4 compatible = "sirf,prima2-cb", "sirf,prima2";
5 #address-cells = <1>;
6 #size-cells = <1>;
7 interrupt-parent = <&intc>;
8
9 memory {
10 reg = <0x00000000 0x20000000>;
11 };
12
13 chosen {
14 bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1";
15 linux,stdout-path = &uart1;
16 };
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu@0 {
23 reg = <0x0>;
24 d-cache-line-size = <32>;
25 i-cache-line-size = <32>;
26 d-cache-size = <32768>;
27 i-cache-size = <32768>;
28 /* from bootloader */
29 timebase-frequency = <0>;
30 bus-frequency = <0>;
31 clock-frequency = <0>;
32 };
33 };
34
35 axi {
36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 ranges = <0x40000000 0x40000000 0x80000000>;
40
41 l2-cache-controller@80040000 {
42 compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
43 reg = <0x80040000 0x1000>;
44 interrupts = <59>;
45 arm,tag-latency = <1 1 1>;
46 arm,data-latency = <1 1 1>;
47 arm,filter-ranges = <0 0x40000000>;
48 };
49
50 intc: interrupt-controller@80020000 {
51 #interrupt-cells = <1>;
52 interrupt-controller;
53 compatible = "sirf,prima2-intc";
54 reg = <0x80020000 0x1000>;
55 };
56
57 sys-iobg {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges = <0x88000000 0x88000000 0x40000>;
62
63 clock-controller@88000000 {
64 compatible = "sirf,prima2-clkc";
65 reg = <0x88000000 0x1000>;
66 interrupts = <3>;
67 };
68
69 reset-controller@88010000 {
70 compatible = "sirf,prima2-rstc";
71 reg = <0x88010000 0x1000>;
72 };
73
74 rsc-controller@88020000 {
75 compatible = "sirf,prima2-rsc";
76 reg = <0x88020000 0x1000>;
77 };
78 };
79
80 mem-iobg {
81 compatible = "simple-bus";
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges = <0x90000000 0x90000000 0x10000>;
85
86 memory-controller@90000000 {
87 compatible = "sirf,prima2-memc";
88 reg = <0x90000000 0x10000>;
89 interrupts = <27>;
90 };
91 };
92
93 disp-iobg {
94 compatible = "simple-bus";
95 #address-cells = <1>;
96 #size-cells = <1>;
97 ranges = <0x90010000 0x90010000 0x30000>;
98
99 display@90010000 {
100 compatible = "sirf,prima2-lcd";
101 reg = <0x90010000 0x20000>;
102 interrupts = <30>;
103 };
104
105 vpp@90020000 {
106 compatible = "sirf,prima2-vpp";
107 reg = <0x90020000 0x10000>;
108 interrupts = <31>;
109 };
110 };
111
112 graphics-iobg {
113 compatible = "simple-bus";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 ranges = <0x98000000 0x98000000 0x8000000>;
117
118 graphics@98000000 {
119 compatible = "powervr,sgx531";
120 reg = <0x98000000 0x8000000>;
121 interrupts = <6>;
122 };
123 };
124
125 multimedia-iobg {
126 compatible = "simple-bus";
127 #address-cells = <1>;
128 #size-cells = <1>;
129 ranges = <0xa0000000 0xa0000000 0x8000000>;
130
131 multimedia@a0000000 {
132 compatible = "sirf,prima2-video-codec";
133 reg = <0xa0000000 0x8000000>;
134 interrupts = <5>;
135 };
136 };
137
138 dsp-iobg {
139 compatible = "simple-bus";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges = <0xa8000000 0xa8000000 0x2000000>;
143
144 dspif@a8000000 {
145 compatible = "sirf,prima2-dspif";
146 reg = <0xa8000000 0x10000>;
147 interrupts = <9>;
148 };
149
150 gps@a8010000 {
151 compatible = "sirf,prima2-gps";
152 reg = <0xa8010000 0x10000>;
153 interrupts = <7>;
154 };
155
156 dsp@a9000000 {
157 compatible = "sirf,prima2-dsp";
158 reg = <0xa9000000 0x1000000>;
159 interrupts = <8>;
160 };
161 };
162
163 peri-iobg {
164 compatible = "simple-bus";
165 #address-cells = <1>;
166 #size-cells = <1>;
167 ranges = <0xb0000000 0xb0000000 0x180000>;
168
169 timer@b0020000 {
170 compatible = "sirf,prima2-tick";
171 reg = <0xb0020000 0x1000>;
172 interrupts = <0>;
173 };
174
175 nand@b0030000 {
176 compatible = "sirf,prima2-nand";
177 reg = <0xb0030000 0x10000>;
178 interrupts = <41>;
179 };
180
181 audio@b0040000 {
182 compatible = "sirf,prima2-audio";
183 reg = <0xb0040000 0x10000>;
184 interrupts = <35>;
185 };
186
187 uart0: uart@b0050000 {
188 cell-index = <0>;
189 compatible = "sirf,prima2-uart";
190 reg = <0xb0050000 0x10000>;
191 interrupts = <17>;
192 };
193
194 uart1: uart@b0060000 {
195 cell-index = <1>;
196 compatible = "sirf,prima2-uart";
197 reg = <0xb0060000 0x10000>;
198 interrupts = <18>;
199 };
200
201 uart2: uart@b0070000 {
202 cell-index = <2>;
203 compatible = "sirf,prima2-uart";
204 reg = <0xb0070000 0x10000>;
205 interrupts = <19>;
206 };
207
208 usp0: usp@b0080000 {
209 cell-index = <0>;
210 compatible = "sirf,prima2-usp";
211 reg = <0xb0080000 0x10000>;
212 interrupts = <20>;
213 };
214
215 usp1: usp@b0090000 {
216 cell-index = <1>;
217 compatible = "sirf,prima2-usp";
218 reg = <0xb0090000 0x10000>;
219 interrupts = <21>;
220 };
221
222 usp2: usp@b00a0000 {
223 cell-index = <2>;
224 compatible = "sirf,prima2-usp";
225 reg = <0xb00a0000 0x10000>;
226 interrupts = <22>;
227 };
228
229 dmac0: dma-controller@b00b0000 {
230 cell-index = <0>;
231 compatible = "sirf,prima2-dmac";
232 reg = <0xb00b0000 0x10000>;
233 interrupts = <12>;
234 };
235
236 dmac1: dma-controller@b0160000 {
237 cell-index = <1>;
238 compatible = "sirf,prima2-dmac";
239 reg = <0xb0160000 0x10000>;
240 interrupts = <13>;
241 };
242
243 vip@b00C0000 {
244 compatible = "sirf,prima2-vip";
245 reg = <0xb00C0000 0x10000>;
246 };
247
248 spi0: spi@b00d0000 {
249 cell-index = <0>;
250 compatible = "sirf,prima2-spi";
251 reg = <0xb00d0000 0x10000>;
252 interrupts = <15>;
253 };
254
255 spi1: spi@b0170000 {
256 cell-index = <1>;
257 compatible = "sirf,prima2-spi";
258 reg = <0xb0170000 0x10000>;
259 interrupts = <16>;
260 };
261
262 i2c0: i2c@b00e0000 {
263 cell-index = <0>;
264 compatible = "sirf,prima2-i2c";
265 reg = <0xb00e0000 0x10000>;
266 interrupts = <24>;
267 };
268
269 i2c1: i2c@b00f0000 {
270 cell-index = <1>;
271 compatible = "sirf,prima2-i2c";
272 reg = <0xb00f0000 0x10000>;
273 interrupts = <25>;
274 };
275
276 tsc@b0110000 {
277 compatible = "sirf,prima2-tsc";
278 reg = <0xb0110000 0x10000>;
279 interrupts = <33>;
280 };
281
282 gpio: gpio-controller@b0120000 {
283 #gpio-cells = <2>;
284 #interrupt-cells = <2>;
285 compatible = "sirf,prima2-gpio-pinmux";
286 reg = <0xb0120000 0x10000>;
287 gpio-controller;
288 interrupt-controller;
289 };
290
291 pwm@b0130000 {
292 compatible = "sirf,prima2-pwm";
293 reg = <0xb0130000 0x10000>;
294 };
295
296 efusesys@b0140000 {
297 compatible = "sirf,prima2-efuse";
298 reg = <0xb0140000 0x10000>;
299 };
300
301 pulsec@b0150000 {
302 compatible = "sirf,prima2-pulsec";
303 reg = <0xb0150000 0x10000>;
304 interrupts = <48>;
305 };
306
307 pci-iobg {
308 compatible = "sirf,prima2-pciiobg", "simple-bus";
309 #address-cells = <1>;
310 #size-cells = <1>;
311 ranges = <0x56000000 0x56000000 0x1b00000>;
312
313 sd0: sdhci@56000000 {
314 cell-index = <0>;
315 compatible = "sirf,prima2-sdhc";
316 reg = <0x56000000 0x100000>;
317 interrupts = <38>;
318 };
319
320 sd1: sdhci@56100000 {
321 cell-index = <1>;
322 compatible = "sirf,prima2-sdhc";
323 reg = <0x56100000 0x100000>;
324 interrupts = <38>;
325 };
326
327 sd2: sdhci@56200000 {
328 cell-index = <2>;
329 compatible = "sirf,prima2-sdhc";
330 reg = <0x56200000 0x100000>;
331 interrupts = <23>;
332 };
333
334 sd3: sdhci@56300000 {
335 cell-index = <3>;
336 compatible = "sirf,prima2-sdhc";
337 reg = <0x56300000 0x100000>;
338 interrupts = <23>;
339 };
340
341 sd4: sdhci@56400000 {
342 cell-index = <4>;
343 compatible = "sirf,prima2-sdhc";
344 reg = <0x56400000 0x100000>;
345 interrupts = <39>;
346 };
347
348 sd5: sdhci@56500000 {
349 cell-index = <5>;
350 compatible = "sirf,prima2-sdhc";
351 reg = <0x56500000 0x100000>;
352 interrupts = <39>;
353 };
354
355 pci-copy@57900000 {
356 compatible = "sirf,prima2-pcicp";
357 reg = <0x57900000 0x100000>;
358 interrupts = <40>;
359 };
360
361 rom-interface@57a00000 {
362 compatible = "sirf,prima2-romif";
363 reg = <0x57a00000 0x100000>;
364 };
365 };
366 };
367
368 rtc-iobg {
369 compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
370 #address-cells = <1>;
371 #size-cells = <1>;
372 reg = <0x80030000 0x10000>;
373
374 gpsrtc@1000 {
375 compatible = "sirf,prima2-gpsrtc";
376 reg = <0x1000 0x1000>;
377 interrupts = <55 56 57>;
378 };
379
380 sysrtc@2000 {
381 compatible = "sirf,prima2-sysrtc";
382 reg = <0x2000 0x1000>;
383 interrupts = <52 53 54>;
384 };
385
386 pwrc@3000 {
387 compatible = "sirf,prima2-pwrc";
388 reg = <0x3000 0x1000>;
389 interrupts = <32>;
390 };
391 };
392
393 uus-iobg {
394 compatible = "simple-bus";
395 #address-cells = <1>;
396 #size-cells = <1>;
397 ranges = <0xb8000000 0xb8000000 0x40000>;
398
399 usb0: usb@b00e0000 {
400 compatible = "chipidea,ci13611a-prima2";
401 reg = <0xb8000000 0x10000>;
402 interrupts = <10>;
403 };
404
405 usb1: usb@b00f0000 {
406 compatible = "chipidea,ci13611a-prima2";
407 reg = <0xb8010000 0x10000>;
408 interrupts = <11>;
409 };
410
411 sata@b00f0000 {
412 compatible = "synopsys,dwc-ahsata";
413 reg = <0xb8020000 0x10000>;
414 interrupts = <37>;
415 };
416
417 security@b00f0000 {
418 compatible = "sirf,prima2-security";
419 reg = <0xb8030000 0x10000>;
420 interrupts = <42>;
421 };
422 };
423 };
424};
diff --git a/arch/arm/boot/dts/prima2-evb.dts b/arch/arm/boot/dts/prima2-evb.dts
new file mode 100644
index 000000000000..57286b4e7b87
--- /dev/null
+++ b/arch/arm/boot/dts/prima2-evb.dts
@@ -0,0 +1,37 @@
1/*
2 * DTS file for CSR SiRFprimaII Evaluation Board
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/dts-v1/;
10
11/include/ "prima2.dtsi"
12
13/ {
14 model = "CSR SiRFprimaII Evaluation Board";
15 compatible = "sirf,prima2", "sirf,prima2-cb";
16
17 memory {
18 reg = <0x00000000 0x20000000>;
19 };
20
21 axi {
22 peri-iobg {
23 uart@b0060000 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart1_pins_a>;
26 };
27 spi@b00d0000 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&spi0_pins_a>;
30 };
31 spi@b0170000 {
32 pinctrl-names = "default";
33 pinctrl-0 = <&spi1_pins_a>;
34 };
35 };
36 };
37};
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
new file mode 100644
index 000000000000..055fca542120
--- /dev/null
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -0,0 +1,640 @@
1/*
2 * DTS file for CSR SiRFprimaII SoC
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/include/ "skeleton.dtsi"
10/ {
11 compatible = "sirf,prima2";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&intc>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 reg = <0x0>;
22 d-cache-line-size = <32>;
23 i-cache-line-size = <32>;
24 d-cache-size = <32768>;
25 i-cache-size = <32768>;
26 /* from bootloader */
27 timebase-frequency = <0>;
28 bus-frequency = <0>;
29 clock-frequency = <0>;
30 };
31 };
32
33 axi {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
37 ranges = <0x40000000 0x40000000 0x80000000>;
38
39 l2-cache-controller@80040000 {
40 compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
41 reg = <0x80040000 0x1000>;
42 interrupts = <59>;
43 arm,tag-latency = <1 1 1>;
44 arm,data-latency = <1 1 1>;
45 arm,filter-ranges = <0 0x40000000>;
46 };
47
48 intc: interrupt-controller@80020000 {
49 #interrupt-cells = <1>;
50 interrupt-controller;
51 compatible = "sirf,prima2-intc";
52 reg = <0x80020000 0x1000>;
53 };
54
55 sys-iobg {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges = <0x88000000 0x88000000 0x40000>;
60
61 clock-controller@88000000 {
62 compatible = "sirf,prima2-clkc";
63 reg = <0x88000000 0x1000>;
64 interrupts = <3>;
65 };
66
67 reset-controller@88010000 {
68 compatible = "sirf,prima2-rstc";
69 reg = <0x88010000 0x1000>;
70 };
71
72 rsc-controller@88020000 {
73 compatible = "sirf,prima2-rsc";
74 reg = <0x88020000 0x1000>;
75 };
76 };
77
78 mem-iobg {
79 compatible = "simple-bus";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 ranges = <0x90000000 0x90000000 0x10000>;
83
84 memory-controller@90000000 {
85 compatible = "sirf,prima2-memc";
86 reg = <0x90000000 0x10000>;
87 interrupts = <27>;
88 };
89 };
90
91 disp-iobg {
92 compatible = "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0x90010000 0x90010000 0x30000>;
96
97 display@90010000 {
98 compatible = "sirf,prima2-lcd";
99 reg = <0x90010000 0x20000>;
100 interrupts = <30>;
101 };
102
103 vpp@90020000 {
104 compatible = "sirf,prima2-vpp";
105 reg = <0x90020000 0x10000>;
106 interrupts = <31>;
107 };
108 };
109
110 graphics-iobg {
111 compatible = "simple-bus";
112 #address-cells = <1>;
113 #size-cells = <1>;
114 ranges = <0x98000000 0x98000000 0x8000000>;
115
116 graphics@98000000 {
117 compatible = "powervr,sgx531";
118 reg = <0x98000000 0x8000000>;
119 interrupts = <6>;
120 };
121 };
122
123 multimedia-iobg {
124 compatible = "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 ranges = <0xa0000000 0xa0000000 0x8000000>;
128
129 multimedia@a0000000 {
130 compatible = "sirf,prima2-video-codec";
131 reg = <0xa0000000 0x8000000>;
132 interrupts = <5>;
133 };
134 };
135
136 dsp-iobg {
137 compatible = "simple-bus";
138 #address-cells = <1>;
139 #size-cells = <1>;
140 ranges = <0xa8000000 0xa8000000 0x2000000>;
141
142 dspif@a8000000 {
143 compatible = "sirf,prima2-dspif";
144 reg = <0xa8000000 0x10000>;
145 interrupts = <9>;
146 };
147
148 gps@a8010000 {
149 compatible = "sirf,prima2-gps";
150 reg = <0xa8010000 0x10000>;
151 interrupts = <7>;
152 };
153
154 dsp@a9000000 {
155 compatible = "sirf,prima2-dsp";
156 reg = <0xa9000000 0x1000000>;
157 interrupts = <8>;
158 };
159 };
160
161 peri-iobg {
162 compatible = "simple-bus";
163 #address-cells = <1>;
164 #size-cells = <1>;
165 ranges = <0xb0000000 0xb0000000 0x180000>;
166
167 timer@b0020000 {
168 compatible = "sirf,prima2-tick";
169 reg = <0xb0020000 0x1000>;
170 interrupts = <0>;
171 };
172
173 nand@b0030000 {
174 compatible = "sirf,prima2-nand";
175 reg = <0xb0030000 0x10000>;
176 interrupts = <41>;
177 };
178
179 audio@b0040000 {
180 compatible = "sirf,prima2-audio";
181 reg = <0xb0040000 0x10000>;
182 interrupts = <35>;
183 };
184
185 uart0: uart@b0050000 {
186 cell-index = <0>;
187 compatible = "sirf,prima2-uart";
188 reg = <0xb0050000 0x10000>;
189 interrupts = <17>;
190 };
191
192 uart1: uart@b0060000 {
193 cell-index = <1>;
194 compatible = "sirf,prima2-uart";
195 reg = <0xb0060000 0x10000>;
196 interrupts = <18>;
197 };
198
199 uart2: uart@b0070000 {
200 cell-index = <2>;
201 compatible = "sirf,prima2-uart";
202 reg = <0xb0070000 0x10000>;
203 interrupts = <19>;
204 };
205
206 usp0: usp@b0080000 {
207 cell-index = <0>;
208 compatible = "sirf,prima2-usp";
209 reg = <0xb0080000 0x10000>;
210 interrupts = <20>;
211 };
212
213 usp1: usp@b0090000 {
214 cell-index = <1>;
215 compatible = "sirf,prima2-usp";
216 reg = <0xb0090000 0x10000>;
217 interrupts = <21>;
218 };
219
220 usp2: usp@b00a0000 {
221 cell-index = <2>;
222 compatible = "sirf,prima2-usp";
223 reg = <0xb00a0000 0x10000>;
224 interrupts = <22>;
225 };
226
227 dmac0: dma-controller@b00b0000 {
228 cell-index = <0>;
229 compatible = "sirf,prima2-dmac";
230 reg = <0xb00b0000 0x10000>;
231 interrupts = <12>;
232 };
233
234 dmac1: dma-controller@b0160000 {
235 cell-index = <1>;
236 compatible = "sirf,prima2-dmac";
237 reg = <0xb0160000 0x10000>;
238 interrupts = <13>;
239 };
240
241 vip@b00C0000 {
242 compatible = "sirf,prima2-vip";
243 reg = <0xb00C0000 0x10000>;
244 };
245
246 spi0: spi@b00d0000 {
247 cell-index = <0>;
248 compatible = "sirf,prima2-spi";
249 reg = <0xb00d0000 0x10000>;
250 interrupts = <15>;
251 };
252
253 spi1: spi@b0170000 {
254 cell-index = <1>;
255 compatible = "sirf,prima2-spi";
256 reg = <0xb0170000 0x10000>;
257 interrupts = <16>;
258 };
259
260 i2c0: i2c@b00e0000 {
261 cell-index = <0>;
262 compatible = "sirf,prima2-i2c";
263 reg = <0xb00e0000 0x10000>;
264 interrupts = <24>;
265 };
266
267 i2c1: i2c@b00f0000 {
268 cell-index = <1>;
269 compatible = "sirf,prima2-i2c";
270 reg = <0xb00f0000 0x10000>;
271 interrupts = <25>;
272 };
273
274 tsc@b0110000 {
275 compatible = "sirf,prima2-tsc";
276 reg = <0xb0110000 0x10000>;
277 interrupts = <33>;
278 };
279
280 gpio: pinctrl@b0120000 {
281 #gpio-cells = <2>;
282 #interrupt-cells = <2>;
283 compatible = "sirf,prima2-pinctrl";
284 reg = <0xb0120000 0x10000>;
285 interrupts = <43 44 45 46 47>;
286 gpio-controller;
287 interrupt-controller;
288
289 lcd_16pins_a: lcd0@0 {
290 lcd {
291 sirf,pins = "lcd_16bitsgrp";
292 sirf,function = "lcd_16bits";
293 };
294 };
295 lcd_18pins_a: lcd0@1 {
296 lcd {
297 sirf,pins = "lcd_18bitsgrp";
298 sirf,function = "lcd_18bits";
299 };
300 };
301 lcd_24pins_a: lcd0@2 {
302 lcd {
303 sirf,pins = "lcd_24bitsgrp";
304 sirf,function = "lcd_24bits";
305 };
306 };
307 lcdrom_pins_a: lcdrom0@0 {
308 lcd {
309 sirf,pins = "lcdromgrp";
310 sirf,function = "lcdrom";
311 };
312 };
313 uart0_pins_a: uart0@0 {
314 uart {
315 sirf,pins = "uart0grp";
316 sirf,function = "uart0";
317 };
318 };
319 uart1_pins_a: uart1@0 {
320 uart {
321 sirf,pins = "uart1grp";
322 sirf,function = "uart1";
323 };
324 };
325 uart2_pins_a: uart2@0 {
326 uart {
327 sirf,pins = "uart2grp";
328 sirf,function = "uart2";
329 };
330 };
331 uart2_noflow_pins_a: uart2@1 {
332 uart {
333 sirf,pins = "uart2_nostreamctrlgrp";
334 sirf,function = "uart2_nostreamctrl";
335 };
336 };
337 spi0_pins_a: spi0@0 {
338 spi {
339 sirf,pins = "spi0grp";
340 sirf,function = "spi0";
341 };
342 };
343 spi1_pins_a: spi1@0 {
344 spi {
345 sirf,pins = "spi1grp";
346 sirf,function = "spi1";
347 };
348 };
349 i2c0_pins_a: i2c0@0 {
350 i2c {
351 sirf,pins = "i2c0grp";
352 sirf,function = "i2c0";
353 };
354 };
355 i2c1_pins_a: i2c1@0 {
356 i2c {
357 sirf,pins = "i2c1grp";
358 sirf,function = "i2c1";
359 };
360 };
361 pwm0_pins_a: pwm0@0 {
362 pwm {
363 sirf,pins = "pwm0grp";
364 sirf,function = "pwm0";
365 };
366 };
367 pwm1_pins_a: pwm1@0 {
368 pwm {
369 sirf,pins = "pwm1grp";
370 sirf,function = "pwm1";
371 };
372 };
373 pwm2_pins_a: pwm2@0 {
374 pwm {
375 sirf,pins = "pwm2grp";
376 sirf,function = "pwm2";
377 };
378 };
379 pwm3_pins_a: pwm3@0 {
380 pwm {
381 sirf,pins = "pwm3grp";
382 sirf,function = "pwm3";
383 };
384 };
385 gps_pins_a: gps@0 {
386 gps {
387 sirf,pins = "gpsgrp";
388 sirf,function = "gps";
389 };
390 };
391 vip_pins_a: vip@0 {
392 vip {
393 sirf,pins = "vipgrp";
394 sirf,function = "vip";
395 };
396 };
397 sdmmc0_pins_a: sdmmc0@0 {
398 sdmmc0 {
399 sirf,pins = "sdmmc0grp";
400 sirf,function = "sdmmc0";
401 };
402 };
403 sdmmc1_pins_a: sdmmc1@0 {
404 sdmmc1 {
405 sirf,pins = "sdmmc1grp";
406 sirf,function = "sdmmc1";
407 };
408 };
409 sdmmc2_pins_a: sdmmc2@0 {
410 sdmmc2 {
411 sirf,pins = "sdmmc2grp";
412 sirf,function = "sdmmc2";
413 };
414 };
415 sdmmc3_pins_a: sdmmc3@0 {
416 sdmmc3 {
417 sirf,pins = "sdmmc3grp";
418 sirf,function = "sdmmc3";
419 };
420 };
421 sdmmc4_pins_a: sdmmc4@0 {
422 sdmmc4 {
423 sirf,pins = "sdmmc4grp";
424 sirf,function = "sdmmc4";
425 };
426 };
427 sdmmc5_pins_a: sdmmc5@0 {
428 sdmmc5 {
429 sirf,pins = "sdmmc5grp";
430 sirf,function = "sdmmc5";
431 };
432 };
433 i2s_pins_a: i2s@0 {
434 i2s {
435 sirf,pins = "i2sgrp";
436 sirf,function = "i2s";
437 };
438 };
439 ac97_pins_a: ac97@0 {
440 ac97 {
441 sirf,pins = "ac97grp";
442 sirf,function = "ac97";
443 };
444 };
445 nand_pins_a: nand@0 {
446 nand {
447 sirf,pins = "nandgrp";
448 sirf,function = "nand";
449 };
450 };
451 usp0_pins_a: usp0@0 {
452 usp0 {
453 sirf,pins = "usp0grp";
454 sirf,function = "usp0";
455 };
456 };
457 usp1_pins_a: usp1@0 {
458 usp1 {
459 sirf,pins = "usp1grp";
460 sirf,function = "usp1";
461 };
462 };
463 usp2_pins_a: usp2@0 {
464 usp2 {
465 sirf,pins = "usp2grp";
466 sirf,function = "usp2";
467 };
468 };
469 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
470 usb0_utmi_drvbus {
471 sirf,pins = "usb0_utmi_drvbusgrp";
472 sirf,function = "usb0_utmi_drvbus";
473 };
474 };
475 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
476 usb1_utmi_drvbus {
477 sirf,pins = "usb1_utmi_drvbusgrp";
478 sirf,function = "usb1_utmi_drvbus";
479 };
480 };
481 warm_rst_pins_a: warm_rst@0 {
482 warm_rst {
483 sirf,pins = "warm_rstgrp";
484 sirf,function = "warm_rst";
485 };
486 };
487 pulse_count_pins_a: pulse_count@0 {
488 pulse_count {
489 sirf,pins = "pulse_countgrp";
490 sirf,function = "pulse_count";
491 };
492 };
493 cko0_rst_pins_a: cko0_rst@0 {
494 cko0_rst {
495 sirf,pins = "cko0_rstgrp";
496 sirf,function = "cko0_rst";
497 };
498 };
499 cko1_rst_pins_a: cko1_rst@0 {
500 cko1_rst {
501 sirf,pins = "cko1_rstgrp";
502 sirf,function = "cko1_rst";
503 };
504 };
505 };
506
507 pwm@b0130000 {
508 compatible = "sirf,prima2-pwm";
509 reg = <0xb0130000 0x10000>;
510 };
511
512 efusesys@b0140000 {
513 compatible = "sirf,prima2-efuse";
514 reg = <0xb0140000 0x10000>;
515 };
516
517 pulsec@b0150000 {
518 compatible = "sirf,prima2-pulsec";
519 reg = <0xb0150000 0x10000>;
520 interrupts = <48>;
521 };
522
523 pci-iobg {
524 compatible = "sirf,prima2-pciiobg", "simple-bus";
525 #address-cells = <1>;
526 #size-cells = <1>;
527 ranges = <0x56000000 0x56000000 0x1b00000>;
528
529 sd0: sdhci@56000000 {
530 cell-index = <0>;
531 compatible = "sirf,prima2-sdhc";
532 reg = <0x56000000 0x100000>;
533 interrupts = <38>;
534 };
535
536 sd1: sdhci@56100000 {
537 cell-index = <1>;
538 compatible = "sirf,prima2-sdhc";
539 reg = <0x56100000 0x100000>;
540 interrupts = <38>;
541 };
542
543 sd2: sdhci@56200000 {
544 cell-index = <2>;
545 compatible = "sirf,prima2-sdhc";
546 reg = <0x56200000 0x100000>;
547 interrupts = <23>;
548 };
549
550 sd3: sdhci@56300000 {
551 cell-index = <3>;
552 compatible = "sirf,prima2-sdhc";
553 reg = <0x56300000 0x100000>;
554 interrupts = <23>;
555 };
556
557 sd4: sdhci@56400000 {
558 cell-index = <4>;
559 compatible = "sirf,prima2-sdhc";
560 reg = <0x56400000 0x100000>;
561 interrupts = <39>;
562 };
563
564 sd5: sdhci@56500000 {
565 cell-index = <5>;
566 compatible = "sirf,prima2-sdhc";
567 reg = <0x56500000 0x100000>;
568 interrupts = <39>;
569 };
570
571 pci-copy@57900000 {
572 compatible = "sirf,prima2-pcicp";
573 reg = <0x57900000 0x100000>;
574 interrupts = <40>;
575 };
576
577 rom-interface@57a00000 {
578 compatible = "sirf,prima2-romif";
579 reg = <0x57a00000 0x100000>;
580 };
581 };
582 };
583
584 rtc-iobg {
585 compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
586 #address-cells = <1>;
587 #size-cells = <1>;
588 reg = <0x80030000 0x10000>;
589
590 gpsrtc@1000 {
591 compatible = "sirf,prima2-gpsrtc";
592 reg = <0x1000 0x1000>;
593 interrupts = <55 56 57>;
594 };
595
596 sysrtc@2000 {
597 compatible = "sirf,prima2-sysrtc";
598 reg = <0x2000 0x1000>;
599 interrupts = <52 53 54>;
600 };
601
602 pwrc@3000 {
603 compatible = "sirf,prima2-pwrc";
604 reg = <0x3000 0x1000>;
605 interrupts = <32>;
606 };
607 };
608
609 uus-iobg {
610 compatible = "simple-bus";
611 #address-cells = <1>;
612 #size-cells = <1>;
613 ranges = <0xb8000000 0xb8000000 0x40000>;
614
615 usb0: usb@b00e0000 {
616 compatible = "chipidea,ci13611a-prima2";
617 reg = <0xb8000000 0x10000>;
618 interrupts = <10>;
619 };
620
621 usb1: usb@b00f0000 {
622 compatible = "chipidea,ci13611a-prima2";
623 reg = <0xb8010000 0x10000>;
624 interrupts = <11>;
625 };
626
627 sata@b00f0000 {
628 compatible = "synopsys,dwc-ahsata";
629 reg = <0xb8020000 0x10000>;
630 interrupts = <37>;
631 };
632
633 security@b00f0000 {
634 compatible = "sirf,prima2-security";
635 reg = <0xb8030000 0x10000>;
636 interrupts = <42>;
637 };
638 };
639 };
640};
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
new file mode 100644
index 000000000000..d7c5d721a5c7
--- /dev/null
+++ b/arch/arm/boot/dts/pxa27x.dtsi
@@ -0,0 +1,14 @@
1/* The pxa3xx skeleton simply augments the 2xx version */
2/include/ "pxa2xx.dtsi"
3
4/ {
5 model = "Marvell PXA27x familiy SoC";
6 compatible = "marvell,pxa27x";
7
8 pxabus {
9 pxairq: interrupt-controller@40d00000 {
10 marvell,intc-priority;
11 marvell,intc-nr-irqs = <34>;
12 };
13 };
14};
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
new file mode 100644
index 000000000000..f18aad35e8b3
--- /dev/null
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -0,0 +1,132 @@
1/*
2 * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC
3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 model = "Marvell PXA2xx family SoC";
13 compatible = "marvell,pxa2xx";
14 interrupt-parent = <&pxairq>;
15
16 aliases {
17 serial0 = &ffuart;
18 serial1 = &btuart;
19 serial2 = &stuart;
20 serial3 = &hwuart;
21 i2c0 = &pwri2c;
22 i2c1 = &pxai2c1;
23 };
24
25 cpus {
26 cpu@0 {
27 compatible = "arm,xscale";
28 };
29 };
30
31 pxabus {
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <1>;
35 ranges;
36
37 pxairq: interrupt-controller@40d00000 {
38 #interrupt-cells = <1>;
39 compatible = "marvell,pxa-intc";
40 interrupt-controller;
41 interrupt-parent;
42 marvell,intc-nr-irqs = <32>;
43 reg = <0x40d00000 0xd0>;
44 };
45
46 gpio: gpio@40e00000 {
47 compatible = "mrvl,pxa-gpio";
48 #address-cells = <0x1>;
49 #size-cells = <0x1>;
50 reg = <0x40e00000 0x10000>;
51 gpio-controller;
52 #gpio-cells = <0x2>;
53 interrupts = <10>;
54 interrupt-names = "gpio_mux";
55 interrupt-controller;
56 #interrupt-cells = <0x2>;
57 ranges;
58
59 gcb0: gpio@40e00000 {
60 reg = <0x40e00000 0x4>;
61 };
62
63 gcb1: gpio@40e00004 {
64 reg = <0x40e00004 0x4>;
65 };
66
67 gcb2: gpio@40e00008 {
68 reg = <0x40e00008 0x4>;
69 };
70 gcb3: gpio@40e0000c {
71 reg = <0x40e0000c 0x4>;
72 };
73 };
74
75 ffuart: uart@40100000 {
76 compatible = "mrvl,pxa-uart";
77 reg = <0x40100000 0x30>;
78 interrupts = <22>;
79 status = "disabled";
80 };
81
82 btuart: uart@40200000 {
83 compatible = "mrvl,pxa-uart";
84 reg = <0x40200000 0x30>;
85 interrupts = <21>;
86 status = "disabled";
87 };
88
89 stuart: uart@40700000 {
90 compatible = "mrvl,pxa-uart";
91 reg = <0x40700000 0x30>;
92 interrupts = <20>;
93 status = "disabled";
94 };
95
96 hwuart: uart@41100000 {
97 compatible = "mrvl,pxa-uart";
98 reg = <0x41100000 0x30>;
99 interrupts = <7>;
100 status = "disabled";
101 };
102
103 pxai2c1: i2c@40301680 {
104 compatible = "mrvl,pxa-i2c";
105 reg = <0x40301680 0x30>;
106 interrupts = <18>;
107 #address-cells = <0x1>;
108 #size-cells = <0>;
109 status = "disabled";
110 };
111
112 usb0: ohci@4c000000 {
113 compatible = "mrvl,pxa-ohci";
114 reg = <0x4c000000 0x10000>;
115 interrupts = <3>;
116 status = "disabled";
117 };
118
119 mmc0: mmc@41100000 {
120 compatible = "mrvl,pxa-mmc";
121 reg = <0x41100000 0x1000>;
122 interrupts = <23>;
123 status = "disabled";
124 };
125
126 rtc@40900000 {
127 compatible = "marvell,pxa-rtc";
128 reg = <0x40900000 0x3c>;
129 interrupts = <30 31>;
130 };
131 };
132};
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi
new file mode 100644
index 000000000000..f9d92da86783
--- /dev/null
+++ b/arch/arm/boot/dts/pxa3xx.dtsi
@@ -0,0 +1,32 @@
1/* The pxa3xx skeleton simply augments the 2xx version */
2/include/ "pxa2xx.dtsi"
3
4/ {
5 model = "Marvell PXA3xx familiy SoC";
6 compatible = "marvell,pxa3xx";
7
8 pxabus {
9 pwri2c: i2c@40f500c0 {
10 compatible = "mrvl,pwri2c";
11 reg = <0x40f500c0 0x30>;
12 interrupts = <6>;
13 #address-cells = <0x1>;
14 #size-cells = <0>;
15 status = "disabled";
16 };
17
18 nand0: nand@43100000 {
19 compatible = "marvell,pxa3xx-nand";
20 reg = <0x43100000 90>;
21 interrupts = <45>;
22 #address-cells = <1>;
23 #size-cells = <1>;
24 status = "disabled";
25 };
26
27 pxairq: interrupt-controller@40d00000 {
28 marvell,intc-priority;
29 marvell,intc-nr-irqs = <56>;
30 };
31 };
32};
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index aebf32de73b4..a3be44d86bcd 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -25,6 +25,11 @@
25 interrupt-parent = <&intc>; 25 interrupt-parent = <&intc>;
26 ranges; 26 ranges;
27 27
28 L2: l2-cache {
29 compatible = "marvell,tauros2-cache";
30 marvell,tauros2-cache-features = <0x3>;
31 };
32
28 axi@d4200000 { /* AXI */ 33 axi@d4200000 { /* AXI */
29 compatible = "mrvl,axi-bus", "simple-bus"; 34 compatible = "mrvl,axi-bus", "simple-bus";
30 #address-cells = <1>; 35 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index 7e334d4cae21..702c0baa6004 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "db8500.dtsi" 13/include/ "dbx5x0.dtsi"
14 14
15/ { 15/ {
16 model = "Calao Systems Snowball platform with device tree"; 16 model = "Calao Systems Snowball platform with device tree";
@@ -83,6 +83,22 @@
83 }; 83 };
84 84
85 soc-u9500 { 85 soc-u9500 {
86
87 sound {
88 compatible = "stericsson,snd-soc-mop500";
89
90 stericsson,cpu-dai = <&msp1 &msp3>;
91 stericsson,audio-codec = <&codec>;
92 };
93
94 msp1: msp@80124000 {
95 status = "okay";
96 };
97
98 msp3: msp@80125000 {
99 status = "okay";
100 };
101
86 external-bus@50000000 { 102 external-bus@50000000 {
87 status = "okay"; 103 status = "okay";
88 104
@@ -111,7 +127,6 @@
111 mmc-cap-mmc-highspeed; 127 mmc-cap-mmc-highspeed;
112 vmmc-supply = <&ab8500_ldo_aux3_reg>; 128 vmmc-supply = <&ab8500_ldo_aux3_reg>;
113 129
114 #gpio-cells = <1>;
115 cd-gpios = <&gpio6 26 0x4>; // 218 130 cd-gpios = <&gpio6 26 0x4>; // 218
116 cd-inverted; 131 cd-inverted;
117 132
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
new file mode 100644
index 000000000000..a2d6d6541f83
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -0,0 +1,58 @@
1/dts-v1/;
2
3/include/ "tegra20-tamonten.dtsi"
4
5/ {
6 model = "Avionic Design Medcom-Wide board";
7 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
8
9 i2c@7000c000 {
10 wm8903: wm8903@1a {
11 compatible = "wlf,wm8903";
12 reg = <0x1a>;
13 interrupt-parent = <&gpio>;
14 interrupts = <187 0x04>;
15
16 gpio-controller;
17 #gpio-cells = <2>;
18
19 micdet-cfg = <0>;
20 micdet-delay = <100>;
21 gpio-cfg = <0xffffffff
22 0xffffffff
23 0
24 0xffffffff
25 0xffffffff>;
26 };
27 };
28
29 backlight {
30 compatible = "pwm-backlight";
31 pwms = <&pwm 0 5000000>;
32
33 brightness-levels = <0 4 8 16 32 64 128 255>;
34 default-brightness-level = <6>;
35 };
36
37 sound {
38 compatible = "ad,tegra-audio-wm8903-medcom-wide",
39 "nvidia,tegra-audio-wm8903";
40 nvidia,model = "Avionic Design Medcom-Wide";
41
42 nvidia,audio-routing =
43 "Headphone Jack", "HPOUTR",
44 "Headphone Jack", "HPOUTL",
45 "Int Spk", "ROP",
46 "Int Spk", "RON",
47 "Int Spk", "LOP",
48 "Int Spk", "LON",
49 "Mic Jack", "MICBIAS",
50 "IN1L", "Mic Jack";
51
52 nvidia,i2s-controller = <&tegra_i2s1>;
53 nvidia,audio-codec = <&wm8903>;
54
55 nvidia,spkr-en-gpios = <&wm8903 2 0>;
56 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
57 };
58};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 684a9e1ff7e9..ddf287f52d49 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -272,12 +272,170 @@
272 status = "okay"; 272 status = "okay";
273 clock-frequency = <400000>; 273 clock-frequency = <400000>;
274 274
275 pmic: tps6586x@34 {
276 compatible = "ti,tps6586x";
277 reg = <0x34>;
278 interrupts = <0 86 0x4>;
279
280 #gpio-cells = <2>;
281 gpio-controller;
282
283 sys-supply = <&p5valw_reg>;
284 vin-sm0-supply = <&sys_reg>;
285 vin-sm1-supply = <&sys_reg>;
286 vin-sm2-supply = <&sys_reg>;
287 vinldo01-supply = <&sm2_reg>;
288 vinldo23-supply = <&sm2_reg>;
289 vinldo4-supply = <&sm2_reg>;
290 vinldo678-supply = <&sm2_reg>;
291 vinldo9-supply = <&sm2_reg>;
292
293 regulators {
294 #address-cells = <1>;
295 #size-cells = <0>;
296
297 sys_reg: regulator@0 {
298 reg = <0>;
299 regulator-compatible = "sys";
300 regulator-name = "vdd_sys";
301 regulator-always-on;
302 };
303
304 regulator@1 {
305 reg = <1>;
306 regulator-compatible = "sm0";
307 regulator-name = "+1.2vs_sm0,vdd_core";
308 regulator-min-microvolt = <1200000>;
309 regulator-max-microvolt = <1200000>;
310 regulator-always-on;
311 };
312
313 regulator@2 {
314 reg = <2>;
315 regulator-compatible = "sm1";
316 regulator-name = "+1.0vs_sm1,vdd_cpu";
317 regulator-min-microvolt = <1000000>;
318 regulator-max-microvolt = <1000000>;
319 regulator-always-on;
320 };
321
322 sm2_reg: regulator@3 {
323 reg = <3>;
324 regulator-compatible = "sm2";
325 regulator-name = "+3.7vs_sm2,vin_ldo*";
326 regulator-min-microvolt = <3700000>;
327 regulator-max-microvolt = <3700000>;
328 regulator-always-on;
329 };
330
331 /* LDO0 is not connected to anything */
332
333 regulator@5 {
334 reg = <5>;
335 regulator-compatible = "ldo1";
336 regulator-name = "+1.1vs_ldo1,avdd_pll*";
337 regulator-min-microvolt = <1100000>;
338 regulator-max-microvolt = <1100000>;
339 regulator-always-on;
340 };
341
342 regulator@6 {
343 reg = <6>;
344 regulator-compatible = "ldo2";
345 regulator-name = "+1.2vs_ldo2,vdd_rtc";
346 regulator-min-microvolt = <1200000>;
347 regulator-max-microvolt = <1200000>;
348 };
349
350 regulator@7 {
351 reg = <7>;
352 regulator-compatible = "ldo3";
353 regulator-name = "+3.3vs_ldo3,avdd_usb*";
354 regulator-min-microvolt = <3300000>;
355 regulator-max-microvolt = <3300000>;
356 regulator-always-on;
357 };
358
359 regulator@8 {
360 reg = <8>;
361 regulator-compatible = "ldo4";
362 regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
363 regulator-min-microvolt = <1800000>;
364 regulator-max-microvolt = <1800000>;
365 regulator-always-on;
366 };
367
368 regulator@9 {
369 reg = <9>;
370 regulator-compatible = "ldo5";
371 regulator-name = "+2.85vs_ldo5,vcore_mmc";
372 regulator-min-microvolt = <2850000>;
373 regulator-max-microvolt = <2850000>;
374 regulator-always-on;
375 };
376
377 regulator@10 {
378 reg = <10>;
379 regulator-compatible = "ldo6";
380 /*
381 * Research indicates this should be
382 * 1.8v; other boards that use this
383 * rail for the same purpose need it
384 * set to 1.8v. The schematic signal
385 * name is incorrect; perhaps copied
386 * from an incorrect NVIDIA reference.
387 */
388 regulator-name = "+2.85vs_ldo6,avdd_vdac";
389 regulator-min-microvolt = <1800000>;
390 regulator-max-microvolt = <1800000>;
391 };
392
393 regulator@11 {
394 reg = <11>;
395 regulator-compatible = "ldo7";
396 regulator-name = "+3.3vs_ldo7,avdd_hdmi";
397 regulator-min-microvolt = <3300000>;
398 regulator-max-microvolt = <3300000>;
399 };
400
401 regulator@12 {
402 reg = <12>;
403 regulator-compatible = "ldo8";
404 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
405 regulator-min-microvolt = <1800000>;
406 regulator-max-microvolt = <1800000>;
407 };
408
409 regulator@13 {
410 reg = <13>;
411 regulator-compatible = "ldo9";
412 regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
413 regulator-min-microvolt = <2850000>;
414 regulator-max-microvolt = <2850000>;
415 regulator-always-on;
416 };
417
418 regulator@14 {
419 reg = <14>;
420 regulator-compatible = "ldo_rtc";
421 regulator-name = "+3.3vs_rtc";
422 regulator-min-microvolt = <3300000>;
423 regulator-max-microvolt = <3300000>;
424 regulator-always-on;
425 };
426 };
427 };
428
275 adt7461@4c { 429 adt7461@4c {
276 compatible = "adi,adt7461"; 430 compatible = "adi,adt7461";
277 reg = <0x4c>; 431 reg = <0x4c>;
278 }; 432 };
279 }; 433 };
280 434
435 pmc {
436 nvidia,invert-interrupt;
437 };
438
281 usb@c5000000 { 439 usb@c5000000 {
282 status = "okay"; 440 status = "okay";
283 }; 441 };
@@ -325,6 +483,21 @@
325 }; 483 };
326 }; 484 };
327 485
486 regulators {
487 compatible = "simple-bus";
488 #address-cells = <1>;
489 #size-cells = <0>;
490
491 p5valw_reg: regulator@0 {
492 compatible = "regulator-fixed";
493 reg = <0>;
494 regulator-name = "+5valw";
495 regulator-min-microvolt = <5000000>;
496 regulator-max-microvolt = <5000000>;
497 regulator-always-on;
498 };
499 };
500
328 sound { 501 sound {
329 compatible = "nvidia,tegra-audio-alc5632-paz00", 502 compatible = "nvidia,tegra-audio-alc5632-paz00",
330 "nvidia,tegra-audio-alc5632"; 503 "nvidia,tegra-audio-alc5632";
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
new file mode 100644
index 000000000000..331a3ef24d59
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -0,0 +1,50 @@
1/dts-v1/;
2
3/include/ "tegra20-tamonten.dtsi"
4
5/ {
6 model = "Avionic Design Plutux board";
7 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
8
9 i2c@7000c000 {
10 wm8903: wm8903@1a {
11 compatible = "wlf,wm8903";
12 reg = <0x1a>;
13 interrupt-parent = <&gpio>;
14 interrupts = <187 0x04>;
15
16 gpio-controller;
17 #gpio-cells = <2>;
18
19 micdet-cfg = <0>;
20 micdet-delay = <100>;
21 gpio-cfg = <0xffffffff
22 0xffffffff
23 0
24 0xffffffff
25 0xffffffff>;
26 };
27 };
28
29 sound {
30 compatible = "ad,tegra-audio-plutux",
31 "nvidia,tegra-audio-wm8903";
32 nvidia,model = "Avionic Design Plutux";
33
34 nvidia,audio-routing =
35 "Headphone Jack", "HPOUTR",
36 "Headphone Jack", "HPOUTL",
37 "Int Spk", "ROP",
38 "Int Spk", "RON",
39 "Int Spk", "LOP",
40 "Int Spk", "LON",
41 "Mic Jack", "MICBIAS",
42 "IN1L", "Mic Jack";
43
44 nvidia,i2s-controller = <&tegra_i2s1>;
45 nvidia,audio-codec = <&wm8903>;
46
47 nvidia,spkr-en-gpios = <&wm8903 2 0>;
48 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
49 };
50};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 85e621ab2968..e60dc7124e92 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -374,6 +374,154 @@
374 status = "okay"; 374 status = "okay";
375 clock-frequency = <400000>; 375 clock-frequency = <400000>;
376 376
377 pmic: tps6586x@34 {
378 compatible = "ti,tps6586x";
379 reg = <0x34>;
380 interrupts = <0 86 0x4>;
381
382 ti,system-power-controller;
383
384 #gpio-cells = <2>;
385 gpio-controller;
386
387 sys-supply = <&vdd_5v0_reg>;
388 vin-sm0-supply = <&sys_reg>;
389 vin-sm1-supply = <&sys_reg>;
390 vin-sm2-supply = <&sys_reg>;
391 vinldo01-supply = <&sm2_reg>;
392 vinldo23-supply = <&sm2_reg>;
393 vinldo4-supply = <&sm2_reg>;
394 vinldo678-supply = <&sm2_reg>;
395 vinldo9-supply = <&sm2_reg>;
396
397 regulators {
398 #address-cells = <1>;
399 #size-cells = <0>;
400
401 sys_reg: regulator@0 {
402 reg = <0>;
403 regulator-compatible = "sys";
404 regulator-name = "vdd_sys";
405 regulator-always-on;
406 };
407
408 regulator@1 {
409 reg = <1>;
410 regulator-compatible = "sm0";
411 regulator-name = "vdd_sm0,vdd_core";
412 regulator-min-microvolt = <1300000>;
413 regulator-max-microvolt = <1300000>;
414 regulator-always-on;
415 };
416
417 regulator@2 {
418 reg = <2>;
419 regulator-compatible = "sm1";
420 regulator-name = "vdd_sm1,vdd_cpu";
421 regulator-min-microvolt = <1125000>;
422 regulator-max-microvolt = <1125000>;
423 regulator-always-on;
424 };
425
426 sm2_reg: regulator@3 {
427 reg = <3>;
428 regulator-compatible = "sm2";
429 regulator-name = "vdd_sm2,vin_ldo*";
430 regulator-min-microvolt = <3700000>;
431 regulator-max-microvolt = <3700000>;
432 regulator-always-on;
433 };
434
435 /* LDO0 is not connected to anything */
436
437 regulator@5 {
438 reg = <5>;
439 regulator-compatible = "ldo1";
440 regulator-name = "vdd_ldo1,avdd_pll*";
441 regulator-min-microvolt = <1100000>;
442 regulator-max-microvolt = <1100000>;
443 regulator-always-on;
444 };
445
446 regulator@6 {
447 reg = <6>;
448 regulator-compatible = "ldo2";
449 regulator-name = "vdd_ldo2,vdd_rtc";
450 regulator-min-microvolt = <1200000>;
451 regulator-max-microvolt = <1200000>;
452 };
453
454 regulator@7 {
455 reg = <7>;
456 regulator-compatible = "ldo3";
457 regulator-name = "vdd_ldo3,avdd_usb*";
458 regulator-min-microvolt = <3300000>;
459 regulator-max-microvolt = <3300000>;
460 regulator-always-on;
461 };
462
463 regulator@8 {
464 reg = <8>;
465 regulator-compatible = "ldo4";
466 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
467 regulator-min-microvolt = <1800000>;
468 regulator-max-microvolt = <1800000>;
469 regulator-always-on;
470 };
471
472 regulator@9 {
473 reg = <9>;
474 regulator-compatible = "ldo5";
475 regulator-name = "vdd_ldo5,vcore_mmc";
476 regulator-min-microvolt = <2850000>;
477 regulator-max-microvolt = <2850000>;
478 regulator-always-on;
479 };
480
481 regulator@10 {
482 reg = <10>;
483 regulator-compatible = "ldo6";
484 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
485 regulator-min-microvolt = <1800000>;
486 regulator-max-microvolt = <1800000>;
487 };
488
489 regulator@11 {
490 reg = <11>;
491 regulator-compatible = "ldo7";
492 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
493 regulator-min-microvolt = <3300000>;
494 regulator-max-microvolt = <3300000>;
495 };
496
497 regulator@12 {
498 reg = <12>;
499 regulator-compatible = "ldo8";
500 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
501 regulator-min-microvolt = <1800000>;
502 regulator-max-microvolt = <1800000>;
503 };
504
505 regulator@13 {
506 reg = <13>;
507 regulator-compatible = "ldo9";
508 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
509 regulator-min-microvolt = <2850000>;
510 regulator-max-microvolt = <2850000>;
511 regulator-always-on;
512 };
513
514 regulator@14 {
515 reg = <14>;
516 regulator-compatible = "ldo_rtc";
517 regulator-name = "vdd_rtc_out,vdd_cell";
518 regulator-min-microvolt = <3300000>;
519 regulator-max-microvolt = <3300000>;
520 regulator-always-on;
521 };
522 };
523 };
524
377 temperature-sensor@4c { 525 temperature-sensor@4c {
378 compatible = "nct1008"; 526 compatible = "nct1008";
379 reg = <0x4c>; 527 reg = <0x4c>;
@@ -387,6 +535,10 @@
387 }; 535 };
388 }; 536 };
389 537
538 pmc {
539 nvidia,invert-interrupt;
540 };
541
390 memory-controller@0x7000f400 { 542 memory-controller@0x7000f400 {
391 emc-table@190000 { 543 emc-table@190000 {
392 reg = <190000>; 544 reg = <190000>;
@@ -473,6 +625,40 @@
473 }; 625 };
474 }; 626 };
475 627
628 regulators {
629 compatible = "simple-bus";
630 #address-cells = <1>;
631 #size-cells = <0>;
632
633 vdd_5v0_reg: regulator@0 {
634 compatible = "regulator-fixed";
635 reg = <0>;
636 regulator-name = "vdd_5v0";
637 regulator-min-microvolt = <5000000>;
638 regulator-max-microvolt = <5000000>;
639 regulator-always-on;
640 };
641
642 regulator@1 {
643 compatible = "regulator-fixed";
644 reg = <1>;
645 regulator-name = "vdd_1v5";
646 regulator-min-microvolt = <1500000>;
647 regulator-max-microvolt = <1500000>;
648 gpio = <&pmic 0 0>;
649 };
650
651 regulator@2 {
652 compatible = "regulator-fixed";
653 reg = <2>;
654 regulator-name = "vdd_1v2";
655 regulator-min-microvolt = <1200000>;
656 regulator-max-microvolt = <1200000>;
657 gpio = <&pmic 1 0>;
658 enable-active-high;
659 };
660 };
661
476 sound { 662 sound {
477 compatible = "nvidia,tegra-audio-wm8903-seaboard", 663 compatible = "nvidia,tegra-audio-wm8903-seaboard",
478 "nvidia,tegra-audio-wm8903"; 664 "nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
new file mode 100644
index 000000000000..f18cec9f6a77
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -0,0 +1,449 @@
1/include/ "tegra20.dtsi"
2
3/ {
4 model = "Avionic Design Tamonten SOM";
5 compatible = "ad,tamonten", "nvidia,tegra20";
6
7 memory {
8 reg = <0x00000000 0x20000000>;
9 };
10
11 pinmux {
12 pinctrl-names = "default";
13 pinctrl-0 = <&state_default>;
14
15 state_default: pinmux {
16 ata {
17 nvidia,pins = "ata";
18 nvidia,function = "ide";
19 };
20 atb {
21 nvidia,pins = "atb", "gma", "gme";
22 nvidia,function = "sdio4";
23 };
24 atc {
25 nvidia,pins = "atc";
26 nvidia,function = "nand";
27 };
28 atd {
29 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
30 "spia", "spib", "spic";
31 nvidia,function = "gmi";
32 };
33 cdev1 {
34 nvidia,pins = "cdev1";
35 nvidia,function = "plla_out";
36 };
37 cdev2 {
38 nvidia,pins = "cdev2";
39 nvidia,function = "pllp_out4";
40 };
41 crtp {
42 nvidia,pins = "crtp";
43 nvidia,function = "crt";
44 };
45 csus {
46 nvidia,pins = "csus";
47 nvidia,function = "vi_sensor_clk";
48 };
49 dap1 {
50 nvidia,pins = "dap1";
51 nvidia,function = "dap1";
52 };
53 dap2 {
54 nvidia,pins = "dap2";
55 nvidia,function = "dap2";
56 };
57 dap3 {
58 nvidia,pins = "dap3";
59 nvidia,function = "dap3";
60 };
61 dap4 {
62 nvidia,pins = "dap4";
63 nvidia,function = "dap4";
64 };
65 ddc {
66 nvidia,pins = "ddc";
67 nvidia,function = "i2c2";
68 };
69 dta {
70 nvidia,pins = "dta", "dtd";
71 nvidia,function = "sdio2";
72 };
73 dtb {
74 nvidia,pins = "dtb", "dtc", "dte";
75 nvidia,function = "rsvd1";
76 };
77 dtf {
78 nvidia,pins = "dtf";
79 nvidia,function = "i2c3";
80 };
81 gmc {
82 nvidia,pins = "gmc";
83 nvidia,function = "uartd";
84 };
85 gpu7 {
86 nvidia,pins = "gpu7";
87 nvidia,function = "rtck";
88 };
89 gpv {
90 nvidia,pins = "gpv", "slxa", "slxk";
91 nvidia,function = "pcie";
92 };
93 hdint {
94 nvidia,pins = "hdint", "pta";
95 nvidia,function = "hdmi";
96 };
97 i2cp {
98 nvidia,pins = "i2cp";
99 nvidia,function = "i2cp";
100 };
101 irrx {
102 nvidia,pins = "irrx", "irtx";
103 nvidia,function = "uarta";
104 };
105 kbca {
106 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
107 "kbce", "kbcf";
108 nvidia,function = "kbc";
109 };
110 lcsn {
111 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
112 "ld3", "ld4", "ld5", "ld6", "ld7",
113 "ld8", "ld9", "ld10", "ld11", "ld12",
114 "ld13", "ld14", "ld15", "ld16", "ld17",
115 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
116 "lhs", "lm0", "lm1", "lpp", "lpw0",
117 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
118 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
119 "lvs";
120 nvidia,function = "displaya";
121 };
122 owc {
123 nvidia,pins = "owc", "spdi", "spdo", "uac";
124 nvidia,function = "rsvd2";
125 };
126 pmc {
127 nvidia,pins = "pmc";
128 nvidia,function = "pwr_on";
129 };
130 rm {
131 nvidia,pins = "rm";
132 nvidia,function = "i2c1";
133 };
134 sdb {
135 nvidia,pins = "sdb", "sdc", "sdd";
136 nvidia,function = "pwm";
137 };
138 sdio1 {
139 nvidia,pins = "sdio1";
140 nvidia,function = "sdio1";
141 };
142 slxc {
143 nvidia,pins = "slxc", "slxd";
144 nvidia,function = "spdif";
145 };
146 spid {
147 nvidia,pins = "spid", "spie", "spif";
148 nvidia,function = "spi1";
149 };
150 spig {
151 nvidia,pins = "spig", "spih";
152 nvidia,function = "spi2_alt";
153 };
154 uaa {
155 nvidia,pins = "uaa", "uab", "uda";
156 nvidia,function = "ulpi";
157 };
158 uad {
159 nvidia,pins = "uad";
160 nvidia,function = "irda";
161 };
162 uca {
163 nvidia,pins = "uca", "ucb";
164 nvidia,function = "uartc";
165 };
166 conf_ata {
167 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
168 "cdev1", "cdev2", "dap1", "dtb", "gma",
169 "gmb", "gmc", "gmd", "gme", "gpu7",
170 "gpv", "i2cp", "pta", "rm", "slxa",
171 "slxk", "spia", "spib", "uac";
172 nvidia,pull = <0>;
173 nvidia,tristate = <0>;
174 };
175 conf_ck32 {
176 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
177 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
178 nvidia,pull = <0>;
179 };
180 conf_csus {
181 nvidia,pins = "csus", "spid", "spif";
182 nvidia,pull = <1>;
183 nvidia,tristate = <1>;
184 };
185 conf_crtp {
186 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
187 "dtc", "dte", "dtf", "gpu", "sdio1",
188 "slxc", "slxd", "spdi", "spdo", "spig",
189 "uda";
190 nvidia,pull = <0>;
191 nvidia,tristate = <1>;
192 };
193 conf_ddc {
194 nvidia,pins = "ddc", "dta", "dtd", "kbca",
195 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
196 "sdc";
197 nvidia,pull = <2>;
198 nvidia,tristate = <0>;
199 };
200 conf_hdint {
201 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
202 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
203 "lvp0", "owc", "sdb";
204 nvidia,tristate = <1>;
205 };
206 conf_irrx {
207 nvidia,pins = "irrx", "irtx", "sdd", "spic",
208 "spie", "spih", "uaa", "uab", "uad",
209 "uca", "ucb";
210 nvidia,pull = <2>;
211 nvidia,tristate = <1>;
212 };
213 conf_lc {
214 nvidia,pins = "lc", "ls";
215 nvidia,pull = <2>;
216 };
217 conf_ld0 {
218 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
219 "ld5", "ld6", "ld7", "ld8", "ld9",
220 "ld10", "ld11", "ld12", "ld13", "ld14",
221 "ld15", "ld16", "ld17", "ldi", "lhp0",
222 "lhp1", "lhp2", "lhs", "lm0", "lpp",
223 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
224 "lvs", "pmc";
225 nvidia,tristate = <0>;
226 };
227 conf_ld17_0 {
228 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
229 "ld23_22";
230 nvidia,pull = <1>;
231 };
232 };
233 };
234
235 i2s@70002800 {
236 status = "okay";
237 };
238
239 serial@70006300 {
240 clock-frequency = <216000000>;
241 status = "okay";
242 };
243
244 i2c@7000c000 {
245 clock-frequency = <400000>;
246 status = "okay";
247 };
248
249 i2c@7000d000 {
250 clock-frequency = <400000>;
251 status = "okay";
252
253 pmic: tps6586x@34 {
254 compatible = "ti,tps6586x";
255 reg = <0x34>;
256 interrupts = <0 86 0x4>;
257
258 ti,system-power-controller;
259
260 #gpio-cells = <2>;
261 gpio-controller;
262
263 sys-supply = <&vdd_5v0_reg>;
264 vin-sm0-supply = <&sys_reg>;
265 vin-sm1-supply = <&sys_reg>;
266 vin-sm2-supply = <&sys_reg>;
267 vinldo01-supply = <&sm2_reg>;
268 vinldo23-supply = <&sm2_reg>;
269 vinldo4-supply = <&sm2_reg>;
270 vinldo678-supply = <&sm2_reg>;
271 vinldo9-supply = <&sm2_reg>;
272
273 regulators {
274 #address-cells = <1>;
275 #size-cells = <0>;
276
277 sys_reg: regulator@0 {
278 reg = <0>;
279 regulator-compatible = "sys";
280 regulator-name = "vdd_sys";
281 regulator-always-on;
282 };
283
284 regulator@1 {
285 reg = <1>;
286 regulator-compatible = "sm0";
287 regulator-name = "vdd_sys_sm0,vdd_core";
288 regulator-min-microvolt = <1200000>;
289 regulator-max-microvolt = <1200000>;
290 regulator-always-on;
291 };
292
293 regulator@2 {
294 reg = <2>;
295 regulator-compatible = "sm1";
296 regulator-name = "vdd_sys_sm1,vdd_cpu";
297 regulator-min-microvolt = <1000000>;
298 regulator-max-microvolt = <1000000>;
299 regulator-always-on;
300 };
301
302 sm2_reg: regulator@3 {
303 reg = <3>;
304 regulator-compatible = "sm2";
305 regulator-name = "vdd_sys_sm2,vin_ldo*";
306 regulator-min-microvolt = <3700000>;
307 regulator-max-microvolt = <3700000>;
308 regulator-always-on;
309 };
310
311 regulator@4 {
312 reg = <4>;
313 regulator-compatible = "ldo0";
314 regulator-name = "vdd_ldo0,vddio_pex_clk";
315 regulator-min-microvolt = <3300000>;
316 regulator-max-microvolt = <3300000>;
317 };
318
319 regulator@5 {
320 reg = <5>;
321 regulator-compatible = "ldo1";
322 regulator-name = "vdd_ldo1,avdd_pll*";
323 regulator-min-microvolt = <1100000>;
324 regulator-max-microvolt = <1100000>;
325 regulator-always-on;
326 };
327
328 regulator@6 {
329 reg = <6>;
330 regulator-compatible = "ldo2";
331 regulator-name = "vdd_ldo2,vdd_rtc";
332 regulator-min-microvolt = <1200000>;
333 regulator-max-microvolt = <1200000>;
334 };
335
336 regulator@7 {
337 reg = <7>;
338 regulator-compatible = "ldo3";
339 regulator-name = "vdd_ldo3,avdd_usb*";
340 regulator-min-microvolt = <3300000>;
341 regulator-max-microvolt = <3300000>;
342 regulator-always-on;
343 };
344
345 regulator@8 {
346 reg = <8>;
347 regulator-compatible = "ldo4";
348 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
349 regulator-min-microvolt = <1800000>;
350 regulator-max-microvolt = <1800000>;
351 regulator-always-on;
352 };
353
354 regulator@9 {
355 reg = <9>;
356 regulator-compatible = "ldo5";
357 regulator-name = "vdd_ldo5,vcore_mmc";
358 regulator-min-microvolt = <2850000>;
359 regulator-max-microvolt = <2850000>;
360 };
361
362 regulator@10 {
363 reg = <10>;
364 regulator-compatible = "ldo6";
365 regulator-name = "vdd_ldo6,avdd_vdac";
366 /*
367 * According to the Tegra 2 Automotive
368 * DataSheet, a typical value for this
369 * would be 2.8V, but the PMIC only
370 * supports 2.85V.
371 */
372 regulator-min-microvolt = <2850000>;
373 regulator-max-microvolt = <2850000>;
374 };
375
376 regulator@11 {
377 reg = <11>;
378 regulator-compatible = "ldo7";
379 regulator-name = "vdd_ldo7,avdd_hdmi";
380 regulator-min-microvolt = <3300000>;
381 regulator-max-microvolt = <3300000>;
382 };
383
384 regulator@12 {
385 reg = <12>;
386 regulator-compatible = "ldo8";
387 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
388 regulator-min-microvolt = <1800000>;
389 regulator-max-microvolt = <1800000>;
390 };
391
392 regulator@13 {
393 reg = <13>;
394 regulator-compatible = "ldo9";
395 regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
396 /*
397 * According to the Tegra 2 Automotive
398 * DataSheet, a typical value for this
399 * would be 2.8V, but the PMIC only
400 * supports 2.85V.
401 */
402 regulator-min-microvolt = <2850000>;
403 regulator-max-microvolt = <2850000>;
404 regulator-always-on;
405 };
406
407 regulator@14 {
408 reg = <14>;
409 regulator-compatible = "ldo_rtc";
410 regulator-name = "vdd_rtc_out";
411 regulator-min-microvolt = <3300000>;
412 regulator-max-microvolt = <3300000>;
413 regulator-always-on;
414 };
415 };
416 };
417 };
418
419 pmc {
420 nvidia,invert-interrupt;
421 };
422
423 usb@c5008000 {
424 status = "okay";
425 };
426
427 sdhci@c8000600 {
428 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
429 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
430 bus-width = <4>;
431 status = "okay";
432 };
433
434 regulators {
435 compatible = "simple-bus";
436
437 #address-cells = <1>;
438 #size-cells = <0>;
439
440 vdd_5v0_reg: regulator@0 {
441 compatible = "regulator-fixed";
442 reg = <0>;
443 regulator-name = "vdd_5v0";
444 regulator-min-microvolt = <5000000>;
445 regulator-max-microvolt = <5000000>;
446 regulator-always-on;
447 };
448 };
449};
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
new file mode 100644
index 000000000000..9aff31b0fe4a
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -0,0 +1,53 @@
1/dts-v1/;
2
3/include/ "tegra20-tamonten.dtsi"
4
5/ {
6 model = "Avionic Design Tamonten Evaluation Carrier";
7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
8
9 i2c@7000c000 {
10 clock-frequency = <400000>;
11 status = "okay";
12
13 wm8903: wm8903@1a {
14 compatible = "wlf,wm8903";
15 reg = <0x1a>;
16 interrupt-parent = <&gpio>;
17 interrupts = <187 0x04>;
18
19 gpio-controller;
20 #gpio-cells = <2>;
21
22 micdet-cfg = <0>;
23 micdet-delay = <100>;
24 gpio-cfg = <0xffffffff
25 0xffffffff
26 0
27 0xffffffff
28 0xffffffff>;
29 };
30 };
31
32 sound {
33 compatible = "ad,tegra-audio-wm8903-tec",
34 "nvidia,tegra-audio-wm8903";
35 nvidia,model = "Avionic Design TEC";
36
37 nvidia,audio-routing =
38 "Headphone Jack", "HPOUTR",
39 "Headphone Jack", "HPOUTL",
40 "Int Spk", "ROP",
41 "Int Spk", "RON",
42 "Int Spk", "LOP",
43 "Int Spk", "LON",
44 "Mic Jack", "MICBIAS",
45 "IN1L", "Mic Jack";
46
47 nvidia,i2s-controller = <&tegra_i2s1>;
48 nvidia,audio-codec = <&wm8903>;
49
50 nvidia,spkr-en-gpios = <&wm8903 2 0>;
51 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
52 };
53};
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index be90544e6b59..3e5952fcfbc5 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -289,6 +289,158 @@
289 i2c@7000d000 { 289 i2c@7000d000 {
290 status = "okay"; 290 status = "okay";
291 clock-frequency = <400000>; 291 clock-frequency = <400000>;
292
293 pmic: tps6586x@34 {
294 compatible = "ti,tps6586x";
295 reg = <0x34>;
296 interrupts = <0 86 0x4>;
297
298 ti,system-power-controller;
299
300 #gpio-cells = <2>;
301 gpio-controller;
302
303 sys-supply = <&vdd_5v0_reg>;
304 vin-sm0-supply = <&sys_reg>;
305 vin-sm1-supply = <&sys_reg>;
306 vin-sm2-supply = <&sys_reg>;
307 vinldo01-supply = <&sm2_reg>;
308 vinldo23-supply = <&sm2_reg>;
309 vinldo4-supply = <&sm2_reg>;
310 vinldo678-supply = <&sm2_reg>;
311 vinldo9-supply = <&sm2_reg>;
312
313 regulators {
314 #address-cells = <1>;
315 #size-cells = <0>;
316
317 sys_reg: regulator@0 {
318 reg = <0>;
319 regulator-compatible = "sys";
320 regulator-name = "vdd_sys";
321 regulator-always-on;
322 };
323
324 regulator@1 {
325 reg = <1>;
326 regulator-compatible = "sm0";
327 regulator-name = "vdd_sm0,vdd_core";
328 regulator-min-microvolt = <1200000>;
329 regulator-max-microvolt = <1200000>;
330 regulator-always-on;
331 };
332
333 regulator@2 {
334 reg = <2>;
335 regulator-compatible = "sm1";
336 regulator-name = "vdd_sm1,vdd_cpu";
337 regulator-min-microvolt = <1000000>;
338 regulator-max-microvolt = <1000000>;
339 regulator-always-on;
340 };
341
342 sm2_reg: regulator@3 {
343 reg = <3>;
344 regulator-compatible = "sm2";
345 regulator-name = "vdd_sm2,vin_ldo*";
346 regulator-min-microvolt = <3700000>;
347 regulator-max-microvolt = <3700000>;
348 regulator-always-on;
349 };
350
351 /* LDO0 is not connected to anything */
352
353 regulator@5 {
354 reg = <5>;
355 regulator-compatible = "ldo1";
356 regulator-name = "vdd_ldo1,avdd_pll*";
357 regulator-min-microvolt = <1100000>;
358 regulator-max-microvolt = <1100000>;
359 regulator-always-on;
360 };
361
362 regulator@6 {
363 reg = <6>;
364 regulator-compatible = "ldo2";
365 regulator-name = "vdd_ldo2,vdd_rtc";
366 regulator-min-microvolt = <1200000>;
367 regulator-max-microvolt = <1200000>;
368 };
369
370 regulator@7 {
371 reg = <7>;
372 regulator-compatible = "ldo3";
373 regulator-name = "vdd_ldo3,avdd_usb*";
374 regulator-min-microvolt = <3300000>;
375 regulator-max-microvolt = <3300000>;
376 regulator-always-on;
377 };
378
379 regulator@8 {
380 reg = <8>;
381 regulator-compatible = "ldo4";
382 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
383 regulator-min-microvolt = <1800000>;
384 regulator-max-microvolt = <1800000>;
385 regulator-always-on;
386 };
387
388 regulator@9 {
389 reg = <9>;
390 regulator-compatible = "ldo5";
391 regulator-name = "vdd_ldo5,vcore_mmc";
392 regulator-min-microvolt = <2850000>;
393 regulator-max-microvolt = <2850000>;
394 regulator-always-on;
395 };
396
397 regulator@10 {
398 reg = <10>;
399 regulator-compatible = "ldo6";
400 regulator-name = "vdd_ldo6,avdd_vdac";
401 regulator-min-microvolt = <1800000>;
402 regulator-max-microvolt = <1800000>;
403 };
404
405 regulator@11 {
406 reg = <11>;
407 regulator-compatible = "ldo7";
408 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
409 regulator-min-microvolt = <3300000>;
410 regulator-max-microvolt = <3300000>;
411 };
412
413 regulator@12 {
414 reg = <12>;
415 regulator-compatible = "ldo8";
416 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
417 regulator-min-microvolt = <1800000>;
418 regulator-max-microvolt = <1800000>;
419 };
420
421 regulator@13 {
422 reg = <13>;
423 regulator-compatible = "ldo9";
424 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
425 regulator-min-microvolt = <2850000>;
426 regulator-max-microvolt = <2850000>;
427 regulator-always-on;
428 };
429
430 regulator@14 {
431 reg = <14>;
432 regulator-compatible = "ldo_rtc";
433 regulator-name = "vdd_rtc_out,vdd_cell";
434 regulator-min-microvolt = <3300000>;
435 regulator-max-microvolt = <3300000>;
436 regulator-always-on;
437 };
438 };
439 };
440 };
441
442 pmc {
443 nvidia,invert-interrupt;
292 }; 444 };
293 445
294 usb@c5000000 { 446 usb@c5000000 {
@@ -317,6 +469,60 @@
317 bus-width = <8>; 469 bus-width = <8>;
318 }; 470 };
319 471
472 regulators {
473 compatible = "simple-bus";
474 #address-cells = <1>;
475 #size-cells = <0>;
476
477 vdd_5v0_reg: regulator@0 {
478 compatible = "regulator-fixed";
479 reg = <0>;
480 regulator-name = "vdd_5v0";
481 regulator-min-microvolt = <5000000>;
482 regulator-max-microvolt = <5000000>;
483 regulator-always-on;
484 };
485
486 regulator@1 {
487 compatible = "regulator-fixed";
488 reg = <1>;
489 regulator-name = "vdd_1v5";
490 regulator-min-microvolt = <1500000>;
491 regulator-max-microvolt = <1500000>;
492 gpio = <&pmic 0 0>;
493 };
494
495 regulator@2 {
496 compatible = "regulator-fixed";
497 reg = <2>;
498 regulator-name = "vdd_1v2";
499 regulator-min-microvolt = <1200000>;
500 regulator-max-microvolt = <1200000>;
501 gpio = <&pmic 1 0>;
502 enable-active-high;
503 };
504
505 regulator@3 {
506 compatible = "regulator-fixed";
507 reg = <3>;
508 regulator-name = "vdd_pnl";
509 regulator-min-microvolt = <2800000>;
510 regulator-max-microvolt = <2800000>;
511 gpio = <&gpio 22 0>; /* gpio PC6 */
512 enable-active-high;
513 };
514
515 regulator@4 {
516 compatible = "regulator-fixed";
517 reg = <4>;
518 regulator-name = "vdd_bl";
519 regulator-min-microvolt = <2800000>;
520 regulator-max-microvolt = <2800000>;
521 gpio = <&gpio 176 0>; /* gpio PW0 */
522 enable-active-high;
523 };
524 };
525
320 sound { 526 sound {
321 compatible = "nvidia,tegra-audio-wm8903-ventana", 527 compatible = "nvidia,tegra-audio-wm8903-ventana",
322 "nvidia,tegra-audio-wm8903"; 528 "nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 6916310bf58f..c636d002d6d8 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -261,6 +261,286 @@
261 gpio-controller; 261 gpio-controller;
262 #gpio-cells = <2>; 262 #gpio-cells = <2>;
263 }; 263 };
264
265 max8907@3c {
266 compatible = "maxim,max8907";
267 reg = <0x3c>;
268 interrupts = <0 86 0x4>;
269
270 maxim,system-power-controller;
271
272 mbatt-supply = <&usb0_vbus_reg>;
273 in-v1-supply = <&mbatt_reg>;
274 in-v2-supply = <&mbatt_reg>;
275 in-v3-supply = <&mbatt_reg>;
276 in1-supply = <&mbatt_reg>;
277 in2-supply = <&nvvdd_sv3_reg>;
278 in3-supply = <&mbatt_reg>;
279 in4-supply = <&mbatt_reg>;
280 in5-supply = <&mbatt_reg>;
281 in6-supply = <&mbatt_reg>;
282 in7-supply = <&mbatt_reg>;
283 in8-supply = <&mbatt_reg>;
284 in9-supply = <&mbatt_reg>;
285 in10-supply = <&mbatt_reg>;
286 in11-supply = <&mbatt_reg>;
287 in12-supply = <&mbatt_reg>;
288 in13-supply = <&mbatt_reg>;
289 in14-supply = <&mbatt_reg>;
290 in15-supply = <&mbatt_reg>;
291 in16-supply = <&mbatt_reg>;
292 in17-supply = <&nvvdd_sv3_reg>;
293 in18-supply = <&nvvdd_sv3_reg>;
294 in19-supply = <&mbatt_reg>;
295 in20-supply = <&mbatt_reg>;
296
297 regulators {
298 #address-cells = <1>;
299 #size-cells = <0>;
300
301 mbatt_reg: regulator@0 {
302 reg = <0>;
303 regulator-compatible = "mbatt";
304 regulator-name = "vbat_pmu";
305 regulator-always-on;
306 };
307
308 regulator@1 {
309 reg = <1>;
310 regulator-compatible = "sd1";
311 regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
312 regulator-min-microvolt = <1000000>;
313 regulator-max-microvolt = <1000000>;
314 regulator-always-on;
315 };
316
317 regulator@2 {
318 reg = <2>;
319 regulator-compatible = "sd2";
320 regulator-name = "nvvdd_sv2,vdd_core";
321 regulator-min-microvolt = <1200000>;
322 regulator-max-microvolt = <1200000>;
323 regulator-always-on;
324 };
325
326 nvvdd_sv3_reg: regulator@3 {
327 reg = <3>;
328 regulator-compatible = "sd3";
329 regulator-name = "nvvdd_sv3";
330 regulator-min-microvolt = <1800000>;
331 regulator-max-microvolt = <1800000>;
332 regulator-always-on;
333 };
334
335 regulator@4 {
336 reg = <4>;
337 regulator-compatible = "ldo1";
338 regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
339 regulator-min-microvolt = <3300000>;
340 regulator-max-microvolt = <3300000>;
341 regulator-always-on;
342 };
343
344 regulator@5 {
345 reg = <5>;
346 regulator-compatible = "ldo2";
347 regulator-name = "nvvdd_ldo2,avdd_pll*";
348 regulator-min-microvolt = <1100000>;
349 regulator-max-microvolt = <1100000>;
350 regulator-always-on;
351 };
352
353 regulator@6 {
354 reg = <6>;
355 regulator-compatible = "ldo3";
356 regulator-name = "nvvdd_ldo3,vcom_1v8b";
357 regulator-min-microvolt = <1800000>;
358 regulator-max-microvolt = <1800000>;
359 regulator-always-on;
360 };
361
362 regulator@7 {
363 reg = <7>;
364 regulator-compatible = "ldo4";
365 regulator-name = "nvvdd_ldo4,avdd_usb*";
366 regulator-min-microvolt = <3300000>;
367 regulator-max-microvolt = <3300000>;
368 regulator-always-on;
369 };
370
371 regulator@8 {
372 reg = <8>;
373 regulator-compatible = "ldo5";
374 regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
375 regulator-min-microvolt = <2800000>;
376 regulator-max-microvolt = <2800000>;
377 regulator-always-on;
378 };
379
380 regulator@9 {
381 reg = <9>;
382 regulator-compatible = "ldo6";
383 regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
384 regulator-min-microvolt = <1800000>;
385 regulator-max-microvolt = <1800000>;
386 };
387
388 regulator@10 {
389 reg = <10>;
390 regulator-compatible = "ldo7";
391 regulator-name = "nvvdd_ldo7,avddio_audio";
392 regulator-min-microvolt = <2800000>;
393 regulator-max-microvolt = <2800000>;
394 regulator-always-on;
395 };
396
397 regulator@11 {
398 reg = <11>;
399 regulator-compatible = "ldo8";
400 regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
401 regulator-min-microvolt = <3000000>;
402 regulator-max-microvolt = <3000000>;
403 };
404
405 regulator@12 {
406 reg = <12>;
407 regulator-compatible = "ldo9";
408 regulator-name = "nvvdd_ldo9,avdd_cam*";
409 regulator-min-microvolt = <2800000>;
410 regulator-max-microvolt = <2800000>;
411 };
412
413 regulator@13 {
414 reg = <13>;
415 regulator-compatible = "ldo10";
416 regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
417 regulator-min-microvolt = <3000000>;
418 regulator-max-microvolt = <3000000>;
419 regulator-always-on;
420 };
421
422 regulator@14 {
423 reg = <14>;
424 regulator-compatible = "ldo11";
425 regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
426 regulator-min-microvolt = <3300000>;
427 regulator-max-microvolt = <3300000>;
428 };
429
430 regulator@15 {
431 reg = <15>;
432 regulator-compatible = "ldo12";
433 regulator-name = "nvvdd_ldo12,vddio_sdio";
434 regulator-min-microvolt = <2800000>;
435 regulator-max-microvolt = <2800000>;
436 regulator-always-on;
437 };
438
439 regulator@16 {
440 reg = <16>;
441 regulator-compatible = "ldo13";
442 regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
443 regulator-min-microvolt = <2800000>;
444 regulator-max-microvolt = <2800000>;
445 };
446
447 regulator@17 {
448 reg = <17>;
449 regulator-compatible = "ldo14";
450 regulator-name = "nvvdd_ldo14,avdd_vdac";
451 regulator-min-microvolt = <2800000>;
452 regulator-max-microvolt = <2800000>;
453 };
454
455 regulator@18 {
456 reg = <18>;
457 regulator-compatible = "ldo15";
458 regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
459 regulator-min-microvolt = <3300000>;
460 regulator-max-microvolt = <3300000>;
461 };
462
463 regulator@19 {
464 reg = <19>;
465 regulator-compatible = "ldo16";
466 regulator-name = "nvvdd_ldo16,vdd_dbrtr";
467 regulator-min-microvolt = <1300000>;
468 regulator-max-microvolt = <1300000>;
469 };
470
471 regulator@20 {
472 reg = <20>;
473 regulator-compatible = "ldo17";
474 regulator-name = "nvvdd_ldo17,vddio_mipi";
475 regulator-min-microvolt = <1200000>;
476 regulator-max-microvolt = <1200000>;
477 };
478
479 regulator@21 {
480 reg = <21>;
481 regulator-compatible = "ldo18";
482 regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
483 regulator-min-microvolt = <1800000>;
484 regulator-max-microvolt = <1800000>;
485 };
486
487 regulator@22 {
488 reg = <22>;
489 regulator-compatible = "ldo19";
490 regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
491 regulator-min-microvolt = <2800000>;
492 regulator-max-microvolt = <2800000>;
493 };
494
495 regulator@23 {
496 reg = <23>;
497 regulator-compatible = "ldo20";
498 regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
499 regulator-min-microvolt = <1200000>;
500 regulator-max-microvolt = <1200000>;
501 regulator-always-on;
502 };
503
504 regulator@24 {
505 reg = <24>;
506 regulator-compatible = "out5v";
507 regulator-name = "usb0_vbus_reg";
508 };
509
510 regulator@25 {
511 reg = <25>;
512 regulator-compatible = "out33v";
513 regulator-name = "pmu_out3v3";
514 };
515
516 regulator@26 {
517 reg = <26>;
518 regulator-compatible = "bbat";
519 regulator-name = "pmu_bbat";
520 regulator-min-microvolt = <2400000>;
521 regulator-max-microvolt = <2400000>;
522 regulator-always-on;
523 };
524
525 regulator@27 {
526 reg = <27>;
527 regulator-compatible = "sdby";
528 regulator-name = "vdd_aon";
529 regulator-always-on;
530 };
531
532 regulator@28 {
533 reg = <28>;
534 regulator-compatible = "vrtc";
535 regulator-name = "vrtc,pmu_vccadc";
536 regulator-always-on;
537 };
538 };
539 };
540 };
541
542 pmc {
543 nvidia,invert-interrupt;
264 }; 544 };
265 545
266 usb@c5000000 { 546 usb@c5000000 {
@@ -284,6 +564,21 @@
284 bus-width = <8>; 564 bus-width = <8>;
285 }; 565 };
286 566
567 regulators {
568 compatible = "simple-bus";
569 #address-cells = <1>;
570 #size-cells = <0>;
571
572 usb0_vbus_reg: regulator {
573 compatible = "regulator-fixed";
574 reg = <0>;
575 regulator-name = "usb0_vbus";
576 regulator-min-microvolt = <5000000>;
577 regulator-max-microvolt = <5000000>;
578 regulator-always-on;
579 };
580 };
581
287 sound { 582 sound {
288 compatible = "nvidia,tegra-audio-wm8753-whistler", 583 compatible = "nvidia,tegra-audio-wm8753-whistler",
289 "nvidia,tegra-audio-wm8753"; 584 "nvidia,tegra-audio-wm8753";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 405d1673904e..67a6cd910b96 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -123,7 +123,7 @@
123 status = "disabled"; 123 status = "disabled";
124 }; 124 };
125 125
126 pwm { 126 pwm: pwm {
127 compatible = "nvidia,tegra20-pwm"; 127 compatible = "nvidia,tegra20-pwm";
128 reg = <0x7000a000 0x100>; 128 reg = <0x7000a000 0x100>;
129 #pwm-cells = <2>; 129 #pwm-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
new file mode 100644
index 000000000000..dd4222f00eca
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -0,0 +1,87 @@
1/dts-v1/;
2
3/include/ "tegra30-cardhu.dtsi"
4
5/* This dts file support the cardhu A02 version of board */
6
7/ {
8 model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
9 compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
10
11 regulators {
12 compatible = "simple-bus";
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 ddr_reg: regulator@100 {
17 compatible = "regulator-fixed";
18 reg = <100>;
19 regulator-name = "vdd_ddr";
20 regulator-min-microvolt = <1500000>;
21 regulator-max-microvolt = <1500000>;
22 regulator-always-on;
23 regulator-boot-on;
24 enable-active-high;
25 gpio = <&pmic 6 0>;
26 };
27
28 sys_3v3_reg: regulator@101 {
29 compatible = "regulator-fixed";
30 reg = <101>;
31 regulator-name = "sys_3v3";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
34 regulator-always-on;
35 regulator-boot-on;
36 enable-active-high;
37 gpio = <&pmic 7 0>;
38 };
39
40 usb1_vbus_reg: regulator@102 {
41 compatible = "regulator-fixed";
42 reg = <102>;
43 regulator-name = "usb1_vbus";
44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>;
46 enable-active-high;
47 gpio = <&gpio 68 0>; /* GPIO PI4 */
48 gpio-open-drain;
49 vin-supply = <&vdd_5v0_reg>;
50 };
51
52 usb3_vbus_reg: regulator@103 {
53 compatible = "regulator-fixed";
54 reg = <103>;
55 regulator-name = "usb3_vbus";
56 regulator-min-microvolt = <5000000>;
57 regulator-max-microvolt = <5000000>;
58 enable-active-high;
59 gpio = <&gpio 63 0>; /* GPIO PH7 */
60 gpio-open-drain;
61 vin-supply = <&vdd_5v0_reg>;
62 };
63
64 vdd_5v0_reg: regulator@104 {
65 compatible = "regulator-fixed";
66 reg = <104>;
67 regulator-name = "5v0";
68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <5000000>;
70 enable-active-high;
71 gpio = <&pmic 2 0>;
72 };
73
74 vdd_bl_reg: regulator@105 {
75 compatible = "regulator-fixed";
76 reg = <105>;
77 regulator-name = "vdd_bl";
78 regulator-min-microvolt = <5000000>;
79 regulator-max-microvolt = <5000000>;
80 regulator-always-on;
81 regulator-boot-on;
82 enable-active-high;
83 gpio = <&gpio 83 0>; /* GPIO PK3 */
84 };
85 };
86};
87
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
new file mode 100644
index 000000000000..0828f097ca86
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -0,0 +1,98 @@
1/dts-v1/;
2
3/include/ "tegra30-cardhu.dtsi"
4
5/* This dts file support the cardhu A04 and later versions of board */
6
7/ {
8 model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
9 compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
10
11 regulators {
12 compatible = "simple-bus";
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 ddr_reg: regulator@100 {
17 compatible = "regulator-fixed";
18 regulator-name = "ddr";
19 reg = <100>;
20 regulator-min-microvolt = <1500000>;
21 regulator-max-microvolt = <1500000>;
22 regulator-always-on;
23 regulator-boot-on;
24 enable-active-high;
25 gpio = <&pmic 7 0>;
26 };
27
28 sys_3v3_reg: regulator@101 {
29 compatible = "regulator-fixed";
30 reg = <101>;
31 regulator-name = "sys_3v3";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
34 regulator-always-on;
35 regulator-boot-on;
36 enable-active-high;
37 gpio = <&pmic 6 0>;
38 };
39
40 usb1_vbus_reg: regulator@102 {
41 compatible = "regulator-fixed";
42 reg = <102>;
43 regulator-name = "usb1_vbus";
44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>;
46 enable-active-high;
47 gpio = <&gpio 238 0>; /* GPIO PDD6 */
48 gpio-open-drain;
49 vin-supply = <&vdd_5v0_reg>;
50 };
51
52 usb3_vbus_reg: regulator@103 {
53 compatible = "regulator-fixed";
54 reg = <103>;
55 regulator-name = "usb3_vbus";
56 regulator-min-microvolt = <5000000>;
57 regulator-max-microvolt = <5000000>;
58 enable-active-high;
59 gpio = <&gpio 236 0>; /* GPIO PDD4 */
60 gpio-open-drain;
61 vin-supply = <&vdd_5v0_reg>;
62 };
63
64 vdd_5v0_reg: regulator@104 {
65 compatible = "regulator-fixed";
66 reg = <104>;
67 regulator-name = "5v0";
68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <5000000>;
70 enable-active-high;
71 gpio = <&pmic 8 0>;
72 };
73
74 vdd_bl_reg: regulator@105 {
75 compatible = "regulator-fixed";
76 reg = <105>;
77 regulator-name = "vdd_bl";
78 regulator-min-microvolt = <5000000>;
79 regulator-max-microvolt = <5000000>;
80 regulator-always-on;
81 regulator-boot-on;
82 enable-active-high;
83 gpio = <&gpio 234 0>; /* GPIO PDD2 */
84 };
85
86 vdd_bl2_reg: regulator@106 {
87 compatible = "regulator-fixed";
88 reg = <106>;
89 regulator-name = "vdd_bl2";
90 regulator-min-microvolt = <5000000>;
91 regulator-max-microvolt = <5000000>;
92 regulator-always-on;
93 regulator-boot-on;
94 enable-active-high;
95 gpio = <&gpio 232 0>; /* GPIO PDD0 */
96 };
97 };
98};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dts b/arch/arm/boot/dts/tegra30-cardhu.dts
deleted file mode 100644
index c169bced131e..000000000000
--- a/arch/arm/boot/dts/tegra30-cardhu.dts
+++ /dev/null
@@ -1,171 +0,0 @@
1/dts-v1/;
2
3/include/ "tegra30.dtsi"
4
5/ {
6 model = "NVIDIA Tegra30 Cardhu evaluation board";
7 compatible = "nvidia,cardhu", "nvidia,tegra30";
8
9 memory {
10 reg = <0x80000000 0x40000000>;
11 };
12
13 pinmux {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 sdmmc1_clk_pz0 {
19 nvidia,pins = "sdmmc1_clk_pz0";
20 nvidia,function = "sdmmc1";
21 nvidia,pull = <0>;
22 nvidia,tristate = <0>;
23 };
24 sdmmc1_cmd_pz1 {
25 nvidia,pins = "sdmmc1_cmd_pz1",
26 "sdmmc1_dat0_py7",
27 "sdmmc1_dat1_py6",
28 "sdmmc1_dat2_py5",
29 "sdmmc1_dat3_py4";
30 nvidia,function = "sdmmc1";
31 nvidia,pull = <2>;
32 nvidia,tristate = <0>;
33 };
34 sdmmc4_clk_pcc4 {
35 nvidia,pins = "sdmmc4_clk_pcc4",
36 "sdmmc4_rst_n_pcc3";
37 nvidia,function = "sdmmc4";
38 nvidia,pull = <0>;
39 nvidia,tristate = <0>;
40 };
41 sdmmc4_dat0_paa0 {
42 nvidia,pins = "sdmmc4_dat0_paa0",
43 "sdmmc4_dat1_paa1",
44 "sdmmc4_dat2_paa2",
45 "sdmmc4_dat3_paa3",
46 "sdmmc4_dat4_paa4",
47 "sdmmc4_dat5_paa5",
48 "sdmmc4_dat6_paa6",
49 "sdmmc4_dat7_paa7";
50 nvidia,function = "sdmmc4";
51 nvidia,pull = <2>;
52 nvidia,tristate = <0>;
53 };
54 dap2_fs_pa2 {
55 nvidia,pins = "dap2_fs_pa2",
56 "dap2_sclk_pa3",
57 "dap2_din_pa4",
58 "dap2_dout_pa5";
59 nvidia,function = "i2s1";
60 nvidia,pull = <0>;
61 nvidia,tristate = <0>;
62 };
63 };
64 };
65
66 serial@70006000 {
67 status = "okay";
68 clock-frequency = <408000000>;
69 };
70
71 i2c@7000c000 {
72 status = "okay";
73 clock-frequency = <100000>;
74 };
75
76 i2c@7000c400 {
77 status = "okay";
78 clock-frequency = <100000>;
79 };
80
81 i2c@7000c500 {
82 status = "okay";
83 clock-frequency = <100000>;
84
85 /* ALS and Proximity sensor */
86 isl29028@44 {
87 compatible = "isil,isl29028";
88 reg = <0x44>;
89 interrupt-parent = <&gpio>;
90 interrupts = <88 0x04>; /*gpio PL0 */
91 };
92 };
93
94 i2c@7000c700 {
95 status = "okay";
96 clock-frequency = <100000>;
97 };
98
99 i2c@7000d000 {
100 status = "okay";
101 clock-frequency = <100000>;
102
103 wm8903: wm8903@1a {
104 compatible = "wlf,wm8903";
105 reg = <0x1a>;
106 interrupt-parent = <&gpio>;
107 interrupts = <179 0x04>; /* gpio PW3 */
108
109 gpio-controller;
110 #gpio-cells = <2>;
111
112 micdet-cfg = <0>;
113 micdet-delay = <100>;
114 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
115 };
116
117 tps62361 {
118 compatible = "ti,tps62361";
119 reg = <0x60>;
120
121 regulator-name = "tps62361-vout";
122 regulator-min-microvolt = <500000>;
123 regulator-max-microvolt = <1500000>;
124 regulator-boot-on;
125 regulator-always-on;
126 ti,vsel0-state-high;
127 ti,vsel1-state-high;
128 };
129 };
130
131 ahub {
132 i2s@70080400 {
133 status = "okay";
134 };
135 };
136
137 sdhci@78000000 {
138 status = "okay";
139 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
140 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
141 power-gpios = <&gpio 31 0>; /* gpio PD7 */
142 bus-width = <4>;
143 };
144
145 sdhci@78000600 {
146 status = "okay";
147 bus-width = <8>;
148 };
149
150 sound {
151 compatible = "nvidia,tegra-audio-wm8903-cardhu",
152 "nvidia,tegra-audio-wm8903";
153 nvidia,model = "NVIDIA Tegra Cardhu";
154
155 nvidia,audio-routing =
156 "Headphone Jack", "HPOUTR",
157 "Headphone Jack", "HPOUTL",
158 "Int Spk", "ROP",
159 "Int Spk", "RON",
160 "Int Spk", "LOP",
161 "Int Spk", "LON",
162 "Mic Jack", "MICBIAS",
163 "IN1L", "Mic Jack";
164
165 nvidia,i2s-controller = <&tegra_i2s1>;
166 nvidia,audio-codec = <&wm8903>;
167
168 nvidia,spkr-en-gpios = <&wm8903 2 0>;
169 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
170 };
171};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
new file mode 100644
index 000000000000..d10c9c5a3606
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -0,0 +1,475 @@
1/include/ "tegra30.dtsi"
2
3/**
4 * This file contains common DT entry for all fab version of Cardhu.
5 * There is multiple fab version of Cardhu starting from A01 to A07.
6 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
7 * A02 will have different sets of GPIOs for fixed regulator compare to
8 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
9 * compatible with fab version A04. Based on Cardhu fab version, the
10 * related dts file need to be chosen like for Cardhu fab version A02,
11 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
12 * tegra30-cardhu-a04.dts.
13 * The identification of board is done in two ways, by looking the sticker
14 * on PCB and by reading board id eeprom.
15 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
16 * number is the fab version like here it is 002 and hence fab version A02.
17 * The (downstream internal) U-Boot of Cardhu display the board-id as
18 * follows:
19 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
20 * In this Fab version is 02 i.e. A02.
21 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
22 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
23 * wide.
24 */
25
26/ {
27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30";
29
30 memory {
31 reg = <0x80000000 0x40000000>;
32 };
33
34 pinmux {
35 pinctrl-names = "default";
36 pinctrl-0 = <&state_default>;
37
38 state_default: pinmux {
39 sdmmc1_clk_pz0 {
40 nvidia,pins = "sdmmc1_clk_pz0";
41 nvidia,function = "sdmmc1";
42 nvidia,pull = <0>;
43 nvidia,tristate = <0>;
44 };
45 sdmmc1_cmd_pz1 {
46 nvidia,pins = "sdmmc1_cmd_pz1",
47 "sdmmc1_dat0_py7",
48 "sdmmc1_dat1_py6",
49 "sdmmc1_dat2_py5",
50 "sdmmc1_dat3_py4";
51 nvidia,function = "sdmmc1";
52 nvidia,pull = <2>;
53 nvidia,tristate = <0>;
54 };
55 sdmmc4_clk_pcc4 {
56 nvidia,pins = "sdmmc4_clk_pcc4",
57 "sdmmc4_rst_n_pcc3";
58 nvidia,function = "sdmmc4";
59 nvidia,pull = <0>;
60 nvidia,tristate = <0>;
61 };
62 sdmmc4_dat0_paa0 {
63 nvidia,pins = "sdmmc4_dat0_paa0",
64 "sdmmc4_dat1_paa1",
65 "sdmmc4_dat2_paa2",
66 "sdmmc4_dat3_paa3",
67 "sdmmc4_dat4_paa4",
68 "sdmmc4_dat5_paa5",
69 "sdmmc4_dat6_paa6",
70 "sdmmc4_dat7_paa7";
71 nvidia,function = "sdmmc4";
72 nvidia,pull = <2>;
73 nvidia,tristate = <0>;
74 };
75 dap2_fs_pa2 {
76 nvidia,pins = "dap2_fs_pa2",
77 "dap2_sclk_pa3",
78 "dap2_din_pa4",
79 "dap2_dout_pa5";
80 nvidia,function = "i2s1";
81 nvidia,pull = <0>;
82 nvidia,tristate = <0>;
83 };
84 };
85 };
86
87 serial@70006000 {
88 status = "okay";
89 clock-frequency = <408000000>;
90 };
91
92 i2c@7000c000 {
93 status = "okay";
94 clock-frequency = <100000>;
95 };
96
97 i2c@7000c400 {
98 status = "okay";
99 clock-frequency = <100000>;
100 };
101
102 i2c@7000c500 {
103 status = "okay";
104 clock-frequency = <100000>;
105
106 /* ALS and Proximity sensor */
107 isl29028@44 {
108 compatible = "isil,isl29028";
109 reg = <0x44>;
110 interrupt-parent = <&gpio>;
111 interrupts = <88 0x04>; /*gpio PL0 */
112 };
113 };
114
115 i2c@7000c700 {
116 status = "okay";
117 clock-frequency = <100000>;
118 };
119
120 i2c@7000d000 {
121 status = "okay";
122 clock-frequency = <100000>;
123
124 wm8903: wm8903@1a {
125 compatible = "wlf,wm8903";
126 reg = <0x1a>;
127 interrupt-parent = <&gpio>;
128 interrupts = <179 0x04>; /* gpio PW3 */
129
130 gpio-controller;
131 #gpio-cells = <2>;
132
133 micdet-cfg = <0>;
134 micdet-delay = <100>;
135 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
136 };
137
138 tps62361 {
139 compatible = "ti,tps62361";
140 reg = <0x60>;
141
142 regulator-name = "tps62361-vout";
143 regulator-min-microvolt = <500000>;
144 regulator-max-microvolt = <1500000>;
145 regulator-boot-on;
146 regulator-always-on;
147 ti,vsel0-state-high;
148 ti,vsel1-state-high;
149 };
150
151 pmic: tps65911@2d {
152 compatible = "ti,tps65911";
153 reg = <0x2d>;
154
155 interrupts = <0 86 0x4>;
156 #interrupt-cells = <2>;
157 interrupt-controller;
158
159 ti,system-power-controller;
160
161 #gpio-cells = <2>;
162 gpio-controller;
163
164 vcc1-supply = <&vdd_ac_bat_reg>;
165 vcc2-supply = <&vdd_ac_bat_reg>;
166 vcc3-supply = <&vio_reg>;
167 vcc4-supply = <&vdd_5v0_reg>;
168 vcc5-supply = <&vdd_ac_bat_reg>;
169 vcc6-supply = <&vdd2_reg>;
170 vcc7-supply = <&vdd_ac_bat_reg>;
171 vccio-supply = <&vdd_ac_bat_reg>;
172
173 regulators {
174 #address-cells = <1>;
175 #size-cells = <0>;
176
177 vdd1_reg: regulator@0 {
178 reg = <0>;
179 regulator-compatible = "vdd1";
180 regulator-name = "vddio_ddr_1v2";
181 regulator-min-microvolt = <1200000>;
182 regulator-max-microvolt = <1200000>;
183 regulator-always-on;
184 };
185
186 vdd2_reg: regulator@1 {
187 reg = <1>;
188 regulator-compatible = "vdd2";
189 regulator-name = "vdd_1v5_gen";
190 regulator-min-microvolt = <1500000>;
191 regulator-max-microvolt = <1500000>;
192 regulator-always-on;
193 };
194
195 vddctrl_reg: regulator@2 {
196 reg = <2>;
197 regulator-compatible = "vddctrl";
198 regulator-name = "vdd_cpu,vdd_sys";
199 regulator-min-microvolt = <1000000>;
200 regulator-max-microvolt = <1000000>;
201 regulator-always-on;
202 };
203
204 vio_reg: regulator@3 {
205 reg = <3>;
206 regulator-compatible = "vio";
207 regulator-name = "vdd_1v8_gen";
208 regulator-min-microvolt = <1800000>;
209 regulator-max-microvolt = <1800000>;
210 regulator-always-on;
211 };
212
213 ldo1_reg: regulator@4 {
214 reg = <4>;
215 regulator-compatible = "ldo1";
216 regulator-name = "vdd_pexa,vdd_pexb";
217 regulator-min-microvolt = <1050000>;
218 regulator-max-microvolt = <1050000>;
219 };
220
221 ldo2_reg: regulator@5 {
222 reg = <5>;
223 regulator-compatible = "ldo2";
224 regulator-name = "vdd_sata,avdd_plle";
225 regulator-min-microvolt = <1050000>;
226 regulator-max-microvolt = <1050000>;
227 };
228
229 /* LDO3 is not connected to anything */
230
231 ldo4_reg: regulator@7 {
232 reg = <7>;
233 regulator-compatible = "ldo4";
234 regulator-name = "vdd_rtc";
235 regulator-min-microvolt = <1200000>;
236 regulator-max-microvolt = <1200000>;
237 regulator-always-on;
238 };
239
240 ldo5_reg: regulator@8 {
241 reg = <8>;
242 regulator-compatible = "ldo5";
243 regulator-name = "vddio_sdmmc,avdd_vdac";
244 regulator-min-microvolt = <3300000>;
245 regulator-max-microvolt = <3300000>;
246 regulator-always-on;
247 };
248
249 ldo6_reg: regulator@9 {
250 reg = <9>;
251 regulator-compatible = "ldo6";
252 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
253 regulator-min-microvolt = <1200000>;
254 regulator-max-microvolt = <1200000>;
255 };
256
257 ldo7_reg: regulator@10 {
258 reg = <10>;
259 regulator-compatible = "ldo7";
260 regulator-name = "vdd_pllm,x,u,a_p_c_s";
261 regulator-min-microvolt = <1200000>;
262 regulator-max-microvolt = <1200000>;
263 regulator-always-on;
264 };
265
266 ldo8_reg: regulator@11 {
267 reg = <11>;
268 regulator-compatible = "ldo8";
269 regulator-name = "vdd_ddr_hs";
270 regulator-min-microvolt = <1000000>;
271 regulator-max-microvolt = <1000000>;
272 regulator-always-on;
273 };
274 };
275 };
276 };
277
278 ahub {
279 i2s@70080400 {
280 status = "okay";
281 };
282 };
283
284 pmc {
285 status = "okay";
286 nvidia,invert-interrupt;
287 };
288
289 sdhci@78000000 {
290 status = "okay";
291 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
292 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
293 power-gpios = <&gpio 31 0>; /* gpio PD7 */
294 bus-width = <4>;
295 };
296
297 sdhci@78000600 {
298 status = "okay";
299 bus-width = <8>;
300 };
301
302 regulators {
303 compatible = "simple-bus";
304 #address-cells = <1>;
305 #size-cells = <0>;
306
307 vdd_ac_bat_reg: regulator@0 {
308 compatible = "regulator-fixed";
309 reg = <0>;
310 regulator-name = "vdd_ac_bat";
311 regulator-min-microvolt = <5000000>;
312 regulator-max-microvolt = <5000000>;
313 regulator-always-on;
314 };
315
316 cam_1v8_reg: regulator@1 {
317 compatible = "regulator-fixed";
318 reg = <1>;
319 regulator-name = "cam_1v8";
320 regulator-min-microvolt = <1800000>;
321 regulator-max-microvolt = <1800000>;
322 enable-active-high;
323 gpio = <&gpio 220 0>; /* gpio PBB4 */
324 vin-supply = <&vio_reg>;
325 };
326
327 cp_5v_reg: regulator@2 {
328 compatible = "regulator-fixed";
329 reg = <2>;
330 regulator-name = "cp_5v";
331 regulator-min-microvolt = <5000000>;
332 regulator-max-microvolt = <5000000>;
333 regulator-boot-on;
334 regulator-always-on;
335 enable-active-high;
336 gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
337 };
338
339 emmc_3v3_reg: regulator@3 {
340 compatible = "regulator-fixed";
341 reg = <3>;
342 regulator-name = "emmc_3v3";
343 regulator-min-microvolt = <3300000>;
344 regulator-max-microvolt = <3300000>;
345 regulator-always-on;
346 regulator-boot-on;
347 enable-active-high;
348 gpio = <&gpio 25 0>; /* gpio PD1 */
349 vin-supply = <&sys_3v3_reg>;
350 };
351
352 modem_3v3_reg: regulator@4 {
353 compatible = "regulator-fixed";
354 reg = <4>;
355 regulator-name = "modem_3v3";
356 regulator-min-microvolt = <3300000>;
357 regulator-max-microvolt = <3300000>;
358 enable-active-high;
359 gpio = <&gpio 30 0>; /* gpio PD6 */
360 };
361
362 pex_hvdd_3v3_reg: regulator@5 {
363 compatible = "regulator-fixed";
364 reg = <5>;
365 regulator-name = "pex_hvdd_3v3";
366 regulator-min-microvolt = <3300000>;
367 regulator-max-microvolt = <3300000>;
368 enable-active-high;
369 gpio = <&gpio 95 0>; /* gpio PL7 */
370 vin-supply = <&sys_3v3_reg>;
371 };
372
373 vdd_cam1_ldo_reg: regulator@6 {
374 compatible = "regulator-fixed";
375 reg = <6>;
376 regulator-name = "vdd_cam1_ldo";
377 regulator-min-microvolt = <2800000>;
378 regulator-max-microvolt = <2800000>;
379 enable-active-high;
380 gpio = <&gpio 142 0>; /* gpio PR6 */
381 vin-supply = <&sys_3v3_reg>;
382 };
383
384 vdd_cam2_ldo_reg: regulator@7 {
385 compatible = "regulator-fixed";
386 reg = <7>;
387 regulator-name = "vdd_cam2_ldo";
388 regulator-min-microvolt = <2800000>;
389 regulator-max-microvolt = <2800000>;
390 enable-active-high;
391 gpio = <&gpio 143 0>; /* gpio PR7 */
392 vin-supply = <&sys_3v3_reg>;
393 };
394
395 vdd_cam3_ldo_reg: regulator@8 {
396 compatible = "regulator-fixed";
397 reg = <8>;
398 regulator-name = "vdd_cam3_ldo";
399 regulator-min-microvolt = <3300000>;
400 regulator-max-microvolt = <3300000>;
401 enable-active-high;
402 gpio = <&gpio 144 0>; /* gpio PS0 */
403 vin-supply = <&sys_3v3_reg>;
404 };
405
406 vdd_com_reg: regulator@9 {
407 compatible = "regulator-fixed";
408 reg = <9>;
409 regulator-name = "vdd_com";
410 regulator-min-microvolt = <3300000>;
411 regulator-max-microvolt = <3300000>;
412 enable-active-high;
413 gpio = <&gpio 24 0>; /* gpio PD0 */
414 vin-supply = <&sys_3v3_reg>;
415 };
416
417 vdd_fuse_3v3_reg: regulator@10 {
418 compatible = "regulator-fixed";
419 reg = <10>;
420 regulator-name = "vdd_fuse_3v3";
421 regulator-min-microvolt = <3300000>;
422 regulator-max-microvolt = <3300000>;
423 enable-active-high;
424 gpio = <&gpio 94 0>; /* gpio PL6 */
425 vin-supply = <&sys_3v3_reg>;
426 };
427
428 vdd_pnl1_reg: regulator@11 {
429 compatible = "regulator-fixed";
430 reg = <11>;
431 regulator-name = "vdd_pnl1";
432 regulator-min-microvolt = <3300000>;
433 regulator-max-microvolt = <3300000>;
434 regulator-always-on;
435 regulator-boot-on;
436 enable-active-high;
437 gpio = <&gpio 92 0>; /* gpio PL4 */
438 vin-supply = <&sys_3v3_reg>;
439 };
440
441 vdd_vid_reg: regulator@12 {
442 compatible = "regulator-fixed";
443 reg = <12>;
444 regulator-name = "vddio_vid";
445 regulator-min-microvolt = <5000000>;
446 regulator-max-microvolt = <5000000>;
447 enable-active-high;
448 gpio = <&gpio 152 0>; /* GPIO PT0 */
449 gpio-open-drain;
450 vin-supply = <&vdd_5v0_reg>;
451 };
452 };
453
454 sound {
455 compatible = "nvidia,tegra-audio-wm8903-cardhu",
456 "nvidia,tegra-audio-wm8903";
457 nvidia,model = "NVIDIA Tegra Cardhu";
458
459 nvidia,audio-routing =
460 "Headphone Jack", "HPOUTR",
461 "Headphone Jack", "HPOUTL",
462 "Int Spk", "ROP",
463 "Int Spk", "RON",
464 "Int Spk", "LOP",
465 "Int Spk", "LON",
466 "Mic Jack", "MICBIAS",
467 "IN1L", "Mic Jack";
468
469 nvidia,i2s-controller = <&tegra_i2s1>;
470 nvidia,audio-codec = <&wm8903>;
471
472 nvidia,spkr-en-gpios = <&wm8903 2 0>;
473 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
474 };
475};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 3e4334d14efb..b1497c7d7d68 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -117,7 +117,7 @@
117 status = "disabled"; 117 status = "disabled";
118 }; 118 };
119 119
120 pwm { 120 pwm: pwm {
121 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; 121 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
122 reg = <0x7000a000 0x100>; 122 reg = <0x7000a000 0x100>;
123 #pwm-cells = <2>; 123 #pwm-cells = <2>;
diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi
new file mode 100644
index 000000000000..a63272422d76
--- /dev/null
+++ b/arch/arm/boot/dts/tps65217.dtsi
@@ -0,0 +1,56 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Integrated Power Management Chip
11 * http://www.ti.com/lit/ds/symlink/tps65217.pdf
12 */
13
14&tps {
15 compatible = "ti,tps65217";
16
17 regulators {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 dcdc1_reg: regulator@0 {
22 reg = <0>;
23 regulator-compatible = "dcdc1";
24 };
25
26 dcdc2_reg: regulator@1 {
27 reg = <1>;
28 regulator-compatible = "dcdc2";
29 };
30
31 dcdc3_reg: regulator@2 {
32 reg = <2>;
33 regulator-compatible = "dcdc3";
34 };
35
36 ldo1_reg: regulator@3 {
37 reg = <3>;
38 regulator-compatible = "ldo1";
39 };
40
41 ldo2_reg: regulator@4 {
42 reg = <4>;
43 regulator-compatible = "ldo2";
44 };
45
46 ldo3_reg: regulator@5 {
47 reg = <5>;
48 regulator-compatible = "ldo3";
49 };
50
51 ldo4_reg: regulator@6 {
52 reg = <6>;
53 regulator-compatible = "ldo4";
54 };
55 };
56};
diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi
new file mode 100644
index 000000000000..92693a89160e
--- /dev/null
+++ b/arch/arm/boot/dts/tps65910.dtsi
@@ -0,0 +1,86 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Integrated Power Management Chip
11 * http://www.ti.com/lit/ds/symlink/tps65910.pdf
12 */
13
14&tps {
15 compatible = "ti,tps65910";
16
17 regulators {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 vrtc_reg: regulator@0 {
22 reg = <0>;
23 regulator-compatible = "vrtc";
24 };
25
26 vio_reg: regulator@1 {
27 reg = <1>;
28 regulator-compatible = "vio";
29 };
30
31 vdd1_reg: regulator@2 {
32 reg = <2>;
33 regulator-compatible = "vdd1";
34 };
35
36 vdd2_reg: regulator@3 {
37 reg = <3>;
38 regulator-compatible = "vdd2";
39 };
40
41 vdd3_reg: regulator@4 {
42 reg = <4>;
43 regulator-compatible = "vdd3";
44 };
45
46 vdig1_reg: regulator@5 {
47 reg = <5>;
48 regulator-compatible = "vdig1";
49 };
50
51 vdig2_reg: regulator@6 {
52 reg = <6>;
53 regulator-compatible = "vdig2";
54 };
55
56 vpll_reg: regulator@7 {
57 reg = <7>;
58 regulator-compatible = "vpll";
59 };
60
61 vdac_reg: regulator@8 {
62 reg = <8>;
63 regulator-compatible = "vdac";
64 };
65
66 vaux1_reg: regulator@9 {
67 reg = <9>;
68 regulator-compatible = "vaux1";
69 };
70
71 vaux2_reg: regulator@10 {
72 reg = <10>;
73 regulator-compatible = "vaux2";
74 };
75
76 vaux33_reg: regulator@11 {
77 reg = <11>;
78 regulator-compatible = "vaux33";
79 };
80
81 vmmc_reg: regulator@12 {
82 reg = <12>;
83 regulator-compatible = "vmmc";
84 };
85 };
86};
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index 22f4d1394ed3..ff000172c93c 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -19,19 +19,19 @@
19 interrupts = <11>; 19 interrupts = <11>;
20 }; 20 };
21 21
22 vdac: regulator@0 { 22 vdac: regulator-vdac {
23 compatible = "ti,twl4030-vdac"; 23 compatible = "ti,twl4030-vdac";
24 regulator-min-microvolt = <1800000>; 24 regulator-min-microvolt = <1800000>;
25 regulator-max-microvolt = <1800000>; 25 regulator-max-microvolt = <1800000>;
26 }; 26 };
27 27
28 vpll2: regulator@1 { 28 vpll2: regulator-vpll2 {
29 compatible = "ti,twl4030-vpll2"; 29 compatible = "ti,twl4030-vpll2";
30 regulator-min-microvolt = <1800000>; 30 regulator-min-microvolt = <1800000>;
31 regulator-max-microvolt = <1800000>; 31 regulator-max-microvolt = <1800000>;
32 }; 32 };
33 33
34 vmmc1: regulator@2 { 34 vmmc1: regulator-vmmc1 {
35 compatible = "ti,twl4030-vmmc1"; 35 compatible = "ti,twl4030-vmmc1";
36 regulator-min-microvolt = <1850000>; 36 regulator-min-microvolt = <1850000>;
37 regulator-max-microvolt = <3150000>; 37 regulator-max-microvolt = <3150000>;
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index d351b27d7213..123e2c40218a 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -20,70 +20,70 @@
20 interrupts = <11>; 20 interrupts = <11>;
21 }; 21 };
22 22
23 vaux1: regulator@0 { 23 vaux1: regulator-vaux1 {
24 compatible = "ti,twl6030-vaux1"; 24 compatible = "ti,twl6030-vaux1";
25 regulator-min-microvolt = <1000000>; 25 regulator-min-microvolt = <1000000>;
26 regulator-max-microvolt = <3000000>; 26 regulator-max-microvolt = <3000000>;
27 }; 27 };
28 28
29 vaux2: regulator@1 { 29 vaux2: regulator-vaux2 {
30 compatible = "ti,twl6030-vaux2"; 30 compatible = "ti,twl6030-vaux2";
31 regulator-min-microvolt = <1200000>; 31 regulator-min-microvolt = <1200000>;
32 regulator-max-microvolt = <2800000>; 32 regulator-max-microvolt = <2800000>;
33 }; 33 };
34 34
35 vaux3: regulator@2 { 35 vaux3: regulator-vaux3 {
36 compatible = "ti,twl6030-vaux3"; 36 compatible = "ti,twl6030-vaux3";
37 regulator-min-microvolt = <1000000>; 37 regulator-min-microvolt = <1000000>;
38 regulator-max-microvolt = <3000000>; 38 regulator-max-microvolt = <3000000>;
39 }; 39 };
40 40
41 vmmc: regulator@3 { 41 vmmc: regulator-vmmc {
42 compatible = "ti,twl6030-vmmc"; 42 compatible = "ti,twl6030-vmmc";
43 regulator-min-microvolt = <1200000>; 43 regulator-min-microvolt = <1200000>;
44 regulator-max-microvolt = <3000000>; 44 regulator-max-microvolt = <3000000>;
45 }; 45 };
46 46
47 vpp: regulator@4 { 47 vpp: regulator-vpp {
48 compatible = "ti,twl6030-vpp"; 48 compatible = "ti,twl6030-vpp";
49 regulator-min-microvolt = <1800000>; 49 regulator-min-microvolt = <1800000>;
50 regulator-max-microvolt = <2500000>; 50 regulator-max-microvolt = <2500000>;
51 }; 51 };
52 52
53 vusim: regulator@5 { 53 vusim: regulator-vusim {
54 compatible = "ti,twl6030-vusim"; 54 compatible = "ti,twl6030-vusim";
55 regulator-min-microvolt = <1200000>; 55 regulator-min-microvolt = <1200000>;
56 regulator-max-microvolt = <2900000>; 56 regulator-max-microvolt = <2900000>;
57 }; 57 };
58 58
59 vdac: regulator@6 { 59 vdac: regulator-vdac {
60 compatible = "ti,twl6030-vdac"; 60 compatible = "ti,twl6030-vdac";
61 }; 61 };
62 62
63 vana: regulator@7 { 63 vana: regulator-vana {
64 compatible = "ti,twl6030-vana"; 64 compatible = "ti,twl6030-vana";
65 }; 65 };
66 66
67 vcxio: regulator@8 { 67 vcxio: regulator-vcxio {
68 compatible = "ti,twl6030-vcxio"; 68 compatible = "ti,twl6030-vcxio";
69 regulator-always-on; 69 regulator-always-on;
70 }; 70 };
71 71
72 vusb: regulator@9 { 72 vusb: regulator-vusb {
73 compatible = "ti,twl6030-vusb"; 73 compatible = "ti,twl6030-vusb";
74 }; 74 };
75 75
76 v1v8: regulator@10 { 76 v1v8: regulator-v1v8 {
77 compatible = "ti,twl6030-v1v8"; 77 compatible = "ti,twl6030-v1v8";
78 regulator-always-on; 78 regulator-always-on;
79 }; 79 };
80 80
81 v2v1: regulator@11 { 81 v2v1: regulator-v2v1 {
82 compatible = "ti,twl6030-v2v1"; 82 compatible = "ti,twl6030-v2v1";
83 regulator-always-on; 83 regulator-always-on;
84 }; 84 };
85 85
86 clk32kg: regulator@12 { 86 clk32kg: regulator-clk32kg {
87 compatible = "ti,twl6030-clk32kg"; 87 compatible = "ti,twl6030-clk32kg";
88 }; 88 };
89}; 89};
diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts
new file mode 100644
index 000000000000..567cf4e8ab84
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500-bv07.dts
@@ -0,0 +1,36 @@
1/*
2 * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/dts-v1/;
10/include/ "vt8500.dtsi"
11
12/ {
13 model = "Benign BV07 Netbook";
14
15 /*
16 * Display node is based on Sascha Hauer's patch on dri-devel.
17 * Added a bpp property to calculate the size of the framebuffer
18 * until the binding is formalized.
19 */
20 display: display@0 {
21 modes {
22 mode0: mode@0 {
23 hactive = <800>;
24 vactive = <480>;
25 hback-porch = <88>;
26 hfront-porch = <40>;
27 hsync-len = <0>;
28 vback-porch = <32>;
29 vfront-porch = <11>;
30 vsync-len = <1>;
31 clock = <0>; /* unused but required */
32 bpp = <16>; /* non-standard but required */
33 };
34 };
35 };
36};
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
new file mode 100644
index 000000000000..d8645e990b21
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -0,0 +1,116 @@
1/*
2 * vt8500.dtsi - Device tree file for VIA VT8500 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "via,vt8500";
13
14 soc {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "simple-bus";
18 ranges;
19 interrupt-parent = <&intc>;
20
21 intc: interrupt-controller@d8140000 {
22 compatible = "via,vt8500-intc";
23 interrupt-controller;
24 reg = <0xd8140000 0x10000>;
25 #interrupt-cells = <1>;
26 };
27
28 gpio: gpio-controller@d8110000 {
29 compatible = "via,vt8500-gpio";
30 gpio-controller;
31 reg = <0xd8110000 0x10000>;
32 #gpio-cells = <3>;
33 };
34
35 pmc@d8130000 {
36 compatible = "via,vt8500-pmc";
37 reg = <0xd8130000 0x1000>;
38
39 clocks {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 ref24: ref24M {
44 #clock-cells = <0>;
45 compatible = "fixed-clock";
46 clock-frequency = <24000000>;
47 };
48 };
49 };
50
51 timer@d8130100 {
52 compatible = "via,vt8500-timer";
53 reg = <0xd8130100 0x28>;
54 interrupts = <36>;
55 };
56
57 ehci@d8007900 {
58 compatible = "via,vt8500-ehci";
59 reg = <0xd8007900 0x200>;
60 interrupts = <43>;
61 };
62
63 uhci@d8007b00 {
64 compatible = "platform-uhci";
65 reg = <0xd8007b00 0x200>;
66 interrupts = <43>;
67 };
68
69 fb@d800e400 {
70 compatible = "via,vt8500-fb";
71 reg = <0xd800e400 0x400>;
72 interrupts = <12>;
73 display = <&display>;
74 default-mode = <&mode0>;
75 };
76
77 ge_rops@d8050400 {
78 compatible = "wm,prizm-ge-rops";
79 reg = <0xd8050400 0x100>;
80 };
81
82 uart@d8200000 {
83 compatible = "via,vt8500-uart";
84 reg = <0xd8200000 0x1040>;
85 interrupts = <32>;
86 clocks = <&ref24>;
87 };
88
89 uart@d82b0000 {
90 compatible = "via,vt8500-uart";
91 reg = <0xd82b0000 0x1040>;
92 interrupts = <33>;
93 clocks = <&ref24>;
94 };
95
96 uart@d8210000 {
97 compatible = "via,vt8500-uart";
98 reg = <0xd8210000 0x1040>;
99 interrupts = <47>;
100 clocks = <&ref24>;
101 };
102
103 uart@d82c0000 {
104 compatible = "via,vt8500-uart";
105 reg = <0xd82c0000 0x1040>;
106 interrupts = <50>;
107 clocks = <&ref24>;
108 };
109
110 rtc@d8100000 {
111 compatible = "via,vt8500-rtc";
112 reg = <0xd8100000 0x10000>;
113 interrupts = <48>;
114 };
115 };
116};
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts
new file mode 100644
index 000000000000..fd4e248074c6
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505-ref.dts
@@ -0,0 +1,36 @@
1/*
2 * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/dts-v1/;
10/include/ "wm8505.dtsi"
11
12/ {
13 model = "Wondermedia WM8505 Netbook";
14
15 /*
16 * Display node is based on Sascha Hauer's patch on dri-devel.
17 * Added a bpp property to calculate the size of the framebuffer
18 * until the binding is formalized.
19 */
20 display: display@0 {
21 modes {
22 mode0: mode@0 {
23 hactive = <800>;
24 vactive = <480>;
25 hback-porch = <88>;
26 hfront-porch = <40>;
27 hsync-len = <0>;
28 vback-porch = <32>;
29 vfront-porch = <11>;
30 vsync-len = <1>;
31 clock = <0>; /* unused but required */
32 bpp = <32>; /* non-standard but required */
33 };
34 };
35 };
36};
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
new file mode 100644
index 000000000000..b459691655ab
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -0,0 +1,143 @@
1/*
2 * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "wm,wm8505";
13
14 cpus {
15 cpu@0 {
16 compatible = "arm,arm926ejs";
17 };
18 };
19
20 soc {
21 #address-cells = <1>;
22 #size-cells = <1>;
23 compatible = "simple-bus";
24 ranges;
25 interrupt-parent = <&intc0>;
26
27 intc0: interrupt-controller@d8140000 {
28 compatible = "via,vt8500-intc";
29 interrupt-controller;
30 reg = <0xd8140000 0x10000>;
31 #interrupt-cells = <1>;
32 };
33
34 /* Secondary IC cascaded to intc0 */
35 intc1: interrupt-controller@d8150000 {
36 compatible = "via,vt8500-intc";
37 interrupt-controller;
38 #interrupt-cells = <1>;
39 reg = <0xD8150000 0x10000>;
40 interrupts = <56 57 58 59 60 61 62 63>;
41 };
42
43 gpio: gpio-controller@d8110000 {
44 compatible = "wm,wm8505-gpio";
45 gpio-controller;
46 reg = <0xd8110000 0x10000>;
47 #gpio-cells = <3>;
48 };
49
50 pmc@d8130000 {
51 compatible = "via,vt8500-pmc";
52 reg = <0xd8130000 0x1000>;
53 clocks {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 ref24: ref24M {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <24000000>;
61 };
62 };
63 };
64
65 timer@d8130100 {
66 compatible = "via,vt8500-timer";
67 reg = <0xd8130100 0x28>;
68 interrupts = <36>;
69 };
70
71 ehci@d8007100 {
72 compatible = "via,vt8500-ehci";
73 reg = <0xd8007100 0x200>;
74 interrupts = <43>;
75 };
76
77 uhci@d8007300 {
78 compatible = "platform-uhci";
79 reg = <0xd8007300 0x200>;
80 interrupts = <43>;
81 };
82
83 fb@d8050800 {
84 compatible = "wm,wm8505-fb";
85 reg = <0xd8050800 0x200>;
86 display = <&display>;
87 default-mode = <&mode0>;
88 };
89
90 ge_rops@d8050400 {
91 compatible = "wm,prizm-ge-rops";
92 reg = <0xd8050400 0x100>;
93 };
94
95 uart@d8200000 {
96 compatible = "via,vt8500-uart";
97 reg = <0xd8200000 0x1040>;
98 interrupts = <32>;
99 clocks = <&ref24>;
100 };
101
102 uart@d82b0000 {
103 compatible = "via,vt8500-uart";
104 reg = <0xd82b0000 0x1040>;
105 interrupts = <33>;
106 clocks = <&ref24>;
107 };
108
109 uart@d8210000 {
110 compatible = "via,vt8500-uart";
111 reg = <0xd8210000 0x1040>;
112 interrupts = <47>;
113 clocks = <&ref24>;
114 };
115
116 uart@d82c0000 {
117 compatible = "via,vt8500-uart";
118 reg = <0xd82c0000 0x1040>;
119 interrupts = <50>;
120 clocks = <&ref24>;
121 };
122
123 uart@d8370000 {
124 compatible = "via,vt8500-uart";
125 reg = <0xd8370000 0x1040>;
126 interrupts = <31>;
127 clocks = <&ref24>;
128 };
129
130 uart@d8380000 {
131 compatible = "via,vt8500-uart";
132 reg = <0xd8380000 0x1040>;
133 interrupts = <30>;
134 clocks = <&ref24>;
135 };
136
137 rtc@d8100000 {
138 compatible = "via,vt8500-rtc";
139 reg = <0xd8100000 0x10000>;
140 interrupts = <48>;
141 };
142 };
143};
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts
new file mode 100644
index 000000000000..cefd938f842f
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650-mid.dts
@@ -0,0 +1,36 @@
1/*
2 * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/dts-v1/;
10/include/ "wm8650.dtsi"
11
12/ {
13 model = "Wondermedia WM8650-MID Tablet";
14
15 /*
16 * Display node is based on Sascha Hauer's patch on dri-devel.
17 * Added a bpp property to calculate the size of the framebuffer
18 * until the binding is formalized.
19 */
20 display: display@0 {
21 modes {
22 mode0: mode@0 {
23 hactive = <800>;
24 vactive = <480>;
25 hback-porch = <88>;
26 hfront-porch = <40>;
27 hsync-len = <0>;
28 vback-porch = <32>;
29 vfront-porch = <11>;
30 vsync-len = <1>;
31 clock = <0>; /* unused but required */
32 bpp = <16>; /* non-standard but required */
33 };
34 };
35 };
36};
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
new file mode 100644
index 000000000000..83b9467559bb
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -0,0 +1,147 @@
1/*
2 * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "wm,wm8650";
13
14 soc {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "simple-bus";
18 ranges;
19 interrupt-parent = <&intc0>;
20
21 intc0: interrupt-controller@d8140000 {
22 compatible = "via,vt8500-intc";
23 interrupt-controller;
24 reg = <0xd8140000 0x10000>;
25 #interrupt-cells = <1>;
26 };
27
28 /* Secondary IC cascaded to intc0 */
29 intc1: interrupt-controller@d8150000 {
30 compatible = "via,vt8500-intc";
31 interrupt-controller;
32 #interrupt-cells = <1>;
33 reg = <0xD8150000 0x10000>;
34 interrupts = <56 57 58 59 60 61 62 63>;
35 };
36
37 gpio: gpio-controller@d8110000 {
38 compatible = "wm,wm8650-gpio";
39 gpio-controller;
40 reg = <0xd8110000 0x10000>;
41 #gpio-cells = <3>;
42 };
43
44 pmc@d8130000 {
45 compatible = "via,vt8500-pmc";
46 reg = <0xd8130000 0x1000>;
47
48 clocks {
49 #address-cells = <1>;
50 #size-cells = <0>;
51
52 ref25: ref25M {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
55 clock-frequency = <25000000>;
56 };
57
58 ref24: ref24M {
59 #clock-cells = <0>;
60 compatible = "fixed-clock";
61 clock-frequency = <24000000>;
62 };
63
64 plla: plla {
65 #clock-cells = <0>;
66 compatible = "wm,wm8650-pll-clock";
67 clocks = <&ref25>;
68 reg = <0x200>;
69 };
70
71 pllb: pllb {
72 #clock-cells = <0>;
73 compatible = "wm,wm8650-pll-clock";
74 clocks = <&ref25>;
75 reg = <0x204>;
76 };
77
78 arm: arm {
79 #clock-cells = <0>;
80 compatible = "via,vt8500-device-clock";
81 clocks = <&plla>;
82 divisor-reg = <0x300>;
83 };
84
85 sdhc: sdhc {
86 #clock-cells = <0>;
87 compatible = "via,vt8500-device-clock";
88 clocks = <&pllb>;
89 divisor-reg = <0x328>;
90 divisor-mask = <0x3f>;
91 enable-reg = <0x254>;
92 enable-bit = <18>;
93 };
94 };
95 };
96
97 timer@d8130100 {
98 compatible = "via,vt8500-timer";
99 reg = <0xd8130100 0x28>;
100 interrupts = <36>;
101 };
102
103 ehci@d8007900 {
104 compatible = "via,vt8500-ehci";
105 reg = <0xd8007900 0x200>;
106 interrupts = <43>;
107 };
108
109 uhci@d8007b00 {
110 compatible = "platform-uhci";
111 reg = <0xd8007b00 0x200>;
112 interrupts = <43>;
113 };
114
115 fb@d8050800 {
116 compatible = "wm,wm8505-fb";
117 reg = <0xd8050800 0x200>;
118 display = <&display>;
119 default-mode = <&mode0>;
120 };
121
122 ge_rops@d8050400 {
123 compatible = "wm,prizm-ge-rops";
124 reg = <0xd8050400 0x100>;
125 };
126
127 uart@d8200000 {
128 compatible = "via,vt8500-uart";
129 reg = <0xd8200000 0x1040>;
130 interrupts = <32>;
131 clocks = <&ref24>;
132 };
133
134 uart@d82b0000 {
135 compatible = "via,vt8500-uart";
136 reg = <0xd82b0000 0x1040>;
137 interrupts = <33>;
138 clocks = <&ref24>;
139 };
140
141 rtc@d8100000 {
142 compatible = "via,vt8500-rtc";
143 reg = <0xd8100000 0x10000>;
144 interrupts = <48>;
145 };
146 };
147};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 05:39:40 -0500