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-rw-r--r--arch/arm/boot/dts/Makefile231
-rw-r--r--arch/arm/boot/dts/alphascale-asm9260-devkit.dts13
-rw-r--r--arch/arm/boot/dts/alphascale-asm9260.dtsi63
-rw-r--r--arch/arm/boot/dts/am4372.dtsi16
-rw-r--r--arch/arm/boot/dts/am437x-gp-evm.dts106
-rw-r--r--arch/arm/boot/dts/am437x-idk-evm.dts405
-rw-r--r--arch/arm/boot/dts/am437x-sk-evm.dts217
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts53
-rw-r--r--arch/arm/boot/dts/am57xx-beagle-x15.dts120
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts24
-rw-r--r--arch/arm/boot/dts/at91rm9200.dtsi12
-rw-r--r--arch/arm/boot/dts/at91rm9200ek.dts4
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi5
-rw-r--r--arch/arm/boot/dts/at91sam9261.dtsi5
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi12
-rw-r--r--arch/arm/boot/dts/at91sam9g20.dtsi9
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi7
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi12
-rw-r--r--arch/arm/boot/dts/at91sam9rl.dtsi5
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi5
-rw-r--r--arch/arm/boot/dts/at91sam9xe.dtsi60
-rw-r--r--arch/arm/boot/dts/atlas7-evb.dts110
-rw-r--r--arch/arm/boot/dts/atlas7.dtsi813
-rw-r--r--arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts68
-rw-r--r--arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts60
-rw-r--r--arch/arm/boot/dts/bcm4708-netgear-r6250.dts1
-rw-r--r--arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts1
-rw-r--r--arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts1
-rw-r--r--arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts68
-rw-r--r--arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts37
-rw-r--r--arch/arm/boot/dts/berlin2.dtsi2
-rw-r--r--arch/arm/boot/dts/berlin2cd.dtsi7
-rw-r--r--arch/arm/boot/dts/berlin2q.dtsi10
-rw-r--r--arch/arm/boot/dts/dm8168-evm.dts129
-rw-r--r--arch/arm/boot/dts/dm816x-clocks.dtsi250
-rw-r--r--arch/arm/boot/dts/dm816x.dtsi387
-rw-r--r--arch/arm/boot/dts/dra7.dtsi2
-rw-r--r--arch/arm/boot/dts/dra72-evm.dts77
-rw-r--r--arch/arm/boot/dts/ethernut5.dts2
-rw-r--r--arch/arm/boot/dts/hip01-ca9x2.dts51
-rw-r--r--arch/arm/boot/dts/hip01.dtsi110
-rw-r--r--arch/arm/boot/dts/marco-evb.dts54
-rw-r--r--arch/arm/boot/dts/marco.dtsi757
-rw-r--r--arch/arm/boot/dts/mt6589-aquaris5.dts12
-rw-r--r--arch/arm/boot/dts/mt6589.dtsi52
-rw-r--r--arch/arm/boot/dts/mt6592.dtsi15
-rw-r--r--arch/arm/boot/dts/mt8127-moose.dts4
-rw-r--r--arch/arm/boot/dts/mt8127.dtsi52
-rw-r--r--arch/arm/boot/dts/mt8135-evbp1.dts4
-rw-r--r--arch/arm/boot/dts/mt8135.dtsi54
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3x.dtsi58
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3x30.dtsi3
-rw-r--r--arch/arm/boot/dts/omap3-gta04.dtsi49
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts3
-rw-r--r--arch/arm/boot/dts/omap3-n950-n9.dtsi5
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3517.dts4
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3530.dts10
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3730.dts5
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-ifc6410.dts12
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064.dtsi2
-rw-r--r--arch/arm/boot/dts/r7s72100-genmai.dts2
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts2
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm.dts173
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi10
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva.dts4
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi115
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi39
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts15
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi62
-rw-r--r--arch/arm/boot/dts/r8a7791-henninger.dts4
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts19
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi69
-rw-r--r--arch/arm/boot/dts/r8a7794-alt.dts4
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi82
-rw-r--r--arch/arm/boot/dts/rk3288-evb-rk808.dts53
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi27
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi34
-rw-r--r--arch/arm/boot/dts/sama5d3xcm.dtsi1
-rw-r--r--arch/arm/boot/dts/sama5d3xmb.dtsi40
-rw-r--r--arch/arm/boot/dts/sama5d4.dtsi10
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts2
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi18
-rw-r--r--arch/arm/boot/dts/stih407-b2120.dts3
-rw-r--r--arch/arm/boot/dts/stih407-family.dtsi62
-rw-r--r--arch/arm/boot/dts/stih407.dtsi151
-rw-r--r--arch/arm/boot/dts/stih410.dtsi208
-rw-r--r--arch/arm/boot/dts/stih418-b2199.dts78
-rw-r--r--arch/arm/boot/dts/stih418-clock.dtsi348
-rw-r--r--arch/arm/boot/dts/stih418.dtsi99
-rw-r--r--arch/arm/boot/dts/stihxxx-b2120.dtsi13
90 files changed, 5323 insertions, 1149 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 968bc7a9a43b..89b732b6d6cf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1,5 +1,7 @@
1ifeq ($(CONFIG_OF),y) 1ifeq ($(CONFIG_OF),y)
2 2
3dtb-$(CONFIG_MACH_ASM9260) += \
4 alphascale-asm9260-devkit.dtb
3# Keep at91 dtb files sorted alphabetically for each SoC 5# Keep at91 dtb files sorted alphabetically for each SoC
4# rm9200 6# rm9200
5dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb 7dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb
@@ -51,33 +53,47 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
51# sama5d4 53# sama5d4
52dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb 54dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb
53 55
54dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb 56dtb-$(CONFIG_ARCH_ATLAS6) += \
55dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb 57 atlas6-evb.dtb
56dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 58dtb-$(CONFIG_ARCH_ATLAS7) += \
57dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b-plus.dtb 59 atlas7-evb.dtb
60dtb-$(CONFIG_ARCH_AXXIA) += \
61 axm5516-amarillo.dtb
62dtb-$(CONFIG_ARCH_BCM2835) += \
63 bcm2835-rpi-b.dtb \
64 bcm2835-rpi-b-plus.dtb
58dtb-$(CONFIG_ARCH_BCM_5301X) += \ 65dtb-$(CONFIG_ARCH_BCM_5301X) += \
59 bcm4708-buffalo-wzr-1750dhp.dtb \ 66 bcm4708-buffalo-wzr-1750dhp.dtb \
67 bcm4708-luxul-xwc-1000.dtb \
60 bcm4708-netgear-r6250.dtb \ 68 bcm4708-netgear-r6250.dtb \
61 bcm4708-netgear-r6300-v2.dtb \ 69 bcm4708-netgear-r6300-v2.dtb \
62 bcm47081-asus-rt-n18u.dtb \ 70 bcm47081-asus-rt-n18u.dtb \
63 bcm47081-buffalo-wzr-600dhp2.dtb 71 bcm47081-buffalo-wzr-600dhp2.dtb \
64dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb 72 bcm47081-buffalo-wzr-900dhp.dtb
65dtb-$(CONFIG_ARCH_BCM_CYGNUS) += bcm911360_entphn.dtb \ 73dtb-$(CONFIG_ARCH_BCM_63XX) += \
74 bcm963138dvt.dtb
75dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
76 bcm911360_entphn.dtb \
66 bcm911360k.dtb \ 77 bcm911360k.dtb \
67 bcm958300k.dtb 78 bcm958300k.dtb
68dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ 79dtb-$(CONFIG_ARCH_BCM_MOBILE) += \
80 bcm28155-ap.dtb \
69 bcm21664-garnet.dtb 81 bcm21664-garnet.dtb
70dtb-$(CONFIG_ARCH_BERLIN) += \ 82dtb-$(CONFIG_ARCH_BERLIN) += \
71 berlin2-sony-nsz-gs7.dtb \ 83 berlin2-sony-nsz-gs7.dtb \
72 berlin2cd-google-chromecast.dtb \ 84 berlin2cd-google-chromecast.dtb \
73 berlin2q-marvell-dmp.dtb 85 berlin2q-marvell-dmp.dtb
74dtb-$(CONFIG_ARCH_BRCMSTB) += \ 86dtb-$(CONFIG_ARCH_BRCMSTB) += \
75 bcm7445-bcm97445svmb.dtb 87 bcm7445-bcm97445svmb.dtb
76dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ 88dtb-$(CONFIG_ARCH_DAVINCI) += \
89 da850-enbw-cmc.dtb \
77 da850-evm.dtb 90 da850-evm.dtb
78dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb 91dtb-$(CONFIG_ARCH_EFM32) += \
79dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-monk.dtb \ 92 efm32gg-dk3750.dtb
80 exynos3250-rinato.dtb \ 93dtb-$(CONFIG_ARCH_EXYNOS3) += \
94 exynos3250-monk.dtb \
95 exynos3250-rinato.dtb
96dtb-$(CONFIG_ARCH_EXYNOS4) += \
81 exynos4210-origen.dtb \ 97 exynos4210-origen.dtb \
82 exynos4210-smdkv310.dtb \ 98 exynos4210-smdkv310.dtb \
83 exynos4210-trats.dtb \ 99 exynos4210-trats.dtb \
@@ -88,7 +104,8 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-monk.dtb \
88 exynos4412-origen.dtb \ 104 exynos4412-origen.dtb \
89 exynos4412-smdk4412.dtb \ 105 exynos4412-smdk4412.dtb \
90 exynos4412-tiny4412.dtb \ 106 exynos4412-tiny4412.dtb \
91 exynos4412-trats2.dtb \ 107 exynos4412-trats2.dtb
108dtb-$(CONFIG_ARCH_EXYNOS5) += \
92 exynos5250-arndale.dtb \ 109 exynos5250-arndale.dtb \
93 exynos5250-smdk5250.dtb \ 110 exynos5250-smdk5250.dtb \
94 exynos5250-snow.dtb \ 111 exynos5250-snow.dtb \
@@ -101,17 +118,26 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-monk.dtb \
101 exynos5440-sd5v1.dtb \ 118 exynos5440-sd5v1.dtb \
102 exynos5440-ssdk5440.dtb \ 119 exynos5440-ssdk5440.dtb \
103 exynos5800-peach-pi.dtb 120 exynos5800-peach-pi.dtb
104dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb 121dtb-$(CONFIG_ARCH_HI3xxx) += \
105dtb-$(CONFIG_ARCH_HIX5HD2) += hisi-x5hd2-dkb.dtb 122 hi3620-hi4511.dtb
106dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ 123dtb-$(CONFIG_ARCH_HIX5HD2) += \
124 hisi-x5hd2-dkb.dtb
125dtb-$(CONFIG_ARCH_HIGHBANK) += \
126 highbank.dtb \
107 ecx-2000.dtb 127 ecx-2000.dtb
108dtb-$(CONFIG_ARCH_HIP04) += hip04-d01.dtb 128dtb-$(CONFIG_ARCH_HIP01) += \
109dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ 129 hip01-ca9x2.dtb
130dtb-$(CONFIG_ARCH_HIP04) += \
131 hip04-d01.dtb
132dtb-$(CONFIG_ARCH_INTEGRATOR) += \
133 integratorap.dtb \
110 integratorcp.dtb 134 integratorcp.dtb
111dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \ 135dtb-$(CONFIG_ARCH_KEYSTONE) += \
136 k2hk-evm.dtb \
112 k2l-evm.dtb \ 137 k2l-evm.dtb \
113 k2e-evm.dtb 138 k2e-evm.dtb
114dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \ 139dtb-$(CONFIG_MACH_KIRKWOOD) += \
140 kirkwood-b3.dtb \
115 kirkwood-blackarmor-nas220.dtb \ 141 kirkwood-blackarmor-nas220.dtb \
116 kirkwood-cloudbox.dtb \ 142 kirkwood-cloudbox.dtb \
117 kirkwood-d2net.dtb \ 143 kirkwood-d2net.dtb \
@@ -176,37 +202,47 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
176 kirkwood-ts219-6282.dtb \ 202 kirkwood-ts219-6282.dtb \
177 kirkwood-ts419-6281.dtb \ 203 kirkwood-ts419-6281.dtb \
178 kirkwood-ts419-6282.dtb 204 kirkwood-ts419-6282.dtb
179dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb 205dtb-$(CONFIG_ARCH_LPC32XX) += \
180dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb 206 ea3250.dtb phy3250.dtb
181dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb 207dtb-$(CONFIG_MACH_MESON6) += \
182dtb-$(CONFIG_ARCH_MMP) += pxa168-aspenite.dtb \ 208 meson6-atv1200.dtb
209dtb-$(CONFIG_ARCH_MMP) += \
210 pxa168-aspenite.dtb \
183 pxa910-dkb.dtb \ 211 pxa910-dkb.dtb \
184 mmp2-brownstone.dtb 212 mmp2-brownstone.dtb
185dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb 213dtb-$(CONFIG_ARCH_MOXART) += \
186dtb-$(CONFIG_ARCH_MXC) += \ 214 moxart-uc7112lx.dtb
215dtb-$(CONFIG_SOC_IMX1) += \
187 imx1-ads.dtb \ 216 imx1-ads.dtb \
188 imx1-apf9328.dtb \ 217 imx1-apf9328.dtb
218dtb-$(CONFIG_SOC_IMX25) += \
189 imx25-eukrea-mbimxsd25-baseboard.dtb \ 219 imx25-eukrea-mbimxsd25-baseboard.dtb \
190 imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ 220 imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \
191 imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ 221 imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \
192 imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \ 222 imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \
193 imx25-karo-tx25.dtb \ 223 imx25-karo-tx25.dtb \
194 imx25-pdk.dtb \ 224 imx25-pdk.dtb
225dtb-$(CONFIG_SOC_IMX31) += \
195 imx27-apf27.dtb \ 226 imx27-apf27.dtb \
196 imx27-apf27dev.dtb \ 227 imx27-apf27dev.dtb \
197 imx27-eukrea-mbimxsd27-baseboard.dtb \ 228 imx27-eukrea-mbimxsd27-baseboard.dtb \
198 imx27-pdk.dtb \ 229 imx27-pdk.dtb \
199 imx27-phytec-phycore-rdk.dtb \ 230 imx27-phytec-phycore-rdk.dtb \
200 imx27-phytec-phycard-s-rdk.dtb \ 231 imx27-phytec-phycard-s-rdk.dtb
201 imx31-bug.dtb \ 232dtb-$(CONFIG_SOC_IMX31) += \
233 imx31-bug.dtb
234dtb-$(CONFIG_SOC_IMX35) += \
202 imx35-eukrea-mbimxsd35-baseboard.dtb \ 235 imx35-eukrea-mbimxsd35-baseboard.dtb \
203 imx35-pdk.dtb \ 236 imx35-pdk.dtb
204 imx50-evk.dtb \ 237dtb-$(CONFIG_SOC_IMX50) += \
238 imx50-evk.dtb
239dtb-$(CONFIG_SOC_IMX51) += \
205 imx51-apf51.dtb \ 240 imx51-apf51.dtb \
206 imx51-apf51dev.dtb \ 241 imx51-apf51dev.dtb \
207 imx51-babbage.dtb \ 242 imx51-babbage.dtb \
208 imx51-digi-connectcore-jsk.dtb \ 243 imx51-digi-connectcore-jsk.dtb \
209 imx51-eukrea-mbimxsd51-baseboard.dtb \ 244 imx51-eukrea-mbimxsd51-baseboard.dtb
245dtb-$(CONFIG_SOC_IMX53) += \
210 imx53-ard.dtb \ 246 imx53-ard.dtb \
211 imx53-m53evk.dtb \ 247 imx53-m53evk.dtb \
212 imx53-mba53.dtb \ 248 imx53-mba53.dtb \
@@ -215,7 +251,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
215 imx53-smd.dtb \ 251 imx53-smd.dtb \
216 imx53-tx53-x03x.dtb \ 252 imx53-tx53-x03x.dtb \
217 imx53-tx53-x13x.dtb \ 253 imx53-tx53-x13x.dtb \
218 imx53-voipac-bsb.dtb \ 254 imx53-voipac-bsb.dtb
255dtb-$(CONFIG_SOC_IMX6Q) += \
219 imx6dl-aristainetos_4.dtb \ 256 imx6dl-aristainetos_4.dtb \
220 imx6dl-aristainetos_7.dtb \ 257 imx6dl-aristainetos_7.dtb \
221 imx6dl-cubox-i.dtb \ 258 imx6dl-cubox-i.dtb \
@@ -266,16 +303,21 @@ dtb-$(CONFIG_ARCH_MXC) += \
266 imx6q-tx6q-1010-comtft.dtb \ 303 imx6q-tx6q-1010-comtft.dtb \
267 imx6q-tx6q-1020.dtb \ 304 imx6q-tx6q-1020.dtb \
268 imx6q-tx6q-1020-comtft.dtb \ 305 imx6q-tx6q-1020-comtft.dtb \
269 imx6q-tx6q-1110.dtb \ 306 imx6q-tx6q-1110.dtb
270 imx6sl-evk.dtb \ 307dtb-$(CONFIG_SOC_IMX6SL) += \
271 imx6sx-sdb.dtb \ 308 imx6sl-evk.dtb
309dtb-$(CONFIG_SOC_IMX6SX) += \
310 imx6sx-sdb.dtb
311dtb-$(CONFIG_SOC_LS1021A) += \
272 ls1021a-qds.dtb \ 312 ls1021a-qds.dtb \
273 ls1021a-twr.dtb \ 313 ls1021a-twr.dtb
314dtb-$(CONFIG_SOC_VF610) += \
274 vf500-colibri-eval-v3.dtb \ 315 vf500-colibri-eval-v3.dtb \
275 vf610-colibri-eval-v3.dtb \ 316 vf610-colibri-eval-v3.dtb \
276 vf610-cosmic.dtb \ 317 vf610-cosmic.dtb \
277 vf610-twr.dtb 318 vf610-twr.dtb
278dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ 319dtb-$(CONFIG_ARCH_MXS) += \
320 imx23-evk.dtb \
279 imx23-olinuxino.dtb \ 321 imx23-olinuxino.dtb \
280 imx23-stmp378x_devb.dtb \ 322 imx23-stmp378x_devb.dtb \
281 imx28-apf28.dtb \ 323 imx28-apf28.dtb \
@@ -296,17 +338,21 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
296 imx28-m28evk.dtb \ 338 imx28-m28evk.dtb \
297 imx28-sps1.dtb \ 339 imx28-sps1.dtb \
298 imx28-tx28.dtb 340 imx28-tx28.dtb
299dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb \ 341dtb-$(CONFIG_ARCH_NOMADIK) += \
342 ste-nomadik-s8815.dtb \
300 ste-nomadik-nhk15.dtb 343 ste-nomadik-nhk15.dtb
301dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \ 344dtb-$(CONFIG_ARCH_NSPIRE) += \
345 nspire-cx.dtb \
302 nspire-tp.dtb \ 346 nspire-tp.dtb \
303 nspire-clp.dtb 347 nspire-clp.dtb
304dtb-$(CONFIG_ARCH_OMAP2) += omap2420-h4.dtb \ 348dtb-$(CONFIG_ARCH_OMAP2) += \
349 omap2420-h4.dtb \
305 omap2420-n800.dtb \ 350 omap2420-n800.dtb \
306 omap2420-n810.dtb \ 351 omap2420-n810.dtb \
307 omap2420-n810-wimax.dtb \ 352 omap2420-n810-wimax.dtb \
308 omap2430-sdp.dtb 353 omap2430-sdp.dtb
309dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \ 354dtb-$(CONFIG_ARCH_OMAP3) += \
355 am3517-craneboard.dtb \
310 am3517-evm.dtb \ 356 am3517-evm.dtb \
311 am3517_mt_ventoux.dtb \ 357 am3517_mt_ventoux.dtb \
312 omap3430-sdp.dtb \ 358 omap3430-sdp.dtb \
@@ -350,7 +396,10 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
350 omap3-sbc-t3730.dtb \ 396 omap3-sbc-t3730.dtb \
351 omap3-thunder.dtb \ 397 omap3-thunder.dtb \
352 omap3-zoom3.dtb 398 omap3-zoom3.dtb
353dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \ 399dtb-$(CONFIG_SOC_TI81XX) += \
400 dm8168-evm.dtb
401dtb-$(CONFIG_SOC_AM33XX) += \
402 am335x-base0033.dtb \
354 am335x-bone.dtb \ 403 am335x-bone.dtb \
355 am335x-boneblack.dtb \ 404 am335x-boneblack.dtb \
356 am335x-evm.dtb \ 405 am335x-evm.dtb \
@@ -358,7 +407,8 @@ dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
358 am335x-nano.dtb \ 407 am335x-nano.dtb \
359 am335x-pepper.dtb \ 408 am335x-pepper.dtb \
360 am335x-lxm.dtb 409 am335x-lxm.dtb
361dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ 410dtb-$(CONFIG_ARCH_OMAP4) += \
411 omap4-duovero-parlor.dtb \
362 omap4-panda.dtb \ 412 omap4-panda.dtb \
363 omap4-panda-a4.dtb \ 413 omap4-panda-a4.dtb \
364 omap4-panda-es.dtb \ 414 omap4-panda-es.dtb \
@@ -366,20 +416,26 @@ dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \
366 omap4-sdp-es23plus.dtb \ 416 omap4-sdp-es23plus.dtb \
367 omap4-var-dvk-om44.dtb \ 417 omap4-var-dvk-om44.dtb \
368 omap4-var-stk-om44.dtb 418 omap4-var-stk-om44.dtb
369dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \ 419dtb-$(CONFIG_SOC_AM43XX) += \
420 am43x-epos-evm.dtb \
370 am437x-sk-evm.dtb \ 421 am437x-sk-evm.dtb \
422 am437x-idk-evm.dtb \
371 am437x-gp-evm.dtb 423 am437x-gp-evm.dtb
372dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \ 424dtb-$(CONFIG_SOC_OMAP5) += \
425 omap5-cm-t54.dtb \
373 omap5-sbc-t54.dtb \ 426 omap5-sbc-t54.dtb \
374 omap5-uevm.dtb 427 omap5-uevm.dtb
375dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \ 428dtb-$(CONFIG_SOC_DRA7XX) += \
429 dra7-evm.dtb \
376 am57xx-beagle-x15.dtb \ 430 am57xx-beagle-x15.dtb \
377 dra72-evm.dtb 431 dra72-evm.dtb
378dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \ 432dtb-$(CONFIG_ARCH_ORION5X) += \
433 orion5x-lacie-d2-network.dtb \
379 orion5x-lacie-ethernet-disk-mini-v2.dtb \ 434 orion5x-lacie-ethernet-disk-mini-v2.dtb \
380 orion5x-maxtor-shared-storage-2.dtb \ 435 orion5x-maxtor-shared-storage-2.dtb \
381 orion5x-rd88f5182-nas.dtb 436 orion5x-rd88f5182-nas.dtb
382dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb 437dtb-$(CONFIG_ARCH_PRIMA2) += \
438 prima2-evb.dtb
383dtb-$(CONFIG_ARCH_QCOM) += \ 439dtb-$(CONFIG_ARCH_QCOM) += \
384 qcom-apq8064-cm-qs600.dtb \ 440 qcom-apq8064-cm-qs600.dtb \
385 qcom-apq8064-ifc6410.dtb \ 441 qcom-apq8064-ifc6410.dtb \
@@ -390,17 +446,21 @@ dtb-$(CONFIG_ARCH_QCOM) += \
390 qcom-msm8660-surf.dtb \ 446 qcom-msm8660-surf.dtb \
391 qcom-msm8960-cdp.dtb \ 447 qcom-msm8960-cdp.dtb \
392 qcom-msm8974-sony-xperia-honami.dtb 448 qcom-msm8974-sony-xperia-honami.dtb
393dtb-$(CONFIG_ARCH_REALVIEW) += arm-realview-pb1176.dtb 449dtb-$(CONFIG_ARCH_REALVIEW) += \
450 arm-realview-pb1176.dtb
394dtb-$(CONFIG_ARCH_ROCKCHIP) += \ 451dtb-$(CONFIG_ARCH_ROCKCHIP) += \
395 rk3066a-bqcurie2.dtb \ 452 rk3066a-bqcurie2.dtb \
396 rk3066a-marsboard.dtb \ 453 rk3066a-marsboard.dtb \
397 rk3188-radxarock.dtb \ 454 rk3188-radxarock.dtb \
398 rk3288-evb-act8846.dtb \ 455 rk3288-evb-act8846.dtb \
399 rk3288-evb-rk808.dtb 456 rk3288-evb-rk808.dtb
400dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb 457dtb-$(CONFIG_ARCH_S3C24XX) += \
401dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ 458 s3c2416-smdk2416.dtb
459dtb-$(CONFIG_ARCH_S3C64XX) += \
460 s3c6410-mini6410.dtb \
402 s3c6410-smdk6410.dtb 461 s3c6410-smdk6410.dtb
403dtb-$(CONFIG_ARCH_S5PV210) += s5pv210-aquila.dtb \ 462dtb-$(CONFIG_ARCH_S5PV210) += \
463 s5pv210-aquila.dtb \
404 s5pv210-goni.dtb \ 464 s5pv210-goni.dtb \
405 s5pv210-smdkc110.dtb \ 465 s5pv210-smdkc110.dtb \
406 s5pv210-smdkv210.dtb \ 466 s5pv210-smdkv210.dtb \
@@ -416,34 +476,42 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
416 sh7372-mackerel.dtb \ 476 sh7372-mackerel.dtb \
417 sh73a0-kzm9g.dtb \ 477 sh73a0-kzm9g.dtb \
418 sh73a0-kzm9g-reference.dtb 478 sh73a0-kzm9g-reference.dtb
419dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ 479dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
480 emev2-kzm9d.dtb \
420 r7s72100-genmai.dtb \ 481 r7s72100-genmai.dtb \
482 r8a73a4-ape6evm.dtb \
421 r8a7740-armadillo800eva.dtb \ 483 r8a7740-armadillo800eva.dtb \
422 r8a7779-marzen.dtb \ 484 r8a7779-marzen.dtb \
423 r8a7790-lager.dtb \ 485 r8a7790-lager.dtb \
424 r8a7791-henninger.dtb \ 486 r8a7791-henninger.dtb \
425 r8a7791-koelsch.dtb \ 487 r8a7791-koelsch.dtb \
426 r8a7794-alt.dtb 488 r8a7794-alt.dtb
427dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ 489dtb-$(CONFIG_ARCH_SOCFPGA) += \
490 socfpga_arria5_socdk.dtb \
428 socfpga_arria10_socdk.dtb \ 491 socfpga_arria10_socdk.dtb \
429 socfpga_cyclone5_socdk.dtb \ 492 socfpga_cyclone5_socdk.dtb \
430 socfpga_cyclone5_sockit.dtb \ 493 socfpga_cyclone5_sockit.dtb \
431 socfpga_cyclone5_socrates.dtb \ 494 socfpga_cyclone5_socrates.dtb \
432 socfpga_vt.dtb 495 socfpga_vt.dtb
433dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ 496dtb-$(CONFIG_ARCH_SPEAR13XX) += \
497 spear1310-evb.dtb \
434 spear1340-evb.dtb 498 spear1340-evb.dtb
435dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ 499dtb-$(CONFIG_ARCH_SPEAR3XX) += \
500 spear300-evb.dtb \
436 spear310-evb.dtb \ 501 spear310-evb.dtb \
437 spear320-evb.dtb \ 502 spear320-evb.dtb \
438 spear320-hmi.dtb 503 spear320-hmi.dtb
439dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb 504dtb-$(CONFIG_ARCH_SPEAR6XX) += \
440dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \ 505 spear600-evb.dtb
506dtb-$(CONFIG_ARCH_STI) += \
507 stih407-b2120.dtb \
441 stih410-b2120.dtb \ 508 stih410-b2120.dtb \
442 stih415-b2000.dtb \ 509 stih415-b2000.dtb \
443 stih415-b2020.dtb \ 510 stih415-b2020.dtb \
444 stih416-b2000.dtb \ 511 stih416-b2000.dtb \
445 stih416-b2020.dtb \ 512 stih416-b2020.dtb \
446 stih416-b2020e.dtb 513 stih416-b2020e.dtb \
514 stih418-b2199.dtb
447dtb-$(CONFIG_MACH_SUN4I) += \ 515dtb-$(CONFIG_MACH_SUN4I) += \
448 sun4i-a10-a1000.dtb \ 516 sun4i-a10-a1000.dtb \
449 sun4i-a10-ba10-tvbox.dtb \ 517 sun4i-a10-ba10-tvbox.dtb \
@@ -479,7 +547,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
479 sun8i-a23-ippo-q8h-v5.dtb 547 sun8i-a23-ippo-q8h-v5.dtb
480dtb-$(CONFIG_MACH_SUN9I) += \ 548dtb-$(CONFIG_MACH_SUN9I) += \
481 sun9i-a80-optimus.dtb 549 sun9i-a80-optimus.dtb
482dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ 550dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
551 tegra20-harmony.dtb \
483 tegra20-iris-512.dtb \ 552 tegra20-iris-512.dtb \
484 tegra20-medcom-wide.dtb \ 553 tegra20-medcom-wide.dtb \
485 tegra20-paz00.dtb \ 554 tegra20-paz00.dtb \
@@ -488,34 +557,43 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
488 tegra20-tec.dtb \ 557 tegra20-tec.dtb \
489 tegra20-trimslice.dtb \ 558 tegra20-trimslice.dtb \
490 tegra20-ventana.dtb \ 559 tegra20-ventana.dtb \
491 tegra20-whistler.dtb \ 560 tegra20-whistler.dtb
561dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
492 tegra30-apalis-eval.dtb \ 562 tegra30-apalis-eval.dtb \
493 tegra30-beaver.dtb \ 563 tegra30-beaver.dtb \
494 tegra30-cardhu-a02.dtb \ 564 tegra30-cardhu-a02.dtb \
495 tegra30-cardhu-a04.dtb \ 565 tegra30-cardhu-a04.dtb \
496 tegra30-colibri-eval-v3.dtb \ 566 tegra30-colibri-eval-v3.dtb
567dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \
497 tegra114-dalmore.dtb \ 568 tegra114-dalmore.dtb \
498 tegra114-roth.dtb \ 569 tegra114-roth.dtb \
499 tegra114-tn7.dtb \ 570 tegra114-tn7.dtb
571dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
500 tegra124-jetson-tk1.dtb \ 572 tegra124-jetson-tk1.dtb \
501 tegra124-nyan-big.dtb \ 573 tegra124-nyan-big.dtb \
502 tegra124-venice2.dtb 574 tegra124-venice2.dtb
503dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb 575dtb-$(CONFIG_ARCH_U300) += \
504dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ 576 ste-u300.dtb
577dtb-$(CONFIG_ARCH_U8500) += \
578 ste-snowball.dtb \
505 ste-hrefprev60-stuib.dtb \ 579 ste-hrefprev60-stuib.dtb \
506 ste-hrefprev60-tvk.dtb \ 580 ste-hrefprev60-tvk.dtb \
507 ste-hrefv60plus-stuib.dtb \ 581 ste-hrefv60plus-stuib.dtb \
508 ste-hrefv60plus-tvk.dtb \ 582 ste-hrefv60plus-tvk.dtb \
509 ste-ccu8540.dtb \ 583 ste-ccu8540.dtb \
510 ste-ccu9540.dtb 584 ste-ccu9540.dtb
511dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ 585dtb-$(CONFIG_ARCH_VERSATILE) += \
586 versatile-ab.dtb \
512 versatile-pb.dtb 587 versatile-pb.dtb
513dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ 588dtb-$(CONFIG_ARCH_VEXPRESS) += \
589 vexpress-v2p-ca5s.dtb \
514 vexpress-v2p-ca9.dtb \ 590 vexpress-v2p-ca9.dtb \
515 vexpress-v2p-ca15-tc1.dtb \ 591 vexpress-v2p-ca15-tc1.dtb \
516 vexpress-v2p-ca15_a7.dtb 592 vexpress-v2p-ca15_a7.dtb
517dtb-$(CONFIG_ARCH_VIRT) += xenvm-4.2.dtb 593dtb-$(CONFIG_ARCH_VIRT) += \
518dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ 594 xenvm-4.2.dtb
595dtb-$(CONFIG_ARCH_VT8500) += \
596 vt8500-bv07.dtb \
519 wm8505-ref.dtb \ 597 wm8505-ref.dtb \
520 wm8650-mid.dtb \ 598 wm8650-mid.dtb \
521 wm8750-apc8750.dtb \ 599 wm8750-apc8750.dtb \
@@ -549,17 +627,18 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \
549 armada-xp-netgear-rn2120.dtb \ 627 armada-xp-netgear-rn2120.dtb \
550 armada-xp-openblocks-ax3-4.dtb \ 628 armada-xp-openblocks-ax3-4.dtb \
551 armada-xp-synology-ds414.dtb 629 armada-xp-synology-ds414.dtb
552dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \ 630dtb-$(CONFIG_MACH_DOVE) += \
631 dove-cm-a510.dtb \
553 dove-cubox.dtb \ 632 dove-cubox.dtb \
554 dove-cubox-es.dtb \ 633 dove-cubox-es.dtb \
555 dove-d2plug.dtb \ 634 dove-d2plug.dtb \
556 dove-d3plug.dtb \ 635 dove-d3plug.dtb \
557 dove-dove-db.dtb 636 dove-dove-db.dtb
558dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb \ 637dtb-$(CONFIG_ARCH_MEDIATEK) += \
638 mt6589-aquaris5.dtb \
559 mt6592-evb.dtb \ 639 mt6592-evb.dtb \
560 mt8127-moose.dtb \ 640 mt8127-moose.dtb \
561 mt8135-evbp1.dtb 641 mt8135-evbp1.dtb
562
563endif 642endif
564 643
565always := $(dtb-y) 644always := $(dtb-y)
diff --git a/arch/arm/boot/dts/alphascale-asm9260-devkit.dts b/arch/arm/boot/dts/alphascale-asm9260-devkit.dts
new file mode 100644
index 000000000000..c77e2c902fb6
--- /dev/null
+++ b/arch/arm/boot/dts/alphascale-asm9260-devkit.dts
@@ -0,0 +1,13 @@
1/*
2 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
3 *
4 * Licensed under the X11 license or the GPL v2 (or later)
5 */
6
7/dts-v1/;
8#include "alphascale-asm9260.dtsi"
9
10/ {
11 model = "Alphascale asm9260 Development Kit";
12 compatible = "alphascale,asm9260devkit", "alphascale,asm9260";
13};
diff --git a/arch/arm/boot/dts/alphascale-asm9260.dtsi b/arch/arm/boot/dts/alphascale-asm9260.dtsi
new file mode 100644
index 000000000000..907fc7bfc418
--- /dev/null
+++ b/arch/arm/boot/dts/alphascale-asm9260.dtsi
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
3 *
4 * Licensed under the X11 license or the GPL v2 (or later)
5 */
6
7#include "skeleton.dtsi"
8#include <dt-bindings/clock/alphascale,asm9260.h>
9
10/ {
11 interrupt-parent = <&icoll>;
12
13 memory {
14 device_type = "memory";
15 reg = <0x20000000 0x2000000>;
16 };
17
18 cpus {
19 #address-cells = <0>;
20 #size-cells = <0>;
21
22 cpu {
23 compatible = "arm,arm926ej-s";
24 device_type = "cpu";
25 clocks = <&acc CLKID_SYS_CPU>;
26 };
27 };
28
29 osc24m: oscillator {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <24000000>;
33 clock-accuracy = <30000>;
34 };
35
36 soc {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "simple-bus";
40 ranges;
41
42 acc: clock-controller@80040000 {
43 compatible = "alphascale,asm9260-clock-controller";
44 #clock-cells = <1>;
45 clocks = <&osc24m>;
46 reg = <0x80040000 0x204>;
47 };
48
49 icoll: interrupt-controller@80054000 {
50 compatible = "alphascale,asm9260-icoll";
51 interrupt-controller;
52 #interrupt-cells = <1>;
53 reg = <0x80054000 0x200>;
54 };
55
56 timer0: timer@80088000 {
57 compatible = "alphascale,asm9260-timer";
58 reg = <0x80088000 0x4000>;
59 clocks = <&acc CLKID_AHB_TIMER0>;
60 interrupts = <29>;
61 };
62 };
63};
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index b62a1cd776cd..1943fc333e7c 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -948,6 +948,22 @@
948 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 948 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
949 status = "disabled"; 949 status = "disabled";
950 }; 950 };
951
952 vpfe0: vpfe@48326000 {
953 compatible = "ti,am437x-vpfe";
954 reg = <0x48326000 0x2000>;
955 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
956 ti,hwmods = "vpfe0";
957 status = "disabled";
958 };
959
960 vpfe1: vpfe@48328000 {
961 compatible = "ti,am437x-vpfe";
962 reg = <0x48328000 0x2000>;
963 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
964 ti,hwmods = "vpfe1";
965 status = "disabled";
966 };
951 }; 967 };
952}; 968};
953 969
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 7eaae4cf9f89..f84d9715a4a9 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -268,6 +268,78 @@
268 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ 268 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
269 >; 269 >;
270 }; 270 };
271
272 vpfe0_pins_default: vpfe0_pins_default {
273 pinctrl-single,pins = <
274 0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
275 0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
276 0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
277 0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
278 0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
279 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
280 0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
281 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
282 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
283 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
284 0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
285 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
286 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
287 >;
288 };
289
290 vpfe0_pins_sleep: vpfe0_pins_sleep {
291 pinctrl-single,pins = <
292 0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
293 0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
294 0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
295 0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
296 0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
297 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
298 0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
299 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
300 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
301 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
302 0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
303 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
304 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
305 >;
306 };
307
308 vpfe1_pins_default: vpfe1_pins_default {
309 pinctrl-single,pins = <
310 0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
311 0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
312 0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
313 0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
314 0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
315 0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
316 0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
317 0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
318 0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
319 0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
320 0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
321 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
322 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
323 >;
324 };
325
326 vpfe1_pins_sleep: vpfe1_pins_sleep {
327 pinctrl-single,pins = <
328 0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
329 0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
330 0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
331 0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
332 0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
333 0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
334 0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
335 0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
336 0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
337 0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
338 0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
339 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
340 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
341 >;
342 };
271}; 343};
272 344
273&i2c0 { 345&i2c0 {
@@ -545,3 +617,37 @@
545 pinctrl-0 = <&dcan1_default>; 617 pinctrl-0 = <&dcan1_default>;
546 status = "okay"; 618 status = "okay";
547}; 619};
620
621&vpfe0 {
622 status = "okay";
623 pinctrl-names = "default", "sleep";
624 pinctrl-0 = <&vpfe0_pins_default>;
625 pinctrl-1 = <&vpfe0_pins_sleep>;
626
627 port {
628 vpfe0_ep: endpoint {
629 /* remote-endpoint = <&sensor>; add once we have it */
630 ti,am437x-vpfe-interface = <0>;
631 bus-width = <8>;
632 hsync-active = <0>;
633 vsync-active = <0>;
634 };
635 };
636};
637
638&vpfe1 {
639 status = "okay";
640 pinctrl-names = "default", "sleep";
641 pinctrl-0 = <&vpfe1_pins_default>;
642 pinctrl-1 = <&vpfe1_pins_sleep>;
643
644 port {
645 vpfe1_ep: endpoint {
646 /* remote-endpoint = <&sensor>; add once we have it */
647 ti,am437x-vpfe-interface = <0>;
648 bus-width = <8>;
649 hsync-active = <0>;
650 vsync-active = <0>;
651 };
652 };
653};
diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts
new file mode 100644
index 000000000000..f9a17e2ca8cb
--- /dev/null
+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
@@ -0,0 +1,405 @@
1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include "am4372.dtsi"
12#include <dt-bindings/pinctrl/am43xx.h>
13#include <dt-bindings/pwm/pwm.h>
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/input/input.h>
16
17/ {
18 model = "TI AM437x Industrial Development Kit";
19 compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43";
20
21 v24_0d: fixed-regulator-v24_0d {
22 compatible = "regulator-fixed";
23 regulator-name = "V24_0D";
24 regulator-min-microvolt = <24000000>;
25 regulator-max-microvolt = <24000000>;
26 regulator-always-on;
27 regulator-boot-on;
28 };
29
30 v3_3d: fixed-regulator-v3_3d {
31 compatible = "regulator-fixed";
32 regulator-name = "V3_3D";
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 regulator-always-on;
36 regulator-boot-on;
37 vin-supply = <&v24_0d>;
38 };
39
40 vdd_corereg: fixed-regulator-vdd_corereg {
41 compatible = "regulator-fixed";
42 regulator-name = "VDD_COREREG";
43 regulator-min-microvolt = <1100000>;
44 regulator-max-microvolt = <1100000>;
45 regulator-always-on;
46 regulator-boot-on;
47 vin-supply = <&v24_0d>;
48 };
49
50 vdd_core: fixed-regulator-vdd_core {
51 compatible = "regulator-fixed";
52 regulator-name = "VDD_CORE";
53 regulator-min-microvolt = <1100000>;
54 regulator-max-microvolt = <1100000>;
55 regulator-always-on;
56 regulator-boot-on;
57 vin-supply = <&vdd_corereg>;
58 };
59
60 v1_8dreg: fixed-regulator-v1_8dreg{
61 compatible = "regulator-fixed";
62 regulator-name = "V1_8DREG";
63 regulator-min-microvolt = <1800000>;
64 regulator-max-microvolt = <1800000>;
65 regulator-always-on;
66 regulator-boot-on;
67 vin-supply = <&v24_0d>;
68 };
69
70 v1_8d: fixed-regulator-v1_8d{
71 compatible = "regulator-fixed";
72 regulator-name = "V1_8D";
73 regulator-min-microvolt = <1800000>;
74 regulator-max-microvolt = <1800000>;
75 regulator-always-on;
76 regulator-boot-on;
77 vin-supply = <&v1_8dreg>;
78 };
79
80 v1_5dreg: fixed-regulator-v1_5dreg{
81 compatible = "regulator-fixed";
82 regulator-name = "V1_5DREG";
83 regulator-min-microvolt = <1500000>;
84 regulator-max-microvolt = <1500000>;
85 regulator-always-on;
86 regulator-boot-on;
87 vin-supply = <&v24_0d>;
88 };
89
90 v1_5d: fixed-regulator-v1_5d{
91 compatible = "regulator-fixed";
92 regulator-name = "V1_5D";
93 regulator-min-microvolt = <1500000>;
94 regulator-max-microvolt = <1500000>;
95 regulator-always-on;
96 regulator-boot-on;
97 vin-supply = <&v1_5dreg>;
98 };
99
100 gpio_keys: gpio_keys {
101 compatible = "gpio-keys";
102 pinctrl-names = "default";
103 pinctrl-0 = <&gpio_keys_pins_default>;
104 #address-cells = <1>;
105 #size-cells = <0>;
106
107 switch@0 {
108 label = "power-button";
109 linux,code = <KEY_POWER>;
110 gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
111 };
112 };
113};
114
115&am43xx_pinmux {
116 gpio_keys_pins_default: gpio_keys_pins_default {
117 pinctrl-single,pins = <
118 0x1b8 (PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */
119 >;
120 };
121
122 i2c0_pins_default: i2c0_pins_default {
123 pinctrl-single,pins = <
124 0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
125 0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
126 >;
127 };
128
129 i2c0_pins_sleep: i2c0_pins_sleep {
130 pinctrl-single,pins = <
131 0x188 (PIN_INPUT_PULLDOWN | MUX_MODE7)
132 0x18c (PIN_INPUT_PULLDOWN | MUX_MODE7)
133 >;
134 };
135
136 i2c1_pins_default: i2c1_pins_default {
137 pinctrl-single,pins = <
138 0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
139 0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
140 >;
141 };
142
143 i2c1_pins_sleep: i2c1_pins_sleep {
144 pinctrl-single,pins = <
145 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_cs0.i2c1_scl */
146 0x158 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d1.i2c1_sda */
147 >;
148 };
149
150 mmc1_pins_default: pinmux_mmc1_pins_default {
151 pinctrl-single,pins = <
152 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
153 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
154 0x1f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
155 0x1f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
156 0x1f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
157 0x1fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
158 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
159 >;
160 };
161
162 mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
163 pinctrl-single,pins = <
164 0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7)
165 0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7)
166 0x1f0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
167 0x1f4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
168 0x1f8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
169 0x1fc (PIN_INPUT_PULLDOWN | MUX_MODE7)
170 0x160 (PIN_INPUT_PULLDOWN | MUX_MODE7)
171 >;
172 };
173
174 ecap0_pins_default: backlight_pins_default {
175 pinctrl-single,pins = <
176 0x164 (PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */
177 >;
178 };
179
180 cpsw_default: cpsw_default {
181 pinctrl-single,pins = <
182 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
183 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
184 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
185 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
186 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
187 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
188 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
189 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
190 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
191 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
192 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
193 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
194 >;
195 };
196
197 cpsw_sleep: cpsw_sleep {
198 pinctrl-single,pins = <
199 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
200 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
201 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
202 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
203 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
204 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
205 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
206 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
207 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
208 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
209 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
210 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
211 >;
212 };
213
214 davinci_mdio_default: davinci_mdio_default {
215 pinctrl-single,pins = <
216 /* MDIO */
217 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
218 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
219 >;
220 };
221
222 davinci_mdio_sleep: davinci_mdio_sleep {
223 pinctrl-single,pins = <
224 /* MDIO reset value */
225 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
226 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
227 >;
228 };
229
230 qspi_pins_default: qspi_pins_default {
231 pinctrl-single,pins = <
232 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */
233 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
234 0x90 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
235 0x94 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
236 0x98 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */
237 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
238 >;
239 };
240
241 qspi_pins_sleep: qspi_pins_sleep{
242 pinctrl-single,pins = <
243 0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7)
244 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7)
245 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
246 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
247 0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
248 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
249 >;
250 };
251};
252
253&i2c0 {
254 status = "okay";
255 pinctrl-names = "default", "sleep";
256 pinctrl-0 = <&i2c0_pins_default>;
257 pinctrl-1 = <&i2c0_pins_default>;
258 clock-frequency = <400000>;
259
260 at24@50 {
261 compatible = "at24,24c256";
262 pagesize = <64>;
263 reg = <0x50>;
264 };
265};
266
267&i2c1 {
268 status = "okay";
269 pinctrl-names = "default", "sleep";
270 pinctrl-0 = <&i2c1_pins_default>;
271 pinctrl-1 = <&i2c1_pins_default>;
272 clock-frequency = <400000>;
273
274 tps: tps62362@60 {
275 compatible = "ti,tps62362";
276 regulator-name = "VDD_MPU";
277 regulator-min-microvolt = <950000>;
278 regulator-max-microvolt = <1330000>;
279 regulator-boot-on;
280 regulator-always-on;
281 ti,vsel0-state-high;
282 ti,vsel1-state-high;
283 vin-supply = <&v3_3d>;
284 };
285};
286
287&epwmss0 {
288 status = "okay";
289};
290
291&ecap0 {
292 status = "okay";
293 pinctrl-names = "default";
294 pinctrl-0 = <&ecap0_pins_default>;
295};
296
297&gpio0 {
298 status = "okay";
299};
300
301&gpio1 {
302 status = "okay";
303};
304
305&gpio4 {
306 status = "okay";
307};
308
309&gpio5 {
310 status = "okay";
311};
312
313&mmc1 {
314 status = "okay";
315 pinctrl-names = "default", "sleep";
316 pinctrl-0 = <&mmc1_pins_default>;
317 pinctrl-1 = <&mmc1_pins_sleep>;
318 vmmc-supply = <&v3_3d>;
319 bus-width = <4>;
320 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
321};
322
323&qspi {
324 status = "okay";
325 pinctrl-names = "default", "sleep";
326 pinctrl-0 = <&qspi_pins_default>;
327 pinctrl-1 = <&qspi_pins_sleep>;
328
329 spi-max-frequency = <48000000>;
330 m25p80@0 {
331 compatible = "mx66l51235l";
332 spi-max-frequency = <48000000>;
333 reg = <0>;
334 spi-cpol;
335 spi-cpha;
336 spi-tx-bus-width = <1>;
337 spi-rx-bus-width = <4>;
338 #address-cells = <1>;
339 #size-cells = <1>;
340
341 /*
342 * MTD partition table. The ROM checks the first 512KiB for a
343 * valid file to boot(XIP).
344 */
345 partition@0 {
346 label = "QSPI.U_BOOT";
347 reg = <0x00000000 0x000080000>;
348 };
349 partition@1 {
350 label = "QSPI.U_BOOT.backup";
351 reg = <0x00080000 0x00080000>;
352 };
353 partition@2 {
354 label = "QSPI.U-BOOT-SPL_OS";
355 reg = <0x00100000 0x00010000>;
356 };
357 partition@3 {
358 label = "QSPI.U_BOOT_ENV";
359 reg = <0x00110000 0x00010000>;
360 };
361 partition@4 {
362 label = "QSPI.U-BOOT-ENV.backup";
363 reg = <0x00120000 0x00010000>;
364 };
365 partition@5 {
366 label = "QSPI.KERNEL";
367 reg = <0x00130000 0x0800000>;
368 };
369 partition@6 {
370 label = "QSPI.FILESYSTEM";
371 reg = <0x00930000 0x36D0000>;
372 };
373 };
374};
375
376&mac {
377 pinctrl-names = "default", "sleep";
378 pinctrl-0 = <&cpsw_default>;
379 pinctrl-1 = <&cpsw_sleep>;
380 status = "okay";
381};
382
383&davinci_mdio {
384 pinctrl-names = "default", "sleep";
385 pinctrl-0 = <&davinci_mdio_default>;
386 pinctrl-1 = <&davinci_mdio_sleep>;
387 status = "okay";
388};
389
390&cpsw_emac0 {
391 phy_id = <&davinci_mdio>, <0>;
392 phy-mode = "rgmii";
393};
394
395&rtc {
396 status = "okay";
397};
398
399&wdt {
400 status = "okay";
401};
402
403&cpu {
404 cpu0-supply = <&tps>;
405};
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index 53bbfc90b26a..832d24318f62 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -153,20 +153,26 @@
153 153
154 i2c0_pins: i2c0_pins { 154 i2c0_pins: i2c0_pins {
155 pinctrl-single,pins = < 155 pinctrl-single,pins = <
156 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 156 0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
157 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 157 0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
158 >; 158 >;
159 }; 159 };
160 160
161 i2c1_pins: i2c1_pins { 161 i2c1_pins: i2c1_pins {
162 pinctrl-single,pins = < 162 pinctrl-single,pins = <
163 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ 163 0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
164 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ 164 0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
165 >; 165 >;
166 }; 166 };
167 167
168 mmc1_pins: pinmux_mmc1_pins { 168 mmc1_pins: pinmux_mmc1_pins {
169 pinctrl-single,pins = < 169 pinctrl-single,pins = <
170 0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
171 0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
172 0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
173 0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
174 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
175 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
170 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 176 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
171 >; 177 >;
172 }; 178 };
@@ -184,35 +190,75 @@
184 >; 190 >;
185 }; 191 };
186 192
193 vpfe0_pins_default: vpfe0_pins_default {
194 pinctrl-single,pins = <
195 0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
196 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
197 0x1b8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/
198 0x1bc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/
199 0x1c0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
200 0x1c4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
201 0x1c8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
202 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
203 0x20c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
204 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
205 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
206 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
207 0x21c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
208 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
209 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
210 >;
211 };
212
213 vpfe0_pins_sleep: vpfe0_pins_sleep {
214 pinctrl-single,pins = <
215 0x1b0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
216 0x1b4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
217 0x1b8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
218 0x1bc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
219 0x1c0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
220 0x1c4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
221 0x1c8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
222 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
223 0x20c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
224 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
225 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
226 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
227 0x21c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
228 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
229 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
230 >;
231 };
232
187 cpsw_default: cpsw_default { 233 cpsw_default: cpsw_default {
188 pinctrl-single,pins = < 234 pinctrl-single,pins = <
189 /* Slave 1 */ 235 /* Slave 1 */
190 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ 236 0x12c (PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
191 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ 237 0x114 (PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
192 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ 238 0x128 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
193 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ 239 0x124 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
194 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ 240 0x120 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
195 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ 241 0x11c (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
196 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ 242 0x130 (PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
197 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ 243 0x118 (PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
198 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ 244 0x140 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
199 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ 245 0x13c (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
200 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ 246 0x138 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
201 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ 247 0x134 (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
202 248
203 /* Slave 2 */ 249 /* Slave 2 */
204 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ 250 0x58 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
205 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ 251 0x40 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
206 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ 252 0x54 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
207 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ 253 0x50 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
208 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ 254 0x4c (PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
209 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ 255 0x48 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
210 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ 256 0x5c (PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
211 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ 257 0x44 (PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */
212 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ 258 0x6c (PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
213 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ 259 0x68 (PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
214 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ 260 0x64 (PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
215 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ 261 0x60 (PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
216 >; 262 >;
217 }; 263 };
218 264
@@ -251,8 +297,8 @@
251 davinci_mdio_default: davinci_mdio_default { 297 davinci_mdio_default: davinci_mdio_default {
252 pinctrl-single,pins = < 298 pinctrl-single,pins = <
253 /* MDIO */ 299 /* MDIO */
254 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 300 0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
255 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 301 0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */
256 >; 302 >;
257 }; 303 };
258 304
@@ -266,46 +312,46 @@
266 312
267 dss_pins: dss_pins { 313 dss_pins: dss_pins {
268 pinctrl-single,pins = < 314 pinctrl-single,pins = <
269 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ 315 0x020 (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */
270 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1) 316 0x024 (PIN_OUTPUT | MUX_MODE1)
271 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1) 317 0x028 (PIN_OUTPUT | MUX_MODE1)
272 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1) 318 0x02c (PIN_OUTPUT | MUX_MODE1)
273 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1) 319 0x030 (PIN_OUTPUT | MUX_MODE1)
274 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1) 320 0x034 (PIN_OUTPUT | MUX_MODE1)
275 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1) 321 0x038 (PIN_OUTPUT | MUX_MODE1)
276 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ 322 0x03c (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */
277 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ 323 0x0a0 (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */
278 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 324 0x0a4 (PIN_OUTPUT | MUX_MODE0)
279 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 325 0x0a8 (PIN_OUTPUT | MUX_MODE0)
280 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0) 326 0x0ac (PIN_OUTPUT | MUX_MODE0)
281 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 327 0x0b0 (PIN_OUTPUT | MUX_MODE0)
282 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 328 0x0b4 (PIN_OUTPUT | MUX_MODE0)
283 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 329 0x0b8 (PIN_OUTPUT | MUX_MODE0)
284 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0) 330 0x0bc (PIN_OUTPUT | MUX_MODE0)
285 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 331 0x0c0 (PIN_OUTPUT | MUX_MODE0)
286 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 332 0x0c4 (PIN_OUTPUT | MUX_MODE0)
287 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 333 0x0c8 (PIN_OUTPUT | MUX_MODE0)
288 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0) 334 0x0cc (PIN_OUTPUT | MUX_MODE0)
289 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 335 0x0d0 (PIN_OUTPUT | MUX_MODE0)
290 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 336 0x0d4 (PIN_OUTPUT | MUX_MODE0)
291 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 337 0x0d8 (PIN_OUTPUT | MUX_MODE0)
292 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ 338 0x0dc (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */
293 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ 339 0x0e0 (PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */
294 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ 340 0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */
295 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ 341 0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */
296 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ 342 0x0ec (PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */
297 343
298 >; 344 >;
299 }; 345 };
300 346
301 qspi_pins: qspi_pins { 347 qspi_pins: qspi_pins {
302 pinctrl-single,pins = < 348 pinctrl-single,pins = <
303 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */ 349 0x7c (PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */
304 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ 350 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
305 0x90 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ 351 0x90 (PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
306 0x94 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ 352 0x94 (PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
307 0x98 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */ 353 0x98 (PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */
308 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ 354 0x9c (PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
309 >; 355 >;
310 }; 356 };
311 357
@@ -323,6 +369,18 @@
323 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ 369 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */
324 >; 370 >;
325 }; 371 };
372
373 usb1_pins: usb1_pins {
374 pinctrl-single,pins = <
375 0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
376 >;
377 };
378
379 usb2_pins: usb2_pins {
380 pinctrl-single,pins = <
381 0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
382 >;
383 };
326}; 384};
327 385
328&i2c0 { 386&i2c0 {
@@ -386,6 +444,11 @@
386 regulator-always-on; 444 regulator-always-on;
387 }; 445 };
388 446
447 power-button {
448 compatible = "ti,tps65218-pwrbutton";
449 status = "okay";
450 interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
451 };
389 }; 452 };
390 453
391 at24@50 { 454 at24@50 {
@@ -479,6 +542,8 @@
479&usb1 { 542&usb1 {
480 dr_mode = "peripheral"; 543 dr_mode = "peripheral";
481 status = "okay"; 544 status = "okay";
545 pinctrl-names = "default";
546 pinctrl-0 = <&usb1_pins>;
482}; 547};
483 548
484&usb2_phy2 { 549&usb2_phy2 {
@@ -488,6 +553,8 @@
488&usb2 { 553&usb2 {
489 dr_mode = "host"; 554 dr_mode = "host";
490 status = "okay"; 555 status = "okay";
556 pinctrl-names = "default";
557 pinctrl-0 = <&usb2_pins>;
491}; 558};
492 559
493&qspi { 560&qspi {
@@ -610,3 +677,25 @@
610&wdt { 677&wdt {
611 status = "okay"; 678 status = "okay";
612}; 679};
680
681&cpu {
682 cpu0-supply = <&dcdc2>;
683};
684
685&vpfe0 {
686 status = "okay";
687 pinctrl-names = "default", "sleep";
688 pinctrl-0 = <&vpfe0_pins_default>;
689 pinctrl-1 = <&vpfe0_pins_sleep>;
690
691 /* Camera port */
692 port {
693 vpfe0_ep: endpoint {
694 /* remote-endpoint = <&sensor>; add once we have it */
695 ti,am437x-vpfe-interface = <0>;
696 bus-width = <8>;
697 hsync-active = <0>;
698 vsync-active = <0>;
699 };
700 };
701};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 662261d6b2ca..257c099c347e 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -243,6 +243,42 @@
243 0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7) 243 0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7)
244 >; 244 >;
245 }; 245 };
246
247 vpfe1_pins_default: vpfe1_pins_default {
248 pinctrl-single,pins = <
249 0x1cc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */
250 0x1d0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */
251 0x1d4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */
252 0x1d8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */
253 0x1dc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */
254 0x1e8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */
255 0x1ec (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */
256 0x1f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */
257 0x1f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */
258 0x1f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */
259 0x1fc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */
260 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */
261 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */
262 >;
263 };
264
265 vpfe1_pins_sleep: vpfe1_pins_sleep {
266 pinctrl-single,pins = <
267 0x1cc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
268 0x1d0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
269 0x1d4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
270 0x1d8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
271 0x1dc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
272 0x1e8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
273 0x1ec (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
274 0x1f0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
275 0x1f4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
276 0x1f8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
277 0x1fc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
278 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
279 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
280 >;
281 };
246 }; 282 };
247 283
248 matrix_keypad: matrix_keypad@0 { 284 matrix_keypad: matrix_keypad@0 {
@@ -634,3 +670,20 @@
634 }; 670 };
635 }; 671 };
636}; 672};
673
674&vpfe1 {
675 status = "okay";
676 pinctrl-names = "default", "sleep";
677 pinctrl-0 = <&vpfe1_pins_default>;
678 pinctrl-1 = <&vpfe1_pins_sleep>;
679
680 port {
681 vpfe1_ep: endpoint {
682 /* remote-endpoint = <&sensor>; add once we have it */
683 ti,am437x-vpfe-interface = <0>;
684 bus-width = <8>;
685 hsync-active = <0>;
686 vsync-active = <0>;
687 };
688 };
689};
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 49edbda68cd5..c5d4ceabdd80 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -80,6 +80,14 @@
80 default-state = "off"; 80 default-state = "off";
81 }; 81 };
82 }; 82 };
83
84 gpio_fan: gpio_fan {
85 /* Based on 5v 500mA AFB02505HHB */
86 compatible = "gpio-fan";
87 gpios = <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>;
88 gpio-fan,speed-map = <0 0>,
89 <13000 1>;
90 };
83}; 91};
84 92
85&dra7_pmx_core { 93&dra7_pmx_core {
@@ -140,6 +148,86 @@
140 >; 148 >;
141 }; 149 };
142 150
151 cpsw_pins_default: cpsw_pins_default {
152 pinctrl-single,pins = <
153 /* Slave 1 */
154 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
155 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
156 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
157 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
158 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
159 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
160 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
161 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
162 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
163 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
164 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
165 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
166
167 /* Slave 2 */
168 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
169 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
170 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
171 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
172 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
173 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
174 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
175 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
176 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
177 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
178 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
179 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
180 >;
181
182 };
183
184 cpsw_pins_sleep: cpsw_pins_sleep {
185 pinctrl-single,pins = <
186 /* Slave 1 */
187 0x250 (PIN_INPUT | MUX_MODE15)
188 0x254 (PIN_INPUT | MUX_MODE15)
189 0x258 (PIN_INPUT | MUX_MODE15)
190 0x25c (PIN_INPUT | MUX_MODE15)
191 0x260 (PIN_INPUT | MUX_MODE15)
192 0x264 (PIN_INPUT | MUX_MODE15)
193 0x268 (PIN_INPUT | MUX_MODE15)
194 0x26c (PIN_INPUT | MUX_MODE15)
195 0x270 (PIN_INPUT | MUX_MODE15)
196 0x274 (PIN_INPUT | MUX_MODE15)
197 0x278 (PIN_INPUT | MUX_MODE15)
198 0x27c (PIN_INPUT | MUX_MODE15)
199
200 /* Slave 2 */
201 0x198 (PIN_INPUT | MUX_MODE15)
202 0x19c (PIN_INPUT | MUX_MODE15)
203 0x1a0 (PIN_INPUT | MUX_MODE15)
204 0x1a4 (PIN_INPUT | MUX_MODE15)
205 0x1a8 (PIN_INPUT | MUX_MODE15)
206 0x1ac (PIN_INPUT | MUX_MODE15)
207 0x1b0 (PIN_INPUT | MUX_MODE15)
208 0x1b4 (PIN_INPUT | MUX_MODE15)
209 0x1b8 (PIN_INPUT | MUX_MODE15)
210 0x1bc (PIN_INPUT | MUX_MODE15)
211 0x1c0 (PIN_INPUT | MUX_MODE15)
212 0x1c4 (PIN_INPUT | MUX_MODE15)
213 >;
214 };
215
216 davinci_mdio_pins_default: davinci_mdio_pins_default {
217 pinctrl-single,pins = <
218 /* MDIO */
219 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_mclk */
220 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_d */
221 >;
222 };
223
224 davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
225 pinctrl-single,pins = <
226 0x23c (PIN_INPUT | MUX_MODE15)
227 0x240 (PIN_INPUT | MUX_MODE15)
228 >;
229 };
230
143 tps659038_pins_default: tps659038_pins_default { 231 tps659038_pins_default: tps659038_pins_default {
144 pinctrl-single,pins = < 232 pinctrl-single,pins = <
145 0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ 233 0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
@@ -314,6 +402,12 @@
314 wakeup-source; 402 wakeup-source;
315 ti,palmas-long-press-seconds = <12>; 403 ti,palmas-long-press-seconds = <12>;
316 }; 404 };
405
406 tps659038_gpio: tps659038_gpio {
407 compatible = "ti,palmas-gpio";
408 gpio-controller;
409 #gpio-cells = <2>;
410 };
317 }; 411 };
318 412
319 tmp102: tmp102@48 { 413 tmp102: tmp102@48 {
@@ -365,6 +459,32 @@
365 pinctrl-0 = <&uart3_pins_default>; 459 pinctrl-0 = <&uart3_pins_default>;
366}; 460};
367 461
462&mac {
463 status = "okay";
464 pinctrl-names = "default", "sleep";
465 pinctrl-0 = <&cpsw_pins_default>;
466 pinctrl-1 = <&cpsw_pins_sleep>;
467 dual_emac;
468};
469
470&cpsw_emac0 {
471 phy_id = <&davinci_mdio>, <1>;
472 phy-mode = "rgmii";
473 dual_emac_res_vlan = <1>;
474};
475
476&cpsw_emac1 {
477 phy_id = <&davinci_mdio>, <2>;
478 phy-mode = "rgmii";
479 dual_emac_res_vlan = <2>;
480};
481
482&davinci_mdio {
483 pinctrl-names = "default", "sleep";
484 pinctrl-0 = <&davinci_mdio_pins_default>;
485 pinctrl-1 = <&davinci_mdio_pins_sleep>;
486};
487
368&mmc1 { 488&mmc1 {
369 status = "okay"; 489 status = "okay";
370 490
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 1466580be295..70b1943a86b1 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -203,27 +203,3 @@
203 compatible = "linux,spdif-dir"; 203 compatible = "linux,spdif-dir";
204 }; 204 };
205}; 205};
206
207&pinctrl {
208 /*
209 * These pins might be muxed as I2S by
210 * the bootloader, but it conflicts
211 * with the real I2S pins that are
212 * muxed using i2s_pins. We must mux
213 * those pins to a function other than
214 * I2S.
215 */
216 pinctrl-0 = <&hog_pins1 &hog_pins2>;
217 pinctrl-names = "default";
218
219 hog_pins1: hog-pins1 {
220 marvell,pins = "mpp6", "mpp8", "mpp10",
221 "mpp12", "mpp13";
222 marvell,function = "gpio";
223 };
224
225 hog_pins2: hog-pins2 {
226 marvell,pins = "mpp5", "mpp7", "mpp9";
227 marvell,function = "gpo";
228 };
229};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 6c97d4af61ee..21c2b504f977 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -66,6 +66,11 @@
66 }; 66 };
67 }; 67 };
68 68
69 sram: sram@00200000 {
70 compatible = "mmio-sram";
71 reg = <0x00200000 0x4000>;
72 };
73
69 ahb { 74 ahb {
70 compatible = "simple-bus"; 75 compatible = "simple-bus";
71 #address-cells = <1>; 76 #address-cells = <1>;
@@ -356,6 +361,13 @@
356 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 361 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
357 }; 362 };
358 363
364 rtc: rtc@fffffe00 {
365 compatible = "atmel,at91rm9200-rtc";
366 reg = <0xfffffe00 0x40>;
367 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
368 status = "disabled";
369 };
370
359 tcb0: timer@fffa0000 { 371 tcb0: timer@fffa0000 {
360 compatible = "atmel,at91rm9200-tcb"; 372 compatible = "atmel,at91rm9200-tcb";
361 reg = <0xfffa0000 0x100>; 373 reg = <0xfffa0000 0x100>;
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index 43eb779dd6f6..2a5d21247d7e 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -77,6 +77,10 @@
77 dbgu: serial@fffff200 { 77 dbgu: serial@fffff200 {
78 status = "okay"; 78 status = "okay";
79 }; 79 };
80
81 rtc: rtc@fffffe00 {
82 status = "okay";
83 };
80 }; 84 };
81 85
82 usb0: ohci@00300000 { 86 usb0: ohci@00300000 {
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index dd1313cbc314..fff0ee69aab4 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -69,6 +69,11 @@
69 }; 69 };
70 }; 70 };
71 71
72 sram0: sram@002ff000 {
73 compatible = "mmio-sram";
74 reg = <0x002ff000 0x2000>;
75 };
76
72 ahb { 77 ahb {
73 compatible = "simple-bus"; 78 compatible = "simple-bus";
74 #address-cells = <1>; 79 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index cdb9ed612109..e247b0b5fdab 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -60,6 +60,11 @@
60 }; 60 };
61 }; 61 };
62 62
63 sram: sram@00300000 {
64 compatible = "mmio-sram";
65 reg = <0x00300000 0x28000>;
66 };
67
63 ahb { 68 ahb {
64 compatible = "simple-bus"; 69 compatible = "simple-bus";
65 #address-cells = <1>; 70 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 1467750e3377..8a210d5033b1 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -62,6 +62,16 @@
62 }; 62 };
63 }; 63 };
64 64
65 sram0: sram@00300000 {
66 compatible = "mmio-sram";
67 reg = <0x00300000 0x14000>;
68 };
69
70 sram1: sram@00500000 {
71 compatible = "mmio-sram";
72 reg = <0x00300000 0x4000>;
73 };
74
65 ahb { 75 ahb {
66 compatible = "simple-bus"; 76 compatible = "simple-bus";
67 #address-cells = <1>; 77 #address-cells = <1>;
@@ -294,7 +304,7 @@
294 reg = <17>; 304 reg = <17>;
295 }; 305 };
296 306
297 ac91_clk: ac97_clk { 307 ac97_clk: ac97_clk {
298 #clock-cells = <0>; 308 #clock-cells = <0>;
299 reg = <18>; 309 reg = <18>;
300 }; 310 };
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index a50ee587a7af..f59301618163 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -16,6 +16,15 @@
16 reg = <0x20000000 0x08000000>; 16 reg = <0x20000000 0x08000000>;
17 }; 17 };
18 18
19 sram0: sram@002ff000 {
20 status = "disabled";
21 };
22
23 sram1: sram@002fc000 {
24 compatible = "mmio-sram";
25 reg = <0x002fc000 0x8000>;
26 };
27
19 ahb { 28 ahb {
20 apb { 29 apb {
21 i2c0: i2c@fffac000 { 30 i2c0: i2c@fffac000 {
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 2a8da8a884b4..ee80aa9c0759 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -74,6 +74,11 @@
74 }; 74 };
75 }; 75 };
76 76
77 sram: sram@00300000 {
78 compatible = "mmio-sram";
79 reg = <0x00300000 0x10000>;
80 };
81
77 ahb { 82 ahb {
78 compatible = "simple-bus"; 83 compatible = "simple-bus";
79 #address-cells = <1>; 84 #address-cells = <1>;
@@ -1287,7 +1292,6 @@
1287 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 1292 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1288 reg = <0x00700000 0x100000>; 1293 reg = <0x00700000 0x100000>;
1289 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1294 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1290 //TODO
1291 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; 1295 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1292 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; 1296 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
1293 status = "disabled"; 1297 status = "disabled";
@@ -1297,7 +1301,6 @@
1297 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1301 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1298 reg = <0x00800000 0x100000>; 1302 reg = <0x00800000 0x100000>;
1299 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1303 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1300 //TODO
1301 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; 1304 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1302 clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck"; 1305 clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck";
1303 status = "disabled"; 1306 status = "disabled";
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 68eb9aded164..c2666a7cb5b1 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -64,6 +64,11 @@
64 }; 64 };
65 }; 65 };
66 66
67 sram: sram@00300000 {
68 compatible = "mmio-sram";
69 reg = <0x00300000 0x8000>;
70 };
71
67 ahb { 72 ahb {
68 compatible = "simple-bus"; 73 compatible = "simple-bus";
69 #address-cells = <1>; 74 #address-cells = <1>;
@@ -893,6 +898,13 @@
893 status = "disabled"; 898 status = "disabled";
894 }; 899 };
895 900
901 rtc@fffffeb0 {
902 compatible = "atmel,at91rm9200-rtc";
903 reg = <0xfffffeb0 0x40>;
904 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
905 status = "disabled";
906 };
907
896 pwm0: pwm@f8034000 { 908 pwm0: pwm@f8034000 {
897 compatible = "atmel,at91sam9rl-pwm"; 909 compatible = "atmel,at91sam9rl-pwm";
898 reg = <0xf8034000 0x300>; 910 reg = <0xf8034000 0x300>;
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 72424371413e..40f645b8fe25 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -70,6 +70,11 @@
70 }; 70 };
71 }; 71 };
72 72
73 sram: sram@00300000 {
74 compatible = "mmio-sram";
75 reg = <0x00300000 0x10000>;
76 };
77
73 ahb { 78 ahb {
74 compatible = "simple-bus"; 79 compatible = "simple-bus";
75 #address-cells = <1>; 80 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index bbb3ba65165f..818dabdd8c0e 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -72,6 +72,11 @@
72 }; 72 };
73 }; 73 };
74 74
75 sram: sram@00300000 {
76 compatible = "mmio-sram";
77 reg = <0x00300000 0x8000>;
78 };
79
75 ahb { 80 ahb {
76 compatible = "simple-bus"; 81 compatible = "simple-bus";
77 #address-cells = <1>; 82 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9xe.dtsi b/arch/arm/boot/dts/at91sam9xe.dtsi
new file mode 100644
index 000000000000..0278f63b2daf
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9xe.dtsi
@@ -0,0 +1,60 @@
1/*
2 * at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC
3 *
4 * Copyright (C) 2015 Atmel,
5 * 2015 Alexandre Belloni <alexandre.Belloni@free-electrons.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include "at91sam9260.dtsi"
47
48/ {
49 model = "Atmel AT91SAM9XE family SoC";
50 compatible = "atmel,at91sam9xe", "atmel,at91sam9260";
51
52 sram0: sram@002ff000 {
53 status = "disabled";
54 };
55
56 sram1: sram@00300000 {
57 compatible = "mmio-sram";
58 reg = <0x00300000 0x4000>;
59 };
60};
diff --git a/arch/arm/boot/dts/atlas7-evb.dts b/arch/arm/boot/dts/atlas7-evb.dts
new file mode 100644
index 000000000000..49cf59a95572
--- /dev/null
+++ b/arch/arm/boot/dts/atlas7-evb.dts
@@ -0,0 +1,110 @@
1/*
2 * DTS file for CSR SiRFatlas7 Evaluation Board
3 *
4 * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/dts-v1/;
10
11/include/ "atlas7.dtsi"
12
13/ {
14 model = "CSR SiRFatlas7 Evaluation Board";
15 compatible = "sirf,atlas7-cb", "sirf,atlas7";
16
17 chosen {
18 bootargs = "console=ttySiRF1,115200 earlyprintk";
19 };
20
21 memory {
22 device_type = "memory";
23 reg = <0x40000000 0x20000000>;
24 };
25
26 reserved-memory {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 ranges;
30
31 vpp_reserved: vpp_mem@5e800000 {
32 compatible = "sirf,reserved-memory";
33 reg = <0x5e800000 0x800000>;
34 };
35
36 nanddisk_reserved: nanddisk@46000000 {
37 reg = <0x46000000 0x200000>;
38 no-map;
39 };
40 };
41
42
43 noc {
44 mediam {
45 nand@17050000 {
46 memory-region = <&nanddisk_reserved>;
47 };
48 };
49
50 gnssm {
51 spi1: spi@18200000 {
52 status = "okay";
53 spiflash: macronix@0{
54 status = "okay";
55 compatible = "macronix,mx25l6405d";
56 reg = <0>;
57 spi-max-frequency = <37500000>;
58 spi-cpha;
59 spi-cpol;
60 #address-cells = <1>;
61 #size-cells = <1>;
62 partitions@0 {
63 label = "myspiboot";
64 reg = <0x0 0x800000>;
65 };
66 };
67 };
68 };
69
70 btm {
71 uart6: uart@11000000 {
72 status = "okay";
73 sirf,uart-has-rtscts;
74 };
75 };
76
77 disp-iobg {
78 vpp@13110000 {
79 memory-region = <&vpp_reserved>;
80 };
81 };
82
83 display0: display@0 {
84 compatible = "lvds-panel";
85 source = "lvds.0";
86
87 bl-gpios = <&gpio_1 63 0>;
88 data-lines = <24>;
89
90 display-timings {
91 native-mode = <&timing0>;
92 timing0: timing0 {
93 clock-frequency = <60000000>;
94 hactive = <1024>;
95 vactive = <600>;
96 hfront-porch = <220>;
97 hback-porch = <100>;
98 hsync-len = <1>;
99 vback-porch = <10>;
100 vfront-porch = <25>;
101 vsync-len = <1>;
102 hsync-active = <0>;
103 vsync-active = <0>;
104 de-active = <1>;
105 pixelclk-active = <1>;
106 };
107 };
108 };
109 };
110};
diff --git a/arch/arm/boot/dts/atlas7.dtsi b/arch/arm/boot/dts/atlas7.dtsi
new file mode 100644
index 000000000000..a753178abc85
--- /dev/null
+++ b/arch/arm/boot/dts/atlas7.dtsi
@@ -0,0 +1,813 @@
1/*
2 * DTS file for CSR SiRFatlas7 SoC
3 *
4 * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/include/ "skeleton.dtsi"
10/ {
11 compatible = "sirf,atlas7";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
15 aliases {
16 serial0 = &uart0;
17 serial1 = &uart1;
18 serial2 = &uart2;
19 serial3 = &uart3;
20 serial4 = &uart4;
21 serial5 = &uart5;
22 serial6 = &uart6;
23 serial9 = &usp2;
24 };
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a7";
32 reg = <0>;
33 };
34 cpu@1 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a7";
37 reg = <1>;
38 };
39 };
40
41 noc {
42 compatible = "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
45 ranges = <0x10000000 0x10000000 0xc0000000>;
46
47 gic: interrupt-controller@10301000 {
48 compatible = "arm,cortex-a9-gic";
49 interrupt-controller;
50 #interrupt-cells = <3>;
51 reg = <0x10301000 0x1000>,
52 <0x10302000 0x0100>;
53 };
54
55 pmu_regulator: pmu_regulator@10E30020 {
56 compatible = "sirf,atlas7-pmu-ldo";
57 reg = <0x10E30020 0x4>;
58 ldo: ldo {
59 regulator-name = "ldo";
60 };
61 };
62
63 atlas7_codec: atlas7_codec@10E30000 {
64 #sound-dai-cells = <0>;
65 compatible = "sirf,atlas7-codec";
66 reg = <0x10E30000 0x400>;
67 clocks = <&car 62>;
68 ldo-supply = <&ldo>;
69 };
70
71 atlas7_iacc: atlas7_iacc@10D01000 {
72 #sound-dai-cells = <0>;
73 compatible = "sirf,atlas7-iacc";
74 reg = <0x10D01000 0x100>;
75 dmas = <&dmac3 0>, <&dmac3 7>, <&dmac3 8>,
76 <&dmac3 3>, <&dmac3 9>;
77 dma-names = "rx", "tx0", "tx1", "tx2", "tx3";
78 clocks = <&car 62>;
79 };
80
81 ipc@13240000 {
82 compatible = "sirf,atlas7-ipc";
83 ranges = <0x13240000 0x13240000 0x00010000>;
84 #address-cells = <1>;
85 #size-cells = <1>;
86
87 hwspinlock {
88 compatible = "sirf,hwspinlock";
89 reg = <0x13240000 0x00010000>;
90
91 num-spinlocks = <30>;
92 };
93
94 ns_m3_rproc@0 {
95 compatible = "sirf,ns2m30-rproc";
96 reg = <0x13240000 0x00010000>;
97 interrupts = <0 123 0>;
98 };
99
100 ns_m3_rproc@1 {
101 compatible = "sirf,ns2m31-rproc";
102 reg = <0x13240000 0x00010000>;
103 interrupts = <0 126 0>;
104 };
105
106 ns_kal_rproc@0 {
107 compatible = "sirf,ns2kal0-rproc";
108 reg = <0x13240000 0x00010000>;
109 interrupts = <0 124 0>;
110 };
111
112 ns_kal_rproc@1 {
113 compatible = "sirf,ns2kal1-rproc";
114 reg = <0x13240000 0x00010000>;
115 interrupts = <0 127 0>;
116 };
117 };
118
119 pinctrl: ioc@18880000 {
120 compatible = "sirf,atlas7-ioc";
121 reg = <0x18880000 0x1000>,
122 <0x10E40000 0x1000>;
123 };
124
125 pmipc {
126 compatible = "arteris, flexnoc", "simple-bus";
127 #address-cells = <1>;
128 #size-cells = <1>;
129 ranges = <0x13240000 0x13240000 0x00010000>;
130 pmipc@0x13240000 {
131 compatible = "sirf,atlas7-pmipc";
132 reg = <0x13240000 0x00010000>;
133 };
134 };
135
136 dramfw {
137 compatible = "arteris, flexnoc", "simple-bus";
138 #address-cells = <1>;
139 #size-cells = <1>;
140 ranges = <0x10830000 0x10830000 0x18000>;
141 dramfw@10820000 {
142 compatible = "sirf,nocfw-dramfw";
143 reg = <0x10830000 0x18000>;
144 };
145 };
146
147 spramfw {
148 compatible = "arteris, flexnoc", "simple-bus";
149 #address-cells = <1>;
150 #size-cells = <1>;
151 ranges = <0x10250000 0x10250000 0x3000>;
152 spramfw@10820000 {
153 compatible = "sirf,nocfw-spramfw";
154 reg = <0x10250000 0x3000>;
155 };
156 };
157
158 cpum {
159 compatible = "arteris, flexnoc", "simple-bus";
160 #address-cells = <1>;
161 #size-cells = <1>;
162 ranges = <0x10200000 0x10200000 0x3000>;
163 cpum@10200000 {
164 compatible = "sirf,nocfw-cpum";
165 reg = <0x10200000 0x3000>;
166 };
167 };
168
169 cgum {
170 compatible = "arteris, flexnoc", "simple-bus";
171 #address-cells = <1>;
172 #size-cells = <1>;
173 ranges = <0x18641000 0x18641000 0x3000>,
174 <0x18620000 0x18620000 0x1000>;
175
176 cgum@18641000 {
177 compatible = "sirf,nocfw-cgum";
178 reg = <0x18641000 0x3000>;
179 };
180
181 car: clock-controller@18620000 {
182 compatible = "sirf,atlas7-car";
183 reg = <0x18620000 0x1000>;
184 #clock-cells = <1>;
185 #reset-cells = <1>;
186 };
187 };
188
189 gnssm {
190 compatible = "arteris, flexnoc", "simple-bus";
191 #address-cells = <1>;
192 #size-cells = <1>;
193 ranges = <0x18000000 0x18000000 0x0000ffff>,
194 <0x18010000 0x18010000 0x1000>,
195 <0x18020000 0x18020000 0x1000>,
196 <0x18030000 0x18030000 0x1000>,
197 <0x18040000 0x18040000 0x1000>,
198 <0x18050000 0x18050000 0x1000>,
199 <0x18060000 0x18060000 0x1000>,
200 <0x18100000 0x18100000 0x3000>,
201 <0x18250000 0x18250000 0x10000>,
202 <0x18200000 0x18200000 0x1000>;
203
204 dmac0: dma-controller@18000000 {
205 cell-index = <0>;
206 compatible = "sirf,atlas7-dmac";
207 reg = <0x18000000 0x1000>;
208 interrupts = <0 12 0>;
209 clocks = <&car 89>;
210 dma-channels = <16>;
211 #dma-cells = <1>;
212 };
213
214 gnssmfw@0x18100000 {
215 compatible = "sirf,nocfw-gnssm";
216 reg = <0x18100000 0x3000>;
217 };
218
219 uart0: uart@18010000 {
220 cell-index = <0>;
221 compatible = "sirf,atlas7-uart";
222 reg = <0x18010000 0x1000>;
223 interrupts = <0 17 0>;
224 clocks = <&car 90>;
225 fifosize = <128>;
226 dmas = <&dmac0 3>, <&dmac0 2>;
227 dma-names = "rx", "tx";
228 };
229
230 uart1: uart@18020000 {
231 cell-index = <1>;
232 compatible = "sirf,atlas7-uart";
233 reg = <0x18020000 0x1000>;
234 interrupts = <0 18 0>;
235 clocks = <&car 88>;
236 fifosize = <32>;
237 };
238
239 uart2: uart@18030000 {
240 cell-index = <2>;
241 compatible = "sirf,atlas7-uart";
242 reg = <0x18030000 0x1000>;
243 interrupts = <0 19 0>;
244 clocks = <&car 91>;
245 fifosize = <128>;
246 dmas = <&dmac0 6>, <&dmac0 7>;
247 dma-names = "rx", "tx";
248 status = "disabled";
249 };
250 uart3: uart@18040000 {
251 cell-index = <3>;
252 compatible = "sirf,atlas7-uart";
253 reg = <0x18040000 0x1000>;
254 interrupts = <0 66 0>;
255 clocks = <&car 92>;
256 fifosize = <128>;
257 dmas = <&dmac0 4>, <&dmac0 5>;
258 dma-names = "rx", "tx";
259 status = "disabled";
260 };
261 uart4: uart@18050000 {
262 cell-index = <4>;
263 compatible = "sirf,atlas7-uart";
264 reg = <0x18050000 0x1000>;
265 interrupts = <0 69 0>;
266 clocks = <&car 93>;
267 fifosize = <128>;
268 dmas = <&dmac0 0>, <&dmac0 1>;
269 dma-names = "rx", "tx";
270 status = "disabled";
271 };
272 uart5: uart@18060000 {
273 cell-index = <5>;
274 compatible = "sirf,atlas7-uart";
275 reg = <0x18060000 0x1000>;
276 interrupts = <0 71 0>;
277 clocks = <&car 94>;
278 fifosize = <128>;
279 dmas = <&dmac0 8>, <&dmac0 9>;
280 dma-names = "rx", "tx";
281 status = "disabled";
282 };
283 dspub@18250000 {
284 compatible = "dx,cc44p";
285 reg = <0x18250000 0x10000>;
286 interrupts = <0 27 0>;
287 };
288
289 spi1: spi@18200000 {
290 compatible = "sirf,prima2-spi";
291 reg = <0x18200000 0x1000>;
292 interrupts = <0 16 0>;
293 clocks = <&car 95>;
294 #address-cells = <1>;
295 #size-cells = <0>;
296 dmas = <&dmac0 12>, <&dmac0 13>;
297 dma-names = "rx", "tx";
298 status = "disabled";
299 };
300 };
301
302
303 gpum {
304 compatible = "arteris, flexnoc", "simple-bus";
305 #address-cells = <1>;
306 #size-cells = <1>;
307 ranges = <0x13000000 0x13000000 0x3000>;
308 gpum@0x13000000 {
309 compatible = "sirf,nocfw-gpum";
310 reg = <0x13000000 0x3000>;
311 };
312 };
313
314 mediam {
315 compatible = "arteris, flexnoc", "simple-bus";
316 #address-cells = <1>;
317 #size-cells = <1>;
318 ranges = <0x16000000 0x16000000 0x00200000>,
319 <0x17020000 0x17020000 0x1000>,
320 <0x17030000 0x17030000 0x1000>,
321 <0x17040000 0x17040000 0x1000>,
322 <0x17050000 0x17050000 0x10000>,
323 <0x17060000 0x17060000 0x200>,
324 <0x17060200 0x17060200 0x100>,
325 <0x17070000 0x17070000 0x200>,
326 <0x17070200 0x17070200 0x100>,
327 <0x170A0000 0x170A0000 0x3000>;
328
329 mediam@170A0000 {
330 compatible = "sirf,nocfw-mediam";
331 reg = <0x170A0000 0x3000>;
332 };
333
334 gpio_0: gpio_mediam@17040000 {
335 #gpio-cells = <2>;
336 #interrupt-cells = <2>;
337 compatible = "sirf,atlas7-gpio";
338 reg = <0x17040000 0x1000>;
339 interrupts = <0 13 0>, <0 14 0>;
340 clocks = <&car 107>;
341 clock-names = "gpio0_io";
342 gpio-controller;
343 interrupt-controller;
344 };
345
346 nand@17050000 {
347 compatible = "sirf,atlas7-nand";
348 reg = <0x17050000 0x10000>;
349 interrupts = <0 41 0>;
350 clocks = <&car 108>, <&car 112>;
351 clock-names = "nand_io", "nand_nand";
352 };
353
354 sd0: sdhci@16000000 {
355 cell-index = <0>;
356 compatible = "sirf,atlas7-sdhc";
357 reg = <0x16000000 0x100000>;
358 interrupts = <0 38 0>;
359 clocks = <&car 109>, <&car 111>;
360 clock-names = "core", "iface";
361 wp-inverted;
362 non-removable;
363 status = "disabled";
364 bus-width = <8>;
365 };
366
367 sd1: sdhci@16100000 {
368 cell-index = <1>;
369 compatible = "sirf,atlas7-sdhc";
370 reg = <0x16100000 0x100000>;
371 interrupts = <0 38 0>;
372 clocks = <&car 109>, <&car 111>;
373 clock-names = "core", "iface";
374 non-removable;
375 status = "disabled";
376 bus-width = <8>;
377 };
378
379 usb0: usb@17060000 {
380 cell-index = <0>;
381 compatible = "sirf,atlas7-usb";
382 reg = <0x17060000 0x200>;
383 interrupts = <0 10 0>;
384 clocks = <&car 113>;
385 sirf,usbphy = <&usbphy0>;
386 phy_type = "utmi";
387 dr_mode = "otg";
388 maximum-speed = "high-speed";
389 status = "okay";
390 };
391
392 usb1: usb@17070000 {
393 cell-index = <1>;
394 compatible = "sirf,atlas7-usb";
395 reg = <0x17070000 0x200>;
396 interrupts = <0 11 0>;
397 clocks = <&car 114>;
398 sirf,usbphy = <&usbphy1>;
399 phy_type = "utmi";
400 dr_mode = "host";
401 maximum-speed = "high-speed";
402 status = "okay";
403 };
404
405 usbphy0: usbphy@0 {
406 compatible = "sirf,atlas7-usbphy";
407 reg = <0x17060200 0x100>;
408 clocks = <&car 115>;
409 status = "okay";
410 };
411
412 usbphy1: usbphy@1 {
413 compatible = "sirf,atlas7-usbphy";
414 reg = <0x17070200 0x100>;
415 clocks = <&car 116>;
416 status = "okay";
417 };
418
419 i2c0: i2c@17020000 {
420 cell-index = <0>;
421 compatible = "sirf,prima2-i2c";
422 reg = <0x17020000 0x1000>;
423 interrupts = <0 24 0>;
424 clocks = <&car 105>;
425 #address-cells = <1>;
426 #size-cells = <0>;
427 };
428
429 };
430
431 vdifm {
432 compatible = "arteris, flexnoc", "simple-bus";
433 #address-cells = <1>;
434 #size-cells = <1>;
435 ranges = <0x13290000 0x13290000 0x3000>,
436 <0x13300000 0x13300000 0x1000>,
437 <0x14200000 0x14200000 0x600000>;
438
439 vdifm@13290000 {
440 compatible = "sirf,nocfw-vdifm";
441 reg = <0x13290000 0x3000>;
442 };
443
444 gpio_1: gpio_vdifm@13300000 {
445 #gpio-cells = <2>;
446 #interrupt-cells = <2>;
447 compatible = "sirf,atlas7-gpio";
448 reg = <0x13300000 0x1000>;
449 interrupts = <0 43 0>, <0 44 0>, <0 45 0>;
450 clocks = <&car 84>;
451 clock-names = "gpio1_io";
452 gpio-controller;
453 interrupt-controller;
454 };
455
456 sd2: sdhci@14200000 {
457 cell-index = <2>;
458 compatible = "sirf,atlas7-sdhc";
459 reg = <0x14200000 0x100000>;
460 interrupts = <0 23 0>;
461 clocks = <&car 70>, <&car 75>;
462 clock-names = "core", "iface";
463 status = "disabled";
464 bus-width = <4>;
465 sd-uhs-sdr50;
466 vqmmc-supply = <&vqmmc>;
467 vqmmc: vqmmc@2 {
468 regulator-min-microvolt = <1650000>;
469 regulator-max-microvolt = <1950000>;
470 regulator-name = "vqmmc-ldo";
471 regulator-type = "voltage";
472 regulator-boot-on;
473 regulator-allow-bypass;
474 };
475 };
476
477 sd3: sdhci@14300000 {
478 cell-index = <3>;
479 compatible = "sirf,atlas7-sdhc";
480 reg = <0x14300000 0x100000>;
481 interrupts = <0 23 0>;
482 clocks = <&car 76>, <&car 81>;
483 clock-names = "core", "iface";
484 status = "disabled";
485 bus-width = <4>;
486 };
487
488 sd5: sdhci@14500000 {
489 cell-index = <5>;
490 compatible = "sirf,atlas7-sdhc";
491 reg = <0x14500000 0x100000>;
492 interrupts = <0 39 0>;
493 clocks = <&car 71>, <&car 76>;
494 clock-names = "core", "iface";
495 status = "disabled";
496 bus-width = <4>;
497 loop-dma;
498 };
499
500 sd6: sdhci@14600000 {
501 cell-index = <6>;
502 compatible = "sirf,atlas7-sdhc";
503 reg = <0x14600000 0x100000>;
504 interrupts = <0 98 0>;
505 clocks = <&car 72>, <&car 77>;
506 clock-names = "core", "iface";
507 status = "disabled";
508 bus-width = <4>;
509 };
510
511 sd7: sdhci@14700000 {
512 cell-index = <7>;
513 compatible = "sirf,atlas7-sdhc";
514 reg = <0x14700000 0x100000>;
515 interrupts = <0 98 0>;
516 clocks = <&car 72>, <&car 77>;
517 clock-names = "core", "iface";
518 status = "disabled";
519 bus-width = <4>;
520 };
521 };
522
523 audiom {
524 compatible = "arteris, flexnoc", "simple-bus";
525 #address-cells = <1>;
526 #size-cells = <1>;
527 ranges = <0x10d50000 0x10d50000 0x0000ffff>,
528 <0x10d60000 0x10d60000 0x0000ffff>,
529 <0x10d80000 0x10d80000 0x0000ffff>,
530 <0x10d90000 0x10d90000 0x0000ffff>,
531 <0x10ED0000 0x10ED0000 0x3000>,
532 <0x10dc8000 0x10dc8000 0x1000>,
533 <0x10dc0000 0x10dc0000 0x1000>,
534 <0x10db0000 0x10db0000 0x4000>,
535 <0x10d40000 0x10d40000 0x1000>,
536 <0x10d30000 0x10d30000 0x1000>;
537
538 timer@10dc0000 {
539 compatible = "sirf,atlas7-tick";
540 reg = <0x10dc0000 0x1000>;
541 interrupts = <0 0 0>,
542 <0 1 0>,
543 <0 2 0>,
544 <0 49 0>,
545 <0 50 0>,
546 <0 51 0>;
547 clocks = <&car 47>;
548 };
549
550 timerb@10dc8000 {
551 compatible = "sirf,atlas7-tick";
552 reg = <0x10dc8000 0x1000>;
553 interrupts = <0 74 0>,
554 <0 75 0>,
555 <0 76 0>,
556 <0 77 0>,
557 <0 78 0>,
558 <0 79 0>;
559 clocks = <&car 47>;
560 };
561
562 vip0@10db0000 {
563 compatible = "sirf,atlas7-vip0";
564 reg = <0x10db0000 0x2000>;
565 interrupts = <0 85 0>;
566 sirf,vip_cma_size = <0xC00000>;
567 };
568
569 cvd@10db2000 {
570 compatible = "sirf,cvd";
571 reg = <0x10db2000 0x2000>;
572 clocks = <&car 46>;
573 };
574
575 dmac2: dma-controller@10d50000 {
576 cell-index = <2>;
577 compatible = "sirf,atlas7-dmac";
578 reg = <0x10d50000 0xffff>;
579 interrupts = <0 55 0>;
580 clocks = <&car 60>;
581 dma-channels = <16>;
582 #dma-cells = <1>;
583 };
584
585 dmac3: dma-controller@10d60000 {
586 cell-index = <3>;
587 compatible = "sirf,atlas7-dmac";
588 reg = <0x10d60000 0xffff>;
589 interrupts = <0 56 0>;
590 clocks = <&car 61>;
591 dma-channels = <16>;
592 #dma-cells = <1>;
593 };
594
595 adc: adc@10d80000 {
596 compatible = "sirf,atlas7-adc";
597 reg = <0x10d80000 0xffff>;
598 interrupts = <0 34 0>;
599 clocks = <&car 49>;
600 #io-channel-cells = <1>;
601 };
602
603 pulsec@10d90000 {
604 compatible = "sirf,prima2-pulsec";
605 reg = <0x10d90000 0xffff>;
606 interrupts = <0 42 0>;
607 clocks = <&car 54>;
608 };
609
610 audiom@10ED0000 {
611 compatible = "sirf,nocfw-audiom";
612 reg = <0x10ED0000 0x3000>;
613 interrupts = <0 102 0>;
614 };
615
616 usp1: usp@10d30000 {
617 cell-index = <1>;
618 reg = <0x10d30000 0x1000>;
619 fifosize = <512>;
620 clocks = <&car 58>;
621 dmas = <&dmac2 6>, <&dmac2 7>;
622 dma-names = "rx", "tx";
623 };
624
625 usp2: usp@10d40000 {
626 cell-index = <2>;
627 reg = <0x10d40000 0x1000>;
628 interrupts = <0 22 0>;
629 clocks = <&car 59>;
630 dmas = <&dmac2 12>, <&dmac2 13>;
631 dma-names = "rx", "tx";
632 #address-cells = <1>;
633 #size-cells = <0>;
634 status = "disabled";
635 };
636 };
637
638 ddrm {
639 compatible = "arteris, flexnoc", "simple-bus";
640 #address-cells = <1>;
641 #size-cells = <1>;
642 ranges = <0x10820000 0x10820000 0x3000>,
643 <0x10800000 0x10800000 0x2000>;
644 ddrm@10820000 {
645 compatible = "sirf,nocfw-ddrm";
646 reg = <0x10820000 0x3000>;
647 interrupts = <0 105 0>;
648 };
649
650 memory-controller@0x10800000 {
651 compatible = "sirf,atlas7-memc";
652 reg = <0x10800000 0x2000>;
653 };
654
655 };
656
657 btm {
658 compatible = "arteris, flexnoc", "simple-bus";
659 #address-cells = <1>;
660 #size-cells = <1>;
661 ranges = <0x11002000 0x11002000 0x0000ffff>,
662 <0x11010000 0x11010000 0x3000>,
663 <0x11000000 0x11000000 0x1000>,
664 <0x11001000 0x11001000 0x1000>;
665
666 dmac4: dma-controller@11002000 {
667 cell-index = <4>;
668 compatible = "sirf,atlas7-dmac";
669 reg = <0x11002000 0x1000>;
670 interrupts = <0 99 0>;
671 clocks = <&car 130>;
672 dma-channels = <16>;
673 #dma-cells = <1>;
674 };
675 uart6: uart@11000000 {
676 cell-index = <6>;
677 compatible = "sirf,atlas7-bt-uart",
678 "sirf,atlas7-uart";
679 reg = <0x11000000 0x1000>;
680 interrupts = <0 100 0>;
681 clocks = <&car 131>, <&car 133>, <&car 134>;
682 clock-names = "uart", "general", "noc";
683 fifosize = <128>;
684 dmas = <&dmac4 12>, <&dmac4 13>;
685 dma-names = "rx", "tx";
686 status = "disabled";
687 };
688
689 usp3: usp@11001000 {
690 compatible = "sirf,atlas7-bt-usp",
691 "sirf,prima2-usp-pcm";
692 cell-index = <3>;
693 reg = <0x11001000 0x1000>;
694 fifosize = <512>;
695 clocks = <&car 132>, <&car 129>, <&car 133>,
696 <&car 134>, <&car 135>;
697 clock-names = "usp3_io", "a7ca_btss", "a7ca_io",
698 "noc_btm_io", "thbtm_io";
699 dmas = <&dmac4 0>, <&dmac4 1>;
700 dma-names = "rx", "tx";
701 };
702
703 btm@11010000 {
704 compatible = "sirf,nocfw-btm";
705 reg = <0x11010000 0x3000>;
706 };
707 };
708
709 rtcm {
710 compatible = "arteris, flexnoc", "simple-bus";
711 #address-cells = <1>;
712 #size-cells = <1>;
713 ranges = <0x18810000 0x18810000 0x3000>,
714 <0x18840000 0x18840000 0x1000>,
715 <0x18890000 0x18890000 0x1000>,
716 <0x188B0000 0x188B0000 0x10000>,
717 <0x188D0000 0x188D0000 0x1000>;
718 rtcm@18810000 {
719 compatible = "sirf,nocfw-rtcm";
720 reg = <0x18810000 0x3000>;
721 interrupts = <0 109 0>;
722 };
723
724 gpio_2: gpio_rtcm@18890000 {
725 #gpio-cells = <2>;
726 #interrupt-cells = <2>;
727 compatible = "sirf,atlas7-gpio";
728 reg = <0x18890000 0x1000>;
729 interrupts = <0 47 0>;
730 gpio-controller;
731 interrupt-controller;
732 };
733
734 rtc-iobg@18840000 {
735 compatible = "sirf,prima2-rtciobg",
736 "sirf-prima2-rtciobg-bus",
737 "simple-bus";
738 #address-cells = <1>;
739 #size-cells = <1>;
740 reg = <0x18840000 0x1000>;
741
742 sysrtc@2000 {
743 compatible = "sirf,prima2-sysrtc";
744 reg = <0x2000 0x100>;
745 interrupts = <0 52 0>;
746 };
747 pwrc@3000 {
748 compatible = "sirf,atlas7-pwrc";
749 reg = <0x3000 0x100>;
750 };
751 };
752
753 qspi: flash@188B0000 {
754 cell-index = <0>;
755 compatible = "sirf,atlas7-qspi-nor";
756 reg = <0x188B0000 0x10000>;
757 interrupts = <0 15 0>;
758 #address-cells = <1>;
759 #size-cells = <0>;
760 };
761
762 retain@0x188D0000 {
763 compatible = "sirf,atlas7-retain";
764 reg = <0x188D0000 0x1000>;
765 };
766
767 };
768 disp-iobg {
769 /* lcdc0 */
770 compatible = "simple-bus";
771 #address-cells = <1>;
772 #size-cells = <1>;
773 ranges = <0x13100000 0x13100000 0x20000>,
774 <0x10e10000 0x10e10000 0x10000>;
775
776 lcd@13100000 {
777 compatible = "sirf,atlas7-lcdc";
778 reg = <0x13100000 0x10000>;
779 interrupts = <0 30 0>;
780 clocks = <&car 79>;
781 };
782 vpp@13110000 {
783 compatible = "sirf,atlas7-vpp";
784 reg = <0x13110000 0x10000>;
785 interrupts = <0 31 0>;
786 clocks = <&car 78>;
787 resets = <&car 29>;
788 };
789 lvds@10e10000 {
790 compatible = "sirf,atlas7-lvdsc";
791 reg = <0x10e10000 0x10000>;
792 interrupts = <0 64 0>;
793 clocks = <&car 54>;
794 resets = <&car 29>;
795 };
796
797 };
798
799 graphics-iobg {
800 compatible = "simple-bus";
801 #address-cells = <1>;
802 #size-cells = <1>;
803 ranges = <0x12000000 0x12000000 0x1000000>;
804
805 graphics@12000000 {
806 compatible = "powervr,sgx531";
807 reg = <0x12000000 0x1000000>;
808 interrupts = <0 6 0>;
809 clocks = <&car 126>;
810 };
811 };
812 };
813};
diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
index 5fc0fae03092..b359c1e6178e 100644
--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
@@ -23,11 +23,77 @@
23 reg = <0x00000000 0x08000000>; 23 reg = <0x00000000 0x08000000>;
24 }; 24 };
25 25
26 spi {
27 compatible = "spi-gpio";
28 num-chipselects = <1>;
29 gpio-sck = <&chipcommon 7 0>;
30 gpio-mosi = <&chipcommon 4 0>;
31 cs-gpios = <&chipcommon 6 0>;
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 hc595: gpio_spi@0 {
36 compatible = "fairchild,74hc595";
37 reg = <0>;
38 registers-number = <1>;
39 spi-max-frequency = <100000>;
40
41 gpio-controller;
42 #gpio-cells = <2>;
43
44 };
45 };
46
47 leds {
48 compatible = "gpio-leds";
49
50 power0 {
51 label = "bcm53xx:red:power";
52 gpios = <&hc595 1 GPIO_ACTIVE_HIGH>;
53 linux,default-trigger = "default-off";
54 };
55
56 power1 {
57 label = "bcm53xx:white:power";
58 gpios = <&hc595 2 GPIO_ACTIVE_HIGH>;
59 linux,default-trigger = "default-on";
60 };
61
62 router0 {
63 label = "bcm53xx:blue:router";
64 gpios = <&hc595 3 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "default-on";
66 };
67
68 router1 {
69 label = "bcm53xx:amber:router";
70 gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
71 linux,default-trigger = "default-off";
72 };
73
74 wan {
75 label = "bcm53xx:blue:wan";
76 gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
77 linux,default-trigger = "default-on";
78 };
79
80 wireless0 {
81 label = "bcm53xx:blue:wireless";
82 gpios = <&hc595 6 GPIO_ACTIVE_HIGH>;
83 linux,default-trigger = "default-off";
84 };
85
86 wireless1 {
87 label = "bcm53xx:amber:wireless";
88 gpios = <&hc595 7 GPIO_ACTIVE_HIGH>;
89 linux,default-trigger = "default-off";
90 };
91 };
92
26 gpio-keys { 93 gpio-keys {
27 compatible = "gpio-keys"; 94 compatible = "gpio-keys";
28 #address-cells = <1>; 95 #address-cells = <1>;
29 #size-cells = <0>; 96 #size-cells = <0>;
30 poll-interval = <200>;
31 97
32 restart { 98 restart {
33 label = "Reset"; 99 label = "Reset";
diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
new file mode 100644
index 000000000000..946c728c4eb7
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
@@ -0,0 +1,60 @@
1/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * DTS for Luxul XWC-1000
4 *
5 * Copyright 2014 Luxul Inc.
6 *
7 * Licensed under the GNU/GPL. See COPYING for details.
8 */
9
10/dts-v1/;
11
12#include "bcm4708.dtsi"
13
14/ {
15 compatible = "luxul,xwc-1000", "brcm,bcm4708";
16 model = "Luxul XWC-1000 (BCM4708)";
17
18 chosen {
19 bootargs = "console=ttyS0,115200";
20 };
21
22 memory {
23 reg = <0x00000000 0x08000000>;
24 };
25
26 axi@18000000 {
27 nand@28000 {
28 reg = <0x00028000 0x1000>;
29 #address-cells = <1>;
30 #size-cells = <1>;
31
32 partition@0 {
33 label = "ubi";
34 reg = <0x00000000 0x08000000>;
35 };
36 };
37 };
38
39 leds {
40 compatible = "gpio-leds";
41
42 status {
43 label = "bcm53xx:green:status";
44 gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
45 linux,default-trigger = "timer";
46 };
47 };
48
49 gpio-keys {
50 compatible = "gpio-keys";
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 restart {
55 label = "Reset";
56 linux,code = <KEY_RESTART>;
57 gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
58 };
59 };
60};
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
index 4ed7de1058b7..f18c9d9b2f2c 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
@@ -71,7 +71,6 @@
71 compatible = "gpio-keys"; 71 compatible = "gpio-keys";
72 #address-cells = <1>; 72 #address-cells = <1>;
73 #size-cells = <0>; 73 #size-cells = <0>;
74 poll-interval = <200>;
75 74
76 wps { 75 wps {
77 label = "WPS"; 76 label = "WPS";
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
index 12fc2a01e6ab..39910428246a 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
@@ -61,7 +61,6 @@
61 compatible = "gpio-keys"; 61 compatible = "gpio-keys";
62 #address-cells = <1>; 62 #address-cells = <1>;
63 #size-cells = <0>; 63 #size-cells = <0>;
64 poll-interval = <200>;
65 64
66 wps { 65 wps {
67 label = "WPS"; 66 label = "WPS";
diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
index fb76378bd511..0ee85ea10bb2 100644
--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
@@ -61,7 +61,6 @@
61 compatible = "gpio-keys"; 61 compatible = "gpio-keys";
62 #address-cells = <1>; 62 #address-cells = <1>;
63 #size-cells = <0>; 63 #size-cells = <0>;
64 poll-interval = <200>;
65 64
66 restart { 65 restart {
67 label = "Reset"; 66 label = "Reset";
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
index bbb414fbad65..db9131e03268 100644
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
@@ -23,11 +23,77 @@
23 reg = <0x00000000 0x08000000>; 23 reg = <0x00000000 0x08000000>;
24 }; 24 };
25 25
26 spi {
27 compatible = "spi-gpio";
28 num-chipselects = <1>;
29 gpio-sck = <&chipcommon 7 0>;
30 gpio-mosi = <&chipcommon 4 0>;
31 cs-gpios = <&chipcommon 6 0>;
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 hc595: gpio_spi@0 {
36 compatible = "fairchild,74hc595";
37 reg = <0>;
38 registers-number = <1>;
39 spi-max-frequency = <100000>;
40
41 gpio-controller;
42 #gpio-cells = <2>;
43
44 };
45 };
46
47 leds {
48 compatible = "gpio-leds";
49
50 power0 {
51 label = "bcm53xx:green:power";
52 gpios = <&hc595 1 GPIO_ACTIVE_HIGH>;
53 linux,default-trigger = "default-on";
54 };
55
56 power1 {
57 label = "bcm53xx:red:power";
58 gpios = <&hc595 2 GPIO_ACTIVE_HIGH>;
59 linux,default-trigger = "default-off";
60 };
61
62 router0 {
63 label = "bcm53xx:green:router";
64 gpios = <&hc595 3 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "default-on";
66 };
67
68 router1 {
69 label = "bcm53xx:amber:router";
70 gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
71 linux,default-trigger = "default-off";
72 };
73
74 wan {
75 label = "bcm53xx:green:wan";
76 gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
77 linux,default-trigger = "default-on";
78 };
79
80 wireless0 {
81 label = "bcm53xx:green:wireless";
82 gpios = <&hc595 6 GPIO_ACTIVE_HIGH>;
83 linux,default-trigger = "default-off";
84 };
85
86 wireless1 {
87 label = "bcm53xx:amber:wireless";
88 gpios = <&hc595 7 GPIO_ACTIVE_HIGH>;
89 linux,default-trigger = "default-off";
90 };
91 };
92
26 gpio-keys { 93 gpio-keys {
27 compatible = "gpio-keys"; 94 compatible = "gpio-keys";
28 #address-cells = <1>; 95 #address-cells = <1>;
29 #size-cells = <0>; 96 #size-cells = <0>;
30 poll-interval = <200>;
31 97
32 aoss { 98 aoss {
33 label = "AOSS"; 99 label = "AOSS";
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
new file mode 100644
index 000000000000..7d6868acb1c6
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
@@ -0,0 +1,37 @@
1/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * DTS for Buffalo WZR-900DHP
4 *
5 * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com>
6 *
7 * Licensed under the GNU/GPL. See COPYING for details.
8 */
9
10/dts-v1/;
11
12#include "bcm47081.dtsi"
13
14/ {
15 compatible = "buffalo,wzr-900dhp", "brcm,bcm47081", "brcm,bcm4708";
16 model = "Buffalo WZR-900DHP (BCM47081)";
17
18 chosen {
19 bootargs = "console=ttyS0,115200";
20 };
21
22 memory {
23 reg = <0x00000000 0x08000000>;
24 };
25
26 gpio-keys {
27 compatible = "gpio-keys";
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 restart {
32 label = "Reset";
33 linux,code = <KEY_RESTART>;
34 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
35 };
36 };
37};
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 015a06c67c91..63d00a63cfa6 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -104,7 +104,7 @@
104 local-timer@ad0600 { 104 local-timer@ad0600 {
105 compatible = "arm,cortex-a9-twd-timer"; 105 compatible = "arm,cortex-a9-twd-timer";
106 reg = <0xad0600 0x20>; 106 reg = <0xad0600 0x20>;
107 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; 107 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
108 clocks = <&chip CLKID_TWD>; 108 clocks = <&chip CLKID_TWD>;
109 }; 109 };
110 110
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 230df3b1770e..81b670ac494a 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -45,6 +45,11 @@
45 45
46 ranges = <0 0xf7000000 0x1000000>; 46 ranges = <0 0xf7000000 0x1000000>;
47 47
48 pmu {
49 compatible = "arm,cortex-a9-pmu";
50 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
51 };
52
48 sdhci0: sdhci@ab0000 { 53 sdhci0: sdhci@ab0000 {
49 compatible = "mrvl,pxav3-mmc"; 54 compatible = "mrvl,pxav3-mmc";
50 reg = <0xab0000 0x200>; 55 reg = <0xab0000 0x200>;
@@ -71,7 +76,7 @@
71 local-timer@ad0600 { 76 local-timer@ad0600 {
72 compatible = "arm,cortex-a9-twd-timer"; 77 compatible = "arm,cortex-a9-twd-timer";
73 reg = <0xad0600 0x20>; 78 reg = <0xad0600 0x20>;
74 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; 79 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
75 clocks = <&chip CLKID_TWD>; 80 clocks = <&chip CLKID_TWD>;
76 }; 81 };
77 82
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 35253c947a7c..41a683fd079c 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -63,6 +63,14 @@
63 ranges = <0 0xf7000000 0x1000000>; 63 ranges = <0 0xf7000000 0x1000000>;
64 interrupt-parent = <&gic>; 64 interrupt-parent = <&gic>;
65 65
66 pmu {
67 compatible = "arm,cortex-a9-pmu";
68 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
72 };
73
66 sdhci0: sdhci@ab0000 { 74 sdhci0: sdhci@ab0000 {
67 compatible = "mrvl,pxav3-mmc"; 75 compatible = "mrvl,pxav3-mmc";
68 reg = <0xab0000 0x200>; 76 reg = <0xab0000 0x200>;
@@ -104,7 +112,7 @@
104 compatible = "arm,cortex-a9-twd-timer"; 112 compatible = "arm,cortex-a9-twd-timer";
105 reg = <0xad0600 0x20>; 113 reg = <0xad0600 0x20>;
106 clocks = <&chip CLKID_TWD>; 114 clocks = <&chip CLKID_TWD>;
107 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; 115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
108 }; 116 };
109 117
110 gic: interrupt-controller@ad1000 { 118 gic: interrupt-controller@ad1000 {
diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
new file mode 100644
index 000000000000..857d0289ad4d
--- /dev/null
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -0,0 +1,129 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 */
6/dts-v1/;
7
8#include "dm816x.dtsi"
9
10/ {
11 model = "DM8168 EVM";
12 compatible = "ti,dm8168-evm", "ti,dm8168";
13
14 memory {
15 device_type = "memory";
16 reg = <0x80000000 0x40000000 /* 1 GB */
17 0xc0000000 0x40000000>; /* 1 GB */
18 };
19
20 /* FDC6331L controlled by SD_POW pin */
21 vmmcsd_fixed: fixedregulator@0 {
22 compatible = "regulator-fixed";
23 regulator-name = "vmmcsd_fixed";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
26 };
27};
28
29&dm816x_pinmux {
30 mcspi1_pins: pinmux_mcspi1_pins {
31 pinctrl-single,pins = <
32 DM816X_IOPAD(0x0a94, PIN_INPUT | MUX_MODE0) /* SPI_SCLK */
33 DM816X_IOPAD(0x0a98, PIN_OUTPUT | MUX_MODE0) /* SPI_SCS0 */
34 DM816X_IOPAD(0x0aa8, PIN_INPUT | MUX_MODE0) /* SPI_D0 */
35 DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0) /* SPI_D1 */
36 >;
37 };
38};
39
40&i2c1 {
41 extgpio0: pcf8575@20 {
42 compatible = "nxp,pcf8575";
43 reg = <0x20>;
44 gpio-controller;
45 #gpio-cells = <2>;
46 };
47};
48
49&i2c2 {
50 extgpio1: pcf8575@20 {
51 compatible = "nxp,pcf8575";
52 reg = <0x20>;
53 gpio-controller;
54 #gpio-cells = <2>;
55 };
56};
57
58&gpmc {
59 ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
60
61 nand@0,0 {
62 linux,mtd-name= "micron,mt29f2g16aadwp";
63 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
64 #address-cells = <1>;
65 #size-cells = <1>;
66 ti,nand-ecc-opt = "bch8";
67 nand-bus-width = <16>;
68 gpmc,device-width = <2>;
69 gpmc,sync-clk-ps = <0>;
70 gpmc,cs-on-ns = <0>;
71 gpmc,cs-rd-off-ns = <44>;
72 gpmc,cs-wr-off-ns = <44>;
73 gpmc,adv-on-ns = <6>;
74 gpmc,adv-rd-off-ns = <34>;
75 gpmc,adv-wr-off-ns = <44>;
76 gpmc,we-on-ns = <0>;
77 gpmc,we-off-ns = <40>;
78 gpmc,oe-on-ns = <0>;
79 gpmc,oe-off-ns = <54>;
80 gpmc,access-ns = <64>;
81 gpmc,rd-cycle-ns = <82>;
82 gpmc,wr-cycle-ns = <82>;
83 gpmc,wait-on-read = "true";
84 gpmc,wait-on-write = "true";
85 gpmc,bus-turnaround-ns = <0>;
86 gpmc,cycle2cycle-delay-ns = <0>;
87 gpmc,clk-activation-ns = <0>;
88 gpmc,wait-monitoring-ns = <0>;
89 gpmc,wr-access-ns = <40>;
90 gpmc,wr-data-mux-bus-ns = <0>;
91 partition@0 {
92 label = "X-Loader";
93 reg = <0 0x80000>;
94 };
95 partition@0x80000 {
96 label = "U-Boot";
97 reg = <0x80000 0x1c0000>;
98 };
99 partition@0x1c0000 {
100 label = "Environment";
101 reg = <0x240000 0x40000>;
102 };
103 partition@0x280000 {
104 label = "Kernel";
105 reg = <0x280000 0x500000>;
106 };
107 partition@0x780000 {
108 label = "Filesystem";
109 reg = <0x780000 0xf880000>;
110 };
111 };
112};
113
114&mcspi1 {
115 pinctrl-names = "default";
116 pinctrl-0 = <&mcspi1_pins>;
117
118 m25p80@0 {
119 compatible = "w25x32";
120 spi-max-frequency = <48000000>;
121 reg = <0>;
122 #address-cells = <1>;
123 #size-cells = <1>;
124 };
125};
126
127&mmc1 {
128 vmmc-supply = <&vmmcsd_fixed>;
129};
diff --git a/arch/arm/boot/dts/dm816x-clocks.dtsi b/arch/arm/boot/dts/dm816x-clocks.dtsi
new file mode 100644
index 000000000000..50d9d338fbe9
--- /dev/null
+++ b/arch/arm/boot/dts/dm816x-clocks.dtsi
@@ -0,0 +1,250 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 */
6
7&scrm {
8 main_fapll: main_fapll {
9 #clock-cells = <1>;
10 compatible = "ti,dm816-fapll-clock";
11 reg = <0x400 0x40>;
12 clocks = <&sys_clkin_ck &sys_clkin_ck>;
13 clock-indices = <1>, <2>, <3>, <4>, <5>,
14 <6>, <7>;
15 clock-output-names = "main_pll_clk1",
16 "main_pll_clk2",
17 "main_pll_clk3",
18 "main_pll_clk4",
19 "main_pll_clk5",
20 "main_pll_clk6",
21 "main_pll_clk7";
22 };
23
24 ddr_fapll: ddr_fapll {
25 #clock-cells = <1>;
26 compatible = "ti,dm816-fapll-clock";
27 reg = <0x440 0x30>;
28 clocks = <&sys_clkin_ck &sys_clkin_ck>;
29 clock-indices = <1>, <2>, <3>, <4>;
30 clock-output-names = "ddr_pll_clk1",
31 "ddr_pll_clk2",
32 "ddr_pll_clk3",
33 "ddr_pll_clk4";
34 };
35
36 video_fapll: video_fapll {
37 #clock-cells = <1>;
38 compatible = "ti,dm816-fapll-clock";
39 reg = <0x470 0x30>;
40 clocks = <&sys_clkin_ck &sys_clkin_ck>;
41 clock-indices = <1>, <2>, <3>;
42 clock-output-names = "video_pll_clk1",
43 "video_pll_clk2",
44 "video_pll_clk3";
45 };
46
47 audio_fapll: audio_fapll {
48 #clock-cells = <1>;
49 compatible = "ti,dm816-fapll-clock";
50 reg = <0x4a0 0x30>;
51 clocks = <&main_fapll 7>, < &sys_clkin_ck>;
52 clock-indices = <1>, <2>, <3>, <4>, <5>;
53 clock-output-names = "audio_pll_clk1",
54 "audio_pll_clk2",
55 "audio_pll_clk3",
56 "audio_pll_clk4",
57 "audio_pll_clk5";
58 };
59};
60
61&scrm_clocks {
62 secure_32k_ck: secure_32k_ck {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <32768>;
66 };
67
68 sys_32k_ck: sys_32k_ck {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <32768>;
72 };
73
74 tclkin_ck: tclkin_ck {
75 #clock-cells = <0>;
76 compatible = "fixed-clock";
77 clock-frequency = <32768>;
78 };
79
80 sys_clkin_ck: sys_clkin_ck {
81 #clock-cells = <0>;
82 compatible = "fixed-clock";
83 clock-frequency = <27000000>;
84 };
85};
86
87/* 0x48180000 */
88&prcm_clocks {
89 clkout_pre_ck: clkout_pre_ck {
90 #clock-cells = <0>;
91 compatible = "ti,mux-clock";
92 clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
93 &audio_fapll 1>;
94 reg = <0x100>;
95 };
96
97 clkout_div_ck: clkout_div_ck {
98 #clock-cells = <0>;
99 compatible = "ti,divider-clock";
100 clocks = <&clkout_pre_ck>;
101 ti,bit-shift = <3>;
102 ti,max-div = <8>;
103 reg = <0x100>;
104 };
105
106 clkout_ck: clkout_ck {
107 #clock-cells = <0>;
108 compatible = "ti,gate-clock";
109 clocks = <&clkout_div_ck>;
110 ti,bit-shift = <7>;
111 reg = <0x100>;
112 };
113
114 /* CM_DPLL clocks p1795 */
115 sysclk1_ck: sysclk1_ck {
116 #clock-cells = <0>;
117 compatible = "ti,divider-clock";
118 clocks = <&main_fapll 1>;
119 ti,max-div = <7>;
120 reg = <0x0300>;
121 };
122
123 sysclk2_ck: sysclk2_ck {
124 #clock-cells = <0>;
125 compatible = "ti,divider-clock";
126 clocks = <&main_fapll 2>;
127 ti,max-div = <7>;
128 reg = <0x0304>;
129 };
130
131 sysclk3_ck: sysclk3_ck {
132 #clock-cells = <0>;
133 compatible = "ti,divider-clock";
134 clocks = <&main_fapll 3>;
135 ti,max-div = <7>;
136 reg = <0x0308>;
137 };
138
139 sysclk4_ck: sysclk4_ck {
140 #clock-cells = <0>;
141 compatible = "ti,divider-clock";
142 clocks = <&main_fapll 4>;
143 ti,max-div = <1>;
144 reg = <0x030c>;
145 };
146
147 sysclk5_ck: sysclk5_ck {
148 #clock-cells = <0>;
149 compatible = "ti,divider-clock";
150 clocks = <&sysclk4_ck>;
151 ti,max-div = <1>;
152 reg = <0x0310>;
153 };
154
155 sysclk6_ck: sysclk6_ck {
156 #clock-cells = <0>;
157 compatible = "ti,divider-clock";
158 clocks = <&main_fapll 4>;
159 ti,dividers = <2>, <4>;
160 reg = <0x0314>;
161 };
162
163 sysclk10_ck: sysclk10_ck {
164 #clock-cells = <0>;
165 compatible = "ti,divider-clock";
166 clocks = <&ddr_fapll 2>;
167 ti,max-div = <7>;
168 reg = <0x0324>;
169 };
170
171 sysclk24_ck: sysclk24_ck {
172 #clock-cells = <0>;
173 compatible = "ti,divider-clock";
174 clocks = <&main_fapll 5>;
175 ti,max-div = <7>;
176 reg = <0x03b4>;
177 };
178
179 mpu_ck: mpu_ck {
180 #clock-cells = <0>;
181 compatible = "ti,gate-clock";
182 clocks = <&sysclk2_ck>;
183 ti,bit-shift = <1>;
184 reg = <0x15dc>;
185 };
186
187 audio_pll_a_ck: audio_pll_a_ck {
188 #clock-cells = <0>;
189 compatible = "ti,divider-clock";
190 clocks = <&audio_fapll 1>;
191 ti,max-div = <7>;
192 reg = <0x035c>;
193 };
194
195 sysclk18_ck: sysclk18_ck {
196 #clock-cells = <0>;
197 compatible = "ti,mux-clock";
198 clocks = <&sys_32k_ck>, <&audio_pll_a_ck>;
199 reg = <0x0378>;
200 };
201
202 timer1_fck: timer1_fck {
203 #clock-cells = <0>;
204 compatible = "ti,mux-clock";
205 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
206 reg = <0x0390>;
207 };
208
209 timer2_fck: timer2_fck {
210 #clock-cells = <0>;
211 compatible = "ti,mux-clock";
212 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
213 reg = <0x0394>;
214 };
215
216 timer3_fck: timer3_fck {
217 #clock-cells = <0>;
218 compatible = "ti,mux-clock";
219 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
220 reg = <0x0398>;
221 };
222
223 timer4_fck: timer4_fck {
224 #clock-cells = <0>;
225 compatible = "ti,mux-clock";
226 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
227 reg = <0x039c>;
228 };
229
230 timer5_fck: timer5_fck {
231 #clock-cells = <0>;
232 compatible = "ti,mux-clock";
233 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
234 reg = <0x03a0>;
235 };
236
237 timer6_fck: timer6_fck {
238 #clock-cells = <0>;
239 compatible = "ti,mux-clock";
240 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
241 reg = <0x03a4>;
242 };
243
244 timer7_fck: timer7_fck {
245 #clock-cells = <0>;
246 compatible = "ti,mux-clock";
247 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
248 reg = <0x03a8>;
249 };
250};
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
new file mode 100644
index 000000000000..7adac097a71c
--- /dev/null
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -0,0 +1,387 @@
1/*
2 * This file is licensed under the terms of the GNU General Public License
3 * version 2. This program is licensed "as is" without any warranty of any
4 * kind, whether express or implied.
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/pinctrl/omap.h>
9
10#include "skeleton.dtsi"
11
12/ {
13 compatible = "ti,dm816";
14 interrupt-parent = <&intc>;
15
16 aliases {
17 i2c0 = &i2c1;
18 i2c1 = &i2c2;
19 serial0 = &uart1;
20 serial1 = &uart2;
21 serial2 = &uart3;
22 ethernet0 = &eth0;
23 ethernet1 = &eth1;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29 cpu@0 {
30 compatible = "arm,cortex-a8";
31 device_type = "cpu";
32 reg = <0>;
33 };
34 };
35
36 pmu {
37 compatible = "arm,cortex-a8-pmu";
38 interrupts = <3>;
39 };
40
41 /*
42 * The soc node represents the soc top level view. It is used for IPs
43 * that are not memory mapped in the MPU view or for the MPU itself.
44 */
45 soc {
46 compatible = "ti,omap-infra";
47 mpu {
48 compatible = "ti,omap3-mpu";
49 ti,hwmods = "mpu";
50 };
51 };
52
53 dm816x_pinmux: pinmux@44e10800 {
54 compatible = "pinctrl-single";
55 reg = <0x48140800 0x50a>;
56 #address-cells = <1>;
57 #size-cells = <0>;
58 pinctrl-single,register-width = <16>;
59 pinctrl-single,function-mask = <0xf>;
60 };
61
62 /*
63 * XXX: Use a flat representation of the dm816x interconnect.
64 * The real dm816x interconnect network is quite complex. Since
65 * it will not bring real advantage to represent that in DT
66 * for the moment, just use a fake OCP bus entry to represent
67 * the whole bus hierarchy.
68 */
69 ocp {
70 compatible = "ti,omap3-l3-smx", "simple-bus";
71 reg = <0x44000000 0x10000>;
72 interrupts = <9 10>;
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76 ti,hwmods = "l3_main";
77
78 prcm: prcm@48180000 {
79 compatible = "ti,dm816-prcm";
80 reg = <0x48180000 0x4000>;
81
82 prcm_clocks: clocks {
83 #address-cells = <1>;
84 #size-cells = <0>;
85 };
86
87 prcm_clockdomains: clockdomains {
88 };
89 };
90
91 scrm: scrm@48140000 {
92 compatible = "ti,dm816-scrm";
93 reg = <0x48140000 0x21000>;
94 #address-cells = <1>;
95 #size-cells = <1>;
96 ranges = <0 0x48140000 0x21000>;
97
98 scrm_clocks: clocks {
99 #address-cells = <1>;
100 #size-cells = <0>;
101 };
102
103 scrm_clockdomains: clockdomains {
104 };
105 };
106
107 cm: syscon@44e10000 {
108 compatible = "ti,am33xx-controlmodule", "syscon";
109 reg = <0x44e10000 0x800>;
110 };
111
112 edma: edma@49000000 {
113 compatible = "ti,edma3";
114 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
115 reg = <0x49000000 0x10000>,
116 <0x44e10f90 0x40>;
117 interrupts = <12 13 14>;
118 #dma-cells = <1>;
119 };
120
121 elm: elm@48080000 {
122 compatible = "ti,816-elm";
123 ti,hwmods = "elm";
124 reg = <0x48080000 0x2000>;
125 interrupts = <4>;
126 };
127
128 gpio1: gpio@48032000 {
129 compatible = "ti,omap3-gpio";
130 ti,hwmods = "gpio1";
131 reg = <0x48032000 0x1000>;
132 interrupts = <97>;
133 };
134
135 gpio2: gpio@4804c000 {
136 compatible = "ti,omap3-gpio";
137 ti,hwmods = "gpio2";
138 reg = <0x4804c000 0x1000>;
139 interrupts = <99>;
140 };
141
142 gpmc: gpmc@50000000 {
143 compatible = "ti,am3352-gpmc";
144 ti,hwmods = "gpmc";
145 reg = <0x50000000 0x2000>;
146 #address-cells = <2>;
147 #size-cells = <1>;
148 interrupts = <100>;
149 gpmc,num-cs = <6>;
150 gpmc,num-waitpins = <2>;
151 };
152
153 i2c1: i2c@48028000 {
154 compatible = "ti,omap4-i2c";
155 ti,hwmods = "i2c1";
156 reg = <0x48028000 0x1000>;
157 #address-cells = <1>;
158 #size-cells = <0>;
159 interrupts = <70>;
160 dmas = <&edma 58 &edma 59>;
161 dma-names = "tx", "rx";
162 };
163
164 i2c2: i2c@4802a000 {
165 compatible = "ti,omap4-i2c";
166 ti,hwmods = "i2c2";
167 reg = <0x4802a000 0x1000>;
168 #address-cells = <1>;
169 #size-cells = <0>;
170 interrupts = <71>;
171 dmas = <&edma 60 &edma 61>;
172 dma-names = "tx", "rx";
173 };
174
175 intc: interrupt-controller@48200000 {
176 compatible = "ti,dm816-intc";
177 interrupt-controller;
178 #interrupt-cells = <1>;
179 reg = <0x48200000 0x1000>;
180 };
181
182 mailbox: mailbox@480c8000 {
183 compatible = "ti,omap4-mailbox";
184 reg = <0x480c8000 0x2000>;
185 interrupts = <77>;
186 ti,hwmods = "mailbox";
187 ti,mbox-num-users = <4>;
188 ti,mbox-num-fifos = <12>;
189 mbox_dsp: mbox_dsp {
190 ti,mbox-tx = <3 0 0>;
191 ti,mbox-rx = <0 0 0>;
192 };
193 };
194
195 mdio: mdio@4a100800 {
196 compatible = "ti,davinci_mdio";
197 #address-cells = <1>;
198 #size-cells = <0>;
199 reg = <0x4a100800 0x100>;
200 ti,hwmods = "davinci_mdio";
201 bus_freq = <1000000>;
202 phy0: ethernet-phy@0 {
203 reg = <1>;
204 };
205 phy1: ethernet-phy@1 {
206 reg = <2>;
207 };
208 };
209
210 eth0: ethernet@4a100000 {
211 compatible = "ti,dm816-emac";
212 ti,hwmods = "emac0";
213 reg = <0x4a100000 0x800
214 0x4a100900 0x3700>;
215 clocks = <&sysclk24_ck>;
216 ti,davinci-ctrl-reg-offset = <0>;
217 ti,davinci-ctrl-mod-reg-offset = <0x900>;
218 ti,davinci-ctrl-ram-offset = <0x2000>;
219 ti,davinci-ctrl-ram-size = <0x2000>;
220 interrupts = <40 41 42 43>;
221 phy-handle = <&phy0>;
222 };
223
224 eth1: ethernet@4a120000 {
225 compatible = "ti,dm816-emac";
226 ti,hwmods = "emac1";
227 reg = <0x4a120000 0x4000>;
228 clocks = <&sysclk24_ck>;
229 ti,davinci-ctrl-reg-offset = <0>;
230 ti,davinci-ctrl-mod-reg-offset = <0x900>;
231 ti,davinci-ctrl-ram-offset = <0x2000>;
232 ti,davinci-ctrl-ram-size = <0x2000>;
233 interrupts = <44 45 46 47>;
234 phy-handle = <&phy1>;
235 };
236
237 mcspi1: spi@48030000 {
238 compatible = "ti,omap4-mcspi";
239 reg = <0x48030000 0x1000>;
240 #address-cells = <1>;
241 #size-cells = <0>;
242 interrupts = <65>;
243 ti,spi-num-cs = <4>;
244 ti,hwmods = "mcspi1";
245 dmas = <&edma 16 &edma 17
246 &edma 18 &edma 19>;
247 dma-names = "tx0", "rx0", "tx1", "rx1";
248 };
249
250 mmc1: mmc@48060000 {
251 compatible = "ti,omap4-hsmmc";
252 reg = <0x48060000 0x11000>;
253 ti,hwmods = "mmc1";
254 interrupts = <64>;
255 dmas = <&edma 24 &edma 25>;
256 dma-names = "tx", "rx";
257 };
258
259 timer1: timer@4802e000 {
260 compatible = "ti,dm816-timer";
261 reg = <0x4802e000 0x2000>;
262 interrupts = <67>;
263 ti,hwmods = "timer1";
264 ti,timer-alwon;
265 };
266
267 timer2: timer@48040000 {
268 compatible = "ti,dm816-timer";
269 reg = <0x48040000 0x2000>;
270 interrupts = <68>;
271 ti,hwmods = "timer2";
272 };
273
274 timer3: timer@48042000 {
275 compatible = "ti,dm816-timer";
276 reg = <0x48042000 0x2000>;
277 interrupts = <69>;
278 ti,hwmods = "timer3";
279 };
280
281 timer4: timer@48044000 {
282 compatible = "ti,dm816-timer";
283 reg = <0x48044000 0x2000>;
284 interrupts = <92>;
285 ti,hwmods = "timer4";
286 };
287
288 timer5: timer@48046000 {
289 compatible = "ti,dm816-timer";
290 reg = <0x48046000 0x2000>;
291 interrupts = <93>;
292 ti,hwmods = "timer5";
293 };
294
295 timer6: timer@48048000 {
296 compatible = "ti,dm816-timer";
297 reg = <0x48048000 0x2000>;
298 interrupts = <94>;
299 ti,hwmods = "timer6";
300 };
301
302 timer7: timer@4804a000 {
303 compatible = "ti,dm816-timer";
304 reg = <0x4804a000 0x2000>;
305 interrupts = <95>;
306 ti,hwmods = "timer7";
307 };
308
309 uart1: uart@48020000 {
310 compatible = "ti,omap3-uart";
311 ti,hwmods = "uart1";
312 reg = <0x48020000 0x2000>;
313 clock-frequency = <48000000>;
314 interrupts = <72>;
315 dmas = <&edma 26 &edma 27>;
316 dma-names = "tx", "rx";
317 };
318
319 uart2: uart@48022000 {
320 compatible = "ti,omap3-uart";
321 ti,hwmods = "uart2";
322 reg = <0x48022000 0x2000>;
323 clock-frequency = <48000000>;
324 interrupts = <73>;
325 dmas = <&edma 28 &edma 29>;
326 dma-names = "tx", "rx";
327 };
328
329 uart3: uart@48024000 {
330 compatible = "ti,omap3-uart";
331 ti,hwmods = "uart3";
332 reg = <0x48024000 0x2000>;
333 clock-frequency = <48000000>;
334 interrupts = <74>;
335 dmas = <&edma 30 &edma 31>;
336 dma-names = "tx", "rx";
337 };
338
339 /* NOTE: USB needs a transceiver driver for phys to work */
340 usb: usb_otg_hs@47401000 {
341 compatible = "ti,am33xx-usb";
342 reg = <0x47401000 0x400000>;
343 ranges;
344 #address-cells = <1>;
345 #size-cells = <1>;
346 ti,hwmods = "usb_otg_hs";
347
348 usb0: usb@47401000 {
349 compatible = "ti,musb-am33xx";
350 reg = <0x47401400 0x400
351 0x47401000 0x200>;
352 reg-names = "mc", "control";
353 interrupts = <18>;
354 interrupt-names = "mc";
355 dr_mode = "otg";
356 mentor,multipoint = <1>;
357 mentor,num-eps = <16>;
358 mentor,ram-bits = <12>;
359 mentor,power = <500>;
360 };
361
362 usb1: usb@47401800 {
363 compatible = "ti,musb-am33xx";
364 status = "disabled";
365 reg = <0x47401c00 0x400
366 0x47401800 0x200>;
367 reg-names = "mc", "control";
368 interrupts = <19>;
369 interrupt-names = "mc";
370 dr_mode = "otg";
371 mentor,multipoint = <1>;
372 mentor,num-eps = <16>;
373 mentor,ram-bits = <12>;
374 mentor,power = <500>;
375 };
376 };
377
378 wd_timer2: wd_timer@480c2000 {
379 compatible = "ti,omap3-wdt";
380 ti,hwmods = "wd_timer";
381 reg = <0x480c2000 0x1000>;
382 interrupts = <0>;
383 };
384 };
385};
386
387#include "dm816x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 22771bc1643a..fffe768477da 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1111,7 +1111,6 @@
1111 "wkupclk", "refclk", 1111 "wkupclk", "refclk",
1112 "div-clk", "phy-div"; 1112 "div-clk", "phy-div";
1113 #phy-cells = <0>; 1113 #phy-cells = <0>;
1114 id = <1>;
1115 ti,hwmods = "pcie1-phy"; 1114 ti,hwmods = "pcie1-phy";
1116 }; 1115 };
1117 1116
@@ -1132,7 +1131,6 @@
1132 "div-clk", "phy-div"; 1131 "div-clk", "phy-div";
1133 #phy-cells = <0>; 1132 #phy-cells = <0>;
1134 ti,hwmods = "pcie2-phy"; 1133 ti,hwmods = "pcie2-phy";
1135 id = <2>;
1136 status = "disabled"; 1134 status = "disabled";
1137 }; 1135 };
1138 }; 1136 };
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 89085d066c65..cacddd74c516 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -121,6 +121,18 @@
121 0x418 (MUX_MODE15) /* wakeup0.off */ 121 0x418 (MUX_MODE15) /* wakeup0.off */
122 >; 122 >;
123 }; 123 };
124
125 qspi1_pins: pinmux_qspi1_pins {
126 pinctrl-single,pins = <
127 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
128 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
129 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
130 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
131 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
132 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
133 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
134 >;
135 };
124}; 136};
125 137
126&i2c1 { 138&i2c1 {
@@ -461,3 +473,68 @@
461 pinctrl-0 = <&dcan1_pins_default>; 473 pinctrl-0 = <&dcan1_pins_default>;
462 pinctrl-1 = <&dcan1_pins_sleep>; 474 pinctrl-1 = <&dcan1_pins_sleep>;
463}; 475};
476
477&qspi {
478 status = "okay";
479 pinctrl-names = "default";
480 pinctrl-0 = <&qspi1_pins>;
481
482 spi-max-frequency = <48000000>;
483 m25p80@0 {
484 compatible = "s25fl256s1";
485 spi-max-frequency = <48000000>;
486 reg = <0>;
487 spi-tx-bus-width = <1>;
488 spi-rx-bus-width = <4>;
489 spi-cpol;
490 spi-cpha;
491 #address-cells = <1>;
492 #size-cells = <1>;
493
494 /* MTD partition table.
495 * The ROM checks the first four physical blocks
496 * for a valid file to boot and the flash here is
497 * 64KiB block size.
498 */
499 partition@0 {
500 label = "QSPI.SPL";
501 reg = <0x00000000 0x000010000>;
502 };
503 partition@1 {
504 label = "QSPI.SPL.backup1";
505 reg = <0x00010000 0x00010000>;
506 };
507 partition@2 {
508 label = "QSPI.SPL.backup2";
509 reg = <0x00020000 0x00010000>;
510 };
511 partition@3 {
512 label = "QSPI.SPL.backup3";
513 reg = <0x00030000 0x00010000>;
514 };
515 partition@4 {
516 label = "QSPI.u-boot";
517 reg = <0x00040000 0x00100000>;
518 };
519 partition@5 {
520 label = "QSPI.u-boot-spl-os";
521 reg = <0x00140000 0x00080000>;
522 };
523 partition@6 {
524 label = "QSPI.u-boot-env";
525 reg = <0x001c0000 0x00010000>;
526 };
527 partition@7 {
528 label = "QSPI.u-boot-env.backup1";
529 reg = <0x001d0000 0x0010000>;
530 };
531 partition@8 {
532 label = "QSPI.kernel";
533 reg = <0x001e0000 0x0800000>;
534 };
535 partition@9 {
536 label = "QSPI.file-system";
537 reg = <0x009e0000 0x01620000>;
538 };
539 };
540};
diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts
index 8f941c2db7c6..243044343ee8 100644
--- a/arch/arm/boot/dts/ethernut5.dts
+++ b/arch/arm/boot/dts/ethernut5.dts
@@ -6,7 +6,7 @@
6 * Licensed under GPLv2. 6 * Licensed under GPLv2.
7 */ 7 */
8/dts-v1/; 8/dts-v1/;
9#include "at91sam9260.dtsi" 9#include "at91sam9xe.dtsi"
10 10
11/ { 11/ {
12 model = "Ethernut 5"; 12 model = "Ethernut 5";
diff --git a/arch/arm/boot/dts/hip01-ca9x2.dts b/arch/arm/boot/dts/hip01-ca9x2.dts
new file mode 100644
index 000000000000..eca5e42770fe
--- /dev/null
+++ b/arch/arm/boot/dts/hip01-ca9x2.dts
@@ -0,0 +1,51 @@
1/*
2 * Hisilicon Ltd. HiP01 SoC
3 *
4 * Copyright (C) 2014 Hisilicon Ltd.
5 * Copyright (C) 2014 Huawei Ltd.
6 *
7 * Author: Wang Long <long.wanglong@huawei.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14/dts-v1/;
15
16/* First 8KB reserved for secondary core boot */
17/memreserve/ 0x80000000 0x00002000;
18
19#include "hip01.dtsi"
20
21/ {
22 model = "Hisilicon HIP01 Development Board";
23 compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01";
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "hisilicon,hip01-smp";
29
30 cpu@0 {
31 device_type = "cpu";
32 compatible = "arm,cortex-a9";
33 reg = <0>;
34 };
35
36 cpu@1 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a9";
39 reg = <1>;
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 reg = <0x80000000 0x80000000>;
46 };
47};
48
49&uart0 {
50 status = "okay";
51};
diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi
new file mode 100644
index 000000000000..33130f8461c3
--- /dev/null
+++ b/arch/arm/boot/dts/hip01.dtsi
@@ -0,0 +1,110 @@
1/*
2 * Hisilicon Ltd. HiP01 SoC
3 *
4 * Copyright (c) 2014 Hisilicon Ltd.
5 * Copyright (c) 2014 Huawei Ltd.
6 *
7 * Author: Wang Long <long.wanglong@huawei.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 gic: interrupt-controller@1e001000 {
22 compatible = "arm,cortex-a9-gic";
23 #interrupt-cells = <3>;
24 #address-cells = <0>;
25 interrupt-controller;
26 reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
27 };
28
29 hisi_refclk144mhz: refclk144mkhz {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <144000000>;
33 clock-output-names = "hisi:refclk144khz";
34 };
35
36 soc {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "simple-bus";
40 interrupt-parent = <&gic>;
41 ranges = <0 0x10000000 0x20000000>;
42
43 amba {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "arm,amba-bus";
47 ranges;
48
49 uart0: uart@10001000 {
50 compatible = "snps,dw-apb-uart";
51 reg = <0x10001000 0x1000>;
52 clocks = <&hisi_refclk144mhz>;
53 clock-names = "apb_pclk";
54 reg-shift = <2>;
55 interrupts = <0 32 4>;
56 status = "disabled";
57 };
58
59 uart1: uart@10002000 {
60 compatible = "snps,dw-apb-uart";
61 reg = <0x10002000 0x1000>;
62 clocks = <&hisi_refclk144mhz>;
63 clock-names = "apb_pclk";
64 reg-shift = <2>;
65 interrupts = <0 33 4>;
66 status = "disabled";
67 };
68
69 uart2: uart@10003000 {
70 compatible = "snps,dw-apb-uart";
71 reg = <0x10003000 0x1000>;
72 clocks = <&hisi_refclk144mhz>;
73 clock-names = "apb_pclk";
74 reg-shift = <2>;
75 interrupts = <0 34 4>;
76 status = "disabled";
77 };
78
79 uart3: uart@10006000 {
80 compatible = "snps,dw-apb-uart";
81 reg = <0x10006000 0x1000>;
82 clocks = <&hisi_refclk144mhz>;
83 clock-names = "apb_pclk";
84 reg-shift = <2>;
85 interrupts = <0 4 4>;
86 status = "disabled";
87 };
88 };
89
90 system-controller@10000000 {
91 compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
92 reg = <0x10000000 0x1000>;
93 reboot-offset = <0x4>;
94 };
95
96 global_timer@0a000200 {
97 compatible = "arm,cortex-a9-global-timer";
98 reg = <0x0a000200 0x100>;
99 interrupts = <1 11 0xf04>;
100 clocks = <&hisi_refclk144mhz>;
101 };
102
103 local_timer@0a000600 {
104 compatible = "arm,cortex-a9-twd-timer";
105 reg = <0x0a000600 0x100>;
106 interrupts = <1 13 0xf04>;
107 clocks = <&hisi_refclk144mhz>;
108 };
109 };
110};
diff --git a/arch/arm/boot/dts/marco-evb.dts b/arch/arm/boot/dts/marco-evb.dts
deleted file mode 100644
index 5130aeacfca5..000000000000
--- a/arch/arm/boot/dts/marco-evb.dts
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * DTS file for CSR SiRFmarco Evaluation Board
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/dts-v1/;
10
11/include/ "marco.dtsi"
12
13/ {
14 model = "CSR SiRFmarco Evaluation Board";
15 compatible = "sirf,marco-cb", "sirf,marco";
16
17 memory {
18 reg = <0x40000000 0x60000000>;
19 };
20
21 axi {
22 peri-iobg {
23 uart1: uart@cc060000 {
24 status = "okay";
25 };
26 uart2: uart@cc070000 {
27 status = "okay";
28 };
29 i2c0: i2c@cc0e0000 {
30 status = "okay";
31 fpga-cpld@4d {
32 compatible = "sirf,fpga-cpld";
33 reg = <0x4d>;
34 };
35 };
36 spi1: spi@cc170000 {
37 status = "okay";
38 pinctrl-names = "default";
39 pinctrl-0 = <&spi1_pins_a>;
40 spi@0 {
41 compatible = "spidev";
42 reg = <0>;
43 spi-max-frequency = <1000000>;
44 };
45 };
46 pci-iobg {
47 sd0: sdhci@cd000000 {
48 bus-width = <8>;
49 status = "okay";
50 };
51 };
52 };
53 };
54};
diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi
deleted file mode 100644
index fb354225740a..000000000000
--- a/arch/arm/boot/dts/marco.dtsi
+++ /dev/null
@@ -1,757 +0,0 @@
1/*
2 * DTS file for CSR SiRFmarco SoC
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/include/ "skeleton.dtsi"
10/ {
11 compatible = "sirf,marco";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a9";
23 reg = <0>;
24 };
25 cpu@1 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a9";
28 reg = <1>;
29 };
30 };
31
32 axi {
33 compatible = "simple-bus";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 ranges = <0x40000000 0x40000000 0xa0000000>;
37
38 l2-cache-controller@c0030000 {
39 compatible = "arm,pl310-cache";
40 reg = <0xc0030000 0x1000>;
41 interrupts = <0 59 0>;
42 arm,tag-latency = <1 1 1>;
43 arm,data-latency = <1 1 1>;
44 arm,filter-ranges = <0x40000000 0x80000000>;
45 };
46
47 gic: interrupt-controller@c0011000 {
48 compatible = "arm,cortex-a9-gic";
49 interrupt-controller;
50 #interrupt-cells = <3>;
51 reg = <0xc0011000 0x1000>,
52 <0xc0010100 0x0100>;
53 };
54
55 rstc-iobg {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges = <0xc2000000 0xc2000000 0x1000000>;
60
61 rstc: reset-controller@c2000000 {
62 compatible = "sirf,marco-rstc";
63 reg = <0xc2000000 0x10000>;
64 #reset-cells = <1>;
65 };
66 };
67
68 sys-iobg {
69 compatible = "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 ranges = <0xc3000000 0xc3000000 0x1000000>;
73
74 clock-controller@c3000000 {
75 compatible = "sirf,marco-clkc";
76 reg = <0xc3000000 0x1000>;
77 interrupts = <0 3 0>;
78 };
79
80 rsc-controller@c3010000 {
81 compatible = "sirf,marco-rsc";
82 reg = <0xc3010000 0x1000>;
83 };
84 };
85
86 mem-iobg {
87 compatible = "simple-bus";
88 #address-cells = <1>;
89 #size-cells = <1>;
90 ranges = <0xc4000000 0xc4000000 0x1000000>;
91
92 memory-controller@c4000000 {
93 compatible = "sirf,marco-memc";
94 reg = <0xc4000000 0x10000>;
95 interrupts = <0 27 0>;
96 };
97 };
98
99 disp-iobg0 {
100 compatible = "simple-bus";
101 #address-cells = <1>;
102 #size-cells = <1>;
103 ranges = <0xc5000000 0xc5000000 0x1000000>;
104
105 display0@c5000000 {
106 compatible = "sirf,marco-lcd";
107 reg = <0xc5000000 0x10000>;
108 interrupts = <0 30 0>;
109 };
110
111 vpp0@c5010000 {
112 compatible = "sirf,marco-vpp";
113 reg = <0xc5010000 0x10000>;
114 interrupts = <0 31 0>;
115 };
116 };
117
118 disp-iobg1 {
119 compatible = "simple-bus";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 ranges = <0xc6000000 0xc6000000 0x1000000>;
123
124 display1@c6000000 {
125 compatible = "sirf,marco-lcd";
126 reg = <0xc6000000 0x10000>;
127 interrupts = <0 62 0>;
128 };
129
130 vpp1@c6010000 {
131 compatible = "sirf,marco-vpp";
132 reg = <0xc6010000 0x10000>;
133 interrupts = <0 63 0>;
134 };
135 };
136
137 graphics-iobg {
138 compatible = "simple-bus";
139 #address-cells = <1>;
140 #size-cells = <1>;
141 ranges = <0xc8000000 0xc8000000 0x1000000>;
142
143 graphics@c8000000 {
144 compatible = "powervr,sgx540";
145 reg = <0xc8000000 0x1000000>;
146 interrupts = <0 6 0>;
147 };
148 };
149
150 multimedia-iobg {
151 compatible = "simple-bus";
152 #address-cells = <1>;
153 #size-cells = <1>;
154 ranges = <0xc9000000 0xc9000000 0x1000000>;
155
156 multimedia@a0000000 {
157 compatible = "sirf,marco-video-codec";
158 reg = <0xc9000000 0x1000000>;
159 interrupts = <0 5 0>;
160 };
161 };
162
163 dsp-iobg {
164 compatible = "simple-bus";
165 #address-cells = <1>;
166 #size-cells = <1>;
167 ranges = <0xca000000 0xca000000 0x2000000>;
168
169 dspif@ca000000 {
170 compatible = "sirf,marco-dspif";
171 reg = <0xca000000 0x10000>;
172 interrupts = <0 9 0>;
173 };
174
175 gps@ca010000 {
176 compatible = "sirf,marco-gps";
177 reg = <0xca010000 0x10000>;
178 interrupts = <0 7 0>;
179 };
180
181 dsp@cb000000 {
182 compatible = "sirf,marco-dsp";
183 reg = <0xcb000000 0x1000000>;
184 interrupts = <0 8 0>;
185 };
186 };
187
188 peri-iobg {
189 compatible = "simple-bus";
190 #address-cells = <1>;
191 #size-cells = <1>;
192 ranges = <0xcc000000 0xcc000000 0x2000000>;
193
194 timer@cc020000 {
195 compatible = "sirf,marco-tick";
196 reg = <0xcc020000 0x1000>;
197 interrupts = <0 0 0>,
198 <0 1 0>,
199 <0 2 0>,
200 <0 49 0>,
201 <0 50 0>,
202 <0 51 0>;
203 };
204
205 nand@cc030000 {
206 compatible = "sirf,marco-nand";
207 reg = <0xcc030000 0x10000>;
208 interrupts = <0 41 0>;
209 };
210
211 audio@cc040000 {
212 compatible = "sirf,marco-audio";
213 reg = <0xcc040000 0x10000>;
214 interrupts = <0 35 0>;
215 };
216
217 uart0: uart@cc050000 {
218 cell-index = <0>;
219 compatible = "sirf,marco-uart";
220 reg = <0xcc050000 0x1000>;
221 interrupts = <0 17 0>;
222 fifosize = <128>;
223 status = "disabled";
224 };
225
226 uart1: uart@cc060000 {
227 cell-index = <1>;
228 compatible = "sirf,marco-uart";
229 reg = <0xcc060000 0x1000>;
230 interrupts = <0 18 0>;
231 fifosize = <32>;
232 status = "disabled";
233 };
234
235 uart2: uart@cc070000 {
236 cell-index = <2>;
237 compatible = "sirf,marco-uart";
238 reg = <0xcc070000 0x1000>;
239 interrupts = <0 19 0>;
240 fifosize = <128>;
241 status = "disabled";
242 };
243
244 uart3: uart@cc190000 {
245 cell-index = <3>;
246 compatible = "sirf,marco-uart";
247 reg = <0xcc190000 0x1000>;
248 interrupts = <0 66 0>;
249 fifosize = <128>;
250 status = "disabled";
251 };
252
253 uart4: uart@cc1a0000 {
254 cell-index = <4>;
255 compatible = "sirf,marco-uart";
256 reg = <0xcc1a0000 0x1000>;
257 interrupts = <0 69 0>;
258 fifosize = <128>;
259 status = "disabled";
260 };
261
262 usp0: usp@cc080000 {
263 cell-index = <0>;
264 compatible = "sirf,marco-usp";
265 reg = <0xcc080000 0x10000>;
266 interrupts = <0 20 0>;
267 status = "disabled";
268 };
269
270 usp1: usp@cc090000 {
271 cell-index = <1>;
272 compatible = "sirf,marco-usp";
273 reg = <0xcc090000 0x10000>;
274 interrupts = <0 21 0>;
275 status = "disabled";
276 };
277
278 usp2: usp@cc0a0000 {
279 cell-index = <2>;
280 compatible = "sirf,marco-usp";
281 reg = <0xcc0a0000 0x10000>;
282 interrupts = <0 22 0>;
283 status = "disabled";
284 };
285
286 dmac0: dma-controller@cc0b0000 {
287 cell-index = <0>;
288 compatible = "sirf,marco-dmac";
289 reg = <0xcc0b0000 0x10000>;
290 interrupts = <0 12 0>;
291 };
292
293 dmac1: dma-controller@cc160000 {
294 cell-index = <1>;
295 compatible = "sirf,marco-dmac";
296 reg = <0xcc160000 0x10000>;
297 interrupts = <0 13 0>;
298 };
299
300 vip@cc0c0000 {
301 compatible = "sirf,marco-vip";
302 reg = <0xcc0c0000 0x10000>;
303 };
304
305 spi0: spi@cc0d0000 {
306 cell-index = <0>;
307 compatible = "sirf,marco-spi";
308 reg = <0xcc0d0000 0x10000>;
309 interrupts = <0 15 0>;
310 sirf,spi-num-chipselects = <1>;
311 cs-gpios = <&gpio 0 0>;
312 sirf,spi-dma-rx-channel = <25>;
313 sirf,spi-dma-tx-channel = <20>;
314 #address-cells = <1>;
315 #size-cells = <0>;
316 status = "disabled";
317 };
318
319 spi1: spi@cc170000 {
320 cell-index = <1>;
321 compatible = "sirf,marco-spi";
322 reg = <0xcc170000 0x10000>;
323 interrupts = <0 16 0>;
324 sirf,spi-num-chipselects = <1>;
325 cs-gpios = <&gpio 0 0>;
326 sirf,spi-dma-rx-channel = <12>;
327 sirf,spi-dma-tx-channel = <13>;
328 #address-cells = <1>;
329 #size-cells = <0>;
330 status = "disabled";
331 };
332
333 i2c0: i2c@cc0e0000 {
334 cell-index = <0>;
335 compatible = "sirf,marco-i2c";
336 reg = <0xcc0e0000 0x10000>;
337 interrupts = <0 24 0>;
338 #address-cells = <1>;
339 #size-cells = <0>;
340 status = "disabled";
341 };
342
343 i2c1: i2c@cc0f0000 {
344 cell-index = <1>;
345 compatible = "sirf,marco-i2c";
346 reg = <0xcc0f0000 0x10000>;
347 interrupts = <0 25 0>;
348 #address-cells = <1>;
349 #size-cells = <0>;
350 status = "disabled";
351 };
352
353 tsc@cc110000 {
354 compatible = "sirf,marco-tsc";
355 reg = <0xcc110000 0x10000>;
356 interrupts = <0 33 0>;
357 };
358
359 gpio: pinctrl@cc120000 {
360 #gpio-cells = <2>;
361 #interrupt-cells = <2>;
362 compatible = "sirf,marco-pinctrl";
363 reg = <0xcc120000 0x10000>;
364 interrupts = <0 43 0>,
365 <0 44 0>,
366 <0 45 0>,
367 <0 46 0>,
368 <0 47 0>;
369 gpio-controller;
370 interrupt-controller;
371
372 lcd_16pins_a: lcd0_0 {
373 lcd {
374 sirf,pins = "lcd_16bitsgrp";
375 sirf,function = "lcd_16bits";
376 };
377 };
378 lcd_18pins_a: lcd0_1 {
379 lcd {
380 sirf,pins = "lcd_18bitsgrp";
381 sirf,function = "lcd_18bits";
382 };
383 };
384 lcd_24pins_a: lcd0_2 {
385 lcd {
386 sirf,pins = "lcd_24bitsgrp";
387 sirf,function = "lcd_24bits";
388 };
389 };
390 lcdrom_pins_a: lcdrom0_0 {
391 lcd {
392 sirf,pins = "lcdromgrp";
393 sirf,function = "lcdrom";
394 };
395 };
396 uart0_pins_a: uart0_0 {
397 uart {
398 sirf,pins = "uart0grp";
399 sirf,function = "uart0";
400 };
401 };
402 uart1_pins_a: uart1_0 {
403 uart {
404 sirf,pins = "uart1grp";
405 sirf,function = "uart1";
406 };
407 };
408 uart2_pins_a: uart2_0 {
409 uart {
410 sirf,pins = "uart2grp";
411 sirf,function = "uart2";
412 };
413 };
414 uart2_noflow_pins_a: uart2_1 {
415 uart {
416 sirf,pins = "uart2_nostreamctrlgrp";
417 sirf,function = "uart2_nostreamctrl";
418 };
419 };
420 spi0_pins_a: spi0_0 {
421 spi {
422 sirf,pins = "spi0grp";
423 sirf,function = "spi0";
424 };
425 };
426 spi1_pins_a: spi1_0 {
427 spi {
428 sirf,pins = "spi1grp";
429 sirf,function = "spi1";
430 };
431 };
432 i2c0_pins_a: i2c0_0 {
433 i2c {
434 sirf,pins = "i2c0grp";
435 sirf,function = "i2c0";
436 };
437 };
438 i2c1_pins_a: i2c1_0 {
439 i2c {
440 sirf,pins = "i2c1grp";
441 sirf,function = "i2c1";
442 };
443 };
444 pwm0_pins_a: pwm0_0 {
445 pwm {
446 sirf,pins = "pwm0grp";
447 sirf,function = "pwm0";
448 };
449 };
450 pwm1_pins_a: pwm1_0 {
451 pwm {
452 sirf,pins = "pwm1grp";
453 sirf,function = "pwm1";
454 };
455 };
456 pwm2_pins_a: pwm2_0 {
457 pwm {
458 sirf,pins = "pwm2grp";
459 sirf,function = "pwm2";
460 };
461 };
462 pwm3_pins_a: pwm3_0 {
463 pwm {
464 sirf,pins = "pwm3grp";
465 sirf,function = "pwm3";
466 };
467 };
468 gps_pins_a: gps_0 {
469 gps {
470 sirf,pins = "gpsgrp";
471 sirf,function = "gps";
472 };
473 };
474 vip_pins_a: vip_0 {
475 vip {
476 sirf,pins = "vipgrp";
477 sirf,function = "vip";
478 };
479 };
480 sdmmc0_pins_a: sdmmc0_0 {
481 sdmmc0 {
482 sirf,pins = "sdmmc0grp";
483 sirf,function = "sdmmc0";
484 };
485 };
486 sdmmc1_pins_a: sdmmc1_0 {
487 sdmmc1 {
488 sirf,pins = "sdmmc1grp";
489 sirf,function = "sdmmc1";
490 };
491 };
492 sdmmc2_pins_a: sdmmc2_0 {
493 sdmmc2 {
494 sirf,pins = "sdmmc2grp";
495 sirf,function = "sdmmc2";
496 };
497 };
498 sdmmc3_pins_a: sdmmc3_0 {
499 sdmmc3 {
500 sirf,pins = "sdmmc3grp";
501 sirf,function = "sdmmc3";
502 };
503 };
504 sdmmc4_pins_a: sdmmc4_0 {
505 sdmmc4 {
506 sirf,pins = "sdmmc4grp";
507 sirf,function = "sdmmc4";
508 };
509 };
510 sdmmc5_pins_a: sdmmc5_0 {
511 sdmmc5 {
512 sirf,pins = "sdmmc5grp";
513 sirf,function = "sdmmc5";
514 };
515 };
516 i2s_pins_a: i2s_0 {
517 i2s {
518 sirf,pins = "i2sgrp";
519 sirf,function = "i2s";
520 };
521 };
522 ac97_pins_a: ac97_0 {
523 ac97 {
524 sirf,pins = "ac97grp";
525 sirf,function = "ac97";
526 };
527 };
528 nand_pins_a: nand_0 {
529 nand {
530 sirf,pins = "nandgrp";
531 sirf,function = "nand";
532 };
533 };
534 usp0_pins_a: usp0_0 {
535 usp0 {
536 sirf,pins = "usp0grp";
537 sirf,function = "usp0";
538 };
539 };
540 usp1_pins_a: usp1_0 {
541 usp1 {
542 sirf,pins = "usp1grp";
543 sirf,function = "usp1";
544 };
545 };
546 usp2_pins_a: usp2_0 {
547 usp2 {
548 sirf,pins = "usp2grp";
549 sirf,function = "usp2";
550 };
551 };
552 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus_0 {
553 usb0_utmi_drvbus {
554 sirf,pins = "usb0_utmi_drvbusgrp";
555 sirf,function = "usb0_utmi_drvbus";
556 };
557 };
558 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus_0 {
559 usb1_utmi_drvbus {
560 sirf,pins = "usb1_utmi_drvbusgrp";
561 sirf,function = "usb1_utmi_drvbus";
562 };
563 };
564 warm_rst_pins_a: warm_rst_0 {
565 warm_rst {
566 sirf,pins = "warm_rstgrp";
567 sirf,function = "warm_rst";
568 };
569 };
570 pulse_count_pins_a: pulse_count_0 {
571 pulse_count {
572 sirf,pins = "pulse_countgrp";
573 sirf,function = "pulse_count";
574 };
575 };
576 cko0_rst_pins_a: cko0_rst_0 {
577 cko0_rst {
578 sirf,pins = "cko0_rstgrp";
579 sirf,function = "cko0_rst";
580 };
581 };
582 cko1_rst_pins_a: cko1_rst_0 {
583 cko1_rst {
584 sirf,pins = "cko1_rstgrp";
585 sirf,function = "cko1_rst";
586 };
587 };
588 };
589
590 pwm@cc130000 {
591 compatible = "sirf,marco-pwm";
592 reg = <0xcc130000 0x10000>;
593 };
594
595 efusesys@cc140000 {
596 compatible = "sirf,marco-efuse";
597 reg = <0xcc140000 0x10000>;
598 };
599
600 pulsec@cc150000 {
601 compatible = "sirf,marco-pulsec";
602 reg = <0xcc150000 0x10000>;
603 interrupts = <0 48 0>;
604 };
605
606 pci-iobg {
607 compatible = "sirf,marco-pciiobg", "simple-bus";
608 #address-cells = <1>;
609 #size-cells = <1>;
610 ranges = <0xcd000000 0xcd000000 0x1000000>;
611
612 sd0: sdhci@cd000000 {
613 cell-index = <0>;
614 compatible = "sirf,marco-sdhc";
615 reg = <0xcd000000 0x100000>;
616 interrupts = <0 38 0>;
617 status = "disabled";
618 };
619
620 sd1: sdhci@cd100000 {
621 cell-index = <1>;
622 compatible = "sirf,marco-sdhc";
623 reg = <0xcd100000 0x100000>;
624 interrupts = <0 38 0>;
625 status = "disabled";
626 };
627
628 sd2: sdhci@cd200000 {
629 cell-index = <2>;
630 compatible = "sirf,marco-sdhc";
631 reg = <0xcd200000 0x100000>;
632 interrupts = <0 23 0>;
633 status = "disabled";
634 };
635
636 sd3: sdhci@cd300000 {
637 cell-index = <3>;
638 compatible = "sirf,marco-sdhc";
639 reg = <0xcd300000 0x100000>;
640 interrupts = <0 23 0>;
641 status = "disabled";
642 };
643
644 sd4: sdhci@cd400000 {
645 cell-index = <4>;
646 compatible = "sirf,marco-sdhc";
647 reg = <0xcd400000 0x100000>;
648 interrupts = <0 39 0>;
649 status = "disabled";
650 };
651
652 sd5: sdhci@cd500000 {
653 cell-index = <5>;
654 compatible = "sirf,marco-sdhc";
655 reg = <0xcd500000 0x100000>;
656 interrupts = <0 39 0>;
657 status = "disabled";
658 };
659
660 pci-copy@cd900000 {
661 compatible = "sirf,marco-pcicp";
662 reg = <0xcd900000 0x100000>;
663 interrupts = <0 40 0>;
664 };
665
666 rom-interface@cda00000 {
667 compatible = "sirf,marco-romif";
668 reg = <0xcda00000 0x100000>;
669 };
670 };
671 };
672
673 rtc-iobg {
674 compatible = "sirf,marco-rtciobg", "sirf-marco-rtciobg-bus";
675 #address-cells = <1>;
676 #size-cells = <1>;
677 reg = <0xc1000000 0x10000>;
678
679 gpsrtc@1000 {
680 compatible = "sirf,marco-gpsrtc";
681 reg = <0x1000 0x1000>;
682 interrupts = <0 55 0>,
683 <0 56 0>,
684 <0 57 0>;
685 };
686
687 sysrtc@2000 {
688 compatible = "sirf,marco-sysrtc";
689 reg = <0x2000 0x1000>;
690 interrupts = <0 52 0>,
691 <0 53 0>,
692 <0 54 0>;
693 };
694
695 pwrc@3000 {
696 compatible = "sirf,marco-pwrc";
697 reg = <0x3000 0x1000>;
698 interrupts = <0 32 0>;
699 };
700 };
701
702 uus-iobg {
703 compatible = "simple-bus";
704 #address-cells = <1>;
705 #size-cells = <1>;
706 ranges = <0xce000000 0xce000000 0x1000000>;
707
708 usb0: usb@ce000000 {
709 compatible = "chipidea,ci13611a-marco";
710 reg = <0xce000000 0x10000>;
711 interrupts = <0 10 0>;
712 };
713
714 usb1: usb@ce010000 {
715 compatible = "chipidea,ci13611a-marco";
716 reg = <0xce010000 0x10000>;
717 interrupts = <0 11 0>;
718 };
719
720 security@ce020000 {
721 compatible = "sirf,marco-security";
722 reg = <0xce020000 0x10000>;
723 interrupts = <0 42 0>;
724 };
725 };
726
727 can-iobg {
728 compatible = "simple-bus";
729 #address-cells = <1>;
730 #size-cells = <1>;
731 ranges = <0xd0000000 0xd0000000 0x1000000>;
732
733 can0: can@d0000000 {
734 compatible = "sirf,marco-can";
735 reg = <0xd0000000 0x10000>;
736 };
737
738 can1: can@d0010000 {
739 compatible = "sirf,marco-can";
740 reg = <0xd0010000 0x10000>;
741 };
742 };
743
744 lvds-iobg {
745 compatible = "simple-bus";
746 #address-cells = <1>;
747 #size-cells = <1>;
748 ranges = <0xd1000000 0xd1000000 0x1000000>;
749
750 lvds@d1000000 {
751 compatible = "sirf,marco-lvds";
752 reg = <0xd1000000 0x10000>;
753 interrupts = <0 64 0>;
754 };
755 };
756 };
757};
diff --git a/arch/arm/boot/dts/mt6589-aquaris5.dts b/arch/arm/boot/dts/mt6589-aquaris5.dts
index 0da047013120..594a6f3bebda 100644
--- a/arch/arm/boot/dts/mt6589-aquaris5.dts
+++ b/arch/arm/boot/dts/mt6589-aquaris5.dts
@@ -21,10 +21,20 @@
21 compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589"; 21 compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";
22 22
23 chosen { 23 chosen {
24 bootargs = "earlyprintk"; 24 bootargs = "console=ttyS0,921600n8 earlyprintk";
25 stdout-path = &uart0;
25 }; 26 };
26 27
27 memory { 28 memory {
28 reg = <0x80000000 0x40000000>; 29 reg = <0x80000000 0x40000000>;
29 }; 30 };
31
32};
33
34&uart0 {
35 status = "okay";
36};
37
38&uart3 {
39 status = "okay";
30}; 40};
diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
index e3c7600ddb38..106b61b10030 100644
--- a/arch/arm/boot/dts/mt6589.dtsi
+++ b/arch/arm/boot/dts/mt6589.dtsi
@@ -19,7 +19,7 @@
19 19
20/ { 20/ {
21 compatible = "mediatek,mt6589"; 21 compatible = "mediatek,mt6589";
22 interrupt-parent = <&gic>; 22 interrupt-parent = <&sysirq>;
23 23
24 cpus { 24 cpus {
25 #address-cells = <1>; 25 #address-cells = <1>;
@@ -65,6 +65,12 @@
65 clock-frequency = <32000>; 65 clock-frequency = <32000>;
66 #clock-cells = <0>; 66 #clock-cells = <0>;
67 }; 67 };
68
69 uart_clk: dummy26m {
70 compatible = "fixed-clock";
71 clock-frequency = <26000000>;
72 #clock-cells = <0>;
73 };
68 }; 74 };
69 75
70 soc { 76 soc {
@@ -76,19 +82,61 @@
76 timer: timer@10008000 { 82 timer: timer@10008000 {
77 compatible = "mediatek,mt6577-timer"; 83 compatible = "mediatek,mt6577-timer";
78 reg = <0x10008000 0x80>; 84 reg = <0x10008000 0x80>;
79 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; 85 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
80 clocks = <&system_clk>, <&rtc_clk>; 86 clocks = <&system_clk>, <&rtc_clk>;
81 clock-names = "system-clk", "rtc-clk"; 87 clock-names = "system-clk", "rtc-clk";
82 }; 88 };
83 89
90 sysirq: interrupt-controller@10200100 {
91 compatible = "mediatek,mt6589-sysirq",
92 "mediatek,mt6577-sysirq";
93 interrupt-controller;
94 #interrupt-cells = <3>;
95 interrupt-parent = <&gic>;
96 reg = <0x10200100 0x1c>;
97 };
98
84 gic: interrupt-controller@10211000 { 99 gic: interrupt-controller@10211000 {
85 compatible = "arm,cortex-a7-gic"; 100 compatible = "arm,cortex-a7-gic";
86 interrupt-controller; 101 interrupt-controller;
87 #interrupt-cells = <3>; 102 #interrupt-cells = <3>;
103 interrupt-parent = <&gic>;
88 reg = <0x10211000 0x1000>, 104 reg = <0x10211000 0x1000>,
89 <0x10212000 0x1000>, 105 <0x10212000 0x1000>,
90 <0x10214000 0x2000>, 106 <0x10214000 0x2000>,
91 <0x10216000 0x2000>; 107 <0x10216000 0x2000>;
92 }; 108 };
109
110 uart0: serial@11006000 {
111 compatible = "mediatek,mt6577-uart";
112 reg = <0x11006000 0x400>;
113 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
114 clocks = <&uart_clk>;
115 status = "disabled";
116 };
117
118 uart1: serial@11007000 {
119 compatible = "mediatek,mt6577-uart";
120 reg = <0x11007000 0x400>;
121 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
122 clocks = <&uart_clk>;
123 status = "disabled";
124 };
125
126 uart2: serial@11008000 {
127 compatible = "mediatek,mt6577-uart";
128 reg = <0x11008000 0x400>;
129 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
130 clocks = <&uart_clk>;
131 status = "disabled";
132 };
133
134 uart3: serial@11009000 {
135 compatible = "mediatek,mt6577-uart";
136 reg = <0x11009000 0x400>;
137 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
138 clocks = <&uart_clk>;
139 status = "disabled";
140 };
93 }; 141 };
94}; 142};
diff --git a/arch/arm/boot/dts/mt6592.dtsi b/arch/arm/boot/dts/mt6592.dtsi
index 31e5a0979d78..67c817418392 100644
--- a/arch/arm/boot/dts/mt6592.dtsi
+++ b/arch/arm/boot/dts/mt6592.dtsi
@@ -18,7 +18,7 @@
18 18
19/ { 19/ {
20 compatible = "mediatek,mt6592"; 20 compatible = "mediatek,mt6592";
21 interrupt-parent = <&gic>; 21 interrupt-parent = <&sysirq>;
22 22
23 cpus { 23 cpus {
24 #address-cells = <1>; 24 #address-cells = <1>;
@@ -81,18 +81,25 @@
81 timer: timer@10008000 { 81 timer: timer@10008000 {
82 compatible = "mediatek,mt6577-timer"; 82 compatible = "mediatek,mt6577-timer";
83 reg = <0x10008000 0x80>; 83 reg = <0x10008000 0x80>;
84 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 84 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
85 clocks = <&system_clk>, <&rtc_clk>; 85 clocks = <&system_clk>, <&rtc_clk>;
86 clock-names = "system-clk", "rtc-clk"; 86 clock-names = "system-clk", "rtc-clk";
87 }; 87 };
88 88
89 sysirq: interrupt-controller@10200220 {
90 compatible = "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq";
91 interrupt-controller;
92 #interrupt-cells = <3>;
93 interrupt-parent = <&gic>;
94 reg = <0x10200220 0x1c>;
95 };
96
89 gic: interrupt-controller@10211000 { 97 gic: interrupt-controller@10211000 {
90 compatible = "arm,cortex-a7-gic"; 98 compatible = "arm,cortex-a7-gic";
91 interrupt-controller; 99 interrupt-controller;
92 #interrupt-cells = <3>; 100 #interrupt-cells = <3>;
101 interrupt-parent = <&gic>;
93 reg = <0x10211000 0x1000>, 102 reg = <0x10211000 0x1000>,
94 <0x10212000 0x1000>; 103 <0x10212000 0x1000>;
95 }; 104 };
96
97}; 105};
98
diff --git a/arch/arm/boot/dts/mt8127-moose.dts b/arch/arm/boot/dts/mt8127-moose.dts
index 13cba0e77e08..073e295a1cb4 100644
--- a/arch/arm/boot/dts/mt8127-moose.dts
+++ b/arch/arm/boot/dts/mt8127-moose.dts
@@ -23,3 +23,7 @@
23 reg = <0 0x80000000 0 0x40000000>; 23 reg = <0 0x80000000 0 0x40000000>;
24 }; 24 };
25}; 25};
26
27&uart0 {
28 status = "okay";
29};
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
index b24c0a2f3c44..aaa786233d93 100644
--- a/arch/arm/boot/dts/mt8127.dtsi
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -18,7 +18,7 @@
18 18
19/ { 19/ {
20 compatible = "mediatek,mt8127"; 20 compatible = "mediatek,mt8127";
21 interrupt-parent = <&gic>; 21 interrupt-parent = <&sysirq>;
22 22
23 cpus { 23 cpus {
24 #address-cells = <1>; 24 #address-cells = <1>;
@@ -64,6 +64,12 @@
64 clock-frequency = <32000>; 64 clock-frequency = <32000>;
65 #clock-cells = <0>; 65 #clock-cells = <0>;
66 }; 66 };
67
68 uart_clk: dummy26m {
69 compatible = "fixed-clock";
70 clock-frequency = <26000000>;
71 #clock-cells = <0>;
72 };
67 }; 73 };
68 74
69 soc { 75 soc {
@@ -76,19 +82,61 @@
76 compatible = "mediatek,mt8127-timer", 82 compatible = "mediatek,mt8127-timer",
77 "mediatek,mt6577-timer"; 83 "mediatek,mt6577-timer";
78 reg = <0 0x10008000 0 0x80>; 84 reg = <0 0x10008000 0 0x80>;
79 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 85 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
80 clocks = <&system_clk>, <&rtc_clk>; 86 clocks = <&system_clk>, <&rtc_clk>;
81 clock-names = "system-clk", "rtc-clk"; 87 clock-names = "system-clk", "rtc-clk";
82 }; 88 };
83 89
90 sysirq: interrupt-controller@10200100 {
91 compatible = "mediatek,mt8127-sysirq",
92 "mediatek,mt6577-sysirq";
93 interrupt-controller;
94 #interrupt-cells = <3>;
95 interrupt-parent = <&gic>;
96 reg = <0 0x10200100 0 0x1c>;
97 };
98
84 gic: interrupt-controller@10211000 { 99 gic: interrupt-controller@10211000 {
85 compatible = "arm,cortex-a7-gic"; 100 compatible = "arm,cortex-a7-gic";
86 interrupt-controller; 101 interrupt-controller;
87 #interrupt-cells = <3>; 102 #interrupt-cells = <3>;
103 interrupt-parent = <&gic>;
88 reg = <0 0x10211000 0 0x1000>, 104 reg = <0 0x10211000 0 0x1000>,
89 <0 0x10212000 0 0x1000>, 105 <0 0x10212000 0 0x1000>,
90 <0 0x10214000 0 0x2000>, 106 <0 0x10214000 0 0x2000>,
91 <0 0x10216000 0 0x2000>; 107 <0 0x10216000 0 0x2000>;
92 }; 108 };
109
110 uart0: serial@11006000 {
111 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
112 reg = <0 0x11002000 0 0x400>;
113 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
114 clocks = <&uart_clk>;
115 status = "disabled";
116 };
117
118 uart1: serial@11007000 {
119 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
120 reg = <0 0x11003000 0 0x400>;
121 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
122 clocks = <&uart_clk>;
123 status = "disabled";
124 };
125
126 uart2: serial@11008000 {
127 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
128 reg = <0 0x11004000 0 0x400>;
129 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
130 clocks = <&uart_clk>;
131 status = "disabled";
132 };
133
134 uart3: serial@11009000 {
135 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
136 reg = <0 0x11005000 0 0x400>;
137 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
138 clocks = <&uart_clk>;
139 status = "disabled";
140 };
93 }; 141 };
94}; 142};
diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts b/arch/arm/boot/dts/mt8135-evbp1.dts
index a5adf9742308..36677382bdd8 100644
--- a/arch/arm/boot/dts/mt8135-evbp1.dts
+++ b/arch/arm/boot/dts/mt8135-evbp1.dts
@@ -23,3 +23,7 @@
23 reg = <0 0x80000000 0 0x40000000>; 23 reg = <0 0x80000000 0 0x40000000>;
24 }; 24 };
25}; 25};
26
27&uart3 {
28 status = "okay";
29};
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 7d56a986358e..a161e99ffcc4 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -18,7 +18,7 @@
18 18
19/ { 19/ {
20 compatible = "mediatek,mt8135"; 20 compatible = "mediatek,mt8135";
21 interrupt-parent = <&gic>; 21 interrupt-parent = <&sysirq>;
22 22
23 cpu-map { 23 cpu-map {
24 cluster0 { 24 cluster0 {
@@ -86,6 +86,13 @@
86 clock-frequency = <32000>; 86 clock-frequency = <32000>;
87 #clock-cells = <0>; 87 #clock-cells = <0>;
88 }; 88 };
89
90 uart_clk: dummy26m {
91 compatible = "fixed-clock";
92 clock-frequency = <26000000>;
93 #clock-cells = <0>;
94 };
95
89 }; 96 };
90 97
91 soc { 98 soc {
@@ -98,19 +105,62 @@
98 compatible = "mediatek,mt8135-timer", 105 compatible = "mediatek,mt8135-timer",
99 "mediatek,mt6577-timer"; 106 "mediatek,mt6577-timer";
100 reg = <0 0x10008000 0 0x80>; 107 reg = <0 0x10008000 0 0x80>;
101 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 108 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
102 clocks = <&system_clk>, <&rtc_clk>; 109 clocks = <&system_clk>, <&rtc_clk>;
103 clock-names = "system-clk", "rtc-clk"; 110 clock-names = "system-clk", "rtc-clk";
104 }; 111 };
105 112
113 sysirq: interrupt-controller@10200030 {
114 compatible = "mediatek,mt8135-sysirq",
115 "mediatek,mt6577-sysirq";
116 interrupt-controller;
117 #interrupt-cells = <3>;
118 interrupt-parent = <&gic>;
119 reg = <0 0x10200030 0 0x1c>;
120 };
121
106 gic: interrupt-controller@10211000 { 122 gic: interrupt-controller@10211000 {
107 compatible = "arm,cortex-a15-gic"; 123 compatible = "arm,cortex-a15-gic";
108 interrupt-controller; 124 interrupt-controller;
109 #interrupt-cells = <3>; 125 #interrupt-cells = <3>;
126 interrupt-parent = <&gic>;
110 reg = <0 0x10211000 0 0x1000>, 127 reg = <0 0x10211000 0 0x1000>,
111 <0 0x10212000 0 0x1000>, 128 <0 0x10212000 0 0x1000>,
112 <0 0x10214000 0 0x2000>, 129 <0 0x10214000 0 0x2000>,
113 <0 0x10216000 0 0x2000>; 130 <0 0x10216000 0 0x2000>;
114 }; 131 };
132
133 uart0: serial@11006000 {
134 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
135 reg = <0 0x11006000 0 0x400>;
136 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
137 clocks = <&uart_clk>;
138 status = "disabled";
139 };
140
141 uart1: serial@11007000 {
142 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
143 reg = <0 0x11007000 0 0x400>;
144 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
145 clocks = <&uart_clk>;
146 status = "disabled";
147 };
148
149 uart2: serial@11008000 {
150 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
151 reg = <0 0x11008000 0 0x400>;
152 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
153 clocks = <&uart_clk>;
154 status = "disabled";
155 };
156
157 uart3: serial@11009000 {
158 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
159 reg = <0 0x11009000 0 0x400>;
160 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
161 clocks = <&uart_clk>;
162 status = "disabled";
163 };
164
115 }; 165 };
116}; 166};
diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
index 6ea6d460db30..4d091ca43e25 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
@@ -259,3 +259,61 @@
259 pinctrl-names = "default"; 259 pinctrl-names = "default";
260 pinctrl-0 = <&mcbsp2_pins>; 260 pinctrl-0 = <&mcbsp2_pins>;
261}; 261};
262
263&gpmc {
264 ranges = <0 0 0x00000000 0x01000000>;
265
266 nand@0,0 {
267 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
268 nand-bus-width = <8>;
269 gpmc,device-width = <1>;
270 ti,nand-ecc-opt = "sw";
271
272 gpmc,cs-on-ns = <0>;
273 gpmc,cs-rd-off-ns = <120>;
274 gpmc,cs-wr-off-ns = <120>;
275
276 gpmc,adv-on-ns = <0>;
277 gpmc,adv-rd-off-ns = <120>;
278 gpmc,adv-wr-off-ns = <120>;
279
280 gpmc,we-on-ns = <6>;
281 gpmc,we-off-ns = <90>;
282
283 gpmc,oe-on-ns = <6>;
284 gpmc,oe-off-ns = <90>;
285
286 gpmc,page-burst-access-ns = <6>;
287 gpmc,access-ns = <72>;
288 gpmc,cycle2cycle-delay-ns = <60>;
289
290 gpmc,rd-cycle-ns = <120>;
291 gpmc,wr-cycle-ns = <120>;
292 gpmc,wr-access-ns = <186>;
293 gpmc,wr-data-mux-bus-ns = <90>;
294
295 #address-cells = <1>;
296 #size-cells = <1>;
297
298 partition@0 {
299 label = "xloader";
300 reg = <0 0x80000>;
301 };
302 partition@0x80000 {
303 label = "uboot";
304 reg = <0x80000 0x1e0000>;
305 };
306 partition@0x260000 {
307 label = "uboot environment";
308 reg = <0x260000 0x40000>;
309 };
310 partition@0x2a0000 {
311 label = "linux";
312 reg = <0x2a0000 0x400000>;
313 };
314 partition@0x6a0000 {
315 label = "rootfs";
316 reg = <0x6a0000 0x1f880000>;
317 };
318 };
319};
diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
index 9a4a3ab9af78..d9e92b654f85 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
@@ -50,7 +50,8 @@
50#include "omap-gpmc-smsc911x.dtsi" 50#include "omap-gpmc-smsc911x.dtsi"
51 51
52&gpmc { 52&gpmc {
53 ranges = <5 0 0x2c000000 0x01000000>; 53 ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */
54 <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
54 55
55 smsc1: ethernet@gpmc { 56 smsc1: ethernet@gpmc {
56 compatible = "smsc,lan9221", "smsc,lan9115"; 57 compatible = "smsc,lan9221", "smsc,lan9115";
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index 655d6e920a86..ee62d00bcbe6 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -83,6 +83,41 @@
83 compatible = "usb-nop-xceiv"; 83 compatible = "usb-nop-xceiv";
84 reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; 84 reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
85 }; 85 };
86
87 tv0: connector@1 {
88 compatible = "svideo-connector";
89 label = "tv";
90
91 port {
92 tv_connector_in: endpoint {
93 remote-endpoint = <&opa_out>;
94 };
95 };
96 };
97
98 tv_amp: opa362 {
99 compatible = "ti,opa362";
100 enable-gpios = <&gpio1 23 0>;
101
102 ports {
103 #address-cells = <1>;
104 #size-cells = <0>;
105
106 port@0 {
107 reg = <0>;
108 opa_in: endpoint@0 {
109 remote-endpoint = <&venc_out>;
110 };
111 };
112
113 port@1 {
114 reg = <1>;
115 opa_out: endpoint@0 {
116 remote-endpoint = <&tv_connector_in>;
117 };
118 };
119 };
120 };
86}; 121};
87 122
88&omap3_pmx_core { 123&omap3_pmx_core {
@@ -396,6 +431,20 @@
396 }; 431 };
397}; 432};
398 433
434&venc {
435 status = "okay";
436
437 vdda-supply = <&vdac>;
438
439 port {
440 venc_out: endpoint {
441 remote-endpoint = <&opa_in>;
442 ti,channels = <2>;
443 ti,invert-polarity;
444 };
445 };
446};
447
399&gpmc { 448&gpmc {
400 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ 449 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
401 450
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 53f3ca064140..abf1daf84926 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -307,7 +307,7 @@
307 regulator-name = "V28"; 307 regulator-name = "V28";
308 regulator-min-microvolt = <2800000>; 308 regulator-min-microvolt = <2800000>;
309 regulator-max-microvolt = <2800000>; 309 regulator-max-microvolt = <2800000>;
310 regulator-always-on; /* due battery cover sensor */ 310 regulator-always-on; /* due to battery cover sensor */
311}; 311};
312 312
313&vaux2 { 313&vaux2 {
@@ -365,7 +365,6 @@
365 regulator-name = "VIO"; 365 regulator-name = "VIO";
366 regulator-min-microvolt = <1800000>; 366 regulator-min-microvolt = <1800000>;
367 regulator-max-microvolt = <1800000>; 367 regulator-max-microvolt = <1800000>;
368
369}; 368};
370 369
371&vintana1 { 370&vintana1 {
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index 1e49dfe7e212..c41db94ee9c2 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -60,6 +60,11 @@
60 60
61&twl { 61&twl {
62 compatible = "ti,twl5031"; 62 compatible = "ti,twl5031";
63
64 twl_power: power {
65 compatible = "ti,twl4030-power";
66 ti,use_poweroff;
67 };
63}; 68};
64 69
65&twl_gpio { 70&twl_gpio {
diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/omap3-sbc-t3517.dts
index 17986536c61f..c2d5c28a1a70 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3517.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3517.dts
@@ -69,3 +69,7 @@
69 }; 69 };
70}; 70};
71 71
72&gpmc {
73 ranges = <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */
74 <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
75};
diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/omap3-sbc-t3530.dts
index c994f0f7e38a..834bc786cd12 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3530.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3530.dts
@@ -26,14 +26,10 @@
26 }; 26 };
27}; 27};
28 28
29/*
30 * The following ranges correspond to SMSC9x eth chips on CM-T3530 CoM and
31 * SB-T35 baseboard respectively.
32 * This setting includes both chips in SBC-T3530 board device tree.
33 */
34&gpmc { 29&gpmc {
35 ranges = <5 0 0x2c000000 0x01000000>, 30 ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */
36 <4 0 0x2d000000 0x01000000>; 31 <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */
32 <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
37}; 33};
38 34
39&mmc1 { 35&mmc1 {
diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts
index 5bdddf29341d..73c7bf4a4a08 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3730.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts
@@ -27,8 +27,9 @@
27}; 27};
28 28
29&gpmc { 29&gpmc {
30 ranges = <5 0 0x2c000000 0x01000000>, 30 ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */
31 <4 0 0x2d000000 0x01000000>; 31 <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */
32 <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
32}; 33};
33 34
34&dss { 35&dss {
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index b396c8311b27..e641001ca2a7 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -1,4 +1,5 @@
1#include "qcom-apq8064-v2.0.dtsi" 1#include "qcom-apq8064-v2.0.dtsi"
2#include <dt-bindings/gpio/gpio.h>
2 3
3/ { 4/ {
4 model = "Qualcomm APQ8064/IFC6410"; 5 model = "Qualcomm APQ8064/IFC6410";
@@ -12,6 +13,14 @@
12 function = "gsbi1"; 13 function = "gsbi1";
13 }; 14 };
14 }; 15 };
16
17 card_detect: card_detect {
18 mux {
19 pins = "gpio26";
20 function = "gpio";
21 bias-disable;
22 };
23 };
15 }; 24 };
16 25
17 gsbi@12440000 { 26 gsbi@12440000 {
@@ -49,6 +58,9 @@
49 /* External micro SD card */ 58 /* External micro SD card */
50 sdcc3: sdcc@12180000 { 59 sdcc3: sdcc@12180000 {
51 status = "okay"; 60 status = "okay";
61 pinctrl-names = "default";
62 pinctrl-0 = <&card_detect>;
63 cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
52 }; 64 };
53 /* WLAN */ 65 /* WLAN */
54 sdcc4: sdcc@121c0000 { 66 sdcc4: sdcc@121c0000 {
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 63b2146f563b..cb225dafe97c 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -74,7 +74,7 @@
74 #gpio-cells = <2>; 74 #gpio-cells = <2>;
75 interrupt-controller; 75 interrupt-controller;
76 #interrupt-cells = <2>; 76 #interrupt-cells = <2>;
77 interrupts = <0 32 0x4>; 77 interrupts = <0 16 0x4>;
78 }; 78 };
79 79
80 intc: interrupt-controller@2000000 { 80 intc: interrupt-controller@2000000 {
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 1518c5bcca33..a9da7a89fc4b 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -45,7 +45,7 @@
45}; 45};
46 46
47&mtu2 { 47&mtu2 {
48 status = "ok"; 48 status = "okay";
49}; 49};
50 50
51&i2c2 { 51&i2c2 {
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
index 84e05f713c54..b3d8f844b57a 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
@@ -67,7 +67,7 @@
67 compatible = "simple-bus"; 67 compatible = "simple-bus";
68 #address-cells = <1>; 68 #address-cells = <1>;
69 #size-cells = <1>; 69 #size-cells = <1>;
70 ranges = <0 0 0 0x80000000>; 70 ranges = <0 0 0 0x20000000>;
71 }; 71 };
72}; 72};
73 73
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index ce085fa444a1..0d50bef01234 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -10,14 +10,20 @@
10 10
11/dts-v1/; 11/dts-v1/;
12#include "r8a73a4.dtsi" 12#include "r8a73a4.dtsi"
13#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
14 15
15/ { 16/ {
16 model = "APE6EVM"; 17 model = "APE6EVM";
17 compatible = "renesas,ape6evm", "renesas,r8a73a4"; 18 compatible = "renesas,ape6evm", "renesas,r8a73a4";
18 19
20 aliases {
21 serial0 = &scifa0;
22 };
23
19 chosen { 24 chosen {
20 bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; 25 bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
26 stdout-path = &scifa0;
21 }; 27 };
22 28
23 memory@40000000 { 29 memory@40000000 {
@@ -30,7 +36,35 @@
30 reg = <2 0x00000000 0 0x40000000>; 36 reg = <2 0x00000000 0 0x40000000>;
31 }; 37 };
32 38
33 ape6evm_fixed_3v3: fixedregulator@0 { 39 vcc_mmc0: regulator@0 {
40 compatible = "regulator-fixed";
41 regulator-name = "MMC0 Vcc";
42 regulator-min-microvolt = <2800000>;
43 regulator-max-microvolt = <2800000>;
44 regulator-always-on;
45 };
46
47 vcc_sdhi0: regulator@1 {
48 compatible = "regulator-fixed";
49
50 regulator-name = "SDHI0 Vcc";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53
54 gpio = <&pfc 76 GPIO_ACTIVE_HIGH>;
55 enable-active-high;
56 };
57
58 /* Common 1.8V and 3.3V rails, used by several devices on APE6EVM */
59 ape6evm_fixed_1v8: regulator@2 {
60 compatible = "regulator-fixed";
61 regulator-name = "1V8";
62 regulator-min-microvolt = <1800000>;
63 regulator-max-microvolt = <1800000>;
64 regulator-always-on;
65 };
66
67 ape6evm_fixed_3v3: regulator@3 {
34 compatible = "regulator-fixed"; 68 compatible = "regulator-fixed";
35 regulator-name = "3V3"; 69 regulator-name = "3V3";
36 regulator-min-microvolt = <3300000>; 70 regulator-min-microvolt = <3300000>;
@@ -39,11 +73,13 @@
39 }; 73 };
40 74
41 lbsc { 75 lbsc {
76 compatible = "simple-bus";
42 #address-cells = <1>; 77 #address-cells = <1>;
43 #size-cells = <1>; 78 #size-cells = <1>;
79 ranges = <0 0 0 0x20000000>;
44 80
45 ethernet@8000000 { 81 ethernet@8000000 {
46 compatible = "smsc,lan9118", "smsc,lan9115"; 82 compatible = "smsc,lan9220", "smsc,lan9115";
47 reg = <0x08000000 0x1000>; 83 reg = <0x08000000 0x1000>;
48 interrupt-parent = <&irqc1>; 84 interrupt-parent = <&irqc1>;
49 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 85 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
@@ -52,7 +88,75 @@
52 smsc,irq-active-high; 88 smsc,irq-active-high;
53 smsc,irq-push-pull; 89 smsc,irq-push-pull;
54 vdd33a-supply = <&ape6evm_fixed_3v3>; 90 vdd33a-supply = <&ape6evm_fixed_3v3>;
55 vddvario-supply = <&ape6evm_fixed_3v3>; 91 vddvario-supply = <&ape6evm_fixed_1v8>;
92 };
93 };
94
95 leds {
96 compatible = "gpio-leds";
97 led1 {
98 gpios = <&pfc 28 GPIO_ACTIVE_LOW>;
99 label = "GNSS_EN";
100 };
101 led2 {
102 gpios = <&pfc 126 GPIO_ACTIVE_LOW>;
103 label = "NFC_NRST";
104 };
105 led3 {
106 gpios = <&pfc 132 GPIO_ACTIVE_LOW>;
107 label = "GNSS_NRST";
108 };
109 led4 {
110 gpios = <&pfc 232 GPIO_ACTIVE_LOW>;
111 label = "BT_WAKEUP";
112 };
113 led5 {
114 gpios = <&pfc 250 GPIO_ACTIVE_LOW>;
115 label = "STROBE";
116 };
117 led6 {
118 gpios = <&pfc 288 GPIO_ACTIVE_LOW>;
119 label = "BBRESETOUT";
120 };
121 };
122
123 keyboard {
124 compatible = "gpio-keys";
125
126 zero-key {
127 gpios = <&pfc 324 GPIO_ACTIVE_LOW>;
128 linux,code = <KEY_0>;
129 label = "S16";
130 };
131
132 menu-key {
133 gpios = <&pfc 325 GPIO_ACTIVE_LOW>;
134 linux,code = <KEY_MENU>;
135 label = "S17";
136 };
137
138 home-key {
139 gpios = <&pfc 326 GPIO_ACTIVE_LOW>;
140 linux,code = <KEY_HOME>;
141 label = "S18";
142 };
143
144 back-key {
145 gpios = <&pfc 327 GPIO_ACTIVE_LOW>;
146 linux,code = <KEY_BACK>;
147 label = "S19";
148 };
149
150 volup-key {
151 gpios = <&pfc 328 GPIO_ACTIVE_LOW>;
152 linux,code = <KEY_VOLUMEUP>;
153 label = "S20";
154 };
155
156 voldown-key {
157 gpios = <&pfc 329 GPIO_ACTIVE_LOW>;
158 linux,code = <KEY_VOLUMEDOWN>;
159 label = "S21";
56 }; 160 };
57 }; 161 };
58}; 162};
@@ -79,3 +183,64 @@
79 >; 183 >;
80 voltage-tolerance = <1>; /* 1% */ 184 voltage-tolerance = <1>; /* 1% */
81}; 185};
186
187&cmt1 {
188 status = "okay";
189};
190
191&pfc {
192 scifa0_pins: serial0 {
193 renesas,groups = "scifa0_data";
194 renesas,function = "scifa0";
195 };
196
197 mmc0_pins: mmc {
198 renesas,groups = "mmc0_data8", "mmc0_ctrl";
199 renesas,function = "mmc0";
200 };
201
202 sdhi0_pins: sd0 {
203 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
204 renesas,function = "sdhi0";
205 };
206
207 sdhi1_pins: sd1 {
208 renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
209 renesas,function = "sdhi1";
210 };
211};
212
213&mmcif0 {
214 vmmc-supply = <&vcc_mmc0>;
215 bus-width = <8>;
216 non-removable;
217 pinctrl-names = "default";
218 pinctrl-0 = <&mmc0_pins>;
219 status = "okay";
220};
221
222&scifa0 {
223 pinctrl-0 = <&scifa0_pins>;
224 pinctrl-names = "default";
225
226 status = "okay";
227};
228
229&sdhi0 {
230 vmmc-supply = <&vcc_sdhi0>;
231 bus-width = <4>;
232 toshiba,mmc-wrprotect-disable;
233 pinctrl-names = "default";
234 pinctrl-0 = <&sdhi0_pins>;
235 status = "okay";
236};
237
238&sdhi1 {
239 vmmc-supply = <&ape6evm_fixed_3v3>;
240 bus-width = <4>;
241 broken-cd;
242 toshiba,mmc-wrprotect-disable;
243 pinctrl-names = "default";
244 pinctrl-0 = <&sdhi1_pins>;
245 status = "okay";
246};
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 5ac57babc3b9..38136d9f6d95 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -38,6 +38,16 @@
38 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 38 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
39 }; 39 };
40 40
41 dbsc1: memory-controller@e6790000 {
42 compatible = "renesas,dbsc-r8a73a4";
43 reg = <0 0xe6790000 0 0x10000>;
44 };
45
46 dbsc2: memory-controller@e67a0000 {
47 compatible = "renesas,dbsc-r8a73a4";
48 reg = <0 0xe67a0000 0 0x10000>;
49 };
50
41 dmac: dma-multiplexer { 51 dmac: dma-multiplexer {
42 compatible = "renesas,shdma-mux"; 52 compatible = "renesas,shdma-mux";
43 #dma-cells = <1>; 53 #dma-cells = <1>;
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index d4af4d86c6b0..9bd0cb439f44 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -172,7 +172,7 @@
172 pinctrl-names = "default"; 172 pinctrl-names = "default";
173 173
174 phy-handle = <&phy0>; 174 phy-handle = <&phy0>;
175 status = "ok"; 175 status = "okay";
176 176
177 phy0: ethernet-phy@0 { 177 phy0: ethernet-phy@0 {
178 reg = <0>; 178 reg = <0>;
@@ -193,7 +193,7 @@
193}; 193};
194 194
195&cmt1 { 195&cmt1 {
196 status = "ok"; 196 status = "okay";
197}; 197};
198 198
199&i2c0 { 199&i2c0 {
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index a8a674bafa67..8a092605d641 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -25,6 +25,7 @@
25 device_type = "cpu"; 25 device_type = "cpu";
26 reg = <0x0>; 26 reg = <0x0>;
27 clock-frequency = <800000000>; 27 clock-frequency = <800000000>;
28 power-domains = <&pd_a3sm>;
28 }; 29 };
29 }; 30 };
30 31
@@ -36,17 +37,29 @@
36 <0xc2000000 0x1000>; 37 <0xc2000000 0x1000>;
37 }; 38 };
38 39
40 dbsc3: memory-controller@fe400000 {
41 compatible = "renesas,dbsc3-r8a7740";
42 reg = <0xfe400000 0x400>;
43 power-domains = <&pd_a4s>;
44 };
45
39 pmu { 46 pmu {
40 compatible = "arm,cortex-a9-pmu"; 47 compatible = "arm,cortex-a9-pmu";
41 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 48 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
42 }; 49 };
43 50
51 ptm {
52 compatible = "arm,coresight-etm3x";
53 power-domains = <&pd_d4>;
54 };
55
44 cmt1: timer@e6138000 { 56 cmt1: timer@e6138000 {
45 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; 57 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
46 reg = <0xe6138000 0x170>; 58 reg = <0xe6138000 0x170>;
47 interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; 59 interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
48 clocks = <&mstp3_clks R8A7740_CLK_CMT1>; 60 clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
49 clock-names = "fck"; 61 clock-names = "fck";
62 power-domains = <&pd_c5>;
50 63
51 renesas,channels-mask = <0x3f>; 64 renesas,channels-mask = <0x3f>;
52 65
@@ -72,6 +85,7 @@
72 0 149 IRQ_TYPE_LEVEL_HIGH 85 0 149 IRQ_TYPE_LEVEL_HIGH
73 0 149 IRQ_TYPE_LEVEL_HIGH>; 86 0 149 IRQ_TYPE_LEVEL_HIGH>;
74 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 87 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
88 power-domains = <&pd_a4s>;
75 }; 89 };
76 90
77 /* irqpin1: IRQ8 - IRQ15 */ 91 /* irqpin1: IRQ8 - IRQ15 */
@@ -93,6 +107,7 @@
93 0 149 IRQ_TYPE_LEVEL_HIGH 107 0 149 IRQ_TYPE_LEVEL_HIGH
94 0 149 IRQ_TYPE_LEVEL_HIGH>; 108 0 149 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 109 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
110 power-domains = <&pd_a4s>;
96 }; 111 };
97 112
98 /* irqpin2: IRQ16 - IRQ23 */ 113 /* irqpin2: IRQ16 - IRQ23 */
@@ -114,6 +129,7 @@
114 0 149 IRQ_TYPE_LEVEL_HIGH 129 0 149 IRQ_TYPE_LEVEL_HIGH
115 0 149 IRQ_TYPE_LEVEL_HIGH>; 130 0 149 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 131 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
132 power-domains = <&pd_a4s>;
117 }; 133 };
118 134
119 /* irqpin3: IRQ24 - IRQ31 */ 135 /* irqpin3: IRQ24 - IRQ31 */
@@ -135,6 +151,7 @@
135 0 149 IRQ_TYPE_LEVEL_HIGH 151 0 149 IRQ_TYPE_LEVEL_HIGH
136 0 149 IRQ_TYPE_LEVEL_HIGH>; 152 0 149 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 153 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
154 power-domains = <&pd_a4s>;
138 }; 155 };
139 156
140 ether: ethernet@e9a00000 { 157 ether: ethernet@e9a00000 {
@@ -143,6 +160,7 @@
143 <0xe9a01800 0x800>; 160 <0xe9a01800 0x800>;
144 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 161 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&mstp3_clks R8A7740_CLK_GETHER>; 162 clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
163 power-domains = <&pd_a4s>;
146 phy-mode = "mii"; 164 phy-mode = "mii";
147 #address-cells = <1>; 165 #address-cells = <1>;
148 #size-cells = <0>; 166 #size-cells = <0>;
@@ -159,6 +177,7 @@
159 0 203 IRQ_TYPE_LEVEL_HIGH 177 0 203 IRQ_TYPE_LEVEL_HIGH
160 0 204 IRQ_TYPE_LEVEL_HIGH>; 178 0 204 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&mstp1_clks R8A7740_CLK_IIC0>; 179 clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
180 power-domains = <&pd_a4r>;
162 status = "disabled"; 181 status = "disabled";
163 }; 182 };
164 183
@@ -172,6 +191,7 @@
172 0 72 IRQ_TYPE_LEVEL_HIGH 191 0 72 IRQ_TYPE_LEVEL_HIGH
173 0 73 IRQ_TYPE_LEVEL_HIGH>; 192 0 73 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&mstp3_clks R8A7740_CLK_IIC1>; 193 clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
194 power-domains = <&pd_a3sp>;
175 status = "disabled"; 195 status = "disabled";
176 }; 196 };
177 197
@@ -181,6 +201,7 @@
181 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 201 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; 202 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
183 clock-names = "sci_ick"; 203 clock-names = "sci_ick";
204 power-domains = <&pd_a3sp>;
184 status = "disabled"; 205 status = "disabled";
185 }; 206 };
186 207
@@ -190,6 +211,7 @@
190 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; 211 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; 212 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
192 clock-names = "sci_ick"; 213 clock-names = "sci_ick";
214 power-domains = <&pd_a3sp>;
193 status = "disabled"; 215 status = "disabled";
194 }; 216 };
195 217
@@ -199,6 +221,7 @@
199 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; 221 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; 222 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
201 clock-names = "sci_ick"; 223 clock-names = "sci_ick";
224 power-domains = <&pd_a3sp>;
202 status = "disabled"; 225 status = "disabled";
203 }; 226 };
204 227
@@ -208,6 +231,7 @@
208 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; 231 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; 232 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
210 clock-names = "sci_ick"; 233 clock-names = "sci_ick";
234 power-domains = <&pd_a3sp>;
211 status = "disabled"; 235 status = "disabled";
212 }; 236 };
213 237
@@ -217,6 +241,7 @@
217 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; 241 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; 242 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
219 clock-names = "sci_ick"; 243 clock-names = "sci_ick";
244 power-domains = <&pd_a3sp>;
220 status = "disabled"; 245 status = "disabled";
221 }; 246 };
222 247
@@ -226,6 +251,7 @@
226 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 251 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; 252 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
228 clock-names = "sci_ick"; 253 clock-names = "sci_ick";
254 power-domains = <&pd_a3sp>;
229 status = "disabled"; 255 status = "disabled";
230 }; 256 };
231 257
@@ -235,6 +261,7 @@
235 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 261 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; 262 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
237 clock-names = "sci_ick"; 263 clock-names = "sci_ick";
264 power-domains = <&pd_a3sp>;
238 status = "disabled"; 265 status = "disabled";
239 }; 266 };
240 267
@@ -244,6 +271,7 @@
244 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 271 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; 272 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
246 clock-names = "sci_ick"; 273 clock-names = "sci_ick";
274 power-domains = <&pd_a3sp>;
247 status = "disabled"; 275 status = "disabled";
248 }; 276 };
249 277
@@ -253,6 +281,7 @@
253 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 281 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; 282 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
255 clock-names = "sci_ick"; 283 clock-names = "sci_ick";
284 power-domains = <&pd_a3sp>;
256 status = "disabled"; 285 status = "disabled";
257 }; 286 };
258 287
@@ -271,12 +300,14 @@
271 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, 300 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
272 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, 301 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
273 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; 302 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
303 power-domains = <&pd_c5>;
274 }; 304 };
275 305
276 tpu: pwm@e6600000 { 306 tpu: pwm@e6600000 {
277 compatible = "renesas,tpu-r8a7740", "renesas,tpu"; 307 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
278 reg = <0xe6600000 0x100>; 308 reg = <0xe6600000 0x100>;
279 clocks = <&mstp3_clks R8A7740_CLK_TPU0>; 309 clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
310 power-domains = <&pd_a3sp>;
280 status = "disabled"; 311 status = "disabled";
281 #pwm-cells = <3>; 312 #pwm-cells = <3>;
282 }; 313 };
@@ -287,6 +318,7 @@
287 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH 318 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
288 0 57 IRQ_TYPE_LEVEL_HIGH>; 319 0 57 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&mstp3_clks R8A7740_CLK_MMC>; 320 clocks = <&mstp3_clks R8A7740_CLK_MMC>;
321 power-domains = <&pd_a3sp>;
290 status = "disabled"; 322 status = "disabled";
291 }; 323 };
292 324
@@ -297,6 +329,7 @@
297 0 118 IRQ_TYPE_LEVEL_HIGH 329 0 118 IRQ_TYPE_LEVEL_HIGH
298 0 119 IRQ_TYPE_LEVEL_HIGH>; 330 0 119 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; 331 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
332 power-domains = <&pd_a3sp>;
300 cap-sd-highspeed; 333 cap-sd-highspeed;
301 cap-sdio-irq; 334 cap-sdio-irq;
302 status = "disabled"; 335 status = "disabled";
@@ -309,6 +342,7 @@
309 0 122 IRQ_TYPE_LEVEL_HIGH 342 0 122 IRQ_TYPE_LEVEL_HIGH
310 0 123 IRQ_TYPE_LEVEL_HIGH>; 343 0 123 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; 344 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
345 power-domains = <&pd_a3sp>;
312 cap-sd-highspeed; 346 cap-sd-highspeed;
313 cap-sdio-irq; 347 cap-sdio-irq;
314 status = "disabled"; 348 status = "disabled";
@@ -321,6 +355,7 @@
321 0 126 IRQ_TYPE_LEVEL_HIGH 355 0 126 IRQ_TYPE_LEVEL_HIGH
322 0 127 IRQ_TYPE_LEVEL_HIGH>; 356 0 127 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; 357 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
358 power-domains = <&pd_a3sp>;
324 cap-sd-highspeed; 359 cap-sd-highspeed;
325 cap-sdio-irq; 360 cap-sdio-irq;
326 status = "disabled"; 361 status = "disabled";
@@ -332,6 +367,7 @@
332 reg = <0xfe1f0000 0x400>; 367 reg = <0xfe1f0000 0x400>;
333 interrupts = <0 9 0x4>; 368 interrupts = <0 9 0x4>;
334 clocks = <&mstp3_clks R8A7740_CLK_FSI>; 369 clocks = <&mstp3_clks R8A7740_CLK_FSI>;
370 power-domains = <&pd_a4mp>;
335 status = "disabled"; 371 status = "disabled";
336 }; 372 };
337 373
@@ -343,6 +379,7 @@
343 <0 200 IRQ_TYPE_LEVEL_HIGH>; 379 <0 200 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&mstp1_clks R8A7740_CLK_TMU0>; 380 clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
345 clock-names = "fck"; 381 clock-names = "fck";
382 power-domains = <&pd_a4r>;
346 383
347 #renesas,channels = <3>; 384 #renesas,channels = <3>;
348 385
@@ -357,6 +394,7 @@
357 <0 172 IRQ_TYPE_LEVEL_HIGH>; 394 <0 172 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&mstp1_clks R8A7740_CLK_TMU1>; 395 clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
359 clock-names = "fck"; 396 clock-names = "fck";
397 power-domains = <&pd_a4r>;
360 398
361 #renesas,channels = <3>; 399 #renesas,channels = <3>;
362 400
@@ -453,7 +491,7 @@
453 reg = <0xe6150080 4>; 491 reg = <0xe6150080 4>;
454 clocks = <&sub_clk>, <&sub_clk>; 492 clocks = <&sub_clk>, <&sub_clk>;
455 #clock-cells = <1>; 493 #clock-cells = <1>;
456 renesas,clock-indices = < 494 clock-indices = <
457 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2 495 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
458 >; 496 >;
459 clock-output-names = 497 clock-output-names =
@@ -468,7 +506,7 @@
468 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>, 506 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
469 <&cpg_clocks R8A7740_CLK_B>; 507 <&cpg_clocks R8A7740_CLK_B>;
470 #clock-cells = <1>; 508 #clock-cells = <1>;
471 renesas,clock-indices = < 509 clock-indices = <
472 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0 510 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
473 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1 511 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
474 R8A7740_CLK_LCDC0 512 R8A7740_CLK_LCDC0
@@ -489,7 +527,7 @@
489 <&sub_clk>, <&sub_clk>, <&sub_clk>, 527 <&sub_clk>, <&sub_clk>, <&sub_clk>,
490 <&sub_clk>; 528 <&sub_clk>;
491 #clock-cells = <1>; 529 #clock-cells = <1>;
492 renesas,clock-indices = < 530 clock-indices = <
493 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA 531 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
494 R8A7740_CLK_SCIFA7 532 R8A7740_CLK_SCIFA7
495 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 533 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
@@ -518,7 +556,7 @@
518 <&cpg_clocks R8A7740_CLK_HP>, 556 <&cpg_clocks R8A7740_CLK_HP>,
519 <&cpg_clocks R8A7740_CLK_HP>; 557 <&cpg_clocks R8A7740_CLK_HP>;
520 #clock-cells = <1>; 558 #clock-cells = <1>;
521 renesas,clock-indices = < 559 clock-indices = <
522 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1 560 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
523 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1 561 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
524 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0 562 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
@@ -535,7 +573,7 @@
535 <&cpg_clocks R8A7740_CLK_HP>, 573 <&cpg_clocks R8A7740_CLK_HP>,
536 <&cpg_clocks R8A7740_CLK_HP>; 574 <&cpg_clocks R8A7740_CLK_HP>;
537 #clock-cells = <1>; 575 #clock-cells = <1>;
538 renesas,clock-indices = < 576 clock-indices = <
539 R8A7740_CLK_USBH R8A7740_CLK_SDHI2 577 R8A7740_CLK_USBH R8A7740_CLK_SDHI2
540 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY 578 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
541 >; 579 >;
@@ -543,4 +581,71 @@
543 "usbhost", "sdhi2", "usbfunc", "usphy"; 581 "usbhost", "sdhi2", "usbfunc", "usphy";
544 }; 582 };
545 }; 583 };
584
585 sysc: system-controller@e6180000 {
586 compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
587 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
588
589 pm-domains {
590 pd_c5: c5 {
591 #address-cells = <1>;
592 #size-cells = <0>;
593 #power-domain-cells = <0>;
594
595 pd_a4lc: a4lc@1 {
596 reg = <1>;
597 #power-domain-cells = <0>;
598 };
599
600 pd_a4mp: a4mp@2 {
601 reg = <2>;
602 #power-domain-cells = <0>;
603 };
604
605 pd_d4: d4@3 {
606 reg = <3>;
607 #power-domain-cells = <0>;
608 };
609
610 pd_a4r: a4r@5 {
611 reg = <5>;
612 #address-cells = <1>;
613 #size-cells = <0>;
614 #power-domain-cells = <0>;
615
616 pd_a3rv: a3rv@6 {
617 reg = <6>;
618 #power-domain-cells = <0>;
619 };
620 };
621
622 pd_a4s: a4s@10 {
623 reg = <10>;
624 #address-cells = <1>;
625 #size-cells = <0>;
626 #power-domain-cells = <0>;
627
628 pd_a3sp: a3sp@11 {
629 reg = <11>;
630 #power-domain-cells = <0>;
631 };
632
633 pd_a3sm: a3sm@12 {
634 reg = <12>;
635 #power-domain-cells = <0>;
636 };
637
638 pd_a3sg: a3sg@13 {
639 reg = <13>;
640 #power-domain-cells = <0>;
641 };
642 };
643
644 pd_a4su: a4su@20 {
645 reg = <20>;
646 #power-domain-cells = <0>;
647 };
648 };
649 };
650 };
546}; 651};
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index ede9a29e4bc6..5c2219b9f3eb 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -12,6 +12,7 @@
12/include/ "skeleton.dtsi" 12/include/ "skeleton.dtsi"
13 13
14#include <dt-bindings/clock/r8a7779-clock.h> 14#include <dt-bindings/clock/r8a7779-clock.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/irq.h>
16 17
17/ { 18/ {
@@ -62,6 +63,14 @@
62 <0xf0000100 0x100>; 63 <0xf0000100 0x100>;
63 }; 64 };
64 65
66 timer@f0000600 {
67 compatible = "arm,cortex-a9-twd-timer";
68 reg = <0xf0000600 0x20>;
69 interrupts = <GIC_PPI 13
70 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
71 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
72 };
73
65 gpio0: gpio@ffc40000 { 74 gpio0: gpio@ffc40000 {
66 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 75 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
67 reg = <0xffc40000 0x2c>; 76 reg = <0xffc40000 0x2c>;
@@ -200,7 +209,7 @@
200 compatible = "renesas,scif-r8a7779", "renesas,scif"; 209 compatible = "renesas,scif-r8a7779", "renesas,scif";
201 reg = <0xffe40000 0x100>; 210 reg = <0xffe40000 0x100>;
202 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 211 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&cpg_clocks R8A7779_CLK_P>; 212 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>;
204 clock-names = "sci_ick"; 213 clock-names = "sci_ick";
205 status = "disabled"; 214 status = "disabled";
206 }; 215 };
@@ -209,7 +218,7 @@
209 compatible = "renesas,scif-r8a7779", "renesas,scif"; 218 compatible = "renesas,scif-r8a7779", "renesas,scif";
210 reg = <0xffe41000 0x100>; 219 reg = <0xffe41000 0x100>;
211 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 220 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cpg_clocks R8A7779_CLK_P>; 221 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>;
213 clock-names = "sci_ick"; 222 clock-names = "sci_ick";
214 status = "disabled"; 223 status = "disabled";
215 }; 224 };
@@ -218,7 +227,7 @@
218 compatible = "renesas,scif-r8a7779", "renesas,scif"; 227 compatible = "renesas,scif-r8a7779", "renesas,scif";
219 reg = <0xffe42000 0x100>; 228 reg = <0xffe42000 0x100>;
220 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; 229 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&cpg_clocks R8A7779_CLK_P>; 230 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>;
222 clock-names = "sci_ick"; 231 clock-names = "sci_ick";
223 status = "disabled"; 232 status = "disabled";
224 }; 233 };
@@ -227,7 +236,7 @@
227 compatible = "renesas,scif-r8a7779", "renesas,scif"; 236 compatible = "renesas,scif-r8a7779", "renesas,scif";
228 reg = <0xffe43000 0x100>; 237 reg = <0xffe43000 0x100>;
229 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>; 238 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&cpg_clocks R8A7779_CLK_P>; 239 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>;
231 clock-names = "sci_ick"; 240 clock-names = "sci_ick";
232 status = "disabled"; 241 status = "disabled";
233 }; 242 };
@@ -236,7 +245,7 @@
236 compatible = "renesas,scif-r8a7779", "renesas,scif"; 245 compatible = "renesas,scif-r8a7779", "renesas,scif";
237 reg = <0xffe44000 0x100>; 246 reg = <0xffe44000 0x100>;
238 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 247 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&cpg_clocks R8A7779_CLK_P>; 248 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>;
240 clock-names = "sci_ick"; 249 clock-names = "sci_ick";
241 status = "disabled"; 250 status = "disabled";
242 }; 251 };
@@ -245,7 +254,7 @@
245 compatible = "renesas,scif-r8a7779", "renesas,scif"; 254 compatible = "renesas,scif-r8a7779", "renesas,scif";
246 reg = <0xffe45000 0x100>; 255 reg = <0xffe45000 0x100>;
247 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; 256 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cpg_clocks R8A7779_CLK_P>; 257 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>;
249 clock-names = "sci_ick"; 258 clock-names = "sci_ick";
250 status = "disabled"; 259 status = "disabled";
251 }; 260 };
@@ -464,18 +473,18 @@
464 <&cpg_clocks R8A7779_CLK_P>, 473 <&cpg_clocks R8A7779_CLK_P>,
465 <&cpg_clocks R8A7779_CLK_S>, 474 <&cpg_clocks R8A7779_CLK_S>,
466 <&cpg_clocks R8A7779_CLK_S>, 475 <&cpg_clocks R8A7779_CLK_S>,
467 <&cpg_clocks R8A7779_CLK_S1>, 476 <&cpg_clocks R8A7779_CLK_P>,
468 <&cpg_clocks R8A7779_CLK_S1>, 477 <&cpg_clocks R8A7779_CLK_P>,
469 <&cpg_clocks R8A7779_CLK_S1>, 478 <&cpg_clocks R8A7779_CLK_P>,
470 <&cpg_clocks R8A7779_CLK_S1>, 479 <&cpg_clocks R8A7779_CLK_P>,
471 <&cpg_clocks R8A7779_CLK_S1>, 480 <&cpg_clocks R8A7779_CLK_P>,
472 <&cpg_clocks R8A7779_CLK_S1>, 481 <&cpg_clocks R8A7779_CLK_P>,
473 <&cpg_clocks R8A7779_CLK_P>, 482 <&cpg_clocks R8A7779_CLK_P>,
474 <&cpg_clocks R8A7779_CLK_P>, 483 <&cpg_clocks R8A7779_CLK_P>,
475 <&cpg_clocks R8A7779_CLK_P>, 484 <&cpg_clocks R8A7779_CLK_P>,
476 <&cpg_clocks R8A7779_CLK_P>; 485 <&cpg_clocks R8A7779_CLK_P>;
477 #clock-cells = <1>; 486 #clock-cells = <1>;
478 renesas,clock-indices = < 487 clock-indices = <
479 R8A7779_CLK_HSPI R8A7779_CLK_TMU2 488 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
480 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0 489 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
481 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0 490 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
@@ -506,7 +515,7 @@
506 <&cpg_clocks R8A7779_CLK_P>, 515 <&cpg_clocks R8A7779_CLK_P>,
507 <&cpg_clocks R8A7779_CLK_S>; 516 <&cpg_clocks R8A7779_CLK_S>;
508 #clock-cells = <1>; 517 #clock-cells = <1>;
509 renesas,clock-indices = < 518 clock-indices = <
510 R8A7779_CLK_USB01 R8A7779_CLK_USB2 519 R8A7779_CLK_USB01 R8A7779_CLK_USB2
511 R8A7779_CLK_DU R8A7779_CLK_VIN2 520 R8A7779_CLK_DU R8A7779_CLK_VIN2
512 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0 521 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
@@ -527,7 +536,7 @@
527 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, 536 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
528 <&s4_clk>, <&s4_clk>; 537 <&s4_clk>, <&s4_clk>;
529 #clock-cells = <1>; 538 #clock-cells = <1>;
530 renesas,clock-indices = < 539 clock-indices = <
531 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2 540 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
532 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 541 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
533 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 542 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 636d53bb87a2..2a191b56c9f9 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -355,7 +355,7 @@
355 355
356 phy-handle = <&phy1>; 356 phy-handle = <&phy1>;
357 renesas,ether-link-active-low; 357 renesas,ether-link-active-low;
358 status = "ok"; 358 status = "okay";
359 359
360 phy1: ethernet-phy@1 { 360 phy1: ethernet-phy@1 {
361 reg = <1>; 361 reg = <1>;
@@ -366,7 +366,7 @@
366}; 366};
367 367
368&cmt0 { 368&cmt0 {
369 status = "ok"; 369 status = "okay";
370}; 370};
371 371
372&mmcif1 { 372&mmcif1 {
@@ -397,6 +397,8 @@
397 spi-max-frequency = <30000000>; 397 spi-max-frequency = <30000000>;
398 spi-tx-bus-width = <4>; 398 spi-tx-bus-width = <4>;
399 spi-rx-bus-width = <4>; 399 spi-rx-bus-width = <4>;
400 spi-cpha;
401 spi-cpol;
400 m25p,fast-read; 402 m25p,fast-read;
401 403
402 partition@0 { 404 partition@0 {
@@ -470,17 +472,17 @@
470}; 472};
471 473
472&iic0 { 474&iic0 {
473 status = "ok"; 475 status = "okay";
474}; 476};
475 477
476&iic1 { 478&iic1 {
477 status = "ok"; 479 status = "okay";
478 pinctrl-0 = <&iic1_pins>; 480 pinctrl-0 = <&iic1_pins>;
479 pinctrl-names = "default"; 481 pinctrl-names = "default";
480}; 482};
481 483
482&iic2 { 484&iic2 {
483 status = "ok"; 485 status = "okay";
484 pinctrl-0 = <&iic2_pins>; 486 pinctrl-0 = <&iic2_pins>;
485 pinctrl-names = "default"; 487 pinctrl-names = "default";
486 488
@@ -562,7 +564,7 @@
562 pinctrl-0 = <&vin1_pins>; 564 pinctrl-0 = <&vin1_pins>;
563 pinctrl-names = "default"; 565 pinctrl-names = "default";
564 566
565 status = "ok"; 567 status = "okay";
566 568
567 port { 569 port {
568 #address-cells = <1>; 570 #address-cells = <1>;
@@ -579,6 +581,7 @@
579 pinctrl-0 = <&sound_pins &sound_clk_pins>; 581 pinctrl-0 = <&sound_pins &sound_clk_pins>;
580 pinctrl-names = "default"; 582 pinctrl-names = "default";
581 583
584 /* Single DAI */
582 #sound-dai-cells = <0>; 585 #sound-dai-cells = <0>;
583 586
584 status = "okay"; 587 status = "okay";
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index af7e255f629e..4b38fc920114 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1054,7 +1054,7 @@
1054 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; 1054 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1055 clocks = <&mp_clk>; 1055 clocks = <&mp_clk>;
1056 #clock-cells = <1>; 1056 #clock-cells = <1>;
1057 renesas,clock-indices = <R8A7790_CLK_MSIOF0>; 1057 clock-indices = <R8A7790_CLK_MSIOF0>;
1058 clock-output-names = "msiof0"; 1058 clock-output-names = "msiof0";
1059 }; 1059 };
1060 mstp1_clks: mstp1_clks@e6150134 { 1060 mstp1_clks: mstp1_clks@e6150134 {
@@ -1065,7 +1065,7 @@
1065 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, 1065 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1066 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; 1066 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1067 #clock-cells = <1>; 1067 #clock-cells = <1>;
1068 renesas,clock-indices = < 1068 clock-indices = <
1069 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1 1069 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1070 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1 1070 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1071 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC 1071 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
@@ -1087,7 +1087,7 @@
1087 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, 1087 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1088 <&zs_clk>; 1088 <&zs_clk>;
1089 #clock-cells = <1>; 1089 #clock-cells = <1>;
1090 renesas,clock-indices = < 1090 clock-indices = <
1091 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 1091 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1092 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 1092 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1093 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 1093 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
@@ -1106,7 +1106,7 @@
1106 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, 1106 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1107 <&hp_clk>, <&hp_clk>; 1107 <&hp_clk>, <&hp_clk>;
1108 #clock-cells = <1>; 1108 #clock-cells = <1>;
1109 renesas,clock-indices = < 1109 clock-indices = <
1110 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 1110 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1111 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 1111 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1112 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 1112 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
@@ -1123,8 +1123,10 @@
1123 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1123 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1124 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; 1124 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
1125 #clock-cells = <1>; 1125 #clock-cells = <1>;
1126 renesas,clock-indices = <R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1 1126 clock-indices = <
1127 R8A7790_CLK_THERMAL R8A7790_CLK_PWM>; 1127 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1128 R8A7790_CLK_THERMAL R8A7790_CLK_PWM
1129 >;
1128 clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; 1130 clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
1129 }; 1131 };
1130 mstp7_clks: mstp7_clks@e615014c { 1132 mstp7_clks: mstp7_clks@e615014c {
@@ -1134,7 +1136,7 @@
1134 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, 1136 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1135 <&zx_clk>; 1137 <&zx_clk>;
1136 #clock-cells = <1>; 1138 #clock-cells = <1>;
1137 renesas,clock-indices = < 1139 clock-indices = <
1138 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 1140 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1139 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 1141 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1140 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 1142 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
@@ -1147,16 +1149,17 @@
1147 mstp8_clks: mstp8_clks@e6150990 { 1149 mstp8_clks: mstp8_clks@e6150990 {
1148 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1150 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1149 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 1151 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1150 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, 1152 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1151 <&zs_clk>, <&zs_clk>; 1153 <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
1152 #clock-cells = <1>; 1154 #clock-cells = <1>;
1153 renesas,clock-indices = < 1155 clock-indices = <
1154 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1 1156 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1155 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1 1157 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
1156 R8A7790_CLK_SATA0 1158 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1157 >; 1159 >;
1158 clock-output-names = 1160 clock-output-names =
1159 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; 1161 "mlb", "vin3", "vin2", "vin1", "vin0", "ether",
1162 "sata1", "sata0";
1160 }; 1163 };
1161 mstp9_clks: mstp9_clks@e6150994 { 1164 mstp9_clks: mstp9_clks@e6150994 {
1162 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1165 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1166,7 +1169,7 @@
1166 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, 1169 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1167 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; 1170 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1168 #clock-cells = <1>; 1171 #clock-cells = <1>;
1169 renesas,clock-indices = < 1172 clock-indices = <
1170 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 1173 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1171 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 1174 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1172 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS 1175 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
@@ -1397,8 +1400,13 @@
1397 }; 1400 };
1398 1401
1399 rcar_sound: rcar_sound@ec500000 { 1402 rcar_sound: rcar_sound@ec500000 {
1400 #sound-dai-cells = <1>; 1403 /*
1401 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; 1404 * #sound-dai-cells is required
1405 *
1406 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1407 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1408 */
1409 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1402 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1410 reg = <0 0xec500000 0 0x1000>, /* SCU */
1403 <0 0xec5a0000 0 0x100>, /* ADG */ 1411 <0 0xec5a0000 0 0x100>, /* ADG */
1404 <0 0xec540000 0 0x1000>, /* SSIU */ 1412 <0 0xec540000 0 0x1000>, /* SSIU */
@@ -1432,16 +1440,16 @@
1432 }; 1440 };
1433 1441
1434 rcar_sound,src { 1442 rcar_sound,src {
1435 src0: src@0 { }; 1443 src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };
1436 src1: src@1 { }; 1444 src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };
1437 src2: src@2 { }; 1445 src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };
1438 src3: src@3 { }; 1446 src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };
1439 src4: src@4 { }; 1447 src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };
1440 src5: src@5 { }; 1448 src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };
1441 src6: src@6 { }; 1449 src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };
1442 src7: src@7 { }; 1450 src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };
1443 src8: src@8 { }; 1451 src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };
1444 src9: src@9 { }; 1452 src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };
1445 }; 1453 };
1446 1454
1447 rcar_sound,ssi { 1455 rcar_sound,ssi {
diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts
index 740e38678032..d2ebf11f9881 100644
--- a/arch/arm/boot/dts/r8a7791-henninger.dts
+++ b/arch/arm/boot/dts/r8a7791-henninger.dts
@@ -156,7 +156,7 @@
156 156
157 phy-handle = <&phy1>; 157 phy-handle = <&phy1>;
158 renesas,ether-link-active-low; 158 renesas,ether-link-active-low;
159 status = "ok"; 159 status = "okay";
160 160
161 phy1: ethernet-phy@1 { 161 phy1: ethernet-phy@1 {
162 reg = <1>; 162 reg = <1>;
@@ -293,7 +293,7 @@
293 293
294/* composite video input */ 294/* composite video input */
295&vin0 { 295&vin0 {
296 status = "ok"; 296 status = "okay";
297 pinctrl-0 = <&vin0_pins>; 297 pinctrl-0 = <&vin0_pins>;
298 pinctrl-names = "default"; 298 pinctrl-names = "default";
299 299
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 990af167c551..96f5b5877f22 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -366,7 +366,7 @@
366 366
367 phy-handle = <&phy1>; 367 phy-handle = <&phy1>;
368 renesas,ether-link-active-low; 368 renesas,ether-link-active-low;
369 status = "ok"; 369 status = "okay";
370 370
371 phy1: ethernet-phy@1 { 371 phy1: ethernet-phy@1 {
372 reg = <1>; 372 reg = <1>;
@@ -377,7 +377,7 @@
377}; 377};
378 378
379&cmt0 { 379&cmt0 {
380 status = "ok"; 380 status = "okay";
381}; 381};
382 382
383&sata0 { 383&sata0 {
@@ -444,6 +444,8 @@
444 spi-max-frequency = <30000000>; 444 spi-max-frequency = <30000000>;
445 spi-tx-bus-width = <4>; 445 spi-tx-bus-width = <4>;
446 spi-rx-bus-width = <4>; 446 spi-rx-bus-width = <4>;
447 spi-cpha;
448 spi-cpol;
447 m25p,fast-read; 449 m25p,fast-read;
448 450
449 partition@0 { 451 partition@0 {
@@ -452,13 +454,13 @@
452 read-only; 454 read-only;
453 }; 455 };
454 partition@80000 { 456 partition@80000 {
455 label = "bootenv"; 457 label = "user";
456 reg = <0x00080000 0x00080000>; 458 reg = <0x00080000 0x00580000>;
457 read-only; 459 read-only;
458 }; 460 };
459 partition@100000 { 461 partition@600000 {
460 label = "data"; 462 label = "flash";
461 reg = <0x00100000 0x03f00000>; 463 reg = <0x00600000 0x03a00000>;
462 }; 464 };
463 }; 465 };
464}; 466};
@@ -563,7 +565,7 @@
563 565
564/* composite video input */ 566/* composite video input */
565&vin1 { 567&vin1 {
566 status = "ok"; 568 status = "okay";
567 pinctrl-0 = <&vin1_pins>; 569 pinctrl-0 = <&vin1_pins>;
568 pinctrl-names = "default"; 570 pinctrl-names = "default";
569 571
@@ -582,6 +584,7 @@
582 pinctrl-0 = <&sound_pins &sound_clk_pins>; 584 pinctrl-0 = <&sound_pins &sound_clk_pins>;
583 pinctrl-names = "default"; 585 pinctrl-names = "default";
584 586
587 /* Single DAI */
585 #sound-dai-cells = <0>; 588 #sound-dai-cells = <0>;
586 589
587 status = "okay"; 590 status = "okay";
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 77c0beeb8d7c..e35812a0d8d4 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -78,7 +78,7 @@
78 <0 0xf1002000 0 0x1000>, 78 <0 0xf1002000 0 0x1000>,
79 <0 0xf1004000 0 0x2000>, 79 <0 0xf1004000 0 0x2000>,
80 <0 0xf1006000 0 0x2000>; 80 <0 0xf1006000 0 0x2000>;
81 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 81 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
82 }; 82 };
83 83
84 gpio0: gpio@e6050000 { 84 gpio0: gpio@e6050000 {
@@ -186,10 +186,10 @@
186 186
187 timer { 187 timer {
188 compatible = "arm,armv7-timer"; 188 compatible = "arm,armv7-timer";
189 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 189 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
190 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 190 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
191 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 191 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
192 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 192 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
193 }; 193 };
194 194
195 cmt0: timer@ffca0000 { 195 cmt0: timer@ffca0000 {
@@ -1062,7 +1062,7 @@
1062 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; 1062 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1063 clocks = <&mp_clk>; 1063 clocks = <&mp_clk>;
1064 #clock-cells = <1>; 1064 #clock-cells = <1>;
1065 renesas,clock-indices = <R8A7791_CLK_MSIOF0>; 1065 clock-indices = <R8A7791_CLK_MSIOF0>;
1066 clock-output-names = "msiof0"; 1066 clock-output-names = "msiof0";
1067 }; 1067 };
1068 mstp1_clks: mstp1_clks@e6150134 { 1068 mstp1_clks: mstp1_clks@e6150134 {
@@ -1073,7 +1073,7 @@
1073 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, 1073 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1074 <&zs_clk>; 1074 <&zs_clk>;
1075 #clock-cells = <1>; 1075 #clock-cells = <1>;
1076 renesas,clock-indices = < 1076 clock-indices = <
1077 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU 1077 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1078 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG 1078 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1079 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 1079 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
@@ -1093,7 +1093,7 @@
1093 <&mp_clk>, <&mp_clk>, <&mp_clk>, 1093 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1094 <&zs_clk>, <&zs_clk>; 1094 <&zs_clk>, <&zs_clk>;
1095 #clock-cells = <1>; 1095 #clock-cells = <1>;
1096 renesas,clock-indices = < 1096 clock-indices = <
1097 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 1097 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
1098 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 1098 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1099 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 1099 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
@@ -1111,7 +1111,7 @@
1111 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, 1111 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1112 <&hp_clk>, <&hp_clk>; 1112 <&hp_clk>, <&hp_clk>;
1113 #clock-cells = <1>; 1113 #clock-cells = <1>;
1114 renesas,clock-indices = < 1114 clock-indices = <
1115 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 1115 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
1116 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 1116 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1117 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 1117 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
@@ -1127,8 +1127,10 @@
1127 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1127 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1128 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; 1128 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
1129 #clock-cells = <1>; 1129 #clock-cells = <1>;
1130 renesas,clock-indices = <R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 1130 clock-indices = <
1131 R8A7791_CLK_THERMAL R8A7791_CLK_PWM>; 1131 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1132 R8A7791_CLK_THERMAL R8A7791_CLK_PWM
1133 >;
1132 clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; 1134 clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
1133 }; 1135 };
1134 mstp7_clks: mstp7_clks@e615014c { 1136 mstp7_clks: mstp7_clks@e615014c {
@@ -1138,7 +1140,7 @@
1138 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, 1140 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1139 <&zx_clk>, <&zx_clk>, <&zx_clk>; 1141 <&zx_clk>, <&zx_clk>, <&zx_clk>;
1140 #clock-cells = <1>; 1142 #clock-cells = <1>;
1141 renesas,clock-indices = < 1143 clock-indices = <
1142 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 1144 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
1143 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 1145 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1144 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 1146 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
@@ -1152,15 +1154,17 @@
1152 mstp8_clks: mstp8_clks@e6150990 { 1154 mstp8_clks: mstp8_clks@e6150990 {
1153 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1155 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1154 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 1156 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1155 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>, 1157 clocks = <&zg_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
1156 <&zs_clk>; 1158 <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
1157 #clock-cells = <1>; 1159 #clock-cells = <1>;
1158 renesas,clock-indices = < 1160 clock-indices = <
1161 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
1159 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 1162 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
1160 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 1163 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
1161 >; 1164 >;
1162 clock-output-names = 1165 clock-output-names =
1163 "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; 1166 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", "ether",
1167 "sata1", "sata0";
1164 }; 1168 };
1165 mstp9_clks: mstp9_clks@e6150994 { 1169 mstp9_clks: mstp9_clks@e6150994 {
1166 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1170 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1171,7 +1175,7 @@
1171 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, 1175 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1172 <&hp_clk>, <&hp_clk>; 1176 <&hp_clk>, <&hp_clk>;
1173 #clock-cells = <1>; 1177 #clock-cells = <1>;
1174 renesas,clock-indices = < 1178 clock-indices = <
1175 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 1179 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1176 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 1180 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
1177 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 1181 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
@@ -1221,7 +1225,7 @@
1221 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; 1225 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1222 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; 1226 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1223 #clock-cells = <1>; 1227 #clock-cells = <1>;
1224 renesas,clock-indices = < 1228 clock-indices = <
1225 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 1229 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1226 >; 1230 >;
1227 clock-output-names = "scifa3", "scifa4", "scifa5"; 1231 clock-output-names = "scifa3", "scifa4", "scifa5";
@@ -1381,8 +1385,13 @@
1381 }; 1385 };
1382 1386
1383 rcar_sound: rcar_sound@ec500000 { 1387 rcar_sound: rcar_sound@ec500000 {
1384 #sound-dai-cells = <1>; 1388 /*
1385 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; 1389 * #sound-dai-cells is required
1390 *
1391 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1392 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1393 */
1394 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
1386 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1395 reg = <0 0xec500000 0 0x1000>, /* SCU */
1387 <0 0xec5a0000 0 0x100>, /* ADG */ 1396 <0 0xec5a0000 0 0x100>, /* ADG */
1388 <0 0xec540000 0 0x1000>, /* SSIU */ 1397 <0 0xec540000 0 0x1000>, /* SSIU */
@@ -1416,16 +1425,16 @@
1416 }; 1425 };
1417 1426
1418 rcar_sound,src { 1427 rcar_sound,src {
1419 src0: src@0 { }; 1428 src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };
1420 src1: src@1 { }; 1429 src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };
1421 src2: src@2 { }; 1430 src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };
1422 src3: src@3 { }; 1431 src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };
1423 src4: src@4 { }; 1432 src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };
1424 src5: src@5 { }; 1433 src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };
1425 src6: src@6 { }; 1434 src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };
1426 src7: src@7 { }; 1435 src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };
1427 src8: src@8 { }; 1436 src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };
1428 src9: src@9 { }; 1437 src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };
1429 }; 1438 };
1430 1439
1431 rcar_sound,ssi { 1440 rcar_sound,ssi {
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index f2cf7576bf3f..0d848e605071 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -40,9 +40,9 @@
40}; 40};
41 41
42&cmt0 { 42&cmt0 {
43 status = "ok"; 43 status = "okay";
44}; 44};
45 45
46&scif2 { 46&scif2 {
47 status = "ok"; 47 status = "okay";
48}; 48};
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 19c9de3f2a5a..8f78da5ef10b 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -47,7 +47,7 @@
47 <0 0xf1002000 0 0x1000>, 47 <0 0xf1002000 0 0x1000>,
48 <0 0xf1004000 0 0x2000>, 48 <0 0xf1004000 0 0x2000>,
49 <0 0xf1006000 0 0x2000>; 49 <0 0xf1006000 0 0x2000>;
50 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 50 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
51 }; 51 };
52 52
53 cmt0: timer@ffca0000 { 53 cmt0: timer@ffca0000 {
@@ -84,10 +84,10 @@
84 84
85 timer { 85 timer {
86 compatible = "arm,armv7-timer"; 86 compatible = "arm,armv7-timer";
87 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 87 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
88 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 88 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
89 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 89 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
90 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 90 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
91 }; 91 };
92 92
93 irqc0: interrupt-controller@e61c0000 { 93 irqc0: interrupt-controller@e61c0000 {
@@ -293,6 +293,28 @@
293 clock-output-names = "main", "pll0", "pll1", "pll3", 293 clock-output-names = "main", "pll0", "pll1", "pll3",
294 "lb", "qspi", "sdh", "sd0", "z"; 294 "lb", "qspi", "sdh", "sd0", "z";
295 }; 295 };
296 /* Variable factor clocks */
297 sd1_clk: sd2_clk@e6150078 {
298 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
299 reg = <0 0xe6150078 0 4>;
300 clocks = <&pll1_div2_clk>;
301 #clock-cells = <0>;
302 clock-output-names = "sd1";
303 };
304 sd2_clk: sd3_clk@e615007c {
305 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
306 reg = <0 0xe615007c 0 4>;
307 clocks = <&pll1_div2_clk>;
308 #clock-cells = <0>;
309 clock-output-names = "sd2";
310 };
311 mmc0_clk: mmc0_clk@e6150240 {
312 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
313 reg = <0 0xe6150240 0 4>;
314 clocks = <&pll1_div2_clk>;
315 #clock-cells = <0>;
316 clock-output-names = "mmc0";
317 };
296 318
297 /* Fixed factor clocks */ 319 /* Fixed factor clocks */
298 pll1_div2_clk: pll1_div2_clk { 320 pll1_div2_clk: pll1_div2_clk {
@@ -455,7 +477,7 @@
455 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; 477 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
456 clocks = <&mp_clk>; 478 clocks = <&mp_clk>;
457 #clock-cells = <1>; 479 #clock-cells = <1>;
458 renesas,clock-indices = <R8A7794_CLK_MSIOF0>; 480 clock-indices = <R8A7794_CLK_MSIOF0>;
459 clock-output-names = "msiof0"; 481 clock-output-names = "msiof0";
460 }; 482 };
461 mstp1_clks: mstp1_clks@e6150134 { 483 mstp1_clks: mstp1_clks@e6150134 {
@@ -465,7 +487,7 @@
465 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, 487 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
466 <&zs_clk>, <&zs_clk>; 488 <&zs_clk>, <&zs_clk>;
467 #clock-cells = <1>; 489 #clock-cells = <1>;
468 renesas,clock-indices = < 490 clock-indices = <
469 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 491 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
470 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 492 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
471 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 493 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
@@ -479,41 +501,51 @@
479 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 501 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
480 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 502 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
481 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 503 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
482 <&mp_clk>, <&mp_clk>, <&mp_clk>; 504 <&mp_clk>, <&mp_clk>, <&mp_clk>,
505 <&zs_clk>, <&zs_clk>;
483 #clock-cells = <1>; 506 #clock-cells = <1>;
484 renesas,clock-indices = < 507 clock-indices = <
485 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 508 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
486 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 509 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
487 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 510 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
511 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
488 >; 512 >;
489 clock-output-names = 513 clock-output-names =
490 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", 514 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
491 "scifb1", "msiof1", "scifb2"; 515 "scifb1", "msiof1", "scifb2",
516 "sys-dmac1", "sys-dmac0";
492 }; 517 };
493 mstp3_clks: mstp3_clks@e615013c { 518 mstp3_clks: mstp3_clks@e615013c {
494 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 519 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
495 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 520 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
496 clocks = <&rclk_clk>; 521 clocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
522 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
497 #clock-cells = <1>; 523 #clock-cells = <1>;
498 renesas,clock-indices = < 524 clock-indices = <
499 R8A7794_CLK_CMT1 525 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
526 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
527 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
500 >; 528 >;
501 clock-output-names = 529 clock-output-names =
502 "cmt1"; 530 "sdhi2", "sdhi1", "sdhi0",
531 "mmcif0", "cmt1", "usbdmac0", "usbdmac1";
503 }; 532 };
504 mstp7_clks: mstp7_clks@e615014c { 533 mstp7_clks: mstp7_clks@e615014c {
505 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 534 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
506 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; 535 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
507 clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, 536 clocks = <&mp_clk>, <&mp_clk>,
537 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
508 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; 538 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
509 #clock-cells = <1>; 539 #clock-cells = <1>;
510 renesas,clock-indices = < 540 clock-indices = <
541 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
511 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 542 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
512 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 543 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
513 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 544 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
514 R8A7794_CLK_SCIF0 545 R8A7794_CLK_SCIF0
515 >; 546 >;
516 clock-output-names = 547 clock-output-names =
548 "ehci", "hsusb",
517 "hscif2", "scif5", "scif4", "hscif1", "hscif0", 549 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
518 "scif3", "scif2", "scif1", "scif0"; 550 "scif3", "scif2", "scif1", "scif0";
519 }; 551 };
@@ -522,18 +554,32 @@
522 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 554 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
523 clocks = <&zg_clk>, <&zg_clk>, <&p_clk>; 555 clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
524 #clock-cells = <1>; 556 #clock-cells = <1>;
525 renesas,clock-indices = < 557 clock-indices = <
526 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER 558 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
527 >; 559 >;
528 clock-output-names = 560 clock-output-names =
529 "vin1", "vin0", "ether"; 561 "vin1", "vin0", "ether";
530 }; 562 };
563 mstp9_clks: mstp9_clks@e6150994 {
564 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
565 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
566 clocks = <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
567 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
568 #clock-cells = <1>;
569 clock-indices = <
570 R8A7794_CLK_QSPI_MOD R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
571 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 R8A7794_CLK_I2C1
572 R8A7794_CLK_I2C0
573 >;
574 clock-output-names =
575 "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
576 };
531 mstp11_clks: mstp11_clks@e615099c { 577 mstp11_clks: mstp11_clks@e615099c {
532 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 578 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
533 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; 579 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
534 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; 580 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
535 #clock-cells = <1>; 581 #clock-cells = <1>;
536 renesas,clock-indices = < 582 clock-indices = <
537 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 583 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
538 >; 584 >;
539 clock-output-names = "scifa3", "scifa4", "scifa5"; 585 clock-output-names = "scifa3", "scifa4", "scifa5";
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index d8c775e6d5fe..d453ddd4b476 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -31,7 +31,7 @@
31 interrupt-parent = <&gpio0>; 31 interrupt-parent = <&gpio0>;
32 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 32 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
33 pinctrl-names = "default"; 33 pinctrl-names = "default";
34 pinctrl-0 = <&pmic_int>; 34 pinctrl-0 = <&pmic_int &global_pwroff>;
35 rockchip,system-power-controller; 35 rockchip,system-power-controller;
36 wakeup-source; 36 wakeup-source;
37 #clock-cells = <1>; 37 #clock-cells = <1>;
@@ -50,6 +50,9 @@
50 regulator-min-microvolt = <750000>; 50 regulator-min-microvolt = <750000>;
51 regulator-max-microvolt = <1350000>; 51 regulator-max-microvolt = <1350000>;
52 regulator-name = "vdd_arm"; 52 regulator-name = "vdd_arm";
53 regulator-state-mem {
54 regulator-off-in-suspend;
55 };
53 }; 56 };
54 57
55 vdd_gpu: DCDC_REG2 { 58 vdd_gpu: DCDC_REG2 {
@@ -58,12 +61,19 @@
58 regulator-min-microvolt = <850000>; 61 regulator-min-microvolt = <850000>;
59 regulator-max-microvolt = <1250000>; 62 regulator-max-microvolt = <1250000>;
60 regulator-name = "vdd_gpu"; 63 regulator-name = "vdd_gpu";
64 regulator-state-mem {
65 regulator-on-in-suspend;
66 regulator-suspend-microvolt = <1000000>;
67 };
61 }; 68 };
62 69
63 vcc_ddr: DCDC_REG3 { 70 vcc_ddr: DCDC_REG3 {
64 regulator-always-on; 71 regulator-always-on;
65 regulator-boot-on; 72 regulator-boot-on;
66 regulator-name = "vcc_ddr"; 73 regulator-name = "vcc_ddr";
74 regulator-state-mem {
75 regulator-on-in-suspend;
76 };
67 }; 77 };
68 78
69 vcc_io: DCDC_REG4 { 79 vcc_io: DCDC_REG4 {
@@ -72,6 +82,10 @@
72 regulator-min-microvolt = <3300000>; 82 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>; 83 regulator-max-microvolt = <3300000>;
74 regulator-name = "vcc_io"; 84 regulator-name = "vcc_io";
85 regulator-state-mem {
86 regulator-on-in-suspend;
87 regulator-suspend-microvolt = <3300000>;
88 };
75 }; 89 };
76 90
77 vccio_pmu: LDO_REG1 { 91 vccio_pmu: LDO_REG1 {
@@ -80,6 +94,10 @@
80 regulator-min-microvolt = <3300000>; 94 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>; 95 regulator-max-microvolt = <3300000>;
82 regulator-name = "vccio_pmu"; 96 regulator-name = "vccio_pmu";
97 regulator-state-mem {
98 regulator-on-in-suspend;
99 regulator-suspend-microvolt = <3300000>;
100 };
83 }; 101 };
84 102
85 vcc_tp: LDO_REG2 { 103 vcc_tp: LDO_REG2 {
@@ -88,6 +106,9 @@
88 regulator-min-microvolt = <3300000>; 106 regulator-min-microvolt = <3300000>;
89 regulator-max-microvolt = <3300000>; 107 regulator-max-microvolt = <3300000>;
90 regulator-name = "vcc_tp"; 108 regulator-name = "vcc_tp";
109 regulator-state-mem {
110 regulator-off-in-suspend;
111 };
91 }; 112 };
92 113
93 vdd_10: LDO_REG3 { 114 vdd_10: LDO_REG3 {
@@ -96,6 +117,10 @@
96 regulator-min-microvolt = <1000000>; 117 regulator-min-microvolt = <1000000>;
97 regulator-max-microvolt = <1000000>; 118 regulator-max-microvolt = <1000000>;
98 regulator-name = "vdd_10"; 119 regulator-name = "vdd_10";
120 regulator-state-mem {
121 regulator-on-in-suspend;
122 regulator-suspend-microvolt = <1000000>;
123 };
99 }; 124 };
100 125
101 vcc18_lcd: LDO_REG4 { 126 vcc18_lcd: LDO_REG4 {
@@ -104,6 +129,10 @@
104 regulator-min-microvolt = <1800000>; 129 regulator-min-microvolt = <1800000>;
105 regulator-max-microvolt = <1800000>; 130 regulator-max-microvolt = <1800000>;
106 regulator-name = "vcc18_lcd"; 131 regulator-name = "vcc18_lcd";
132 regulator-state-mem {
133 regulator-on-in-suspend;
134 regulator-suspend-microvolt = <1800000>;
135 };
107 }; 136 };
108 137
109 vccio_sd: LDO_REG5 { 138 vccio_sd: LDO_REG5 {
@@ -112,6 +141,10 @@
112 regulator-min-microvolt = <1800000>; 141 regulator-min-microvolt = <1800000>;
113 regulator-max-microvolt = <3300000>; 142 regulator-max-microvolt = <3300000>;
114 regulator-name = "vccio_sd"; 143 regulator-name = "vccio_sd";
144 regulator-state-mem {
145 regulator-on-in-suspend;
146 regulator-suspend-microvolt = <3300000>;
147 };
115 }; 148 };
116 149
117 vdd10_lcd: LDO_REG6 { 150 vdd10_lcd: LDO_REG6 {
@@ -120,6 +153,10 @@
120 regulator-min-microvolt = <1000000>; 153 regulator-min-microvolt = <1000000>;
121 regulator-max-microvolt = <1000000>; 154 regulator-max-microvolt = <1000000>;
122 regulator-name = "vdd10_lcd"; 155 regulator-name = "vdd10_lcd";
156 regulator-state-mem {
157 regulator-on-in-suspend;
158 regulator-suspend-microvolt = <1000000>;
159 };
123 }; 160 };
124 161
125 vcc_18: LDO_REG7 { 162 vcc_18: LDO_REG7 {
@@ -128,6 +165,10 @@
128 regulator-min-microvolt = <1800000>; 165 regulator-min-microvolt = <1800000>;
129 regulator-max-microvolt = <1800000>; 166 regulator-max-microvolt = <1800000>;
130 regulator-name = "vcc_18"; 167 regulator-name = "vcc_18";
168 regulator-state-mem {
169 regulator-on-in-suspend;
170 regulator-suspend-microvolt = <1800000>;
171 };
131 }; 172 };
132 173
133 vcca_codec: LDO_REG8 { 174 vcca_codec: LDO_REG8 {
@@ -136,18 +177,28 @@
136 regulator-min-microvolt = <3300000>; 177 regulator-min-microvolt = <3300000>;
137 regulator-max-microvolt = <3300000>; 178 regulator-max-microvolt = <3300000>;
138 regulator-name = "vcca_codec"; 179 regulator-name = "vcca_codec";
180 regulator-state-mem {
181 regulator-on-in-suspend;
182 regulator-suspend-microvolt = <3300000>;
183 };
139 }; 184 };
140 185
141 vcc_wl: SWITCH_REG1 { 186 vcc_wl: SWITCH_REG1 {
142 regulator-always-on; 187 regulator-always-on;
143 regulator-boot-on; 188 regulator-boot-on;
144 regulator-name = "vcc_wl"; 189 regulator-name = "vcc_wl";
190 regulator-state-mem {
191 regulator-on-in-suspend;
192 };
145 }; 193 };
146 194
147 vcc_lcd: SWITCH_REG2 { 195 vcc_lcd: SWITCH_REG2 {
148 regulator-always-on; 196 regulator-always-on;
149 regulator-boot-on; 197 regulator-boot-on;
150 regulator-name = "vcc_lcd"; 198 regulator-name = "vcc_lcd";
199 regulator-state-mem {
200 regulator-on-in-suspend;
201 };
151 }; 202 };
152 }; 203 };
153 }; 204 };
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index fd19f00784bd..2a878a35facc 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -151,6 +151,7 @@
151 151
152 sdmmc: dwmmc@ff0c0000 { 152 sdmmc: dwmmc@ff0c0000 {
153 compatible = "rockchip,rk3288-dw-mshc"; 153 compatible = "rockchip,rk3288-dw-mshc";
154 clock-freq-min-max = <400000 150000000>;
154 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 155 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
155 clock-names = "biu", "ciu"; 156 clock-names = "biu", "ciu";
156 fifo-depth = <0x100>; 157 fifo-depth = <0x100>;
@@ -161,6 +162,7 @@
161 162
162 sdio0: dwmmc@ff0d0000 { 163 sdio0: dwmmc@ff0d0000 {
163 compatible = "rockchip,rk3288-dw-mshc"; 164 compatible = "rockchip,rk3288-dw-mshc";
165 clock-freq-min-max = <400000 150000000>;
164 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>; 166 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
165 clock-names = "biu", "ciu"; 167 clock-names = "biu", "ciu";
166 fifo-depth = <0x100>; 168 fifo-depth = <0x100>;
@@ -171,6 +173,7 @@
171 173
172 sdio1: dwmmc@ff0e0000 { 174 sdio1: dwmmc@ff0e0000 {
173 compatible = "rockchip,rk3288-dw-mshc"; 175 compatible = "rockchip,rk3288-dw-mshc";
176 clock-freq-min-max = <400000 150000000>;
174 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>; 177 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
175 clock-names = "biu", "ciu"; 178 clock-names = "biu", "ciu";
176 fifo-depth = <0x100>; 179 fifo-depth = <0x100>;
@@ -181,6 +184,7 @@
181 184
182 emmc: dwmmc@ff0f0000 { 185 emmc: dwmmc@ff0f0000 {
183 compatible = "rockchip,rk3288-dw-mshc"; 186 compatible = "rockchip,rk3288-dw-mshc";
187 clock-freq-min-max = <400000 150000000>;
184 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 188 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
185 clock-names = "biu", "ciu"; 189 clock-names = "biu", "ciu";
186 fifo-depth = <0x100>; 190 fifo-depth = <0x100>;
@@ -502,6 +506,11 @@
502 }; 506 };
503 }; 507 };
504 508
509 sram@ff720000 {
510 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
511 reg = <0xff720000 0x1000>;
512 };
513
505 pmu: power-management@ff730000 { 514 pmu: power-management@ff730000 {
506 compatible = "rockchip,rk3288-pmu", "syscon"; 515 compatible = "rockchip,rk3288-pmu", "syscon";
507 reg = <0xff730000 0x100>; 516 reg = <0xff730000 0x100>;
@@ -725,6 +734,24 @@
725 bias-disable; 734 bias-disable;
726 }; 735 };
727 736
737 sleep {
738 global_pwroff: global-pwroff {
739 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
740 };
741
742 ddrio_pwroff: ddrio-pwroff {
743 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
744 };
745
746 ddr0_retention: ddr0-retention {
747 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
748 };
749
750 ddr1_retention: ddr1-retention {
751 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
752 };
753 };
754
728 i2c0 { 755 i2c0 {
729 i2c0_xfer: i2c0-xfer { 756 i2c0_xfer: i2c0-xfer {
730 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, 757 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 5f4144d1e3a1..261311bdf65b 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -78,6 +78,11 @@
78 }; 78 };
79 }; 79 };
80 80
81 sram: sram@00300000 {
82 compatible = "mmio-sram";
83 reg = <0x00300000 0x20000>;
84 };
85
81 ahb { 86 ahb {
82 compatible = "simple-bus"; 87 compatible = "simple-bus";
83 #address-cells = <1>; 88 #address-cells = <1>;
@@ -214,7 +219,20 @@
214 compatible = "atmel,at91sam9g45-isi"; 219 compatible = "atmel,at91sam9g45-isi";
215 reg = <0xf0034000 0x4000>; 220 reg = <0xf0034000 0x4000>;
216 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; 221 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_isi_data_0_7>;
224 clocks = <&isi_clk>;
225 clock-names = "isi_clk";
217 status = "disabled"; 226 status = "disabled";
227 port {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 };
231 };
232
233 sfr: sfr@f0038000 {
234 compatible = "atmel,sama5d3-sfr", "syscon";
235 reg = <0xf0038000 0x60>;
218 }; 236 };
219 237
220 mmc1: mmc@f8000000 { 238 mmc1: mmc@f8000000 {
@@ -545,7 +563,7 @@
545 }; 563 };
546 564
547 isi { 565 isi {
548 pinctrl_isi: isi-0 { 566 pinctrl_isi_data_0_7: isi-0-data-0-7 {
549 atmel,pins = 567 atmel,pins =
550 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ 568 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
551 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ 569 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
@@ -557,13 +575,19 @@
557 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ 575 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
558 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ 576 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
559 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ 577 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
560 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ 578 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
561 AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ 579 };
580
581 pinctrl_isi_data_8_9: isi-0-data-8-9 {
582 atmel,pins =
583 <AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
562 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ 584 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
563 }; 585 };
564 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 { 586
587 pinctrl_isi_data_10_11: isi-0-data-10-11 {
565 atmel,pins = 588 atmel,pins =
566 <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */ 589 <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC27 periph C ISI_PD10, conflicts with SPI1_NPCS2, TWCK1 */
590 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */
567 }; 591 };
568 }; 592 };
569 593
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index cfcd200b0c17..7d6babdab039 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -122,6 +122,7 @@
122 d2 { 122 d2 {
123 label = "d2"; 123 label = "d2";
124 gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */ 124 gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */
125 linux,default-trigger = "heartbeat";
125 }; 126 };
126 }; 127 };
127}; 128};
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index 49c10d33df30..9fdb8a07b145 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -52,6 +52,29 @@
52 }; 52 };
53 }; 53 };
54 54
55 i2c1: i2c@f0018000 {
56 ov2640: camera@0x30 {
57 compatible = "ovti,ov2640";
58 reg = <0x30>;
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
61 resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>;
62 pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
63 /* use pck1 for the master clock of ov2640 */
64 clocks = <&pck1>;
65 clock-names = "xvclk";
66 assigned-clocks = <&pck1>;
67 assigned-clock-rates = <25000000>;
68
69 port {
70 ov2640_0: endpoint {
71 remote-endpoint = <&isi_0>;
72 bus-width = <8>;
73 };
74 };
75 };
76 };
77
55 usart1: serial@f0020000 { 78 usart1: serial@f0020000 {
56 dmas = <0>, <0>; /* Do not use DMA for usart1 */ 79 dmas = <0>, <0>; /* Do not use DMA for usart1 */
57 pinctrl-names = "default"; 80 pinctrl-names = "default";
@@ -60,8 +83,12 @@
60 }; 83 };
61 84
62 isi: isi@f0034000 { 85 isi: isi@f0034000 {
63 pinctrl-names = "default"; 86 port {
64 pinctrl-0 = <&pinctrl_isi &pinctrl_isi_pck_as_mck &pinctrl_isi_power &pinctrl_isi_reset>; 87 isi_0: endpoint {
88 remote-endpoint = <&ov2640_0>;
89 bus-width = <8>;
90 };
91 };
65 }; 92 };
66 93
67 mmc1: mmc@f8000000 { 94 mmc1: mmc@f8000000 {
@@ -117,12 +144,17 @@
117 <AT91_PIOD 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD30 periph B */ 144 <AT91_PIOD 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD30 periph B */
118 }; 145 };
119 146
120 pinctrl_isi_reset: isi_reset-0 { 147 pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 {
148 atmel,pins =
149 <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
150 };
151
152 pinctrl_sensor_reset: sensor_reset-0 {
121 atmel,pins = 153 atmel,pins =
122 <AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE24 gpio */ 154 <AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE24 gpio */
123 }; 155 };
124 156
125 pinctrl_isi_power: isi_power-0 { 157 pinctrl_sensor_power: sensor_power-0 {
126 atmel,pins = 158 atmel,pins =
127 <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE29 gpio */ 159 <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE29 gpio */
128 }; 160 };
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 1b0f30c2c4a5..1b4fe4e19721 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -103,6 +103,11 @@
103 }; 103 };
104 }; 104 };
105 105
106 ns_sram: sram@00210000 {
107 compatible = "mmio-sram";
108 reg = <0x00210000 0x10000>;
109 };
110
106 ahb { 111 ahb {
107 compatible = "simple-bus"; 112 compatible = "simple-bus";
108 #address-cells = <1>; 113 #address-cells = <1>;
@@ -870,6 +875,11 @@
870 status = "disabled"; 875 status = "disabled";
871 }; 876 };
872 877
878 sfr: sfr@f8028000 {
879 compatible = "atmel,sama5d4-sfr", "syscon";
880 reg = <0xf8028000 0x60>;
881 };
882
873 mmc1: mmc@fc000000 { 883 mmc1: mmc@fc000000 {
874 compatible = "atmel,hsmci"; 884 compatible = "atmel,hsmci";
875 reg = <0xfc000000 0x600>; 885 reg = <0xfc000000 0x600>;
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 939be1299ca6..863dc4c7d7f6 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -179,7 +179,7 @@
179}; 179};
180 180
181&cmt1 { 181&cmt1 {
182 status = "ok"; 182 status = "okay";
183}; 183};
184 184
185&i2c0 { 185&i2c0 {
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index d8def5a529da..37c8a761aeab 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -42,6 +42,22 @@
42 <0xf0000100 0x100>; 42 <0xf0000100 0x100>;
43 }; 43 };
44 44
45 sbsc2: memory-controller@fb400000 {
46 compatible = "renesas,sbsc-sh73a0";
47 reg = <0xfb400000 0x400>;
48 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
49 <0 38 IRQ_TYPE_LEVEL_HIGH>;
50 interrupt-names = "sec", "temp";
51 };
52
53 sbsc1: memory-controller@fe400000 {
54 compatible = "renesas,sbsc-sh73a0";
55 reg = <0xfe400000 0x400>;
56 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
57 <0 36 IRQ_TYPE_LEVEL_HIGH>;
58 interrupt-names = "sec", "temp";
59 };
60
45 pmu { 61 pmu {
46 compatible = "arm,cortex-a9-pmu"; 62 compatible = "arm,cortex-a9-pmu";
47 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>, 63 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
@@ -317,7 +333,7 @@
317 333
318 sh_fsi2: sound@ec230000 { 334 sh_fsi2: sound@ec230000 {
319 #sound-dai-cells = <1>; 335 #sound-dai-cells = <1>;
320 compatible = "renesas,sh_fsi2"; 336 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
321 reg = <0xec230000 0x400>; 337 reg = <0xec230000 0x400>;
322 interrupts = <0 146 0x4>; 338 interrupts = <0 146 0x4>;
323 status = "disabled"; 339 status = "disabled";
diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts
index 261d5e2c48d2..af487145cd89 100644
--- a/arch/arm/boot/dts/stih407-b2120.dts
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -7,9 +7,8 @@
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
8 */ 8 */
9/dts-v1/; 9/dts-v1/;
10#include "stih407-clock.dtsi"
11#include "stih407-family.dtsi"
12#include "stihxxx-b2120.dtsi" 10#include "stihxxx-b2120.dtsi"
11#include "stih407.dtsi"
13/ { 12/ {
14 model = "STiH407 B2120"; 13 model = "STiH407 B2120";
15 compatible = "st,stih407-b2120", "st,stih407"; 14 compatible = "st,stih407-b2120", "st,stih407";
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 3e31d32133b8..c06a54681912 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -274,5 +274,67 @@
274 274
275 status = "disabled"; 275 status = "disabled";
276 }; 276 };
277
278 usb2_picophy0: phy1 {
279 compatible = "st,stih407-usb2-phy";
280 #phy-cells = <0>;
281 st,syscfg = <&syscfg_core 0x100 0xf4>;
282 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
283 <&picophyreset STIH407_PICOPHY0_RESET>;
284 reset-names = "global", "port";
285 };
286
287 miphy28lp_phy: miphy28lp@9b22000 {
288 compatible = "st,miphy28lp-phy";
289 st,syscfg = <&syscfg_core>;
290 #address-cells = <1>;
291 #size-cells = <1>;
292 ranges;
293
294 phy_port0: port@9b22000 {
295 reg = <0x9b22000 0xff>,
296 <0x9b09000 0xff>,
297 <0x9b04000 0xff>;
298 reg-names = "sata-up",
299 "pcie-up",
300 "pipew";
301
302 st,syscfg = <0x114 0x818 0xe0 0xec>;
303 #phy-cells = <1>;
304
305 reset-names = "miphy-sw-rst";
306 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
307 };
308
309 phy_port1: port@9b2a000 {
310 reg = <0x9b2a000 0xff>,
311 <0x9b19000 0xff>,
312 <0x9b14000 0xff>;
313 reg-names = "sata-up",
314 "pcie-up",
315 "pipew";
316
317 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
318
319 #phy-cells = <1>;
320
321 reset-names = "miphy-sw-rst";
322 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
323 };
324
325 phy_port2: port@8f95000 {
326 reg = <0x8f95000 0xff>,
327 <0x8f90000 0xff>;
328 reg-names = "pipew",
329 "usb3-up";
330
331 st,syscfg = <0x11c 0x820>;
332
333 #phy-cells = <1>;
334
335 reset-names = "miphy-sw-rst";
336 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
337 };
338 };
277 }; 339 };
278}; 340};
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
new file mode 100644
index 000000000000..3efa3b2ebe90
--- /dev/null
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -0,0 +1,151 @@
1/*
2 * Copyright (C) 2015 STMicroelectronics Limited.
3 * Author: Gabriel Fernandez <gabriel.fernandez@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih407-clock.dtsi"
10#include "stih407-family.dtsi"
11/ {
12 soc {
13 /* Display */
14 vtg_main: sti-vtg-main@8d02800 {
15 compatible = "st,vtg";
16 reg = <0x8d02800 0x200>;
17 interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
18 };
19
20 vtg_aux: sti-vtg-aux@8d00200 {
21 compatible = "st,vtg";
22 reg = <0x8d00200 0x100>;
23 interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
24 };
25
26 sti-display-subsystem {
27 compatible = "st,sti-display-subsystem";
28 #address-cells = <1>;
29 #size-cells = <1>;
30
31 assigned-clocks = <&clk_s_d2_quadfs 0>,
32 <&clk_s_d2_quadfs 0>,
33 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
34 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
35 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
36 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
37 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
38 <&clk_s_d2_flexgen CLK_PIX_GDP4>;
39
40 assigned-clock-parents = <0>,
41 <0>,
42 <&clk_s_d2_quadfs 0>,
43 <&clk_s_d2_quadfs 0>,
44 <&clk_s_d2_quadfs 0>,
45 <&clk_s_d2_quadfs 0>,
46 <&clk_s_d2_quadfs 0>,
47 <&clk_s_d2_quadfs 0>;
48
49 assigned-clock-rates = <297000000>, <297000000>;
50
51 ranges;
52
53 sti-compositor@9d11000 {
54 compatible = "st,stih407-compositor";
55 reg = <0x9d11000 0x1000>;
56
57 clock-names = "compo_main",
58 "compo_aux",
59 "pix_main",
60 "pix_aux",
61 "pix_gdp1",
62 "pix_gdp2",
63 "pix_gdp3",
64 "pix_gdp4",
65 "main_parent",
66 "aux_parent";
67
68 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
69 <&clk_s_c0_flexgen CLK_COMPO_DVP>,
70 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
71 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
72 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
73 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
74 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
75 <&clk_s_d2_flexgen CLK_PIX_GDP4>,
76 <&clk_s_d2_quadfs 0>,
77 <&clk_s_d2_quadfs 1>;
78
79 reset-names = "compo-main", "compo-aux";
80 resets = <&softreset STIH407_COMPO_SOFTRESET>,
81 <&softreset STIH407_COMPO_SOFTRESET>;
82 st,vtg = <&vtg_main>, <&vtg_aux>;
83 };
84
85 sti-tvout@8d08000 {
86 compatible = "st,stih407-tvout";
87 reg = <0x8d08000 0x1000>;
88 reg-names = "tvout-reg";
89 reset-names = "tvout";
90 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
91 #address-cells = <1>;
92 #size-cells = <1>;
93 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
94 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
95 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
96 <&clk_s_d0_flexgen CLK_PCM_0>,
97 <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
98 <&clk_s_d2_flexgen CLK_HDDAC>;
99
100 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
101 <&clk_tmdsout_hdmi>,
102 <&clk_s_d2_quadfs 0>,
103 <&clk_s_d0_quadfs 0>,
104 <&clk_s_d2_quadfs 0>,
105 <&clk_s_d2_quadfs 0>;
106 ranges;
107
108 sti-hdmi@8d04000 {
109 compatible = "st,stih407-hdmi";
110 reg = <0x8d04000 0x1000>;
111 reg-names = "hdmi-reg";
112 interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
113 interrupt-names = "irq";
114 clock-names = "pix",
115 "tmds",
116 "phy",
117 "audio",
118 "main_parent",
119 "aux_parent";
120
121 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
122 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
123 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
124 <&clk_s_d0_flexgen CLK_PCM_0>,
125 <&clk_s_d2_quadfs 0>,
126 <&clk_s_d2_quadfs 1>;
127
128 hdmi,hpd-gpio = <&pio5 3>;
129 reset-names = "hdmi";
130 resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
131 ddc = <&hdmiddc>;
132
133 };
134
135 sti-hda@8d02000 {
136 compatible = "st,stih407-hda";
137 reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
138 reg-names = "hda-reg", "video-dacs-ctrl";
139 clock-names = "pix",
140 "hddac",
141 "main_parent",
142 "aux_parent";
143 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
144 <&clk_s_d2_flexgen CLK_HDDAC>,
145 <&clk_s_d2_quadfs 0>,
146 <&clk_s_d2_quadfs 1>;
147 };
148 };
149 };
150 };
151};
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index c05627eb717d..208b5e89036a 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -10,5 +10,213 @@
10#include "stih407-family.dtsi" 10#include "stih407-family.dtsi"
11#include "stih410-pinctrl.dtsi" 11#include "stih410-pinctrl.dtsi"
12/ { 12/ {
13 soc {
14 usb2_picophy1: phy2 {
15 compatible = "st,stih407-usb2-phy";
16 #phy-cells = <0>;
17 st,syscfg = <&syscfg_core 0xf8 0xf4>;
18 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
19 <&picophyreset STIH407_PICOPHY0_RESET>;
20 reset-names = "global", "port";
21 };
13 22
23 usb2_picophy2: phy3 {
24 compatible = "st,stih407-usb2-phy";
25 #phy-cells = <0>;
26 st,syscfg = <&syscfg_core 0xfc 0xf4>;
27 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
28 <&picophyreset STIH407_PICOPHY1_RESET>;
29 reset-names = "global", "port";
30 };
31
32 ohci0: usb@9a03c00 {
33 compatible = "st,st-ohci-300x";
34 reg = <0x9a03c00 0x100>;
35 interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
36 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
37 resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
38 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
39 reset-names = "power", "softreset";
40 phys = <&usb2_picophy1>;
41 phy-names = "usb";
42 };
43
44 ehci0: usb@9a03e00 {
45 compatible = "st,st-ehci-300x";
46 reg = <0x9a03e00 0x100>;
47 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_usb0>;
50 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
51 resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
52 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
53 reset-names = "power", "softreset";
54 phys = <&usb2_picophy1>;
55 phy-names = "usb";
56 };
57
58 ohci1: usb@9a83c00 {
59 compatible = "st,st-ohci-300x";
60 reg = <0x9a83c00 0x100>;
61 interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
62 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
63 resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
64 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
65 reset-names = "power", "softreset";
66 phys = <&usb2_picophy2>;
67 phy-names = "usb";
68 };
69
70 ehci1: usb@9a83e00 {
71 compatible = "st,st-ehci-300x";
72 reg = <0x9a83e00 0x100>;
73 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_usb1>;
76 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
77 resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
78 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
79 reset-names = "power", "softreset";
80 phys = <&usb2_picophy2>;
81 phy-names = "usb";
82 };
83
84 /* Display */
85 vtg_main: sti-vtg-main@8d02800 {
86 compatible = "st,vtg";
87 reg = <0x8d02800 0x200>;
88 interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
89 };
90
91 vtg_aux: sti-vtg-aux@8d00200 {
92 compatible = "st,vtg";
93 reg = <0x8d00200 0x100>;
94 interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
95 };
96
97 sti-display-subsystem {
98 compatible = "st,sti-display-subsystem";
99 #address-cells = <1>;
100 #size-cells = <1>;
101
102 assigned-clocks = <&clk_s_d2_quadfs 0>,
103 <&clk_s_d2_quadfs 0>,
104 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
105 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
106 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
107 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
108 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
109 <&clk_s_d2_flexgen CLK_PIX_GDP4>;
110
111 assigned-clock-parents = <0>,
112 <0>,
113 <&clk_s_d2_quadfs 0>,
114 <&clk_s_d2_quadfs 0>,
115 <&clk_s_d2_quadfs 0>,
116 <&clk_s_d2_quadfs 0>,
117 <&clk_s_d2_quadfs 0>,
118 <&clk_s_d2_quadfs 0>;
119
120 assigned-clock-rates = <297000000>, <297000000>;
121
122 ranges;
123
124 sti-compositor@9d11000 {
125 compatible = "st,stih407-compositor";
126 reg = <0x9d11000 0x1000>;
127
128 clock-names = "compo_main",
129 "compo_aux",
130 "pix_main",
131 "pix_aux",
132 "pix_gdp1",
133 "pix_gdp2",
134 "pix_gdp3",
135 "pix_gdp4",
136 "main_parent",
137 "aux_parent";
138
139 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
140 <&clk_s_c0_flexgen CLK_COMPO_DVP>,
141 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
142 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
143 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
144 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
145 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
146 <&clk_s_d2_flexgen CLK_PIX_GDP4>,
147 <&clk_s_d2_quadfs 0>,
148 <&clk_s_d2_quadfs 1>;
149
150 reset-names = "compo-main", "compo-aux";
151 resets = <&softreset STIH407_COMPO_SOFTRESET>,
152 <&softreset STIH407_COMPO_SOFTRESET>;
153 st,vtg = <&vtg_main>, <&vtg_aux>;
154 };
155
156 sti-tvout@8d08000 {
157 compatible = "st,stih407-tvout";
158 reg = <0x8d08000 0x1000>;
159 reg-names = "tvout-reg";
160 reset-names = "tvout";
161 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
162 #address-cells = <1>;
163 #size-cells = <1>;
164 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
165 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
166 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
167 <&clk_s_d0_flexgen CLK_PCM_0>,
168 <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
169 <&clk_s_d2_flexgen CLK_HDDAC>;
170
171 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
172 <&clk_tmdsout_hdmi>,
173 <&clk_s_d2_quadfs 0>,
174 <&clk_s_d0_quadfs 0>,
175 <&clk_s_d2_quadfs 0>,
176 <&clk_s_d2_quadfs 0>;
177 ranges;
178
179 sti-hdmi@8d04000 {
180 compatible = "st,stih407-hdmi";
181 reg = <0x8d04000 0x1000>;
182 reg-names = "hdmi-reg";
183 interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
184 interrupt-names = "irq";
185 clock-names = "pix",
186 "tmds",
187 "phy",
188 "audio",
189 "main_parent",
190 "aux_parent";
191
192 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
193 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
194 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
195 <&clk_s_d0_flexgen CLK_PCM_0>,
196 <&clk_s_d2_quadfs 0>,
197 <&clk_s_d2_quadfs 1>;
198
199 hdmi,hpd-gpio = <&pio5 3>;
200 reset-names = "hdmi";
201 resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
202 ddc = <&hdmiddc>;
203
204 };
205
206 sti-hda@8d02000 {
207 compatible = "st,stih407-hda";
208 reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
209 reg-names = "hda-reg", "video-dacs-ctrl";
210 clock-names = "pix",
211 "hddac",
212 "main_parent",
213 "aux_parent";
214 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
215 <&clk_s_d2_flexgen CLK_HDDAC>,
216 <&clk_s_d2_quadfs 0>,
217 <&clk_s_d2_quadfs 1>;
218 };
219 };
220 };
221 };
14}; 222};
diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts
new file mode 100644
index 000000000000..926235c08e4d
--- /dev/null
+++ b/arch/arm/boot/dts/stih418-b2199.dts
@@ -0,0 +1,78 @@
1/*
2 * Copyright (C) 2015 STMicroelectronics (R&D) Limited.
3 * Author: Maxime Coquelin <maxime.coquelin@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9/dts-v1/;
10#include "stih418.dtsi"
11/ {
12 model = "STiH418 B2199";
13 compatible = "st,stih418-b2199", "st,stih418";
14
15 chosen {
16 bootargs = "console=ttyAS0,115200 clk_ignore_unused";
17 linux,stdout-path = &sbc_serial0;
18 };
19
20 memory {
21 device_type = "memory";
22 reg = <0x40000000 0xc0000000>;
23 };
24
25 aliases {
26 ttyAS0 = &sbc_serial0;
27 };
28
29 soc {
30 sbc_serial0: serial@9530000 {
31 status = "okay";
32 };
33
34 leds {
35 compatible = "gpio-leds";
36 red {
37 #gpio-cells = <2>;
38 label = "Front Panel LED";
39 gpios = <&pio4 1 0>;
40 linux,default-trigger = "heartbeat";
41 };
42 green {
43 #gpio-cells = <2>;
44 gpios = <&pio1 3 0>;
45 default-state = "off";
46 };
47 };
48
49 i2c@9842000 {
50 status = "okay";
51 };
52
53 i2c@9843000 {
54 status = "okay";
55 };
56
57 i2c@9844000 {
58 status = "okay";
59 };
60
61 i2c@9845000 {
62 status = "okay";
63 };
64
65 i2c@9540000 {
66 status = "okay";
67 };
68
69 /* SSC11 to HDMI */
70 i2c@9541000 {
71 status = "okay";
72 /* HDMI V1.3a supports Standard mode only */
73 clock-frequency = <100000>;
74 st,i2c-min-scl-pulse-width-us = <0>;
75 st,i2c-min-sda-pulse-width-us = <5>;
76 };
77 };
78};
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
new file mode 100644
index 000000000000..0ab23daa2829
--- /dev/null
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -0,0 +1,348 @@
1/*
2 * Copyright (C) 2015 STMicroelectronics R&D Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include <dt-bindings/clock/stih418-clks.h>
9/ {
10 clocks {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges;
14
15 compatible = "st,stih418-clk", "simple-bus";
16
17 /*
18 * Fixed 30MHz oscillator inputs to SoC
19 */
20 clk_sysin: clk-sysin {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <30000000>;
24 clock-output-names = "CLK_SYSIN";
25 };
26
27 /*
28 * ARM Peripheral clock for timers
29 */
30 arm_periph_clk: clk-m-a9-periphs {
31 #clock-cells = <0>;
32 compatible = "fixed-factor-clock";
33 clocks = <&clk_m_a9>;
34 clock-div = <2>;
35 clock-mult = <1>;
36 };
37
38 /*
39 * A9 PLL.
40 */
41 clockgen-a9@92b0000 {
42 compatible = "st,clkgen-c32";
43 reg = <0x92b0000 0xffff>;
44
45 clockgen_a9_pll: clockgen-a9-pll {
46 #clock-cells = <1>;
47 compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
48
49 clocks = <&clk_sysin>;
50
51 clock-output-names = "clockgen-a9-pll-odf";
52 };
53 };
54
55 /*
56 * ARM CPU related clocks.
57 */
58 clk_m_a9: clk-m-a9@92b0000 {
59 #clock-cells = <0>;
60 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
61 reg = <0x92b0000 0x10000>;
62
63 clocks = <&clockgen_a9_pll 0>,
64 <&clockgen_a9_pll 0>,
65 <&clk_s_c0_flexgen 13>,
66 <&clk_m_a9_ext2f_div2>;
67 };
68
69 /*
70 * ARM Peripheral clock for timers
71 */
72 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
73 #clock-cells = <0>;
74 compatible = "fixed-factor-clock";
75
76 clocks = <&clk_s_c0_flexgen 13>;
77
78 clock-output-names = "clk-m-a9-ext2f-div2";
79
80 clock-div = <2>;
81 clock-mult = <1>;
82 };
83
84 /*
85 * Bootloader initialized system infrastructure clock for
86 * serial devices.
87 */
88 clk_ext2f_a9: clockgen-c0@13 {
89 #clock-cells = <0>;
90 compatible = "fixed-clock";
91 clock-frequency = <200000000>;
92 clock-output-names = "clk-s-icn-reg-0";
93 };
94
95 clockgen-a@090ff000 {
96 compatible = "st,clkgen-c32";
97 reg = <0x90ff000 0x1000>;
98
99 clk_s_a0_pll: clk-s-a0-pll {
100 #clock-cells = <1>;
101 compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
102
103 clocks = <&clk_sysin>;
104
105 clock-output-names = "clk-s-a0-pll-ofd-0";
106 };
107
108 clk_s_a0_flexgen: clk-s-a0-flexgen {
109 compatible = "st,flexgen";
110
111 #clock-cells = <1>;
112
113 clocks = <&clk_s_a0_pll 0>,
114 <&clk_sysin>;
115
116 clock-output-names = "clk-ic-lmi0",
117 "clk-ic-lmi1";
118 };
119 };
120
121 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
122 #clock-cells = <1>;
123 compatible = "st,stih407-quadfs660-C", "st,quadfs";
124 reg = <0x9103000 0x1000>;
125
126 clocks = <&clk_sysin>;
127
128 clock-output-names = "clk-s-c0-fs0-ch0",
129 "clk-s-c0-fs0-ch1",
130 "clk-s-c0-fs0-ch2",
131 "clk-s-c0-fs0-ch3";
132 };
133
134 clk_s_c0: clockgen-c@09103000 {
135 compatible = "st,clkgen-c32";
136 reg = <0x9103000 0x1000>;
137
138 clk_s_c0_pll0: clk-s-c0-pll0 {
139 #clock-cells = <1>;
140 compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
141
142 clocks = <&clk_sysin>;
143
144 clock-output-names = "clk-s-c0-pll0-odf-0";
145 };
146
147 clk_s_c0_pll1: clk-s-c0-pll1 {
148 #clock-cells = <1>;
149 compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
150
151 clocks = <&clk_sysin>;
152
153 clock-output-names = "clk-s-c0-pll1-odf-0";
154 };
155
156 clk_s_c0_flexgen: clk-s-c0-flexgen {
157 #clock-cells = <1>;
158 compatible = "st,flexgen";
159
160 clocks = <&clk_s_c0_pll0 0>,
161 <&clk_s_c0_pll1 0>,
162 <&clk_s_c0_quadfs 0>,
163 <&clk_s_c0_quadfs 1>,
164 <&clk_s_c0_quadfs 2>,
165 <&clk_s_c0_quadfs 3>,
166 <&clk_sysin>;
167
168 clock-output-names = "clk-icn-gpu",
169 "clk-fdma",
170 "clk-nand",
171 "clk-hva",
172 "clk-proc-stfe",
173 "clk-tp",
174 "clk-rx-icn-dmu",
175 "clk-rx-icn-hva",
176 "clk-icn-cpu",
177 "clk-tx-icn-dmu",
178 "clk-mmc-0",
179 "clk-mmc-1",
180 "clk-jpegdec",
181 "clk-icn-reg",
182 "clk-proc-bdisp-0",
183 "clk-proc-bdisp-1",
184 "clk-pp-dmu",
185 "clk-vid-dmu",
186 "clk-dss-lpc",
187 "clk-st231-aud-0",
188 "clk-st231-gp-1",
189 "clk-st231-dmu",
190 "clk-icn-lmi",
191 "clk-tx-icn-1",
192 "clk-icn-sbc",
193 "clk-stfe-frc2",
194 "clk-eth-phyref",
195 "clk-eth-ref-phyclk",
196 "clk-flash-promip",
197 "clk-main-disp",
198 "clk-aux-disp",
199 "clk-compo-dvp",
200 "clk-tx-icn-hades",
201 "clk-rx-icn-hades",
202 "clk-icn-reg-16",
203 "clk-pp-hevc",
204 "clk-clust-hevc",
205 "clk-hwpe-hevc",
206 "clk-fc-hevc",
207 "clk-proc-mixer",
208 "clk-proc-sc",
209 "clk-avsp-hevc";
210 };
211 };
212
213 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
214 #clock-cells = <1>;
215 compatible = "st,stih407-quadfs660-D", "st,quadfs";
216 reg = <0x9104000 0x1000>;
217
218 clocks = <&clk_sysin>;
219
220 clock-output-names = "clk-s-d0-fs0-ch0",
221 "clk-s-d0-fs0-ch1",
222 "clk-s-d0-fs0-ch2",
223 "clk-s-d0-fs0-ch3";
224 };
225
226 clockgen-d0@09104000 {
227 compatible = "st,clkgen-c32";
228 reg = <0x9104000 0x1000>;
229
230 clk_s_d0_flexgen: clk-s-d0-flexgen {
231 #clock-cells = <1>;
232 compatible = "st,flexgen";
233
234 clocks = <&clk_s_d0_quadfs 0>,
235 <&clk_s_d0_quadfs 1>,
236 <&clk_s_d0_quadfs 2>,
237 <&clk_s_d0_quadfs 3>,
238 <&clk_sysin>;
239
240 clock-output-names = "clk-pcm-0",
241 "clk-pcm-1",
242 "clk-pcm-2",
243 "clk-spdiff",
244 "clk-pcmr10-master",
245 "clk-usb2-phy";
246 };
247 };
248
249 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
250 #clock-cells = <1>;
251 compatible = "st,stih407-quadfs660-D", "st,quadfs";
252 reg = <0x9106000 0x1000>;
253
254 clocks = <&clk_sysin>;
255
256 clock-output-names = "clk-s-d2-fs0-ch0",
257 "clk-s-d2-fs0-ch1",
258 "clk-s-d2-fs0-ch2",
259 "clk-s-d2-fs0-ch3";
260 };
261
262 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
263 #clock-cells = <0>;
264 compatible = "fixed-clock";
265 clock-frequency = <0>;
266 };
267
268 clockgen-d2@x9106000 {
269 compatible = "st,clkgen-c32";
270 reg = <0x9106000 0x1000>;
271
272 clk_s_d2_flexgen: clk-s-d2-flexgen {
273 #clock-cells = <1>;
274 compatible = "st,flexgen";
275
276 clocks = <&clk_s_d2_quadfs 0>,
277 <&clk_s_d2_quadfs 1>,
278 <&clk_s_d2_quadfs 2>,
279 <&clk_s_d2_quadfs 3>,
280 <&clk_sysin>,
281 <&clk_sysin>,
282 <&clk_tmdsout_hdmi>;
283
284 clock-output-names = "clk-pix-main-disp",
285 "",
286 "",
287 "",
288 "",
289 "clk-tmds-hdmi-div2",
290 "clk-pix-aux-disp",
291 "clk-denc",
292 "clk-pix-hddac",
293 "clk-hddac",
294 "clk-sddac",
295 "clk-pix-dvo",
296 "clk-dvo",
297 "clk-pix-hdmi",
298 "clk-tmds-hdmi",
299 "clk-ref-hdmiphy",
300 "", "", "", "", "",
301 "", "", "", "", "",
302 "", "", "", "", "",
303 "", "", "", "", "",
304 "", "", "", "", "",
305 "", "", "", "", "",
306 "", "clk-vp9";
307 };
308 };
309
310 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
311 #clock-cells = <1>;
312 compatible = "st,stih407-quadfs660-D", "st,quadfs";
313 reg = <0x9107000 0x1000>;
314
315 clocks = <&clk_sysin>;
316
317 clock-output-names = "clk-s-d3-fs0-ch0",
318 "clk-s-d3-fs0-ch1",
319 "clk-s-d3-fs0-ch2",
320 "clk-s-d3-fs0-ch3";
321 };
322
323 clockgen-d3@9107000 {
324 compatible = "st,clkgen-c32";
325 reg = <0x9107000 0x1000>;
326
327 clk_s_d3_flexgen: clk-s-d3-flexgen {
328 #clock-cells = <1>;
329 compatible = "st,flexgen";
330
331 clocks = <&clk_s_d3_quadfs 0>,
332 <&clk_s_d3_quadfs 1>,
333 <&clk_s_d3_quadfs 2>,
334 <&clk_s_d3_quadfs 3>,
335 <&clk_sysin>;
336
337 clock-output-names = "clk-stfe-frc1",
338 "clk-tsout-0",
339 "clk-tsout-1",
340 "clk-mchi",
341 "clk-vsens-compo",
342 "clk-frc1-remote",
343 "clk-lpc-0",
344 "clk-lpc-1";
345 };
346 };
347 };
348};
diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi
new file mode 100644
index 000000000000..354d90f521b6
--- /dev/null
+++ b/arch/arm/boot/dts/stih418.dtsi
@@ -0,0 +1,99 @@
1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Peter Griffin <peter.griffin@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih418-clock.dtsi"
10#include "stih407-family.dtsi"
11#include "stih410-pinctrl.dtsi"
12/ {
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16 cpu@2 {
17 device_type = "cpu";
18 compatible = "arm,cortex-a9";
19 reg = <2>;
20 };
21 cpu@3 {
22 device_type = "cpu";
23 compatible = "arm,cortex-a9";
24 reg = <3>;
25 };
26 };
27
28 soc {
29 usb2_picophy1: phy2 {
30 compatible = "st,stih407-usb2-phy";
31 #phy-cells = <0>;
32 st,syscfg = <&syscfg_core 0xf8 0xf4>;
33 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
34 <&picophyreset STIH407_PICOPHY0_RESET>;
35 reset-names = "global", "port";
36 };
37
38 usb2_picophy2: phy3 {
39 compatible = "st,stih407-usb2-phy";
40 #phy-cells = <0>;
41 st,syscfg = <&syscfg_core 0xfc 0xf4>;
42 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
43 <&picophyreset STIH407_PICOPHY1_RESET>;
44 reset-names = "global", "port";
45 };
46
47 ohci0: usb@9a03c00 {
48 compatible = "st,st-ohci-300x";
49 reg = <0x9a03c00 0x100>;
50 interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
51 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
52 resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
53 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
54 reset-names = "power", "softreset";
55 phys = <&usb2_picophy1>;
56 phy-names = "usb";
57 };
58
59 ehci0: usb@9a03e00 {
60 compatible = "st,st-ehci-300x";
61 reg = <0x9a03e00 0x100>;
62 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_usb0>;
65 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
66 resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
67 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
68 reset-names = "power", "softreset";
69 phys = <&usb2_picophy1>;
70 phy-names = "usb";
71 };
72
73 ohci1: usb@9a83c00 {
74 compatible = "st,st-ohci-300x";
75 reg = <0x9a83c00 0x100>;
76 interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
77 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
78 resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
79 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
80 reset-names = "power", "softreset";
81 phys = <&usb2_picophy2>;
82 phy-names = "usb";
83 };
84
85 ehci1: usb@9a83e00 {
86 compatible = "st,st-ehci-300x";
87 reg = <0x9a83e00 0x100>;
88 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_usb1>;
91 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
92 resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
93 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
94 reset-names = "power", "softreset";
95 phys = <&usb2_picophy2>;
96 phy-names = "usb";
97 };
98 };
99};
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index 0074bd49797c..c1d859092be7 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -48,12 +48,23 @@
48 }; 48 };
49 49
50 /* SSC11 to HDMI */ 50 /* SSC11 to HDMI */
51 i2c@9541000 { 51 hdmiddc: i2c@9541000 {
52 status = "okay"; 52 status = "okay";
53 /* HDMI V1.3a supports Standard mode only */ 53 /* HDMI V1.3a supports Standard mode only */
54 clock-frequency = <100000>; 54 clock-frequency = <100000>;
55 st,i2c-min-scl-pulse-width-us = <0>; 55 st,i2c-min-scl-pulse-width-us = <0>;
56 st,i2c-min-sda-pulse-width-us = <5>; 56 st,i2c-min-sda-pulse-width-us = <5>;
57 }; 57 };
58
59 miphy28lp_phy: miphy28lp@9b22000 {
60
61 phy_port0: port@9b22000 {
62 st,osc-rdy;
63 };
64
65 phy_port1: port@9b2a000 {
66 st,osc-force-ext;
67 };
68 };
58 }; 69 };
59}; 70};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-27 13:19:17 -0500