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-rw-r--r--arch/arm/boot/dts/Makefile4
-rw-r--r--arch/arm/boot/dts/at91sam9g25.dtsi2
-rw-r--r--arch/arm/boot/dts/at91sam9g35.dtsi1
-rw-r--r--arch/arm/boot/dts/at91sam9x25.dtsi24
-rw-r--r--arch/arm/boot/dts/at91sam9x35.dtsi1
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi67
-rw-r--r--arch/arm/boot/dts/at91sam9x5_macb0.dtsi56
-rw-r--r--arch/arm/boot/dts/at91sam9x5_macb1.dtsi44
-rw-r--r--arch/arm/boot/dts/at91sam9x5_usart3.dtsi51
-rw-r--r--arch/arm/boot/dts/ecx-common.dtsi8
-rw-r--r--arch/arm/boot/dts/exynos4210-origen.dts7
-rw-r--r--arch/arm/boot/dts/exynos4210-trats.dts7
-rw-r--r--arch/arm/boot/dts/exynos4210-universal_c210.dts4
-rw-r--r--arch/arm/boot/dts/exynos5250-pinctrl.dtsi44
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi5
-rw-r--r--arch/arm/boot/dts/exynos5440-sd5v1.dts2
-rw-r--r--arch/arm/boot/dts/exynos5440-ssdk5440.dts2
-rw-r--r--arch/arm/boot/dts/imx23.dtsi1
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts4
-rw-r--r--arch/arm/boot/dts/imx28.dtsi1
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi4
-rw-r--r--arch/arm/boot/dts/integrator.dtsi5
-rw-r--r--arch/arm/boot/dts/integratorap.dts5
-rw-r--r--arch/arm/boot/dts/integratorcp.dts13
-rw-r--r--arch/arm/boot/dts/keystone-clocks.dtsi821
-rw-r--r--arch/arm/boot/dts/keystone.dts63
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts4
-rw-r--r--arch/arm/boot/dts/omap3-evm.dts2
-rw-r--r--arch/arm/boot/dts/omap3-overo.dtsi2
-rw-r--r--arch/arm/boot/dts/omap3.dtsi4
-rw-r--r--arch/arm/boot/dts/omap4.dtsi23
-rw-r--r--arch/arm/boot/dts/omap5.dtsi20
-rw-r--r--arch/arm/boot/dts/qcom-msm8660-surf.dts (renamed from arch/arm/boot/dts/msm8660-surf.dts)0
-rw-r--r--arch/arm/boot/dts/qcom-msm8960-cdp.dts (renamed from arch/arm/boot/dts/msm8960-cdp.dts)0
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi22
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi203
-rw-r--r--arch/arm/boot/dts/sama5d31.dtsi16
-rw-r--r--arch/arm/boot/dts/sama5d31ek.dts3
-rw-r--r--arch/arm/boot/dts/sama5d33.dtsi14
-rw-r--r--arch/arm/boot/dts/sama5d33ek.dts3
-rw-r--r--arch/arm/boot/dts/sama5d34.dtsi16
-rw-r--r--arch/arm/boot/dts/sama5d34ek.dts3
-rw-r--r--arch/arm/boot/dts/sama5d35.dtsi18
-rw-r--r--arch/arm/boot/dts/sama5d35ek.dts3
-rw-r--r--arch/arm/boot/dts/sama5d3_can.dtsi54
-rw-r--r--arch/arm/boot/dts/sama5d3_emac.dtsi44
-rw-r--r--arch/arm/boot/dts/sama5d3_gmac.dtsi77
-rw-r--r--arch/arm/boot/dts/sama5d3_lcd.dtsi55
-rw-r--r--arch/arm/boot/dts/sama5d3_mci2.dtsi47
-rw-r--r--arch/arm/boot/dts/sama5d3_tcb1.dtsi27
-rw-r--r--arch/arm/boot/dts/sama5d3_uart.dtsi53
-rw-r--r--arch/arm/boot/dts/sama5d3xcm.dtsi1
-rw-r--r--arch/arm/boot/dts/ste-nomadik-stn8815.dtsi12
-rw-r--r--arch/arm/boot/dts/twl4030.dtsi1
54 files changed, 1595 insertions, 378 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 6ff3139b4d8a..7662b71628cd 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -103,8 +103,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
103 kirkwood-ts219-6282.dtb \ 103 kirkwood-ts219-6282.dtb \
104 kirkwood-openblocks_a6.dtb 104 kirkwood-openblocks_a6.dtb
105dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb 105dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
106dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \ 106dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \
107 msm8960-cdp.dtb 107 qcom-msm8960-cdp.dtb
108dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ 108dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
109 armada-370-mirabox.dtb \ 109 armada-370-mirabox.dtb \
110 armada-370-netgear-rn102.dtb \ 110 armada-370-netgear-rn102.dtb \
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index b4ec6fe53fc7..17b879990914 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -7,6 +7,8 @@
7 */ 7 */
8 8
9#include "at91sam9x5.dtsi" 9#include "at91sam9x5.dtsi"
10#include "at91sam9x5_usart3.dtsi"
11#include "at91sam9x5_macb0.dtsi"
10 12
11/ { 13/ {
12 model = "Atmel AT91SAM9G25 SoC"; 14 model = "Atmel AT91SAM9G25 SoC";
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
index bebf9f55614b..e35c2fcf8298 100644
--- a/arch/arm/boot/dts/at91sam9g35.dtsi
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -7,6 +7,7 @@
7 */ 7 */
8 8
9#include "at91sam9x5.dtsi" 9#include "at91sam9x5.dtsi"
10#include "at91sam9x5_macb0.dtsi"
10 11
11/ { 12/ {
12 model = "Atmel AT91SAM9G35 SoC"; 13 model = "Atmel AT91SAM9G35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index 49e94aba938f..c2554219f7a4 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -7,6 +7,9 @@
7 */ 7 */
8 8
9#include "at91sam9x5.dtsi" 9#include "at91sam9x5.dtsi"
10#include "at91sam9x5_usart3.dtsi"
11#include "at91sam9x5_macb0.dtsi"
12#include "at91sam9x5_macb1.dtsi"
10 13
11/ { 14/ {
12 model = "Atmel AT91SAM9X25 SoC"; 15 model = "Atmel AT91SAM9X25 SoC";
@@ -22,27 +25,6 @@
22 0x80000000 0xfffd0000 0xb83fffff /* pioC */ 25 0x80000000 0xfffd0000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */ 26 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >; 27 >;
25
26 macb1 {
27 pinctrl_macb1_rmii: macb1_rmii-0 {
28 atmel,pins =
29 <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */
30 AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */
31 AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */
32 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
33 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
34 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
35 AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */
36 AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */
37 AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */
38 AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
39 };
40 };
41 };
42
43 macb1: ethernet@f8030000 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_macb1_rmii>;
46 }; 28 };
47 }; 29 };
48 }; 30 };
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index 1a3d525a1f5d..8eac66ce0ab7 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -7,6 +7,7 @@
7 */ 7 */
8 8
9#include "at91sam9x5.dtsi" 9#include "at91sam9x5.dtsi"
10#include "at91sam9x5_macb0.dtsi"
10 11
11/ { 12/ {
12 model = "Atmel AT91SAM9X35 SoC"; 13 model = "Atmel AT91SAM9X35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index e74dc15efa9d..40267a116c3c 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -206,29 +206,6 @@
206 }; 206 };
207 }; 207 };
208 208
209 usart3 {
210 pinctrl_usart3: usart3-0 {
211 atmel,pins =
212 <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
213 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
214 };
215
216 pinctrl_usart3_rts: usart3_rts-0 {
217 atmel,pins =
218 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
219 };
220
221 pinctrl_usart3_cts: usart3_cts-0 {
222 atmel,pins =
223 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
224 };
225
226 pinctrl_usart3_sck: usart3_sck-0 {
227 atmel,pins =
228 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
229 };
230 };
231
232 uart0 { 209 uart0 {
233 pinctrl_uart0: uart0-0 { 210 pinctrl_uart0: uart0-0 {
234 atmel,pins = 211 atmel,pins =
@@ -277,34 +254,6 @@
277 }; 254 };
278 }; 255 };
279 256
280 macb0 {
281 pinctrl_macb0_rmii: macb0_rmii-0 {
282 atmel,pins =
283 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
284 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
285 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
286 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
287 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
288 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
289 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
290 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
291 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
292 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
293 };
294
295 pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
296 atmel,pins =
297 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */
298 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */
299 AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
300 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
301 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
302 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
303 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
304 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
305 };
306 };
307
308 mmc0 { 257 mmc0 {
309 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { 258 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
310 atmel,pins = 259 atmel,pins =
@@ -610,22 +559,6 @@
610 status = "disabled"; 559 status = "disabled";
611 }; 560 };
612 561
613 macb0: ethernet@f802c000 {
614 compatible = "cdns,at32ap7000-macb", "cdns,macb";
615 reg = <0xf802c000 0x100>;
616 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
617 pinctrl-names = "default";
618 pinctrl-0 = <&pinctrl_macb0_rmii>;
619 status = "disabled";
620 };
621
622 macb1: ethernet@f8030000 {
623 compatible = "cdns,at32ap7000-macb", "cdns,macb";
624 reg = <0xf8030000 0x100>;
625 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
626 status = "disabled";
627 };
628
629 i2c0: i2c@f8010000 { 562 i2c0: i2c@f8010000 {
630 compatible = "atmel,at91sam9x5-i2c"; 563 compatible = "atmel,at91sam9x5-i2c";
631 reg = <0xf8010000 0x100>; 564 reg = <0xf8010000 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
new file mode 100644
index 000000000000..55731ffba764
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
@@ -0,0 +1,56 @@
1/*
2 * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
3 * Ethernet interface.
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 ahb {
15 apb {
16 pinctrl@fffff400 {
17 macb0 {
18 pinctrl_macb0_rmii: macb0_rmii-0 {
19 atmel,pins =
20 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
21 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
22 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
23 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
24 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
25 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
26 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
27 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
28 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
29 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
30 };
31
32 pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
33 atmel,pins =
34 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */
35 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */
36 AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
37 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
38 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
39 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
40 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
41 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
42 };
43 };
44 };
45
46 macb0: ethernet@f802c000 {
47 compatible = "cdns,at32ap7000-macb", "cdns,macb";
48 reg = <0xf802c000 0x100>;
49 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_macb0_rmii>;
52 status = "disabled";
53 };
54 };
55 };
56};
diff --git a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
new file mode 100644
index 000000000000..77425a627a94
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
@@ -0,0 +1,44 @@
1/*
2 * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2
3 * Ethernet interfaces.
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 ahb {
15 apb {
16 pinctrl@fffff400 {
17 macb1 {
18 pinctrl_macb1_rmii: macb1_rmii-0 {
19 atmel,pins =
20 <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */
21 AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */
22 AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */
23 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
24 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
25 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
26 AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */
27 AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */
28 AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */
29 AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
30 };
31 };
32 };
33
34 macb1: ethernet@f8030000 {
35 compatible = "cdns,at32ap7000-macb", "cdns,macb";
36 reg = <0xf8030000 0x100>;
37 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_macb1_rmii>;
40 status = "disabled";
41 };
42 };
43 };
44};
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
new file mode 100644
index 000000000000..2347e9563cef
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
@@ -0,0 +1,51 @@
1/*
2 * at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
3 * 4 USART.
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 ahb {
15 apb {
16 pinctrl@fffff400 {
17 usart3 {
18 pinctrl_usart3: usart3-0 {
19 atmel,pins =
20 <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
21 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
22 };
23
24 pinctrl_usart3_rts: usart3_rts-0 {
25 atmel,pins =
26 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
27 };
28
29 pinctrl_usart3_cts: usart3_cts-0 {
30 atmel,pins =
31 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
32 };
33
34 pinctrl_usart3_sck: usart3_sck-0 {
35 atmel,pins =
36 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
37 };
38 };
39 };
40
41 usart3: serial@f8028000 {
42 compatible = "atmel,at91sam9260-usart";
43 reg = <0xf8028000 0x200>;
44 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_usart3>;
47 status = "disabled";
48 };
49 };
50 };
51};
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
index e8559b753c9d..bc22557d7a6a 100644
--- a/arch/arm/boot/dts/ecx-common.dtsi
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -19,6 +19,14 @@
19 bootargs = "console=ttyAMA0"; 19 bootargs = "console=ttyAMA0";
20 }; 20 };
21 21
22 psci {
23 compatible = "arm,psci";
24 method = "smc";
25 cpu_suspend = <0x84000002>;
26 cpu_off = <0x84000004>;
27 cpu_on = <0x84000006>;
28 };
29
22 soc { 30 soc {
23 #address-cells = <1>; 31 #address-cells = <1>;
24 #size-cells = <1>; 32 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 382d8c7e2906..46378fee2a13 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -192,7 +192,12 @@
192 }; 192 };
193 193
194 buck1_reg: BUCK1 { 194 buck1_reg: BUCK1 {
195 regulator-name = "VDD_ARM_1.2V"; 195 /*
196 * HACK: The real name is VDD_ARM_1.2V,
197 * but exynos-cpufreq does not support
198 * DT-based regulator lookup yet.
199 */
200 regulator-name = "vdd_arm";
196 regulator-min-microvolt = <950000>; 201 regulator-min-microvolt = <950000>;
197 regulator-max-microvolt = <1350000>; 202 regulator-max-microvolt = <1350000>;
198 regulator-always-on; 203 regulator-always-on;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 1c164f234bcc..63cc571ca307 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -290,7 +290,12 @@
290 }; 290 };
291 291
292 varm_breg: BUCK1 { 292 varm_breg: BUCK1 {
293 regulator-name = "VARM_1.2V_C210"; 293 /*
294 * HACK: The real name is VARM_1.2V_C210,
295 * but exynos-cpufreq does not support
296 * DT-based regulator lookup yet.
297 */
298 regulator-name = "vdd_arm";
294 regulator-min-microvolt = <900000>; 299 regulator-min-microvolt = <900000>;
295 regulator-max-microvolt = <1350000>; 300 regulator-max-microvolt = <1350000>;
296 regulator-always-on; 301 regulator-always-on;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 889cdada1ce9..d2e3f5f5916d 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -350,3 +350,7 @@
350 status = "okay"; 350 status = "okay";
351 }; 351 };
352}; 352};
353
354&mdma1 {
355 reg = <0x12840000 0x1000>;
356};
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index 724a22f9b1c8..9a49e6804ae1 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -210,21 +210,21 @@
210 samsung,pins = "gpa0-2", "gpa0-3"; 210 samsung,pins = "gpa0-2", "gpa0-3";
211 samsung,pin-function = <2>; 211 samsung,pin-function = <2>;
212 samsung,pin-pud = <0>; 212 samsung,pin-pud = <0>;
213 samaung,pin-drv = <0>; 213 samsung,pin-drv = <0>;
214 }; 214 };
215 215
216 i2c2_bus: i2c2-bus { 216 i2c2_bus: i2c2-bus {
217 samsung,pins = "gpa0-6", "gpa0-7"; 217 samsung,pins = "gpa0-6", "gpa0-7";
218 samsung,pin-function = <3>; 218 samsung,pin-function = <3>;
219 samsung,pin-pud = <3>; 219 samsung,pin-pud = <3>;
220 samaung,pin-drv = <0>; 220 samsung,pin-drv = <0>;
221 }; 221 };
222 222
223 i2c2_hs_bus: i2c2-hs-bus { 223 i2c2_hs_bus: i2c2-hs-bus {
224 samsung,pins = "gpa0-6", "gpa0-7"; 224 samsung,pins = "gpa0-6", "gpa0-7";
225 samsung,pin-function = <4>; 225 samsung,pin-function = <4>;
226 samsung,pin-pud = <3>; 226 samsung,pin-pud = <3>;
227 samaung,pin-drv = <0>; 227 samsung,pin-drv = <0>;
228 }; 228 };
229 229
230 uart2_data: uart2-data { 230 uart2_data: uart2-data {
@@ -238,21 +238,21 @@
238 samsung,pins = "gpa1-2", "gpa1-3"; 238 samsung,pins = "gpa1-2", "gpa1-3";
239 samsung,pin-function = <2>; 239 samsung,pin-function = <2>;
240 samsung,pin-pud = <0>; 240 samsung,pin-pud = <0>;
241 samaung,pin-drv = <0>; 241 samsung,pin-drv = <0>;
242 }; 242 };
243 243
244 i2c3_bus: i2c3-bus { 244 i2c3_bus: i2c3-bus {
245 samsung,pins = "gpa1-2", "gpa1-3"; 245 samsung,pins = "gpa1-2", "gpa1-3";
246 samsung,pin-function = <3>; 246 samsung,pin-function = <3>;
247 samsung,pin-pud = <3>; 247 samsung,pin-pud = <3>;
248 samaung,pin-drv = <0>; 248 samsung,pin-drv = <0>;
249 }; 249 };
250 250
251 i2c3_hs_bus: i2c3-hs-bus { 251 i2c3_hs_bus: i2c3-hs-bus {
252 samsung,pins = "gpa1-2", "gpa1-3"; 252 samsung,pins = "gpa1-2", "gpa1-3";
253 samsung,pin-function = <4>; 253 samsung,pin-function = <4>;
254 samsung,pin-pud = <3>; 254 samsung,pin-pud = <3>;
255 samaung,pin-drv = <0>; 255 samsung,pin-drv = <0>;
256 }; 256 };
257 257
258 uart3_data: uart3-data { 258 uart3_data: uart3-data {
@@ -273,14 +273,14 @@
273 samsung,pins = "gpa2-0", "gpa2-1"; 273 samsung,pins = "gpa2-0", "gpa2-1";
274 samsung,pin-function = <3>; 274 samsung,pin-function = <3>;
275 samsung,pin-pud = <3>; 275 samsung,pin-pud = <3>;
276 samaung,pin-drv = <0>; 276 samsung,pin-drv = <0>;
277 }; 277 };
278 278
279 i2c5_bus: i2c5-bus { 279 i2c5_bus: i2c5-bus {
280 samsung,pins = "gpa2-2", "gpa2-3"; 280 samsung,pins = "gpa2-2", "gpa2-3";
281 samsung,pin-function = <3>; 281 samsung,pin-function = <3>;
282 samsung,pin-pud = <3>; 282 samsung,pin-pud = <3>;
283 samaung,pin-drv = <0>; 283 samsung,pin-drv = <0>;
284 }; 284 };
285 285
286 spi1_bus: spi1-bus { 286 spi1_bus: spi1-bus {
@@ -376,14 +376,14 @@
376 samsung,pins = "gpb3-0", "gpb3-1"; 376 samsung,pins = "gpb3-0", "gpb3-1";
377 samsung,pin-function = <4>; 377 samsung,pin-function = <4>;
378 samsung,pin-pud = <3>; 378 samsung,pin-pud = <3>;
379 samaung,pin-drv = <0>; 379 samsung,pin-drv = <0>;
380 }; 380 };
381 381
382 i2c1_hs_bus: i2c1-hs-bus { 382 i2c1_hs_bus: i2c1-hs-bus {
383 samsung,pins = "gpb3-2", "gpb3-3"; 383 samsung,pins = "gpb3-2", "gpb3-3";
384 samsung,pin-function = <4>; 384 samsung,pin-function = <4>;
385 samsung,pin-pud = <3>; 385 samsung,pin-pud = <3>;
386 samaung,pin-drv = <0>; 386 samsung,pin-drv = <0>;
387 }; 387 };
388 388
389 sd0_clk: sd0-clk { 389 sd0_clk: sd0-clk {
@@ -551,14 +551,14 @@
551 samsung,pins = "gpd0-2", "gpd0-3"; 551 samsung,pins = "gpd0-2", "gpd0-3";
552 samsung,pin-function = <2>; 552 samsung,pin-function = <2>;
553 samsung,pin-pud = <0>; 553 samsung,pin-pud = <0>;
554 samaung,pin-drv = <0>; 554 samsung,pin-drv = <0>;
555 }; 555 };
556 556
557 dp_hpd: dp_hpd { 557 dp_hpd: dp_hpd {
558 samsung,pins = "gpx0-7"; 558 samsung,pins = "gpx0-7";
559 samsung,pin-function = <3>; 559 samsung,pin-function = <3>;
560 samsung,pin-pud = <0>; 560 samsung,pin-pud = <0>;
561 samaung,pin-drv = <0>; 561 samsung,pin-drv = <0>;
562 }; 562 };
563 }; 563 };
564 564
@@ -649,42 +649,42 @@
649 "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; 649 "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
650 samsung,pin-function = <3>; 650 samsung,pin-function = <3>;
651 samsung,pin-pud = <0>; 651 samsung,pin-pud = <0>;
652 samaung,pin-drv = <0>; 652 samsung,pin-drv = <0>;
653 }; 653 };
654 654
655 cam_i2c2_bus: cam-i2c2-bus { 655 cam_i2c2_bus: cam-i2c2-bus {
656 samsung,pins = "gpe0-6", "gpe1-0"; 656 samsung,pins = "gpe0-6", "gpe1-0";
657 samsung,pin-function = <4>; 657 samsung,pin-function = <4>;
658 samsung,pin-pud = <3>; 658 samsung,pin-pud = <3>;
659 samaung,pin-drv = <0>; 659 samsung,pin-drv = <0>;
660 }; 660 };
661 661
662 cam_spi1_bus: cam-spi1-bus { 662 cam_spi1_bus: cam-spi1-bus {
663 samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; 663 samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3";
664 samsung,pin-function = <4>; 664 samsung,pin-function = <4>;
665 samsung,pin-pud = <0>; 665 samsung,pin-pud = <0>;
666 samaung,pin-drv = <0>; 666 samsung,pin-drv = <0>;
667 }; 667 };
668 668
669 cam_i2c1_bus: cam-i2c1-bus { 669 cam_i2c1_bus: cam-i2c1-bus {
670 samsung,pins = "gpf0-2", "gpf0-3"; 670 samsung,pins = "gpf0-2", "gpf0-3";
671 samsung,pin-function = <2>; 671 samsung,pin-function = <2>;
672 samsung,pin-pud = <3>; 672 samsung,pin-pud = <3>;
673 samaung,pin-drv = <0>; 673 samsung,pin-drv = <0>;
674 }; 674 };
675 675
676 cam_i2c0_bus: cam-i2c0-bus { 676 cam_i2c0_bus: cam-i2c0-bus {
677 samsung,pins = "gpf0-0", "gpf0-1"; 677 samsung,pins = "gpf0-0", "gpf0-1";
678 samsung,pin-function = <2>; 678 samsung,pin-function = <2>;
679 samsung,pin-pud = <3>; 679 samsung,pin-pud = <3>;
680 samaung,pin-drv = <0>; 680 samsung,pin-drv = <0>;
681 }; 681 };
682 682
683 cam_spi0_bus: cam-spi0-bus { 683 cam_spi0_bus: cam-spi0-bus {
684 samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; 684 samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
685 samsung,pin-function = <2>; 685 samsung,pin-function = <2>;
686 samsung,pin-pud = <0>; 686 samsung,pin-pud = <0>;
687 samaung,pin-drv = <0>; 687 samsung,pin-drv = <0>;
688 }; 688 };
689 689
690 cam_bayrgb_bus: cam-bayrgb-bus { 690 cam_bayrgb_bus: cam-bayrgb-bus {
@@ -695,7 +695,7 @@
695 "gpg2-0", "gpg2-1"; 695 "gpg2-0", "gpg2-1";
696 samsung,pin-function = <2>; 696 samsung,pin-function = <2>;
697 samsung,pin-pud = <0>; 697 samsung,pin-pud = <0>;
698 samaung,pin-drv = <0>; 698 samsung,pin-drv = <0>;
699 }; 699 };
700 700
701 cam_port_a: cam-port-a { 701 cam_port_a: cam-port-a {
@@ -704,7 +704,7 @@
704 "gph1-4", "gph1-5", "gph1-6", "gph1-7"; 704 "gph1-4", "gph1-5", "gph1-6", "gph1-7";
705 samsung,pin-function = <2>; 705 samsung,pin-function = <2>;
706 samsung,pin-pud = <0>; 706 samsung,pin-pud = <0>;
707 samaung,pin-drv = <0>; 707 samsung,pin-drv = <0>;
708 }; 708 };
709 }; 709 };
710 710
@@ -756,7 +756,7 @@
756 "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7"; 756 "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7";
757 samsung,pin-function = <2>; 757 samsung,pin-function = <2>;
758 samsung,pin-pud = <0>; 758 samsung,pin-pud = <0>;
759 samaung,pin-drv = <0>; 759 samsung,pin-drv = <0>;
760 }; 760 };
761 761
762 c2c_txd: c2c-txd { 762 c2c_txd: c2c-txd {
@@ -766,7 +766,7 @@
766 "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7"; 766 "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7";
767 samsung,pin-function = <2>; 767 samsung,pin-function = <2>;
768 samsung,pin-pud = <0>; 768 samsung,pin-pud = <0>;
769 samaung,pin-drv = <0>; 769 samsung,pin-drv = <0>;
770 }; 770 };
771 }; 771 };
772 772
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 7d7cc777ff7b..bbac42a78ce5 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -96,6 +96,11 @@
96 <1 14 0xf08>, 96 <1 14 0xf08>,
97 <1 11 0xf08>, 97 <1 11 0xf08>,
98 <1 10 0xf08>; 98 <1 10 0xf08>;
99 /* Unfortunately we need this since some versions of U-Boot
100 * on Exynos don't set the CNTFRQ register, so we need the
101 * value from DT.
102 */
103 clock-frequency = <24000000>;
99 }; 104 };
100 105
101 mct@101C0000 { 106 mct@101C0000 {
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts
index 5b22508050da..777fb1c2c70f 100644
--- a/arch/arm/boot/dts/exynos5440-sd5v1.dts
+++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts
@@ -17,7 +17,7 @@
17 compatible = "samsung,sd5v1", "samsung,exynos5440"; 17 compatible = "samsung,sd5v1", "samsung,exynos5440";
18 18
19 chosen { 19 chosen {
20 bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; 20 bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
21 }; 21 };
22 22
23 fixed-rate-clocks { 23 fixed-rate-clocks {
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index ede772741f81..a7cb84884cfb 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -17,7 +17,7 @@
17 compatible = "samsung,ssdk5440", "samsung,exynos5440"; 17 compatible = "samsung,ssdk5440", "samsung,exynos5440";
18 18
19 chosen { 19 chosen {
20 bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; 20 bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
21 }; 21 };
22 22
23 spi_0: spi@D0000 { 23 spi_0: spi@D0000 {
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 28b5ce289662..07caf767d428 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -430,6 +430,7 @@
430 reg = <0x80050000 0x2000>; 430 reg = <0x80050000 0x2000>;
431 interrupts = <36 37 38 39 40 41 42 43 44>; 431 interrupts = <36 37 38 39 40 41 42 43 44>;
432 status = "disabled"; 432 status = "disabled";
433 clocks = <&clks 26>;
433 }; 434 };
434 435
435 spdif@80054000 { 436 spdif@80054000 {
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 15715d921d14..aa33393903a8 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -183,6 +183,10 @@
183 183
184 lradc@80050000 { 184 lradc@80050000 {
185 status = "okay"; 185 status = "okay";
186 fsl,lradc-touchscreen-wires = <4>;
187 fsl,ave-ctrl = <4>;
188 fsl,ave-delay = <2>;
189 fsl,settling = <10>;
186 }; 190 };
187 191
188 i2c0: i2c@80058000 { 192 i2c0: i2c@80058000 {
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 7363fded95ee..175deefb048b 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -902,6 +902,7 @@
902 interrupts = <10 14 15 16 17 18 19 902 interrupts = <10 14 15 16 17 18 19
903 20 21 22 23 24 25>; 903 20 21 22 23 24 25>;
904 status = "disabled"; 904 status = "disabled";
905 clocks = <&clks 41>;
905 }; 906 };
906 907
907 spdif: spdif@80054000 { 908 spdif: spdif@80054000 {
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c46651e4d966..177d9e791a01 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -380,7 +380,9 @@
380 }; 380 };
381 381
382 anatop: anatop@020c8000 { 382 anatop: anatop@020c8000 {
383 compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus"; 383 compatible = "fsl,imx6sl-anatop",
384 "fsl,imx6q-anatop",
385 "syscon", "simple-bus";
384 reg = <0x020c8000 0x1000>; 386 reg = <0x020c8000 0x1000>;
385 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; 387 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
386 388
diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi
index 813b91d7bea2..0f06f8687b0b 100644
--- a/arch/arm/boot/dts/integrator.dtsi
+++ b/arch/arm/boot/dts/integrator.dtsi
@@ -5,6 +5,11 @@
5/include/ "skeleton.dtsi" 5/include/ "skeleton.dtsi"
6 6
7/ { 7/ {
8 core-module@10000000 {
9 compatible = "arm,core-module-integrator";
10 reg = <0x10000000 0x200>;
11 };
12
8 timer@13000000 { 13 timer@13000000 {
9 reg = <0x13000000 0x100>; 14 reg = <0x13000000 0x100>;
10 interrupt-parent = <&pic>; 15 interrupt-parent = <&pic>;
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index b6b82eca8d1e..e6be9315ff0a 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -19,8 +19,11 @@
19 }; 19 };
20 20
21 syscon { 21 syscon {
22 /* AP system controller registers */ 22 compatible = "arm,integrator-ap-syscon";
23 reg = <0x11000000 0x100>; 23 reg = <0x11000000 0x100>;
24 interrupt-parent = <&pic>;
25 /* These are the logical module IRQs */
26 interrupts = <9>, <10>, <11>, <12>;
24 }; 27 };
25 28
26 timer0: timer@13000000 { 29 timer0: timer@13000000 {
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index ff1aea0ee043..7deb3a3182b4 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -9,29 +9,28 @@
9 model = "ARM Integrator/CP"; 9 model = "ARM Integrator/CP";
10 compatible = "arm,integrator-cp"; 10 compatible = "arm,integrator-cp";
11 11
12 aliases {
13 arm,timer-primary = &timer2;
14 arm,timer-secondary = &timer1;
15 };
16
17 chosen { 12 chosen {
18 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; 13 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
19 }; 14 };
20 15
21 cpcon { 16 syscon {
22 /* CP controller registers */ 17 compatible = "arm,integrator-cp-syscon";
23 reg = <0xcb000000 0x100>; 18 reg = <0xcb000000 0x100>;
24 }; 19 };
25 20
26 timer0: timer@13000000 { 21 timer0: timer@13000000 {
22 /* TIMER0 runs @ 25MHz */
27 compatible = "arm,integrator-cp-timer"; 23 compatible = "arm,integrator-cp-timer";
24 status = "disabled";
28 }; 25 };
29 26
30 timer1: timer@13000100 { 27 timer1: timer@13000100 {
28 /* TIMER1 runs @ 1MHz */
31 compatible = "arm,integrator-cp-timer"; 29 compatible = "arm,integrator-cp-timer";
32 }; 30 };
33 31
34 timer2: timer@13000200 { 32 timer2: timer@13000200 {
33 /* TIMER2 runs @ 1MHz */
35 compatible = "arm,integrator-cp-timer"; 34 compatible = "arm,integrator-cp-timer";
36 }; 35 };
37 36
diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi
new file mode 100644
index 000000000000..d6713b113258
--- /dev/null
+++ b/arch/arm/boot/dts/keystone-clocks.dtsi
@@ -0,0 +1,821 @@
1/*
2 * Device Tree Source for Keystone 2 clock tree
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11clocks {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges;
15
16 refclkmain: refclkmain {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <122880000>;
20 clock-output-names = "refclk-main";
21 };
22
23 mainpllclk: mainpllclk@2310110 {
24 #clock-cells = <0>;
25 compatible = "ti,keystone,main-pll-clock";
26 clocks = <&refclkmain>;
27 reg = <0x02620350 4>, <0x02310110 4>;
28 reg-names = "control", "multiplier";
29 fixed-postdiv = <2>;
30 };
31
32 papllclk: papllclk@2620358 {
33 #clock-cells = <0>;
34 compatible = "ti,keystone,pll-clock";
35 clocks = <&refclkmain>;
36 clock-output-names = "pa-pll-clk";
37 reg = <0x02620358 4>;
38 reg-names = "control";
39 fixed-postdiv = <6>;
40 };
41
42 ddr3allclk: ddr3apllclk@2620360 {
43 #clock-cells = <0>;
44 compatible = "ti,keystone,pll-clock";
45 clocks = <&refclkmain>;
46 clock-output-names = "ddr-3a-pll-clk";
47 reg = <0x02620360 4>;
48 reg-names = "control";
49 fixed-postdiv = <6>;
50 };
51
52 ddr3bllclk: ddr3bpllclk@2620368 {
53 #clock-cells = <0>;
54 compatible = "ti,keystone,pll-clock";
55 clocks = <&refclkmain>;
56 clock-output-names = "ddr-3b-pll-clk";
57 reg = <0x02620368 4>;
58 reg-names = "control";
59 fixed-postdiv = <6>;
60 };
61
62 armpllclk: armpllclk@2620370 {
63 #clock-cells = <0>;
64 compatible = "ti,keystone,pll-clock";
65 clocks = <&refclkmain>;
66 clock-output-names = "arm-pll-clk";
67 reg = <0x02620370 4>;
68 reg-names = "control";
69 fixed-postdiv = <6>;
70 };
71
72 mainmuxclk: mainmuxclk@2310108 {
73 #clock-cells = <0>;
74 compatible = "ti,keystone,pll-mux-clock";
75 clocks = <&mainpllclk>, <&refclkmain>;
76 reg = <0x02310108 4>;
77 bit-shift = <23>;
78 bit-mask = <1>;
79 clock-output-names = "mainmuxclk";
80 };
81
82 chipclk1: chipclk1 {
83 #clock-cells = <0>;
84 compatible = "fixed-factor-clock";
85 clocks = <&mainmuxclk>;
86 clock-div = <1>;
87 clock-mult = <1>;
88 clock-output-names = "chipclk1";
89 };
90
91 chipclk1rstiso: chipclk1rstiso {
92 #clock-cells = <0>;
93 compatible = "fixed-factor-clock";
94 clocks = <&mainmuxclk>;
95 clock-div = <1>;
96 clock-mult = <1>;
97 clock-output-names = "chipclk1rstiso";
98 };
99
100 gemtraceclk: gemtraceclk@2310120 {
101 #clock-cells = <0>;
102 compatible = "ti,keystone,pll-divider-clock";
103 clocks = <&mainmuxclk>;
104 reg = <0x02310120 4>;
105 bit-shift = <0>;
106 bit-mask = <8>;
107 clock-output-names = "gemtraceclk";
108 };
109
110 chipstmxptclk: chipstmxptclk {
111 #clock-cells = <0>;
112 compatible = "ti,keystone,pll-divider-clock";
113 clocks = <&mainmuxclk>;
114 reg = <0x02310164 4>;
115 bit-shift = <0>;
116 bit-mask = <8>;
117 clock-output-names = "chipstmxptclk";
118 };
119
120 chipclk12: chipclk12 {
121 #clock-cells = <0>;
122 compatible = "fixed-factor-clock";
123 clocks = <&chipclk1>;
124 clock-div = <2>;
125 clock-mult = <1>;
126 clock-output-names = "chipclk12";
127 };
128
129 chipclk13: chipclk13 {
130 #clock-cells = <0>;
131 compatible = "fixed-factor-clock";
132 clocks = <&chipclk1>;
133 clock-div = <3>;
134 clock-mult = <1>;
135 clock-output-names = "chipclk13";
136 };
137
138 chipclk14: chipclk14 {
139 #clock-cells = <0>;
140 compatible = "fixed-factor-clock";
141 clocks = <&chipclk1>;
142 clock-div = <4>;
143 clock-mult = <1>;
144 clock-output-names = "chipclk14";
145 };
146
147 chipclk16: chipclk16 {
148 #clock-cells = <0>;
149 compatible = "fixed-factor-clock";
150 clocks = <&chipclk1>;
151 clock-div = <6>;
152 clock-mult = <1>;
153 clock-output-names = "chipclk16";
154 };
155
156 chipclk112: chipclk112 {
157 #clock-cells = <0>;
158 compatible = "fixed-factor-clock";
159 clocks = <&chipclk1>;
160 clock-div = <12>;
161 clock-mult = <1>;
162 clock-output-names = "chipclk112";
163 };
164
165 chipclk124: chipclk124 {
166 #clock-cells = <0>;
167 compatible = "fixed-factor-clock";
168 clocks = <&chipclk1>;
169 clock-div = <24>;
170 clock-mult = <1>;
171 clock-output-names = "chipclk114";
172 };
173
174 chipclk1rstiso13: chipclk1rstiso13 {
175 #clock-cells = <0>;
176 compatible = "fixed-factor-clock";
177 clocks = <&chipclk1rstiso>;
178 clock-div = <3>;
179 clock-mult = <1>;
180 clock-output-names = "chipclk1rstiso13";
181 };
182
183 chipclk1rstiso14: chipclk1rstiso14 {
184 #clock-cells = <0>;
185 compatible = "fixed-factor-clock";
186 clocks = <&chipclk1rstiso>;
187 clock-div = <4>;
188 clock-mult = <1>;
189 clock-output-names = "chipclk1rstiso14";
190 };
191
192 chipclk1rstiso16: chipclk1rstiso16 {
193 #clock-cells = <0>;
194 compatible = "fixed-factor-clock";
195 clocks = <&chipclk1rstiso>;
196 clock-div = <6>;
197 clock-mult = <1>;
198 clock-output-names = "chipclk1rstiso16";
199 };
200
201 chipclk1rstiso112: chipclk1rstiso112 {
202 #clock-cells = <0>;
203 compatible = "fixed-factor-clock";
204 clocks = <&chipclk1rstiso>;
205 clock-div = <12>;
206 clock-mult = <1>;
207 clock-output-names = "chipclk1rstiso112";
208 };
209
210 clkmodrst0: clkmodrst0 {
211 #clock-cells = <0>;
212 compatible = "ti,keystone,psc-clock";
213 clocks = <&chipclk16>;
214 clock-output-names = "modrst0";
215 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
216 reg-names = "control", "domain";
217 domain-id = <0>;
218 };
219
220
221 clkusb: clkusb {
222 #clock-cells = <0>;
223 compatible = "ti,keystone,psc-clock";
224 clocks = <&chipclk16>;
225 clock-output-names = "usb";
226 reg = <0x02350008 0xb00>, <0x02350000 0x400>;
227 reg-names = "control", "domain";
228 domain-id = <0>;
229 };
230
231 clkaemifspi: clkaemifspi {
232 #clock-cells = <0>;
233 compatible = "ti,keystone,psc-clock";
234 clocks = <&chipclk16>;
235 clock-output-names = "aemif-spi";
236 reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
237 reg-names = "control", "domain";
238 domain-id = <0>;
239 };
240
241
242 clkdebugsstrc: clkdebugsstrc {
243 #clock-cells = <0>;
244 compatible = "ti,keystone,psc-clock";
245 clocks = <&chipclk13>;
246 clock-output-names = "debugss-trc";
247 reg = <0x02350014 0xb00>, <0x02350000 0x400>;
248 reg-names = "control", "domain";
249 domain-id = <0>;
250 };
251
252 clktetbtrc: clktetbtrc {
253 #clock-cells = <0>;
254 compatible = "ti,keystone,psc-clock";
255 clocks = <&chipclk13>;
256 clock-output-names = "tetb-trc";
257 reg = <0x02350018 0xb00>, <0x02350004 0x400>;
258 reg-names = "control", "domain";
259 domain-id = <1>;
260 };
261
262 clkpa: clkpa {
263 #clock-cells = <0>;
264 compatible = "ti,keystone,psc-clock";
265 clocks = <&chipclk16>;
266 clock-output-names = "pa";
267 reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
268 reg-names = "control", "domain";
269 domain-id = <2>;
270 };
271
272 clkcpgmac: clkcpgmac {
273 #clock-cells = <0>;
274 compatible = "ti,keystone,psc-clock";
275 clocks = <&clkpa>;
276 clock-output-names = "cpgmac";
277 reg = <0x02350020 0xb00>, <0x02350008 0x400>;
278 reg-names = "control", "domain";
279 domain-id = <2>;
280 };
281
282 clksa: clksa {
283 #clock-cells = <0>;
284 compatible = "ti,keystone,psc-clock";
285 clocks = <&clkpa>;
286 clock-output-names = "sa";
287 reg = <0x02350024 0xb00>, <0x02350008 0x400>;
288 reg-names = "control", "domain";
289 domain-id = <2>;
290 };
291
292 clkpcie: clkpcie {
293 #clock-cells = <0>;
294 compatible = "ti,keystone,psc-clock";
295 clocks = <&chipclk12>;
296 clock-output-names = "pcie";
297 reg = <0x02350028 0xb00>, <0x0235000c 0x400>;
298 reg-names = "control", "domain";
299 domain-id = <3>;
300 };
301
302 clksrio: clksrio {
303 #clock-cells = <0>;
304 compatible = "ti,keystone,psc-clock";
305 clocks = <&chipclk1rstiso13>;
306 clock-output-names = "srio";
307 reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
308 reg-names = "control", "domain";
309 domain-id = <4>;
310 };
311
312 clkhyperlink0: clkhyperlink0 {
313 #clock-cells = <0>;
314 compatible = "ti,keystone,psc-clock";
315 clocks = <&chipclk12>;
316 clock-output-names = "hyperlink-0";
317 reg = <0x02350030 0xb00>, <0x02350014 0x400>;
318 reg-names = "control", "domain";
319 domain-id = <5>;
320 };
321
322 clksr: clksr {
323 #clock-cells = <0>;
324 compatible = "ti,keystone,psc-clock";
325 clocks = <&chipclk1rstiso112>;
326 clock-output-names = "sr";
327 reg = <0x02350034 0xb00>, <0x02350018 0x400>;
328 reg-names = "control", "domain";
329 domain-id = <6>;
330 };
331
332 clkmsmcsram: clkmsmcsram {
333 #clock-cells = <0>;
334 compatible = "ti,keystone,psc-clock";
335 clocks = <&chipclk1>;
336 clock-output-names = "msmcsram";
337 reg = <0x02350038 0xb00>, <0x0235001c 0x400>;
338 reg-names = "control", "domain";
339 domain-id = <7>;
340 };
341
342 clkgem0: clkgem0 {
343 #clock-cells = <0>;
344 compatible = "ti,keystone,psc-clock";
345 clocks = <&chipclk1>;
346 clock-output-names = "gem0";
347 reg = <0x0235003c 0xb00>, <0x02350020 0x400>;
348 reg-names = "control", "domain";
349 domain-id = <8>;
350 };
351
352 clkgem1: clkgem1 {
353 #clock-cells = <0>;
354 compatible = "ti,keystone,psc-clock";
355 clocks = <&chipclk1>;
356 clock-output-names = "gem1";
357 reg = <0x02350040 0xb00>, <0x02350024 0x400>;
358 reg-names = "control", "domain";
359 domain-id = <9>;
360 };
361
362 clkgem2: clkgem2 {
363 #clock-cells = <0>;
364 compatible = "ti,keystone,psc-clock";
365 clocks = <&chipclk1>;
366 clock-output-names = "gem2";
367 reg = <0x02350044 0xb00>, <0x02350028 0x400>;
368 reg-names = "control", "domain";
369 domain-id = <10>;
370 };
371
372 clkgem3: clkgem3 {
373 #clock-cells = <0>;
374 compatible = "ti,keystone,psc-clock";
375 clocks = <&chipclk1>;
376 clock-output-names = "gem3";
377 reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
378 reg-names = "control", "domain";
379 domain-id = <11>;
380 };
381
382 clkgem4: clkgem4 {
383 #clock-cells = <0>;
384 compatible = "ti,keystone,psc-clock";
385 clocks = <&chipclk1>;
386 clock-output-names = "gem4";
387 reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
388 reg-names = "control", "domain";
389 domain-id = <12>;
390 };
391
392 clkgem5: clkgem5 {
393 #clock-cells = <0>;
394 compatible = "ti,keystone,psc-clock";
395 clocks = <&chipclk1>;
396 clock-output-names = "gem5";
397 reg = <0x02350050 0xb00>, <0x02350034 0x400>;
398 reg-names = "control", "domain";
399 domain-id = <13>;
400 };
401
402 clkgem6: clkgem6 {
403 #clock-cells = <0>;
404 compatible = "ti,keystone,psc-clock";
405 clocks = <&chipclk1>;
406 clock-output-names = "gem6";
407 reg = <0x02350054 0xb00>, <0x02350038 0x400>;
408 reg-names = "control", "domain";
409 domain-id = <14>;
410 };
411
412 clkgem7: clkgem7 {
413 #clock-cells = <0>;
414 compatible = "ti,keystone,psc-clock";
415 clocks = <&chipclk1>;
416 clock-output-names = "gem7";
417 reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
418 reg-names = "control", "domain";
419 domain-id = <15>;
420 };
421
422 clkddr30: clkddr30 {
423 #clock-cells = <0>;
424 compatible = "ti,keystone,psc-clock";
425 clocks = <&chipclk12>;
426 clock-output-names = "ddr3-0";
427 reg = <0x0235005c 0xb00>, <0x02350040 0x400>;
428 reg-names = "control", "domain";
429 domain-id = <16>;
430 };
431
432 clkddr31: clkddr31 {
433 #clock-cells = <0>;
434 compatible = "ti,keystone,psc-clock";
435 clocks = <&chipclk13>;
436 clock-output-names = "ddr3-1";
437 reg = <0x02350060 0xb00>, <0x02350040 0x400>;
438 reg-names = "control", "domain";
439 domain-id = <16>;
440 };
441
442 clktac: clktac {
443 #clock-cells = <0>;
444 compatible = "ti,keystone,psc-clock";
445 clocks = <&chipclk13>;
446 clock-output-names = "tac";
447 reg = <0x02350064 0xb00>, <0x02350044 0x400>;
448 reg-names = "control", "domain";
449 domain-id = <17>;
450 };
451
452 clkrac01: clktac01 {
453 #clock-cells = <0>;
454 compatible = "ti,keystone,psc-clock";
455 clocks = <&chipclk13>;
456 clock-output-names = "rac-01";
457 reg = <0x02350068 0xb00>, <0x02350044 0x400>;
458 reg-names = "control", "domain";
459 domain-id = <17>;
460 };
461
462 clkrac23: clktac23 {
463 #clock-cells = <0>;
464 compatible = "ti,keystone,psc-clock";
465 clocks = <&chipclk13>;
466 clock-output-names = "rac-23";
467 reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
468 reg-names = "control", "domain";
469 domain-id = <18>;
470 };
471
472 clkfftc0: clkfftc0 {
473 #clock-cells = <0>;
474 compatible = "ti,keystone,psc-clock";
475 clocks = <&chipclk13>;
476 clock-output-names = "fftc-0";
477 reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
478 reg-names = "control", "domain";
479 domain-id = <19>;
480 };
481
482 clkfftc1: clkfftc1 {
483 #clock-cells = <0>;
484 compatible = "ti,keystone,psc-clock";
485 clocks = <&chipclk13>;
486 clock-output-names = "fftc-1";
487 reg = <0x02350074 0xb00>, <0x023504c0 0x400>;
488 reg-names = "control", "domain";
489 domain-id = <19>;
490 };
491
492 clkfftc2: clkfftc2 {
493 #clock-cells = <0>;
494 compatible = "ti,keystone,psc-clock";
495 clocks = <&chipclk13>;
496 clock-output-names = "fftc-2";
497 reg = <0x02350078 0xb00>, <0x02350050 0x400>;
498 reg-names = "control", "domain";
499 domain-id = <20>;
500 };
501
502 clkfftc3: clkfftc3 {
503 #clock-cells = <0>;
504 compatible = "ti,keystone,psc-clock";
505 clocks = <&chipclk13>;
506 clock-output-names = "fftc-3";
507 reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
508 reg-names = "control", "domain";
509 domain-id = <20>;
510 };
511
512 clkfftc4: clkfftc4 {
513 #clock-cells = <0>;
514 compatible = "ti,keystone,psc-clock";
515 clocks = <&chipclk13>;
516 clock-output-names = "fftc-4";
517 reg = <0x02350080 0xb00>, <0x02350050 0x400>;
518 reg-names = "control", "domain";
519 domain-id = <20>;
520 };
521
522 clkfftc5: clkfftc5 {
523 #clock-cells = <0>;
524 compatible = "ti,keystone,psc-clock";
525 clocks = <&chipclk13>;
526 clock-output-names = "fftc-5";
527 reg = <0x02350084 0xb00>, <0x02350050 0x400>;
528 reg-names = "control", "domain";
529 domain-id = <20>;
530 };
531
532 clkaif: clkaif {
533 #clock-cells = <0>;
534 compatible = "ti,keystone,psc-clock";
535 clocks = <&chipclk13>;
536 clock-output-names = "aif";
537 reg = <0x02350088 0xb00>, <0x02350054 0x400>;
538 reg-names = "control", "domain";
539 domain-id = <21>;
540 };
541
542 clktcp3d0: clktcp3d0 {
543 #clock-cells = <0>;
544 compatible = "ti,keystone,psc-clock";
545 clocks = <&chipclk13>;
546 clock-output-names = "tcp3d-0";
547 reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
548 reg-names = "control", "domain";
549 domain-id = <22>;
550 };
551
552 clktcp3d1: clktcp3d1 {
553 #clock-cells = <0>;
554 compatible = "ti,keystone,psc-clock";
555 clocks = <&chipclk13>;
556 clock-output-names = "tcp3d-1";
557 reg = <0x02350090 0xb00>, <0x02350058 0x400>;
558 reg-names = "control", "domain";
559 domain-id = <22>;
560 };
561
562 clktcp3d2: clktcp3d2 {
563 #clock-cells = <0>;
564 compatible = "ti,keystone,psc-clock";
565 clocks = <&chipclk13>;
566 clock-output-names = "tcp3d-2";
567 reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
568 reg-names = "control", "domain";
569 domain-id = <23>;
570 };
571
572 clktcp3d3: clktcp3d3 {
573 #clock-cells = <0>;
574 compatible = "ti,keystone,psc-clock";
575 clocks = <&chipclk13>;
576 clock-output-names = "tcp3d-3";
577 reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
578 reg-names = "control", "domain";
579 domain-id = <23>;
580 };
581
582 clkvcp0: clkvcp0 {
583 #clock-cells = <0>;
584 compatible = "ti,keystone,psc-clock";
585 clocks = <&chipclk13>;
586 clock-output-names = "vcp-0";
587 reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
588 reg-names = "control", "domain";
589 domain-id = <24>;
590 };
591
592 clkvcp1: clkvcp1 {
593 #clock-cells = <0>;
594 compatible = "ti,keystone,psc-clock";
595 clocks = <&chipclk13>;
596 clock-output-names = "vcp-1";
597 reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
598 reg-names = "control", "domain";
599 domain-id = <24>;
600 };
601
602 clkvcp2: clkvcp2 {
603 #clock-cells = <0>;
604 compatible = "ti,keystone,psc-clock";
605 clocks = <&chipclk13>;
606 clock-output-names = "vcp-2";
607 reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
608 reg-names = "control", "domain";
609 domain-id = <24>;
610 };
611
612 clkvcp3: clkvcp3 {
613 #clock-cells = <0>;
614 compatible = "ti,keystone,psc-clock";
615 clocks = <&chipclk13>;
616 clock-output-names = "vcp-3";
617 reg = <0x0235000a8 0xb00>, <0x02350060 0x400>;
618 reg-names = "control", "domain";
619 domain-id = <24>;
620 };
621
622 clkvcp4: clkvcp4 {
623 #clock-cells = <0>;
624 compatible = "ti,keystone,psc-clock";
625 clocks = <&chipclk13>;
626 clock-output-names = "vcp-4";
627 reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
628 reg-names = "control", "domain";
629 domain-id = <25>;
630 };
631
632 clkvcp5: clkvcp5 {
633 #clock-cells = <0>;
634 compatible = "ti,keystone,psc-clock";
635 clocks = <&chipclk13>;
636 clock-output-names = "vcp-5";
637 reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
638 reg-names = "control", "domain";
639 domain-id = <25>;
640 };
641
642 clkvcp6: clkvcp6 {
643 #clock-cells = <0>;
644 compatible = "ti,keystone,psc-clock";
645 clocks = <&chipclk13>;
646 clock-output-names = "vcp-6";
647 reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
648 reg-names = "control", "domain";
649 domain-id = <25>;
650 };
651
652 clkvcp7: clkvcp7 {
653 #clock-cells = <0>;
654 compatible = "ti,keystone,psc-clock";
655 clocks = <&chipclk13>;
656 clock-output-names = "vcp-7";
657 reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
658 reg-names = "control", "domain";
659 domain-id = <25>;
660 };
661
662 clkbcp: clkbcp {
663 #clock-cells = <0>;
664 compatible = "ti,keystone,psc-clock";
665 clocks = <&chipclk13>;
666 clock-output-names = "bcp";
667 reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
668 reg-names = "control", "domain";
669 domain-id = <26>;
670 };
671
672 clkdxb: clkdxb {
673 #clock-cells = <0>;
674 compatible = "ti,keystone,psc-clock";
675 clocks = <&chipclk13>;
676 clock-output-names = "dxb";
677 reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
678 reg-names = "control", "domain";
679 domain-id = <27>;
680 };
681
682 clkhyperlink1: clkhyperlink1 {
683 #clock-cells = <0>;
684 compatible = "ti,keystone,psc-clock";
685 clocks = <&chipclk12>;
686 clock-output-names = "hyperlink-1";
687 reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
688 reg-names = "control", "domain";
689 domain-id = <28>;
690 };
691
692 clkxge: clkxge {
693 #clock-cells = <0>;
694 compatible = "ti,keystone,psc-clock";
695 clocks = <&chipclk13>;
696 clock-output-names = "xge";
697 reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
698 reg-names = "control", "domain";
699 domain-id = <29>;
700 };
701
702 clkwdtimer0: clkwdtimer0 {
703 #clock-cells = <0>;
704 compatible = "ti,keystone,psc-clock";
705 clocks = <&clkmodrst0>;
706 clock-output-names = "timer0";
707 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
708 reg-names = "control", "domain";
709 domain-id = <0>;
710 };
711
712 clkwdtimer1: clkwdtimer1 {
713 #clock-cells = <0>;
714 compatible = "ti,keystone,psc-clock";
715 clocks = <&clkmodrst0>;
716 clock-output-names = "timer1";
717 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
718 reg-names = "control", "domain";
719 domain-id = <0>;
720 };
721
722 clkwdtimer2: clkwdtimer2 {
723 #clock-cells = <0>;
724 compatible = "ti,keystone,psc-clock";
725 clocks = <&clkmodrst0>;
726 clock-output-names = "timer2";
727 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
728 reg-names = "control", "domain";
729 domain-id = <0>;
730 };
731
732 clkwdtimer3: clkwdtimer3 {
733 #clock-cells = <0>;
734 compatible = "ti,keystone,psc-clock";
735 clocks = <&clkmodrst0>;
736 clock-output-names = "timer3";
737 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
738 reg-names = "control", "domain";
739 domain-id = <0>;
740 };
741
742 clkuart0: clkuart0 {
743 #clock-cells = <0>;
744 compatible = "ti,keystone,psc-clock";
745 clocks = <&clkmodrst0>;
746 clock-output-names = "uart0";
747 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
748 reg-names = "control", "domain";
749 domain-id = <0>;
750 };
751
752 clkuart1: clkuart1 {
753 #clock-cells = <0>;
754 compatible = "ti,keystone,psc-clock";
755 clocks = <&clkmodrst0>;
756 clock-output-names = "uart1";
757 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
758 reg-names = "control", "domain";
759 domain-id = <0>;
760 };
761
762 clkaemif: clkaemif {
763 #clock-cells = <0>;
764 compatible = "ti,keystone,psc-clock";
765 clocks = <&clkaemifspi>;
766 clock-output-names = "aemif";
767 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
768 reg-names = "control", "domain";
769 domain-id = <0>;
770 };
771
772 clkusim: clkusim {
773 #clock-cells = <0>;
774 compatible = "ti,keystone,psc-clock";
775 clocks = <&clkmodrst0>;
776 clock-output-names = "usim";
777 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
778 reg-names = "control", "domain";
779 domain-id = <0>;
780 };
781
782 clki2c: clki2c {
783 #clock-cells = <0>;
784 compatible = "ti,keystone,psc-clock";
785 clocks = <&clkmodrst0>;
786 clock-output-names = "i2c";
787 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
788 reg-names = "control", "domain";
789 domain-id = <0>;
790 };
791
792 clkspi: clkspi {
793 #clock-cells = <0>;
794 compatible = "ti,keystone,psc-clock";
795 clocks = <&clkaemifspi>;
796 clock-output-names = "spi";
797 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
798 reg-names = "control", "domain";
799 domain-id = <0>;
800 };
801
802 clkgpio: clkgpio {
803 #clock-cells = <0>;
804 compatible = "ti,keystone,psc-clock";
805 clocks = <&clkmodrst0>;
806 clock-output-names = "gpio";
807 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
808 reg-names = "control", "domain";
809 domain-id = <0>;
810 };
811
812 clkkeymgr: clkkeymgr {
813 #clock-cells = <0>;
814 compatible = "ti,keystone,psc-clock";
815 clocks = <&clkmodrst0>;
816 clock-output-names = "keymgr";
817 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
818 reg-names = "control", "domain";
819 domain-id = <0>;
820 };
821};
diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts
index a68e34bbecb2..100bdf52b847 100644
--- a/arch/arm/boot/dts/keystone.dts
+++ b/arch/arm/boot/dts/keystone.dts
@@ -100,13 +100,15 @@
100 reg = <0x023100e8 4>; /* pll reset control reg */ 100 reg = <0x023100e8 4>; /* pll reset control reg */
101 }; 101 };
102 102
103 /include/ "keystone-clocks.dtsi"
104
103 uart0: serial@02530c00 { 105 uart0: serial@02530c00 {
104 compatible = "ns16550a"; 106 compatible = "ns16550a";
105 current-speed = <115200>; 107 current-speed = <115200>;
106 reg-shift = <2>; 108 reg-shift = <2>;
107 reg-io-width = <4>; 109 reg-io-width = <4>;
108 reg = <0x02530c00 0x100>; 110 reg = <0x02530c00 0x100>;
109 clock-frequency = <133120000>; 111 clocks = <&clkuart0>;
110 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 112 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
111 }; 113 };
112 114
@@ -116,9 +118,66 @@
116 reg-shift = <2>; 118 reg-shift = <2>;
117 reg-io-width = <4>; 119 reg-io-width = <4>;
118 reg = <0x02531000 0x100>; 120 reg = <0x02531000 0x100>;
119 clock-frequency = <133120000>; 121 clocks = <&clkuart1>;
120 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; 122 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
121 }; 123 };
122 124
125 i2c0: i2c@2530000 {
126 compatible = "ti,davinci-i2c";
127 reg = <0x02530000 0x400>;
128 clock-frequency = <100000>;
129 clocks = <&clki2c>;
130 interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
131 #address-cells = <1>;
132 #size-cells = <0>;
133
134 dtt@50 {
135 compatible = "at,24c1024";
136 reg = <0x50>;
137 };
138 };
139
140 i2c1: i2c@2530400 {
141 compatible = "ti,davinci-i2c";
142 reg = <0x02530400 0x400>;
143 clock-frequency = <100000>;
144 clocks = <&clki2c>;
145 interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
146 };
147
148 i2c2: i2c@2530800 {
149 compatible = "ti,davinci-i2c";
150 reg = <0x02530800 0x400>;
151 clock-frequency = <100000>;
152 clocks = <&clki2c>;
153 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
154 };
155
156 spi0: spi@21000400 {
157 compatible = "ti,dm6441-spi";
158 reg = <0x21000400 0x200>;
159 num-cs = <4>;
160 ti,davinci-spi-intr-line = <0>;
161 interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
162 clocks = <&clkspi>;
163 };
164
165 spi1: spi@21000600 {
166 compatible = "ti,dm6441-spi";
167 reg = <0x21000600 0x200>;
168 num-cs = <4>;
169 ti,davinci-spi-intr-line = <0>;
170 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
171 clocks = <&clkspi>;
172 };
173
174 spi2: spi@21000800 {
175 compatible = "ti,dm6441-spi";
176 reg = <0x21000800 0x200>;
177 num-cs = <4>;
178 ti,davinci-spi-intr-line = <0>;
179 interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
180 clocks = <&clkspi>;
181 };
123 }; 182 };
124}; 183};
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 0c514dc8460c..ba4dcfc6b721 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -11,7 +11,7 @@
11 11
12/ { 12/ {
13 model = "TI OMAP3 BeagleBoard xM"; 13 model = "TI OMAP3 BeagleBoard xM";
14 compatible = "ti,omap3-beagle-xm", "ti,omap3-beagle", "ti,omap3"; 14 compatible = "ti,omap3-beagle-xm", "ti,omap36xx", "ti,omap3";
15 15
16 cpus { 16 cpus {
17 cpu@0 { 17 cpu@0 {
@@ -144,6 +144,8 @@
144&usb_otg_hs { 144&usb_otg_hs {
145 interface-type = <0>; 145 interface-type = <0>;
146 usb-phy = <&usb2_phy>; 146 usb-phy = <&usb2_phy>;
147 phys = <&usb2_phy>;
148 phy-names = "usb2-phy";
147 mode = <3>; 149 mode = <3>;
148 power = <50>; 150 power = <50>;
149}; 151};
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 7d4329d179c4..4134dd05c3a4 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -70,6 +70,8 @@
70&usb_otg_hs { 70&usb_otg_hs {
71 interface-type = <0>; 71 interface-type = <0>;
72 usb-phy = <&usb2_phy>; 72 usb-phy = <&usb2_phy>;
73 phys = <&usb2_phy>;
74 phy-names = "usb2-phy";
73 mode = <3>; 75 mode = <3>;
74 power = <50>; 76 power = <50>;
75}; 77};
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
index 8f1abec78275..a461d2fd1fb0 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -76,6 +76,8 @@
76&usb_otg_hs { 76&usb_otg_hs {
77 interface-type = <0>; 77 interface-type = <0>;
78 usb-phy = <&usb2_phy>; 78 usb-phy = <&usb2_phy>;
79 phys = <&usb2_phy>;
80 phy-names = "usb2-phy";
79 mode = <3>; 81 mode = <3>;
80 power = <50>; 82 power = <50>;
81}; 83};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 7d95cda1fae4..b41bd57f4328 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -108,7 +108,7 @@
108 #address-cells = <1>; 108 #address-cells = <1>;
109 #size-cells = <0>; 109 #size-cells = <0>;
110 pinctrl-single,register-width = <16>; 110 pinctrl-single,register-width = <16>;
111 pinctrl-single,function-mask = <0x7f1f>; 111 pinctrl-single,function-mask = <0xff1f>;
112 }; 112 };
113 113
114 omap3_pmx_wkup: pinmux@0x48002a00 { 114 omap3_pmx_wkup: pinmux@0x48002a00 {
@@ -117,7 +117,7 @@
117 #address-cells = <1>; 117 #address-cells = <1>;
118 #size-cells = <0>; 118 #size-cells = <0>;
119 pinctrl-single,register-width = <16>; 119 pinctrl-single,register-width = <16>;
120 pinctrl-single,function-mask = <0x7f1f>; 120 pinctrl-single,function-mask = <0xff1f>;
121 }; 121 };
122 122
123 gpio1: gpio@48310000 { 123 gpio1: gpio@48310000 {
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 22d9f2b593d4..ea4054bfdfd4 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -519,7 +519,8 @@
519 usb2_phy: usb2phy@4a0ad080 { 519 usb2_phy: usb2phy@4a0ad080 {
520 compatible = "ti,omap-usb2"; 520 compatible = "ti,omap-usb2";
521 reg = <0x4a0ad080 0x58>; 521 reg = <0x4a0ad080 0x58>;
522 ctrl-module = <&omap_control_usb>; 522 ctrl-module = <&omap_control_usb2phy>;
523 #phy-cells = <0>;
523 }; 524 };
524 }; 525 };
525 526
@@ -643,12 +644,16 @@
643 }; 644 };
644 }; 645 };
645 646
646 omap_control_usb: omap-control-usb@4a002300 { 647 omap_control_usb2phy: control-phy@4a002300 {
647 compatible = "ti,omap-control-usb"; 648 compatible = "ti,control-phy-usb2";
648 reg = <0x4a002300 0x4>, 649 reg = <0x4a002300 0x4>;
649 <0x4a00233c 0x4>; 650 reg-names = "power";
650 reg-names = "control_dev_conf", "otghs_control"; 651 };
651 ti,type = <1>; 652
653 omap_control_usbotg: control-phy@4a00233c {
654 compatible = "ti,control-phy-otghs";
655 reg = <0x4a00233c 0x4>;
656 reg-names = "otghs_control";
652 }; 657 };
653 658
654 usb_otg_hs: usb_otg_hs@4a0ab000 { 659 usb_otg_hs: usb_otg_hs@4a0ab000 {
@@ -658,10 +663,12 @@
658 interrupt-names = "mc", "dma"; 663 interrupt-names = "mc", "dma";
659 ti,hwmods = "usb_otg_hs"; 664 ti,hwmods = "usb_otg_hs";
660 usb-phy = <&usb2_phy>; 665 usb-phy = <&usb2_phy>;
666 phys = <&usb2_phy>;
667 phy-names = "usb2-phy";
661 multipoint = <1>; 668 multipoint = <1>;
662 num-eps = <16>; 669 num-eps = <16>;
663 ram-bits = <12>; 670 ram-bits = <12>;
664 ti,has-mailbox; 671 ctrl-module = <&omap_control_usbotg>;
665 }; 672 };
666 }; 673 };
667}; 674};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 7cdea1bfea09..c0ec6dce30fe 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -626,12 +626,16 @@
626 hw-caps-temp-alert; 626 hw-caps-temp-alert;
627 }; 627 };
628 628
629 omap_control_usb: omap-control-usb@4a002300 { 629 omap_control_usb2phy: control-phy@4a002300 {
630 compatible = "ti,omap-control-usb"; 630 compatible = "ti,control-phy-usb2";
631 reg = <0x4a002300 0x4>, 631 reg = <0x4a002300 0x4>;
632 <0x4a002370 0x4>; 632 reg-names = "power";
633 reg-names = "control_dev_conf", "phy_power_usb"; 633 };
634 ti,type = <2>; 634
635 omap_control_usb3phy: control-phy@4a002370 {
636 compatible = "ti,control-phy-pipe3";
637 reg = <0x4a002370 0x4>;
638 reg-names = "power";
635 }; 639 };
636 640
637 omap_dwc3@4a020000 { 641 omap_dwc3@4a020000 {
@@ -662,7 +666,7 @@
662 usb2_phy: usb2phy@4a084000 { 666 usb2_phy: usb2phy@4a084000 {
663 compatible = "ti,omap-usb2"; 667 compatible = "ti,omap-usb2";
664 reg = <0x4a084000 0x7c>; 668 reg = <0x4a084000 0x7c>;
665 ctrl-module = <&omap_control_usb>; 669 ctrl-module = <&omap_control_usb2phy>;
666 }; 670 };
667 671
668 usb3_phy: usb3phy@4a084400 { 672 usb3_phy: usb3phy@4a084400 {
@@ -671,7 +675,7 @@
671 <0x4a084800 0x64>, 675 <0x4a084800 0x64>,
672 <0x4a084c00 0x40>; 676 <0x4a084c00 0x40>;
673 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 677 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
674 ctrl-module = <&omap_control_usb>; 678 ctrl-module = <&omap_control_usb3phy>;
675 }; 679 };
676 }; 680 };
677 681
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 386d42870215..386d42870215 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index 93e9f7e0b7ad..93e9f7e0b7ad 100644
--- a/arch/arm/boot/dts/msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 2218c64410de..be5d2b09a363 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -161,17 +161,14 @@
161 uart0_xfer: uart0-xfer { 161 uart0_xfer: uart0-xfer {
162 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>, 162 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
163 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>; 163 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
164 rockchip,config = <&pcfg_pull_default>;
165 }; 164 };
166 165
167 uart0_cts: uart0-cts { 166 uart0_cts: uart0-cts {
168 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>; 167 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
169 rockchip,config = <&pcfg_pull_default>;
170 }; 168 };
171 169
172 uart0_rts: uart0-rts { 170 uart0_rts: uart0-rts {
173 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>; 171 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
174 rockchip,config = <&pcfg_pull_default>;
175 }; 172 };
176 }; 173 };
177 174
@@ -179,17 +176,14 @@
179 uart1_xfer: uart1-xfer { 176 uart1_xfer: uart1-xfer {
180 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>, 177 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
181 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>; 178 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
182 rockchip,config = <&pcfg_pull_default>;
183 }; 179 };
184 180
185 uart1_cts: uart1-cts { 181 uart1_cts: uart1-cts {
186 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>; 182 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
187 rockchip,config = <&pcfg_pull_default>;
188 }; 183 };
189 184
190 uart1_rts: uart1-rts { 185 uart1_rts: uart1-rts {
191 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>; 186 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
192 rockchip,config = <&pcfg_pull_default>;
193 }; 187 };
194 }; 188 };
195 189
@@ -197,7 +191,6 @@
197 uart2_xfer: uart2-xfer { 191 uart2_xfer: uart2-xfer {
198 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>, 192 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
199 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>; 193 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
200 rockchip,config = <&pcfg_pull_default>;
201 }; 194 };
202 /* no rts / cts for uart2 */ 195 /* no rts / cts for uart2 */
203 }; 196 };
@@ -206,44 +199,36 @@
206 uart3_xfer: uart3-xfer { 199 uart3_xfer: uart3-xfer {
207 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>, 200 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
208 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>; 201 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
209 rockchip,config = <&pcfg_pull_default>;
210 }; 202 };
211 203
212 uart3_cts: uart3-cts { 204 uart3_cts: uart3-cts {
213 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>; 205 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
214 rockchip,config = <&pcfg_pull_default>;
215 }; 206 };
216 207
217 uart3_rts: uart3-rts { 208 uart3_rts: uart3-rts {
218 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>; 209 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
219 rockchip,config = <&pcfg_pull_default>;
220 }; 210 };
221 }; 211 };
222 212
223 sd0 { 213 sd0 {
224 sd0_clk: sd0-clk { 214 sd0_clk: sd0-clk {
225 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>; 215 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
226 rockchip,config = <&pcfg_pull_default>;
227 }; 216 };
228 217
229 sd0_cmd: sd0-cmd { 218 sd0_cmd: sd0-cmd {
230 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>; 219 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
231 rockchip,config = <&pcfg_pull_default>;
232 }; 220 };
233 221
234 sd0_cd: sd0-cd { 222 sd0_cd: sd0-cd {
235 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>; 223 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
236 rockchip,config = <&pcfg_pull_default>;
237 }; 224 };
238 225
239 sd0_wp: sd0-wp { 226 sd0_wp: sd0-wp {
240 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>; 227 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
241 rockchip,config = <&pcfg_pull_default>;
242 }; 228 };
243 229
244 sd0_bus1: sd0-bus-width1 { 230 sd0_bus1: sd0-bus-width1 {
245 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>; 231 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
246 rockchip,config = <&pcfg_pull_default>;
247 }; 232 };
248 233
249 sd0_bus4: sd0-bus-width4 { 234 sd0_bus4: sd0-bus-width4 {
@@ -251,34 +236,28 @@
251 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>, 236 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
252 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>, 237 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
253 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>; 238 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
254 rockchip,config = <&pcfg_pull_default>;
255 }; 239 };
256 }; 240 };
257 241
258 sd1 { 242 sd1 {
259 sd1_clk: sd1-clk { 243 sd1_clk: sd1-clk {
260 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>; 244 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
261 rockchip,config = <&pcfg_pull_default>;
262 }; 245 };
263 246
264 sd1_cmd: sd1-cmd { 247 sd1_cmd: sd1-cmd {
265 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>; 248 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
266 rockchip,config = <&pcfg_pull_default>;
267 }; 249 };
268 250
269 sd1_cd: sd1-cd { 251 sd1_cd: sd1-cd {
270 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>; 252 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
271 rockchip,config = <&pcfg_pull_default>;
272 }; 253 };
273 254
274 sd1_wp: sd1-wp { 255 sd1_wp: sd1-wp {
275 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>; 256 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
276 rockchip,config = <&pcfg_pull_default>;
277 }; 257 };
278 258
279 sd1_bus1: sd1-bus-width1 { 259 sd1_bus1: sd1-bus-width1 {
280 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>; 260 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
281 rockchip,config = <&pcfg_pull_default>;
282 }; 261 };
283 262
284 sd1_bus4: sd1-bus-width4 { 263 sd1_bus4: sd1-bus-width4 {
@@ -286,7 +265,6 @@
286 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>, 265 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
287 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>, 266 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
288 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>; 267 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
289 rockchip,config = <&pcfg_pull_default>;
290 }; 268 };
291 }; 269 };
292 }; 270 };
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index b7f49615120d..5cdaba4cea86 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -31,7 +31,6 @@
31 gpio3 = &pioD; 31 gpio3 = &pioD;
32 gpio4 = &pioE; 32 gpio4 = &pioE;
33 tcb0 = &tcb0; 33 tcb0 = &tcb0;
34 tcb1 = &tcb1;
35 i2c0 = &i2c0; 34 i2c0 = &i2c0;
36 i2c1 = &i2c1; 35 i2c1 = &i2c1;
37 i2c2 = &i2c2; 36 i2c2 = &i2c2;
@@ -105,15 +104,6 @@
105 status = "disabled"; 104 status = "disabled";
106 }; 105 };
107 106
108 can0: can@f000c000 {
109 compatible = "atmel,at91sam9x5-can";
110 reg = <0xf000c000 0x300>;
111 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_can0_rx_tx>;
114 status = "disabled";
115 };
116
117 tcb0: timer@f0010000 { 107 tcb0: timer@f0010000 {
118 compatible = "atmel,at91sam9x5-tcb"; 108 compatible = "atmel,at91sam9x5-tcb";
119 reg = <0xf0010000 0x100>; 109 reg = <0xf0010000 0x100>;
@@ -166,15 +156,6 @@
166 status = "disabled"; 156 status = "disabled";
167 }; 157 };
168 158
169 macb0: ethernet@f0028000 {
170 compatible = "cdns,pc302-gem", "cdns,gem";
171 reg = <0xf0028000 0x100>;
172 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
175 status = "disabled";
176 };
177
178 isi: isi@f0034000 { 159 isi: isi@f0034000 {
179 compatible = "atmel,at91sam9g45-isi"; 160 compatible = "atmel,at91sam9g45-isi";
180 reg = <0xf0034000 0x4000>; 161 reg = <0xf0034000 0x4000>;
@@ -195,19 +176,6 @@
195 #size-cells = <0>; 176 #size-cells = <0>;
196 }; 177 };
197 178
198 mmc2: mmc@f8004000 {
199 compatible = "atmel,hsmci";
200 reg = <0xf8004000 0x600>;
201 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
202 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>;
203 dma-names = "rxtx";
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
206 status = "disabled";
207 #address-cells = <1>;
208 #size-cells = <0>;
209 };
210
211 spi1: spi@f8008000 { 179 spi1: spi@f8008000 {
212 #address-cells = <1>; 180 #address-cells = <1>;
213 #size-cells = <0>; 181 #size-cells = <0>;
@@ -231,20 +199,6 @@
231 status = "disabled"; 199 status = "disabled";
232 }; 200 };
233 201
234 can1: can@f8010000 {
235 compatible = "atmel,at91sam9x5-can";
236 reg = <0xf8010000 0x300>;
237 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_can1_rx_tx>;
240 };
241
242 tcb1: timer@f8014000 {
243 compatible = "atmel,at91sam9x5-tcb";
244 reg = <0xf8014000 0x100>;
245 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
246 };
247
248 adc0: adc@f8018000 { 202 adc0: adc@f8018000 {
249 compatible = "atmel,at91sam9260-adc"; 203 compatible = "atmel,at91sam9260-adc";
250 reg = <0xf8018000 0x100>; 204 reg = <0xf8018000 0x100>;
@@ -341,15 +295,6 @@
341 status = "disabled"; 295 status = "disabled";
342 }; 296 };
343 297
344 macb1: ethernet@f802c000 {
345 compatible = "cdns,at32ap7000-macb", "cdns,macb";
346 reg = <0xf802c000 0x100>;
347 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&pinctrl_macb1_rmii>;
350 status = "disabled";
351 };
352
353 sha@f8034000 { 298 sha@f8034000 {
354 compatible = "atmel,sam9g46-sha"; 299 compatible = "atmel,sam9g46-sha";
355 reg = <0xf8034000 0x100>; 300 reg = <0xf8034000 0x100>;
@@ -474,22 +419,6 @@
474 }; 419 };
475 }; 420 };
476 421
477 can0 {
478 pinctrl_can0_rx_tx: can0_rx_tx {
479 atmel,pins =
480 <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
481 AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
482 };
483 };
484
485 can1 {
486 pinctrl_can1_rx_tx: can1_rx_tx {
487 atmel,pins =
488 <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
489 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
490 };
491 };
492
493 dbgu { 422 dbgu {
494 pinctrl_dbgu: dbgu-0 { 423 pinctrl_dbgu: dbgu-0 {
495 atmel,pins = 424 atmel,pins =
@@ -537,107 +466,6 @@
537 }; 466 };
538 }; 467 };
539 468
540 lcd {
541 pinctrl_lcd: lcd-0 {
542 atmel,pins =
543 <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */
544 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */
545 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */
546 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */
547 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */
548 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */
549 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */
550 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */
551 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */
552 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */
553 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */
554 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */
555 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */
556 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */
557 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */
558 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */
559 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */
560 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */
561 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */
562 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */
563 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */
564 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */
565 AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */
566 AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */
567 AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */
568 AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */
569 AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */
570 AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */
571 AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */
572 AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
573 };
574 };
575
576 macb0 {
577 pinctrl_macb0_data_rgmii: macb0_data_rgmii {
578 atmel,pins =
579 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */
580 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */
581 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */
582 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */
583 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */
584 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */
585 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */
586 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */
587 };
588 pinctrl_macb0_data_gmii: macb0_data_gmii {
589 atmel,pins =
590 <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */
591 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
592 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
593 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
594 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
595 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */
596 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */
597 AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */
598 };
599 pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
600 atmel,pins =
601 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */
602 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
603 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
604 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
605 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
606 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
607 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */
608 };
609 pinctrl_macb0_signal_gmii: macb0_signal_gmii {
610 atmel,pins =
611 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
612 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */
613 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
614 AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */
615 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
616 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */
617 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */
618 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
619 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
620 AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */
621 };
622
623 };
624
625 macb1 {
626 pinctrl_macb1_rmii: macb1_rmii-0 {
627 atmel,pins =
628 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */
629 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */
630 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */
631 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */
632 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */
633 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */
634 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */
635 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */
636 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */
637 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */
638 };
639 };
640
641 mmc0 { 469 mmc0 {
642 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { 470 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
643 atmel,pins = 471 atmel,pins =
@@ -675,21 +503,6 @@
675 }; 503 };
676 }; 504 };
677 505
678 mmc2 {
679 pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
680 atmel,pins =
681 <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
682 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
683 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
684 };
685 pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
686 atmel,pins =
687 <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
688 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
689 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
690 };
691 };
692
693 nand0 { 506 nand0 {
694 pinctrl_nand0_ale_cle: nand0_ale_cle-0 { 507 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
695 atmel,pins = 508 atmel,pins =
@@ -748,22 +561,6 @@
748 }; 561 };
749 }; 562 };
750 563
751 uart0 {
752 pinctrl_uart0: uart0-0 {
753 atmel,pins =
754 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
755 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
756 };
757 };
758
759 uart1 {
760 pinctrl_uart1: uart1-0 {
761 atmel,pins =
762 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
763 AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
764 };
765 };
766
767 usart0 { 564 usart0 {
768 pinctrl_usart0: usart0-0 { 565 pinctrl_usart0: usart0-0 {
769 atmel,pins = 566 atmel,pins =
diff --git a/arch/arm/boot/dts/sama5d31.dtsi b/arch/arm/boot/dts/sama5d31.dtsi
new file mode 100644
index 000000000000..7997dc9863ed
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d31.dtsi
@@ -0,0 +1,16 @@
1/*
2 * sama5d31.dtsi - Device Tree Include file for SAMA5D31 SoC
3 *
4 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8#include "sama5d3.dtsi"
9#include "sama5d3_lcd.dtsi"
10#include "sama5d3_emac.dtsi"
11#include "sama5d3_mci2.dtsi"
12#include "sama5d3_uart.dtsi"
13
14/ {
15 compatible = "atmel,samad31", "atmel,sama5d3", "atmel,sama5";
16};
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts
index 027bac7510b6..04eec0dfcf7d 100644
--- a/arch/arm/boot/dts/sama5d31ek.dts
+++ b/arch/arm/boot/dts/sama5d31ek.dts
@@ -7,12 +7,13 @@
7 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
8 */ 8 */
9/dts-v1/; 9/dts-v1/;
10#include "sama5d31.dtsi"
10#include "sama5d3xmb.dtsi" 11#include "sama5d3xmb.dtsi"
11#include "sama5d3xdm.dtsi" 12#include "sama5d3xdm.dtsi"
12 13
13/ { 14/ {
14 model = "Atmel SAMA5D31-EK"; 15 model = "Atmel SAMA5D31-EK";
15 compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; 16 compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
16 17
17 ahb { 18 ahb {
18 apb { 19 apb {
diff --git a/arch/arm/boot/dts/sama5d33.dtsi b/arch/arm/boot/dts/sama5d33.dtsi
new file mode 100644
index 000000000000..39f832253caf
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d33.dtsi
@@ -0,0 +1,14 @@
1/*
2 * sama5d33.dtsi - Device Tree Include file for SAMA5D33 SoC
3 *
4 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8#include "sama5d3.dtsi"
9#include "sama5d3_lcd.dtsi"
10#include "sama5d3_gmac.dtsi"
11
12/ {
13 compatible = "atmel,samad33", "atmel,sama5d3", "atmel,sama5";
14};
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts
index 99bd0c8e0471..cbd6a3ff1545 100644
--- a/arch/arm/boot/dts/sama5d33ek.dts
+++ b/arch/arm/boot/dts/sama5d33ek.dts
@@ -7,12 +7,13 @@
7 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
8 */ 8 */
9/dts-v1/; 9/dts-v1/;
10#include "sama5d33.dtsi"
10#include "sama5d3xmb.dtsi" 11#include "sama5d3xmb.dtsi"
11#include "sama5d3xdm.dtsi" 12#include "sama5d3xdm.dtsi"
12 13
13/ { 14/ {
14 model = "Atmel SAMA5D33-EK"; 15 model = "Atmel SAMA5D33-EK";
15 compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; 16 compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5";
16 17
17 ahb { 18 ahb {
18 apb { 19 apb {
diff --git a/arch/arm/boot/dts/sama5d34.dtsi b/arch/arm/boot/dts/sama5d34.dtsi
new file mode 100644
index 000000000000..89cda2c0da39
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d34.dtsi
@@ -0,0 +1,16 @@
1/*
2 * sama5d34.dtsi - Device Tree Include file for SAMA5D34 SoC
3 *
4 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8#include "sama5d3.dtsi"
9#include "sama5d3_lcd.dtsi"
10#include "sama5d3_gmac.dtsi"
11#include "sama5d3_can.dtsi"
12#include "sama5d3_mci2.dtsi"
13
14/ {
15 compatible = "atmel,samad34", "atmel,sama5d3", "atmel,sama5";
16};
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
index fb8ee11cf282..878aa164275a 100644
--- a/arch/arm/boot/dts/sama5d34ek.dts
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -7,12 +7,13 @@
7 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
8 */ 8 */
9/dts-v1/; 9/dts-v1/;
10#include "sama5d34.dtsi"
10#include "sama5d3xmb.dtsi" 11#include "sama5d3xmb.dtsi"
11#include "sama5d3xdm.dtsi" 12#include "sama5d3xdm.dtsi"
12 13
13/ { 14/ {
14 model = "Atmel SAMA5D34-EK"; 15 model = "Atmel SAMA5D34-EK";
15 compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; 16 compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5";
16 17
17 ahb { 18 ahb {
18 apb { 19 apb {
diff --git a/arch/arm/boot/dts/sama5d35.dtsi b/arch/arm/boot/dts/sama5d35.dtsi
new file mode 100644
index 000000000000..d20cd71b5f0e
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d35.dtsi
@@ -0,0 +1,18 @@
1/*
2 * sama5d35.dtsi - Device Tree Include file for SAMA5D35 SoC
3 *
4 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8#include "sama5d3.dtsi"
9#include "sama5d3_gmac.dtsi"
10#include "sama5d3_emac.dtsi"
11#include "sama5d3_can.dtsi"
12#include "sama5d3_mci2.dtsi"
13#include "sama5d3_uart.dtsi"
14#include "sama5d3_tcb1.dtsi"
15
16/ {
17 compatible = "atmel,samad35", "atmel,sama5d3", "atmel,sama5";
18};
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts
index 509a53d9cc7b..9089c7c6cea8 100644
--- a/arch/arm/boot/dts/sama5d35ek.dts
+++ b/arch/arm/boot/dts/sama5d35ek.dts
@@ -7,11 +7,12 @@
7 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
8 */ 8 */
9/dts-v1/; 9/dts-v1/;
10#include "sama5d35.dtsi"
10#include "sama5d3xmb.dtsi" 11#include "sama5d3xmb.dtsi"
11 12
12/ { 13/ {
13 model = "Atmel SAMA5D35-EK"; 14 model = "Atmel SAMA5D35-EK";
14 compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; 15 compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5";
15 16
16 ahb { 17 ahb {
17 apb { 18 apb {
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi
new file mode 100644
index 000000000000..8ed3260cef66
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_can.dtsi
@@ -0,0 +1,54 @@
1/*
2 * at91sama5d3_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
3 * CAN support
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 ahb {
15 apb {
16 pinctrl@fffff200 {
17 can0 {
18 pinctrl_can0_rx_tx: can0_rx_tx {
19 atmel,pins =
20 <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
21 AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
22 };
23 };
24
25 can1 {
26 pinctrl_can1_rx_tx: can1_rx_tx {
27 atmel,pins =
28 <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
29 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
30 };
31 };
32
33 };
34
35 can0: can@f000c000 {
36 compatible = "atmel,at91sam9x5-can";
37 reg = <0xf000c000 0x300>;
38 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_can0_rx_tx>;
41 status = "disabled";
42 };
43
44 can1: can@f8010000 {
45 compatible = "atmel,at91sam9x5-can";
46 reg = <0xf8010000 0x300>;
47 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_can1_rx_tx>;
50 status = "disabled";
51 };
52 };
53 };
54};
diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi
new file mode 100644
index 000000000000..4d4f351f1f9f
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_emac.dtsi
@@ -0,0 +1,44 @@
1/*
2 * at91sama5d3_emac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
3 * Ethernet.
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 ahb {
15 apb {
16 pinctrl@fffff200 {
17 macb1 {
18 pinctrl_macb1_rmii: macb1_rmii-0 {
19 atmel,pins =
20 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */
21 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */
22 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */
23 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */
24 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */
25 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */
26 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */
27 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */
28 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */
29 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */
30 };
31 };
32 };
33
34 macb1: ethernet@f802c000 {
35 compatible = "cdns,at32ap7000-macb", "cdns,macb";
36 reg = <0xf802c000 0x100>;
37 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_macb1_rmii>;
40 status = "disabled";
41 };
42 };
43 };
44};
diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi
new file mode 100644
index 000000000000..0ba8be30ccd8
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi
@@ -0,0 +1,77 @@
1/*
2 * at91sama5d3_gmac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
3 * Gigabit Ethernet.
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 ahb {
15 apb {
16 pinctrl@fffff200 {
17 macb0 {
18 pinctrl_macb0_data_rgmii: macb0_data_rgmii {
19 atmel,pins =
20 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */
21 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */
22 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */
23 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */
24 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */
25 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */
26 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */
27 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */
28 };
29 pinctrl_macb0_data_gmii: macb0_data_gmii {
30 atmel,pins =
31 <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */
32 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
33 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
34 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
35 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
36 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */
37 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */
38 AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */
39 };
40 pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
41 atmel,pins =
42 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */
43 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
44 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
45 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
46 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
47 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
48 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */
49 };
50 pinctrl_macb0_signal_gmii: macb0_signal_gmii {
51 atmel,pins =
52 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
53 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */
54 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
55 AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */
56 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
57 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */
58 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */
59 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
60 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
61 AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */
62 };
63
64 };
65 };
66
67 macb0: ethernet@f0028000 {
68 compatible = "cdns,pc302-gem", "cdns,gem";
69 reg = <0xf0028000 0x100>;
70 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
73 status = "disabled";
74 };
75 };
76 };
77};
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi
new file mode 100644
index 000000000000..01f52a79f8ba
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi
@@ -0,0 +1,55 @@
1/*
2 * at91sama5d3_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
3 * LCD support
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 ahb {
15 apb {
16 pinctrl@fffff200 {
17 lcd {
18 pinctrl_lcd: lcd-0 {
19 atmel,pins =
20 <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */
21 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */
22 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */
23 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */
24 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */
25 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */
26 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */
27 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */
28 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */
29 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */
30 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */
31 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */
32 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */
33 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */
34 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */
35 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */
36 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */
37 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */
38 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */
39 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */
40 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */
41 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */
42 AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */
43 AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */
44 AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */
45 AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */
46 AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */
47 AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */
48 AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */
49 AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
50 };
51 };
52 };
53 };
54 };
55};
diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi
new file mode 100644
index 000000000000..38e88e39e551
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi
@@ -0,0 +1,47 @@
1/*
2 * at91sama5d3_mci2.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
3 * 3 MMC ports
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 ahb {
15 apb {
16 pinctrl@fffff200 {
17 mmc2 {
18 pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
19 atmel,pins =
20 <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
21 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
22 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
23 };
24 pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
25 atmel,pins =
26 <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
27 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
28 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
29 };
30 };
31 };
32
33 mmc2: mmc@f8004000 {
34 compatible = "atmel,hsmci";
35 reg = <0xf8004000 0x600>;
36 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
37 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>;
38 dma-names = "rxtx";
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
41 status = "disabled";
42 #address-cells = <1>;
43 #size-cells = <0>;
44 };
45 };
46 };
47};
diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
new file mode 100644
index 000000000000..5264bb4a6998
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
@@ -0,0 +1,27 @@
1/*
2 * at91sama5d3_tcb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
3 * 2 TC blocks.
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 aliases {
15 tcb1 = &tcb1;
16 };
17
18 ahb {
19 apb {
20 tcb1: timer@f8014000 {
21 compatible = "atmel,at91sam9x5-tcb";
22 reg = <0xf8014000 0x100>;
23 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
24 };
25 };
26 };
27};
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
new file mode 100644
index 000000000000..98fcb2d57446
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -0,0 +1,53 @@
1/*
2 * at91sama5d3_uart.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
3 * UART support
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 ahb {
15 apb {
16 pinctrl@fffff200 {
17 uart0 {
18 pinctrl_uart0: uart0-0 {
19 atmel,pins =
20 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
21 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
22 };
23 };
24
25 uart1 {
26 pinctrl_uart1: uart1-0 {
27 atmel,pins =
28 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
29 AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
30 };
31 };
32 };
33
34 uart0: serial@f0024000 {
35 compatible = "atmel,at91sam9260-usart";
36 reg = <0xf0024000 0x200>;
37 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_uart0>;
40 status = "disabled";
41 };
42
43 uart1: serial@f8028000 {
44 compatible = "atmel,at91sam9260-usart";
45 reg = <0xf8028000 0x200>;
46 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_uart1>;
49 status = "disabled";
50 };
51 };
52 };
53};
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 31ed9e3bb649..726a0f35100c 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -6,7 +6,6 @@
6 * 6 *
7 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
8 */ 8 */
9#include "sama5d3.dtsi"
10 9
11/ { 10/ {
12 compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5"; 11 compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5";
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index 9169d3025f39..79425e3836ce 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -653,6 +653,7 @@
653 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; 653 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
654 clocks = <&hclksmc>; 654 clocks = <&hclksmc>;
655 status = "okay"; 655 status = "okay";
656 timings = /bits/ 8 <0 0 0 0x10 0x0a 0>;
656 657
657 partition@0 { 658 partition@0 {
658 label = "X-Loader(NAND)"; 659 label = "X-Loader(NAND)";
@@ -707,8 +708,14 @@
707 pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>; 708 pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>;
708 709
709 stw4811@2d { 710 stw4811@2d {
710 compatible = "st,stw4811"; 711 compatible = "st,stw4811";
711 reg = <0x2d>; 712 reg = <0x2d>;
713 vmmc_regulator: vmmc {
714 compatible = "st,stw481x-vmmc";
715 regulator-name = "VMMC";
716 regulator-min-microvolt = <1800000>;
717 regulator-max-microvolt = <3300000>;
718 };
712 }; 719 };
713 }; 720 };
714 721
@@ -839,6 +846,7 @@
839 cd-inverted; 846 cd-inverted;
840 pinctrl-names = "default"; 847 pinctrl-names = "default";
841 pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; 848 pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
849 vmmc-supply = <&vmmc_regulator>;
842 }; 850 };
843 }; 851 };
844}; 852};
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index ae6a17aed9ee..5aba238d1f1e 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -86,6 +86,7 @@
86 usb1v8-supply = <&vusb1v8>; 86 usb1v8-supply = <&vusb1v8>;
87 usb3v1-supply = <&vusb3v1>; 87 usb3v1-supply = <&vusb3v1>;
88 usb_mode = <1>; 88 usb_mode = <1>;
89 #phy-cells = <0>;
89 }; 90 };
90 91
91 twl_pwm: pwm { 92 twl_pwm: pwm {
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-16 04:22:42 -0400