diff options
Diffstat (limited to 'arch/arm/boot/dts')
150 files changed, 12623 insertions, 853 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c6255884cbb..20358fb43450 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile | |||
| @@ -3,6 +3,7 @@ ifeq ($(CONFIG_OF),y) | |||
| 3 | # Keep at91 dtb files sorted alphabetically for each SoC | 3 | # Keep at91 dtb files sorted alphabetically for each SoC |
| 4 | # rm9200 | 4 | # rm9200 |
| 5 | dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb | 5 | dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb |
| 6 | dtb-$(CONFIG_ARCH_AT91) += mpa1600.dtb | ||
| 6 | # sam9260 | 7 | # sam9260 |
| 7 | dtb-$(CONFIG_ARCH_AT91) += animeo_ip.dtb | 8 | dtb-$(CONFIG_ARCH_AT91) += animeo_ip.dtb |
| 8 | dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb | 9 | dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb |
| @@ -26,11 +27,17 @@ dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb | |||
| 26 | # sam9n12 | 27 | # sam9n12 |
| 27 | dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb | 28 | dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb |
| 28 | # sam9x5 | 29 | # sam9x5 |
| 30 | dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb | ||
| 29 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb | 31 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb |
| 30 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb | 32 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb |
| 31 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb | 33 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb |
| 32 | dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb | 34 | dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb |
| 33 | dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb | 35 | dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb |
| 36 | # sama5d3 | ||
| 37 | dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb | ||
| 38 | dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb | ||
| 39 | dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb | ||
| 40 | dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb | ||
| 34 | 41 | ||
| 35 | dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb | 42 | dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb |
| 36 | dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb | 43 | dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb |
| @@ -87,19 +94,26 @@ dtb-$(CONFIG_ARCH_MXC) += \ | |||
| 87 | imx25-karo-tx25.dtb \ | 94 | imx25-karo-tx25.dtb \ |
| 88 | imx25-pdk.dtb \ | 95 | imx25-pdk.dtb \ |
| 89 | imx27-apf27.dtb \ | 96 | imx27-apf27.dtb \ |
| 97 | imx27-apf27dev.dtb \ | ||
| 90 | imx27-pdk.dtb \ | 98 | imx27-pdk.dtb \ |
| 99 | imx27-phytec-phycore.dtb \ | ||
| 91 | imx31-bug.dtb \ | 100 | imx31-bug.dtb \ |
| 92 | imx51-apf51.dtb \ | 101 | imx51-apf51.dtb \ |
| 102 | imx51-apf51dev.dtb \ | ||
| 93 | imx51-babbage.dtb \ | 103 | imx51-babbage.dtb \ |
| 94 | imx53-ard.dtb \ | 104 | imx53-ard.dtb \ |
| 95 | imx53-evk.dtb \ | 105 | imx53-evk.dtb \ |
| 96 | imx53-mba53.dtb \ | 106 | imx53-mba53.dtb \ |
| 97 | imx53-qsb.dtb \ | 107 | imx53-qsb.dtb \ |
| 98 | imx53-smd.dtb \ | 108 | imx53-smd.dtb \ |
| 109 | imx6dl-sabreauto.dtb \ | ||
| 110 | imx6dl-sabresd.dtb \ | ||
| 111 | imx6dl-wandboard.dtb \ | ||
| 99 | imx6q-arm2.dtb \ | 112 | imx6q-arm2.dtb \ |
| 100 | imx6q-sabreauto.dtb \ | 113 | imx6q-sabreauto.dtb \ |
| 101 | imx6q-sabrelite.dtb \ | 114 | imx6q-sabrelite.dtb \ |
| 102 | imx6q-sabresd.dtb | 115 | imx6q-sabresd.dtb \ |
| 116 | imx6q-sbc6x.dtb | ||
| 103 | dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ | 117 | dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ |
| 104 | imx23-olinuxino.dtb \ | 118 | imx23-olinuxino.dtb \ |
| 105 | imx23-stmp378x_devb.dtb \ | 119 | imx23-stmp378x_devb.dtb \ |
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 0957645b73af..91fe4f148f80 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi | |||
| @@ -349,7 +349,7 @@ | |||
| 349 | rx_descs = <64>; | 349 | rx_descs = <64>; |
| 350 | mac_control = <0x20>; | 350 | mac_control = <0x20>; |
| 351 | slaves = <2>; | 351 | slaves = <2>; |
| 352 | cpts_active_slave = <0>; | 352 | active_slave = <0>; |
| 353 | cpts_clock_mult = <0x80000000>; | 353 | cpts_clock_mult = <0x80000000>; |
| 354 | cpts_clock_shift = <29>; | 354 | cpts_clock_shift = <29>; |
| 355 | reg = <0x4a100000 0x800 | 355 | reg = <0x4a100000 0x800 |
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index e34b280ce6ec..6403acdbb75f 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts | |||
| @@ -94,5 +94,22 @@ | |||
| 94 | spi-max-frequency = <50000000>; | 94 | spi-max-frequency = <50000000>; |
| 95 | }; | 95 | }; |
| 96 | }; | 96 | }; |
| 97 | |||
| 98 | pcie-controller { | ||
| 99 | status = "okay"; | ||
| 100 | /* | ||
| 101 | * The two PCIe units are accessible through | ||
| 102 | * both standard PCIe slots and mini-PCIe | ||
| 103 | * slots on the board. | ||
| 104 | */ | ||
| 105 | pcie@1,0 { | ||
| 106 | /* Port 0, Lane 0 */ | ||
| 107 | status = "okay"; | ||
| 108 | }; | ||
| 109 | pcie@2,0 { | ||
| 110 | /* Port 1, Lane 0 */ | ||
| 111 | status = "okay"; | ||
| 112 | }; | ||
| 113 | }; | ||
| 97 | }; | 114 | }; |
| 98 | }; | 115 | }; |
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 3234875824dc..58ee79372206 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts | |||
| @@ -33,6 +33,43 @@ | |||
| 33 | clock-frequency = <600000000>; | 33 | clock-frequency = <600000000>; |
| 34 | status = "okay"; | 34 | status = "okay"; |
| 35 | }; | 35 | }; |
| 36 | |||
| 37 | pinctrl { | ||
| 38 | pwr_led_pin: pwr-led-pin { | ||
| 39 | marvell,pins = "mpp63"; | ||
| 40 | marvell,function = "gpo"; | ||
| 41 | }; | ||
| 42 | |||
| 43 | stat_led_pins: stat-led-pins { | ||
| 44 | marvell,pins = "mpp64", "mpp65"; | ||
| 45 | marvell,function = "gpio"; | ||
| 46 | }; | ||
| 47 | }; | ||
| 48 | |||
| 49 | gpio_leds { | ||
| 50 | compatible = "gpio-leds"; | ||
| 51 | pinctrl-names = "default"; | ||
| 52 | pinctrl-0 = <&pwr_led_pin &stat_led_pins>; | ||
| 53 | |||
| 54 | green_pwr_led { | ||
| 55 | label = "mirabox:green:pwr"; | ||
| 56 | gpios = <&gpio1 31 1>; | ||
| 57 | linux,default-trigger = "heartbeat"; | ||
| 58 | }; | ||
| 59 | |||
| 60 | blue_stat_led { | ||
| 61 | label = "mirabox:blue:stat"; | ||
| 62 | gpios = <&gpio2 0 1>; | ||
| 63 | linux,default-trigger = "cpu0"; | ||
| 64 | }; | ||
| 65 | |||
| 66 | green_stat_led { | ||
| 67 | label = "mirabox:green:stat"; | ||
| 68 | gpios = <&gpio2 1 1>; | ||
| 69 | default-state = "off"; | ||
| 70 | }; | ||
| 71 | }; | ||
| 72 | |||
| 36 | mdio { | 73 | mdio { |
| 37 | phy0: ethernet-phy@0 { | 74 | phy0: ethernet-phy@0 { |
| 38 | reg = <0>; | 75 | reg = <0>; |
| @@ -70,5 +107,32 @@ | |||
| 70 | usb@d0051000 { | 107 | usb@d0051000 { |
| 71 | status = "okay"; | 108 | status = "okay"; |
| 72 | }; | 109 | }; |
| 110 | |||
| 111 | i2c@d0011000 { | ||
| 112 | status = "okay"; | ||
| 113 | clock-frequency = <100000>; | ||
| 114 | pca9505: pca9505@25 { | ||
| 115 | compatible = "nxp,pca9505"; | ||
| 116 | gpio-controller; | ||
| 117 | #gpio-cells = <2>; | ||
| 118 | reg = <0x25>; | ||
| 119 | }; | ||
| 120 | }; | ||
| 121 | |||
| 122 | pcie-controller { | ||
| 123 | status = "okay"; | ||
| 124 | |||
| 125 | /* Internal mini-PCIe connector */ | ||
| 126 | pcie@1,0 { | ||
| 127 | /* Port 0, Lane 0 */ | ||
| 128 | status = "okay"; | ||
| 129 | }; | ||
| 130 | |||
| 131 | /* Connected on the PCB to a USB 3.0 XHCI controller */ | ||
| 132 | pcie@2,0 { | ||
| 133 | /* Port 1, Lane 0 */ | ||
| 134 | status = "okay"; | ||
| 135 | }; | ||
| 136 | }; | ||
| 73 | }; | 137 | }; |
| 74 | }; | 138 | }; |
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 070bba4f2585..516dec31b469 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts | |||
| @@ -73,4 +73,15 @@ | |||
| 73 | status = "okay"; | 73 | status = "okay"; |
| 74 | }; | 74 | }; |
| 75 | }; | 75 | }; |
| 76 | |||
| 77 | gpio-keys { | ||
| 78 | compatible = "gpio-keys"; | ||
| 79 | #address-cells = <1>; | ||
| 80 | #size-cells = <0>; | ||
| 81 | button@1 { | ||
| 82 | label = "Software Button"; | ||
| 83 | linux,code = <116>; | ||
| 84 | gpios = <&gpio0 6 1>; | ||
| 85 | }; | ||
| 86 | }; | ||
| 76 | }; | 87 | }; |
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 5b708208b607..758c4ea90344 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi | |||
| @@ -181,6 +181,51 @@ | |||
| 181 | clocks = <&coreclk 0>; | 181 | clocks = <&coreclk 0>; |
| 182 | status = "disabled"; | 182 | status = "disabled"; |
| 183 | }; | 183 | }; |
| 184 | |||
| 185 | devbus-bootcs@d0010400 { | ||
| 186 | compatible = "marvell,mvebu-devbus"; | ||
| 187 | reg = <0xd0010400 0x8>; | ||
| 188 | #address-cells = <1>; | ||
| 189 | #size-cells = <1>; | ||
| 190 | clocks = <&coreclk 0>; | ||
| 191 | status = "disabled"; | ||
| 192 | }; | ||
| 193 | |||
| 194 | devbus-cs0@d0010408 { | ||
| 195 | compatible = "marvell,mvebu-devbus"; | ||
| 196 | reg = <0xd0010408 0x8>; | ||
| 197 | #address-cells = <1>; | ||
| 198 | #size-cells = <1>; | ||
| 199 | clocks = <&coreclk 0>; | ||
| 200 | status = "disabled"; | ||
| 201 | }; | ||
| 202 | |||
| 203 | devbus-cs1@d0010410 { | ||
| 204 | compatible = "marvell,mvebu-devbus"; | ||
| 205 | reg = <0xd0010410 0x8>; | ||
| 206 | #address-cells = <1>; | ||
| 207 | #size-cells = <1>; | ||
| 208 | clocks = <&coreclk 0>; | ||
| 209 | status = "disabled"; | ||
| 210 | }; | ||
| 211 | |||
| 212 | devbus-cs2@d0010418 { | ||
| 213 | compatible = "marvell,mvebu-devbus"; | ||
| 214 | reg = <0xd0010418 0x8>; | ||
| 215 | #address-cells = <1>; | ||
| 216 | #size-cells = <1>; | ||
| 217 | clocks = <&coreclk 0>; | ||
| 218 | status = "disabled"; | ||
| 219 | }; | ||
| 220 | |||
| 221 | devbus-cs3@d0010420 { | ||
| 222 | compatible = "marvell,mvebu-devbus"; | ||
| 223 | reg = <0xd0010420 0x8>; | ||
| 224 | #address-cells = <1>; | ||
| 225 | #size-cells = <1>; | ||
| 226 | clocks = <&coreclk 0>; | ||
| 227 | status = "disabled"; | ||
| 228 | }; | ||
| 184 | }; | 229 | }; |
| 185 | }; | 230 | }; |
| 186 | 231 | ||
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index a195debb67d3..18f6eb47cc50 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi | |||
| @@ -159,5 +159,63 @@ | |||
| 159 | clocks = <&coreclk 0>; | 159 | clocks = <&coreclk 0>; |
| 160 | }; | 160 | }; |
| 161 | 161 | ||
| 162 | thermal@d0018300 { | ||
| 163 | compatible = "marvell,armada370-thermal"; | ||
| 164 | reg = <0xd0018300 0x4 | ||
| 165 | 0xd0018304 0x4>; | ||
| 166 | status = "okay"; | ||
| 167 | }; | ||
| 168 | |||
| 169 | pcie-controller { | ||
| 170 | compatible = "marvell,armada-370-pcie"; | ||
| 171 | status = "disabled"; | ||
| 172 | device_type = "pci"; | ||
| 173 | |||
| 174 | #address-cells = <3>; | ||
| 175 | #size-cells = <2>; | ||
| 176 | |||
| 177 | bus-range = <0x00 0xff>; | ||
| 178 | |||
| 179 | reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>; | ||
| 180 | |||
| 181 | reg-names = "pcie0.0", "pcie1.0"; | ||
| 182 | |||
| 183 | ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ | ||
| 184 | 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */ | ||
| 185 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | ||
| 186 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | ||
| 187 | |||
| 188 | pcie@1,0 { | ||
| 189 | device_type = "pci"; | ||
| 190 | assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; | ||
| 191 | reg = <0x0800 0 0 0 0>; | ||
| 192 | #address-cells = <3>; | ||
| 193 | #size-cells = <2>; | ||
| 194 | #interrupt-cells = <1>; | ||
| 195 | ranges; | ||
| 196 | interrupt-map-mask = <0 0 0 0>; | ||
| 197 | interrupt-map = <0 0 0 0 &mpic 58>; | ||
| 198 | marvell,pcie-port = <0>; | ||
| 199 | marvell,pcie-lane = <0>; | ||
| 200 | clocks = <&gateclk 5>; | ||
| 201 | status = "disabled"; | ||
| 202 | }; | ||
| 203 | |||
| 204 | pcie@2,0 { | ||
| 205 | device_type = "pci"; | ||
| 206 | assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>; | ||
| 207 | reg = <0x1000 0 0 0 0>; | ||
| 208 | #address-cells = <3>; | ||
| 209 | #size-cells = <2>; | ||
| 210 | #interrupt-cells = <1>; | ||
| 211 | ranges; | ||
| 212 | interrupt-map-mask = <0 0 0 0>; | ||
| 213 | interrupt-map = <0 0 0 0 &mpic 62>; | ||
| 214 | marvell,pcie-port = <1>; | ||
| 215 | marvell,pcie-lane = <0>; | ||
| 216 | clocks = <&gateclk 9>; | ||
| 217 | status = "disabled"; | ||
| 218 | }; | ||
| 219 | }; | ||
| 162 | }; | 220 | }; |
| 163 | }; | 221 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index e83505e4c236..54cc5bb705fb 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts | |||
| @@ -121,5 +121,38 @@ | |||
| 121 | spi-max-frequency = <20000000>; | 121 | spi-max-frequency = <20000000>; |
| 122 | }; | 122 | }; |
| 123 | }; | 123 | }; |
| 124 | |||
| 125 | pcie-controller { | ||
| 126 | status = "okay"; | ||
| 127 | |||
| 128 | /* | ||
| 129 | * All 6 slots are physically present as | ||
| 130 | * standard PCIe slots on the board. | ||
| 131 | */ | ||
| 132 | pcie@1,0 { | ||
| 133 | /* Port 0, Lane 0 */ | ||
| 134 | status = "okay"; | ||
| 135 | }; | ||
| 136 | pcie@2,0 { | ||
| 137 | /* Port 0, Lane 1 */ | ||
| 138 | status = "okay"; | ||
| 139 | }; | ||
| 140 | pcie@3,0 { | ||
| 141 | /* Port 0, Lane 2 */ | ||
| 142 | status = "okay"; | ||
| 143 | }; | ||
| 144 | pcie@4,0 { | ||
| 145 | /* Port 0, Lane 3 */ | ||
| 146 | status = "okay"; | ||
| 147 | }; | ||
| 148 | pcie@9,0 { | ||
| 149 | /* Port 2, Lane 0 */ | ||
| 150 | status = "okay"; | ||
| 151 | }; | ||
| 152 | pcie@10,0 { | ||
| 153 | /* Port 3, Lane 0 */ | ||
| 154 | status = "okay"; | ||
| 155 | }; | ||
| 156 | }; | ||
| 124 | }; | 157 | }; |
| 125 | }; | 158 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 1c8afe2ffebc..04f28a712b98 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts | |||
| @@ -109,5 +109,55 @@ | |||
| 109 | spi-max-frequency = <108000000>; | 109 | spi-max-frequency = <108000000>; |
| 110 | }; | 110 | }; |
| 111 | }; | 111 | }; |
| 112 | |||
| 113 | devbus-bootcs@d0010400 { | ||
| 114 | status = "okay"; | ||
| 115 | ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */ | ||
| 116 | |||
| 117 | /* Device Bus parameters are required */ | ||
| 118 | |||
| 119 | /* Read parameters */ | ||
| 120 | devbus,bus-width = <8>; | ||
| 121 | devbus,turn-off-ps = <60000>; | ||
| 122 | devbus,badr-skew-ps = <0>; | ||
| 123 | devbus,acc-first-ps = <124000>; | ||
| 124 | devbus,acc-next-ps = <248000>; | ||
| 125 | devbus,rd-setup-ps = <0>; | ||
| 126 | devbus,rd-hold-ps = <0>; | ||
| 127 | |||
| 128 | /* Write parameters */ | ||
| 129 | devbus,sync-enable = <0>; | ||
| 130 | devbus,wr-high-ps = <60000>; | ||
| 131 | devbus,wr-low-ps = <60000>; | ||
| 132 | devbus,ale-wr-ps = <60000>; | ||
| 133 | |||
| 134 | /* NOR 16 MiB */ | ||
| 135 | nor@0 { | ||
| 136 | compatible = "cfi-flash"; | ||
| 137 | reg = <0 0x1000000>; | ||
| 138 | bank-width = <2>; | ||
| 139 | }; | ||
| 140 | }; | ||
| 141 | |||
| 142 | pcie-controller { | ||
| 143 | status = "okay"; | ||
| 144 | |||
| 145 | /* | ||
| 146 | * The 3 slots are physically present as | ||
| 147 | * standard PCIe slots on the board. | ||
| 148 | */ | ||
| 149 | pcie@1,0 { | ||
| 150 | /* Port 0, Lane 0 */ | ||
| 151 | status = "okay"; | ||
| 152 | }; | ||
| 153 | pcie@9,0 { | ||
| 154 | /* Port 2, Lane 0 */ | ||
| 155 | status = "okay"; | ||
| 156 | }; | ||
| 157 | pcie@10,0 { | ||
| 158 | /* Port 3, Lane 0 */ | ||
| 159 | status = "okay"; | ||
| 160 | }; | ||
| 161 | }; | ||
| 112 | }; | 162 | }; |
| 113 | }; | 163 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index f56c40599f5b..c2c78459a4d4 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi | |||
| @@ -76,5 +76,109 @@ | |||
| 76 | #interrupts-cells = <2>; | 76 | #interrupts-cells = <2>; |
| 77 | interrupts = <87>, <88>, <89>; | 77 | interrupts = <87>, <88>, <89>; |
| 78 | }; | 78 | }; |
| 79 | |||
| 80 | /* | ||
| 81 | * MV78230 has 2 PCIe units Gen2.0: One unit can be | ||
| 82 | * configured as x4 or quad x1 lanes. One unit is | ||
| 83 | * x4/x1. | ||
| 84 | */ | ||
| 85 | pcie-controller { | ||
| 86 | compatible = "marvell,armada-xp-pcie"; | ||
| 87 | status = "disabled"; | ||
| 88 | device_type = "pci"; | ||
| 89 | |||
| 90 | #address-cells = <3>; | ||
| 91 | #size-cells = <2>; | ||
| 92 | |||
| 93 | bus-range = <0x00 0xff>; | ||
| 94 | |||
| 95 | ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ | ||
| 96 | 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */ | ||
| 97 | 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */ | ||
| 98 | 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */ | ||
| 99 | 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */ | ||
| 100 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | ||
| 101 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | ||
| 102 | |||
| 103 | pcie@1,0 { | ||
| 104 | device_type = "pci"; | ||
| 105 | assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; | ||
| 106 | reg = <0x0800 0 0 0 0>; | ||
| 107 | #address-cells = <3>; | ||
| 108 | #size-cells = <2>; | ||
| 109 | #interrupt-cells = <1>; | ||
| 110 | ranges; | ||
| 111 | interrupt-map-mask = <0 0 0 0>; | ||
| 112 | interrupt-map = <0 0 0 0 &mpic 58>; | ||
| 113 | marvell,pcie-port = <0>; | ||
| 114 | marvell,pcie-lane = <0>; | ||
| 115 | clocks = <&gateclk 5>; | ||
| 116 | status = "disabled"; | ||
| 117 | }; | ||
| 118 | |||
| 119 | pcie@2,0 { | ||
| 120 | device_type = "pci"; | ||
| 121 | assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>; | ||
| 122 | reg = <0x1000 0 0 0 0>; | ||
| 123 | #address-cells = <3>; | ||
| 124 | #size-cells = <2>; | ||
| 125 | #interrupt-cells = <1>; | ||
| 126 | ranges; | ||
| 127 | interrupt-map-mask = <0 0 0 0>; | ||
| 128 | interrupt-map = <0 0 0 0 &mpic 59>; | ||
| 129 | marvell,pcie-port = <0>; | ||
| 130 | marvell,pcie-lane = <1>; | ||
| 131 | clocks = <&gateclk 6>; | ||
| 132 | status = "disabled"; | ||
| 133 | }; | ||
| 134 | |||
| 135 | pcie@3,0 { | ||
| 136 | device_type = "pci"; | ||
| 137 | assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>; | ||
| 138 | reg = <0x1800 0 0 0 0>; | ||
| 139 | #address-cells = <3>; | ||
| 140 | #size-cells = <2>; | ||
| 141 | #interrupt-cells = <1>; | ||
| 142 | ranges; | ||
| 143 | interrupt-map-mask = <0 0 0 0>; | ||
| 144 | interrupt-map = <0 0 0 0 &mpic 60>; | ||
| 145 | marvell,pcie-port = <0>; | ||
| 146 | marvell,pcie-lane = <2>; | ||
| 147 | clocks = <&gateclk 7>; | ||
| 148 | status = "disabled"; | ||
| 149 | }; | ||
| 150 | |||
| 151 | pcie@4,0 { | ||
| 152 | device_type = "pci"; | ||
| 153 | assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>; | ||
| 154 | reg = <0x2000 0 0 0 0>; | ||
| 155 | #address-cells = <3>; | ||
| 156 | #size-cells = <2>; | ||
| 157 | #interrupt-cells = <1>; | ||
| 158 | ranges; | ||
| 159 | interrupt-map-mask = <0 0 0 0>; | ||
| 160 | interrupt-map = <0 0 0 0 &mpic 61>; | ||
| 161 | marvell,pcie-port = <0>; | ||
| 162 | marvell,pcie-lane = <3>; | ||
| 163 | clocks = <&gateclk 8>; | ||
| 164 | status = "disabled"; | ||
| 165 | }; | ||
| 166 | |||
| 167 | pcie@9,0 { | ||
| 168 | device_type = "pci"; | ||
| 169 | assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>; | ||
| 170 | reg = <0x4800 0 0 0 0>; | ||
| 171 | #address-cells = <3>; | ||
| 172 | #size-cells = <2>; | ||
| 173 | #interrupt-cells = <1>; | ||
| 174 | ranges; | ||
| 175 | interrupt-map-mask = <0 0 0 0>; | ||
| 176 | interrupt-map = <0 0 0 0 &mpic 99>; | ||
| 177 | marvell,pcie-port = <2>; | ||
| 178 | marvell,pcie-lane = <0>; | ||
| 179 | clocks = <&gateclk 26>; | ||
| 180 | status = "disabled"; | ||
| 181 | }; | ||
| 182 | }; | ||
| 79 | }; | 183 | }; |
| 80 | }; | 184 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index f8f2b787d2b0..885bf229eef7 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi | |||
| @@ -96,5 +96,127 @@ | |||
| 96 | clocks = <&gateclk 1>; | 96 | clocks = <&gateclk 1>; |
| 97 | status = "disabled"; | 97 | status = "disabled"; |
| 98 | }; | 98 | }; |
| 99 | |||
| 100 | /* | ||
| 101 | * MV78260 has 3 PCIe units Gen2.0: Two units can be | ||
| 102 | * configured as x4 or quad x1 lanes. One unit is | ||
| 103 | * x4/x1. | ||
| 104 | */ | ||
| 105 | pcie-controller { | ||
| 106 | compatible = "marvell,armada-xp-pcie"; | ||
| 107 | status = "disabled"; | ||
| 108 | device_type = "pci"; | ||
| 109 | |||
| 110 | #address-cells = <3>; | ||
| 111 | #size-cells = <2>; | ||
| 112 | |||
| 113 | bus-range = <0x00 0xff>; | ||
| 114 | |||
| 115 | ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ | ||
| 116 | 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */ | ||
| 117 | 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */ | ||
| 118 | 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */ | ||
| 119 | 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */ | ||
| 120 | 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */ | ||
| 121 | 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */ | ||
| 122 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | ||
| 123 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | ||
| 124 | |||
| 125 | pcie@1,0 { | ||
| 126 | device_type = "pci"; | ||
| 127 | assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; | ||
| 128 | reg = <0x0800 0 0 0 0>; | ||
| 129 | #address-cells = <3>; | ||
| 130 | #size-cells = <2>; | ||
| 131 | #interrupt-cells = <1>; | ||
| 132 | ranges; | ||
| 133 | interrupt-map-mask = <0 0 0 0>; | ||
| 134 | interrupt-map = <0 0 0 0 &mpic 58>; | ||
| 135 | marvell,pcie-port = <0>; | ||
| 136 | marvell,pcie-lane = <0>; | ||
| 137 | clocks = <&gateclk 5>; | ||
| 138 | status = "disabled"; | ||
| 139 | }; | ||
| 140 | |||
| 141 | pcie@2,0 { | ||
| 142 | device_type = "pci"; | ||
| 143 | assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>; | ||
| 144 | reg = <0x1000 0 0 0 0>; | ||
| 145 | #address-cells = <3>; | ||
| 146 | #size-cells = <2>; | ||
| 147 | #interrupt-cells = <1>; | ||
| 148 | ranges; | ||
| 149 | interrupt-map-mask = <0 0 0 0>; | ||
| 150 | interrupt-map = <0 0 0 0 &mpic 59>; | ||
| 151 | marvell,pcie-port = <0>; | ||
| 152 | marvell,pcie-lane = <1>; | ||
| 153 | clocks = <&gateclk 6>; | ||
| 154 | status = "disabled"; | ||
| 155 | }; | ||
| 156 | |||
| 157 | pcie@3,0 { | ||
| 158 | device_type = "pci"; | ||
| 159 | assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>; | ||
| 160 | reg = <0x1800 0 0 0 0>; | ||
| 161 | #address-cells = <3>; | ||
| 162 | #size-cells = <2>; | ||
| 163 | #interrupt-cells = <1>; | ||
| 164 | ranges; | ||
| 165 | interrupt-map-mask = <0 0 0 0>; | ||
| 166 | interrupt-map = <0 0 0 0 &mpic 60>; | ||
| 167 | marvell,pcie-port = <0>; | ||
| 168 | marvell,pcie-lane = <2>; | ||
| 169 | clocks = <&gateclk 7>; | ||
| 170 | status = "disabled"; | ||
| 171 | }; | ||
| 172 | |||
| 173 | pcie@4,0 { | ||
| 174 | device_type = "pci"; | ||
| 175 | assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>; | ||
| 176 | reg = <0x2000 0 0 0 0>; | ||
| 177 | #address-cells = <3>; | ||
| 178 | #size-cells = <2>; | ||
| 179 | #interrupt-cells = <1>; | ||
| 180 | ranges; | ||
| 181 | interrupt-map-mask = <0 0 0 0>; | ||
| 182 | interrupt-map = <0 0 0 0 &mpic 61>; | ||
| 183 | marvell,pcie-port = <0>; | ||
| 184 | marvell,pcie-lane = <3>; | ||
| 185 | clocks = <&gateclk 8>; | ||
| 186 | status = "disabled"; | ||
| 187 | }; | ||
| 188 | |||
| 189 | pcie@9,0 { | ||
| 190 | device_type = "pci"; | ||
| 191 | assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>; | ||
| 192 | reg = <0x4800 0 0 0 0>; | ||
| 193 | #address-cells = <3>; | ||
| 194 | #size-cells = <2>; | ||
| 195 | #interrupt-cells = <1>; | ||
| 196 | ranges; | ||
| 197 | interrupt-map-mask = <0 0 0 0>; | ||
| 198 | interrupt-map = <0 0 0 0 &mpic 99>; | ||
| 199 | marvell,pcie-port = <2>; | ||
| 200 | marvell,pcie-lane = <0>; | ||
| 201 | clocks = <&gateclk 26>; | ||
| 202 | status = "disabled"; | ||
| 203 | }; | ||
| 204 | |||
| 205 | pcie@10,0 { | ||
| 206 | device_type = "pci"; | ||
| 207 | assigned-addresses = <0x82000800 0 0xd0082000 0 0x2000>; | ||
| 208 | reg = <0x5000 0 0 0 0>; | ||
| 209 | #address-cells = <3>; | ||
| 210 | #size-cells = <2>; | ||
| 211 | #interrupt-cells = <1>; | ||
| 212 | ranges; | ||
| 213 | interrupt-map-mask = <0 0 0 0>; | ||
| 214 | interrupt-map = <0 0 0 0 &mpic 103>; | ||
| 215 | marvell,pcie-port = <3>; | ||
| 216 | marvell,pcie-lane = <0>; | ||
| 217 | clocks = <&gateclk 27>; | ||
| 218 | status = "disabled"; | ||
| 219 | }; | ||
| 220 | }; | ||
| 99 | }; | 221 | }; |
| 100 | }; | 222 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 936c25dc32b0..23a5ac4490a8 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi | |||
| @@ -111,5 +111,193 @@ | |||
| 111 | clocks = <&gateclk 1>; | 111 | clocks = <&gateclk 1>; |
| 112 | status = "disabled"; | 112 | status = "disabled"; |
| 113 | }; | 113 | }; |
| 114 | |||
| 115 | /* | ||
| 116 | * MV78460 has 4 PCIe units Gen2.0: Two units can be | ||
| 117 | * configured as x4 or quad x1 lanes. Two units are | ||
| 118 | * x4/x1. | ||
| 119 | */ | ||
| 120 | pcie-controller { | ||
| 121 | compatible = "marvell,armada-xp-pcie"; | ||
| 122 | status = "disabled"; | ||
| 123 | device_type = "pci"; | ||
| 124 | |||
| 125 | #address-cells = <3>; | ||
| 126 | #size-cells = <2>; | ||
| 127 | |||
| 128 | bus-range = <0x00 0xff>; | ||
| 129 | |||
| 130 | ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ | ||
| 131 | 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */ | ||
| 132 | 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */ | ||
| 133 | 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */ | ||
| 134 | 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */ | ||
| 135 | 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */ | ||
| 136 | 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */ | ||
| 137 | 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */ | ||
| 138 | 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */ | ||
| 139 | 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */ | ||
| 140 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | ||
| 141 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | ||
| 142 | |||
| 143 | pcie@1,0 { | ||
| 144 | device_type = "pci"; | ||
| 145 | assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; | ||
| 146 | reg = <0x0800 0 0 0 0>; | ||
| 147 | #address-cells = <3>; | ||
| 148 | #size-cells = <2>; | ||
| 149 | #interrupt-cells = <1>; | ||
| 150 | ranges; | ||
| 151 | interrupt-map-mask = <0 0 0 0>; | ||
| 152 | interrupt-map = <0 0 0 0 &mpic 58>; | ||
| 153 | marvell,pcie-port = <0>; | ||
| 154 | marvell,pcie-lane = <0>; | ||
| 155 | clocks = <&gateclk 5>; | ||
| 156 | status = "disabled"; | ||
| 157 | }; | ||
| 158 | |||
| 159 | pcie@2,0 { | ||
| 160 | device_type = "pci"; | ||
| 161 | assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>; | ||
| 162 | reg = <0x1000 0 0 0 0>; | ||
| 163 | #address-cells = <3>; | ||
| 164 | #size-cells = <2>; | ||
| 165 | #interrupt-cells = <1>; | ||
| 166 | ranges; | ||
| 167 | interrupt-map-mask = <0 0 0 0>; | ||
| 168 | interrupt-map = <0 0 0 0 &mpic 59>; | ||
| 169 | marvell,pcie-port = <0>; | ||
| 170 | marvell,pcie-lane = <1>; | ||
| 171 | clocks = <&gateclk 6>; | ||
| 172 | status = "disabled"; | ||
| 173 | }; | ||
| 174 | |||
| 175 | pcie@3,0 { | ||
| 176 | device_type = "pci"; | ||
| 177 | assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>; | ||
| 178 | reg = <0x1800 0 0 0 0>; | ||
| 179 | #address-cells = <3>; | ||
| 180 | #size-cells = <2>; | ||
| 181 | #interrupt-cells = <1>; | ||
| 182 | ranges; | ||
| 183 | interrupt-map-mask = <0 0 0 0>; | ||
| 184 | interrupt-map = <0 0 0 0 &mpic 60>; | ||
| 185 | marvell,pcie-port = <0>; | ||
| 186 | marvell,pcie-lane = <2>; | ||
| 187 | clocks = <&gateclk 7>; | ||
| 188 | status = "disabled"; | ||
| 189 | }; | ||
| 190 | |||
| 191 | pcie@4,0 { | ||
| 192 | device_type = "pci"; | ||
| 193 | assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>; | ||
| 194 | reg = <0x2000 0 0 0 0>; | ||
| 195 | #address-cells = <3>; | ||
| 196 | #size-cells = <2>; | ||
| 197 | #interrupt-cells = <1>; | ||
| 198 | ranges; | ||
| 199 | interrupt-map-mask = <0 0 0 0>; | ||
| 200 | interrupt-map = <0 0 0 0 &mpic 61>; | ||
| 201 | marvell,pcie-port = <0>; | ||
| 202 | marvell,pcie-lane = <3>; | ||
| 203 | clocks = <&gateclk 8>; | ||
| 204 | status = "disabled"; | ||
| 205 | }; | ||
| 206 | |||
| 207 | pcie@5,0 { | ||
| 208 | device_type = "pci"; | ||
| 209 | assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>; | ||
| 210 | reg = <0x2800 0 0 0 0>; | ||
| 211 | #address-cells = <3>; | ||
| 212 | #size-cells = <2>; | ||
| 213 | #interrupt-cells = <1>; | ||
| 214 | ranges; | ||
| 215 | interrupt-map-mask = <0 0 0 0>; | ||
| 216 | interrupt-map = <0 0 0 0 &mpic 62>; | ||
| 217 | marvell,pcie-port = <1>; | ||
| 218 | marvell,pcie-lane = <0>; | ||
| 219 | clocks = <&gateclk 9>; | ||
| 220 | status = "disabled"; | ||
| 221 | }; | ||
| 222 | |||
| 223 | pcie@6,0 { | ||
| 224 | device_type = "pci"; | ||
| 225 | assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>; | ||
| 226 | reg = <0x3000 0 0 0 0>; | ||
| 227 | #address-cells = <3>; | ||
| 228 | #size-cells = <2>; | ||
| 229 | #interrupt-cells = <1>; | ||
| 230 | ranges; | ||
| 231 | interrupt-map-mask = <0 0 0 0>; | ||
| 232 | interrupt-map = <0 0 0 0 &mpic 63>; | ||
| 233 | marvell,pcie-port = <1>; | ||
| 234 | marvell,pcie-lane = <1>; | ||
| 235 | clocks = <&gateclk 10>; | ||
| 236 | status = "disabled"; | ||
| 237 | }; | ||
| 238 | |||
| 239 | pcie@7,0 { | ||
| 240 | device_type = "pci"; | ||
| 241 | assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>; | ||
| 242 | reg = <0x3800 0 0 0 0>; | ||
| 243 | #address-cells = <3>; | ||
| 244 | #size-cells = <2>; | ||
| 245 | #interrupt-cells = <1>; | ||
| 246 | ranges; | ||
| 247 | interrupt-map-mask = <0 0 0 0>; | ||
| 248 | interrupt-map = <0 0 0 0 &mpic 64>; | ||
| 249 | marvell,pcie-port = <1>; | ||
| 250 | marvell,pcie-lane = <2>; | ||
| 251 | clocks = <&gateclk 11>; | ||
| 252 | status = "disabled"; | ||
| 253 | }; | ||
| 254 | |||
| 255 | pcie@8,0 { | ||
| 256 | device_type = "pci"; | ||
| 257 | assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>; | ||
| 258 | reg = <0x4000 0 0 0 0>; | ||
| 259 | #address-cells = <3>; | ||
| 260 | #size-cells = <2>; | ||
| 261 | #interrupt-cells = <1>; | ||
| 262 | ranges; | ||
| 263 | interrupt-map-mask = <0 0 0 0>; | ||
| 264 | interrupt-map = <0 0 0 0 &mpic 65>; | ||
| 265 | marvell,pcie-port = <1>; | ||
| 266 | marvell,pcie-lane = <3>; | ||
| 267 | clocks = <&gateclk 12>; | ||
| 268 | status = "disabled"; | ||
| 269 | }; | ||
| 270 | pcie@9,0 { | ||
| 271 | device_type = "pci"; | ||
| 272 | assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>; | ||
| 273 | reg = <0x4800 0 0 0 0>; | ||
| 274 | #address-cells = <3>; | ||
| 275 | #size-cells = <2>; | ||
| 276 | #interrupt-cells = <1>; | ||
| 277 | ranges; | ||
| 278 | interrupt-map-mask = <0 0 0 0>; | ||
| 279 | interrupt-map = <0 0 0 0 &mpic 99>; | ||
| 280 | marvell,pcie-port = <2>; | ||
| 281 | marvell,pcie-lane = <0>; | ||
| 282 | clocks = <&gateclk 26>; | ||
| 283 | status = "disabled"; | ||
| 284 | }; | ||
| 285 | |||
| 286 | pcie@10,0 { | ||
| 287 | device_type = "pci"; | ||
| 288 | assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>; | ||
| 289 | reg = <0x5000 0 0 0 0>; | ||
| 290 | #address-cells = <3>; | ||
| 291 | #size-cells = <2>; | ||
| 292 | #interrupt-cells = <1>; | ||
| 293 | ranges; | ||
| 294 | interrupt-map-mask = <0 0 0 0>; | ||
| 295 | interrupt-map = <0 0 0 0 &mpic 103>; | ||
| 296 | marvell,pcie-port = <3>; | ||
| 297 | marvell,pcie-lane = <0>; | ||
| 298 | clocks = <&gateclk 27>; | ||
| 299 | status = "disabled"; | ||
| 300 | }; | ||
| 301 | }; | ||
| 114 | }; | 302 | }; |
| 115 | }; | 303 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 3818a82176a2..9d04f04d4e39 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | |||
| @@ -139,5 +139,43 @@ | |||
| 139 | usb@d0051000 { | 139 | usb@d0051000 { |
| 140 | status = "okay"; | 140 | status = "okay"; |
| 141 | }; | 141 | }; |
| 142 | |||
| 143 | devbus-bootcs@d0010400 { | ||
| 144 | status = "okay"; | ||
| 145 | ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ | ||
| 146 | |||
| 147 | /* Device Bus parameters are required */ | ||
| 148 | |||
| 149 | /* Read parameters */ | ||
| 150 | devbus,bus-width = <8>; | ||
| 151 | devbus,turn-off-ps = <60000>; | ||
| 152 | devbus,badr-skew-ps = <0>; | ||
| 153 | devbus,acc-first-ps = <124000>; | ||
| 154 | devbus,acc-next-ps = <248000>; | ||
| 155 | devbus,rd-setup-ps = <0>; | ||
| 156 | devbus,rd-hold-ps = <0>; | ||
| 157 | |||
| 158 | /* Write parameters */ | ||
| 159 | devbus,sync-enable = <0>; | ||
| 160 | devbus,wr-high-ps = <60000>; | ||
| 161 | devbus,wr-low-ps = <60000>; | ||
| 162 | devbus,ale-wr-ps = <60000>; | ||
| 163 | |||
| 164 | /* NOR 128 MiB */ | ||
| 165 | nor@0 { | ||
| 166 | compatible = "cfi-flash"; | ||
| 167 | reg = <0 0x8000000>; | ||
| 168 | bank-width = <2>; | ||
| 169 | }; | ||
| 170 | }; | ||
| 171 | |||
| 172 | pcie-controller { | ||
| 173 | status = "okay"; | ||
| 174 | /* Internal mini-PCIe connector */ | ||
| 175 | pcie@1,0 { | ||
| 176 | /* Port 0, Lane 0 */ | ||
| 177 | status = "okay"; | ||
| 178 | }; | ||
| 179 | }; | ||
| 142 | }; | 180 | }; |
| 143 | }; | 181 | }; |
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index ca00d8326c87..29dfeb6d4a26 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi | |||
| @@ -151,5 +151,11 @@ | |||
| 151 | status = "disabled"; | 151 | status = "disabled"; |
| 152 | }; | 152 | }; |
| 153 | 153 | ||
| 154 | thermal@d00182b0 { | ||
| 155 | compatible = "marvell,armadaxp-thermal"; | ||
| 156 | reg = <0xd00182b0 0x4 | ||
| 157 | 0xd00184d0 0x4>; | ||
| 158 | status = "okay"; | ||
| 159 | }; | ||
| 154 | }; | 160 | }; |
| 155 | }; | 161 | }; |
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts new file mode 100644 index 000000000000..c7aebba4e8e7 --- /dev/null +++ b/arch/arm/boot/dts/at91-ariag25.dts | |||
| @@ -0,0 +1,171 @@ | |||
| 1 | /* | ||
| 2 | * at91-ariag25.dts - Device Tree file for Acme Systems Aria G25 (AT91SAM9G25 based) | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Douglas Gilbert <dgilbert@interlog.com>, | ||
| 5 | * Robert Nelson <robertcnelson@gmail.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /dts-v1/; | ||
| 10 | /include/ "at91sam9g25.dtsi" | ||
| 11 | |||
| 12 | / { | ||
| 13 | model = "Acme Systems Aria G25"; | ||
| 14 | compatible = "acme,ariag25", "atmel,at91sam9x5ek", | ||
| 15 | "atmel,at91sam9x5", "atmel,at91sam9"; | ||
| 16 | |||
| 17 | aliases { | ||
| 18 | serial0 = &dbgu; | ||
| 19 | serial1 = &usart0; | ||
| 20 | serial2 = &usart1; | ||
| 21 | serial3 = &usart2; | ||
| 22 | serial4 = &usart3; | ||
| 23 | serial5 = &uart0; | ||
| 24 | }; | ||
| 25 | |||
| 26 | chosen { | ||
| 27 | bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | memory { | ||
| 31 | /* 128 MB, change this for 256 MB revision */ | ||
| 32 | reg = <0x20000000 0x8000000>; | ||
| 33 | }; | ||
| 34 | |||
| 35 | clocks { | ||
| 36 | #address-cells = <1>; | ||
| 37 | #size-cells = <1>; | ||
| 38 | ranges; | ||
| 39 | |||
| 40 | main_clock: clock@0 { | ||
| 41 | compatible = "atmel,osc", "fixed-clock"; | ||
| 42 | clock-frequency = <12000000>; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | |||
| 46 | ahb { | ||
| 47 | apb { | ||
| 48 | mmc0: mmc@f0008000 { | ||
| 49 | /* N.B. Aria has no SD card detect (CD), assumed present */ | ||
| 50 | |||
| 51 | pinctrl-0 = < | ||
| 52 | &pinctrl_mmc0_slot0_clk_cmd_dat0 | ||
| 53 | &pinctrl_mmc0_slot0_dat1_3>; | ||
| 54 | status = "okay"; | ||
| 55 | slot@0 { | ||
| 56 | reg = <0>; | ||
| 57 | bus-width = <4>; | ||
| 58 | }; | ||
| 59 | }; | ||
| 60 | |||
| 61 | i2c0: i2c@f8010000 { | ||
| 62 | status = "okay"; | ||
| 63 | }; | ||
| 64 | |||
| 65 | i2c1: i2c@f8014000 { | ||
| 66 | status = "okay"; | ||
| 67 | }; | ||
| 68 | |||
| 69 | /* TWD2+TCLK2 hidden behind ethernet, so no i2c2 */ | ||
| 70 | |||
| 71 | usart0: serial@f801c000 { | ||
| 72 | pinctrl-0 = <&pinctrl_usart0 | ||
| 73 | &pinctrl_usart0_rts | ||
| 74 | &pinctrl_usart0_cts>; | ||
| 75 | status = "okay"; | ||
| 76 | }; | ||
| 77 | |||
| 78 | usart1: serial@f8020000 { | ||
| 79 | pinctrl-0 = <&pinctrl_usart1 | ||
| 80 | /* &pinctrl_usart1_rts */ | ||
| 81 | /* &pinctrl_usart1_cts */ | ||
| 82 | >; | ||
| 83 | status = "okay"; | ||
| 84 | }; | ||
| 85 | |||
| 86 | usart2: serial@f8024000 { | ||
| 87 | /* cannot activate RTS2+CTS2, clash with | ||
| 88 | * ethernet on PB0 and PB1 */ | ||
| 89 | pinctrl-0 = <&pinctrl_usart2>; | ||
| 90 | status = "okay"; | ||
| 91 | }; | ||
| 92 | |||
| 93 | usart3: serial@f8028000 { | ||
| 94 | compatible = "atmel,at91sam9260-usart"; | ||
| 95 | reg = <0xf8028000 0x200>; | ||
| 96 | interrupts = <8 4 5>; | ||
| 97 | pinctrl-names = "default"; | ||
| 98 | pinctrl-0 = <&pinctrl_usart3 | ||
| 99 | /* &pinctrl_usart3_rts */ | ||
| 100 | /* &pinctrl_usart3_cts */ | ||
| 101 | >; | ||
| 102 | status = "okay"; | ||
| 103 | }; | ||
| 104 | |||
| 105 | macb0: ethernet@f802c000 { | ||
| 106 | phy-mode = "rmii"; | ||
| 107 | /* | ||
| 108 | * following can be overwritten by bootloader: | ||
| 109 | * for example u-boot 'ftd set' command | ||
| 110 | */ | ||
| 111 | local-mac-address = [00 00 00 00 00 00]; | ||
| 112 | status = "okay"; | ||
| 113 | }; | ||
| 114 | |||
| 115 | uart0: serial@f8040000 { | ||
| 116 | compatible = "atmel,at91sam9260-usart"; | ||
| 117 | reg = <0xf8040000 0x200>; | ||
| 118 | interrupts = <15 4 5>; | ||
| 119 | pinctrl-names = "default"; | ||
| 120 | pinctrl-0 = <&pinctrl_uart0>; | ||
| 121 | status = "okay"; | ||
| 122 | }; | ||
| 123 | |||
| 124 | adc0: adc@f804c000 { | ||
| 125 | status = "okay"; | ||
| 126 | atmel,adc-channels-used = <0xf>; | ||
| 127 | atmel,adc-num-channels = <4>; | ||
| 128 | }; | ||
| 129 | |||
| 130 | dbgu: serial@fffff200 { | ||
| 131 | status = "okay"; | ||
| 132 | }; | ||
| 133 | |||
| 134 | pinctrl@fffff400 { | ||
| 135 | w1_0 { | ||
| 136 | pinctrl_w1_0: w1_0-0 { | ||
| 137 | atmel,pins = <0 21 0x0 0x1>; /* PA21 PIO, pull-up */ | ||
| 138 | }; | ||
| 139 | }; | ||
| 140 | }; | ||
| 141 | }; | ||
| 142 | |||
| 143 | usb0: ohci@00600000 { | ||
| 144 | status = "okay"; | ||
| 145 | num-ports = <3>; | ||
| 146 | }; | ||
| 147 | |||
| 148 | usb1: ehci@00700000 { | ||
| 149 | status = "okay"; | ||
| 150 | }; | ||
| 151 | }; | ||
| 152 | |||
| 153 | leds { | ||
| 154 | compatible = "gpio-leds"; | ||
| 155 | |||
| 156 | /* little green LED in middle of Aria G25 module */ | ||
| 157 | aria_led { | ||
| 158 | label = "aria_led"; | ||
| 159 | gpios = <&pioB 8 0>; /* PB8 */ | ||
| 160 | linux,default-trigger = "heartbeat"; | ||
| 161 | }; | ||
| 162 | |||
| 163 | }; | ||
| 164 | |||
| 165 | onewire@0 { | ||
| 166 | compatible = "w1-gpio"; | ||
| 167 | gpios = <&pioA 21 1>; | ||
| 168 | pinctrl-names = "default"; | ||
| 169 | pinctrl-0 = <&pinctrl_w1_0>; | ||
| 170 | }; | ||
| 171 | }; | ||
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index b0268a5f4b4e..5d3ed5aafc69 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | gpio3 = &pioD; | 29 | gpio3 = &pioD; |
| 30 | tcb0 = &tcb0; | 30 | tcb0 = &tcb0; |
| 31 | tcb1 = &tcb1; | 31 | tcb1 = &tcb1; |
| 32 | i2c0 = &i2c0; | ||
| 32 | ssc0 = &ssc0; | 33 | ssc0 = &ssc0; |
| 33 | ssc1 = &ssc1; | 34 | ssc1 = &ssc1; |
| 34 | ssc2 = &ssc2; | 35 | ssc2 = &ssc2; |
| @@ -91,6 +92,17 @@ | |||
| 91 | interrupts = <20 4 0 21 4 0 22 4 0>; | 92 | interrupts = <20 4 0 21 4 0 22 4 0>; |
| 92 | }; | 93 | }; |
| 93 | 94 | ||
| 95 | i2c0: i2c@fffb8000 { | ||
| 96 | compatible = "atmel,at91rm9200-i2c"; | ||
| 97 | reg = <0xfffb8000 0x4000>; | ||
| 98 | interrupts = <12 4 6>; | ||
| 99 | pinctrl-names = "default"; | ||
| 100 | pinctrl-0 = <&pinctrl_twi>; | ||
| 101 | #address-cells = <1>; | ||
| 102 | #size-cells = <0>; | ||
| 103 | status = "disabled"; | ||
| 104 | }; | ||
| 105 | |||
| 94 | mmc0: mmc@fffb4000 { | 106 | mmc0: mmc@fffb4000 { |
| 95 | compatible = "atmel,hsmci"; | 107 | compatible = "atmel,hsmci"; |
| 96 | reg = <0xfffb4000 0x4000>; | 108 | reg = <0xfffb4000 0x4000>; |
| @@ -365,6 +377,20 @@ | |||
| 365 | }; | 377 | }; |
| 366 | }; | 378 | }; |
| 367 | 379 | ||
| 380 | twi { | ||
| 381 | pinctrl_twi: twi-0 { | ||
| 382 | atmel,pins = | ||
| 383 | <0 25 0x1 0x2 /* PA25 periph A with multi drive */ | ||
| 384 | 0 26 0x1 0x2>; /* PA26 periph A with multi drive */ | ||
| 385 | }; | ||
| 386 | |||
| 387 | pinctrl_twi_gpio: twi_gpio-0 { | ||
| 388 | atmel,pins = | ||
| 389 | <0 25 0x0 0x2 /* PA25 GPIO with multi drive */ | ||
| 390 | 0 26 0x0 0x2>; /* PA26 GPIO with multi drive */ | ||
| 391 | }; | ||
| 392 | }; | ||
| 393 | |||
| 368 | pioA: gpio@fffff400 { | 394 | pioA: gpio@fffff400 { |
| 369 | compatible = "atmel,at91rm9200-gpio"; | 395 | compatible = "atmel,at91rm9200-gpio"; |
| 370 | reg = <0xfffff400 0x200>; | 396 | reg = <0xfffff400 0x200>; |
| @@ -500,6 +526,8 @@ | |||
| 500 | i2c-gpio,sda-open-drain; | 526 | i2c-gpio,sda-open-drain; |
| 501 | i2c-gpio,scl-open-drain; | 527 | i2c-gpio,scl-open-drain; |
| 502 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | 528 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| 529 | pinctrl-names = "default"; | ||
| 530 | pinctrl-0 = <&pinctrl_twi_gpio>; | ||
| 503 | #address-cells = <1>; | 531 | #address-cells = <1>; |
| 504 | #size-cells = <0>; | 532 | #size-cells = <0>; |
| 505 | status = "disabled"; | 533 | status = "disabled"; |
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index cb7bcc51608d..70b5ccbac234 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi | |||
| @@ -158,8 +158,8 @@ | |||
| 158 | usart1 { | 158 | usart1 { |
| 159 | pinctrl_usart1: usart1-0 { | 159 | pinctrl_usart1: usart1-0 { |
| 160 | atmel,pins = | 160 | atmel,pins = |
| 161 | <2 6 0x1 0x1 /* PB6 periph A with pullup */ | 161 | <1 6 0x1 0x1 /* PB6 periph A with pullup */ |
| 162 | 2 7 0x1 0x0>; /* PB7 periph A */ | 162 | 1 7 0x1 0x0>; /* PB7 periph A */ |
| 163 | }; | 163 | }; |
| 164 | 164 | ||
| 165 | pinctrl_usart1_rts: usart1_rts-0 { | 165 | pinctrl_usart1_rts: usart1_rts-0 { |
| @@ -194,18 +194,18 @@ | |||
| 194 | usart3 { | 194 | usart3 { |
| 195 | pinctrl_usart3: usart3-0 { | 195 | pinctrl_usart3: usart3-0 { |
| 196 | atmel,pins = | 196 | atmel,pins = |
| 197 | <2 10 0x1 0x1 /* PB10 periph A with pullup */ | 197 | <1 10 0x1 0x1 /* PB10 periph A with pullup */ |
| 198 | 2 11 0x1 0x0>; /* PB11 periph A */ | 198 | 1 11 0x1 0x0>; /* PB11 periph A */ |
| 199 | }; | 199 | }; |
| 200 | 200 | ||
| 201 | pinctrl_usart3_rts: usart3_rts-0 { | 201 | pinctrl_usart3_rts: usart3_rts-0 { |
| 202 | atmel,pins = | 202 | atmel,pins = |
| 203 | <3 8 0x2 0x0>; /* PB8 periph B */ | 203 | <2 8 0x2 0x0>; /* PC8 periph B */ |
| 204 | }; | 204 | }; |
| 205 | 205 | ||
| 206 | pinctrl_usart3_cts: usart3_cts-0 { | 206 | pinctrl_usart3_cts: usart3_cts-0 { |
| 207 | atmel,pins = | 207 | atmel,pins = |
| 208 | <3 10 0x2 0x0>; /* PB10 periph B */ | 208 | <2 10 0x2 0x0>; /* PC10 periph B */ |
| 209 | }; | 209 | }; |
| 210 | }; | 210 | }; |
| 211 | 211 | ||
| @@ -220,8 +220,8 @@ | |||
| 220 | uart1 { | 220 | uart1 { |
| 221 | pinctrl_uart1: uart1-0 { | 221 | pinctrl_uart1: uart1-0 { |
| 222 | atmel,pins = | 222 | atmel,pins = |
| 223 | <2 12 0x1 0x1 /* PB12 periph A with pullup */ | 223 | <1 12 0x1 0x1 /* PB12 periph A with pullup */ |
| 224 | 2 13 0x1 0x0>; /* PB13 periph A */ | 224 | 1 13 0x1 0x0>; /* PB13 periph A */ |
| 225 | }; | 225 | }; |
| 226 | }; | 226 | }; |
| 227 | 227 | ||
| @@ -322,6 +322,24 @@ | |||
| 322 | }; | 322 | }; |
| 323 | }; | 323 | }; |
| 324 | 324 | ||
| 325 | spi0 { | ||
| 326 | pinctrl_spi0: spi0-0 { | ||
| 327 | atmel,pins = | ||
| 328 | <0 0 0x1 0x0 /* PA0 periph A SPI0_MISO pin */ | ||
| 329 | 0 1 0x1 0x0 /* PA1 periph A SPI0_MOSI pin */ | ||
| 330 | 0 2 0x1 0x0>; /* PA2 periph A SPI0_SPCK pin */ | ||
| 331 | }; | ||
| 332 | }; | ||
| 333 | |||
| 334 | spi1 { | ||
| 335 | pinctrl_spi1: spi1-0 { | ||
| 336 | atmel,pins = | ||
| 337 | <1 0 0x1 0x0 /* PB0 periph A SPI1_MISO pin */ | ||
| 338 | 1 1 0x1 0x0 /* PB1 periph A SPI1_MOSI pin */ | ||
| 339 | 1 2 0x1 0x0>; /* PB2 periph A SPI1_SPCK pin */ | ||
| 340 | }; | ||
| 341 | }; | ||
| 342 | |||
| 325 | pioA: gpio@fffff400 { | 343 | pioA: gpio@fffff400 { |
| 326 | compatible = "atmel,at91rm9200-gpio"; | 344 | compatible = "atmel,at91rm9200-gpio"; |
| 327 | reg = <0xfffff400 0x200>; | 345 | reg = <0xfffff400 0x200>; |
| @@ -471,6 +489,28 @@ | |||
| 471 | status = "disabled"; | 489 | status = "disabled"; |
| 472 | }; | 490 | }; |
| 473 | 491 | ||
| 492 | spi0: spi@fffc8000 { | ||
| 493 | #address-cells = <1>; | ||
| 494 | #size-cells = <0>; | ||
| 495 | compatible = "atmel,at91rm9200-spi"; | ||
| 496 | reg = <0xfffc8000 0x200>; | ||
| 497 | interrupts = <12 4 3>; | ||
| 498 | pinctrl-names = "default"; | ||
| 499 | pinctrl-0 = <&pinctrl_spi0>; | ||
| 500 | status = "disabled"; | ||
| 501 | }; | ||
| 502 | |||
| 503 | spi1: spi@fffcc000 { | ||
| 504 | #address-cells = <1>; | ||
| 505 | #size-cells = <0>; | ||
| 506 | compatible = "atmel,at91rm9200-spi"; | ||
| 507 | reg = <0xfffcc000 0x200>; | ||
| 508 | interrupts = <13 4 3>; | ||
| 509 | pinctrl-names = "default"; | ||
| 510 | pinctrl-0 = <&pinctrl_spi1>; | ||
| 511 | status = "disabled"; | ||
| 512 | }; | ||
| 513 | |||
| 474 | adc0: adc@fffe0000 { | 514 | adc0: adc@fffe0000 { |
| 475 | compatible = "atmel,at91sam9260-adc"; | 515 | compatible = "atmel,at91sam9260-adc"; |
| 476 | reg = <0xfffe0000 0x100>; | 516 | reg = <0xfffe0000 0x100>; |
| @@ -484,6 +524,9 @@ | |||
| 484 | atmel,adc-drdy-mask = <0x10000>; | 524 | atmel,adc-drdy-mask = <0x10000>; |
| 485 | atmel,adc-status-register = <0x1c>; | 525 | atmel,adc-status-register = <0x1c>; |
| 486 | atmel,adc-trigger-register = <0x04>; | 526 | atmel,adc-trigger-register = <0x04>; |
| 527 | atmel,adc-res = <8 10>; | ||
| 528 | atmel,adc-res-names = "lowres", "highres"; | ||
| 529 | atmel,adc-use-res = "highres"; | ||
| 487 | 530 | ||
| 488 | trigger@0 { | 531 | trigger@0 { |
| 489 | trigger-name = "timer-counter-0"; | 532 | trigger-name = "timer-counter-0"; |
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 271d4de026e9..94b58ab2cc08 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi | |||
| @@ -303,6 +303,24 @@ | |||
| 303 | }; | 303 | }; |
| 304 | }; | 304 | }; |
| 305 | 305 | ||
| 306 | spi0 { | ||
| 307 | pinctrl_spi0: spi0-0 { | ||
| 308 | atmel,pins = | ||
| 309 | <0 0 0x2 0x0 /* PA0 periph B SPI0_MISO pin */ | ||
| 310 | 0 1 0x2 0x0 /* PA1 periph B SPI0_MOSI pin */ | ||
| 311 | 0 2 0x2 0x0>; /* PA2 periph B SPI0_SPCK pin */ | ||
| 312 | }; | ||
| 313 | }; | ||
| 314 | |||
| 315 | spi1 { | ||
| 316 | pinctrl_spi1: spi1-0 { | ||
| 317 | atmel,pins = | ||
| 318 | <1 12 0x1 0x0 /* PB12 periph A SPI1_MISO pin */ | ||
| 319 | 1 13 0x1 0x0 /* PB13 periph A SPI1_MOSI pin */ | ||
| 320 | 1 14 0x1 0x0>; /* PB14 periph A SPI1_SPCK pin */ | ||
| 321 | }; | ||
| 322 | }; | ||
| 323 | |||
| 306 | pioA: gpio@fffff200 { | 324 | pioA: gpio@fffff200 { |
| 307 | compatible = "atmel,at91rm9200-gpio"; | 325 | compatible = "atmel,at91rm9200-gpio"; |
| 308 | reg = <0xfffff200 0x200>; | 326 | reg = <0xfffff200 0x200>; |
| @@ -462,6 +480,28 @@ | |||
| 462 | reg = <0xfffffd40 0x10>; | 480 | reg = <0xfffffd40 0x10>; |
| 463 | status = "disabled"; | 481 | status = "disabled"; |
| 464 | }; | 482 | }; |
| 483 | |||
| 484 | spi0: spi@fffa4000 { | ||
| 485 | #address-cells = <1>; | ||
| 486 | #size-cells = <0>; | ||
| 487 | compatible = "atmel,at91rm9200-spi"; | ||
| 488 | reg = <0xfffa4000 0x200>; | ||
| 489 | interrupts = <14 4 3>; | ||
| 490 | pinctrl-names = "default"; | ||
| 491 | pinctrl-0 = <&pinctrl_spi0>; | ||
| 492 | status = "disabled"; | ||
| 493 | }; | ||
| 494 | |||
| 495 | spi1: spi@fffa8000 { | ||
| 496 | #address-cells = <1>; | ||
| 497 | #size-cells = <0>; | ||
| 498 | compatible = "atmel,at91rm9200-spi"; | ||
| 499 | reg = <0xfffa8000 0x200>; | ||
| 500 | interrupts = <15 4 3>; | ||
| 501 | pinctrl-names = "default"; | ||
| 502 | pinctrl-0 = <&pinctrl_spi1>; | ||
| 503 | status = "disabled"; | ||
| 504 | }; | ||
| 465 | }; | 505 | }; |
| 466 | 506 | ||
| 467 | nand0: nand@40000000 { | 507 | nand0: nand@40000000 { |
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 1eb08728f527..3b82d91e7fcc 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts | |||
| @@ -79,6 +79,16 @@ | |||
| 79 | }; | 79 | }; |
| 80 | }; | 80 | }; |
| 81 | }; | 81 | }; |
| 82 | |||
| 83 | spi0: spi@fffa4000 { | ||
| 84 | status = "okay"; | ||
| 85 | cs-gpios = <&pioA 5 0>, <0>, <0>, <0>; | ||
| 86 | mtd_dataflash@0 { | ||
| 87 | compatible = "atmel,at45", "atmel,dataflash"; | ||
| 88 | spi-max-frequency = <50000000>; | ||
| 89 | reg = <0>; | ||
| 90 | }; | ||
| 91 | }; | ||
| 82 | }; | 92 | }; |
| 83 | 93 | ||
| 84 | nand0: nand@40000000 { | 94 | nand0: nand@40000000 { |
| @@ -155,8 +165,6 @@ | |||
| 155 | 165 | ||
| 156 | gpio_keys { | 166 | gpio_keys { |
| 157 | compatible = "gpio-keys"; | 167 | compatible = "gpio-keys"; |
| 158 | #address-cells = <1>; | ||
| 159 | #size-cells = <0>; | ||
| 160 | 168 | ||
| 161 | left_click { | 169 | left_click { |
| 162 | label = "left_click"; | 170 | label = "left_click"; |
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi index fbe7a7089c2a..28467fd6bf96 100644 --- a/arch/arm/boot/dts/at91sam9g15.dtsi +++ b/arch/arm/boot/dts/at91sam9g15.dtsi | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Atmel AT91SAM9G15 SoC"; | 12 | model = "Atmel AT91SAM9G15 SoC"; |
| 13 | compatible = "atmel, at91sam9g15, atmel,at91sam9x5"; | 13 | compatible = "atmel,at91sam9g15", "atmel,at91sam9x5"; |
| 14 | 14 | ||
| 15 | ahb { | 15 | ahb { |
| 16 | apb { | 16 | apb { |
diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts index 86dd3f6d938f..5427b2dba87e 100644 --- a/arch/arm/boot/dts/at91sam9g15ek.dts +++ b/arch/arm/boot/dts/at91sam9g15ek.dts | |||
| @@ -11,6 +11,6 @@ | |||
| 11 | /include/ "at91sam9x5ek.dtsi" | 11 | /include/ "at91sam9x5ek.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | model = "Atmel AT91SAM9G25-EK"; | 14 | model = "Atmel AT91SAM9G15-EK"; |
| 15 | compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; | 15 | compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; |
| 16 | }; | 16 | }; |
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index da15e83e7f17..6a92c5baef8c 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi | |||
| @@ -96,6 +96,16 @@ | |||
| 96 | status = "okay"; | 96 | status = "okay"; |
| 97 | pinctrl-0 = <&pinctrl_ssc0_tx>; | 97 | pinctrl-0 = <&pinctrl_ssc0_tx>; |
| 98 | }; | 98 | }; |
| 99 | |||
| 100 | spi0: spi@fffc8000 { | ||
| 101 | status = "okay"; | ||
| 102 | cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; | ||
| 103 | mtd_dataflash@0 { | ||
| 104 | compatible = "atmel,at45", "atmel,dataflash"; | ||
| 105 | spi-max-frequency = <50000000>; | ||
| 106 | reg = <1>; | ||
| 107 | }; | ||
| 108 | }; | ||
| 99 | }; | 109 | }; |
| 100 | 110 | ||
| 101 | nand0: nand@40000000 { | 111 | nand0: nand@40000000 { |
| @@ -167,8 +177,6 @@ | |||
| 167 | 177 | ||
| 168 | gpio_keys { | 178 | gpio_keys { |
| 169 | compatible = "gpio-keys"; | 179 | compatible = "gpio-keys"; |
| 170 | #address-cells = <1>; | ||
| 171 | #size-cells = <0>; | ||
| 172 | 180 | ||
| 173 | btn3 { | 181 | btn3 { |
| 174 | label = "Button 3"; | 182 | label = "Button 3"; |
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi index 05a718fb83c4..5fd32df03f25 100644 --- a/arch/arm/boot/dts/at91sam9g25.dtsi +++ b/arch/arm/boot/dts/at91sam9g25.dtsi | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Atmel AT91SAM9G25 SoC"; | 12 | model = "Atmel AT91SAM9G25 SoC"; |
| 13 | compatible = "atmel, at91sam9g25, atmel,at91sam9x5"; | 13 | compatible = "atmel,at91sam9g25", "atmel,at91sam9x5"; |
| 14 | 14 | ||
| 15 | ahb { | 15 | ahb { |
| 16 | apb { | 16 | apb { |
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts index c5ab16fba059..a1c511fecdc1 100644 --- a/arch/arm/boot/dts/at91sam9g25ek.dts +++ b/arch/arm/boot/dts/at91sam9g25ek.dts | |||
| @@ -13,4 +13,13 @@ | |||
| 13 | / { | 13 | / { |
| 14 | model = "Atmel AT91SAM9G25-EK"; | 14 | model = "Atmel AT91SAM9G25-EK"; |
| 15 | compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; | 15 | compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; |
| 16 | |||
| 17 | ahb { | ||
| 18 | apb { | ||
| 19 | macb0: ethernet@f802c000 { | ||
| 20 | phy-mode = "rmii"; | ||
| 21 | status = "okay"; | ||
| 22 | }; | ||
| 23 | }; | ||
| 24 | }; | ||
| 16 | }; | 25 | }; |
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi index f9d14a722794..d6fa8af50724 100644 --- a/arch/arm/boot/dts/at91sam9g35.dtsi +++ b/arch/arm/boot/dts/at91sam9g35.dtsi | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Atmel AT91SAM9G35 SoC"; | 12 | model = "Atmel AT91SAM9G35 SoC"; |
| 13 | compatible = "atmel, at91sam9g35, atmel,at91sam9x5"; | 13 | compatible = "atmel,at91sam9g35", "atmel,at91sam9x5"; |
| 14 | 14 | ||
| 15 | ahb { | 15 | ahb { |
| 16 | apb { | 16 | apb { |
diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts index 95944bdd798d..6f58ab8d21f5 100644 --- a/arch/arm/boot/dts/at91sam9g35ek.dts +++ b/arch/arm/boot/dts/at91sam9g35ek.dts | |||
| @@ -13,4 +13,13 @@ | |||
| 13 | / { | 13 | / { |
| 14 | model = "Atmel AT91SAM9G35-EK"; | 14 | model = "Atmel AT91SAM9G35-EK"; |
| 15 | compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; | 15 | compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; |
| 16 | |||
| 17 | ahb { | ||
| 18 | apb { | ||
| 19 | macb0: ethernet@f802c000 { | ||
| 20 | phy-mode = "rmii"; | ||
| 21 | status = "okay"; | ||
| 22 | }; | ||
| 23 | }; | ||
| 24 | }; | ||
| 16 | }; | 25 | }; |
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 6b1d4cab24c2..f8f7370e8669 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi | |||
| @@ -322,6 +322,24 @@ | |||
| 322 | }; | 322 | }; |
| 323 | }; | 323 | }; |
| 324 | 324 | ||
| 325 | spi0 { | ||
| 326 | pinctrl_spi0: spi0-0 { | ||
| 327 | atmel,pins = | ||
| 328 | <1 0 0x1 0x0 /* PB0 periph A SPI0_MISO pin */ | ||
| 329 | 1 1 0x1 0x0 /* PB1 periph A SPI0_MOSI pin */ | ||
| 330 | 1 2 0x1 0x0>; /* PB2 periph A SPI0_SPCK pin */ | ||
| 331 | }; | ||
| 332 | }; | ||
| 333 | |||
| 334 | spi1 { | ||
| 335 | pinctrl_spi1: spi1-0 { | ||
| 336 | atmel,pins = | ||
| 337 | <1 14 0x1 0x0 /* PB14 periph A SPI1_MISO pin */ | ||
| 338 | 1 15 0x1 0x0 /* PB15 periph A SPI1_MOSI pin */ | ||
| 339 | 1 16 0x1 0x0>; /* PB16 periph A SPI1_SPCK pin */ | ||
| 340 | }; | ||
| 341 | }; | ||
| 342 | |||
| 325 | pioA: gpio@fffff200 { | 343 | pioA: gpio@fffff200 { |
| 326 | compatible = "atmel,at91rm9200-gpio"; | 344 | compatible = "atmel,at91rm9200-gpio"; |
| 327 | reg = <0xfffff200 0x200>; | 345 | reg = <0xfffff200 0x200>; |
| @@ -484,6 +502,9 @@ | |||
| 484 | atmel,adc-drdy-mask = <0x10000>; | 502 | atmel,adc-drdy-mask = <0x10000>; |
| 485 | atmel,adc-status-register = <0x1c>; | 503 | atmel,adc-status-register = <0x1c>; |
| 486 | atmel,adc-trigger-register = <0x08>; | 504 | atmel,adc-trigger-register = <0x08>; |
| 505 | atmel,adc-res = <8 10>; | ||
| 506 | atmel,adc-res-names = "lowres", "highres"; | ||
| 507 | atmel,adc-use-res = "highres"; | ||
| 487 | 508 | ||
| 488 | trigger@0 { | 509 | trigger@0 { |
| 489 | trigger-name = "external-rising"; | 510 | trigger-name = "external-rising"; |
| @@ -531,6 +552,28 @@ | |||
| 531 | reg = <0xfffffd40 0x10>; | 552 | reg = <0xfffffd40 0x10>; |
| 532 | status = "disabled"; | 553 | status = "disabled"; |
| 533 | }; | 554 | }; |
| 555 | |||
| 556 | spi0: spi@fffa4000 { | ||
| 557 | #address-cells = <1>; | ||
| 558 | #size-cells = <0>; | ||
| 559 | compatible = "atmel,at91rm9200-spi"; | ||
| 560 | reg = <0xfffa4000 0x200>; | ||
| 561 | interrupts = <14 4 3>; | ||
| 562 | pinctrl-names = "default"; | ||
| 563 | pinctrl-0 = <&pinctrl_spi0>; | ||
| 564 | status = "disabled"; | ||
| 565 | }; | ||
| 566 | |||
| 567 | spi1: spi@fffa8000 { | ||
| 568 | #address-cells = <1>; | ||
| 569 | #size-cells = <0>; | ||
| 570 | compatible = "atmel,at91rm9200-spi"; | ||
| 571 | reg = <0xfffa8000 0x200>; | ||
| 572 | interrupts = <15 4 3>; | ||
| 573 | pinctrl-names = "default"; | ||
| 574 | pinctrl-0 = <&pinctrl_spi1>; | ||
| 575 | status = "disabled"; | ||
| 576 | }; | ||
| 534 | }; | 577 | }; |
| 535 | 578 | ||
| 536 | nand0: nand@40000000 { | 579 | nand0: nand@40000000 { |
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 20c31913c270..51d9251b5bbe 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts | |||
| @@ -102,6 +102,16 @@ | |||
| 102 | }; | 102 | }; |
| 103 | }; | 103 | }; |
| 104 | }; | 104 | }; |
| 105 | |||
| 106 | spi0: spi@fffa4000{ | ||
| 107 | status = "okay"; | ||
| 108 | cs-gpios = <&pioB 3 0>, <0>, <0>, <0>; | ||
| 109 | mtd_dataflash@0 { | ||
| 110 | compatible = "atmel,at45", "atmel,dataflash"; | ||
| 111 | spi-max-frequency = <13000000>; | ||
| 112 | reg = <0>; | ||
| 113 | }; | ||
| 114 | }; | ||
| 105 | }; | 115 | }; |
| 106 | 116 | ||
| 107 | nand0: nand@40000000 { | 117 | nand0: nand@40000000 { |
| @@ -162,8 +172,6 @@ | |||
| 162 | 172 | ||
| 163 | gpio_keys { | 173 | gpio_keys { |
| 164 | compatible = "gpio-keys"; | 174 | compatible = "gpio-keys"; |
| 165 | #address-cells = <1>; | ||
| 166 | #size-cells = <0>; | ||
| 167 | 175 | ||
| 168 | left_click { | 176 | left_click { |
| 169 | label = "left_click"; | 177 | label = "left_click"; |
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 7750f98dd764..b2961f1ea51b 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi | |||
| @@ -261,6 +261,24 @@ | |||
| 261 | }; | 261 | }; |
| 262 | }; | 262 | }; |
| 263 | 263 | ||
| 264 | spi0 { | ||
| 265 | pinctrl_spi0: spi0-0 { | ||
| 266 | atmel,pins = | ||
| 267 | <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */ | ||
| 268 | 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */ | ||
| 269 | 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */ | ||
| 270 | }; | ||
| 271 | }; | ||
| 272 | |||
| 273 | spi1 { | ||
| 274 | pinctrl_spi1: spi1-0 { | ||
| 275 | atmel,pins = | ||
| 276 | <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */ | ||
| 277 | 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */ | ||
| 278 | 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */ | ||
| 279 | }; | ||
| 280 | }; | ||
| 281 | |||
| 264 | pioA: gpio@fffff400 { | 282 | pioA: gpio@fffff400 { |
| 265 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 283 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 266 | reg = <0xfffff400 0x200>; | 284 | reg = <0xfffff400 0x200>; |
| @@ -373,6 +391,28 @@ | |||
| 373 | #size-cells = <0>; | 391 | #size-cells = <0>; |
| 374 | status = "disabled"; | 392 | status = "disabled"; |
| 375 | }; | 393 | }; |
| 394 | |||
| 395 | spi0: spi@f0000000 { | ||
| 396 | #address-cells = <1>; | ||
| 397 | #size-cells = <0>; | ||
| 398 | compatible = "atmel,at91rm9200-spi"; | ||
| 399 | reg = <0xf0000000 0x100>; | ||
| 400 | interrupts = <13 4 3>; | ||
| 401 | pinctrl-names = "default"; | ||
| 402 | pinctrl-0 = <&pinctrl_spi0>; | ||
| 403 | status = "disabled"; | ||
| 404 | }; | ||
| 405 | |||
| 406 | spi1: spi@f0004000 { | ||
| 407 | #address-cells = <1>; | ||
| 408 | #size-cells = <0>; | ||
| 409 | compatible = "atmel,at91rm9200-spi"; | ||
| 410 | reg = <0xf0004000 0x100>; | ||
| 411 | interrupts = <14 4 3>; | ||
| 412 | pinctrl-names = "default"; | ||
| 413 | pinctrl-0 = <&pinctrl_spi1>; | ||
| 414 | status = "disabled"; | ||
| 415 | }; | ||
| 376 | }; | 416 | }; |
| 377 | 417 | ||
| 378 | nand0: nand@40000000 { | 418 | nand0: nand@40000000 { |
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index d400f8de4387..d30e48bd1e9d 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts | |||
| @@ -67,6 +67,16 @@ | |||
| 67 | }; | 67 | }; |
| 68 | }; | 68 | }; |
| 69 | }; | 69 | }; |
| 70 | |||
| 71 | spi0: spi@f0000000 { | ||
| 72 | status = "okay"; | ||
| 73 | cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; | ||
| 74 | m25p80@0 { | ||
| 75 | compatible = "atmel,at25df321a"; | ||
| 76 | spi-max-frequency = <50000000>; | ||
| 77 | reg = <0>; | ||
| 78 | }; | ||
| 79 | }; | ||
| 70 | }; | 80 | }; |
| 71 | 81 | ||
| 72 | nand0: nand@40000000 { | 82 | nand0: nand@40000000 { |
| @@ -104,8 +114,6 @@ | |||
| 104 | 114 | ||
| 105 | gpio_keys { | 115 | gpio_keys { |
| 106 | compatible = "gpio-keys"; | 116 | compatible = "gpio-keys"; |
| 107 | #address-cells = <1>; | ||
| 108 | #size-cells = <0>; | ||
| 109 | 117 | ||
| 110 | enter { | 118 | enter { |
| 111 | label = "Enter"; | 119 | label = "Enter"; |
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi index 54eb33ba6d22..9ac2bc2b4f07 100644 --- a/arch/arm/boot/dts/at91sam9x25.dtsi +++ b/arch/arm/boot/dts/at91sam9x25.dtsi | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Atmel AT91SAM9X25 SoC"; | 12 | model = "Atmel AT91SAM9X25 SoC"; |
| 13 | compatible = "atmel, at91sam9x25, atmel,at91sam9x5"; | 13 | compatible = "atmel,at91sam9x25", "atmel,at91sam9x5"; |
| 14 | 14 | ||
| 15 | ahb { | 15 | ahb { |
| 16 | apb { | 16 | apb { |
diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts index af907eaa1f25..3b40d11d65e7 100644 --- a/arch/arm/boot/dts/at91sam9x25ek.dts +++ b/arch/arm/boot/dts/at91sam9x25ek.dts | |||
| @@ -13,4 +13,18 @@ | |||
| 13 | / { | 13 | / { |
| 14 | model = "Atmel AT91SAM9G25-EK"; | 14 | model = "Atmel AT91SAM9G25-EK"; |
| 15 | compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; | 15 | compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; |
| 16 | |||
| 17 | ahb { | ||
| 18 | apb { | ||
| 19 | macb0: ethernet@f802c000 { | ||
| 20 | phy-mode = "rmii"; | ||
| 21 | status = "okay"; | ||
| 22 | }; | ||
| 23 | |||
| 24 | macb1: ethernet@f8030000 { | ||
| 25 | phy-mode = "rmii"; | ||
| 26 | status = "okay"; | ||
| 27 | }; | ||
| 28 | }; | ||
| 29 | }; | ||
| 16 | }; | 30 | }; |
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi index fb102d6126ce..ba67d83d17ac 100644 --- a/arch/arm/boot/dts/at91sam9x35.dtsi +++ b/arch/arm/boot/dts/at91sam9x35.dtsi | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Atmel AT91SAM9X35 SoC"; | 12 | model = "Atmel AT91SAM9X35 SoC"; |
| 13 | compatible = "atmel, at91sam9x35, atmel,at91sam9x5"; | 13 | compatible = "atmel,at91sam9x35", "atmel,at91sam9x5"; |
| 14 | 14 | ||
| 15 | ahb { | 15 | ahb { |
| 16 | apb { | 16 | apb { |
diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts index 5ccb607b5414..6ad19a0d5424 100644 --- a/arch/arm/boot/dts/at91sam9x35ek.dts +++ b/arch/arm/boot/dts/at91sam9x35ek.dts | |||
| @@ -13,4 +13,13 @@ | |||
| 13 | / { | 13 | / { |
| 14 | model = "Atmel AT91SAM9X35-EK"; | 14 | model = "Atmel AT91SAM9X35-EK"; |
| 15 | compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; | 15 | compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; |
| 16 | |||
| 17 | ahb { | ||
| 18 | apb { | ||
| 19 | macb0: ethernet@f802c000 { | ||
| 20 | phy-mode = "rmii"; | ||
| 21 | status = "okay"; | ||
| 22 | }; | ||
| 23 | }; | ||
| 24 | }; | ||
| 16 | }; | 25 | }; |
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index a98c0d50fbbe..640b3bbbb706 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi | |||
| @@ -343,6 +343,72 @@ | |||
| 343 | }; | 343 | }; |
| 344 | }; | 344 | }; |
| 345 | 345 | ||
| 346 | spi0 { | ||
| 347 | pinctrl_spi0: spi0-0 { | ||
| 348 | atmel,pins = | ||
| 349 | <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */ | ||
| 350 | 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */ | ||
| 351 | 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */ | ||
| 352 | }; | ||
| 353 | }; | ||
| 354 | |||
| 355 | spi1 { | ||
| 356 | pinctrl_spi1: spi1-0 { | ||
| 357 | atmel,pins = | ||
| 358 | <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */ | ||
| 359 | 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */ | ||
| 360 | 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */ | ||
| 361 | }; | ||
| 362 | }; | ||
| 363 | |||
| 364 | i2c0 { | ||
| 365 | pinctrl_i2c0: i2c0-0 { | ||
| 366 | atmel,pins = | ||
| 367 | <0 30 0x1 0x0 /* PA30 periph A I2C0 data */ | ||
| 368 | 0 31 0x1 0x0>; /* PA31 periph A I2C0 clock */ | ||
| 369 | }; | ||
| 370 | }; | ||
| 371 | |||
| 372 | i2c1 { | ||
| 373 | pinctrl_i2c1: i2c1-0 { | ||
| 374 | atmel,pins = | ||
| 375 | <2 0 0x3 0x0 /* PC0 periph C I2C1 data */ | ||
| 376 | 2 1 0x3 0x0>; /* PC1 periph C I2C1 clock */ | ||
| 377 | }; | ||
| 378 | }; | ||
| 379 | |||
| 380 | i2c2 { | ||
| 381 | pinctrl_i2c2: i2c2-0 { | ||
| 382 | atmel,pins = | ||
| 383 | <1 4 0x2 0x0 /* PB4 periph B I2C2 data */ | ||
| 384 | 1 5 0x2 0x0>; /* PB5 periph B I2C2 clock */ | ||
| 385 | }; | ||
| 386 | }; | ||
| 387 | |||
| 388 | i2c_gpio0 { | ||
| 389 | pinctrl_i2c_gpio0: i2c_gpio0-0 { | ||
| 390 | atmel,pins = | ||
| 391 | <0 30 0x0 0x2 /* PA30 gpio multidrive I2C0 data */ | ||
| 392 | 0 31 0x0 0x2>; /* PA31 gpio multidrive I2C0 clock */ | ||
| 393 | }; | ||
| 394 | }; | ||
| 395 | |||
| 396 | i2c_gpio1 { | ||
| 397 | pinctrl_i2c_gpio1: i2c_gpio1-0 { | ||
| 398 | atmel,pins = | ||
| 399 | <2 0 0x0 0x2 /* PC0 gpio multidrive I2C1 data */ | ||
| 400 | 2 1 0x0 0x2>; /* PC1 gpio multidrive I2C1 clock */ | ||
| 401 | }; | ||
| 402 | }; | ||
| 403 | |||
| 404 | i2c_gpio2 { | ||
| 405 | pinctrl_i2c_gpio2: i2c_gpio2-0 { | ||
| 406 | atmel,pins = | ||
| 407 | <1 4 0x0 0x2 /* PB4 gpio multidrive I2C2 data */ | ||
| 408 | 1 5 0x0 0x2>; /* PB5 gpio multidrive I2C2 clock */ | ||
| 409 | }; | ||
| 410 | }; | ||
| 411 | |||
| 346 | pioA: gpio@fffff400 { | 412 | pioA: gpio@fffff400 { |
| 347 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 413 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 348 | reg = <0xfffff400 0x200>; | 414 | reg = <0xfffff400 0x200>; |
| @@ -471,6 +537,8 @@ | |||
| 471 | interrupts = <9 4 6>; | 537 | interrupts = <9 4 6>; |
| 472 | #address-cells = <1>; | 538 | #address-cells = <1>; |
| 473 | #size-cells = <0>; | 539 | #size-cells = <0>; |
| 540 | pinctrl-names = "default"; | ||
| 541 | pinctrl-0 = <&pinctrl_i2c0>; | ||
| 474 | status = "disabled"; | 542 | status = "disabled"; |
| 475 | }; | 543 | }; |
| 476 | 544 | ||
| @@ -480,6 +548,8 @@ | |||
| 480 | interrupts = <10 4 6>; | 548 | interrupts = <10 4 6>; |
| 481 | #address-cells = <1>; | 549 | #address-cells = <1>; |
| 482 | #size-cells = <0>; | 550 | #size-cells = <0>; |
| 551 | pinctrl-names = "default"; | ||
| 552 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 483 | status = "disabled"; | 553 | status = "disabled"; |
| 484 | }; | 554 | }; |
| 485 | 555 | ||
| @@ -489,6 +559,8 @@ | |||
| 489 | interrupts = <11 4 6>; | 559 | interrupts = <11 4 6>; |
| 490 | #address-cells = <1>; | 560 | #address-cells = <1>; |
| 491 | #size-cells = <0>; | 561 | #size-cells = <0>; |
| 562 | pinctrl-names = "default"; | ||
| 563 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 492 | status = "disabled"; | 564 | status = "disabled"; |
| 493 | }; | 565 | }; |
| 494 | 566 | ||
| @@ -505,6 +577,9 @@ | |||
| 505 | atmel,adc-drdy-mask = <0x1000000>; | 577 | atmel,adc-drdy-mask = <0x1000000>; |
| 506 | atmel,adc-status-register = <0x30>; | 578 | atmel,adc-status-register = <0x30>; |
| 507 | atmel,adc-trigger-register = <0xc0>; | 579 | atmel,adc-trigger-register = <0xc0>; |
| 580 | atmel,adc-res = <8 10>; | ||
| 581 | atmel,adc-res-names = "lowres", "highres"; | ||
| 582 | atmel,adc-use-res = "highres"; | ||
| 508 | 583 | ||
| 509 | trigger@0 { | 584 | trigger@0 { |
| 510 | trigger-name = "external-rising"; | 585 | trigger-name = "external-rising"; |
| @@ -529,6 +604,35 @@ | |||
| 529 | trigger-value = <0x6>; | 604 | trigger-value = <0x6>; |
| 530 | }; | 605 | }; |
| 531 | }; | 606 | }; |
| 607 | |||
| 608 | spi0: spi@f0000000 { | ||
| 609 | #address-cells = <1>; | ||
| 610 | #size-cells = <0>; | ||
| 611 | compatible = "atmel,at91rm9200-spi"; | ||
| 612 | reg = <0xf0000000 0x100>; | ||
| 613 | interrupts = <13 4 3>; | ||
| 614 | pinctrl-names = "default"; | ||
| 615 | pinctrl-0 = <&pinctrl_spi0>; | ||
| 616 | status = "disabled"; | ||
| 617 | }; | ||
| 618 | |||
| 619 | spi1: spi@f0004000 { | ||
| 620 | #address-cells = <1>; | ||
| 621 | #size-cells = <0>; | ||
| 622 | compatible = "atmel,at91rm9200-spi"; | ||
| 623 | reg = <0xf0004000 0x100>; | ||
| 624 | interrupts = <14 4 3>; | ||
| 625 | pinctrl-names = "default"; | ||
| 626 | pinctrl-0 = <&pinctrl_spi1>; | ||
| 627 | status = "disabled"; | ||
| 628 | }; | ||
| 629 | |||
| 630 | rtc@fffffeb0 { | ||
| 631 | compatible = "atmel,at91rm9200-rtc"; | ||
| 632 | reg = <0xfffffeb0 0x40>; | ||
| 633 | interrupts = <1 4 7>; | ||
| 634 | status = "disabled"; | ||
| 635 | }; | ||
| 532 | }; | 636 | }; |
| 533 | 637 | ||
| 534 | nand0: nand@40000000 { | 638 | nand0: nand@40000000 { |
| @@ -577,6 +681,8 @@ | |||
| 577 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | 681 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| 578 | #address-cells = <1>; | 682 | #address-cells = <1>; |
| 579 | #size-cells = <0>; | 683 | #size-cells = <0>; |
| 684 | pinctrl-names = "default"; | ||
| 685 | pinctrl-0 = <&pinctrl_i2c_gpio0>; | ||
| 580 | status = "disabled"; | 686 | status = "disabled"; |
| 581 | }; | 687 | }; |
| 582 | 688 | ||
| @@ -590,6 +696,8 @@ | |||
| 590 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | 696 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| 591 | #address-cells = <1>; | 697 | #address-cells = <1>; |
| 592 | #size-cells = <0>; | 698 | #size-cells = <0>; |
| 699 | pinctrl-names = "default"; | ||
| 700 | pinctrl-0 = <&pinctrl_i2c_gpio1>; | ||
| 593 | status = "disabled"; | 701 | status = "disabled"; |
| 594 | }; | 702 | }; |
| 595 | 703 | ||
| @@ -603,6 +711,8 @@ | |||
| 603 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | 711 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| 604 | #address-cells = <1>; | 712 | #address-cells = <1>; |
| 605 | #size-cells = <0>; | 713 | #size-cells = <0>; |
| 714 | pinctrl-names = "default"; | ||
| 715 | pinctrl-0 = <&pinctrl_i2c_gpio2>; | ||
| 606 | status = "disabled"; | 716 | status = "disabled"; |
| 607 | }; | 717 | }; |
| 608 | }; | 718 | }; |
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi index 4027ac7e4502..347a74a857f6 100644 --- a/arch/arm/boot/dts/at91sam9x5cm.dtsi +++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi | |||
| @@ -24,6 +24,16 @@ | |||
| 24 | }; | 24 | }; |
| 25 | 25 | ||
| 26 | ahb { | 26 | ahb { |
| 27 | apb { | ||
| 28 | pinctrl@fffff400 { | ||
| 29 | 1wire_cm { | ||
| 30 | pinctrl_1wire_cm: 1wire_cm-0 { | ||
| 31 | atmel,pins = <1 18 0x0 0x2>; /* PB18 multidrive, conflicts with led */ | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | |||
| 27 | nand0: nand@40000000 { | 37 | nand0: nand@40000000 { |
| 28 | nand-bus-width = <8>; | 38 | nand-bus-width = <8>; |
| 29 | nand-ecc-mode = "hw"; | 39 | nand-ecc-mode = "hw"; |
| @@ -74,4 +84,14 @@ | |||
| 74 | gpios = <&pioD 21 0>; | 84 | gpios = <&pioD 21 0>; |
| 75 | }; | 85 | }; |
| 76 | }; | 86 | }; |
| 87 | |||
| 88 | 1wire_cm { | ||
| 89 | compatible = "w1-gpio"; | ||
| 90 | gpios = <&pioB 18 0>; | ||
| 91 | linux,open-drain; | ||
| 92 | pinctrl-names = "default"; | ||
| 93 | pinctrl-0 = <&pinctrl_1wire_cm>; | ||
| 94 | status = "okay"; | ||
| 95 | }; | ||
| 96 | |||
| 77 | }; | 97 | }; |
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi index 8a7cf1d9cf5d..1fa48d2bfd80 100644 --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi +++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi | |||
| @@ -13,7 +13,7 @@ | |||
| 13 | compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; | 13 | compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; |
| 14 | 14 | ||
| 15 | chosen { | 15 | chosen { |
| 16 | bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; | 16 | bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; |
| 17 | }; | 17 | }; |
| 18 | 18 | ||
| 19 | ahb { | 19 | ahb { |
| @@ -52,23 +52,10 @@ | |||
| 52 | status = "okay"; | 52 | status = "okay"; |
| 53 | }; | 53 | }; |
| 54 | 54 | ||
| 55 | macb0: ethernet@f802c000 { | ||
| 56 | phy-mode = "rmii"; | ||
| 57 | status = "okay"; | ||
| 58 | }; | ||
| 59 | |||
| 60 | i2c0: i2c@f8010000 { | 55 | i2c0: i2c@f8010000 { |
| 61 | status = "okay"; | 56 | status = "okay"; |
| 62 | }; | 57 | }; |
| 63 | 58 | ||
| 64 | i2c1: i2c@f8014000 { | ||
| 65 | status = "okay"; | ||
| 66 | }; | ||
| 67 | |||
| 68 | i2c2: i2c@f8018000 { | ||
| 69 | status = "okay"; | ||
| 70 | }; | ||
| 71 | |||
| 72 | pinctrl@fffff400 { | 59 | pinctrl@fffff400 { |
| 73 | mmc0 { | 60 | mmc0 { |
| 74 | pinctrl_board_mmc0: mmc0-board { | 61 | pinctrl_board_mmc0: mmc0-board { |
| @@ -84,6 +71,16 @@ | |||
| 84 | }; | 71 | }; |
| 85 | }; | 72 | }; |
| 86 | }; | 73 | }; |
| 74 | |||
| 75 | spi0: spi@f0000000 { | ||
| 76 | status = "okay"; | ||
| 77 | cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; | ||
| 78 | m25p80@0 { | ||
| 79 | compatible = "atmel,at25df321a"; | ||
| 80 | spi-max-frequency = <50000000>; | ||
| 81 | reg = <0>; | ||
| 82 | }; | ||
| 83 | }; | ||
| 87 | }; | 84 | }; |
| 88 | 85 | ||
| 89 | usb0: ohci@00600000 { | 86 | usb0: ohci@00600000 { |
diff --git a/arch/arm/boot/dts/atlas6-evb.dts b/arch/arm/boot/dts/atlas6-evb.dts new file mode 100644 index 000000000000..ab042ca8dea1 --- /dev/null +++ b/arch/arm/boot/dts/atlas6-evb.dts | |||
| @@ -0,0 +1,78 @@ | |||
| 1 | /* | ||
| 2 | * DTS file for CSR SiRFatlas6 Evaluation Board | ||
| 3 | * | ||
| 4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /dts-v1/; | ||
| 10 | |||
| 11 | /include/ "atlas6.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "CSR SiRFatlas6 Evaluation Board"; | ||
| 15 | compatible = "sirf,atlas6-cb", "sirf,atlas6"; | ||
| 16 | |||
| 17 | memory { | ||
| 18 | reg = <0x00000000 0x20000000>; | ||
| 19 | }; | ||
| 20 | |||
| 21 | axi { | ||
| 22 | peri-iobg { | ||
| 23 | uart@b0060000 { | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | pinctrl-0 = <&uart1_pins_a>; | ||
| 26 | }; | ||
| 27 | spi@b00d0000 { | ||
| 28 | status = "okay"; | ||
| 29 | pinctrl-names = "default"; | ||
| 30 | pinctrl-0 = <&spi0_pins_a>; | ||
| 31 | spi@0 { | ||
| 32 | compatible = "spidev"; | ||
| 33 | reg = <0>; | ||
| 34 | spi-max-frequency = <1000000>; | ||
| 35 | }; | ||
| 36 | }; | ||
| 37 | spi@b0170000 { | ||
| 38 | pinctrl-names = "default"; | ||
| 39 | pinctrl-0 = <&spi1_pins_a>; | ||
| 40 | }; | ||
| 41 | i2c0: i2c@b00e0000 { | ||
| 42 | status = "okay"; | ||
| 43 | pinctrl-names = "default"; | ||
| 44 | pinctrl-0 = <&i2c0_pins_a>; | ||
| 45 | lcd@40 { | ||
| 46 | compatible = "sirf,lcd"; | ||
| 47 | reg = <0x40>; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | }; | ||
| 52 | disp-iobg { | ||
| 53 | lcd@90010000 { | ||
| 54 | status = "okay"; | ||
| 55 | pinctrl-names = "default"; | ||
| 56 | pinctrl-0 = <&lcd_24pins_a>; | ||
| 57 | }; | ||
| 58 | }; | ||
| 59 | }; | ||
| 60 | display: display@0 { | ||
| 61 | panels { | ||
| 62 | panel0: panel@0 { | ||
| 63 | panel-name = "Innolux TFT"; | ||
| 64 | hactive = <800>; | ||
| 65 | vactive = <480>; | ||
| 66 | left_margin = <20>; | ||
| 67 | right_margin = <234>; | ||
| 68 | upper_margin = <3>; | ||
| 69 | lower_margin = <41>; | ||
| 70 | hsync_len = <3>; | ||
| 71 | vsync_len = <2>; | ||
| 72 | pixclock = <33264000>; | ||
| 73 | sync = <3>; | ||
| 74 | timing = <0x88>; | ||
| 75 | }; | ||
| 76 | }; | ||
| 77 | }; | ||
| 78 | }; | ||
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi new file mode 100644 index 000000000000..7d1a27949c13 --- /dev/null +++ b/arch/arm/boot/dts/atlas6.dtsi | |||
| @@ -0,0 +1,668 @@ | |||
| 1 | /* | ||
| 2 | * DTS file for CSR SiRFatlas6 SoC | ||
| 3 | * | ||
| 4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /include/ "skeleton.dtsi" | ||
| 10 | / { | ||
| 11 | compatible = "sirf,atlas6"; | ||
| 12 | #address-cells = <1>; | ||
| 13 | #size-cells = <1>; | ||
| 14 | interrupt-parent = <&intc>; | ||
| 15 | |||
| 16 | cpus { | ||
| 17 | #address-cells = <1>; | ||
| 18 | #size-cells = <0>; | ||
| 19 | |||
| 20 | cpu@0 { | ||
| 21 | reg = <0x0>; | ||
| 22 | d-cache-line-size = <32>; | ||
| 23 | i-cache-line-size = <32>; | ||
| 24 | d-cache-size = <32768>; | ||
| 25 | i-cache-size = <32768>; | ||
| 26 | /* from bootloader */ | ||
| 27 | timebase-frequency = <0>; | ||
| 28 | bus-frequency = <0>; | ||
| 29 | clock-frequency = <0>; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | |||
| 33 | axi { | ||
| 34 | compatible = "simple-bus"; | ||
| 35 | #address-cells = <1>; | ||
| 36 | #size-cells = <1>; | ||
| 37 | ranges = <0x40000000 0x40000000 0x80000000>; | ||
| 38 | |||
| 39 | intc: interrupt-controller@80020000 { | ||
| 40 | #interrupt-cells = <1>; | ||
| 41 | interrupt-controller; | ||
| 42 | compatible = "sirf,prima2-intc"; | ||
| 43 | reg = <0x80020000 0x1000>; | ||
| 44 | }; | ||
| 45 | |||
| 46 | sys-iobg { | ||
| 47 | compatible = "simple-bus"; | ||
| 48 | #address-cells = <1>; | ||
| 49 | #size-cells = <1>; | ||
| 50 | ranges = <0x88000000 0x88000000 0x40000>; | ||
| 51 | |||
| 52 | clks: clock-controller@88000000 { | ||
| 53 | compatible = "sirf,atlas6-clkc"; | ||
| 54 | reg = <0x88000000 0x1000>; | ||
| 55 | interrupts = <3>; | ||
| 56 | #clock-cells = <1>; | ||
| 57 | }; | ||
| 58 | |||
| 59 | reset-controller@88010000 { | ||
| 60 | compatible = "sirf,prima2-rstc"; | ||
| 61 | reg = <0x88010000 0x1000>; | ||
| 62 | }; | ||
| 63 | |||
| 64 | rsc-controller@88020000 { | ||
| 65 | compatible = "sirf,prima2-rsc"; | ||
| 66 | reg = <0x88020000 0x1000>; | ||
| 67 | }; | ||
| 68 | }; | ||
| 69 | |||
| 70 | mem-iobg { | ||
| 71 | compatible = "simple-bus"; | ||
| 72 | #address-cells = <1>; | ||
| 73 | #size-cells = <1>; | ||
| 74 | ranges = <0x90000000 0x90000000 0x10000>; | ||
| 75 | |||
| 76 | memory-controller@90000000 { | ||
| 77 | compatible = "sirf,prima2-memc"; | ||
| 78 | reg = <0x90000000 0x10000>; | ||
| 79 | interrupts = <27>; | ||
| 80 | clocks = <&clks 5>; | ||
| 81 | }; | ||
| 82 | }; | ||
| 83 | |||
| 84 | disp-iobg { | ||
| 85 | compatible = "simple-bus"; | ||
| 86 | #address-cells = <1>; | ||
| 87 | #size-cells = <1>; | ||
| 88 | ranges = <0x90010000 0x90010000 0x30000>; | ||
| 89 | |||
| 90 | lcd@90010000 { | ||
| 91 | compatible = "sirf,prima2-lcd"; | ||
| 92 | reg = <0x90010000 0x20000>; | ||
| 93 | interrupts = <30>; | ||
| 94 | clocks = <&clks 34>; | ||
| 95 | display=<&display>; | ||
| 96 | /* later transfer to pwm */ | ||
| 97 | bl-gpio = <&gpio 7 0>; | ||
| 98 | default-panel = <&panel0>; | ||
| 99 | }; | ||
| 100 | |||
| 101 | vpp@90020000 { | ||
| 102 | compatible = "sirf,prima2-vpp"; | ||
| 103 | reg = <0x90020000 0x10000>; | ||
| 104 | interrupts = <31>; | ||
| 105 | clocks = <&clks 35>; | ||
| 106 | }; | ||
| 107 | }; | ||
| 108 | |||
| 109 | graphics-iobg { | ||
| 110 | compatible = "simple-bus"; | ||
| 111 | #address-cells = <1>; | ||
| 112 | #size-cells = <1>; | ||
| 113 | ranges = <0x98000000 0x98000000 0x8000000>; | ||
| 114 | |||
| 115 | graphics@98000000 { | ||
| 116 | compatible = "powervr,sgx510"; | ||
| 117 | reg = <0x98000000 0x8000000>; | ||
| 118 | interrupts = <6>; | ||
| 119 | clocks = <&clks 32>; | ||
| 120 | }; | ||
| 121 | }; | ||
| 122 | |||
| 123 | dsp-iobg { | ||
| 124 | compatible = "simple-bus"; | ||
| 125 | #address-cells = <1>; | ||
| 126 | #size-cells = <1>; | ||
| 127 | ranges = <0xa8000000 0xa8000000 0x2000000>; | ||
| 128 | |||
| 129 | dspif@a8000000 { | ||
| 130 | compatible = "sirf,prima2-dspif"; | ||
| 131 | reg = <0xa8000000 0x10000>; | ||
| 132 | interrupts = <9>; | ||
| 133 | }; | ||
| 134 | |||
| 135 | gps@a8010000 { | ||
| 136 | compatible = "sirf,prima2-gps"; | ||
| 137 | reg = <0xa8010000 0x10000>; | ||
| 138 | interrupts = <7>; | ||
| 139 | clocks = <&clks 9>; | ||
| 140 | }; | ||
| 141 | |||
| 142 | dsp@a9000000 { | ||
| 143 | compatible = "sirf,prima2-dsp"; | ||
| 144 | reg = <0xa9000000 0x1000000>; | ||
| 145 | interrupts = <8>; | ||
| 146 | clocks = <&clks 8>; | ||
| 147 | }; | ||
| 148 | }; | ||
| 149 | |||
| 150 | peri-iobg { | ||
| 151 | compatible = "simple-bus"; | ||
| 152 | #address-cells = <1>; | ||
| 153 | #size-cells = <1>; | ||
| 154 | ranges = <0xb0000000 0xb0000000 0x180000>, | ||
| 155 | <0x56000000 0x56000000 0x1b00000>; | ||
| 156 | |||
| 157 | timer@b0020000 { | ||
| 158 | compatible = "sirf,prima2-tick"; | ||
| 159 | reg = <0xb0020000 0x1000>; | ||
| 160 | interrupts = <0>; | ||
| 161 | }; | ||
| 162 | |||
| 163 | nand@b0030000 { | ||
| 164 | compatible = "sirf,prima2-nand"; | ||
| 165 | reg = <0xb0030000 0x10000>; | ||
| 166 | interrupts = <41>; | ||
| 167 | clocks = <&clks 26>; | ||
| 168 | }; | ||
| 169 | |||
| 170 | audio@b0040000 { | ||
| 171 | compatible = "sirf,prima2-audio"; | ||
| 172 | reg = <0xb0040000 0x10000>; | ||
| 173 | interrupts = <35>; | ||
| 174 | clocks = <&clks 27>; | ||
| 175 | }; | ||
| 176 | |||
| 177 | uart0: uart@b0050000 { | ||
| 178 | cell-index = <0>; | ||
| 179 | compatible = "sirf,prima2-uart"; | ||
| 180 | reg = <0xb0050000 0x1000>; | ||
| 181 | interrupts = <17>; | ||
| 182 | fifosize = <128>; | ||
| 183 | clocks = <&clks 13>; | ||
| 184 | }; | ||
| 185 | |||
| 186 | uart1: uart@b0060000 { | ||
| 187 | cell-index = <1>; | ||
| 188 | compatible = "sirf,prima2-uart"; | ||
| 189 | reg = <0xb0060000 0x1000>; | ||
| 190 | interrupts = <18>; | ||
| 191 | fifosize = <32>; | ||
| 192 | clocks = <&clks 14>; | ||
| 193 | }; | ||
| 194 | |||
| 195 | uart2: uart@b0070000 { | ||
| 196 | cell-index = <2>; | ||
| 197 | compatible = "sirf,prima2-uart"; | ||
| 198 | reg = <0xb0070000 0x1000>; | ||
| 199 | interrupts = <19>; | ||
| 200 | fifosize = <128>; | ||
| 201 | clocks = <&clks 15>; | ||
| 202 | }; | ||
| 203 | |||
| 204 | usp0: usp@b0080000 { | ||
| 205 | cell-index = <0>; | ||
| 206 | compatible = "sirf,prima2-usp"; | ||
| 207 | reg = <0xb0080000 0x10000>; | ||
| 208 | interrupts = <20>; | ||
| 209 | clocks = <&clks 28>; | ||
| 210 | }; | ||
| 211 | |||
| 212 | usp1: usp@b0090000 { | ||
| 213 | cell-index = <1>; | ||
| 214 | compatible = "sirf,prima2-usp"; | ||
| 215 | reg = <0xb0090000 0x10000>; | ||
| 216 | interrupts = <21>; | ||
| 217 | clocks = <&clks 29>; | ||
| 218 | }; | ||
| 219 | |||
| 220 | dmac0: dma-controller@b00b0000 { | ||
| 221 | cell-index = <0>; | ||
| 222 | compatible = "sirf,prima2-dmac"; | ||
| 223 | reg = <0xb00b0000 0x10000>; | ||
| 224 | interrupts = <12>; | ||
| 225 | clocks = <&clks 24>; | ||
| 226 | }; | ||
| 227 | |||
| 228 | dmac1: dma-controller@b0160000 { | ||
| 229 | cell-index = <1>; | ||
| 230 | compatible = "sirf,prima2-dmac"; | ||
| 231 | reg = <0xb0160000 0x10000>; | ||
| 232 | interrupts = <13>; | ||
| 233 | clocks = <&clks 25>; | ||
| 234 | }; | ||
| 235 | |||
| 236 | vip@b00C0000 { | ||
| 237 | compatible = "sirf,prima2-vip"; | ||
| 238 | reg = <0xb00C0000 0x10000>; | ||
| 239 | clocks = <&clks 31>; | ||
| 240 | }; | ||
| 241 | |||
| 242 | spi0: spi@b00d0000 { | ||
| 243 | cell-index = <0>; | ||
| 244 | compatible = "sirf,prima2-spi"; | ||
| 245 | reg = <0xb00d0000 0x10000>; | ||
| 246 | interrupts = <15>; | ||
| 247 | sirf,spi-num-chipselects = <1>; | ||
| 248 | cs-gpios = <&gpio 0 0>; | ||
| 249 | sirf,spi-dma-rx-channel = <25>; | ||
| 250 | sirf,spi-dma-tx-channel = <20>; | ||
| 251 | #address-cells = <1>; | ||
| 252 | #size-cells = <0>; | ||
| 253 | clocks = <&clks 19>; | ||
| 254 | status = "disabled"; | ||
| 255 | }; | ||
| 256 | |||
| 257 | spi1: spi@b0170000 { | ||
| 258 | cell-index = <1>; | ||
| 259 | compatible = "sirf,prima2-spi"; | ||
| 260 | reg = <0xb0170000 0x10000>; | ||
| 261 | interrupts = <16>; | ||
| 262 | clocks = <&clks 20>; | ||
| 263 | status = "disabled"; | ||
| 264 | }; | ||
| 265 | |||
| 266 | i2c0: i2c@b00e0000 { | ||
| 267 | cell-index = <0>; | ||
| 268 | compatible = "sirf,prima2-i2c"; | ||
| 269 | reg = <0xb00e0000 0x10000>; | ||
| 270 | interrupts = <24>; | ||
| 271 | #address-cells = <1>; | ||
| 272 | #size-cells = <0>; | ||
| 273 | clocks = <&clks 17>; | ||
| 274 | }; | ||
| 275 | |||
| 276 | i2c1: i2c@b00f0000 { | ||
| 277 | cell-index = <1>; | ||
| 278 | compatible = "sirf,prima2-i2c"; | ||
| 279 | reg = <0xb00f0000 0x10000>; | ||
| 280 | interrupts = <25>; | ||
| 281 | #address-cells = <1>; | ||
| 282 | #size-cells = <0>; | ||
| 283 | clocks = <&clks 18>; | ||
| 284 | }; | ||
| 285 | |||
| 286 | tsc@b0110000 { | ||
| 287 | compatible = "sirf,prima2-tsc"; | ||
| 288 | reg = <0xb0110000 0x10000>; | ||
| 289 | interrupts = <33>; | ||
| 290 | clocks = <&clks 16>; | ||
| 291 | }; | ||
| 292 | |||
| 293 | gpio: pinctrl@b0120000 { | ||
| 294 | #gpio-cells = <2>; | ||
| 295 | #interrupt-cells = <2>; | ||
| 296 | compatible = "sirf,atlas6-pinctrl"; | ||
| 297 | reg = <0xb0120000 0x10000>; | ||
| 298 | interrupts = <43 44 45 46 47>; | ||
| 299 | gpio-controller; | ||
| 300 | interrupt-controller; | ||
| 301 | |||
| 302 | lcd_16pins_a: lcd0@0 { | ||
| 303 | lcd { | ||
| 304 | sirf,pins = "lcd_16bitsgrp"; | ||
| 305 | sirf,function = "lcd_16bits"; | ||
| 306 | }; | ||
| 307 | }; | ||
| 308 | lcd_18pins_a: lcd0@1 { | ||
| 309 | lcd { | ||
| 310 | sirf,pins = "lcd_18bitsgrp"; | ||
| 311 | sirf,function = "lcd_18bits"; | ||
| 312 | }; | ||
| 313 | }; | ||
| 314 | lcd_24pins_a: lcd0@2 { | ||
| 315 | lcd { | ||
| 316 | sirf,pins = "lcd_24bitsgrp"; | ||
| 317 | sirf,function = "lcd_24bits"; | ||
| 318 | }; | ||
| 319 | }; | ||
| 320 | lcdrom_pins_a: lcdrom0@0 { | ||
| 321 | lcd { | ||
| 322 | sirf,pins = "lcdromgrp"; | ||
| 323 | sirf,function = "lcdrom"; | ||
| 324 | }; | ||
| 325 | }; | ||
| 326 | uart0_pins_a: uart0@0 { | ||
| 327 | uart { | ||
| 328 | sirf,pins = "uart0grp"; | ||
| 329 | sirf,function = "uart0"; | ||
| 330 | }; | ||
| 331 | }; | ||
| 332 | uart1_pins_a: uart1@0 { | ||
| 333 | uart { | ||
| 334 | sirf,pins = "uart1grp"; | ||
| 335 | sirf,function = "uart1"; | ||
| 336 | }; | ||
| 337 | }; | ||
| 338 | uart2_pins_a: uart2@0 { | ||
| 339 | uart { | ||
| 340 | sirf,pins = "uart2grp"; | ||
| 341 | sirf,function = "uart2"; | ||
| 342 | }; | ||
| 343 | }; | ||
| 344 | uart2_noflow_pins_a: uart2@1 { | ||
| 345 | uart { | ||
| 346 | sirf,pins = "uart2_nostreamctrlgrp"; | ||
| 347 | sirf,function = "uart2_nostreamctrl"; | ||
| 348 | }; | ||
| 349 | }; | ||
| 350 | spi0_pins_a: spi0@0 { | ||
| 351 | spi { | ||
| 352 | sirf,pins = "spi0grp"; | ||
| 353 | sirf,function = "spi0"; | ||
| 354 | }; | ||
| 355 | }; | ||
| 356 | spi1_pins_a: spi1@0 { | ||
| 357 | spi { | ||
| 358 | sirf,pins = "spi1grp"; | ||
| 359 | sirf,function = "spi1"; | ||
| 360 | }; | ||
| 361 | }; | ||
| 362 | i2c0_pins_a: i2c0@0 { | ||
| 363 | i2c { | ||
| 364 | sirf,pins = "i2c0grp"; | ||
| 365 | sirf,function = "i2c0"; | ||
| 366 | }; | ||
| 367 | }; | ||
| 368 | i2c1_pins_a: i2c1@0 { | ||
| 369 | i2c { | ||
| 370 | sirf,pins = "i2c1grp"; | ||
| 371 | sirf,function = "i2c1"; | ||
| 372 | }; | ||
| 373 | }; | ||
| 374 | pwm0_pins_a: pwm0@0 { | ||
| 375 | pwm { | ||
| 376 | sirf,pins = "pwm0grp"; | ||
| 377 | sirf,function = "pwm0"; | ||
| 378 | }; | ||
| 379 | }; | ||
| 380 | pwm1_pins_a: pwm1@0 { | ||
| 381 | pwm { | ||
| 382 | sirf,pins = "pwm1grp"; | ||
| 383 | sirf,function = "pwm1"; | ||
| 384 | }; | ||
| 385 | }; | ||
| 386 | pwm2_pins_a: pwm2@0 { | ||
| 387 | pwm { | ||
| 388 | sirf,pins = "pwm2grp"; | ||
| 389 | sirf,function = "pwm2"; | ||
| 390 | }; | ||
| 391 | }; | ||
| 392 | pwm3_pins_a: pwm3@0 { | ||
| 393 | pwm { | ||
| 394 | sirf,pins = "pwm3grp"; | ||
| 395 | sirf,function = "pwm3"; | ||
| 396 | }; | ||
| 397 | }; | ||
| 398 | pwm4_pins_a: pwm4@0 { | ||
| 399 | pwm { | ||
| 400 | sirf,pins = "pwm4grp"; | ||
| 401 | sirf,function = "pwm4"; | ||
| 402 | }; | ||
| 403 | }; | ||
| 404 | gps_pins_a: gps@0 { | ||
| 405 | gps { | ||
| 406 | sirf,pins = "gpsgrp"; | ||
| 407 | sirf,function = "gps"; | ||
| 408 | }; | ||
| 409 | }; | ||
| 410 | vip_pins_a: vip@0 { | ||
| 411 | vip { | ||
| 412 | sirf,pins = "vipgrp"; | ||
| 413 | sirf,function = "vip"; | ||
| 414 | }; | ||
| 415 | }; | ||
| 416 | sdmmc0_pins_a: sdmmc0@0 { | ||
| 417 | sdmmc0 { | ||
| 418 | sirf,pins = "sdmmc0grp"; | ||
| 419 | sirf,function = "sdmmc0"; | ||
| 420 | }; | ||
| 421 | }; | ||
| 422 | sdmmc1_pins_a: sdmmc1@0 { | ||
| 423 | sdmmc1 { | ||
| 424 | sirf,pins = "sdmmc1grp"; | ||
| 425 | sirf,function = "sdmmc1"; | ||
| 426 | }; | ||
| 427 | }; | ||
| 428 | sdmmc2_pins_a: sdmmc2@0 { | ||
| 429 | sdmmc2 { | ||
| 430 | sirf,pins = "sdmmc2grp"; | ||
| 431 | sirf,function = "sdmmc2"; | ||
| 432 | }; | ||
| 433 | }; | ||
| 434 | sdmmc2_nowp_pins_a: sdmmc2_nowp@0 { | ||
| 435 | sdmmc2_nowp { | ||
| 436 | sirf,pins = "sdmmc2_nowpgrp"; | ||
| 437 | sirf,function = "sdmmc2_nowp"; | ||
| 438 | }; | ||
| 439 | }; | ||
| 440 | sdmmc3_pins_a: sdmmc3@0 { | ||
| 441 | sdmmc3 { | ||
| 442 | sirf,pins = "sdmmc3grp"; | ||
| 443 | sirf,function = "sdmmc3"; | ||
| 444 | }; | ||
| 445 | }; | ||
| 446 | sdmmc5_pins_a: sdmmc5@0 { | ||
| 447 | sdmmc5 { | ||
| 448 | sirf,pins = "sdmmc5grp"; | ||
| 449 | sirf,function = "sdmmc5"; | ||
| 450 | }; | ||
| 451 | }; | ||
| 452 | i2s_pins_a: i2s@0 { | ||
| 453 | i2s { | ||
| 454 | sirf,pins = "i2sgrp"; | ||
| 455 | sirf,function = "i2s"; | ||
| 456 | }; | ||
| 457 | }; | ||
| 458 | i2s_no_din_pins_a: i2s_no_din@0 { | ||
| 459 | i2s_no_din { | ||
| 460 | sirf,pins = "i2s_no_dingrp"; | ||
| 461 | sirf,function = "i2s_no_din"; | ||
| 462 | }; | ||
| 463 | }; | ||
| 464 | i2s_6chn_pins_a: i2s_6chn@0 { | ||
| 465 | i2s_6chn { | ||
| 466 | sirf,pins = "i2s_6chngrp"; | ||
| 467 | sirf,function = "i2s_6chn"; | ||
| 468 | }; | ||
| 469 | }; | ||
| 470 | ac97_pins_a: ac97@0 { | ||
| 471 | ac97 { | ||
| 472 | sirf,pins = "ac97grp"; | ||
| 473 | sirf,function = "ac97"; | ||
| 474 | }; | ||
| 475 | }; | ||
| 476 | nand_pins_a: nand@0 { | ||
| 477 | nand { | ||
| 478 | sirf,pins = "nandgrp"; | ||
| 479 | sirf,function = "nand"; | ||
| 480 | }; | ||
| 481 | }; | ||
| 482 | usp0_pins_a: usp0@0 { | ||
| 483 | usp0 { | ||
| 484 | sirf,pins = "usp0grp"; | ||
| 485 | sirf,function = "usp0"; | ||
| 486 | }; | ||
| 487 | }; | ||
| 488 | usp1_pins_a: usp1@0 { | ||
| 489 | usp1 { | ||
| 490 | sirf,pins = "usp1grp"; | ||
| 491 | sirf,function = "usp1"; | ||
| 492 | }; | ||
| 493 | }; | ||
| 494 | usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 { | ||
| 495 | usb0_upli_drvbus { | ||
| 496 | sirf,pins = "usb0_upli_drvbusgrp"; | ||
| 497 | sirf,function = "usb0_upli_drvbus"; | ||
| 498 | }; | ||
| 499 | }; | ||
| 500 | usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { | ||
| 501 | usb1_utmi_drvbus { | ||
| 502 | sirf,pins = "usb1_utmi_drvbusgrp"; | ||
| 503 | sirf,function = "usb1_utmi_drvbus"; | ||
| 504 | }; | ||
| 505 | }; | ||
| 506 | warm_rst_pins_a: warm_rst@0 { | ||
| 507 | warm_rst { | ||
| 508 | sirf,pins = "warm_rstgrp"; | ||
| 509 | sirf,function = "warm_rst"; | ||
| 510 | }; | ||
| 511 | }; | ||
| 512 | pulse_count_pins_a: pulse_count@0 { | ||
| 513 | pulse_count { | ||
| 514 | sirf,pins = "pulse_countgrp"; | ||
| 515 | sirf,function = "pulse_count"; | ||
| 516 | }; | ||
| 517 | }; | ||
| 518 | cko0_rst_pins_a: cko0_rst@0 { | ||
| 519 | cko0_rst { | ||
| 520 | sirf,pins = "cko0_rstgrp"; | ||
| 521 | sirf,function = "cko0_rst"; | ||
| 522 | }; | ||
| 523 | }; | ||
| 524 | cko1_rst_pins_a: cko1_rst@0 { | ||
| 525 | cko1_rst { | ||
| 526 | sirf,pins = "cko1_rstgrp"; | ||
| 527 | sirf,function = "cko1_rst"; | ||
| 528 | }; | ||
| 529 | }; | ||
| 530 | }; | ||
| 531 | |||
| 532 | pwm@b0130000 { | ||
| 533 | compatible = "sirf,prima2-pwm"; | ||
| 534 | reg = <0xb0130000 0x10000>; | ||
| 535 | clocks = <&clks 21>; | ||
| 536 | }; | ||
| 537 | |||
| 538 | efusesys@b0140000 { | ||
| 539 | compatible = "sirf,prima2-efuse"; | ||
| 540 | reg = <0xb0140000 0x10000>; | ||
| 541 | clocks = <&clks 22>; | ||
| 542 | }; | ||
| 543 | |||
| 544 | pulsec@b0150000 { | ||
| 545 | compatible = "sirf,prima2-pulsec"; | ||
| 546 | reg = <0xb0150000 0x10000>; | ||
| 547 | interrupts = <48>; | ||
| 548 | clocks = <&clks 23>; | ||
| 549 | }; | ||
| 550 | |||
| 551 | pci-iobg { | ||
| 552 | compatible = "sirf,prima2-pciiobg", "simple-bus"; | ||
| 553 | #address-cells = <1>; | ||
| 554 | #size-cells = <1>; | ||
| 555 | ranges = <0x56000000 0x56000000 0x1b00000>; | ||
| 556 | |||
| 557 | sd0: sdhci@56000000 { | ||
| 558 | cell-index = <0>; | ||
| 559 | compatible = "sirf,prima2-sdhc"; | ||
| 560 | reg = <0x56000000 0x100000>; | ||
| 561 | interrupts = <38>; | ||
| 562 | bus-width = <8>; | ||
| 563 | clocks = <&clks 36>; | ||
| 564 | }; | ||
| 565 | |||
| 566 | sd1: sdhci@56100000 { | ||
| 567 | cell-index = <1>; | ||
| 568 | compatible = "sirf,prima2-sdhc"; | ||
| 569 | reg = <0x56100000 0x100000>; | ||
| 570 | interrupts = <38>; | ||
| 571 | status = "disabled"; | ||
| 572 | clocks = <&clks 36>; | ||
| 573 | }; | ||
| 574 | |||
| 575 | sd2: sdhci@56200000 { | ||
| 576 | cell-index = <2>; | ||
| 577 | compatible = "sirf,prima2-sdhc"; | ||
| 578 | reg = <0x56200000 0x100000>; | ||
| 579 | interrupts = <23>; | ||
| 580 | status = "disabled"; | ||
| 581 | clocks = <&clks 37>; | ||
| 582 | }; | ||
| 583 | |||
| 584 | sd3: sdhci@56300000 { | ||
| 585 | cell-index = <3>; | ||
| 586 | compatible = "sirf,prima2-sdhc"; | ||
| 587 | reg = <0x56300000 0x100000>; | ||
| 588 | interrupts = <23>; | ||
| 589 | status = "disabled"; | ||
| 590 | clocks = <&clks 37>; | ||
| 591 | }; | ||
| 592 | |||
| 593 | sd5: sdhci@56500000 { | ||
| 594 | cell-index = <5>; | ||
| 595 | compatible = "sirf,prima2-sdhc"; | ||
| 596 | reg = <0x56500000 0x100000>; | ||
| 597 | interrupts = <39>; | ||
| 598 | status = "disabled"; | ||
| 599 | clocks = <&clks 38>; | ||
| 600 | }; | ||
| 601 | |||
| 602 | pci-copy@57900000 { | ||
| 603 | compatible = "sirf,prima2-pcicp"; | ||
| 604 | reg = <0x57900000 0x100000>; | ||
| 605 | interrupts = <40>; | ||
| 606 | }; | ||
| 607 | |||
| 608 | rom-interface@57a00000 { | ||
| 609 | compatible = "sirf,prima2-romif"; | ||
| 610 | reg = <0x57a00000 0x100000>; | ||
| 611 | }; | ||
| 612 | }; | ||
| 613 | }; | ||
| 614 | |||
| 615 | rtc-iobg { | ||
| 616 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; | ||
| 617 | #address-cells = <1>; | ||
| 618 | #size-cells = <1>; | ||
| 619 | reg = <0x80030000 0x10000>; | ||
| 620 | |||
| 621 | gpsrtc@1000 { | ||
| 622 | compatible = "sirf,prima2-gpsrtc"; | ||
| 623 | reg = <0x1000 0x1000>; | ||
| 624 | interrupts = <55 56 57>; | ||
| 625 | }; | ||
| 626 | |||
| 627 | sysrtc@2000 { | ||
| 628 | compatible = "sirf,prima2-sysrtc"; | ||
| 629 | reg = <0x2000 0x1000>; | ||
| 630 | interrupts = <52 53 54>; | ||
| 631 | }; | ||
| 632 | |||
| 633 | pwrc@3000 { | ||
| 634 | compatible = "sirf,prima2-pwrc"; | ||
| 635 | reg = <0x3000 0x1000>; | ||
| 636 | interrupts = <32>; | ||
| 637 | }; | ||
| 638 | }; | ||
| 639 | |||
| 640 | uus-iobg { | ||
| 641 | compatible = "simple-bus"; | ||
| 642 | #address-cells = <1>; | ||
| 643 | #size-cells = <1>; | ||
| 644 | ranges = <0xb8000000 0xb8000000 0x40000>; | ||
| 645 | |||
| 646 | usb0: usb@b00e0000 { | ||
| 647 | compatible = "chipidea,ci13611a-prima2"; | ||
| 648 | reg = <0xb8000000 0x10000>; | ||
| 649 | interrupts = <10>; | ||
| 650 | clocks = <&clks 40>; | ||
| 651 | }; | ||
| 652 | |||
| 653 | usb1: usb@b00f0000 { | ||
| 654 | compatible = "chipidea,ci13611a-prima2"; | ||
| 655 | reg = <0xb8010000 0x10000>; | ||
| 656 | interrupts = <11>; | ||
| 657 | clocks = <&clks 41>; | ||
| 658 | }; | ||
| 659 | |||
| 660 | security@b00f0000 { | ||
| 661 | compatible = "sirf,prima2-security"; | ||
| 662 | reg = <0xb8030000 0x10000>; | ||
| 663 | interrupts = <42>; | ||
| 664 | clocks = <&clks 7>; | ||
| 665 | }; | ||
| 666 | }; | ||
| 667 | }; | ||
| 668 | }; | ||
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index ad135885bd2a..8f71f40722b9 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi | |||
| @@ -47,4 +47,12 @@ | |||
| 47 | cache-unified; | 47 | cache-unified; |
| 48 | cache-level = <2>; | 48 | cache-level = <2>; |
| 49 | }; | 49 | }; |
| 50 | |||
| 51 | timer@35006000 { | ||
| 52 | compatible = "bcm,kona-timer"; | ||
| 53 | reg = <0x35006000 0x1000>; | ||
| 54 | interrupts = <0x0 7 0x4>; | ||
| 55 | clock-frequency = <32768>; | ||
| 56 | }; | ||
| 57 | |||
| 50 | }; | 58 | }; |
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index 7e0481e2441a..f0052dccf9a8 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi | |||
| @@ -34,6 +34,11 @@ | |||
| 34 | reg = <0x7e100000 0x28>; | 34 | reg = <0x7e100000 0x28>; |
| 35 | }; | 35 | }; |
| 36 | 36 | ||
| 37 | rng { | ||
| 38 | compatible = "brcm,bcm2835-rng"; | ||
| 39 | reg = <0x7e104000 0x10>; | ||
| 40 | }; | ||
| 41 | |||
| 37 | uart@20201000 { | 42 | uart@20201000 { |
| 38 | compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; | 43 | compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; |
| 39 | reg = <0x7e201000 0x1000>; | 44 | reg = <0x7e201000 0x1000>; |
| @@ -64,6 +69,16 @@ | |||
| 64 | #interrupt-cells = <2>; | 69 | #interrupt-cells = <2>; |
| 65 | }; | 70 | }; |
| 66 | 71 | ||
| 72 | spi: spi@20204000 { | ||
| 73 | compatible = "brcm,bcm2835-spi"; | ||
| 74 | reg = <0x7e204000 0x1000>; | ||
| 75 | interrupts = <2 22>; | ||
| 76 | clocks = <&clk_spi>; | ||
| 77 | #address-cells = <1>; | ||
| 78 | #size-cells = <0>; | ||
| 79 | status = "disabled"; | ||
| 80 | }; | ||
| 81 | |||
| 67 | i2c0: i2c@20205000 { | 82 | i2c0: i2c@20205000 { |
| 68 | compatible = "brcm,bcm2835-i2c"; | 83 | compatible = "brcm,bcm2835-i2c"; |
| 69 | reg = <0x7e205000 0x1000>; | 84 | reg = <0x7e205000 0x1000>; |
| @@ -107,5 +122,12 @@ | |||
| 107 | #clock-cells = <0>; | 122 | #clock-cells = <0>; |
| 108 | clock-frequency = <250000000>; | 123 | clock-frequency = <250000000>; |
| 109 | }; | 124 | }; |
| 125 | |||
| 126 | clk_spi: spi { | ||
| 127 | compatible = "fixed-clock"; | ||
| 128 | reg = <2>; | ||
| 129 | #clock-cells = <0>; | ||
| 130 | clock-frequency = <250000000>; | ||
| 131 | }; | ||
| 110 | }; | 132 | }; |
| 111 | }; | 133 | }; |
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index f712fb607a42..c5834a6c5bf4 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts | |||
| @@ -35,14 +35,84 @@ | |||
| 35 | clock-frequency = <100000>; | 35 | clock-frequency = <100000>; |
| 36 | pinctrl-names = "default"; | 36 | pinctrl-names = "default"; |
| 37 | pinctrl-0 = <&i2c0_pins>; | 37 | pinctrl-0 = <&i2c0_pins>; |
| 38 | |||
| 39 | tps: tps@48 { | ||
| 40 | reg = <0x48>; | ||
| 41 | }; | ||
| 38 | }; | 42 | }; |
| 39 | wdt: wdt@1c21000 { | 43 | wdt: wdt@1c21000 { |
| 40 | status = "okay"; | 44 | status = "okay"; |
| 41 | }; | 45 | }; |
| 46 | mmc0: mmc@1c40000 { | ||
| 47 | max-frequency = <50000000>; | ||
| 48 | bus-width = <4>; | ||
| 49 | status = "okay"; | ||
| 50 | pinctrl-names = "default"; | ||
| 51 | pinctrl-0 = <&mmc0_pins>; | ||
| 52 | }; | ||
| 42 | }; | 53 | }; |
| 43 | nand_cs3@62000000 { | 54 | nand_cs3@62000000 { |
| 44 | status = "okay"; | 55 | status = "okay"; |
| 45 | pinctrl-names = "default"; | 56 | pinctrl-names = "default"; |
| 46 | pinctrl-0 = <&nand_cs3_pins>; | 57 | pinctrl-0 = <&nand_cs3_pins>; |
| 47 | }; | 58 | }; |
| 59 | vbat: fixedregulator@0 { | ||
| 60 | compatible = "regulator-fixed"; | ||
| 61 | regulator-name = "vbat"; | ||
| 62 | regulator-min-microvolt = <5000000>; | ||
| 63 | regulator-max-microvolt = <5000000>; | ||
| 64 | regulator-boot-on; | ||
| 65 | }; | ||
| 66 | }; | ||
| 67 | |||
| 68 | /include/ "tps6507x.dtsi" | ||
| 69 | |||
| 70 | &tps { | ||
| 71 | vdcdc1_2-supply = <&vbat>; | ||
| 72 | vdcdc3-supply = <&vbat>; | ||
| 73 | vldo1_2-supply = <&vbat>; | ||
| 74 | |||
| 75 | regulators { | ||
| 76 | vdcdc1_reg: regulator@0 { | ||
| 77 | regulator-name = "VDCDC1_3.3V"; | ||
| 78 | regulator-min-microvolt = <3150000>; | ||
| 79 | regulator-max-microvolt = <3450000>; | ||
| 80 | regulator-always-on; | ||
| 81 | regulator-boot-on; | ||
| 82 | }; | ||
| 83 | |||
| 84 | vdcdc2_reg: regulator@1 { | ||
| 85 | regulator-name = "VDCDC2_3.3V"; | ||
| 86 | regulator-min-microvolt = <1710000>; | ||
| 87 | regulator-max-microvolt = <3450000>; | ||
| 88 | regulator-always-on; | ||
| 89 | regulator-boot-on; | ||
| 90 | ti,defdcdc_default = <1>; | ||
| 91 | }; | ||
| 92 | |||
| 93 | vdcdc3_reg: regulator@2 { | ||
| 94 | regulator-name = "VDCDC3_1.2V"; | ||
| 95 | regulator-min-microvolt = <950000>; | ||
| 96 | regulator-max-microvolt = <1350000>; | ||
| 97 | regulator-always-on; | ||
| 98 | regulator-boot-on; | ||
| 99 | ti,defdcdc_default = <1>; | ||
| 100 | }; | ||
| 101 | |||
| 102 | ldo1_reg: regulator@3 { | ||
| 103 | regulator-name = "LDO1_1.8V"; | ||
| 104 | regulator-min-microvolt = <1710000>; | ||
| 105 | regulator-max-microvolt = <1890000>; | ||
| 106 | regulator-always-on; | ||
| 107 | regulator-boot-on; | ||
| 108 | }; | ||
| 109 | |||
| 110 | ldo2_reg: regulator@4 { | ||
| 111 | regulator-name = "LDO2_1.2V"; | ||
| 112 | regulator-min-microvolt = <1140000>; | ||
| 113 | regulator-max-microvolt = <1320000>; | ||
| 114 | regulator-always-on; | ||
| 115 | regulator-boot-on; | ||
| 116 | }; | ||
| 117 | }; | ||
| 48 | }; | 118 | }; |
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 3ec1bda64356..3ade343f13cc 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi | |||
| @@ -62,6 +62,15 @@ | |||
| 62 | 0x10 0x00002200 0x0000ff00 | 62 | 0x10 0x00002200 0x0000ff00 |
| 63 | >; | 63 | >; |
| 64 | }; | 64 | }; |
| 65 | mmc0_pins: pinmux_mmc_pins { | ||
| 66 | pinctrl-single,bits = < | ||
| 67 | /* MMCSD0_DAT[3] MMCSD0_DAT[2] | ||
| 68 | * MMCSD0_DAT[1] MMCSD0_DAT[0] | ||
| 69 | * MMCSD0_CMD MMCSD0_CLK | ||
| 70 | */ | ||
| 71 | 0x28 0x00222222 0x00ffffff | ||
| 72 | >; | ||
| 73 | }; | ||
| 65 | }; | 74 | }; |
| 66 | serial0: serial@1c42000 { | 75 | serial0: serial@1c42000 { |
| 67 | compatible = "ns16550a"; | 76 | compatible = "ns16550a"; |
| @@ -107,6 +116,12 @@ | |||
| 107 | reg = <0x21000 0x1000>; | 116 | reg = <0x21000 0x1000>; |
| 108 | status = "disabled"; | 117 | status = "disabled"; |
| 109 | }; | 118 | }; |
| 119 | mmc0: mmc@1c40000 { | ||
| 120 | compatible = "ti,da830-mmc"; | ||
| 121 | reg = <0x40000 0x1000>; | ||
| 122 | interrupts = <16>; | ||
| 123 | status = "disabled"; | ||
| 124 | }; | ||
| 110 | }; | 125 | }; |
| 111 | nand_cs3@62000000 { | 126 | nand_cs3@62000000 { |
| 112 | compatible = "ti,davinci-nand"; | 127 | compatible = "ti,davinci-nand"; |
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index aaa63d0a8096..b6bc4ff17f26 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi | |||
| @@ -191,7 +191,7 @@ | |||
| 191 | 191 | ||
| 192 | prcmu: prcmu@80157000 { | 192 | prcmu: prcmu@80157000 { |
| 193 | compatible = "stericsson,db8500-prcmu"; | 193 | compatible = "stericsson,db8500-prcmu"; |
| 194 | reg = <0x80157000 0x1000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; | 194 | reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; |
| 195 | reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; | 195 | reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; |
| 196 | interrupts = <0 47 0x4>; | 196 | interrupts = <0 47 0x4>; |
| 197 | #address-cells = <1>; | 197 | #address-cells = <1>; |
| @@ -674,10 +674,13 @@ | |||
| 674 | compatible = "regulator-gpio"; | 674 | compatible = "regulator-gpio"; |
| 675 | 675 | ||
| 676 | regulator-min-microvolt = <1800000>; | 676 | regulator-min-microvolt = <1800000>; |
| 677 | regulator-max-microvolt = <2600000>; | 677 | regulator-max-microvolt = <2900000>; |
| 678 | regulator-name = "mmci-reg"; | 678 | regulator-name = "mmci-reg"; |
| 679 | regulator-type = "voltage"; | 679 | regulator-type = "voltage"; |
| 680 | 680 | ||
| 681 | startup-delay-us = <100>; | ||
| 682 | enable-active-high; | ||
| 683 | |||
| 681 | states = <1800000 0x1 | 684 | states = <1800000 0x1 |
| 682 | 2900000 0x0>; | 685 | 2900000 0x0>; |
| 683 | 686 | ||
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index f7509cafc377..6cab46849cdb 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi | |||
| @@ -50,6 +50,11 @@ | |||
| 50 | #clock-cells = <1>; | 50 | #clock-cells = <1>; |
| 51 | }; | 51 | }; |
| 52 | 52 | ||
| 53 | thermal: thermal@d001c { | ||
| 54 | compatible = "marvell,dove-thermal"; | ||
| 55 | reg = <0xd001c 0x0c>, <0xd005c 0x08>; | ||
| 56 | }; | ||
| 57 | |||
| 53 | uart0: serial@12000 { | 58 | uart0: serial@12000 { |
| 54 | compatible = "ns16550a"; | 59 | compatible = "ns16550a"; |
| 55 | reg = <0x12000 0x100>; | 60 | reg = <0x12000 0x100>; |
diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi index 379128eb9d98..c0bc426952ea 100644 --- a/arch/arm/boot/dts/href.dtsi +++ b/arch/arm/boot/dts/href.dtsi | |||
| @@ -87,6 +87,7 @@ | |||
| 87 | mmc-cap-sd-highspeed; | 87 | mmc-cap-sd-highspeed; |
| 88 | mmc-cap-mmc-highspeed; | 88 | mmc-cap-mmc-highspeed; |
| 89 | vmmc-supply = <&ab8500_ldo_aux3_reg>; | 89 | vmmc-supply = <&ab8500_ldo_aux3_reg>; |
| 90 | vqmmc-supply = <&vmmci>; | ||
| 90 | 91 | ||
| 91 | cd-gpios = <&tc3589x_gpio 3 0x4>; | 92 | cd-gpios = <&tc3589x_gpio 3 0x4>; |
| 92 | 93 | ||
diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts index eec29c4a86dc..c2d274815923 100644 --- a/arch/arm/boot/dts/hrefprev60.dts +++ b/arch/arm/boot/dts/hrefprev60.dts | |||
| @@ -25,6 +25,14 @@ | |||
| 25 | }; | 25 | }; |
| 26 | 26 | ||
| 27 | soc-u9500 { | 27 | soc-u9500 { |
| 28 | prcmu@80157000 { | ||
| 29 | ab8500@5 { | ||
| 30 | ab8500-gpio { | ||
| 31 | compatible = "stericsson,ab8500-gpio"; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | |||
| 28 | i2c@80004000 { | 36 | i2c@80004000 { |
| 29 | tps61052@33 { | 37 | tps61052@33 { |
| 30 | compatible = "tps61052"; | 38 | compatible = "tps61052"; |
| @@ -40,7 +48,7 @@ | |||
| 40 | 48 | ||
| 41 | vmmci: regulator-gpio { | 49 | vmmci: regulator-gpio { |
| 42 | gpios = <&tc3589x_gpio 18 0x4>; | 50 | gpios = <&tc3589x_gpio 18 0x4>; |
| 43 | gpio-enable = <&tc3589x_gpio 17 0x4>; | 51 | enable-gpio = <&tc3589x_gpio 17 0x4>; |
| 44 | 52 | ||
| 45 | status = "okay"; | 53 | status = "okay"; |
| 46 | }; | 54 | }; |
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 56afcf41aae0..ad2d79324cd3 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi | |||
| @@ -295,6 +295,7 @@ | |||
| 295 | }; | 295 | }; |
| 296 | 296 | ||
| 297 | digctl@8001c000 { | 297 | digctl@8001c000 { |
| 298 | compatible = "fsl,imx23-digctl"; | ||
| 298 | reg = <0x8001c000 2000>; | 299 | reg = <0x8001c000 2000>; |
| 299 | status = "disabled"; | 300 | status = "disabled"; |
| 300 | }; | 301 | }; |
| @@ -321,6 +322,7 @@ | |||
| 321 | }; | 322 | }; |
| 322 | 323 | ||
| 323 | ocotp@8002c000 { | 324 | ocotp@8002c000 { |
| 325 | compatible = "fsl,ocotp"; | ||
| 324 | reg = <0x8002c000 0x2000>; | 326 | reg = <0x8002c000 0x2000>; |
| 325 | status = "disabled"; | 327 | status = "disabled"; |
| 326 | }; | 328 | }; |
| @@ -360,7 +362,7 @@ | |||
| 360 | ranges; | 362 | ranges; |
| 361 | 363 | ||
| 362 | clks: clkctrl@80040000 { | 364 | clks: clkctrl@80040000 { |
| 363 | compatible = "fsl,imx23-clkctrl"; | 365 | compatible = "fsl,imx23-clkctrl", "fsl,clkctrl"; |
| 364 | reg = <0x80040000 0x2000>; | 366 | reg = <0x80040000 0x2000>; |
| 365 | #clock-cells = <1>; | 367 | #clock-cells = <1>; |
| 366 | }; | 368 | }; |
| @@ -426,6 +428,7 @@ | |||
| 426 | compatible = "fsl,imx23-timrot", "fsl,timrot"; | 428 | compatible = "fsl,imx23-timrot", "fsl,timrot"; |
| 427 | reg = <0x80068000 0x2000>; | 429 | reg = <0x80068000 0x2000>; |
| 428 | interrupts = <28 29 30 31>; | 430 | interrupts = <28 29 30 31>; |
| 431 | clocks = <&clks 28>; | ||
| 429 | }; | 432 | }; |
| 430 | 433 | ||
| 431 | auart0: serial@8006c000 { | 434 | auart0: serial@8006c000 { |
diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts index 1a9d0491cdce..f8db366c46ff 100644 --- a/arch/arm/boot/dts/imx25-karo-tx25.dts +++ b/arch/arm/boot/dts/imx25-karo-tx25.dts | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | /include/ "imx25.dtsi" | 13 | #include "imx25.dtsi" |
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | model = "Ka-Ro TX25"; | 16 | model = "Ka-Ro TX25"; |
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index a02a860afd18..f607ce520eda 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | /include/ "imx25.dtsi" | 13 | #include "imx25.dtsi" |
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | model = "Freescale i.MX25 Product Development Kit"; | 16 | model = "Freescale i.MX25 Product Development Kit"; |
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 94f33059158a..d2550e0bca24 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi | |||
| @@ -9,7 +9,7 @@ | |||
| 9 | * http://www.gnu.org/copyleft/gpl.html | 9 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /include/ "skeleton.dtsi" | 12 | #include "skeleton.dtsi" |
| 13 | 13 | ||
| 14 | / { | 14 | / { |
| 15 | aliases { | 15 | aliases { |
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts index b464c807d8d9..ba4c6df08ece 100644 --- a/arch/arm/boot/dts/imx27-apf27.dts +++ b/arch/arm/boot/dts/imx27-apf27.dts | |||
| @@ -13,7 +13,7 @@ | |||
| 13 | */ | 13 | */ |
| 14 | 14 | ||
| 15 | /dts-v1/; | 15 | /dts-v1/; |
| 16 | /include/ "imx27.dtsi" | 16 | #include "imx27.dtsi" |
| 17 | 17 | ||
| 18 | / { | 18 | / { |
| 19 | model = "Armadeus Systems APF27 module"; | 19 | model = "Armadeus Systems APF27 module"; |
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts new file mode 100644 index 000000000000..66b8e1c1b0be --- /dev/null +++ b/arch/arm/boot/dts/imx27-apf27dev.dts | |||
| @@ -0,0 +1,60 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Armadeus Systems - <support@armadeus.com> | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* APF27Dev is a docking board for the APF27 SOM */ | ||
| 13 | #include "imx27-apf27.dts" | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "Armadeus Systems APF27Dev docking/development board"; | ||
| 17 | compatible = "armadeus,imx27-apf27dev", "armadeus,imx27-apf27", "fsl,imx27"; | ||
| 18 | |||
| 19 | gpio-keys { | ||
| 20 | compatible = "gpio-keys"; | ||
| 21 | |||
| 22 | user-key { | ||
| 23 | label = "user"; | ||
| 24 | gpios = <&gpio6 13 0>; | ||
| 25 | linux,code = <276>; /* BTN_EXTRA */ | ||
| 26 | }; | ||
| 27 | }; | ||
| 28 | |||
| 29 | leds { | ||
| 30 | compatible = "gpio-leds"; | ||
| 31 | |||
| 32 | user { | ||
| 33 | label = "Heartbeat"; | ||
| 34 | gpios = <&gpio6 14 0>; | ||
| 35 | linux,default-trigger = "heartbeat"; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | |||
| 40 | &cspi1 { | ||
| 41 | fsl,spi-num-chipselects = <1>; | ||
| 42 | cs-gpios = <&gpio4 28 1>; | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | &cspi2 { | ||
| 47 | fsl,spi-num-chipselects = <3>; | ||
| 48 | cs-gpios = <&gpio4 21 1>, <&gpio4 27 1>, | ||
| 49 | <&gpio2 17 1>; | ||
| 50 | status = "okay"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | &i2c1 { | ||
| 54 | clock-frequency = <400000>; | ||
| 55 | status = "okay"; | ||
| 56 | }; | ||
| 57 | |||
| 58 | &i2c2 { | ||
| 59 | status = "okay"; | ||
| 60 | }; | ||
diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index 41cd1105608e..5ce89aa275df 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | /include/ "imx27.dtsi" | 13 | #include "imx27.dtsi" |
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | model = "Freescale i.MX27 Product Development Kit"; | 16 | model = "Freescale i.MX27 Product Development Kit"; |
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts index 53b0ec0c228e..fe64e3a91df0 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | /include/ "imx27.dtsi" | 13 | #include "imx27.dtsi" |
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | model = "Phytec pcm038"; | 16 | model = "Phytec pcm038"; |
| @@ -71,3 +71,9 @@ | |||
| 71 | #size-cells = <1>; | 71 | #size-cells = <1>; |
| 72 | }; | 72 | }; |
| 73 | }; | 73 | }; |
| 74 | |||
| 75 | &nfc { | ||
| 76 | nand-bus-width = <8>; | ||
| 77 | nand-ecc-mode = "hw"; | ||
| 78 | status = "okay"; | ||
| 79 | }; | ||
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 5a82cb5707a8..ff4bd4873edf 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi | |||
| @@ -9,7 +9,7 @@ | |||
| 9 | * http://www.gnu.org/copyleft/gpl.html | 9 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /include/ "skeleton.dtsi" | 12 | #include "skeleton.dtsi" |
| 13 | 13 | ||
| 14 | / { | 14 | / { |
| 15 | aliases { | 15 | aliases { |
| @@ -60,14 +60,41 @@ | |||
| 60 | 60 | ||
| 61 | wdog: wdog@10002000 { | 61 | wdog: wdog@10002000 { |
| 62 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; | 62 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; |
| 63 | reg = <0x10002000 0x4000>; | 63 | reg = <0x10002000 0x1000>; |
| 64 | interrupts = <27>; | 64 | interrupts = <27>; |
| 65 | clocks = <&clks 0>; | ||
| 66 | }; | ||
| 67 | |||
| 68 | gpt1: timer@10003000 { | ||
| 69 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | ||
| 70 | reg = <0x10003000 0x1000>; | ||
| 71 | interrupts = <26>; | ||
| 72 | clocks = <&clks 46>, <&clks 61>; | ||
| 73 | clock-names = "ipg", "per"; | ||
| 74 | }; | ||
| 75 | |||
| 76 | gpt2: timer@10004000 { | ||
| 77 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | ||
| 78 | reg = <0x10004000 0x1000>; | ||
| 79 | interrupts = <25>; | ||
| 80 | clocks = <&clks 45>, <&clks 61>; | ||
| 81 | clock-names = "ipg", "per"; | ||
| 82 | }; | ||
| 83 | |||
| 84 | gpt3: timer@10005000 { | ||
| 85 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | ||
| 86 | reg = <0x10005000 0x1000>; | ||
| 87 | interrupts = <24>; | ||
| 88 | clocks = <&clks 44>, <&clks 61>; | ||
| 89 | clock-names = "ipg", "per"; | ||
| 65 | }; | 90 | }; |
| 66 | 91 | ||
| 67 | uart1: serial@1000a000 { | 92 | uart1: serial@1000a000 { |
| 68 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; | 93 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 69 | reg = <0x1000a000 0x1000>; | 94 | reg = <0x1000a000 0x1000>; |
| 70 | interrupts = <20>; | 95 | interrupts = <20>; |
| 96 | clocks = <&clks 81>, <&clks 61>; | ||
| 97 | clock-names = "ipg", "per"; | ||
| 71 | status = "disabled"; | 98 | status = "disabled"; |
| 72 | }; | 99 | }; |
| 73 | 100 | ||
| @@ -75,6 +102,8 @@ | |||
| 75 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; | 102 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 76 | reg = <0x1000b000 0x1000>; | 103 | reg = <0x1000b000 0x1000>; |
| 77 | interrupts = <19>; | 104 | interrupts = <19>; |
| 105 | clocks = <&clks 80>, <&clks 61>; | ||
| 106 | clock-names = "ipg", "per"; | ||
| 78 | status = "disabled"; | 107 | status = "disabled"; |
| 79 | }; | 108 | }; |
| 80 | 109 | ||
| @@ -82,6 +111,8 @@ | |||
| 82 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; | 111 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 83 | reg = <0x1000c000 0x1000>; | 112 | reg = <0x1000c000 0x1000>; |
| 84 | interrupts = <18>; | 113 | interrupts = <18>; |
| 114 | clocks = <&clks 79>, <&clks 61>; | ||
| 115 | clock-names = "ipg", "per"; | ||
| 85 | status = "disabled"; | 116 | status = "disabled"; |
| 86 | }; | 117 | }; |
| 87 | 118 | ||
| @@ -89,6 +120,8 @@ | |||
| 89 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; | 120 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 90 | reg = <0x1000d000 0x1000>; | 121 | reg = <0x1000d000 0x1000>; |
| 91 | interrupts = <17>; | 122 | interrupts = <17>; |
| 123 | clocks = <&clks 78>, <&clks 61>; | ||
| 124 | clock-names = "ipg", "per"; | ||
| 92 | status = "disabled"; | 125 | status = "disabled"; |
| 93 | }; | 126 | }; |
| 94 | 127 | ||
| @@ -98,6 +131,8 @@ | |||
| 98 | compatible = "fsl,imx27-cspi"; | 131 | compatible = "fsl,imx27-cspi"; |
| 99 | reg = <0x1000e000 0x1000>; | 132 | reg = <0x1000e000 0x1000>; |
| 100 | interrupts = <16>; | 133 | interrupts = <16>; |
| 134 | clocks = <&clks 53>, <&clks 0>; | ||
| 135 | clock-names = "ipg", "per"; | ||
| 101 | status = "disabled"; | 136 | status = "disabled"; |
| 102 | }; | 137 | }; |
| 103 | 138 | ||
| @@ -107,6 +142,8 @@ | |||
| 107 | compatible = "fsl,imx27-cspi"; | 142 | compatible = "fsl,imx27-cspi"; |
| 108 | reg = <0x1000f000 0x1000>; | 143 | reg = <0x1000f000 0x1000>; |
| 109 | interrupts = <15>; | 144 | interrupts = <15>; |
| 145 | clocks = <&clks 52>, <&clks 0>; | ||
| 146 | clock-names = "ipg", "per"; | ||
| 110 | status = "disabled"; | 147 | status = "disabled"; |
| 111 | }; | 148 | }; |
| 112 | 149 | ||
| @@ -116,6 +153,7 @@ | |||
| 116 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; | 153 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; |
| 117 | reg = <0x10012000 0x1000>; | 154 | reg = <0x10012000 0x1000>; |
| 118 | interrupts = <12>; | 155 | interrupts = <12>; |
| 156 | clocks = <&clks 40>; | ||
| 119 | status = "disabled"; | 157 | status = "disabled"; |
| 120 | }; | 158 | }; |
| 121 | 159 | ||
| @@ -185,13 +223,33 @@ | |||
| 185 | compatible = "fsl,imx27-cspi"; | 223 | compatible = "fsl,imx27-cspi"; |
| 186 | reg = <0x10017000 0x1000>; | 224 | reg = <0x10017000 0x1000>; |
| 187 | interrupts = <6>; | 225 | interrupts = <6>; |
| 226 | clocks = <&clks 51>, <&clks 0>; | ||
| 227 | clock-names = "ipg", "per"; | ||
| 188 | status = "disabled"; | 228 | status = "disabled"; |
| 189 | }; | 229 | }; |
| 190 | 230 | ||
| 231 | gpt4: timer@10019000 { | ||
| 232 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | ||
| 233 | reg = <0x10019000 0x1000>; | ||
| 234 | interrupts = <4>; | ||
| 235 | clocks = <&clks 43>, <&clks 61>; | ||
| 236 | clock-names = "ipg", "per"; | ||
| 237 | }; | ||
| 238 | |||
| 239 | gpt5: timer@1001a000 { | ||
| 240 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | ||
| 241 | reg = <0x1001a000 0x1000>; | ||
| 242 | interrupts = <3>; | ||
| 243 | clocks = <&clks 42>, <&clks 61>; | ||
| 244 | clock-names = "ipg", "per"; | ||
| 245 | }; | ||
| 246 | |||
| 191 | uart5: serial@1001b000 { | 247 | uart5: serial@1001b000 { |
| 192 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; | 248 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 193 | reg = <0x1001b000 0x1000>; | 249 | reg = <0x1001b000 0x1000>; |
| 194 | interrupts = <49>; | 250 | interrupts = <49>; |
| 251 | clocks = <&clks 77>, <&clks 61>; | ||
| 252 | clock-names = "ipg", "per"; | ||
| 195 | status = "disabled"; | 253 | status = "disabled"; |
| 196 | }; | 254 | }; |
| 197 | 255 | ||
| @@ -199,6 +257,8 @@ | |||
| 199 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; | 257 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 200 | reg = <0x1001c000 0x1000>; | 258 | reg = <0x1001c000 0x1000>; |
| 201 | interrupts = <48>; | 259 | interrupts = <48>; |
| 260 | clocks = <&clks 78>, <&clks 61>; | ||
| 261 | clock-names = "ipg", "per"; | ||
| 202 | status = "disabled"; | 262 | status = "disabled"; |
| 203 | }; | 263 | }; |
| 204 | 264 | ||
| @@ -208,9 +268,17 @@ | |||
| 208 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; | 268 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; |
| 209 | reg = <0x1001d000 0x1000>; | 269 | reg = <0x1001d000 0x1000>; |
| 210 | interrupts = <1>; | 270 | interrupts = <1>; |
| 271 | clocks = <&clks 39>; | ||
| 211 | status = "disabled"; | 272 | status = "disabled"; |
| 212 | }; | 273 | }; |
| 213 | 274 | ||
| 275 | gpt6: timer@1001f000 { | ||
| 276 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | ||
| 277 | reg = <0x1001f000 0x1000>; | ||
| 278 | interrupts = <2>; | ||
| 279 | clocks = <&clks 41>, <&clks 61>; | ||
| 280 | clock-names = "ipg", "per"; | ||
| 281 | }; | ||
| 214 | }; | 282 | }; |
| 215 | 283 | ||
| 216 | aipi@10020000 { /* AIPI2 */ | 284 | aipi@10020000 { /* AIPI2 */ |
| @@ -224,10 +292,19 @@ | |||
| 224 | compatible = "fsl,imx27-fec"; | 292 | compatible = "fsl,imx27-fec"; |
| 225 | reg = <0x1002b000 0x4000>; | 293 | reg = <0x1002b000 0x4000>; |
| 226 | interrupts = <50>; | 294 | interrupts = <50>; |
| 295 | clocks = <&clks 48>, <&clks 67>, <&clks 0>; | ||
| 296 | clock-names = "ipg", "ahb", "ptp"; | ||
| 227 | status = "disabled"; | 297 | status = "disabled"; |
| 228 | }; | 298 | }; |
| 299 | |||
| 300 | clks: ccm@10027000{ | ||
| 301 | compatible = "fsl,imx27-ccm"; | ||
| 302 | reg = <0x10027000 0x1000>; | ||
| 303 | #clock-cells = <1>; | ||
| 304 | }; | ||
| 229 | }; | 305 | }; |
| 230 | 306 | ||
| 307 | |||
| 231 | nfc: nand@d8000000 { | 308 | nfc: nand@d8000000 { |
| 232 | #address-cells = <1>; | 309 | #address-cells = <1>; |
| 233 | #size-cells = <1>; | 310 | #size-cells = <1>; |
| @@ -235,6 +312,7 @@ | |||
| 235 | compatible = "fsl,imx27-nand"; | 312 | compatible = "fsl,imx27-nand"; |
| 236 | reg = <0xd8000000 0x1000>; | 313 | reg = <0xd8000000 0x1000>; |
| 237 | interrupts = <29>; | 314 | interrupts = <29>; |
| 315 | clocks = <&clks 54>; | ||
| 238 | status = "disabled"; | 316 | status = "disabled"; |
| 239 | }; | 317 | }; |
| 240 | }; | 318 | }; |
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 7ba49662b9bc..64af2381c1b0 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi | |||
| @@ -647,6 +647,7 @@ | |||
| 647 | }; | 647 | }; |
| 648 | 648 | ||
| 649 | digctl@8001c000 { | 649 | digctl@8001c000 { |
| 650 | compatible = "fsl,imx28-digctl"; | ||
| 650 | reg = <0x8001c000 0x2000>; | 651 | reg = <0x8001c000 0x2000>; |
| 651 | interrupts = <89>; | 652 | interrupts = <89>; |
| 652 | status = "disabled"; | 653 | status = "disabled"; |
| @@ -676,6 +677,7 @@ | |||
| 676 | }; | 677 | }; |
| 677 | 678 | ||
| 678 | ocotp@8002c000 { | 679 | ocotp@8002c000 { |
| 680 | compatible = "fsl,ocotp"; | ||
| 679 | reg = <0x8002c000 0x2000>; | 681 | reg = <0x8002c000 0x2000>; |
| 680 | status = "disabled"; | 682 | status = "disabled"; |
| 681 | }; | 683 | }; |
| @@ -755,7 +757,7 @@ | |||
| 755 | ranges; | 757 | ranges; |
| 756 | 758 | ||
| 757 | clks: clkctrl@80040000 { | 759 | clks: clkctrl@80040000 { |
| 758 | compatible = "fsl,imx28-clkctrl"; | 760 | compatible = "fsl,imx28-clkctrl", "fsl,clkctrl"; |
| 759 | reg = <0x80040000 0x2000>; | 761 | reg = <0x80040000 0x2000>; |
| 760 | #clock-cells = <1>; | 762 | #clock-cells = <1>; |
| 761 | }; | 763 | }; |
| @@ -838,6 +840,7 @@ | |||
| 838 | compatible = "fsl,imx28-timrot", "fsl,timrot"; | 840 | compatible = "fsl,imx28-timrot", "fsl,timrot"; |
| 839 | reg = <0x80068000 0x2000>; | 841 | reg = <0x80068000 0x2000>; |
| 840 | interrupts = <48 49 50 51>; | 842 | interrupts = <48 49 50 51>; |
| 843 | clocks = <&clks 26>; | ||
| 841 | }; | 844 | }; |
| 842 | 845 | ||
| 843 | auart0: serial@8006a000 { | 846 | auart0: serial@8006a000 { |
diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts index 9ac6f6ba1d64..2424abfc9c7b 100644 --- a/arch/arm/boot/dts/imx31-bug.dts +++ b/arch/arm/boot/dts/imx31-bug.dts | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | /include/ "imx31.dtsi" | 13 | #include "imx31.dtsi" |
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | model = "Buglabs i.MX31 Bug 1.x"; | 16 | model = "Buglabs i.MX31 Bug 1.x"; |
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 454c2d175402..c5449257ad9a 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi | |||
| @@ -9,7 +9,7 @@ | |||
| 9 | * http://www.gnu.org/copyleft/gpl.html | 9 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /include/ "skeleton.dtsi" | 12 | #include "skeleton.dtsi" |
| 13 | 13 | ||
| 14 | / { | 14 | / { |
| 15 | aliases { | 15 | aliases { |
| @@ -101,5 +101,21 @@ | |||
| 101 | #clock-cells = <1>; | 101 | #clock-cells = <1>; |
| 102 | }; | 102 | }; |
| 103 | }; | 103 | }; |
| 104 | |||
| 105 | aips@53f00000 { /* AIPS2 */ | ||
| 106 | compatible = "fsl,aips-bus", "simple-bus"; | ||
| 107 | #address-cells = <1>; | ||
| 108 | #size-cells = <1>; | ||
| 109 | reg = <0x53f00000 0x100000>; | ||
| 110 | ranges; | ||
| 111 | |||
| 112 | gpt: timer@53f90000 { | ||
| 113 | compatible = "fsl,imx31-gpt"; | ||
| 114 | reg = <0x53f90000 0x4000>; | ||
| 115 | interrupts = <29>; | ||
| 116 | clocks = <&clks 10>, <&clks 22>; | ||
| 117 | clock-names = "ipg", "per"; | ||
| 118 | }; | ||
| 119 | }; | ||
| 104 | }; | 120 | }; |
| 105 | }; | 121 | }; |
diff --git a/arch/arm/boot/dts/imx35-pinfunc.h b/arch/arm/boot/dts/imx35-pinfunc.h new file mode 100644 index 000000000000..4911f2c405fa --- /dev/null +++ b/arch/arm/boot/dts/imx35-pinfunc.h | |||
| @@ -0,0 +1,970 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __DTS_IMX35_PINFUNC_H | ||
| 11 | #define __DTS_IMX35_PINFUNC_H | ||
| 12 | |||
| 13 | /* | ||
| 14 | * The pin function ID is a tuple of | ||
| 15 | * <mux_reg conf_reg input_reg mux_mode input_val> | ||
| 16 | */ | ||
| 17 | #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0 | ||
| 18 | #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0 | ||
| 19 | #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0 | ||
| 20 | #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0 | ||
| 21 | #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0 | ||
| 22 | #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0 | ||
| 23 | #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0 | ||
| 24 | #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0 | ||
| 25 | #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0 | ||
| 26 | #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0 | ||
| 27 | #define MX35_PAD_COMPARE__GPIO1_5 0x008 0x32c 0x854 0x5 0x0 | ||
| 28 | #define MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x008 0x32c 0x000 0x7 0x0 | ||
| 29 | #define MX35_PAD_WDOG_RST__WDOG_WDOG_B 0x00c 0x330 0x000 0x0 0x0 | ||
| 30 | #define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE 0x00c 0x330 0x000 0x3 0x0 | ||
| 31 | #define MX35_PAD_WDOG_RST__GPIO1_6 0x00c 0x330 0x858 0x5 0x0 | ||
| 32 | #define MX35_PAD_GPIO1_0__GPIO1_0 0x010 0x334 0x82c 0x0 0x0 | ||
| 33 | #define MX35_PAD_GPIO1_0__CCM_PMIC_RDY 0x010 0x334 0x7d4 0x1 0x0 | ||
| 34 | #define MX35_PAD_GPIO1_0__OWIRE_LINE 0x010 0x334 0x990 0x2 0x0 | ||
| 35 | #define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 0x010 0x334 0x000 0x7 0x0 | ||
| 36 | #define MX35_PAD_GPIO1_1__GPIO1_1 0x014 0x338 0x838 0x0 0x0 | ||
| 37 | #define MX35_PAD_GPIO1_1__PWM_PWMO 0x014 0x338 0x000 0x2 0x0 | ||
| 38 | #define MX35_PAD_GPIO1_1__CSPI1_SS2 0x014 0x338 0x7d8 0x3 0x0 | ||
| 39 | #define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT 0x014 0x338 0x000 0x6 0x0 | ||
| 40 | #define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 0x014 0x338 0x000 0x7 0x0 | ||
| 41 | #define MX35_PAD_GPIO2_0__GPIO2_0 0x018 0x33c 0x868 0x0 0x0 | ||
| 42 | #define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK 0x018 0x33c 0x000 0x1 0x0 | ||
| 43 | #define MX35_PAD_GPIO3_0__GPIO3_0 0x01c 0x340 0x8e8 0x0 0x0 | ||
| 44 | #define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK 0x01c 0x340 0x000 0x1 0x0 | ||
| 45 | #define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B 0x000 0x344 0x000 0x0 0x0 | ||
| 46 | #define MX35_PAD_POR_B__CCM_POR_B 0x000 0x348 0x000 0x0 0x0 | ||
| 47 | #define MX35_PAD_CLKO__CCM_CLKO 0x020 0x34c 0x000 0x0 0x0 | ||
| 48 | #define MX35_PAD_CLKO__GPIO1_8 0x020 0x34c 0x860 0x5 0x0 | ||
| 49 | #define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 0x000 0x350 0x000 0x0 0x0 | ||
| 50 | #define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 0x000 0x354 0x000 0x0 0x0 | ||
| 51 | #define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 0x000 0x358 0x000 0x0 0x0 | ||
| 52 | #define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 0x000 0x35c 0x000 0x0 0x0 | ||
| 53 | #define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 0x000 0x360 0x000 0x0 0x0 | ||
| 54 | #define MX35_PAD_VSTBY__CCM_VSTBY 0x024 0x364 0x000 0x0 0x0 | ||
| 55 | #define MX35_PAD_VSTBY__GPIO1_7 0x024 0x364 0x85c 0x5 0x0 | ||
| 56 | #define MX35_PAD_A0__EMI_EIM_DA_L_0 0x028 0x368 0x000 0x0 0x0 | ||
| 57 | #define MX35_PAD_A1__EMI_EIM_DA_L_1 0x02c 0x36c 0x000 0x0 0x0 | ||
| 58 | #define MX35_PAD_A2__EMI_EIM_DA_L_2 0x030 0x370 0x000 0x0 0x0 | ||
| 59 | #define MX35_PAD_A3__EMI_EIM_DA_L_3 0x034 0x374 0x000 0x0 0x0 | ||
| 60 | #define MX35_PAD_A4__EMI_EIM_DA_L_4 0x038 0x378 0x000 0x0 0x0 | ||
| 61 | #define MX35_PAD_A5__EMI_EIM_DA_L_5 0x03c 0x37c 0x000 0x0 0x0 | ||
| 62 | #define MX35_PAD_A6__EMI_EIM_DA_L_6 0x040 0x380 0x000 0x0 0x0 | ||
| 63 | #define MX35_PAD_A7__EMI_EIM_DA_L_7 0x044 0x384 0x000 0x0 0x0 | ||
| 64 | #define MX35_PAD_A8__EMI_EIM_DA_H_8 0x048 0x388 0x000 0x0 0x0 | ||
| 65 | #define MX35_PAD_A9__EMI_EIM_DA_H_9 0x04c 0x38c 0x000 0x0 0x0 | ||
| 66 | #define MX35_PAD_A10__EMI_EIM_DA_H_10 0x050 0x390 0x000 0x0 0x0 | ||
| 67 | #define MX35_PAD_MA10__EMI_MA10 0x054 0x394 0x000 0x0 0x0 | ||
| 68 | #define MX35_PAD_A11__EMI_EIM_DA_H_11 0x058 0x398 0x000 0x0 0x0 | ||
| 69 | #define MX35_PAD_A12__EMI_EIM_DA_H_12 0x05c 0x39c 0x000 0x0 0x0 | ||
| 70 | #define MX35_PAD_A13__EMI_EIM_DA_H_13 0x060 0x3a0 0x000 0x0 0x0 | ||
| 71 | #define MX35_PAD_A14__EMI_EIM_DA_H2_14 0x064 0x3a4 0x000 0x0 0x0 | ||
| 72 | #define MX35_PAD_A15__EMI_EIM_DA_H2_15 0x068 0x3a8 0x000 0x0 0x0 | ||
| 73 | #define MX35_PAD_A16__EMI_EIM_A_16 0x06c 0x3ac 0x000 0x0 0x0 | ||
| 74 | #define MX35_PAD_A17__EMI_EIM_A_17 0x070 0x3b0 0x000 0x0 0x0 | ||
| 75 | #define MX35_PAD_A18__EMI_EIM_A_18 0x074 0x3b4 0x000 0x0 0x0 | ||
| 76 | #define MX35_PAD_A19__EMI_EIM_A_19 0x078 0x3b8 0x000 0x0 0x0 | ||
| 77 | #define MX35_PAD_A20__EMI_EIM_A_20 0x07c 0x3bc 0x000 0x0 0x0 | ||
| 78 | #define MX35_PAD_A21__EMI_EIM_A_21 0x080 0x3c0 0x000 0x0 0x0 | ||
| 79 | #define MX35_PAD_A22__EMI_EIM_A_22 0x084 0x3c4 0x000 0x0 0x0 | ||
| 80 | #define MX35_PAD_A23__EMI_EIM_A_23 0x088 0x3c8 0x000 0x0 0x0 | ||
| 81 | #define MX35_PAD_A24__EMI_EIM_A_24 0x08c 0x3cc 0x000 0x0 0x0 | ||
| 82 | #define MX35_PAD_A25__EMI_EIM_A_25 0x090 0x3d0 0x000 0x0 0x0 | ||
| 83 | #define MX35_PAD_SDBA1__EMI_EIM_SDBA1 0x000 0x3d4 0x000 0x0 0x0 | ||
| 84 | #define MX35_PAD_SDBA0__EMI_EIM_SDBA0 0x000 0x3d8 0x000 0x0 0x0 | ||
| 85 | #define MX35_PAD_SD0__EMI_DRAM_D_0 0x000 0x3dc 0x000 0x0 0x0 | ||
| 86 | #define MX35_PAD_SD1__EMI_DRAM_D_1 0x000 0x3e0 0x000 0x0 0x0 | ||
| 87 | #define MX35_PAD_SD2__EMI_DRAM_D_2 0x000 0x3e4 0x000 0x0 0x0 | ||
| 88 | #define MX35_PAD_SD3__EMI_DRAM_D_3 0x000 0x3e8 0x000 0x0 0x0 | ||
| 89 | #define MX35_PAD_SD4__EMI_DRAM_D_4 0x000 0x3ec 0x000 0x0 0x0 | ||
| 90 | #define MX35_PAD_SD5__EMI_DRAM_D_5 0x000 0x3f0 0x000 0x0 0x0 | ||
| 91 | #define MX35_PAD_SD6__EMI_DRAM_D_6 0x000 0x3f4 0x000 0x0 0x0 | ||
| 92 | #define MX35_PAD_SD7__EMI_DRAM_D_7 0x000 0x3f8 0x000 0x0 0x0 | ||
| 93 | #define MX35_PAD_SD8__EMI_DRAM_D_8 0x000 0x3fc 0x000 0x0 0x0 | ||
| 94 | #define MX35_PAD_SD9__EMI_DRAM_D_9 0x000 0x400 0x000 0x0 0x0 | ||
| 95 | #define MX35_PAD_SD10__EMI_DRAM_D_10 0x000 0x404 0x000 0x0 0x0 | ||
| 96 | #define MX35_PAD_SD11__EMI_DRAM_D_11 0x000 0x408 0x000 0x0 0x0 | ||
| 97 | #define MX35_PAD_SD12__EMI_DRAM_D_12 0x000 0x40c 0x000 0x0 0x0 | ||
| 98 | #define MX35_PAD_SD13__EMI_DRAM_D_13 0x000 0x410 0x000 0x0 0x0 | ||
| 99 | #define MX35_PAD_SD14__EMI_DRAM_D_14 0x000 0x414 0x000 0x0 0x0 | ||
| 100 | #define MX35_PAD_SD15__EMI_DRAM_D_15 0x000 0x418 0x000 0x0 0x0 | ||
| 101 | #define MX35_PAD_SD16__EMI_DRAM_D_16 0x000 0x41c 0x000 0x0 0x0 | ||
| 102 | #define MX35_PAD_SD17__EMI_DRAM_D_17 0x000 0x420 0x000 0x0 0x0 | ||
| 103 | #define MX35_PAD_SD18__EMI_DRAM_D_18 0x000 0x424 0x000 0x0 0x0 | ||
| 104 | #define MX35_PAD_SD19__EMI_DRAM_D_19 0x000 0x428 0x000 0x0 0x0 | ||
| 105 | #define MX35_PAD_SD20__EMI_DRAM_D_20 0x000 0x42c 0x000 0x0 0x0 | ||
| 106 | #define MX35_PAD_SD21__EMI_DRAM_D_21 0x000 0x430 0x000 0x0 0x0 | ||
| 107 | #define MX35_PAD_SD22__EMI_DRAM_D_22 0x000 0x434 0x000 0x0 0x0 | ||
| 108 | #define MX35_PAD_SD23__EMI_DRAM_D_23 0x000 0x438 0x000 0x0 0x0 | ||
| 109 | #define MX35_PAD_SD24__EMI_DRAM_D_24 0x000 0x43c 0x000 0x0 0x0 | ||
| 110 | #define MX35_PAD_SD25__EMI_DRAM_D_25 0x000 0x440 0x000 0x0 0x0 | ||
| 111 | #define MX35_PAD_SD26__EMI_DRAM_D_26 0x000 0x444 0x000 0x0 0x0 | ||
| 112 | #define MX35_PAD_SD27__EMI_DRAM_D_27 0x000 0x448 0x000 0x0 0x0 | ||
| 113 | #define MX35_PAD_SD28__EMI_DRAM_D_28 0x000 0x44c 0x000 0x0 0x0 | ||
| 114 | #define MX35_PAD_SD29__EMI_DRAM_D_29 0x000 0x450 0x000 0x0 0x0 | ||
| 115 | #define MX35_PAD_SD30__EMI_DRAM_D_30 0x000 0x454 0x000 0x0 0x0 | ||
| 116 | #define MX35_PAD_SD31__EMI_DRAM_D_31 0x000 0x458 0x000 0x0 0x0 | ||
| 117 | #define MX35_PAD_DQM0__EMI_DRAM_DQM_0 0x000 0x45c 0x000 0x0 0x0 | ||
| 118 | #define MX35_PAD_DQM1__EMI_DRAM_DQM_1 0x000 0x460 0x000 0x0 0x0 | ||
| 119 | #define MX35_PAD_DQM2__EMI_DRAM_DQM_2 0x000 0x464 0x000 0x0 0x0 | ||
| 120 | #define MX35_PAD_DQM3__EMI_DRAM_DQM_3 0x000 0x468 0x000 0x0 0x0 | ||
| 121 | #define MX35_PAD_EB0__EMI_EIM_EB0_B 0x094 0x46c 0x000 0x0 0x0 | ||
| 122 | #define MX35_PAD_EB1__EMI_EIM_EB1_B 0x098 0x470 0x000 0x0 0x0 | ||
| 123 | #define MX35_PAD_OE__EMI_EIM_OE 0x09c 0x474 0x000 0x0 0x0 | ||
| 124 | #define MX35_PAD_CS0__EMI_EIM_CS0 0x0a0 0x478 0x000 0x0 0x0 | ||
| 125 | #define MX35_PAD_CS1__EMI_EIM_CS1 0x0a4 0x47c 0x000 0x0 0x0 | ||
| 126 | #define MX35_PAD_CS1__EMI_NANDF_CE3 0x0a4 0x47c 0x000 0x3 0x0 | ||
| 127 | #define MX35_PAD_CS2__EMI_EIM_CS2 0x0a8 0x480 0x000 0x0 0x0 | ||
| 128 | #define MX35_PAD_CS3__EMI_EIM_CS3 0x0ac 0x484 0x000 0x0 0x0 | ||
| 129 | #define MX35_PAD_CS4__EMI_EIM_CS4 0x0b0 0x488 0x000 0x0 0x0 | ||
| 130 | #define MX35_PAD_CS4__EMI_DTACK_B 0x0b0 0x488 0x800 0x1 0x0 | ||
| 131 | #define MX35_PAD_CS4__EMI_NANDF_CE1 0x0b0 0x488 0x000 0x3 0x0 | ||
| 132 | #define MX35_PAD_CS4__GPIO1_20 0x0b0 0x488 0x83c 0x5 0x0 | ||
| 133 | #define MX35_PAD_CS5__EMI_EIM_CS5 0x0b4 0x48c 0x000 0x0 0x0 | ||
| 134 | #define MX35_PAD_CS5__CSPI2_SS2 0x0b4 0x48c 0x7f8 0x1 0x0 | ||
| 135 | #define MX35_PAD_CS5__CSPI1_SS2 0x0b4 0x48c 0x7d8 0x2 0x1 | ||
| 136 | #define MX35_PAD_CS5__EMI_NANDF_CE2 0x0b4 0x48c 0x000 0x3 0x0 | ||
| 137 | #define MX35_PAD_CS5__GPIO1_21 0x0b4 0x48c 0x840 0x5 0x0 | ||
| 138 | #define MX35_PAD_NF_CE0__EMI_NANDF_CE0 0x0b8 0x490 0x000 0x0 0x0 | ||
| 139 | #define MX35_PAD_NF_CE0__GPIO1_22 0x0b8 0x490 0x844 0x5 0x0 | ||
| 140 | #define MX35_PAD_ECB__EMI_EIM_ECB 0x000 0x494 0x000 0x0 0x0 | ||
| 141 | #define MX35_PAD_LBA__EMI_EIM_LBA 0x0bc 0x498 0x000 0x0 0x0 | ||
| 142 | #define MX35_PAD_BCLK__EMI_EIM_BCLK 0x0c0 0x49c 0x000 0x0 0x0 | ||
| 143 | #define MX35_PAD_RW__EMI_EIM_RW 0x0c4 0x4a0 0x000 0x0 0x0 | ||
| 144 | #define MX35_PAD_RAS__EMI_DRAM_RAS 0x000 0x4a4 0x000 0x0 0x0 | ||
| 145 | #define MX35_PAD_CAS__EMI_DRAM_CAS 0x000 0x4a8 0x000 0x0 0x0 | ||
| 146 | #define MX35_PAD_SDWE__EMI_DRAM_SDWE 0x000 0x4ac 0x000 0x0 0x0 | ||
| 147 | #define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 0x000 0x4b0 0x000 0x0 0x0 | ||
| 148 | #define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 0x000 0x4b4 0x000 0x0 0x0 | ||
| 149 | #define MX35_PAD_SDCLK__EMI_DRAM_SDCLK 0x000 0x4b8 0x000 0x0 0x0 | ||
| 150 | #define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 0x000 0x4bc 0x000 0x0 0x0 | ||
| 151 | #define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 0x000 0x4c0 0x000 0x0 0x0 | ||
| 152 | #define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 0x000 0x4c4 0x000 0x0 0x0 | ||
| 153 | #define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 0x000 0x4c8 0x000 0x0 0x0 | ||
| 154 | #define MX35_PAD_NFWE_B__EMI_NANDF_WE_B 0x0c8 0x4cc 0x000 0x0 0x0 | ||
| 155 | #define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 0x0c8 0x4cc 0x9d8 0x1 0x0 | ||
| 156 | #define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC 0x0c8 0x4cc 0x924 0x2 0x0 | ||
| 157 | #define MX35_PAD_NFWE_B__GPIO2_18 0x0c8 0x4cc 0x88c 0x5 0x0 | ||
| 158 | #define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 0x0c8 0x4cc 0x000 0x7 0x0 | ||
| 159 | #define MX35_PAD_NFRE_B__EMI_NANDF_RE_B 0x0cc 0x4d0 0x000 0x0 0x0 | ||
| 160 | #define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR 0x0cc 0x4d0 0x9ec 0x1 0x0 | ||
| 161 | #define MX35_PAD_NFRE_B__IPU_DISPB_BCLK 0x0cc 0x4d0 0x000 0x2 0x0 | ||
| 162 | #define MX35_PAD_NFRE_B__GPIO2_19 0x0cc 0x4d0 0x890 0x5 0x0 | ||
| 163 | #define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 0x0cc 0x4d0 0x000 0x7 0x0 | ||
| 164 | #define MX35_PAD_NFALE__EMI_NANDF_ALE 0x0d0 0x4d4 0x000 0x0 0x0 | ||
| 165 | #define MX35_PAD_NFALE__USB_TOP_USBH2_STP 0x0d0 0x4d4 0x000 0x1 0x0 | ||
| 166 | #define MX35_PAD_NFALE__IPU_DISPB_CS0 0x0d0 0x4d4 0x000 0x2 0x0 | ||
| 167 | #define MX35_PAD_NFALE__GPIO2_20 0x0d0 0x4d4 0x898 0x5 0x0 | ||
| 168 | #define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 0x0d0 0x4d4 0x000 0x7 0x0 | ||
| 169 | #define MX35_PAD_NFCLE__EMI_NANDF_CLE 0x0d4 0x4d8 0x000 0x0 0x0 | ||
| 170 | #define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT 0x0d4 0x4d8 0x9f0 0x1 0x0 | ||
| 171 | #define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS 0x0d4 0x4d8 0x000 0x2 0x0 | ||
| 172 | #define MX35_PAD_NFCLE__GPIO2_21 0x0d4 0x4d8 0x89c 0x5 0x0 | ||
| 173 | #define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 0x0d4 0x4d8 0x000 0x7 0x0 | ||
| 174 | #define MX35_PAD_NFWP_B__EMI_NANDF_WP_B 0x0d8 0x4dc 0x000 0x0 0x0 | ||
| 175 | #define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 0x0d8 0x4dc 0x9e8 0x1 0x0 | ||
| 176 | #define MX35_PAD_NFWP_B__IPU_DISPB_WR 0x0d8 0x4dc 0x000 0x2 0x0 | ||
| 177 | #define MX35_PAD_NFWP_B__GPIO2_22 0x0d8 0x4dc 0x8a0 0x5 0x0 | ||
| 178 | #define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL 0x0d8 0x4dc 0x000 0x7 0x0 | ||
| 179 | #define MX35_PAD_NFRB__EMI_NANDF_RB 0x0dc 0x4e0 0x000 0x0 0x0 | ||
| 180 | #define MX35_PAD_NFRB__IPU_DISPB_RD 0x0dc 0x4e0 0x000 0x2 0x0 | ||
| 181 | #define MX35_PAD_NFRB__GPIO2_23 0x0dc 0x4e0 0x8a4 0x5 0x0 | ||
| 182 | #define MX35_PAD_NFRB__ARM11P_TOP_TRCLK 0x0dc 0x4e0 0x000 0x7 0x0 | ||
| 183 | #define MX35_PAD_D15__EMI_EIM_D_15 0x000 0x4e4 0x000 0x0 0x0 | ||
| 184 | #define MX35_PAD_D14__EMI_EIM_D_14 0x000 0x4e8 0x000 0x0 0x0 | ||
| 185 | #define MX35_PAD_D13__EMI_EIM_D_13 0x000 0x4ec 0x000 0x0 0x0 | ||
| 186 | #define MX35_PAD_D12__EMI_EIM_D_12 0x000 0x4f0 0x000 0x0 0x0 | ||
| 187 | #define MX35_PAD_D11__EMI_EIM_D_11 0x000 0x4f4 0x000 0x0 0x0 | ||
| 188 | #define MX35_PAD_D10__EMI_EIM_D_10 0x000 0x4f8 0x000 0x0 0x0 | ||
| 189 | #define MX35_PAD_D9__EMI_EIM_D_9 0x000 0x4fc 0x000 0x0 0x0 | ||
| 190 | #define MX35_PAD_D8__EMI_EIM_D_8 0x000 0x500 0x000 0x0 0x0 | ||
| 191 | #define MX35_PAD_D7__EMI_EIM_D_7 0x000 0x504 0x000 0x0 0x0 | ||
| 192 | #define MX35_PAD_D6__EMI_EIM_D_6 0x000 0x508 0x000 0x0 0x0 | ||
| 193 | #define MX35_PAD_D5__EMI_EIM_D_5 0x000 0x50c 0x000 0x0 0x0 | ||
| 194 | #define MX35_PAD_D4__EMI_EIM_D_4 0x000 0x510 0x000 0x0 0x0 | ||
| 195 | #define MX35_PAD_D3__EMI_EIM_D_3 0x000 0x514 0x000 0x0 0x0 | ||
| 196 | #define MX35_PAD_D2__EMI_EIM_D_2 0x000 0x518 0x000 0x0 0x0 | ||
| 197 | #define MX35_PAD_D1__EMI_EIM_D_1 0x000 0x51c 0x000 0x0 0x0 | ||
| 198 | #define MX35_PAD_D0__EMI_EIM_D_0 0x000 0x520 0x000 0x0 0x0 | ||
| 199 | #define MX35_PAD_CSI_D8__IPU_CSI_D_8 0x0e0 0x524 0x000 0x0 0x0 | ||
| 200 | #define MX35_PAD_CSI_D8__KPP_COL_0 0x0e0 0x524 0x950 0x1 0x0 | ||
| 201 | #define MX35_PAD_CSI_D8__GPIO1_20 0x0e0 0x524 0x83c 0x5 0x1 | ||
| 202 | #define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 0x0e0 0x524 0x000 0x7 0x0 | ||
| 203 | #define MX35_PAD_CSI_D9__IPU_CSI_D_9 0x0e4 0x528 0x000 0x0 0x0 | ||
| 204 | #define MX35_PAD_CSI_D9__KPP_COL_1 0x0e4 0x528 0x954 0x1 0x0 | ||
| 205 | #define MX35_PAD_CSI_D9__GPIO1_21 0x0e4 0x528 0x840 0x5 0x1 | ||
| 206 | #define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 0x0e4 0x528 0x000 0x7 0x0 | ||
| 207 | #define MX35_PAD_CSI_D10__IPU_CSI_D_10 0x0e8 0x52c 0x000 0x0 0x0 | ||
| 208 | #define MX35_PAD_CSI_D10__KPP_COL_2 0x0e8 0x52c 0x958 0x1 0x0 | ||
| 209 | #define MX35_PAD_CSI_D10__GPIO1_22 0x0e8 0x52c 0x844 0x5 0x1 | ||
| 210 | #define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 0x0e8 0x52c 0x000 0x7 0x0 | ||
| 211 | #define MX35_PAD_CSI_D11__IPU_CSI_D_11 0x0ec 0x530 0x000 0x0 0x0 | ||
| 212 | #define MX35_PAD_CSI_D11__KPP_COL_3 0x0ec 0x530 0x95c 0x1 0x0 | ||
| 213 | #define MX35_PAD_CSI_D11__GPIO1_23 0x0ec 0x530 0x000 0x5 0x0 | ||
| 214 | #define MX35_PAD_CSI_D12__IPU_CSI_D_12 0x0f0 0x534 0x000 0x0 0x0 | ||
| 215 | #define MX35_PAD_CSI_D12__KPP_ROW_0 0x0f0 0x534 0x970 0x1 0x0 | ||
| 216 | #define MX35_PAD_CSI_D12__GPIO1_24 0x0f0 0x534 0x000 0x5 0x0 | ||
| 217 | #define MX35_PAD_CSI_D13__IPU_CSI_D_13 0x0f4 0x538 0x000 0x0 0x0 | ||
| 218 | #define MX35_PAD_CSI_D13__KPP_ROW_1 0x0f4 0x538 0x974 0x1 0x0 | ||
| 219 | #define MX35_PAD_CSI_D13__GPIO1_25 0x0f4 0x538 0x000 0x5 0x0 | ||
| 220 | #define MX35_PAD_CSI_D14__IPU_CSI_D_14 0x0f8 0x53c 0x000 0x0 0x0 | ||
| 221 | #define MX35_PAD_CSI_D14__KPP_ROW_2 0x0f8 0x53c 0x978 0x1 0x0 | ||
| 222 | #define MX35_PAD_CSI_D14__GPIO1_26 0x0f8 0x53c 0x000 0x5 0x0 | ||
| 223 | #define MX35_PAD_CSI_D15__IPU_CSI_D_15 0x0fc 0x540 0x97c 0x0 0x0 | ||
| 224 | #define MX35_PAD_CSI_D15__KPP_ROW_3 0x0fc 0x540 0x000 0x1 0x0 | ||
| 225 | #define MX35_PAD_CSI_D15__GPIO1_27 0x0fc 0x540 0x000 0x5 0x0 | ||
| 226 | #define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK 0x100 0x544 0x000 0x0 0x0 | ||
| 227 | #define MX35_PAD_CSI_MCLK__GPIO1_28 0x100 0x544 0x000 0x5 0x0 | ||
| 228 | #define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC 0x104 0x548 0x000 0x0 0x0 | ||
| 229 | #define MX35_PAD_CSI_VSYNC__GPIO1_29 0x104 0x548 0x000 0x5 0x0 | ||
| 230 | #define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC 0x108 0x54c 0x000 0x0 0x0 | ||
| 231 | #define MX35_PAD_CSI_HSYNC__GPIO1_30 0x108 0x54c 0x000 0x5 0x0 | ||
| 232 | #define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK 0x10c 0x550 0x000 0x0 0x0 | ||
| 233 | #define MX35_PAD_CSI_PIXCLK__GPIO1_31 0x10c 0x550 0x000 0x5 0x0 | ||
| 234 | #define MX35_PAD_I2C1_CLK__I2C1_SCL 0x110 0x554 0x000 0x0 0x0 | ||
| 235 | #define MX35_PAD_I2C1_CLK__GPIO2_24 0x110 0x554 0x8a8 0x5 0x0 | ||
| 236 | #define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK 0x110 0x554 0x000 0x6 0x0 | ||
| 237 | #define MX35_PAD_I2C1_DAT__I2C1_SDA 0x114 0x558 0x000 0x0 0x0 | ||
| 238 | #define MX35_PAD_I2C1_DAT__GPIO2_25 0x114 0x558 0x8ac 0x5 0x0 | ||
| 239 | #define MX35_PAD_I2C2_CLK__I2C2_SCL 0x118 0x55c 0x000 0x0 0x0 | ||
| 240 | #define MX35_PAD_I2C2_CLK__CAN1_TXCAN 0x118 0x55c 0x000 0x1 0x0 | ||
| 241 | #define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR 0x118 0x55c 0x000 0x2 0x0 | ||
| 242 | #define MX35_PAD_I2C2_CLK__GPIO2_26 0x118 0x55c 0x8b0 0x5 0x0 | ||
| 243 | #define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 0x118 0x55c 0x000 0x6 0x0 | ||
| 244 | #define MX35_PAD_I2C2_DAT__I2C2_SDA 0x11c 0x560 0x000 0x0 0x0 | ||
| 245 | #define MX35_PAD_I2C2_DAT__CAN1_RXCAN 0x11c 0x560 0x7c8 0x1 0x0 | ||
| 246 | #define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC 0x11c 0x560 0x9f4 0x2 0x0 | ||
| 247 | #define MX35_PAD_I2C2_DAT__GPIO2_27 0x11c 0x560 0x8b4 0x5 0x0 | ||
| 248 | #define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 0x11c 0x560 0x000 0x6 0x0 | ||
| 249 | #define MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x120 0x564 0x000 0x0 0x0 | ||
| 250 | #define MX35_PAD_STXD4__GPIO2_28 0x120 0x564 0x8b8 0x5 0x0 | ||
| 251 | #define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 0x120 0x564 0x000 0x7 0x0 | ||
| 252 | #define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x124 0x568 0x000 0x0 0x0 | ||
| 253 | #define MX35_PAD_SRXD4__GPIO2_29 0x124 0x568 0x8bc 0x5 0x0 | ||
| 254 | #define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 0x124 0x568 0x000 0x7 0x0 | ||
| 255 | #define MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x128 0x56c 0x000 0x0 0x0 | ||
| 256 | #define MX35_PAD_SCK4__GPIO2_30 0x128 0x56c 0x8c4 0x5 0x0 | ||
| 257 | #define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 0x128 0x56c 0x000 0x7 0x0 | ||
| 258 | #define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x12c 0x570 0x000 0x0 0x0 | ||
| 259 | #define MX35_PAD_STXFS4__GPIO2_31 0x12c 0x570 0x8c8 0x5 0x0 | ||
| 260 | #define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 0x12c 0x570 0x000 0x7 0x0 | ||
| 261 | #define MX35_PAD_STXD5__AUDMUX_AUD5_TXD 0x130 0x574 0x000 0x0 0x0 | ||
| 262 | #define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 0x130 0x574 0x000 0x1 0x0 | ||
| 263 | #define MX35_PAD_STXD5__CSPI2_MOSI 0x130 0x574 0x7ec 0x2 0x0 | ||
| 264 | #define MX35_PAD_STXD5__GPIO1_0 0x130 0x574 0x82c 0x5 0x1 | ||
| 265 | #define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 0x130 0x574 0x000 0x7 0x0 | ||
| 266 | #define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD 0x134 0x578 0x000 0x0 0x0 | ||
| 267 | #define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 0x134 0x578 0x998 0x1 0x0 | ||
| 268 | #define MX35_PAD_SRXD5__CSPI2_MISO 0x134 0x578 0x7e8 0x2 0x0 | ||
| 269 | #define MX35_PAD_SRXD5__GPIO1_1 0x134 0x578 0x838 0x5 0x1 | ||
| 270 | #define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 0x134 0x578 0x000 0x7 0x0 | ||
| 271 | #define MX35_PAD_SCK5__AUDMUX_AUD5_TXC 0x138 0x57c 0x000 0x0 0x0 | ||
| 272 | #define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK 0x138 0x57c 0x994 0x1 0x0 | ||
| 273 | #define MX35_PAD_SCK5__CSPI2_SCLK 0x138 0x57c 0x7e0 0x2 0x0 | ||
| 274 | #define MX35_PAD_SCK5__GPIO1_2 0x138 0x57c 0x848 0x5 0x0 | ||
| 275 | #define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 0x138 0x57c 0x000 0x7 0x0 | ||
| 276 | #define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS 0x13c 0x580 0x000 0x0 0x0 | ||
| 277 | #define MX35_PAD_STXFS5__CSPI2_RDY 0x13c 0x580 0x7e4 0x2 0x0 | ||
| 278 | #define MX35_PAD_STXFS5__GPIO1_3 0x13c 0x580 0x84c 0x5 0x0 | ||
| 279 | #define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 0x13c 0x580 0x000 0x7 0x0 | ||
| 280 | #define MX35_PAD_SCKR__ESAI_SCKR 0x140 0x584 0x000 0x0 0x0 | ||
| 281 | #define MX35_PAD_SCKR__GPIO1_4 0x140 0x584 0x850 0x5 0x1 | ||
| 282 | #define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 0x140 0x584 0x000 0x7 0x0 | ||
| 283 | #define MX35_PAD_FSR__ESAI_FSR 0x144 0x588 0x000 0x0 0x0 | ||
| 284 | #define MX35_PAD_FSR__GPIO1_5 0x144 0x588 0x854 0x5 0x1 | ||
| 285 | #define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 0x144 0x588 0x000 0x7 0x0 | ||
| 286 | #define MX35_PAD_HCKR__ESAI_HCKR 0x148 0x58c 0x000 0x0 0x0 | ||
| 287 | #define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS 0x148 0x58c 0x000 0x1 0x0 | ||
| 288 | #define MX35_PAD_HCKR__CSPI2_SS0 0x148 0x58c 0x7f0 0x2 0x0 | ||
| 289 | #define MX35_PAD_HCKR__IPU_FLASH_STROBE 0x148 0x58c 0x000 0x3 0x0 | ||
| 290 | #define MX35_PAD_HCKR__GPIO1_6 0x148 0x58c 0x858 0x5 0x1 | ||
| 291 | #define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 0x148 0x58c 0x000 0x7 0x0 | ||
| 292 | #define MX35_PAD_SCKT__ESAI_SCKT 0x14c 0x590 0x000 0x0 0x0 | ||
| 293 | #define MX35_PAD_SCKT__GPIO1_7 0x14c 0x590 0x85c 0x5 0x1 | ||
| 294 | #define MX35_PAD_SCKT__IPU_CSI_D_0 0x14c 0x590 0x930 0x6 0x0 | ||
| 295 | #define MX35_PAD_SCKT__KPP_ROW_2 0x14c 0x590 0x978 0x7 0x1 | ||
| 296 | #define MX35_PAD_FST__ESAI_FST 0x150 0x594 0x000 0x0 0x0 | ||
| 297 | #define MX35_PAD_FST__GPIO1_8 0x150 0x594 0x860 0x5 0x1 | ||
| 298 | #define MX35_PAD_FST__IPU_CSI_D_1 0x150 0x594 0x934 0x6 0x0 | ||
| 299 | #define MX35_PAD_FST__KPP_ROW_3 0x150 0x594 0x97c 0x7 0x1 | ||
| 300 | #define MX35_PAD_HCKT__ESAI_HCKT 0x154 0x598 0x000 0x0 0x0 | ||
| 301 | #define MX35_PAD_HCKT__AUDMUX_AUD5_RXC 0x154 0x598 0x7a8 0x1 0x0 | ||
| 302 | #define MX35_PAD_HCKT__GPIO1_9 0x154 0x598 0x864 0x5 0x0 | ||
| 303 | #define MX35_PAD_HCKT__IPU_CSI_D_2 0x154 0x598 0x938 0x6 0x0 | ||
| 304 | #define MX35_PAD_HCKT__KPP_COL_3 0x154 0x598 0x95c 0x7 0x1 | ||
| 305 | #define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 0x158 0x59c 0x000 0x0 0x0 | ||
| 306 | #define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC 0x158 0x59c 0x000 0x1 0x0 | ||
| 307 | #define MX35_PAD_TX5_RX0__CSPI2_SS2 0x158 0x59c 0x7f8 0x2 0x1 | ||
| 308 | #define MX35_PAD_TX5_RX0__CAN2_TXCAN 0x158 0x59c 0x000 0x3 0x0 | ||
| 309 | #define MX35_PAD_TX5_RX0__UART2_DTR 0x158 0x59c 0x000 0x4 0x0 | ||
| 310 | #define MX35_PAD_TX5_RX0__GPIO1_10 0x158 0x59c 0x830 0x5 0x0 | ||
| 311 | #define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 0x158 0x59c 0x000 0x7 0x0 | ||
| 312 | #define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 0x15c 0x5a0 0x000 0x0 0x0 | ||
| 313 | #define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS 0x15c 0x5a0 0x000 0x1 0x0 | ||
| 314 | #define MX35_PAD_TX4_RX1__CSPI2_SS3 0x15c 0x5a0 0x7fc 0x2 0x0 | ||
| 315 | #define MX35_PAD_TX4_RX1__CAN2_RXCAN 0x15c 0x5a0 0x7cc 0x3 0x0 | ||
| 316 | #define MX35_PAD_TX4_RX1__UART2_DSR 0x15c 0x5a0 0x000 0x4 0x0 | ||
| 317 | #define MX35_PAD_TX4_RX1__GPIO1_11 0x15c 0x5a0 0x834 0x5 0x0 | ||
| 318 | #define MX35_PAD_TX4_RX1__IPU_CSI_D_3 0x15c 0x5a0 0x93c 0x6 0x0 | ||
| 319 | #define MX35_PAD_TX4_RX1__KPP_ROW_0 0x15c 0x5a0 0x970 0x7 0x1 | ||
| 320 | #define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 0x160 0x5a4 0x000 0x0 0x0 | ||
| 321 | #define MX35_PAD_TX3_RX2__I2C3_SCL 0x160 0x5a4 0x91c 0x1 0x0 | ||
| 322 | #define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 0x160 0x5a4 0x000 0x3 0x0 | ||
| 323 | #define MX35_PAD_TX3_RX2__GPIO1_12 0x160 0x5a4 0x000 0x5 0x0 | ||
| 324 | #define MX35_PAD_TX3_RX2__IPU_CSI_D_4 0x160 0x5a4 0x940 0x6 0x0 | ||
| 325 | #define MX35_PAD_TX3_RX2__KPP_ROW_1 0x160 0x5a4 0x974 0x7 0x1 | ||
| 326 | #define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 0x164 0x5a8 0x000 0x0 0x0 | ||
| 327 | #define MX35_PAD_TX2_RX3__I2C3_SDA 0x164 0x5a8 0x920 0x1 0x0 | ||
| 328 | #define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 0x164 0x5a8 0x000 0x3 0x0 | ||
| 329 | #define MX35_PAD_TX2_RX3__GPIO1_13 0x164 0x5a8 0x000 0x5 0x0 | ||
| 330 | #define MX35_PAD_TX2_RX3__IPU_CSI_D_5 0x164 0x5a8 0x944 0x6 0x0 | ||
| 331 | #define MX35_PAD_TX2_RX3__KPP_COL_0 0x164 0x5a8 0x950 0x7 0x1 | ||
| 332 | #define MX35_PAD_TX1__ESAI_TX1 0x168 0x5ac 0x000 0x0 0x0 | ||
| 333 | #define MX35_PAD_TX1__CCM_PMIC_RDY 0x168 0x5ac 0x7d4 0x1 0x1 | ||
| 334 | #define MX35_PAD_TX1__CSPI1_SS2 0x168 0x5ac 0x7d8 0x2 0x2 | ||
| 335 | #define MX35_PAD_TX1__EMI_NANDF_CE3 0x168 0x5ac 0x000 0x3 0x0 | ||
| 336 | #define MX35_PAD_TX1__UART2_RI 0x168 0x5ac 0x000 0x4 0x0 | ||
| 337 | #define MX35_PAD_TX1__GPIO1_14 0x168 0x5ac 0x000 0x5 0x0 | ||
| 338 | #define MX35_PAD_TX1__IPU_CSI_D_6 0x168 0x5ac 0x948 0x6 0x0 | ||
| 339 | #define MX35_PAD_TX1__KPP_COL_1 0x168 0x5ac 0x954 0x7 0x1 | ||
| 340 | #define MX35_PAD_TX0__ESAI_TX0 0x16c 0x5b0 0x000 0x0 0x0 | ||
| 341 | #define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK 0x16c 0x5b0 0x994 0x1 0x1 | ||
| 342 | #define MX35_PAD_TX0__CSPI1_SS3 0x16c 0x5b0 0x7dc 0x2 0x0 | ||
| 343 | #define MX35_PAD_TX0__EMI_DTACK_B 0x16c 0x5b0 0x800 0x3 0x1 | ||
| 344 | #define MX35_PAD_TX0__UART2_DCD 0x16c 0x5b0 0x000 0x4 0x0 | ||
| 345 | #define MX35_PAD_TX0__GPIO1_15 0x16c 0x5b0 0x000 0x5 0x0 | ||
| 346 | #define MX35_PAD_TX0__IPU_CSI_D_7 0x16c 0x5b0 0x94c 0x6 0x0 | ||
| 347 | #define MX35_PAD_TX0__KPP_COL_2 0x16c 0x5b0 0x958 0x7 0x1 | ||
| 348 | #define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI 0x170 0x5b4 0x000 0x0 0x0 | ||
| 349 | #define MX35_PAD_CSPI1_MOSI__GPIO1_16 0x170 0x5b4 0x000 0x5 0x0 | ||
| 350 | #define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 0x170 0x5b4 0x000 0x7 0x0 | ||
| 351 | #define MX35_PAD_CSPI1_MISO__CSPI1_MISO 0x174 0x5b8 0x000 0x0 0x0 | ||
| 352 | #define MX35_PAD_CSPI1_MISO__GPIO1_17 0x174 0x5b8 0x000 0x5 0x0 | ||
| 353 | #define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 0x174 0x5b8 0x000 0x7 0x0 | ||
| 354 | #define MX35_PAD_CSPI1_SS0__CSPI1_SS0 0x178 0x5bc 0x000 0x0 0x0 | ||
| 355 | #define MX35_PAD_CSPI1_SS0__OWIRE_LINE 0x178 0x5bc 0x990 0x1 0x1 | ||
| 356 | #define MX35_PAD_CSPI1_SS0__CSPI2_SS3 0x178 0x5bc 0x7fc 0x2 0x1 | ||
| 357 | #define MX35_PAD_CSPI1_SS0__GPIO1_18 0x178 0x5bc 0x000 0x5 0x0 | ||
| 358 | #define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 0x178 0x5bc 0x000 0x7 0x0 | ||
| 359 | #define MX35_PAD_CSPI1_SS1__CSPI1_SS1 0x17c 0x5c0 0x000 0x0 0x0 | ||
| 360 | #define MX35_PAD_CSPI1_SS1__PWM_PWMO 0x17c 0x5c0 0x000 0x1 0x0 | ||
| 361 | #define MX35_PAD_CSPI1_SS1__CCM_CLK32K 0x17c 0x5c0 0x7d0 0x2 0x1 | ||
| 362 | #define MX35_PAD_CSPI1_SS1__GPIO1_19 0x17c 0x5c0 0x000 0x5 0x0 | ||
| 363 | #define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 0x17c 0x5c0 0x000 0x6 0x0 | ||
| 364 | #define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 0x17c 0x5c0 0x000 0x7 0x0 | ||
| 365 | #define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK 0x180 0x5c4 0x000 0x0 0x0 | ||
| 366 | #define MX35_PAD_CSPI1_SCLK__GPIO3_4 0x180 0x5c4 0x904 0x5 0x0 | ||
| 367 | #define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 0x180 0x5c4 0x000 0x6 0x0 | ||
| 368 | #define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 0x180 0x5c4 0x000 0x7 0x0 | ||
| 369 | #define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY 0x184 0x5c8 0x000 0x0 0x0 | ||
| 370 | #define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 0x184 0x5c8 0x908 0x5 0x0 | ||
| 371 | #define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 0x184 0x5c8 0x000 0x6 0x0 | ||
| 372 | #define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 0x184 0x5c8 0x000 0x7 0x0 | ||
| 373 | #define MX35_PAD_RXD1__UART1_RXD_MUX 0x188 0x5cc 0x000 0x0 0x0 | ||
| 374 | #define MX35_PAD_RXD1__CSPI2_MOSI 0x188 0x5cc 0x7ec 0x1 0x1 | ||
| 375 | #define MX35_PAD_RXD1__KPP_COL_4 0x188 0x5cc 0x960 0x4 0x0 | ||
| 376 | #define MX35_PAD_RXD1__GPIO3_6 0x188 0x5cc 0x90c 0x5 0x0 | ||
| 377 | #define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 0x188 0x5cc 0x000 0x7 0x0 | ||
| 378 | #define MX35_PAD_TXD1__UART1_TXD_MUX 0x18c 0x5d0 0x000 0x0 0x0 | ||
| 379 | #define MX35_PAD_TXD1__CSPI2_MISO 0x18c 0x5d0 0x7e8 0x1 0x1 | ||
| 380 | #define MX35_PAD_TXD1__KPP_COL_5 0x18c 0x5d0 0x964 0x4 0x0 | ||
| 381 | #define MX35_PAD_TXD1__GPIO3_7 0x18c 0x5d0 0x910 0x5 0x0 | ||
| 382 | #define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 0x18c 0x5d0 0x000 0x7 0x0 | ||
| 383 | #define MX35_PAD_RTS1__UART1_RTS 0x190 0x5d4 0x000 0x0 0x0 | ||
| 384 | #define MX35_PAD_RTS1__CSPI2_SCLK 0x190 0x5d4 0x7e0 0x1 0x1 | ||
| 385 | #define MX35_PAD_RTS1__I2C3_SCL 0x190 0x5d4 0x91c 0x2 0x1 | ||
| 386 | #define MX35_PAD_RTS1__IPU_CSI_D_0 0x190 0x5d4 0x930 0x3 0x1 | ||
| 387 | #define MX35_PAD_RTS1__KPP_COL_6 0x190 0x5d4 0x968 0x4 0x0 | ||
| 388 | #define MX35_PAD_RTS1__GPIO3_8 0x190 0x5d4 0x914 0x5 0x0 | ||
| 389 | #define MX35_PAD_RTS1__EMI_NANDF_CE1 0x190 0x5d4 0x000 0x6 0x0 | ||
| 390 | #define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 0x190 0x5d4 0x000 0x7 0x0 | ||
| 391 | #define MX35_PAD_CTS1__UART1_CTS 0x194 0x5d8 0x000 0x0 0x0 | ||
| 392 | #define MX35_PAD_CTS1__CSPI2_RDY 0x194 0x5d8 0x7e4 0x1 0x1 | ||
| 393 | #define MX35_PAD_CTS1__I2C3_SDA 0x194 0x5d8 0x920 0x2 0x1 | ||
| 394 | #define MX35_PAD_CTS1__IPU_CSI_D_1 0x194 0x5d8 0x934 0x3 0x1 | ||
| 395 | #define MX35_PAD_CTS1__KPP_COL_7 0x194 0x5d8 0x96c 0x4 0x0 | ||
| 396 | #define MX35_PAD_CTS1__GPIO3_9 0x194 0x5d8 0x918 0x5 0x0 | ||
| 397 | #define MX35_PAD_CTS1__EMI_NANDF_CE2 0x194 0x5d8 0x000 0x6 0x0 | ||
| 398 | #define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 0x194 0x5d8 0x000 0x7 0x0 | ||
| 399 | #define MX35_PAD_RXD2__UART2_RXD_MUX 0x198 0x5dc 0x000 0x0 0x0 | ||
| 400 | #define MX35_PAD_RXD2__KPP_ROW_4 0x198 0x5dc 0x980 0x4 0x0 | ||
| 401 | #define MX35_PAD_RXD2__GPIO3_10 0x198 0x5dc 0x8ec 0x5 0x0 | ||
| 402 | #define MX35_PAD_TXD2__UART2_TXD_MUX 0x19c 0x5e0 0x000 0x0 0x0 | ||
| 403 | #define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK 0x19c 0x5e0 0x994 0x1 0x2 | ||
| 404 | #define MX35_PAD_TXD2__KPP_ROW_5 0x19c 0x5e0 0x984 0x4 0x0 | ||
| 405 | #define MX35_PAD_TXD2__GPIO3_11 0x19c 0x5e0 0x8f0 0x5 0x0 | ||
| 406 | #define MX35_PAD_RTS2__UART2_RTS 0x1a0 0x5e4 0x000 0x0 0x0 | ||
| 407 | #define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 0x1a0 0x5e4 0x998 0x1 0x1 | ||
| 408 | #define MX35_PAD_RTS2__CAN2_RXCAN 0x1a0 0x5e4 0x7cc 0x2 0x1 | ||
| 409 | #define MX35_PAD_RTS2__IPU_CSI_D_2 0x1a0 0x5e4 0x938 0x3 0x1 | ||
| 410 | #define MX35_PAD_RTS2__KPP_ROW_6 0x1a0 0x5e4 0x988 0x4 0x0 | ||
| 411 | #define MX35_PAD_RTS2__GPIO3_12 0x1a0 0x5e4 0x8f4 0x5 0x0 | ||
| 412 | #define MX35_PAD_RTS2__AUDMUX_AUD5_RXC 0x1a0 0x5e4 0x000 0x6 0x0 | ||
| 413 | #define MX35_PAD_RTS2__UART3_RXD_MUX 0x1a0 0x5e4 0x9a0 0x7 0x0 | ||
| 414 | #define MX35_PAD_CTS2__UART2_CTS 0x1a4 0x5e8 0x000 0x0 0x0 | ||
| 415 | #define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 0x1a4 0x5e8 0x000 0x1 0x0 | ||
| 416 | #define MX35_PAD_CTS2__CAN2_TXCAN 0x1a4 0x5e8 0x000 0x2 0x0 | ||
| 417 | #define MX35_PAD_CTS2__IPU_CSI_D_3 0x1a4 0x5e8 0x93c 0x3 0x1 | ||
| 418 | #define MX35_PAD_CTS2__KPP_ROW_7 0x1a4 0x5e8 0x98c 0x4 0x0 | ||
| 419 | #define MX35_PAD_CTS2__GPIO3_13 0x1a4 0x5e8 0x8f8 0x5 0x0 | ||
| 420 | #define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS 0x1a4 0x5e8 0x000 0x6 0x0 | ||
| 421 | #define MX35_PAD_CTS2__UART3_TXD_MUX 0x1a4 0x5e8 0x000 0x7 0x0 | ||
| 422 | #define MX35_PAD_RTCK__ARM11P_TOP_RTCK 0x000 0x5ec 0x000 0x0 0x0 | ||
| 423 | #define MX35_PAD_TCK__SJC_TCK 0x000 0x5f0 0x000 0x0 0x0 | ||
| 424 | #define MX35_PAD_TMS__SJC_TMS 0x000 0x5f4 0x000 0x0 0x0 | ||
| 425 | #define MX35_PAD_TDI__SJC_TDI 0x000 0x5f8 0x000 0x0 0x0 | ||
| 426 | #define MX35_PAD_TDO__SJC_TDO 0x000 0x5fc 0x000 0x0 0x0 | ||
| 427 | #define MX35_PAD_TRSTB__SJC_TRSTB 0x000 0x600 0x000 0x0 0x0 | ||
| 428 | #define MX35_PAD_DE_B__SJC_DE_B 0x000 0x604 0x000 0x0 0x0 | ||
| 429 | #define MX35_PAD_SJC_MOD__SJC_MOD 0x000 0x608 0x000 0x0 0x0 | ||
| 430 | #define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR 0x1a8 0x60c 0x000 0x0 0x0 | ||
| 431 | #define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR 0x1a8 0x60c 0x000 0x1 0x0 | ||
| 432 | #define MX35_PAD_USBOTG_PWR__GPIO3_14 0x1a8 0x60c 0x8fc 0x5 0x0 | ||
| 433 | #define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC 0x1ac 0x610 0x000 0x0 0x0 | ||
| 434 | #define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC 0x1ac 0x610 0x9f4 0x1 0x1 | ||
| 435 | #define MX35_PAD_USBOTG_OC__GPIO3_15 0x1ac 0x610 0x900 0x5 0x0 | ||
| 436 | #define MX35_PAD_LD0__IPU_DISPB_DAT_0 0x1b0 0x614 0x000 0x0 0x0 | ||
| 437 | #define MX35_PAD_LD0__GPIO2_0 0x1b0 0x614 0x868 0x5 0x1 | ||
| 438 | #define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 0x1b0 0x614 0x000 0x6 0x0 | ||
| 439 | #define MX35_PAD_LD1__IPU_DISPB_DAT_1 0x1b4 0x618 0x000 0x0 0x0 | ||
| 440 | #define MX35_PAD_LD1__GPIO2_1 0x1b4 0x618 0x894 0x5 0x0 | ||
| 441 | #define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 0x1b4 0x618 0x000 0x6 0x0 | ||
| 442 | #define MX35_PAD_LD2__IPU_DISPB_DAT_2 0x1b8 0x61c 0x000 0x0 0x0 | ||
| 443 | #define MX35_PAD_LD2__GPIO2_2 0x1b8 0x61c 0x8c0 0x5 0x0 | ||
| 444 | #define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 0x1b8 0x61c 0x000 0x6 0x0 | ||
| 445 | #define MX35_PAD_LD3__IPU_DISPB_DAT_3 0x1bc 0x620 0x000 0x0 0x0 | ||
| 446 | #define MX35_PAD_LD3__GPIO2_3 0x1bc 0x620 0x8cc 0x5 0x0 | ||
| 447 | #define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 0x1bc 0x620 0x000 0x6 0x0 | ||
| 448 | #define MX35_PAD_LD4__IPU_DISPB_DAT_4 0x1c0 0x624 0x000 0x0 0x0 | ||
| 449 | #define MX35_PAD_LD4__GPIO2_4 0x1c0 0x624 0x8d0 0x5 0x0 | ||
| 450 | #define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 0x1c0 0x624 0x000 0x6 0x0 | ||
| 451 | #define MX35_PAD_LD5__IPU_DISPB_DAT_5 0x1c4 0x628 0x000 0x0 0x0 | ||
| 452 | #define MX35_PAD_LD5__GPIO2_5 0x1c4 0x628 0x8d4 0x5 0x0 | ||
| 453 | #define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 0x1c4 0x628 0x000 0x6 0x0 | ||
| 454 | #define MX35_PAD_LD6__IPU_DISPB_DAT_6 0x1c8 0x62c 0x000 0x0 0x0 | ||
| 455 | #define MX35_PAD_LD6__GPIO2_6 0x1c8 0x62c 0x8d8 0x5 0x0 | ||
| 456 | #define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 0x1c8 0x62c 0x000 0x6 0x0 | ||
| 457 | #define MX35_PAD_LD7__IPU_DISPB_DAT_7 0x1cc 0x630 0x000 0x0 0x0 | ||
| 458 | #define MX35_PAD_LD7__GPIO2_7 0x1cc 0x630 0x8dc 0x5 0x0 | ||
| 459 | #define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 0x1cc 0x630 0x000 0x6 0x0 | ||
| 460 | #define MX35_PAD_LD8__IPU_DISPB_DAT_8 0x1d0 0x634 0x000 0x0 0x0 | ||
| 461 | #define MX35_PAD_LD8__GPIO2_8 0x1d0 0x634 0x8e0 0x5 0x0 | ||
| 462 | #define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 0x1d0 0x634 0x000 0x6 0x0 | ||
| 463 | #define MX35_PAD_LD9__IPU_DISPB_DAT_9 0x1d4 0x638 0x000 0x0 0x0 | ||
| 464 | #define MX35_PAD_LD9__GPIO2_9 0x1d4 0x638 0x8e4 0x5 0x0 | ||
| 465 | #define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 0x1d4 0x638 0x000 0x6 0x0 | ||
| 466 | #define MX35_PAD_LD10__IPU_DISPB_DAT_10 0x1d8 0x63c 0x000 0x0 0x0 | ||
| 467 | #define MX35_PAD_LD10__GPIO2_10 0x1d8 0x63c 0x86c 0x5 0x0 | ||
| 468 | #define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 0x1d8 0x63c 0x000 0x6 0x0 | ||
| 469 | #define MX35_PAD_LD11__IPU_DISPB_DAT_11 0x1dc 0x640 0x000 0x0 0x0 | ||
| 470 | #define MX35_PAD_LD11__GPIO2_11 0x1dc 0x640 0x870 0x5 0x0 | ||
| 471 | #define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 0x1dc 0x640 0x000 0x6 0x0 | ||
| 472 | #define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 0x1dc 0x640 0x000 0x7 0x0 | ||
| 473 | #define MX35_PAD_LD12__IPU_DISPB_DAT_12 0x1e0 0x644 0x000 0x0 0x0 | ||
| 474 | #define MX35_PAD_LD12__GPIO2_12 0x1e0 0x644 0x874 0x5 0x0 | ||
| 475 | #define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 0x1e0 0x644 0x000 0x6 0x0 | ||
| 476 | #define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 0x1e0 0x644 0x000 0x7 0x0 | ||
| 477 | #define MX35_PAD_LD13__IPU_DISPB_DAT_13 0x1e4 0x648 0x000 0x0 0x0 | ||
| 478 | #define MX35_PAD_LD13__GPIO2_13 0x1e4 0x648 0x878 0x5 0x0 | ||
| 479 | #define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 0x1e4 0x648 0x000 0x6 0x0 | ||
| 480 | #define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 0x1e4 0x648 0x000 0x7 0x0 | ||
| 481 | #define MX35_PAD_LD14__IPU_DISPB_DAT_14 0x1e8 0x64c 0x000 0x0 0x0 | ||
| 482 | #define MX35_PAD_LD14__GPIO2_14 0x1e8 0x64c 0x87c 0x5 0x0 | ||
| 483 | #define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 0x1e8 0x64c 0x000 0x6 0x0 | ||
| 484 | #define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 0x1e8 0x64c 0x000 0x7 0x0 | ||
| 485 | #define MX35_PAD_LD15__IPU_DISPB_DAT_15 0x1ec 0x650 0x000 0x0 0x0 | ||
| 486 | #define MX35_PAD_LD15__GPIO2_15 0x1ec 0x650 0x880 0x5 0x0 | ||
| 487 | #define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 0x1ec 0x650 0x000 0x6 0x0 | ||
| 488 | #define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 0x1ec 0x650 0x000 0x7 0x0 | ||
| 489 | #define MX35_PAD_LD16__IPU_DISPB_DAT_16 0x1f0 0x654 0x000 0x0 0x0 | ||
| 490 | #define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC 0x1f0 0x654 0x928 0x2 0x0 | ||
| 491 | #define MX35_PAD_LD16__GPIO2_16 0x1f0 0x654 0x884 0x5 0x0 | ||
| 492 | #define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 0x1f0 0x654 0x000 0x6 0x0 | ||
| 493 | #define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 0x1f0 0x654 0x000 0x7 0x0 | ||
| 494 | #define MX35_PAD_LD17__IPU_DISPB_DAT_17 0x1f4 0x658 0x000 0x0 0x0 | ||
| 495 | #define MX35_PAD_LD17__IPU_DISPB_CS2 0x1f4 0x658 0x000 0x2 0x0 | ||
| 496 | #define MX35_PAD_LD17__GPIO2_17 0x1f4 0x658 0x888 0x5 0x0 | ||
| 497 | #define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 0x1f4 0x658 0x000 0x6 0x0 | ||
| 498 | #define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 0x1f4 0x658 0x000 0x7 0x0 | ||
| 499 | #define MX35_PAD_LD18__IPU_DISPB_DAT_18 0x1f8 0x65c 0x000 0x0 0x0 | ||
| 500 | #define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC 0x1f8 0x65c 0x924 0x1 0x1 | ||
| 501 | #define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC 0x1f8 0x65c 0x928 0x2 0x1 | ||
| 502 | #define MX35_PAD_LD18__ESDHC3_CMD 0x1f8 0x65c 0x818 0x3 0x0 | ||
| 503 | #define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 0x1f8 0x65c 0x9b0 0x4 0x0 | ||
| 504 | #define MX35_PAD_LD18__GPIO3_24 0x1f8 0x65c 0x000 0x5 0x0 | ||
| 505 | #define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 0x1f8 0x65c 0x000 0x6 0x0 | ||
| 506 | #define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 0x1f8 0x65c 0x000 0x7 0x0 | ||
| 507 | #define MX35_PAD_LD19__IPU_DISPB_DAT_19 0x1fc 0x660 0x000 0x0 0x0 | ||
| 508 | #define MX35_PAD_LD19__IPU_DISPB_BCLK 0x1fc 0x660 0x000 0x1 0x0 | ||
| 509 | #define MX35_PAD_LD19__IPU_DISPB_CS1 0x1fc 0x660 0x000 0x2 0x0 | ||
| 510 | #define MX35_PAD_LD19__ESDHC3_CLK 0x1fc 0x660 0x814 0x3 0x0 | ||
| 511 | #define MX35_PAD_LD19__USB_TOP_USBOTG_DIR 0x1fc 0x660 0x9c4 0x4 0x0 | ||
| 512 | #define MX35_PAD_LD19__GPIO3_25 0x1fc 0x660 0x000 0x5 0x0 | ||
| 513 | #define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 0x1fc 0x660 0x000 0x6 0x0 | ||
| 514 | #define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 0x1fc 0x660 0x000 0x7 0x0 | ||
| 515 | #define MX35_PAD_LD20__IPU_DISPB_DAT_20 0x200 0x664 0x000 0x0 0x0 | ||
| 516 | #define MX35_PAD_LD20__IPU_DISPB_CS0 0x200 0x664 0x000 0x1 0x0 | ||
| 517 | #define MX35_PAD_LD20__IPU_DISPB_SD_CLK 0x200 0x664 0x000 0x2 0x0 | ||
| 518 | #define MX35_PAD_LD20__ESDHC3_DAT0 0x200 0x664 0x81c 0x3 0x0 | ||
| 519 | #define MX35_PAD_LD20__GPIO3_26 0x200 0x664 0x000 0x5 0x0 | ||
| 520 | #define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 0x200 0x664 0x000 0x6 0x0 | ||
| 521 | #define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 0x200 0x664 0x000 0x7 0x0 | ||
| 522 | #define MX35_PAD_LD21__IPU_DISPB_DAT_21 0x204 0x668 0x000 0x0 0x0 | ||
| 523 | #define MX35_PAD_LD21__IPU_DISPB_PAR_RS 0x204 0x668 0x000 0x1 0x0 | ||
| 524 | #define MX35_PAD_LD21__IPU_DISPB_SER_RS 0x204 0x668 0x000 0x2 0x0 | ||
| 525 | #define MX35_PAD_LD21__ESDHC3_DAT1 0x204 0x668 0x820 0x3 0x0 | ||
| 526 | #define MX35_PAD_LD21__USB_TOP_USBOTG_STP 0x204 0x668 0x000 0x4 0x0 | ||
| 527 | #define MX35_PAD_LD21__GPIO3_27 0x204 0x668 0x000 0x5 0x0 | ||
| 528 | #define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x204 0x668 0x000 0x6 0x0 | ||
| 529 | #define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 0x204 0x668 0x000 0x7 0x0 | ||
| 530 | #define MX35_PAD_LD22__IPU_DISPB_DAT_22 0x208 0x66c 0x000 0x0 0x0 | ||
| 531 | #define MX35_PAD_LD22__IPU_DISPB_WR 0x208 0x66c 0x000 0x1 0x0 | ||
| 532 | #define MX35_PAD_LD22__IPU_DISPB_SD_D_I 0x208 0x66c 0x92c 0x2 0x0 | ||
| 533 | #define MX35_PAD_LD22__ESDHC3_DAT2 0x208 0x66c 0x824 0x3 0x0 | ||
| 534 | #define MX35_PAD_LD22__USB_TOP_USBOTG_NXT 0x208 0x66c 0x9c8 0x4 0x0 | ||
| 535 | #define MX35_PAD_LD22__GPIO3_28 0x208 0x66c 0x000 0x5 0x0 | ||
| 536 | #define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR 0x208 0x66c 0x000 0x6 0x0 | ||
| 537 | #define MX35_PAD_LD22__ARM11P_TOP_TRCTL 0x208 0x66c 0x000 0x7 0x0 | ||
| 538 | #define MX35_PAD_LD23__IPU_DISPB_DAT_23 0x20c 0x670 0x000 0x0 0x0 | ||
| 539 | #define MX35_PAD_LD23__IPU_DISPB_RD 0x20c 0x670 0x000 0x1 0x0 | ||
| 540 | #define MX35_PAD_LD23__IPU_DISPB_SD_D_IO 0x20c 0x670 0x92c 0x2 0x1 | ||
| 541 | #define MX35_PAD_LD23__ESDHC3_DAT3 0x20c 0x670 0x828 0x3 0x0 | ||
| 542 | #define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 0x20c 0x670 0x9c0 0x4 0x0 | ||
| 543 | #define MX35_PAD_LD23__GPIO3_29 0x20c 0x670 0x000 0x5 0x0 | ||
| 544 | #define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS 0x20c 0x670 0x000 0x6 0x0 | ||
| 545 | #define MX35_PAD_LD23__ARM11P_TOP_TRCLK 0x20c 0x670 0x000 0x7 0x0 | ||
| 546 | #define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC 0x210 0x674 0x000 0x0 0x0 | ||
| 547 | #define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO 0x210 0x674 0x92c 0x2 0x2 | ||
| 548 | #define MX35_PAD_D3_HSYNC__GPIO3_30 0x210 0x674 0x000 0x5 0x0 | ||
| 549 | #define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE 0x210 0x674 0x000 0x6 0x0 | ||
| 550 | #define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 0x210 0x674 0x000 0x7 0x0 | ||
| 551 | #define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK 0x214 0x678 0x000 0x0 0x0 | ||
| 552 | #define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK 0x214 0x678 0x000 0x2 0x0 | ||
| 553 | #define MX35_PAD_D3_FPSHIFT__GPIO3_31 0x214 0x678 0x000 0x5 0x0 | ||
| 554 | #define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 0x214 0x678 0x000 0x6 0x0 | ||
| 555 | #define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 0x214 0x678 0x000 0x7 0x0 | ||
| 556 | #define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY 0x218 0x67c 0x000 0x0 0x0 | ||
| 557 | #define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O 0x218 0x67c 0x000 0x2 0x0 | ||
| 558 | #define MX35_PAD_D3_DRDY__GPIO1_0 0x218 0x67c 0x82c 0x5 0x2 | ||
| 559 | #define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 0x218 0x67c 0x000 0x6 0x0 | ||
| 560 | #define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 0x218 0x67c 0x000 0x7 0x0 | ||
| 561 | #define MX35_PAD_CONTRAST__IPU_DISPB_CONTR 0x21c 0x680 0x000 0x0 0x0 | ||
| 562 | #define MX35_PAD_CONTRAST__GPIO1_1 0x21c 0x680 0x838 0x5 0x2 | ||
| 563 | #define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 0x21c 0x680 0x000 0x6 0x0 | ||
| 564 | #define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 0x21c 0x680 0x000 0x7 0x0 | ||
| 565 | #define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC 0x220 0x684 0x000 0x0 0x0 | ||
| 566 | #define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 0x220 0x684 0x000 0x2 0x0 | ||
| 567 | #define MX35_PAD_D3_VSYNC__GPIO1_2 0x220 0x684 0x848 0x5 0x1 | ||
| 568 | #define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD 0x220 0x684 0x000 0x6 0x0 | ||
| 569 | #define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 0x220 0x684 0x000 0x7 0x0 | ||
| 570 | #define MX35_PAD_D3_REV__IPU_DISPB_D3_REV 0x224 0x688 0x000 0x0 0x0 | ||
| 571 | #define MX35_PAD_D3_REV__IPU_DISPB_SER_RS 0x224 0x688 0x000 0x2 0x0 | ||
| 572 | #define MX35_PAD_D3_REV__GPIO1_3 0x224 0x688 0x84c 0x5 0x1 | ||
| 573 | #define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB 0x224 0x688 0x000 0x6 0x0 | ||
| 574 | #define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 0x224 0x688 0x000 0x7 0x0 | ||
| 575 | #define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS 0x228 0x68c 0x000 0x0 0x0 | ||
| 576 | #define MX35_PAD_D3_CLS__IPU_DISPB_CS2 0x228 0x68c 0x000 0x2 0x0 | ||
| 577 | #define MX35_PAD_D3_CLS__GPIO1_4 0x228 0x68c 0x850 0x5 0x2 | ||
| 578 | #define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 0x228 0x68c 0x000 0x6 0x0 | ||
| 579 | #define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 0x228 0x68c 0x000 0x7 0x0 | ||
| 580 | #define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL 0x22c 0x690 0x000 0x0 0x0 | ||
| 581 | #define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC 0x22c 0x690 0x928 0x2 0x2 | ||
| 582 | #define MX35_PAD_D3_SPL__GPIO1_5 0x22c 0x690 0x854 0x5 0x2 | ||
| 583 | #define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 0x22c 0x690 0x000 0x6 0x0 | ||
| 584 | #define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 0x22c 0x690 0x000 0x7 0x0 | ||
| 585 | #define MX35_PAD_SD1_CMD__ESDHC1_CMD 0x230 0x694 0x000 0x0 0x0 | ||
| 586 | #define MX35_PAD_SD1_CMD__MSHC_SCLK 0x230 0x694 0x000 0x1 0x0 | ||
| 587 | #define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC 0x230 0x694 0x924 0x3 0x2 | ||
| 588 | #define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 0x230 0x694 0x9b4 0x4 0x0 | ||
| 589 | #define MX35_PAD_SD1_CMD__GPIO1_6 0x230 0x694 0x858 0x5 0x2 | ||
| 590 | #define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL 0x230 0x694 0x000 0x7 0x0 | ||
| 591 | #define MX35_PAD_SD1_CLK__ESDHC1_CLK 0x234 0x698 0x000 0x0 0x0 | ||
| 592 | #define MX35_PAD_SD1_CLK__MSHC_BS 0x234 0x698 0x000 0x1 0x0 | ||
| 593 | #define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK 0x234 0x698 0x000 0x3 0x0 | ||
| 594 | #define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 0x234 0x698 0x9b8 0x4 0x0 | ||
| 595 | #define MX35_PAD_SD1_CLK__GPIO1_7 0x234 0x698 0x85c 0x5 0x2 | ||
| 596 | #define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK 0x234 0x698 0x000 0x7 0x0 | ||
| 597 | #define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x238 0x69c 0x000 0x0 0x0 | ||
| 598 | #define MX35_PAD_SD1_DATA0__MSHC_DATA_0 0x238 0x69c 0x000 0x1 0x0 | ||
| 599 | #define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 0x238 0x69c 0x000 0x3 0x0 | ||
| 600 | #define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 0x238 0x69c 0x9bc 0x4 0x0 | ||
| 601 | #define MX35_PAD_SD1_DATA0__GPIO1_8 0x238 0x69c 0x860 0x5 0x2 | ||
| 602 | #define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 0x238 0x69c 0x000 0x7 0x0 | ||
| 603 | #define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x23c 0x6a0 0x000 0x0 0x0 | ||
| 604 | #define MX35_PAD_SD1_DATA1__MSHC_DATA_1 0x23c 0x6a0 0x000 0x1 0x0 | ||
| 605 | #define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS 0x23c 0x6a0 0x000 0x3 0x0 | ||
| 606 | #define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 0x23c 0x6a0 0x9a4 0x4 0x0 | ||
| 607 | #define MX35_PAD_SD1_DATA1__GPIO1_9 0x23c 0x6a0 0x864 0x5 0x1 | ||
| 608 | #define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 0x23c 0x6a0 0x000 0x7 0x0 | ||
| 609 | #define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x240 0x6a4 0x000 0x0 0x0 | ||
| 610 | #define MX35_PAD_SD1_DATA2__MSHC_DATA_2 0x240 0x6a4 0x000 0x1 0x0 | ||
| 611 | #define MX35_PAD_SD1_DATA2__IPU_DISPB_WR 0x240 0x6a4 0x000 0x3 0x0 | ||
| 612 | #define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 0x240 0x6a4 0x9a8 0x4 0x0 | ||
| 613 | #define MX35_PAD_SD1_DATA2__GPIO1_10 0x240 0x6a4 0x830 0x5 0x1 | ||
| 614 | #define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 0x240 0x6a4 0x000 0x7 0x0 | ||
| 615 | #define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x244 0x6a8 0x000 0x0 0x0 | ||
| 616 | #define MX35_PAD_SD1_DATA3__MSHC_DATA_3 0x244 0x6a8 0x000 0x1 0x0 | ||
| 617 | #define MX35_PAD_SD1_DATA3__IPU_DISPB_RD 0x244 0x6a8 0x000 0x3 0x0 | ||
| 618 | #define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 0x244 0x6a8 0x9ac 0x4 0x0 | ||
| 619 | #define MX35_PAD_SD1_DATA3__GPIO1_11 0x244 0x6a8 0x834 0x5 0x1 | ||
| 620 | #define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 0x244 0x6a8 0x000 0x7 0x0 | ||
| 621 | #define MX35_PAD_SD2_CMD__ESDHC2_CMD 0x248 0x6ac 0x000 0x0 0x0 | ||
| 622 | #define MX35_PAD_SD2_CMD__I2C3_SCL 0x248 0x6ac 0x91c 0x1 0x2 | ||
| 623 | #define MX35_PAD_SD2_CMD__ESDHC1_DAT4 0x248 0x6ac 0x804 0x2 0x0 | ||
| 624 | #define MX35_PAD_SD2_CMD__IPU_CSI_D_2 0x248 0x6ac 0x938 0x3 0x2 | ||
| 625 | #define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 0x248 0x6ac 0x9dc 0x4 0x0 | ||
| 626 | #define MX35_PAD_SD2_CMD__GPIO2_0 0x248 0x6ac 0x868 0x5 0x2 | ||
| 627 | #define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 0x248 0x6ac 0x000 0x6 0x0 | ||
| 628 | #define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC 0x248 0x6ac 0x928 0x7 0x3 | ||
| 629 | #define MX35_PAD_SD2_CLK__ESDHC2_CLK 0x24c 0x6b0 0x000 0x0 0x0 | ||
| 630 | #define MX35_PAD_SD2_CLK__I2C3_SDA 0x24c 0x6b0 0x920 0x1 0x2 | ||
| 631 | #define MX35_PAD_SD2_CLK__ESDHC1_DAT5 0x24c 0x6b0 0x808 0x2 0x0 | ||
| 632 | #define MX35_PAD_SD2_CLK__IPU_CSI_D_3 0x24c 0x6b0 0x93c 0x3 0x2 | ||
| 633 | #define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 0x24c 0x6b0 0x9e0 0x4 0x0 | ||
| 634 | #define MX35_PAD_SD2_CLK__GPIO2_1 0x24c 0x6b0 0x894 0x5 0x1 | ||
| 635 | #define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 0x24c 0x6b0 0x998 0x6 0x2 | ||
| 636 | #define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 0x24c 0x6b0 0x000 0x7 0x0 | ||
| 637 | #define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 0x250 0x6b4 0x000 0x0 0x0 | ||
| 638 | #define MX35_PAD_SD2_DATA0__UART3_RXD_MUX 0x250 0x6b4 0x9a0 0x1 0x1 | ||
| 639 | #define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 0x250 0x6b4 0x80c 0x2 0x0 | ||
| 640 | #define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 0x250 0x6b4 0x940 0x3 0x1 | ||
| 641 | #define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 0x250 0x6b4 0x9e4 0x4 0x0 | ||
| 642 | #define MX35_PAD_SD2_DATA0__GPIO2_2 0x250 0x6b4 0x8c0 0x5 0x1 | ||
| 643 | #define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK 0x250 0x6b4 0x994 0x6 0x3 | ||
| 644 | #define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 0x254 0x6b8 0x000 0x0 0x0 | ||
| 645 | #define MX35_PAD_SD2_DATA1__UART3_TXD_MUX 0x254 0x6b8 0x000 0x1 0x0 | ||
| 646 | #define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 0x254 0x6b8 0x810 0x2 0x0 | ||
| 647 | #define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 0x254 0x6b8 0x944 0x3 0x1 | ||
| 648 | #define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 0x254 0x6b8 0x9cc 0x4 0x0 | ||
| 649 | #define MX35_PAD_SD2_DATA1__GPIO2_3 0x254 0x6b8 0x8cc 0x5 0x1 | ||
| 650 | #define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 0x258 0x6bc 0x000 0x0 0x0 | ||
| 651 | #define MX35_PAD_SD2_DATA2__UART3_RTS 0x258 0x6bc 0x99c 0x1 0x0 | ||
| 652 | #define MX35_PAD_SD2_DATA2__CAN1_RXCAN 0x258 0x6bc 0x7c8 0x2 0x1 | ||
| 653 | #define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 0x258 0x6bc 0x948 0x3 0x1 | ||
| 654 | #define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 0x258 0x6bc 0x9d0 0x4 0x0 | ||
| 655 | #define MX35_PAD_SD2_DATA2__GPIO2_4 0x258 0x6bc 0x8d0 0x5 0x1 | ||
| 656 | #define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 0x25c 0x6c0 0x000 0x0 0x0 | ||
| 657 | #define MX35_PAD_SD2_DATA3__UART3_CTS 0x25c 0x6c0 0x000 0x1 0x0 | ||
| 658 | #define MX35_PAD_SD2_DATA3__CAN1_TXCAN 0x25c 0x6c0 0x000 0x2 0x0 | ||
| 659 | #define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 0x25c 0x6c0 0x94c 0x3 0x1 | ||
| 660 | #define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 0x25c 0x6c0 0x9d4 0x4 0x0 | ||
| 661 | #define MX35_PAD_SD2_DATA3__GPIO2_5 0x25c 0x6c0 0x8d4 0x5 0x1 | ||
| 662 | #define MX35_PAD_ATA_CS0__ATA_CS0 0x260 0x6c4 0x000 0x0 0x0 | ||
| 663 | #define MX35_PAD_ATA_CS0__CSPI1_SS3 0x260 0x6c4 0x7dc 0x1 0x1 | ||
| 664 | #define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 0x260 0x6c4 0x000 0x3 0x0 | ||
| 665 | #define MX35_PAD_ATA_CS0__GPIO2_6 0x260 0x6c4 0x8d8 0x5 0x1 | ||
| 666 | #define MX35_PAD_ATA_CS0__IPU_DIAGB_0 0x260 0x6c4 0x000 0x6 0x0 | ||
| 667 | #define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 0x260 0x6c4 0x000 0x7 0x0 | ||
| 668 | #define MX35_PAD_ATA_CS1__ATA_CS1 0x264 0x6c8 0x000 0x0 0x0 | ||
| 669 | #define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 0x264 0x6c8 0x000 0x3 0x0 | ||
| 670 | #define MX35_PAD_ATA_CS1__CSPI2_SS0 0x264 0x6c8 0x7f0 0x4 0x1 | ||
| 671 | #define MX35_PAD_ATA_CS1__GPIO2_7 0x264 0x6c8 0x8dc 0x5 0x1 | ||
| 672 | #define MX35_PAD_ATA_CS1__IPU_DIAGB_1 0x264 0x6c8 0x000 0x6 0x0 | ||
| 673 | #define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 0x264 0x6c8 0x000 0x7 0x0 | ||
| 674 | #define MX35_PAD_ATA_DIOR__ATA_DIOR 0x268 0x6cc 0x000 0x0 0x0 | ||
| 675 | #define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 0x268 0x6cc 0x81c 0x1 0x1 | ||
| 676 | #define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR 0x268 0x6cc 0x9c4 0x2 0x1 | ||
| 677 | #define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 0x268 0x6cc 0x000 0x3 0x0 | ||
| 678 | #define MX35_PAD_ATA_DIOR__CSPI2_SS1 0x268 0x6cc 0x7f4 0x4 0x1 | ||
| 679 | #define MX35_PAD_ATA_DIOR__GPIO2_8 0x268 0x6cc 0x8e0 0x5 0x1 | ||
| 680 | #define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 0x268 0x6cc 0x000 0x6 0x0 | ||
| 681 | #define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 0x268 0x6cc 0x000 0x7 0x0 | ||
| 682 | #define MX35_PAD_ATA_DIOW__ATA_DIOW 0x26c 0x6d0 0x000 0x0 0x0 | ||
| 683 | #define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 0x26c 0x6d0 0x820 0x1 0x1 | ||
| 684 | #define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP 0x26c 0x6d0 0x000 0x2 0x0 | ||
| 685 | #define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 0x26c 0x6d0 0x000 0x3 0x0 | ||
| 686 | #define MX35_PAD_ATA_DIOW__CSPI2_MOSI 0x26c 0x6d0 0x7ec 0x4 0x2 | ||
| 687 | #define MX35_PAD_ATA_DIOW__GPIO2_9 0x26c 0x6d0 0x8e4 0x5 0x1 | ||
| 688 | #define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 0x26c 0x6d0 0x000 0x6 0x0 | ||
| 689 | #define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 0x26c 0x6d0 0x000 0x7 0x0 | ||
| 690 | #define MX35_PAD_ATA_DMACK__ATA_DMACK 0x270 0x6d4 0x000 0x0 0x0 | ||
| 691 | #define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 0x270 0x6d4 0x824 0x1 0x1 | ||
| 692 | #define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT 0x270 0x6d4 0x9c8 0x2 0x1 | ||
| 693 | #define MX35_PAD_ATA_DMACK__CSPI2_MISO 0x270 0x6d4 0x7e8 0x4 0x2 | ||
| 694 | #define MX35_PAD_ATA_DMACK__GPIO2_10 0x270 0x6d4 0x86c 0x5 0x1 | ||
| 695 | #define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 0x270 0x6d4 0x000 0x6 0x0 | ||
| 696 | #define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 0x270 0x6d4 0x000 0x7 0x0 | ||
| 697 | #define MX35_PAD_ATA_RESET_B__ATA_RESET_B 0x274 0x6d8 0x000 0x0 0x0 | ||
| 698 | #define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 0x274 0x6d8 0x828 0x1 0x1 | ||
| 699 | #define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 0x274 0x6d8 0x9a4 0x2 0x1 | ||
| 700 | #define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O 0x274 0x6d8 0x000 0x3 0x0 | ||
| 701 | #define MX35_PAD_ATA_RESET_B__CSPI2_RDY 0x274 0x6d8 0x7e4 0x4 0x2 | ||
| 702 | #define MX35_PAD_ATA_RESET_B__GPIO2_11 0x274 0x6d8 0x870 0x5 0x1 | ||
| 703 | #define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 0x274 0x6d8 0x000 0x6 0x0 | ||
| 704 | #define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 0x274 0x6d8 0x000 0x7 0x0 | ||
| 705 | #define MX35_PAD_ATA_IORDY__ATA_IORDY 0x278 0x6dc 0x000 0x0 0x0 | ||
| 706 | #define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 0x278 0x6dc 0x000 0x1 0x0 | ||
| 707 | #define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 0x278 0x6dc 0x9a8 0x2 0x1 | ||
| 708 | #define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO 0x278 0x6dc 0x92c 0x3 0x3 | ||
| 709 | #define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 0x278 0x6dc 0x000 0x4 0x0 | ||
| 710 | #define MX35_PAD_ATA_IORDY__GPIO2_12 0x278 0x6dc 0x874 0x5 0x1 | ||
| 711 | #define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 0x278 0x6dc 0x000 0x6 0x0 | ||
| 712 | #define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 0x278 0x6dc 0x000 0x7 0x0 | ||
| 713 | #define MX35_PAD_ATA_DATA0__ATA_DATA_0 0x27c 0x6e0 0x000 0x0 0x0 | ||
| 714 | #define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 0x27c 0x6e0 0x000 0x1 0x0 | ||
| 715 | #define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 0x27c 0x6e0 0x9ac 0x2 0x1 | ||
| 716 | #define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC 0x27c 0x6e0 0x928 0x3 0x4 | ||
| 717 | #define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 0x27c 0x6e0 0x000 0x4 0x0 | ||
| 718 | #define MX35_PAD_ATA_DATA0__GPIO2_13 0x27c 0x6e0 0x878 0x5 0x1 | ||
| 719 | #define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 0x27c 0x6e0 0x000 0x6 0x0 | ||
| 720 | #define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 0x27c 0x6e0 0x000 0x7 0x0 | ||
| 721 | #define MX35_PAD_ATA_DATA1__ATA_DATA_1 0x280 0x6e4 0x000 0x0 0x0 | ||
| 722 | #define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 0x280 0x6e4 0x000 0x1 0x0 | ||
| 723 | #define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 0x280 0x6e4 0x9b0 0x2 0x1 | ||
| 724 | #define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK 0x280 0x6e4 0x000 0x3 0x0 | ||
| 725 | #define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 0x280 0x6e4 0x000 0x4 0x0 | ||
| 726 | #define MX35_PAD_ATA_DATA1__GPIO2_14 0x280 0x6e4 0x87c 0x5 0x1 | ||
| 727 | #define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 0x280 0x6e4 0x000 0x6 0x0 | ||
| 728 | #define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 0x280 0x6e4 0x000 0x7 0x0 | ||
| 729 | #define MX35_PAD_ATA_DATA2__ATA_DATA_2 0x284 0x6e8 0x000 0x0 0x0 | ||
| 730 | #define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 0x284 0x6e8 0x000 0x1 0x0 | ||
| 731 | #define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 0x284 0x6e8 0x9b4 0x2 0x1 | ||
| 732 | #define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS 0x284 0x6e8 0x000 0x3 0x0 | ||
| 733 | #define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 0x284 0x6e8 0x000 0x4 0x0 | ||
| 734 | #define MX35_PAD_ATA_DATA2__GPIO2_15 0x284 0x6e8 0x880 0x5 0x1 | ||
| 735 | #define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 0x284 0x6e8 0x000 0x6 0x0 | ||
| 736 | #define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 0x284 0x6e8 0x000 0x7 0x0 | ||
| 737 | #define MX35_PAD_ATA_DATA3__ATA_DATA_3 0x288 0x6ec 0x000 0x0 0x0 | ||
| 738 | #define MX35_PAD_ATA_DATA3__ESDHC3_CLK 0x288 0x6ec 0x814 0x1 0x1 | ||
| 739 | #define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 0x288 0x6ec 0x9b8 0x2 0x1 | ||
| 740 | #define MX35_PAD_ATA_DATA3__CSPI2_SCLK 0x288 0x6ec 0x7e0 0x4 0x2 | ||
| 741 | #define MX35_PAD_ATA_DATA3__GPIO2_16 0x288 0x6ec 0x884 0x5 0x1 | ||
| 742 | #define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 0x288 0x6ec 0x000 0x6 0x0 | ||
| 743 | #define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 0x288 0x6ec 0x000 0x7 0x0 | ||
| 744 | #define MX35_PAD_ATA_DATA4__ATA_DATA_4 0x28c 0x6f0 0x000 0x0 0x0 | ||
| 745 | #define MX35_PAD_ATA_DATA4__ESDHC3_CMD 0x28c 0x6f0 0x818 0x1 0x1 | ||
| 746 | #define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 0x28c 0x6f0 0x9bc 0x2 0x1 | ||
| 747 | #define MX35_PAD_ATA_DATA4__GPIO2_17 0x28c 0x6f0 0x888 0x5 0x1 | ||
| 748 | #define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 0x28c 0x6f0 0x000 0x6 0x0 | ||
| 749 | #define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 0x28c 0x6f0 0x000 0x7 0x0 | ||
| 750 | #define MX35_PAD_ATA_DATA5__ATA_DATA_5 0x290 0x6f4 0x000 0x0 0x0 | ||
| 751 | #define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 0x290 0x6f4 0x9c0 0x2 0x1 | ||
| 752 | #define MX35_PAD_ATA_DATA5__GPIO2_18 0x290 0x6f4 0x88c 0x5 0x1 | ||
| 753 | #define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 0x290 0x6f4 0x000 0x6 0x0 | ||
| 754 | #define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 0x290 0x6f4 0x000 0x7 0x0 | ||
| 755 | #define MX35_PAD_ATA_DATA6__ATA_DATA_6 0x294 0x6f8 0x000 0x0 0x0 | ||
| 756 | #define MX35_PAD_ATA_DATA6__CAN1_TXCAN 0x294 0x6f8 0x000 0x1 0x0 | ||
| 757 | #define MX35_PAD_ATA_DATA6__UART1_DTR 0x294 0x6f8 0x000 0x2 0x0 | ||
| 758 | #define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD 0x294 0x6f8 0x7b4 0x3 0x0 | ||
| 759 | #define MX35_PAD_ATA_DATA6__GPIO2_19 0x294 0x6f8 0x890 0x5 0x1 | ||
| 760 | #define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 0x294 0x6f8 0x000 0x6 0x0 | ||
| 761 | #define MX35_PAD_ATA_DATA7__ATA_DATA_7 0x298 0x6fc 0x000 0x0 0x0 | ||
| 762 | #define MX35_PAD_ATA_DATA7__CAN1_RXCAN 0x298 0x6fc 0x7c8 0x1 0x2 | ||
| 763 | #define MX35_PAD_ATA_DATA7__UART1_DSR 0x298 0x6fc 0x000 0x2 0x0 | ||
| 764 | #define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD 0x298 0x6fc 0x7b0 0x3 0x0 | ||
| 765 | #define MX35_PAD_ATA_DATA7__GPIO2_20 0x298 0x6fc 0x898 0x5 0x1 | ||
| 766 | #define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 0x298 0x6fc 0x000 0x6 0x0 | ||
| 767 | #define MX35_PAD_ATA_DATA8__ATA_DATA_8 0x29c 0x700 0x000 0x0 0x0 | ||
| 768 | #define MX35_PAD_ATA_DATA8__UART3_RTS 0x29c 0x700 0x99c 0x1 0x1 | ||
| 769 | #define MX35_PAD_ATA_DATA8__UART1_RI 0x29c 0x700 0x000 0x2 0x0 | ||
| 770 | #define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC 0x29c 0x700 0x7c0 0x3 0x0 | ||
| 771 | #define MX35_PAD_ATA_DATA8__GPIO2_21 0x29c 0x700 0x89c 0x5 0x1 | ||
| 772 | #define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 0x29c 0x700 0x000 0x6 0x0 | ||
| 773 | #define MX35_PAD_ATA_DATA9__ATA_DATA_9 0x2a0 0x704 0x000 0x0 0x0 | ||
| 774 | #define MX35_PAD_ATA_DATA9__UART3_CTS 0x2a0 0x704 0x000 0x1 0x0 | ||
| 775 | #define MX35_PAD_ATA_DATA9__UART1_DCD 0x2a0 0x704 0x000 0x2 0x0 | ||
| 776 | #define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS 0x2a0 0x704 0x7c4 0x3 0x0 | ||
| 777 | #define MX35_PAD_ATA_DATA9__GPIO2_22 0x2a0 0x704 0x8a0 0x5 0x1 | ||
| 778 | #define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 0x2a0 0x704 0x000 0x6 0x0 | ||
| 779 | #define MX35_PAD_ATA_DATA10__ATA_DATA_10 0x2a4 0x708 0x000 0x0 0x0 | ||
| 780 | #define MX35_PAD_ATA_DATA10__UART3_RXD_MUX 0x2a4 0x708 0x9a0 0x1 0x2 | ||
| 781 | #define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC 0x2a4 0x708 0x7b8 0x3 0x0 | ||
| 782 | #define MX35_PAD_ATA_DATA10__GPIO2_23 0x2a4 0x708 0x8a4 0x5 0x1 | ||
| 783 | #define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 0x2a4 0x708 0x000 0x6 0x0 | ||
| 784 | #define MX35_PAD_ATA_DATA11__ATA_DATA_11 0x2a8 0x70c 0x000 0x0 0x0 | ||
| 785 | #define MX35_PAD_ATA_DATA11__UART3_TXD_MUX 0x2a8 0x70c 0x000 0x1 0x0 | ||
| 786 | #define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS 0x2a8 0x70c 0x7bc 0x3 0x0 | ||
| 787 | #define MX35_PAD_ATA_DATA11__GPIO2_24 0x2a8 0x70c 0x8a8 0x5 0x1 | ||
| 788 | #define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 0x2a8 0x70c 0x000 0x6 0x0 | ||
| 789 | #define MX35_PAD_ATA_DATA12__ATA_DATA_12 0x2ac 0x710 0x000 0x0 0x0 | ||
| 790 | #define MX35_PAD_ATA_DATA12__I2C3_SCL 0x2ac 0x710 0x91c 0x1 0x3 | ||
| 791 | #define MX35_PAD_ATA_DATA12__GPIO2_25 0x2ac 0x710 0x8ac 0x5 0x1 | ||
| 792 | #define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 0x2ac 0x710 0x000 0x6 0x0 | ||
| 793 | #define MX35_PAD_ATA_DATA13__ATA_DATA_13 0x2b0 0x714 0x000 0x0 0x0 | ||
| 794 | #define MX35_PAD_ATA_DATA13__I2C3_SDA 0x2b0 0x714 0x920 0x1 0x3 | ||
| 795 | #define MX35_PAD_ATA_DATA13__GPIO2_26 0x2b0 0x714 0x8b0 0x5 0x1 | ||
| 796 | #define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 0x2b0 0x714 0x000 0x6 0x0 | ||
| 797 | #define MX35_PAD_ATA_DATA14__ATA_DATA_14 0x2b4 0x718 0x000 0x0 0x0 | ||
| 798 | #define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 0x2b4 0x718 0x930 0x1 0x2 | ||
| 799 | #define MX35_PAD_ATA_DATA14__KPP_ROW_0 0x2b4 0x718 0x970 0x3 0x2 | ||
| 800 | #define MX35_PAD_ATA_DATA14__GPIO2_27 0x2b4 0x718 0x8b4 0x5 0x1 | ||
| 801 | #define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 0x2b4 0x718 0x000 0x6 0x0 | ||
| 802 | #define MX35_PAD_ATA_DATA15__ATA_DATA_15 0x2b8 0x71c 0x000 0x0 0x0 | ||
| 803 | #define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 0x2b8 0x71c 0x934 0x1 0x2 | ||
| 804 | #define MX35_PAD_ATA_DATA15__KPP_ROW_1 0x2b8 0x71c 0x974 0x3 0x2 | ||
| 805 | #define MX35_PAD_ATA_DATA15__GPIO2_28 0x2b8 0x71c 0x8b8 0x5 0x1 | ||
| 806 | #define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 0x2b8 0x71c 0x000 0x6 0x0 | ||
| 807 | #define MX35_PAD_ATA_INTRQ__ATA_INTRQ 0x2bc 0x720 0x000 0x0 0x0 | ||
| 808 | #define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 0x2bc 0x720 0x938 0x1 0x3 | ||
| 809 | #define MX35_PAD_ATA_INTRQ__KPP_ROW_2 0x2bc 0x720 0x978 0x3 0x2 | ||
| 810 | #define MX35_PAD_ATA_INTRQ__GPIO2_29 0x2bc 0x720 0x8bc 0x5 0x1 | ||
| 811 | #define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 0x2bc 0x720 0x000 0x6 0x0 | ||
| 812 | #define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN 0x2c0 0x724 0x000 0x0 0x0 | ||
| 813 | #define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 0x2c0 0x724 0x93c 0x1 0x3 | ||
| 814 | #define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 0x2c0 0x724 0x97c 0x3 0x2 | ||
| 815 | #define MX35_PAD_ATA_BUFF_EN__GPIO2_30 0x2c0 0x724 0x8c4 0x5 0x1 | ||
| 816 | #define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 0x2c0 0x724 0x000 0x6 0x0 | ||
| 817 | #define MX35_PAD_ATA_DMARQ__ATA_DMARQ 0x2c4 0x728 0x000 0x0 0x0 | ||
| 818 | #define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 0x2c4 0x728 0x940 0x1 0x2 | ||
| 819 | #define MX35_PAD_ATA_DMARQ__KPP_COL_0 0x2c4 0x728 0x950 0x3 0x2 | ||
| 820 | #define MX35_PAD_ATA_DMARQ__GPIO2_31 0x2c4 0x728 0x8c8 0x5 0x1 | ||
| 821 | #define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 0x2c4 0x728 0x000 0x6 0x0 | ||
| 822 | #define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 0x2c4 0x728 0x000 0x7 0x0 | ||
| 823 | #define MX35_PAD_ATA_DA0__ATA_DA_0 0x2c8 0x72c 0x000 0x0 0x0 | ||
| 824 | #define MX35_PAD_ATA_DA0__IPU_CSI_D_5 0x2c8 0x72c 0x944 0x1 0x2 | ||
| 825 | #define MX35_PAD_ATA_DA0__KPP_COL_1 0x2c8 0x72c 0x954 0x3 0x2 | ||
| 826 | #define MX35_PAD_ATA_DA0__GPIO3_0 0x2c8 0x72c 0x8e8 0x5 0x1 | ||
| 827 | #define MX35_PAD_ATA_DA0__IPU_DIAGB_26 0x2c8 0x72c 0x000 0x6 0x0 | ||
| 828 | #define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 0x2c8 0x72c 0x000 0x7 0x0 | ||
| 829 | #define MX35_PAD_ATA_DA1__ATA_DA_1 0x2cc 0x730 0x000 0x0 0x0 | ||
| 830 | #define MX35_PAD_ATA_DA1__IPU_CSI_D_6 0x2cc 0x730 0x948 0x1 0x2 | ||
| 831 | #define MX35_PAD_ATA_DA1__KPP_COL_2 0x2cc 0x730 0x958 0x3 0x2 | ||
| 832 | #define MX35_PAD_ATA_DA1__GPIO3_1 0x2cc 0x730 0x000 0x5 0x0 | ||
| 833 | #define MX35_PAD_ATA_DA1__IPU_DIAGB_27 0x2cc 0x730 0x000 0x6 0x0 | ||
| 834 | #define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 0x2cc 0x730 0x000 0x7 0x0 | ||
| 835 | #define MX35_PAD_ATA_DA2__ATA_DA_2 0x2d0 0x734 0x000 0x0 0x0 | ||
| 836 | #define MX35_PAD_ATA_DA2__IPU_CSI_D_7 0x2d0 0x734 0x94c 0x1 0x2 | ||
| 837 | #define MX35_PAD_ATA_DA2__KPP_COL_3 0x2d0 0x734 0x95c 0x3 0x2 | ||
| 838 | #define MX35_PAD_ATA_DA2__GPIO3_2 0x2d0 0x734 0x000 0x5 0x0 | ||
| 839 | #define MX35_PAD_ATA_DA2__IPU_DIAGB_28 0x2d0 0x734 0x000 0x6 0x0 | ||
| 840 | #define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 0x2d0 0x734 0x000 0x7 0x0 | ||
| 841 | #define MX35_PAD_MLB_CLK__MLB_MLBCLK 0x2d4 0x738 0x000 0x0 0x0 | ||
| 842 | #define MX35_PAD_MLB_CLK__GPIO3_3 0x2d4 0x738 0x000 0x5 0x0 | ||
| 843 | #define MX35_PAD_MLB_DAT__MLB_MLBDAT 0x2d8 0x73c 0x000 0x0 0x0 | ||
| 844 | #define MX35_PAD_MLB_DAT__GPIO3_4 0x2d8 0x73c 0x904 0x5 0x1 | ||
| 845 | #define MX35_PAD_MLB_SIG__MLB_MLBSIG 0x2dc 0x740 0x000 0x0 0x0 | ||
| 846 | #define MX35_PAD_MLB_SIG__GPIO3_5 0x2dc 0x740 0x908 0x5 0x1 | ||
| 847 | #define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x2e0 0x744 0x000 0x0 0x0 | ||
| 848 | #define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 0x2e0 0x744 0x804 0x1 0x1 | ||
| 849 | #define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX 0x2e0 0x744 0x9a0 0x2 0x3 | ||
| 850 | #define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR 0x2e0 0x744 0x9ec 0x3 0x1 | ||
| 851 | #define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI 0x2e0 0x744 0x7ec 0x4 0x3 | ||
| 852 | #define MX35_PAD_FEC_TX_CLK__GPIO3_6 0x2e0 0x744 0x90c 0x5 0x1 | ||
| 853 | #define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC 0x2e0 0x744 0x928 0x6 0x5 | ||
| 854 | #define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 0x2e0 0x744 0x000 0x7 0x0 | ||
| 855 | #define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x2e4 0x748 0x000 0x0 0x0 | ||
| 856 | #define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 0x2e4 0x748 0x808 0x1 0x1 | ||
| 857 | #define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX 0x2e4 0x748 0x000 0x2 0x0 | ||
| 858 | #define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP 0x2e4 0x748 0x000 0x3 0x0 | ||
| 859 | #define MX35_PAD_FEC_RX_CLK__CSPI2_MISO 0x2e4 0x748 0x7e8 0x4 0x3 | ||
| 860 | #define MX35_PAD_FEC_RX_CLK__GPIO3_7 0x2e4 0x748 0x910 0x5 0x1 | ||
| 861 | #define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I 0x2e4 0x748 0x92c 0x6 0x4 | ||
| 862 | #define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 0x2e4 0x748 0x000 0x7 0x0 | ||
| 863 | #define MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x2e8 0x74c 0x000 0x0 0x0 | ||
| 864 | #define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 0x2e8 0x74c 0x80c 0x1 0x1 | ||
| 865 | #define MX35_PAD_FEC_RX_DV__UART3_RTS 0x2e8 0x74c 0x99c 0x2 0x2 | ||
| 866 | #define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT 0x2e8 0x74c 0x9f0 0x3 0x1 | ||
| 867 | #define MX35_PAD_FEC_RX_DV__CSPI2_SCLK 0x2e8 0x74c 0x7e0 0x4 0x3 | ||
| 868 | #define MX35_PAD_FEC_RX_DV__GPIO3_8 0x2e8 0x74c 0x914 0x5 0x1 | ||
| 869 | #define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK 0x2e8 0x74c 0x000 0x6 0x0 | ||
| 870 | #define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 0x2e8 0x74c 0x000 0x7 0x0 | ||
| 871 | #define MX35_PAD_FEC_COL__FEC_COL 0x2ec 0x750 0x000 0x0 0x0 | ||
| 872 | #define MX35_PAD_FEC_COL__ESDHC1_DAT7 0x2ec 0x750 0x810 0x1 0x1 | ||
| 873 | #define MX35_PAD_FEC_COL__UART3_CTS 0x2ec 0x750 0x000 0x2 0x0 | ||
| 874 | #define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 0x2ec 0x750 0x9cc 0x3 0x1 | ||
| 875 | #define MX35_PAD_FEC_COL__CSPI2_RDY 0x2ec 0x750 0x7e4 0x4 0x3 | ||
| 876 | #define MX35_PAD_FEC_COL__GPIO3_9 0x2ec 0x750 0x918 0x5 0x1 | ||
| 877 | #define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS 0x2ec 0x750 0x000 0x6 0x0 | ||
| 878 | #define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 0x2ec 0x750 0x000 0x7 0x0 | ||
| 879 | #define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x2f0 0x754 0x000 0x0 0x0 | ||
| 880 | #define MX35_PAD_FEC_RDATA0__PWM_PWMO 0x2f0 0x754 0x000 0x1 0x0 | ||
| 881 | #define MX35_PAD_FEC_RDATA0__UART3_DTR 0x2f0 0x754 0x000 0x2 0x0 | ||
| 882 | #define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 0x2f0 0x754 0x9d0 0x3 0x1 | ||
| 883 | #define MX35_PAD_FEC_RDATA0__CSPI2_SS0 0x2f0 0x754 0x7f0 0x4 0x2 | ||
| 884 | #define MX35_PAD_FEC_RDATA0__GPIO3_10 0x2f0 0x754 0x8ec 0x5 0x1 | ||
| 885 | #define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 0x2f0 0x754 0x000 0x6 0x0 | ||
| 886 | #define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 0x2f0 0x754 0x000 0x7 0x0 | ||
| 887 | #define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x2f4 0x758 0x000 0x0 0x0 | ||
| 888 | #define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 0x2f4 0x758 0x000 0x1 0x0 | ||
| 889 | #define MX35_PAD_FEC_TDATA0__UART3_DSR 0x2f4 0x758 0x000 0x2 0x0 | ||
| 890 | #define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 0x2f4 0x758 0x9d4 0x3 0x1 | ||
| 891 | #define MX35_PAD_FEC_TDATA0__CSPI2_SS1 0x2f4 0x758 0x7f4 0x4 0x2 | ||
| 892 | #define MX35_PAD_FEC_TDATA0__GPIO3_11 0x2f4 0x758 0x8f0 0x5 0x1 | ||
| 893 | #define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 0x2f4 0x758 0x000 0x6 0x0 | ||
| 894 | #define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 0x2f4 0x758 0x000 0x7 0x0 | ||
| 895 | #define MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x2f8 0x75c 0x000 0x0 0x0 | ||
| 896 | #define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 0x2f8 0x75c 0x998 0x1 0x3 | ||
| 897 | #define MX35_PAD_FEC_TX_EN__UART3_RI 0x2f8 0x75c 0x000 0x2 0x0 | ||
| 898 | #define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 0x2f8 0x75c 0x9d8 0x3 0x1 | ||
| 899 | #define MX35_PAD_FEC_TX_EN__GPIO3_12 0x2f8 0x75c 0x8f4 0x5 0x1 | ||
| 900 | #define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS 0x2f8 0x75c 0x000 0x6 0x0 | ||
| 901 | #define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 0x2f8 0x75c 0x000 0x7 0x0 | ||
| 902 | #define MX35_PAD_FEC_MDC__FEC_MDC 0x2fc 0x760 0x000 0x0 0x0 | ||
| 903 | #define MX35_PAD_FEC_MDC__CAN2_TXCAN 0x2fc 0x760 0x000 0x1 0x0 | ||
| 904 | #define MX35_PAD_FEC_MDC__UART3_DCD 0x2fc 0x760 0x000 0x2 0x0 | ||
| 905 | #define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 0x2fc 0x760 0x9dc 0x3 0x1 | ||
| 906 | #define MX35_PAD_FEC_MDC__GPIO3_13 0x2fc 0x760 0x8f8 0x5 0x1 | ||
| 907 | #define MX35_PAD_FEC_MDC__IPU_DISPB_WR 0x2fc 0x760 0x000 0x6 0x0 | ||
| 908 | #define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 0x2fc 0x760 0x000 0x7 0x0 | ||
| 909 | #define MX35_PAD_FEC_MDIO__FEC_MDIO 0x300 0x764 0x000 0x0 0x0 | ||
| 910 | #define MX35_PAD_FEC_MDIO__CAN2_RXCAN 0x300 0x764 0x7cc 0x1 0x2 | ||
| 911 | #define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 0x300 0x764 0x9e0 0x3 0x1 | ||
| 912 | #define MX35_PAD_FEC_MDIO__GPIO3_14 0x300 0x764 0x8fc 0x5 0x1 | ||
| 913 | #define MX35_PAD_FEC_MDIO__IPU_DISPB_RD 0x300 0x764 0x000 0x6 0x0 | ||
| 914 | #define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 0x300 0x764 0x000 0x7 0x0 | ||
| 915 | #define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x304 0x768 0x000 0x0 0x0 | ||
| 916 | #define MX35_PAD_FEC_TX_ERR__OWIRE_LINE 0x304 0x768 0x990 0x1 0x2 | ||
| 917 | #define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK 0x304 0x768 0x994 0x2 0x4 | ||
| 918 | #define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 0x304 0x768 0x9e4 0x3 0x1 | ||
| 919 | #define MX35_PAD_FEC_TX_ERR__GPIO3_15 0x304 0x768 0x900 0x5 0x1 | ||
| 920 | #define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC 0x304 0x768 0x924 0x6 0x3 | ||
| 921 | #define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 0x304 0x768 0x000 0x7 0x0 | ||
| 922 | #define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x308 0x76c 0x000 0x0 0x0 | ||
| 923 | #define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 0x308 0x76c 0x930 0x1 0x3 | ||
| 924 | #define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 0x308 0x76c 0x9e8 0x3 0x1 | ||
| 925 | #define MX35_PAD_FEC_RX_ERR__KPP_COL_4 0x308 0x76c 0x960 0x4 0x1 | ||
| 926 | #define MX35_PAD_FEC_RX_ERR__GPIO3_16 0x308 0x76c 0x000 0x5 0x0 | ||
| 927 | #define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO 0x308 0x76c 0x92c 0x6 0x5 | ||
| 928 | #define MX35_PAD_FEC_CRS__FEC_CRS 0x30c 0x770 0x000 0x0 0x0 | ||
| 929 | #define MX35_PAD_FEC_CRS__IPU_CSI_D_1 0x30c 0x770 0x934 0x1 0x3 | ||
| 930 | #define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR 0x30c 0x770 0x000 0x3 0x0 | ||
| 931 | #define MX35_PAD_FEC_CRS__KPP_COL_5 0x30c 0x770 0x964 0x4 0x1 | ||
| 932 | #define MX35_PAD_FEC_CRS__GPIO3_17 0x30c 0x770 0x000 0x5 0x0 | ||
| 933 | #define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE 0x30c 0x770 0x000 0x6 0x0 | ||
| 934 | #define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x310 0x774 0x000 0x0 0x0 | ||
| 935 | #define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 0x310 0x774 0x938 0x1 0x4 | ||
| 936 | #define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC 0x310 0x774 0x000 0x2 0x0 | ||
| 937 | #define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC 0x310 0x774 0x9f4 0x3 0x2 | ||
| 938 | #define MX35_PAD_FEC_RDATA1__KPP_COL_6 0x310 0x774 0x968 0x4 0x1 | ||
| 939 | #define MX35_PAD_FEC_RDATA1__GPIO3_18 0x310 0x774 0x000 0x5 0x0 | ||
| 940 | #define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 0x310 0x774 0x000 0x6 0x0 | ||
| 941 | #define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x314 0x778 0x000 0x0 0x0 | ||
| 942 | #define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 0x314 0x778 0x93c 0x1 0x4 | ||
| 943 | #define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS 0x314 0x778 0x7bc 0x2 0x1 | ||
| 944 | #define MX35_PAD_FEC_TDATA1__KPP_COL_7 0x314 0x778 0x96c 0x4 0x1 | ||
| 945 | #define MX35_PAD_FEC_TDATA1__GPIO3_19 0x314 0x778 0x000 0x5 0x0 | ||
| 946 | #define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 0x314 0x778 0x000 0x6 0x0 | ||
| 947 | #define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x318 0x77c 0x000 0x0 0x0 | ||
| 948 | #define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 0x318 0x77c 0x940 0x1 0x3 | ||
| 949 | #define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD 0x318 0x77c 0x7b4 0x2 0x1 | ||
| 950 | #define MX35_PAD_FEC_RDATA2__KPP_ROW_4 0x318 0x77c 0x980 0x4 0x1 | ||
| 951 | #define MX35_PAD_FEC_RDATA2__GPIO3_20 0x318 0x77c 0x000 0x5 0x0 | ||
| 952 | #define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x31c 0x780 0x000 0x0 0x0 | ||
| 953 | #define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 0x31c 0x780 0x944 0x1 0x3 | ||
| 954 | #define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD 0x31c 0x780 0x7b0 0x2 0x1 | ||
| 955 | #define MX35_PAD_FEC_TDATA2__KPP_ROW_5 0x31c 0x780 0x984 0x4 0x1 | ||
| 956 | #define MX35_PAD_FEC_TDATA2__GPIO3_21 0x31c 0x780 0x000 0x5 0x0 | ||
| 957 | #define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x320 0x784 0x000 0x0 0x0 | ||
| 958 | #define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 0x320 0x784 0x948 0x1 0x3 | ||
| 959 | #define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC 0x320 0x784 0x7c0 0x2 0x1 | ||
| 960 | #define MX35_PAD_FEC_RDATA3__KPP_ROW_6 0x320 0x784 0x988 0x4 0x1 | ||
| 961 | #define MX35_PAD_FEC_RDATA3__GPIO3_22 0x320 0x784 0x000 0x6 0x0 | ||
| 962 | #define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x324 0x788 0x000 0x0 0x0 | ||
| 963 | #define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 0x324 0x788 0x94c 0x1 0x3 | ||
| 964 | #define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS 0x324 0x788 0x7c4 0x2 0x1 | ||
| 965 | #define MX35_PAD_FEC_TDATA3__KPP_ROW_7 0x324 0x788 0x98c 0x4 0x1 | ||
| 966 | #define MX35_PAD_FEC_TDATA3__GPIO3_23 0x324 0x788 0x000 0x5 0x0 | ||
| 967 | #define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK 0x000 0x78c 0x000 0x0 0x0 | ||
| 968 | #define MX35_PAD_TEST_MODE__TCU_TEST_MODE 0x000 0x790 0x000 0x0 0x0 | ||
| 969 | |||
| 970 | #endif /* __DTS_IMX35_PINFUNC_H */ | ||
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts index 92d3a66a69e2..2bcf6981d490 100644 --- a/arch/arm/boot/dts/imx51-apf51.dts +++ b/arch/arm/boot/dts/imx51-apf51.dts | |||
| @@ -15,7 +15,7 @@ | |||
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | /dts-v1/; | 17 | /dts-v1/; |
| 18 | /include/ "imx51.dtsi" | 18 | #include "imx51.dtsi" |
| 19 | 19 | ||
| 20 | / { | 20 | / { |
| 21 | model = "Armadeus Systems APF51 module"; | 21 | model = "Armadeus Systems APF51 module"; |
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts new file mode 100644 index 000000000000..123fe84e0e8c --- /dev/null +++ b/arch/arm/boot/dts/imx51-apf51dev.dts | |||
| @@ -0,0 +1,97 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Armadeus Systems - <support@armadeus.com> | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* APF51Dev is a docking board for the APF51 SOM */ | ||
| 13 | #include "imx51-apf51.dts" | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "Armadeus Systems APF51Dev docking/development board"; | ||
| 17 | compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51"; | ||
| 18 | |||
| 19 | gpio-keys { | ||
| 20 | compatible = "gpio-keys"; | ||
| 21 | |||
| 22 | user-key { | ||
| 23 | label = "user"; | ||
| 24 | gpios = <&gpio1 3 0>; | ||
| 25 | linux,code = <256>; /* BTN_0 */ | ||
| 26 | }; | ||
| 27 | }; | ||
| 28 | |||
| 29 | leds { | ||
| 30 | compatible = "gpio-leds"; | ||
| 31 | |||
| 32 | user { | ||
| 33 | label = "Heartbeat"; | ||
| 34 | gpios = <&gpio1 2 0>; | ||
| 35 | linux,default-trigger = "heartbeat"; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | |||
| 40 | &ecspi1 { | ||
| 41 | pinctrl-names = "default"; | ||
| 42 | pinctrl-0 = <&pinctrl_ecspi1_1>; | ||
| 43 | fsl,spi-num-chipselects = <2>; | ||
| 44 | cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; | ||
| 45 | status = "okay"; | ||
| 46 | }; | ||
| 47 | |||
| 48 | &ecspi2 { | ||
| 49 | pinctrl-names = "default"; | ||
| 50 | pinctrl-0 = <&pinctrl_ecspi2_1>; | ||
| 51 | fsl,spi-num-chipselects = <2>; | ||
| 52 | cs-gpios = <&gpio3 28 1>, <&gpio3 27 1>; | ||
| 53 | status = "okay"; | ||
| 54 | }; | ||
| 55 | |||
| 56 | &esdhc1 { | ||
| 57 | pinctrl-names = "default"; | ||
| 58 | pinctrl-0 = <&pinctrl_esdhc1_1>; | ||
| 59 | cd-gpios = <&gpio2 29 0>; | ||
| 60 | bus-width = <4>; | ||
| 61 | status = "okay"; | ||
| 62 | }; | ||
| 63 | |||
| 64 | &esdhc2 { | ||
| 65 | pinctrl-names = "default"; | ||
| 66 | pinctrl-0 = <&pinctrl_esdhc2_1>; | ||
| 67 | bus-width = <4>; | ||
| 68 | non-removable; | ||
| 69 | status = "okay"; | ||
| 70 | }; | ||
| 71 | |||
| 72 | &i2c2 { | ||
| 73 | pinctrl-names = "default"; | ||
| 74 | pinctrl-0 = <&pinctrl_i2c2_2>; | ||
| 75 | status = "okay"; | ||
| 76 | }; | ||
| 77 | |||
| 78 | &iomuxc { | ||
| 79 | pinctrl-names = "default"; | ||
| 80 | pinctrl-0 = <&pinctrl_hog>; | ||
| 81 | |||
| 82 | hog { | ||
| 83 | pinctrl_hog: hoggrp { | ||
| 84 | fsl,pins = < | ||
| 85 | MX51_PAD_EIM_EB2__GPIO2_22 0x0C5 | ||
| 86 | MX51_PAD_EIM_EB3__GPIO2_23 0x0C5 | ||
| 87 | MX51_PAD_EIM_CS4__GPIO2_29 0x100 | ||
| 88 | MX51_PAD_NANDF_D13__GPIO3_27 0x0C5 | ||
| 89 | MX51_PAD_NANDF_D12__GPIO3_28 0x0C5 | ||
| 90 | MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5 | ||
| 91 | MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5 | ||
| 92 | MX51_PAD_GPIO1_2__GPIO1_2 0x0C5 | ||
| 93 | MX51_PAD_GPIO1_3__GPIO1_3 0x0C5 | ||
| 94 | >; | ||
| 95 | }; | ||
| 96 | }; | ||
| 97 | }; | ||
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index aab6e43219af..6dd9486c755b 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts | |||
| @@ -11,7 +11,7 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /dts-v1/; | 13 | /dts-v1/; |
| 14 | /include/ "imx51.dtsi" | 14 | #include "imx51.dtsi" |
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | model = "Freescale i.MX51 Babbage Board"; | 17 | model = "Freescale i.MX51 Babbage Board"; |
| @@ -222,13 +222,13 @@ | |||
| 222 | hog { | 222 | hog { |
| 223 | pinctrl_hog: hoggrp { | 223 | pinctrl_hog: hoggrp { |
| 224 | fsl,pins = < | 224 | fsl,pins = < |
| 225 | 694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */ | 225 | MX51_PAD_GPIO1_0__SD1_CD 0x20d5 |
| 226 | 697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */ | 226 | MX51_PAD_GPIO1_1__SD1_WP 0x20d5 |
| 227 | 737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */ | 227 | MX51_PAD_GPIO1_5__GPIO1_5 0x100 |
| 228 | 740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */ | 228 | MX51_PAD_GPIO1_6__GPIO1_6 0x100 |
| 229 | 121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */ | 229 | MX51_PAD_EIM_A27__GPIO2_21 0x5 |
| 230 | 402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */ | 230 | MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 |
| 231 | 405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */ | 231 | MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 |
| 232 | >; | 232 | >; |
| 233 | }; | 233 | }; |
| 234 | }; | 234 | }; |
diff --git a/arch/arm/boot/dts/imx51-pinfunc.h b/arch/arm/boot/dts/imx51-pinfunc.h new file mode 100644 index 000000000000..9eb92abaeb6d --- /dev/null +++ b/arch/arm/boot/dts/imx51-pinfunc.h | |||
| @@ -0,0 +1,773 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __DTS_IMX51_PINFUNC_H | ||
| 11 | #define __DTS_IMX51_PINFUNC_H | ||
| 12 | |||
| 13 | /* | ||
| 14 | * The pin function ID is a tuple of | ||
| 15 | * <mux_reg conf_reg input_reg mux_mode input_val> | ||
| 16 | */ | ||
| 17 | #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0 | ||
| 18 | #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0 | ||
| 19 | #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0 | ||
| 20 | #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0 | ||
| 21 | #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0 | ||
| 22 | #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0 | ||
| 23 | #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0 | ||
| 24 | #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0 | ||
| 25 | #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0 | ||
| 26 | #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0 | ||
| 27 | #define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0 | ||
| 28 | #define MX51_PAD_EIM_D17__UART3_CTS 0x060 0x3f4 0x000 0x4 0x0 | ||
| 29 | #define MX51_PAD_EIM_D17__USBH2_DATA1 0x060 0x3f4 0x000 0x2 0x0 | ||
| 30 | #define MX51_PAD_EIM_D18__AUD5_TXC 0x064 0x3f8 0x8e4 0x7 0x0 | ||
| 31 | #define MX51_PAD_EIM_D18__EIM_D18 0x064 0x3f8 0x000 0x0 0x0 | ||
| 32 | #define MX51_PAD_EIM_D18__GPIO2_2 0x064 0x3f8 0x000 0x1 0x0 | ||
| 33 | #define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0 | ||
| 34 | #define MX51_PAD_EIM_D18__UART3_RTS 0x064 0x3f8 0x9f0 0x4 0x1 | ||
| 35 | #define MX51_PAD_EIM_D18__USBH2_DATA2 0x064 0x3f8 0x000 0x2 0x0 | ||
| 36 | #define MX51_PAD_EIM_D19__AUD4_RXC 0x068 0x3fc 0x000 0x5 0x0 | ||
| 37 | #define MX51_PAD_EIM_D19__AUD5_TXFS 0x068 0x3fc 0x8e8 0x7 0x0 | ||
| 38 | #define MX51_PAD_EIM_D19__EIM_D19 0x068 0x3fc 0x000 0x0 0x0 | ||
| 39 | #define MX51_PAD_EIM_D19__GPIO2_3 0x068 0x3fc 0x000 0x1 0x0 | ||
| 40 | #define MX51_PAD_EIM_D19__I2C1_SCL 0x068 0x3fc 0x9b0 0x4 0x0 | ||
| 41 | #define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1 | ||
| 42 | #define MX51_PAD_EIM_D19__USBH2_DATA3 0x068 0x3fc 0x000 0x2 0x0 | ||
| 43 | #define MX51_PAD_EIM_D20__AUD4_TXD 0x06c 0x400 0x8c8 0x5 0x0 | ||
| 44 | #define MX51_PAD_EIM_D20__EIM_D20 0x06c 0x400 0x000 0x0 0x0 | ||
| 45 | #define MX51_PAD_EIM_D20__GPIO2_4 0x06c 0x400 0x000 0x1 0x0 | ||
| 46 | #define MX51_PAD_EIM_D20__SRTC_ALARM_DEB 0x06c 0x400 0x000 0x4 0x0 | ||
| 47 | #define MX51_PAD_EIM_D20__USBH2_DATA4 0x06c 0x400 0x000 0x2 0x0 | ||
| 48 | #define MX51_PAD_EIM_D21__AUD4_RXD 0x070 0x404 0x8c4 0x5 0x0 | ||
| 49 | #define MX51_PAD_EIM_D21__EIM_D21 0x070 0x404 0x000 0x0 0x0 | ||
| 50 | #define MX51_PAD_EIM_D21__GPIO2_5 0x070 0x404 0x000 0x1 0x0 | ||
| 51 | #define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0 | ||
| 52 | #define MX51_PAD_EIM_D21__USBH2_DATA5 0x070 0x404 0x000 0x2 0x0 | ||
| 53 | #define MX51_PAD_EIM_D22__AUD4_TXC 0x074 0x408 0x8cc 0x5 0x0 | ||
| 54 | #define MX51_PAD_EIM_D22__EIM_D22 0x074 0x408 0x000 0x0 0x0 | ||
| 55 | #define MX51_PAD_EIM_D22__GPIO2_6 0x074 0x408 0x000 0x1 0x0 | ||
| 56 | #define MX51_PAD_EIM_D22__USBH2_DATA6 0x074 0x408 0x000 0x2 0x0 | ||
| 57 | #define MX51_PAD_EIM_D23__AUD4_TXFS 0x078 0x40c 0x8d0 0x5 0x0 | ||
| 58 | #define MX51_PAD_EIM_D23__EIM_D23 0x078 0x40c 0x000 0x0 0x0 | ||
| 59 | #define MX51_PAD_EIM_D23__GPIO2_7 0x078 0x40c 0x000 0x1 0x0 | ||
| 60 | #define MX51_PAD_EIM_D23__SPDIF_OUT1 0x078 0x40c 0x000 0x4 0x0 | ||
| 61 | #define MX51_PAD_EIM_D23__USBH2_DATA7 0x078 0x40c 0x000 0x2 0x0 | ||
| 62 | #define MX51_PAD_EIM_D24__AUD6_RXFS 0x07c 0x410 0x8f8 0x5 0x0 | ||
| 63 | #define MX51_PAD_EIM_D24__EIM_D24 0x07c 0x410 0x000 0x0 0x0 | ||
| 64 | #define MX51_PAD_EIM_D24__GPIO2_8 0x07c 0x410 0x000 0x1 0x0 | ||
| 65 | #define MX51_PAD_EIM_D24__I2C2_SDA 0x07c 0x410 0x9bc 0x4 0x0 | ||
| 66 | #define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0 | ||
| 67 | #define MX51_PAD_EIM_D24__USBOTG_DATA0 0x07c 0x410 0x000 0x2 0x0 | ||
| 68 | #define MX51_PAD_EIM_D25__EIM_D25 0x080 0x414 0x000 0x0 0x0 | ||
| 69 | #define MX51_PAD_EIM_D25__KEY_COL6 0x080 0x414 0x9c8 0x1 0x0 | ||
| 70 | #define MX51_PAD_EIM_D25__UART2_CTS 0x080 0x414 0x000 0x4 0x0 | ||
| 71 | #define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0 | ||
| 72 | #define MX51_PAD_EIM_D25__USBOTG_DATA1 0x080 0x414 0x000 0x2 0x0 | ||
| 73 | #define MX51_PAD_EIM_D26__EIM_D26 0x084 0x418 0x000 0x0 0x0 | ||
| 74 | #define MX51_PAD_EIM_D26__KEY_COL7 0x084 0x418 0x9cc 0x1 0x0 | ||
| 75 | #define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3 | ||
| 76 | #define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0 | ||
| 77 | #define MX51_PAD_EIM_D26__USBOTG_DATA2 0x084 0x418 0x000 0x2 0x0 | ||
| 78 | #define MX51_PAD_EIM_D27__AUD6_RXC 0x088 0x41c 0x8f4 0x5 0x0 | ||
| 79 | #define MX51_PAD_EIM_D27__EIM_D27 0x088 0x41c 0x000 0x0 0x0 | ||
| 80 | #define MX51_PAD_EIM_D27__GPIO2_9 0x088 0x41c 0x000 0x1 0x0 | ||
| 81 | #define MX51_PAD_EIM_D27__I2C2_SCL 0x088 0x41c 0x9b8 0x4 0x0 | ||
| 82 | #define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3 0x3 | ||
| 83 | #define MX51_PAD_EIM_D27__USBOTG_DATA3 0x088 0x41c 0x000 0x2 0x0 | ||
| 84 | #define MX51_PAD_EIM_D28__AUD6_TXD 0x08c 0x420 0x8f0 0x5 0x0 | ||
| 85 | #define MX51_PAD_EIM_D28__EIM_D28 0x08c 0x420 0x000 0x0 0x0 | ||
| 86 | #define MX51_PAD_EIM_D28__KEY_ROW4 0x08c 0x420 0x9d0 0x1 0x0 | ||
| 87 | #define MX51_PAD_EIM_D28__USBOTG_DATA4 0x08c 0x420 0x000 0x2 0x0 | ||
| 88 | #define MX51_PAD_EIM_D29__AUD6_RXD 0x090 0x424 0x8ec 0x5 0x0 | ||
| 89 | #define MX51_PAD_EIM_D29__EIM_D29 0x090 0x424 0x000 0x0 0x0 | ||
| 90 | #define MX51_PAD_EIM_D29__KEY_ROW5 0x090 0x424 0x9d4 0x1 0x0 | ||
| 91 | #define MX51_PAD_EIM_D29__USBOTG_DATA5 0x090 0x424 0x000 0x2 0x0 | ||
| 92 | #define MX51_PAD_EIM_D30__AUD6_TXC 0x094 0x428 0x8fc 0x5 0x0 | ||
| 93 | #define MX51_PAD_EIM_D30__EIM_D30 0x094 0x428 0x000 0x0 0x0 | ||
| 94 | #define MX51_PAD_EIM_D30__KEY_ROW6 0x094 0x428 0x9d8 0x1 0x0 | ||
| 95 | #define MX51_PAD_EIM_D30__USBOTG_DATA6 0x094 0x428 0x000 0x2 0x0 | ||
| 96 | #define MX51_PAD_EIM_D31__AUD6_TXFS 0x098 0x42c 0x900 0x5 0x0 | ||
| 97 | #define MX51_PAD_EIM_D31__EIM_D31 0x098 0x42c 0x000 0x0 0x0 | ||
| 98 | #define MX51_PAD_EIM_D31__KEY_ROW7 0x098 0x42c 0x9dc 0x1 0x0 | ||
| 99 | #define MX51_PAD_EIM_D31__USBOTG_DATA7 0x098 0x42c 0x000 0x2 0x0 | ||
| 100 | #define MX51_PAD_EIM_A16__EIM_A16 0x09c 0x430 0x000 0x0 0x0 | ||
| 101 | #define MX51_PAD_EIM_A16__GPIO2_10 0x09c 0x430 0x000 0x1 0x0 | ||
| 102 | #define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 0x09c 0x430 0x000 0x7 0x0 | ||
| 103 | #define MX51_PAD_EIM_A17__EIM_A17 0x0a0 0x434 0x000 0x0 0x0 | ||
| 104 | #define MX51_PAD_EIM_A17__GPIO2_11 0x0a0 0x434 0x000 0x1 0x0 | ||
| 105 | #define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 0x0a0 0x434 0x000 0x7 0x0 | ||
| 106 | #define MX51_PAD_EIM_A18__BOOT_LPB0 0x0a4 0x438 0x000 0x7 0x0 | ||
| 107 | #define MX51_PAD_EIM_A18__EIM_A18 0x0a4 0x438 0x000 0x0 0x0 | ||
| 108 | #define MX51_PAD_EIM_A18__GPIO2_12 0x0a4 0x438 0x000 0x1 0x0 | ||
| 109 | #define MX51_PAD_EIM_A19__BOOT_LPB1 0x0a8 0x43c 0x000 0x7 0x0 | ||
| 110 | #define MX51_PAD_EIM_A19__EIM_A19 0x0a8 0x43c 0x000 0x0 0x0 | ||
| 111 | #define MX51_PAD_EIM_A19__GPIO2_13 0x0a8 0x43c 0x000 0x1 0x0 | ||
| 112 | #define MX51_PAD_EIM_A20__BOOT_UART_SRC0 0x0ac 0x440 0x000 0x7 0x0 | ||
| 113 | #define MX51_PAD_EIM_A20__EIM_A20 0x0ac 0x440 0x000 0x0 0x0 | ||
| 114 | #define MX51_PAD_EIM_A20__GPIO2_14 0x0ac 0x440 0x000 0x1 0x0 | ||
| 115 | #define MX51_PAD_EIM_A21__BOOT_UART_SRC1 0x0b0 0x444 0x000 0x7 0x0 | ||
| 116 | #define MX51_PAD_EIM_A21__EIM_A21 0x0b0 0x444 0x000 0x0 0x0 | ||
| 117 | #define MX51_PAD_EIM_A21__GPIO2_15 0x0b0 0x444 0x000 0x1 0x0 | ||
| 118 | #define MX51_PAD_EIM_A22__EIM_A22 0x0b4 0x448 0x000 0x0 0x0 | ||
| 119 | #define MX51_PAD_EIM_A22__GPIO2_16 0x0b4 0x448 0x000 0x1 0x0 | ||
| 120 | #define MX51_PAD_EIM_A23__BOOT_HPN_EN 0x0b8 0x44c 0x000 0x7 0x0 | ||
| 121 | #define MX51_PAD_EIM_A23__EIM_A23 0x0b8 0x44c 0x000 0x0 0x0 | ||
| 122 | #define MX51_PAD_EIM_A23__GPIO2_17 0x0b8 0x44c 0x000 0x1 0x0 | ||
| 123 | #define MX51_PAD_EIM_A24__EIM_A24 0x0bc 0x450 0x000 0x0 0x0 | ||
| 124 | #define MX51_PAD_EIM_A24__GPIO2_18 0x0bc 0x450 0x000 0x1 0x0 | ||
| 125 | #define MX51_PAD_EIM_A24__USBH2_CLK 0x0bc 0x450 0x000 0x2 0x0 | ||
| 126 | #define MX51_PAD_EIM_A25__DISP1_PIN4 0x0c0 0x454 0x000 0x6 0x0 | ||
| 127 | #define MX51_PAD_EIM_A25__EIM_A25 0x0c0 0x454 0x000 0x0 0x0 | ||
| 128 | #define MX51_PAD_EIM_A25__GPIO2_19 0x0c0 0x454 0x000 0x1 0x0 | ||
| 129 | #define MX51_PAD_EIM_A25__USBH2_DIR 0x0c0 0x454 0x000 0x2 0x0 | ||
| 130 | #define MX51_PAD_EIM_A26__CSI1_DATA_EN 0x0c4 0x458 0x9a0 0x5 0x0 | ||
| 131 | #define MX51_PAD_EIM_A26__DISP2_EXT_CLK 0x0c4 0x458 0x908 0x6 0x0 | ||
| 132 | #define MX51_PAD_EIM_A26__EIM_A26 0x0c4 0x458 0x000 0x0 0x0 | ||
| 133 | #define MX51_PAD_EIM_A26__GPIO2_20 0x0c4 0x458 0x000 0x1 0x0 | ||
| 134 | #define MX51_PAD_EIM_A26__USBH2_STP 0x0c4 0x458 0x000 0x2 0x0 | ||
| 135 | #define MX51_PAD_EIM_A27__CSI2_DATA_EN 0x0c8 0x45c 0x99c 0x5 0x0 | ||
| 136 | #define MX51_PAD_EIM_A27__DISP1_PIN1 0x0c8 0x45c 0x9a4 0x6 0x0 | ||
| 137 | #define MX51_PAD_EIM_A27__EIM_A27 0x0c8 0x45c 0x000 0x0 0x0 | ||
| 138 | #define MX51_PAD_EIM_A27__GPIO2_21 0x0c8 0x45c 0x000 0x1 0x0 | ||
| 139 | #define MX51_PAD_EIM_A27__USBH2_NXT 0x0c8 0x45c 0x000 0x2 0x0 | ||
| 140 | #define MX51_PAD_EIM_EB0__EIM_EB0 0x0cc 0x460 0x000 0x0 0x0 | ||
| 141 | #define MX51_PAD_EIM_EB1__EIM_EB1 0x0d0 0x464 0x000 0x0 0x0 | ||
| 142 | #define MX51_PAD_EIM_EB2__AUD5_RXFS 0x0d4 0x468 0x8e0 0x6 0x0 | ||
| 143 | #define MX51_PAD_EIM_EB2__CSI1_D2 0x0d4 0x468 0x000 0x5 0x0 | ||
| 144 | #define MX51_PAD_EIM_EB2__EIM_EB2 0x0d4 0x468 0x000 0x0 0x0 | ||
| 145 | #define MX51_PAD_EIM_EB2__FEC_MDIO 0x0d4 0x468 0x954 0x3 0x0 | ||
| 146 | #define MX51_PAD_EIM_EB2__GPIO2_22 0x0d4 0x468 0x000 0x1 0x0 | ||
| 147 | #define MX51_PAD_EIM_EB2__GPT_CMPOUT1 0x0d4 0x468 0x000 0x7 0x0 | ||
| 148 | #define MX51_PAD_EIM_EB3__AUD5_RXC 0x0d8 0x46c 0x8dc 0x6 0x0 | ||
| 149 | #define MX51_PAD_EIM_EB3__CSI1_D3 0x0d8 0x46c 0x000 0x5 0x0 | ||
| 150 | #define MX51_PAD_EIM_EB3__EIM_EB3 0x0d8 0x46c 0x000 0x0 0x0 | ||
| 151 | #define MX51_PAD_EIM_EB3__FEC_RDATA1 0x0d8 0x46c 0x95c 0x3 0x0 | ||
| 152 | #define MX51_PAD_EIM_EB3__GPIO2_23 0x0d8 0x46c 0x000 0x1 0x0 | ||
| 153 | #define MX51_PAD_EIM_EB3__GPT_CMPOUT2 0x0d8 0x46c 0x000 0x7 0x0 | ||
| 154 | #define MX51_PAD_EIM_OE__EIM_OE 0x0dc 0x470 0x000 0x0 0x0 | ||
| 155 | #define MX51_PAD_EIM_OE__GPIO2_24 0x0dc 0x470 0x000 0x1 0x0 | ||
| 156 | #define MX51_PAD_EIM_CS0__EIM_CS0 0x0e0 0x474 0x000 0x0 0x0 | ||
| 157 | #define MX51_PAD_EIM_CS0__GPIO2_25 0x0e0 0x474 0x000 0x1 0x0 | ||
| 158 | #define MX51_PAD_EIM_CS1__EIM_CS1 0x0e4 0x478 0x000 0x0 0x0 | ||
| 159 | #define MX51_PAD_EIM_CS1__GPIO2_26 0x0e4 0x478 0x000 0x1 0x0 | ||
| 160 | #define MX51_PAD_EIM_CS2__AUD5_TXD 0x0e8 0x47c 0x8d8 0x6 0x1 | ||
| 161 | #define MX51_PAD_EIM_CS2__CSI1_D4 0x0e8 0x47c 0x000 0x5 0x0 | ||
| 162 | #define MX51_PAD_EIM_CS2__EIM_CS2 0x0e8 0x47c 0x000 0x0 0x0 | ||
| 163 | #define MX51_PAD_EIM_CS2__FEC_RDATA2 0x0e8 0x47c 0x960 0x3 0x0 | ||
| 164 | #define MX51_PAD_EIM_CS2__GPIO2_27 0x0e8 0x47c 0x000 0x1 0x0 | ||
| 165 | #define MX51_PAD_EIM_CS2__USBOTG_STP 0x0e8 0x47c 0x000 0x2 0x0 | ||
| 166 | #define MX51_PAD_EIM_CS3__AUD5_RXD 0x0ec 0x480 0x8d4 0x6 0x1 | ||
| 167 | #define MX51_PAD_EIM_CS3__CSI1_D5 0x0ec 0x480 0x000 0x5 0x0 | ||
| 168 | #define MX51_PAD_EIM_CS3__EIM_CS3 0x0ec 0x480 0x000 0x0 0x0 | ||
| 169 | #define MX51_PAD_EIM_CS3__FEC_RDATA3 0x0ec 0x480 0x964 0x3 0x0 | ||
| 170 | #define MX51_PAD_EIM_CS3__GPIO2_28 0x0ec 0x480 0x000 0x1 0x0 | ||
| 171 | #define MX51_PAD_EIM_CS3__USBOTG_NXT 0x0ec 0x480 0x000 0x2 0x0 | ||
| 172 | #define MX51_PAD_EIM_CS4__AUD5_TXC 0x0f0 0x484 0x8e4 0x6 0x1 | ||
| 173 | #define MX51_PAD_EIM_CS4__CSI1_D6 0x0f0 0x484 0x000 0x5 0x0 | ||
| 174 | #define MX51_PAD_EIM_CS4__EIM_CS4 0x0f0 0x484 0x000 0x0 0x0 | ||
| 175 | #define MX51_PAD_EIM_CS4__FEC_RX_ER 0x0f0 0x484 0x970 0x3 0x0 | ||
| 176 | #define MX51_PAD_EIM_CS4__GPIO2_29 0x0f0 0x484 0x000 0x1 0x0 | ||
| 177 | #define MX51_PAD_EIM_CS4__USBOTG_CLK 0x0f0 0x484 0x000 0x2 0x0 | ||
| 178 | #define MX51_PAD_EIM_CS5__AUD5_TXFS 0x0f4 0x488 0x8e8 0x6 0x1 | ||
| 179 | #define MX51_PAD_EIM_CS5__CSI1_D7 0x0f4 0x488 0x000 0x5 0x0 | ||
| 180 | #define MX51_PAD_EIM_CS5__DISP1_EXT_CLK 0x0f4 0x488 0x904 0x4 0x0 | ||
| 181 | #define MX51_PAD_EIM_CS5__EIM_CS5 0x0f4 0x488 0x000 0x0 0x0 | ||
| 182 | #define MX51_PAD_EIM_CS5__FEC_CRS 0x0f4 0x488 0x950 0x3 0x0 | ||
| 183 | #define MX51_PAD_EIM_CS5__GPIO2_30 0x0f4 0x488 0x000 0x1 0x0 | ||
| 184 | #define MX51_PAD_EIM_CS5__USBOTG_DIR 0x0f4 0x488 0x000 0x2 0x0 | ||
| 185 | #define MX51_PAD_EIM_DTACK__EIM_DTACK 0x0f8 0x48c 0x000 0x0 0x0 | ||
| 186 | #define MX51_PAD_EIM_DTACK__GPIO2_31 0x0f8 0x48c 0x000 0x1 0x0 | ||
| 187 | #define MX51_PAD_EIM_LBA__EIM_LBA 0x0fc 0x494 0x000 0x0 0x0 | ||
| 188 | #define MX51_PAD_EIM_LBA__GPIO3_1 0x0fc 0x494 0x978 0x1 0x0 | ||
| 189 | #define MX51_PAD_EIM_CRE__EIM_CRE 0x100 0x4a0 0x000 0x0 0x0 | ||
| 190 | #define MX51_PAD_EIM_CRE__GPIO3_2 0x100 0x4a0 0x97c 0x1 0x0 | ||
| 191 | #define MX51_PAD_DRAM_CS1__DRAM_CS1 0x104 0x4d0 0x000 0x0 0x0 | ||
| 192 | #define MX51_PAD_NANDF_WE_B__GPIO3_3 0x108 0x4e4 0x980 0x3 0x0 | ||
| 193 | #define MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x108 0x4e4 0x000 0x0 0x0 | ||
| 194 | #define MX51_PAD_NANDF_WE_B__PATA_DIOW 0x108 0x4e4 0x000 0x1 0x0 | ||
| 195 | #define MX51_PAD_NANDF_WE_B__SD3_DATA0 0x108 0x4e4 0x93c 0x2 0x0 | ||
| 196 | #define MX51_PAD_NANDF_RE_B__GPIO3_4 0x10c 0x4e8 0x984 0x3 0x0 | ||
| 197 | #define MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x10c 0x4e8 0x000 0x0 0x0 | ||
| 198 | #define MX51_PAD_NANDF_RE_B__PATA_DIOR 0x10c 0x4e8 0x000 0x1 0x0 | ||
| 199 | #define MX51_PAD_NANDF_RE_B__SD3_DATA1 0x10c 0x4e8 0x940 0x2 0x0 | ||
| 200 | #define MX51_PAD_NANDF_ALE__GPIO3_5 0x110 0x4ec 0x988 0x3 0x0 | ||
| 201 | #define MX51_PAD_NANDF_ALE__NANDF_ALE 0x110 0x4ec 0x000 0x0 0x0 | ||
| 202 | #define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x110 0x4ec 0x000 0x1 0x0 | ||
| 203 | #define MX51_PAD_NANDF_CLE__GPIO3_6 0x114 0x4f0 0x98c 0x3 0x0 | ||
| 204 | #define MX51_PAD_NANDF_CLE__NANDF_CLE 0x114 0x4f0 0x000 0x0 0x0 | ||
| 205 | #define MX51_PAD_NANDF_CLE__PATA_RESET_B 0x114 0x4f0 0x000 0x1 0x0 | ||
| 206 | #define MX51_PAD_NANDF_WP_B__GPIO3_7 0x118 0x4f4 0x990 0x3 0x0 | ||
| 207 | #define MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x118 0x4f4 0x000 0x0 0x0 | ||
| 208 | #define MX51_PAD_NANDF_WP_B__PATA_DMACK 0x118 0x4f4 0x000 0x1 0x0 | ||
| 209 | #define MX51_PAD_NANDF_WP_B__SD3_DATA2 0x118 0x4f4 0x944 0x2 0x0 | ||
| 210 | #define MX51_PAD_NANDF_RB0__ECSPI2_SS1 0x11c 0x4f8 0x930 0x5 0x0 | ||
| 211 | #define MX51_PAD_NANDF_RB0__GPIO3_8 0x11c 0x4f8 0x994 0x3 0x0 | ||
| 212 | #define MX51_PAD_NANDF_RB0__NANDF_RB0 0x11c 0x4f8 0x000 0x0 0x0 | ||
| 213 | #define MX51_PAD_NANDF_RB0__PATA_DMARQ 0x11c 0x4f8 0x000 0x1 0x0 | ||
| 214 | #define MX51_PAD_NANDF_RB0__SD3_DATA3 0x11c 0x4f8 0x948 0x2 0x0 | ||
| 215 | #define MX51_PAD_NANDF_RB1__CSPI_MOSI 0x120 0x4fc 0x91c 0x6 0x0 | ||
| 216 | #define MX51_PAD_NANDF_RB1__ECSPI2_RDY 0x120 0x4fc 0x000 0x2 0x0 | ||
| 217 | #define MX51_PAD_NANDF_RB1__GPIO3_9 0x120 0x4fc 0x000 0x3 0x0 | ||
| 218 | #define MX51_PAD_NANDF_RB1__NANDF_RB1 0x120 0x4fc 0x000 0x0 0x0 | ||
| 219 | #define MX51_PAD_NANDF_RB1__PATA_IORDY 0x120 0x4fc 0x000 0x1 0x0 | ||
| 220 | #define MX51_PAD_NANDF_RB1__SD4_CMD 0x120 0x4fc 0x000 0x5 0x0 | ||
| 221 | #define MX51_PAD_NANDF_RB2__DISP2_WAIT 0x124 0x500 0x9a8 0x5 0x0 | ||
| 222 | #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x124 0x500 0x000 0x2 0x0 | ||
| 223 | #define MX51_PAD_NANDF_RB2__FEC_COL 0x124 0x500 0x94c 0x1 0x0 | ||
| 224 | #define MX51_PAD_NANDF_RB2__GPIO3_10 0x124 0x500 0x000 0x3 0x0 | ||
| 225 | #define MX51_PAD_NANDF_RB2__NANDF_RB2 0x124 0x500 0x000 0x0 0x0 | ||
| 226 | #define MX51_PAD_NANDF_RB2__USBH3_H3_DP 0x124 0x500 0x000 0x7 0x0 | ||
| 227 | #define MX51_PAD_NANDF_RB2__USBH3_NXT 0x124 0x500 0xa20 0x6 0x0 | ||
| 228 | #define MX51_PAD_NANDF_RB3__DISP1_WAIT 0x128 0x504 0x000 0x5 0x0 | ||
| 229 | #define MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x128 0x504 0x000 0x2 0x0 | ||
| 230 | #define MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x128 0x504 0x968 0x1 0x0 | ||
| 231 | #define MX51_PAD_NANDF_RB3__GPIO3_11 0x128 0x504 0x000 0x3 0x0 | ||
| 232 | #define MX51_PAD_NANDF_RB3__NANDF_RB3 0x128 0x504 0x000 0x0 0x0 | ||
| 233 | #define MX51_PAD_NANDF_RB3__USBH3_CLK 0x128 0x504 0x9f8 0x6 0x0 | ||
| 234 | #define MX51_PAD_NANDF_RB3__USBH3_H3_DM 0x128 0x504 0x000 0x7 0x0 | ||
| 235 | #define MX51_PAD_GPIO_NAND__GPIO_NAND 0x12c 0x514 0x998 0x0 0x0 | ||
| 236 | #define MX51_PAD_GPIO_NAND__PATA_INTRQ 0x12c 0x514 0x000 0x1 0x0 | ||
| 237 | #define MX51_PAD_NANDF_CS0__GPIO3_16 0x130 0x518 0x000 0x3 0x0 | ||
| 238 | #define MX51_PAD_NANDF_CS0__NANDF_CS0 0x130 0x518 0x000 0x0 0x0 | ||
| 239 | #define MX51_PAD_NANDF_CS1__GPIO3_17 0x134 0x51c 0x000 0x3 0x0 | ||
| 240 | #define MX51_PAD_NANDF_CS1__NANDF_CS1 0x134 0x51c 0x000 0x0 0x0 | ||
| 241 | #define MX51_PAD_NANDF_CS2__CSPI_SCLK 0x138 0x520 0x914 0x6 0x0 | ||
| 242 | #define MX51_PAD_NANDF_CS2__FEC_TX_ER 0x138 0x520 0x000 0x2 0x0 | ||
| 243 | #define MX51_PAD_NANDF_CS2__GPIO3_18 0x138 0x520 0x000 0x3 0x0 | ||
| 244 | #define MX51_PAD_NANDF_CS2__NANDF_CS2 0x138 0x520 0x000 0x0 0x0 | ||
| 245 | #define MX51_PAD_NANDF_CS2__PATA_CS_0 0x138 0x520 0x000 0x1 0x0 | ||
| 246 | #define MX51_PAD_NANDF_CS2__SD4_CLK 0x138 0x520 0x000 0x5 0x0 | ||
| 247 | #define MX51_PAD_NANDF_CS2__USBH3_H1_DP 0x138 0x520 0x000 0x7 0x0 | ||
| 248 | #define MX51_PAD_NANDF_CS3__FEC_MDC 0x13c 0x524 0x000 0x2 0x0 | ||
| 249 | #define MX51_PAD_NANDF_CS3__GPIO3_19 0x13c 0x524 0x000 0x3 0x0 | ||
| 250 | #define MX51_PAD_NANDF_CS3__NANDF_CS3 0x13c 0x524 0x000 0x0 0x0 | ||
| 251 | #define MX51_PAD_NANDF_CS3__PATA_CS_1 0x13c 0x524 0x000 0x1 0x0 | ||
| 252 | #define MX51_PAD_NANDF_CS3__SD4_DAT0 0x13c 0x524 0x000 0x5 0x0 | ||
| 253 | #define MX51_PAD_NANDF_CS3__USBH3_H1_DM 0x13c 0x524 0x000 0x7 0x0 | ||
| 254 | #define MX51_PAD_NANDF_CS4__FEC_TDATA1 0x140 0x528 0x000 0x2 0x0 | ||
| 255 | #define MX51_PAD_NANDF_CS4__GPIO3_20 0x140 0x528 0x000 0x3 0x0 | ||
| 256 | #define MX51_PAD_NANDF_CS4__NANDF_CS4 0x140 0x528 0x000 0x0 0x0 | ||
| 257 | #define MX51_PAD_NANDF_CS4__PATA_DA_0 0x140 0x528 0x000 0x1 0x0 | ||
| 258 | #define MX51_PAD_NANDF_CS4__SD4_DAT1 0x140 0x528 0x000 0x5 0x0 | ||
| 259 | #define MX51_PAD_NANDF_CS4__USBH3_STP 0x140 0x528 0xa24 0x7 0x0 | ||
| 260 | #define MX51_PAD_NANDF_CS5__FEC_TDATA2 0x144 0x52c 0x000 0x2 0x0 | ||
| 261 | #define MX51_PAD_NANDF_CS5__GPIO3_21 0x144 0x52c 0x000 0x3 0x0 | ||
| 262 | #define MX51_PAD_NANDF_CS5__NANDF_CS5 0x144 0x52c 0x000 0x0 0x0 | ||
| 263 | #define MX51_PAD_NANDF_CS5__PATA_DA_1 0x144 0x52c 0x000 0x1 0x0 | ||
| 264 | #define MX51_PAD_NANDF_CS5__SD4_DAT2 0x144 0x52c 0x000 0x5 0x0 | ||
| 265 | #define MX51_PAD_NANDF_CS5__USBH3_DIR 0x144 0x52c 0xa1c 0x7 0x0 | ||
| 266 | #define MX51_PAD_NANDF_CS6__CSPI_SS3 0x148 0x530 0x928 0x7 0x0 | ||
| 267 | #define MX51_PAD_NANDF_CS6__FEC_TDATA3 0x148 0x530 0x000 0x2 0x0 | ||
| 268 | #define MX51_PAD_NANDF_CS6__GPIO3_22 0x148 0x530 0x000 0x3 0x0 | ||
| 269 | #define MX51_PAD_NANDF_CS6__NANDF_CS6 0x148 0x530 0x000 0x0 0x0 | ||
| 270 | #define MX51_PAD_NANDF_CS6__PATA_DA_2 0x148 0x530 0x000 0x1 0x0 | ||
| 271 | #define MX51_PAD_NANDF_CS6__SD4_DAT3 0x148 0x530 0x000 0x5 0x0 | ||
| 272 | #define MX51_PAD_NANDF_CS7__FEC_TX_EN 0x14c 0x534 0x000 0x1 0x0 | ||
| 273 | #define MX51_PAD_NANDF_CS7__GPIO3_23 0x14c 0x534 0x000 0x3 0x0 | ||
| 274 | #define MX51_PAD_NANDF_CS7__NANDF_CS7 0x14c 0x534 0x000 0x0 0x0 | ||
| 275 | #define MX51_PAD_NANDF_CS7__SD3_CLK 0x14c 0x534 0x000 0x5 0x0 | ||
| 276 | #define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 0x150 0x538 0x000 0x2 0x0 | ||
| 277 | #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x150 0x538 0x974 0x1 0x0 | ||
| 278 | #define MX51_PAD_NANDF_RDY_INT__GPIO3_24 0x150 0x538 0x000 0x3 0x0 | ||
| 279 | #define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 0x150 0x538 0x938 0x0 0x0 | ||
| 280 | #define MX51_PAD_NANDF_RDY_INT__SD3_CMD 0x150 0x538 0x000 0x5 0x0 | ||
| 281 | #define MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x154 0x53c 0x000 0x2 0x0 | ||
| 282 | #define MX51_PAD_NANDF_D15__GPIO3_25 0x154 0x53c 0x000 0x3 0x0 | ||
| 283 | #define MX51_PAD_NANDF_D15__NANDF_D15 0x154 0x53c 0x000 0x0 0x0 | ||
| 284 | #define MX51_PAD_NANDF_D15__PATA_DATA15 0x154 0x53c 0x000 0x1 0x0 | ||
| 285 | #define MX51_PAD_NANDF_D15__SD3_DAT7 0x154 0x53c 0x000 0x5 0x0 | ||
| 286 | #define MX51_PAD_NANDF_D14__ECSPI2_SS3 0x158 0x540 0x934 0x2 0x0 | ||
| 287 | #define MX51_PAD_NANDF_D14__GPIO3_26 0x158 0x540 0x000 0x3 0x0 | ||
| 288 | #define MX51_PAD_NANDF_D14__NANDF_D14 0x158 0x540 0x000 0x0 0x0 | ||
| 289 | #define MX51_PAD_NANDF_D14__PATA_DATA14 0x158 0x540 0x000 0x1 0x0 | ||
| 290 | #define MX51_PAD_NANDF_D14__SD3_DAT6 0x158 0x540 0x000 0x5 0x0 | ||
| 291 | #define MX51_PAD_NANDF_D13__ECSPI2_SS2 0x15c 0x544 0x000 0x2 0x0 | ||
| 292 | #define MX51_PAD_NANDF_D13__GPIO3_27 0x15c 0x544 0x000 0x3 0x0 | ||
| 293 | #define MX51_PAD_NANDF_D13__NANDF_D13 0x15c 0x544 0x000 0x0 0x0 | ||
| 294 | #define MX51_PAD_NANDF_D13__PATA_DATA13 0x15c 0x544 0x000 0x1 0x0 | ||
| 295 | #define MX51_PAD_NANDF_D13__SD3_DAT5 0x15c 0x544 0x000 0x5 0x0 | ||
| 296 | #define MX51_PAD_NANDF_D12__ECSPI2_SS1 0x160 0x548 0x930 0x2 0x1 | ||
| 297 | #define MX51_PAD_NANDF_D12__GPIO3_28 0x160 0x548 0x000 0x3 0x0 | ||
| 298 | #define MX51_PAD_NANDF_D12__NANDF_D12 0x160 0x548 0x000 0x0 0x0 | ||
| 299 | #define MX51_PAD_NANDF_D12__PATA_DATA12 0x160 0x548 0x000 0x1 0x0 | ||
| 300 | #define MX51_PAD_NANDF_D12__SD3_DAT4 0x160 0x548 0x000 0x5 0x0 | ||
| 301 | #define MX51_PAD_NANDF_D11__FEC_RX_DV 0x164 0x54c 0x96c 0x2 0x0 | ||
| 302 | #define MX51_PAD_NANDF_D11__GPIO3_29 0x164 0x54c 0x000 0x3 0x0 | ||
| 303 | #define MX51_PAD_NANDF_D11__NANDF_D11 0x164 0x54c 0x000 0x0 0x0 | ||
| 304 | #define MX51_PAD_NANDF_D11__PATA_DATA11 0x164 0x54c 0x000 0x1 0x0 | ||
| 305 | #define MX51_PAD_NANDF_D11__SD3_DATA3 0x164 0x54c 0x948 0x5 0x1 | ||
| 306 | #define MX51_PAD_NANDF_D10__GPIO3_30 0x168 0x550 0x000 0x3 0x0 | ||
| 307 | #define MX51_PAD_NANDF_D10__NANDF_D10 0x168 0x550 0x000 0x0 0x0 | ||
| 308 | #define MX51_PAD_NANDF_D10__PATA_DATA10 0x168 0x550 0x000 0x1 0x0 | ||
| 309 | #define MX51_PAD_NANDF_D10__SD3_DATA2 0x168 0x550 0x944 0x5 0x1 | ||
| 310 | #define MX51_PAD_NANDF_D9__FEC_RDATA0 0x16c 0x554 0x958 0x2 0x0 | ||
| 311 | #define MX51_PAD_NANDF_D9__GPIO3_31 0x16c 0x554 0x000 0x3 0x0 | ||
| 312 | #define MX51_PAD_NANDF_D9__NANDF_D9 0x16c 0x554 0x000 0x0 0x0 | ||
| 313 | #define MX51_PAD_NANDF_D9__PATA_DATA9 0x16c 0x554 0x000 0x1 0x0 | ||
| 314 | #define MX51_PAD_NANDF_D9__SD3_DATA1 0x16c 0x554 0x940 0x5 0x1 | ||
| 315 | #define MX51_PAD_NANDF_D8__FEC_TDATA0 0x170 0x558 0x000 0x2 0x0 | ||
| 316 | #define MX51_PAD_NANDF_D8__GPIO4_0 0x170 0x558 0x000 0x3 0x0 | ||
| 317 | #define MX51_PAD_NANDF_D8__NANDF_D8 0x170 0x558 0x000 0x0 0x0 | ||
| 318 | #define MX51_PAD_NANDF_D8__PATA_DATA8 0x170 0x558 0x000 0x1 0x0 | ||
| 319 | #define MX51_PAD_NANDF_D8__SD3_DATA0 0x170 0x558 0x93c 0x5 0x1 | ||
| 320 | #define MX51_PAD_NANDF_D7__GPIO4_1 0x174 0x55c 0x000 0x3 0x0 | ||
| 321 | #define MX51_PAD_NANDF_D7__NANDF_D7 0x174 0x55c 0x000 0x0 0x0 | ||
| 322 | #define MX51_PAD_NANDF_D7__PATA_DATA7 0x174 0x55c 0x000 0x1 0x0 | ||
| 323 | #define MX51_PAD_NANDF_D7__USBH3_DATA0 0x174 0x55c 0x9fc 0x5 0x0 | ||
| 324 | #define MX51_PAD_NANDF_D6__GPIO4_2 0x178 0x560 0x000 0x3 0x0 | ||
| 325 | #define MX51_PAD_NANDF_D6__NANDF_D6 0x178 0x560 0x000 0x0 0x0 | ||
| 326 | #define MX51_PAD_NANDF_D6__PATA_DATA6 0x178 0x560 0x000 0x1 0x0 | ||
| 327 | #define MX51_PAD_NANDF_D6__SD4_LCTL 0x178 0x560 0x000 0x2 0x0 | ||
| 328 | #define MX51_PAD_NANDF_D6__USBH3_DATA1 0x178 0x560 0xa00 0x5 0x0 | ||
| 329 | #define MX51_PAD_NANDF_D5__GPIO4_3 0x17c 0x564 0x000 0x3 0x0 | ||
| 330 | #define MX51_PAD_NANDF_D5__NANDF_D5 0x17c 0x564 0x000 0x0 0x0 | ||
| 331 | #define MX51_PAD_NANDF_D5__PATA_DATA5 0x17c 0x564 0x000 0x1 0x0 | ||
| 332 | #define MX51_PAD_NANDF_D5__SD4_WP 0x17c 0x564 0x000 0x2 0x0 | ||
| 333 | #define MX51_PAD_NANDF_D5__USBH3_DATA2 0x17c 0x564 0xa04 0x5 0x0 | ||
| 334 | #define MX51_PAD_NANDF_D4__GPIO4_4 0x180 0x568 0x000 0x3 0x0 | ||
| 335 | #define MX51_PAD_NANDF_D4__NANDF_D4 0x180 0x568 0x000 0x0 0x0 | ||
| 336 | #define MX51_PAD_NANDF_D4__PATA_DATA4 0x180 0x568 0x000 0x1 0x0 | ||
| 337 | #define MX51_PAD_NANDF_D4__SD4_CD 0x180 0x568 0x000 0x2 0x0 | ||
| 338 | #define MX51_PAD_NANDF_D4__USBH3_DATA3 0x180 0x568 0xa08 0x5 0x0 | ||
| 339 | #define MX51_PAD_NANDF_D3__GPIO4_5 0x184 0x56c 0x000 0x3 0x0 | ||
| 340 | #define MX51_PAD_NANDF_D3__NANDF_D3 0x184 0x56c 0x000 0x0 0x0 | ||
| 341 | #define MX51_PAD_NANDF_D3__PATA_DATA3 0x184 0x56c 0x000 0x1 0x0 | ||
| 342 | #define MX51_PAD_NANDF_D3__SD4_DAT4 0x184 0x56c 0x000 0x2 0x0 | ||
| 343 | #define MX51_PAD_NANDF_D3__USBH3_DATA4 0x184 0x56c 0xa0c 0x5 0x0 | ||
| 344 | #define MX51_PAD_NANDF_D2__GPIO4_6 0x188 0x570 0x000 0x3 0x0 | ||
| 345 | #define MX51_PAD_NANDF_D2__NANDF_D2 0x188 0x570 0x000 0x0 0x0 | ||
| 346 | #define MX51_PAD_NANDF_D2__PATA_DATA2 0x188 0x570 0x000 0x1 0x0 | ||
| 347 | #define MX51_PAD_NANDF_D2__SD4_DAT5 0x188 0x570 0x000 0x2 0x0 | ||
| 348 | #define MX51_PAD_NANDF_D2__USBH3_DATA5 0x188 0x570 0xa10 0x5 0x0 | ||
| 349 | #define MX51_PAD_NANDF_D1__GPIO4_7 0x18c 0x574 0x000 0x3 0x0 | ||
| 350 | #define MX51_PAD_NANDF_D1__NANDF_D1 0x18c 0x574 0x000 0x0 0x0 | ||
| 351 | #define MX51_PAD_NANDF_D1__PATA_DATA1 0x18c 0x574 0x000 0x1 0x0 | ||
| 352 | #define MX51_PAD_NANDF_D1__SD4_DAT6 0x18c 0x574 0x000 0x2 0x0 | ||
| 353 | #define MX51_PAD_NANDF_D1__USBH3_DATA6 0x18c 0x574 0xa14 0x5 0x0 | ||
| 354 | #define MX51_PAD_NANDF_D0__GPIO4_8 0x190 0x578 0x000 0x3 0x0 | ||
| 355 | #define MX51_PAD_NANDF_D0__NANDF_D0 0x190 0x578 0x000 0x0 0x0 | ||
| 356 | #define MX51_PAD_NANDF_D0__PATA_DATA0 0x190 0x578 0x000 0x1 0x0 | ||
| 357 | #define MX51_PAD_NANDF_D0__SD4_DAT7 0x190 0x578 0x000 0x2 0x0 | ||
| 358 | #define MX51_PAD_NANDF_D0__USBH3_DATA7 0x190 0x578 0xa18 0x5 0x0 | ||
| 359 | #define MX51_PAD_CSI1_D8__CSI1_D8 0x194 0x57c 0x000 0x0 0x0 | ||
| 360 | #define MX51_PAD_CSI1_D8__GPIO3_12 0x194 0x57c 0x998 0x3 0x1 | ||
| 361 | #define MX51_PAD_CSI1_D9__CSI1_D9 0x198 0x580 0x000 0x0 0x0 | ||
| 362 | #define MX51_PAD_CSI1_D9__GPIO3_13 0x198 0x580 0x000 0x3 0x0 | ||
| 363 | #define MX51_PAD_CSI1_D10__CSI1_D10 0x19c 0x584 0x000 0x0 0x0 | ||
| 364 | #define MX51_PAD_CSI1_D11__CSI1_D11 0x1a0 0x588 0x000 0x0 0x0 | ||
| 365 | #define MX51_PAD_CSI1_D12__CSI1_D12 0x1a4 0x58c 0x000 0x0 0x0 | ||
| 366 | #define MX51_PAD_CSI1_D13__CSI1_D13 0x1a8 0x590 0x000 0x0 0x0 | ||
| 367 | #define MX51_PAD_CSI1_D14__CSI1_D14 0x1ac 0x594 0x000 0x0 0x0 | ||
| 368 | #define MX51_PAD_CSI1_D15__CSI1_D15 0x1b0 0x598 0x000 0x0 0x0 | ||
| 369 | #define MX51_PAD_CSI1_D16__CSI1_D16 0x1b4 0x59c 0x000 0x0 0x0 | ||
| 370 | #define MX51_PAD_CSI1_D17__CSI1_D17 0x1b8 0x5a0 0x000 0x0 0x0 | ||
| 371 | #define MX51_PAD_CSI1_D18__CSI1_D18 0x1bc 0x5a4 0x000 0x0 0x0 | ||
| 372 | #define MX51_PAD_CSI1_D19__CSI1_D19 0x1c0 0x5a8 0x000 0x0 0x0 | ||
| 373 | #define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 0x1c4 0x5ac 0x000 0x0 0x0 | ||
| 374 | #define MX51_PAD_CSI1_VSYNC__GPIO3_14 0x1c4 0x5ac 0x000 0x3 0x0 | ||
| 375 | #define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 0x1c8 0x5b0 0x000 0x0 0x0 | ||
| 376 | #define MX51_PAD_CSI1_HSYNC__GPIO3_15 0x1c8 0x5b0 0x000 0x3 0x0 | ||
| 377 | #define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 0x000 0x5b4 0x000 0x0 0x0 | ||
| 378 | #define MX51_PAD_CSI1_MCLK__CSI1_MCLK 0x000 0x5b8 0x000 0x0 0x0 | ||
| 379 | #define MX51_PAD_CSI2_D12__CSI2_D12 0x1cc 0x5bc 0x000 0x0 0x0 | ||
| 380 | #define MX51_PAD_CSI2_D12__GPIO4_9 0x1cc 0x5bc 0x000 0x3 0x0 | ||
| 381 | #define MX51_PAD_CSI2_D13__CSI2_D13 0x1d0 0x5c0 0x000 0x0 0x0 | ||
| 382 | #define MX51_PAD_CSI2_D13__GPIO4_10 0x1d0 0x5c0 0x000 0x3 0x0 | ||
| 383 | #define MX51_PAD_CSI2_D14__CSI2_D14 0x1d4 0x5c4 0x000 0x0 0x0 | ||
| 384 | #define MX51_PAD_CSI2_D15__CSI2_D15 0x1d8 0x5c8 0x000 0x0 0x0 | ||
| 385 | #define MX51_PAD_CSI2_D16__CSI2_D16 0x1dc 0x5cc 0x000 0x0 0x0 | ||
| 386 | #define MX51_PAD_CSI2_D17__CSI2_D17 0x1e0 0x5d0 0x000 0x0 0x0 | ||
| 387 | #define MX51_PAD_CSI2_D18__CSI2_D18 0x1e4 0x5d4 0x000 0x0 0x0 | ||
| 388 | #define MX51_PAD_CSI2_D18__GPIO4_11 0x1e4 0x5d4 0x000 0x3 0x0 | ||
| 389 | #define MX51_PAD_CSI2_D19__CSI2_D19 0x1e8 0x5d8 0x000 0x0 0x0 | ||
| 390 | #define MX51_PAD_CSI2_D19__GPIO4_12 0x1e8 0x5d8 0x000 0x3 0x0 | ||
| 391 | #define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 0x1ec 0x5dc 0x000 0x0 0x0 | ||
| 392 | #define MX51_PAD_CSI2_VSYNC__GPIO4_13 0x1ec 0x5dc 0x000 0x3 0x0 | ||
| 393 | #define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 0x1f0 0x5e0 0x000 0x0 0x0 | ||
| 394 | #define MX51_PAD_CSI2_HSYNC__GPIO4_14 0x1f0 0x5e0 0x000 0x3 0x0 | ||
| 395 | #define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 0x1f4 0x5e4 0x000 0x0 0x0 | ||
| 396 | #define MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x1f4 0x5e4 0x000 0x3 0x0 | ||
| 397 | #define MX51_PAD_I2C1_CLK__GPIO4_16 0x1f8 0x5e8 0x000 0x3 0x0 | ||
| 398 | #define MX51_PAD_I2C1_CLK__I2C1_CLK 0x1f8 0x5e8 0x000 0x0 0x0 | ||
| 399 | #define MX51_PAD_I2C1_DAT__GPIO4_17 0x1fc 0x5ec 0x000 0x3 0x0 | ||
| 400 | #define MX51_PAD_I2C1_DAT__I2C1_DAT 0x1fc 0x5ec 0x000 0x0 0x0 | ||
| 401 | #define MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x200 0x5f0 0x000 0x0 0x0 | ||
| 402 | #define MX51_PAD_AUD3_BB_TXD__GPIO4_18 0x200 0x5f0 0x000 0x3 0x0 | ||
| 403 | #define MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x204 0x5f4 0x000 0x0 0x0 | ||
| 404 | #define MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x204 0x5f4 0x000 0x3 0x0 | ||
| 405 | #define MX51_PAD_AUD3_BB_RXD__UART3_RXD 0x204 0x5f4 0x9f4 0x1 0x2 | ||
| 406 | #define MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x208 0x5f8 0x000 0x0 0x0 | ||
| 407 | #define MX51_PAD_AUD3_BB_CK__GPIO4_20 0x208 0x5f8 0x000 0x3 0x0 | ||
| 408 | #define MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x20c 0x5fc 0x000 0x0 0x0 | ||
| 409 | #define MX51_PAD_AUD3_BB_FS__GPIO4_21 0x20c 0x5fc 0x000 0x3 0x0 | ||
| 410 | #define MX51_PAD_AUD3_BB_FS__UART3_TXD 0x20c 0x5fc 0x000 0x1 0x0 | ||
| 411 | #define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x210 0x600 0x000 0x0 0x0 | ||
| 412 | #define MX51_PAD_CSPI1_MOSI__GPIO4_22 0x210 0x600 0x000 0x3 0x0 | ||
| 413 | #define MX51_PAD_CSPI1_MOSI__I2C1_SDA 0x210 0x600 0x9b4 0x1 0x1 | ||
| 414 | #define MX51_PAD_CSPI1_MISO__AUD4_RXD 0x214 0x604 0x8c4 0x1 0x1 | ||
| 415 | #define MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x214 0x604 0x000 0x0 0x0 | ||
| 416 | #define MX51_PAD_CSPI1_MISO__GPIO4_23 0x214 0x604 0x000 0x3 0x0 | ||
| 417 | #define MX51_PAD_CSPI1_SS0__AUD4_TXC 0x218 0x608 0x8cc 0x1 0x1 | ||
| 418 | #define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 0x218 0x608 0x000 0x0 0x0 | ||
| 419 | #define MX51_PAD_CSPI1_SS0__GPIO4_24 0x218 0x608 0x000 0x3 0x0 | ||
| 420 | #define MX51_PAD_CSPI1_SS1__AUD4_TXD 0x21c 0x60c 0x8c8 0x1 0x1 | ||
| 421 | #define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 0x21c 0x60c 0x000 0x0 0x0 | ||
| 422 | #define MX51_PAD_CSPI1_SS1__GPIO4_25 0x21c 0x60c 0x000 0x3 0x0 | ||
| 423 | #define MX51_PAD_CSPI1_RDY__AUD4_TXFS 0x220 0x610 0x8d0 0x1 0x1 | ||
| 424 | #define MX51_PAD_CSPI1_RDY__ECSPI1_RDY 0x220 0x610 0x000 0x0 0x0 | ||
| 425 | #define MX51_PAD_CSPI1_RDY__GPIO4_26 0x220 0x610 0x000 0x3 0x0 | ||
| 426 | #define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x224 0x614 0x000 0x0 0x0 | ||
| 427 | #define MX51_PAD_CSPI1_SCLK__GPIO4_27 0x224 0x614 0x000 0x3 0x0 | ||
| 428 | #define MX51_PAD_CSPI1_SCLK__I2C1_SCL 0x224 0x614 0x9b0 0x1 0x1 | ||
| 429 | #define MX51_PAD_UART1_RXD__GPIO4_28 0x228 0x618 0x000 0x3 0x0 | ||
| 430 | #define MX51_PAD_UART1_RXD__UART1_RXD 0x228 0x618 0x9e4 0x0 0x0 | ||
| 431 | #define MX51_PAD_UART1_TXD__GPIO4_29 0x22c 0x61c 0x000 0x3 0x0 | ||
| 432 | #define MX51_PAD_UART1_TXD__PWM2_PWMO 0x22c 0x61c 0x000 0x1 0x0 | ||
| 433 | #define MX51_PAD_UART1_TXD__UART1_TXD 0x22c 0x61c 0x000 0x0 0x0 | ||
| 434 | #define MX51_PAD_UART1_RTS__GPIO4_30 0x230 0x620 0x000 0x3 0x0 | ||
| 435 | #define MX51_PAD_UART1_RTS__UART1_RTS 0x230 0x620 0x9e0 0x0 0x0 | ||
| 436 | #define MX51_PAD_UART1_CTS__GPIO4_31 0x234 0x624 0x000 0x3 0x0 | ||
| 437 | #define MX51_PAD_UART1_CTS__UART1_CTS 0x234 0x624 0x000 0x0 0x0 | ||
| 438 | #define MX51_PAD_UART2_RXD__FIRI_TXD 0x238 0x628 0x000 0x1 0x0 | ||
| 439 | #define MX51_PAD_UART2_RXD__GPIO1_20 0x238 0x628 0x000 0x3 0x0 | ||
| 440 | #define MX51_PAD_UART2_RXD__UART2_RXD 0x238 0x628 0x9ec 0x0 0x2 | ||
| 441 | #define MX51_PAD_UART2_TXD__FIRI_RXD 0x23c 0x62c 0x000 0x1 0x0 | ||
| 442 | #define MX51_PAD_UART2_TXD__GPIO1_21 0x23c 0x62c 0x000 0x3 0x0 | ||
| 443 | #define MX51_PAD_UART2_TXD__UART2_TXD 0x23c 0x62c 0x000 0x0 0x0 | ||
| 444 | #define MX51_PAD_UART3_RXD__CSI1_D0 0x240 0x630 0x000 0x2 0x0 | ||
| 445 | #define MX51_PAD_UART3_RXD__GPIO1_22 0x240 0x630 0x000 0x3 0x0 | ||
| 446 | #define MX51_PAD_UART3_RXD__UART1_DTR 0x240 0x630 0x000 0x0 0x0 | ||
| 447 | #define MX51_PAD_UART3_RXD__UART3_RXD 0x240 0x630 0x9f4 0x1 0x4 | ||
| 448 | #define MX51_PAD_UART3_TXD__CSI1_D1 0x244 0x634 0x000 0x2 0x0 | ||
| 449 | #define MX51_PAD_UART3_TXD__GPIO1_23 0x244 0x634 0x000 0x3 0x0 | ||
| 450 | #define MX51_PAD_UART3_TXD__UART1_DSR 0x244 0x634 0x000 0x0 0x0 | ||
| 451 | #define MX51_PAD_UART3_TXD__UART3_TXD 0x244 0x634 0x000 0x1 0x0 | ||
| 452 | #define MX51_PAD_OWIRE_LINE__GPIO1_24 0x248 0x638 0x000 0x3 0x0 | ||
| 453 | #define MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x248 0x638 0x000 0x0 0x0 | ||
| 454 | #define MX51_PAD_OWIRE_LINE__SPDIF_OUT 0x248 0x638 0x000 0x6 0x0 | ||
| 455 | #define MX51_PAD_KEY_ROW0__KEY_ROW0 0x24c 0x63c 0x000 0x0 0x0 | ||
| 456 | #define MX51_PAD_KEY_ROW1__KEY_ROW1 0x250 0x640 0x000 0x0 0x0 | ||
| 457 | #define MX51_PAD_KEY_ROW2__KEY_ROW2 0x254 0x644 0x000 0x0 0x0 | ||
| 458 | #define MX51_PAD_KEY_ROW3__KEY_ROW3 0x258 0x648 0x000 0x0 0x0 | ||
| 459 | #define MX51_PAD_KEY_COL0__KEY_COL0 0x25c 0x64c 0x000 0x0 0x0 | ||
| 460 | #define MX51_PAD_KEY_COL0__PLL1_BYP 0x25c 0x64c 0x90c 0x7 0x0 | ||
| 461 | #define MX51_PAD_KEY_COL1__KEY_COL1 0x260 0x650 0x000 0x0 0x0 | ||
| 462 | #define MX51_PAD_KEY_COL1__PLL2_BYP 0x260 0x650 0x910 0x7 0x0 | ||
| 463 | #define MX51_PAD_KEY_COL2__KEY_COL2 0x264 0x654 0x000 0x0 0x0 | ||
| 464 | #define MX51_PAD_KEY_COL2__PLL3_BYP 0x264 0x654 0x000 0x7 0x0 | ||
| 465 | #define MX51_PAD_KEY_COL3__KEY_COL3 0x268 0x658 0x000 0x0 0x0 | ||
| 466 | #define MX51_PAD_KEY_COL4__I2C2_SCL 0x26c 0x65c 0x9b8 0x3 0x1 | ||
| 467 | #define MX51_PAD_KEY_COL4__KEY_COL4 0x26c 0x65c 0x000 0x0 0x0 | ||
| 468 | #define MX51_PAD_KEY_COL4__SPDIF_OUT1 0x26c 0x65c 0x000 0x6 0x0 | ||
| 469 | #define MX51_PAD_KEY_COL4__UART1_RI 0x26c 0x65c 0x000 0x1 0x0 | ||
| 470 | #define MX51_PAD_KEY_COL4__UART3_RTS 0x26c 0x65c 0x9f0 0x2 0x4 | ||
| 471 | #define MX51_PAD_KEY_COL5__I2C2_SDA 0x270 0x660 0x9bc 0x3 0x1 | ||
| 472 | #define MX51_PAD_KEY_COL5__KEY_COL5 0x270 0x660 0x000 0x0 0x0 | ||
| 473 | #define MX51_PAD_KEY_COL5__UART1_DCD 0x270 0x660 0x000 0x1 0x0 | ||
| 474 | #define MX51_PAD_KEY_COL5__UART3_CTS 0x270 0x660 0x000 0x2 0x0 | ||
| 475 | #define MX51_PAD_USBH1_CLK__CSPI_SCLK 0x278 0x678 0x914 0x1 0x1 | ||
| 476 | #define MX51_PAD_USBH1_CLK__GPIO1_25 0x278 0x678 0x000 0x2 0x0 | ||
| 477 | #define MX51_PAD_USBH1_CLK__I2C2_SCL 0x278 0x678 0x9b8 0x5 0x2 | ||
| 478 | #define MX51_PAD_USBH1_CLK__USBH1_CLK 0x278 0x678 0x000 0x0 0x0 | ||
| 479 | #define MX51_PAD_USBH1_DIR__CSPI_MOSI 0x27c 0x67c 0x91c 0x1 0x1 | ||
| 480 | #define MX51_PAD_USBH1_DIR__GPIO1_26 0x27c 0x67c 0x000 0x2 0x0 | ||
| 481 | #define MX51_PAD_USBH1_DIR__I2C2_SDA 0x27c 0x67c 0x9bc 0x5 0x2 | ||
| 482 | #define MX51_PAD_USBH1_DIR__USBH1_DIR 0x27c 0x67c 0x000 0x0 0x0 | ||
| 483 | #define MX51_PAD_USBH1_STP__CSPI_RDY 0x280 0x680 0x000 0x1 0x0 | ||
| 484 | #define MX51_PAD_USBH1_STP__GPIO1_27 0x280 0x680 0x000 0x2 0x0 | ||
| 485 | #define MX51_PAD_USBH1_STP__UART3_RXD 0x280 0x680 0x9f4 0x5 0x6 | ||
| 486 | #define MX51_PAD_USBH1_STP__USBH1_STP 0x280 0x680 0x000 0x0 0x0 | ||
| 487 | #define MX51_PAD_USBH1_NXT__CSPI_MISO 0x284 0x684 0x918 0x1 0x0 | ||
| 488 | #define MX51_PAD_USBH1_NXT__GPIO1_28 0x284 0x684 0x000 0x2 0x0 | ||
| 489 | #define MX51_PAD_USBH1_NXT__UART3_TXD 0x284 0x684 0x000 0x5 0x0 | ||
| 490 | #define MX51_PAD_USBH1_NXT__USBH1_NXT 0x284 0x684 0x000 0x0 0x0 | ||
| 491 | #define MX51_PAD_USBH1_DATA0__GPIO1_11 0x288 0x688 0x000 0x2 0x0 | ||
| 492 | #define MX51_PAD_USBH1_DATA0__UART2_CTS 0x288 0x688 0x000 0x1 0x0 | ||
| 493 | #define MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x288 0x688 0x000 0x0 0x0 | ||
| 494 | #define MX51_PAD_USBH1_DATA1__GPIO1_12 0x28c 0x68c 0x000 0x2 0x0 | ||
| 495 | #define MX51_PAD_USBH1_DATA1__UART2_RXD 0x28c 0x68c 0x9ec 0x1 0x4 | ||
| 496 | #define MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x28c 0x68c 0x000 0x0 0x0 | ||
| 497 | #define MX51_PAD_USBH1_DATA2__GPIO1_13 0x290 0x690 0x000 0x2 0x0 | ||
| 498 | #define MX51_PAD_USBH1_DATA2__UART2_TXD 0x290 0x690 0x000 0x1 0x0 | ||
| 499 | #define MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x290 0x690 0x000 0x0 0x0 | ||
| 500 | #define MX51_PAD_USBH1_DATA3__GPIO1_14 0x294 0x694 0x000 0x2 0x0 | ||
| 501 | #define MX51_PAD_USBH1_DATA3__UART2_RTS 0x294 0x694 0x9e8 0x1 0x5 | ||
| 502 | #define MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x294 0x694 0x000 0x0 0x0 | ||
| 503 | #define MX51_PAD_USBH1_DATA4__CSPI_SS0 0x298 0x698 0x000 0x1 0x0 | ||
| 504 | #define MX51_PAD_USBH1_DATA4__GPIO1_15 0x298 0x698 0x000 0x2 0x0 | ||
| 505 | #define MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x298 0x698 0x000 0x0 0x0 | ||
| 506 | #define MX51_PAD_USBH1_DATA5__CSPI_SS1 0x29c 0x69c 0x920 0x1 0x0 | ||
| 507 | #define MX51_PAD_USBH1_DATA5__GPIO1_16 0x29c 0x69c 0x000 0x2 0x0 | ||
| 508 | #define MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x29c 0x69c 0x000 0x0 0x0 | ||
| 509 | #define MX51_PAD_USBH1_DATA6__CSPI_SS3 0x2a0 0x6a0 0x928 0x1 0x1 | ||
| 510 | #define MX51_PAD_USBH1_DATA6__GPIO1_17 0x2a0 0x6a0 0x000 0x2 0x0 | ||
| 511 | #define MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x2a0 0x6a0 0x000 0x0 0x0 | ||
| 512 | #define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 0x2a4 0x6a4 0x000 0x1 0x0 | ||
| 513 | #define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 0x2a4 0x6a4 0x934 0x5 0x1 | ||
| 514 | #define MX51_PAD_USBH1_DATA7__GPIO1_18 0x2a4 0x6a4 0x000 0x2 0x0 | ||
| 515 | #define MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x2a4 0x6a4 0x000 0x0 0x0 | ||
| 516 | #define MX51_PAD_DI1_PIN11__DI1_PIN11 0x2a8 0x6a8 0x000 0x0 0x0 | ||
| 517 | #define MX51_PAD_DI1_PIN11__ECSPI1_SS2 0x2a8 0x6a8 0x000 0x7 0x0 | ||
| 518 | #define MX51_PAD_DI1_PIN11__GPIO3_0 0x2a8 0x6a8 0x000 0x4 0x0 | ||
| 519 | #define MX51_PAD_DI1_PIN12__DI1_PIN12 0x2ac 0x6ac 0x000 0x0 0x0 | ||
| 520 | #define MX51_PAD_DI1_PIN12__GPIO3_1 0x2ac 0x6ac 0x978 0x4 0x1 | ||
| 521 | #define MX51_PAD_DI1_PIN13__DI1_PIN13 0x2b0 0x6b0 0x000 0x0 0x0 | ||
| 522 | #define MX51_PAD_DI1_PIN13__GPIO3_2 0x2b0 0x6b0 0x97c 0x4 0x1 | ||
| 523 | #define MX51_PAD_DI1_D0_CS__DI1_D0_CS 0x2b4 0x6b4 0x000 0x0 0x0 | ||
| 524 | #define MX51_PAD_DI1_D0_CS__GPIO3_3 0x2b4 0x6b4 0x980 0x4 0x1 | ||
| 525 | #define MX51_PAD_DI1_D1_CS__DI1_D1_CS 0x2b8 0x6b8 0x000 0x0 0x0 | ||
| 526 | #define MX51_PAD_DI1_D1_CS__DISP1_PIN14 0x2b8 0x6b8 0x000 0x2 0x0 | ||
| 527 | #define MX51_PAD_DI1_D1_CS__DISP1_PIN5 0x2b8 0x6b8 0x000 0x3 0x0 | ||
| 528 | #define MX51_PAD_DI1_D1_CS__GPIO3_4 0x2b8 0x6b8 0x984 0x4 0x1 | ||
| 529 | #define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 0x2bc 0x6bc 0x9a4 0x2 0x1 | ||
| 530 | #define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 0x2bc 0x6bc 0x9c4 0x0 0x0 | ||
| 531 | #define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 0x2bc 0x6bc 0x988 0x4 0x1 | ||
| 532 | #define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 0x2c0 0x6c0 0x000 0x3 0x0 | ||
| 533 | #define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 0x2c0 0x6c0 0x9c4 0x0 0x1 | ||
| 534 | #define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0x2c0 0x6c0 0x98c 0x4 0x1 | ||
| 535 | #define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 0x2c4 0x6c4 0x000 0x2 0x0 | ||
| 536 | #define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 0x2c4 0x6c4 0x000 0x3 0x0 | ||
| 537 | #define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 0x2c4 0x6c4 0x000 0x0 0x0 | ||
| 538 | #define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 0x2c4 0x6c4 0x990 0x4 0x1 | ||
| 539 | #define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK 0x2c8 0x6c8 0x000 0x2 0x0 | ||
| 540 | #define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 0x2c8 0x6c8 0x000 0x2 0x0 | ||
| 541 | #define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 0x2c8 0x6c8 0x000 0x3 0x0 | ||
| 542 | #define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 0x2c8 0x6c8 0x000 0x0 0x0 | ||
| 543 | #define MX51_PAD_DISPB2_SER_RS__GPIO3_8 0x2c8 0x6c8 0x994 0x4 0x1 | ||
| 544 | #define MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x2cc 0x6cc 0x000 0x0 0x0 | ||
| 545 | #define MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x2d0 0x6d0 0x000 0x0 0x0 | ||
| 546 | #define MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x2d4 0x6d4 0x000 0x0 0x0 | ||
| 547 | #define MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x2d8 0x6d8 0x000 0x0 0x0 | ||
| 548 | #define MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x2dc 0x6dc 0x000 0x0 0x0 | ||
| 549 | #define MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x2e0 0x6e0 0x000 0x0 0x0 | ||
| 550 | #define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 0x2e4 0x6e4 0x000 0x7 0x0 | ||
| 551 | #define MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x2e4 0x6e4 0x000 0x0 0x0 | ||
| 552 | #define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 0x2e8 0x6e8 0x000 0x7 0x0 | ||
| 553 | #define MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x2e8 0x6e8 0x000 0x0 0x0 | ||
| 554 | #define MX51_PAD_DISP1_DAT8__BOOT_SRC0 0x2ec 0x6ec 0x000 0x7 0x0 | ||
| 555 | #define MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x2ec 0x6ec 0x000 0x0 0x0 | ||
| 556 | #define MX51_PAD_DISP1_DAT9__BOOT_SRC1 0x2f0 0x6f0 0x000 0x7 0x0 | ||
| 557 | #define MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x2f0 0x6f0 0x000 0x0 0x0 | ||
| 558 | #define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 0x2f4 0x6f4 0x000 0x7 0x0 | ||
| 559 | #define MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x2f4 0x6f4 0x000 0x0 0x0 | ||
| 560 | #define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 0x2f8 0x6f8 0x000 0x7 0x0 | ||
| 561 | #define MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x2f8 0x6f8 0x000 0x0 0x0 | ||
| 562 | #define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 0x2fc 0x6fc 0x000 0x7 0x0 | ||
| 563 | #define MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x2fc 0x6fc 0x000 0x0 0x0 | ||
| 564 | #define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 0x300 0x700 0x000 0x7 0x0 | ||
| 565 | #define MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x300 0x700 0x000 0x0 0x0 | ||
| 566 | #define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 0x304 0x704 0x000 0x7 0x0 | ||
| 567 | #define MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x304 0x704 0x000 0x0 0x0 | ||
| 568 | #define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 0x308 0x708 0x000 0x7 0x0 | ||
| 569 | #define MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x308 0x708 0x000 0x0 0x0 | ||
| 570 | #define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 0x30c 0x70c 0x000 0x7 0x0 | ||
| 571 | #define MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x30c 0x70c 0x000 0x0 0x0 | ||
| 572 | #define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 0x310 0x710 0x000 0x7 0x0 | ||
| 573 | #define MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x310 0x710 0x000 0x0 0x0 | ||
| 574 | #define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 0x314 0x714 0x000 0x7 0x0 | ||
| 575 | #define MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x314 0x714 0x000 0x0 0x0 | ||
| 576 | #define MX51_PAD_DISP1_DAT18__DISP2_PIN11 0x314 0x714 0x000 0x5 0x0 | ||
| 577 | #define MX51_PAD_DISP1_DAT18__DISP2_PIN5 0x314 0x714 0x000 0x4 0x0 | ||
| 578 | #define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 0x318 0x718 0x000 0x7 0x0 | ||
| 579 | #define MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x318 0x718 0x000 0x0 0x0 | ||
| 580 | #define MX51_PAD_DISP1_DAT19__DISP2_PIN12 0x318 0x718 0x000 0x5 0x0 | ||
| 581 | #define MX51_PAD_DISP1_DAT19__DISP2_PIN6 0x318 0x718 0x000 0x4 0x0 | ||
| 582 | #define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 0x31c 0x71c 0x000 0x7 0x0 | ||
| 583 | #define MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x31c 0x71c 0x000 0x0 0x0 | ||
| 584 | #define MX51_PAD_DISP1_DAT20__DISP2_PIN13 0x31c 0x71c 0x000 0x5 0x0 | ||
| 585 | #define MX51_PAD_DISP1_DAT20__DISP2_PIN7 0x31c 0x71c 0x000 0x4 0x0 | ||
| 586 | #define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 0x320 0x720 0x000 0x7 0x0 | ||
| 587 | #define MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x320 0x720 0x000 0x0 0x0 | ||
| 588 | #define MX51_PAD_DISP1_DAT21__DISP2_PIN14 0x320 0x720 0x000 0x5 0x0 | ||
| 589 | #define MX51_PAD_DISP1_DAT21__DISP2_PIN8 0x320 0x720 0x000 0x4 0x0 | ||
| 590 | #define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 0x324 0x724 0x000 0x7 0x0 | ||
| 591 | #define MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x324 0x724 0x000 0x0 0x0 | ||
| 592 | #define MX51_PAD_DISP1_DAT22__DISP2_D0_CS 0x324 0x724 0x000 0x6 0x0 | ||
| 593 | #define MX51_PAD_DISP1_DAT22__DISP2_DAT16 0x324 0x724 0x000 0x5 0x0 | ||
| 594 | #define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 0x328 0x728 0x000 0x7 0x0 | ||
| 595 | #define MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x328 0x728 0x000 0x0 0x0 | ||
| 596 | #define MX51_PAD_DISP1_DAT23__DISP2_D1_CS 0x328 0x728 0x000 0x6 0x0 | ||
| 597 | #define MX51_PAD_DISP1_DAT23__DISP2_DAT17 0x328 0x728 0x000 0x5 0x0 | ||
| 598 | #define MX51_PAD_DISP1_DAT23__DISP2_SER_CS 0x328 0x728 0x000 0x4 0x0 | ||
| 599 | #define MX51_PAD_DI1_PIN3__DI1_PIN3 0x32c 0x72c 0x000 0x0 0x0 | ||
| 600 | #define MX51_PAD_DI1_PIN2__DI1_PIN2 0x330 0x734 0x000 0x0 0x0 | ||
| 601 | #define MX51_PAD_DI_GP2__DISP1_SER_CLK 0x338 0x740 0x000 0x0 0x0 | ||
| 602 | #define MX51_PAD_DI_GP2__DISP2_WAIT 0x338 0x740 0x9a8 0x2 0x1 | ||
| 603 | #define MX51_PAD_DI_GP3__CSI1_DATA_EN 0x33c 0x744 0x9a0 0x3 0x1 | ||
| 604 | #define MX51_PAD_DI_GP3__DISP1_SER_DIO 0x33c 0x744 0x9c0 0x0 0x0 | ||
| 605 | #define MX51_PAD_DI_GP3__FEC_TX_ER 0x33c 0x744 0x000 0x2 0x0 | ||
| 606 | #define MX51_PAD_DI2_PIN4__CSI2_DATA_EN 0x340 0x748 0x99c 0x3 0x1 | ||
| 607 | #define MX51_PAD_DI2_PIN4__DI2_PIN4 0x340 0x748 0x000 0x0 0x0 | ||
| 608 | #define MX51_PAD_DI2_PIN4__FEC_CRS 0x340 0x748 0x950 0x2 0x1 | ||
| 609 | #define MX51_PAD_DI2_PIN2__DI2_PIN2 0x344 0x74c 0x000 0x0 0x0 | ||
| 610 | #define MX51_PAD_DI2_PIN2__FEC_MDC 0x344 0x74c 0x000 0x2 0x0 | ||
| 611 | #define MX51_PAD_DI2_PIN3__DI2_PIN3 0x348 0x750 0x000 0x0 0x0 | ||
| 612 | #define MX51_PAD_DI2_PIN3__FEC_MDIO 0x348 0x750 0x954 0x2 0x1 | ||
| 613 | #define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x34c 0x754 0x000 0x0 0x0 | ||
| 614 | #define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x34c 0x754 0x95c 0x2 0x1 | ||
| 615 | #define MX51_PAD_DI_GP4__DI2_PIN15 0x350 0x758 0x000 0x4 0x0 | ||
| 616 | #define MX51_PAD_DI_GP4__DISP1_SER_DIN 0x350 0x758 0x9c0 0x0 0x1 | ||
| 617 | #define MX51_PAD_DI_GP4__DISP2_PIN1 0x350 0x758 0x000 0x3 0x0 | ||
| 618 | #define MX51_PAD_DI_GP4__FEC_RDATA2 0x350 0x758 0x960 0x2 0x1 | ||
| 619 | #define MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x354 0x75c 0x000 0x0 0x0 | ||
| 620 | #define MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x354 0x75c 0x964 0x2 0x1 | ||
| 621 | #define MX51_PAD_DISP2_DAT0__KEY_COL6 0x354 0x75c 0x9c8 0x4 0x1 | ||
| 622 | #define MX51_PAD_DISP2_DAT0__UART3_RXD 0x354 0x75c 0x9f4 0x5 0x8 | ||
| 623 | #define MX51_PAD_DISP2_DAT0__USBH3_CLK 0x354 0x75c 0x9f8 0x3 0x1 | ||
| 624 | #define MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x358 0x760 0x000 0x0 0x0 | ||
| 625 | #define MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x358 0x760 0x970 0x2 0x1 | ||
| 626 | #define MX51_PAD_DISP2_DAT1__KEY_COL7 0x358 0x760 0x9cc 0x4 0x1 | ||
| 627 | #define MX51_PAD_DISP2_DAT1__UART3_TXD 0x358 0x760 0x000 0x5 0x0 | ||
| 628 | #define MX51_PAD_DISP2_DAT1__USBH3_DIR 0x358 0x760 0xa1c 0x3 0x1 | ||
| 629 | #define MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x35c 0x764 0x000 0x0 0x0 | ||
| 630 | #define MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x360 0x768 0x000 0x0 0x0 | ||
| 631 | #define MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x364 0x76c 0x000 0x0 0x0 | ||
| 632 | #define MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x368 0x770 0x000 0x0 0x0 | ||
| 633 | #define MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x36c 0x774 0x000 0x0 0x0 | ||
| 634 | #define MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x36c 0x774 0x000 0x2 0x0 | ||
| 635 | #define MX51_PAD_DISP2_DAT6__GPIO1_19 0x36c 0x774 0x000 0x5 0x0 | ||
| 636 | #define MX51_PAD_DISP2_DAT6__KEY_ROW4 0x36c 0x774 0x9d0 0x4 0x1 | ||
| 637 | #define MX51_PAD_DISP2_DAT6__USBH3_STP 0x36c 0x774 0xa24 0x3 0x1 | ||
| 638 | #define MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x370 0x778 0x000 0x0 0x0 | ||
| 639 | #define MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x370 0x778 0x000 0x2 0x0 | ||
| 640 | #define MX51_PAD_DISP2_DAT7__GPIO1_29 0x370 0x778 0x000 0x5 0x0 | ||
| 641 | #define MX51_PAD_DISP2_DAT7__KEY_ROW5 0x370 0x778 0x9d4 0x4 0x1 | ||
| 642 | #define MX51_PAD_DISP2_DAT7__USBH3_NXT 0x370 0x778 0xa20 0x3 0x1 | ||
| 643 | #define MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x374 0x77c 0x000 0x0 0x0 | ||
| 644 | #define MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x374 0x77c 0x000 0x2 0x0 | ||
| 645 | #define MX51_PAD_DISP2_DAT8__GPIO1_30 0x374 0x77c 0x000 0x5 0x0 | ||
| 646 | #define MX51_PAD_DISP2_DAT8__KEY_ROW6 0x374 0x77c 0x9d8 0x4 0x1 | ||
| 647 | #define MX51_PAD_DISP2_DAT8__USBH3_DATA0 0x374 0x77c 0x9fc 0x3 0x1 | ||
| 648 | #define MX51_PAD_DISP2_DAT9__AUD6_RXC 0x378 0x780 0x8f4 0x4 0x1 | ||
| 649 | #define MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x378 0x780 0x000 0x0 0x0 | ||
| 650 | #define MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x378 0x780 0x000 0x2 0x0 | ||
| 651 | #define MX51_PAD_DISP2_DAT9__GPIO1_31 0x378 0x780 0x000 0x5 0x0 | ||
| 652 | #define MX51_PAD_DISP2_DAT9__USBH3_DATA1 0x378 0x780 0xa00 0x3 0x1 | ||
| 653 | #define MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x37c 0x784 0x000 0x0 0x0 | ||
| 654 | #define MX51_PAD_DISP2_DAT10__DISP2_SER_CS 0x37c 0x784 0x000 0x5 0x0 | ||
| 655 | #define MX51_PAD_DISP2_DAT10__FEC_COL 0x37c 0x784 0x94c 0x2 0x1 | ||
| 656 | #define MX51_PAD_DISP2_DAT10__KEY_ROW7 0x37c 0x784 0x9dc 0x4 0x1 | ||
| 657 | #define MX51_PAD_DISP2_DAT10__USBH3_DATA2 0x37c 0x784 0xa04 0x3 0x1 | ||
| 658 | #define MX51_PAD_DISP2_DAT11__AUD6_TXD 0x380 0x788 0x8f0 0x4 0x1 | ||
| 659 | #define MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x380 0x788 0x000 0x0 0x0 | ||
| 660 | #define MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x380 0x788 0x968 0x2 0x1 | ||
| 661 | #define MX51_PAD_DISP2_DAT11__GPIO1_10 0x380 0x788 0x000 0x7 0x0 | ||
| 662 | #define MX51_PAD_DISP2_DAT11__USBH3_DATA3 0x380 0x788 0xa08 0x3 0x1 | ||
| 663 | #define MX51_PAD_DISP2_DAT12__AUD6_RXD 0x384 0x78c 0x8ec 0x4 0x1 | ||
| 664 | #define MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x384 0x78c 0x000 0x0 0x0 | ||
| 665 | #define MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x384 0x78c 0x96c 0x2 0x1 | ||
| 666 | #define MX51_PAD_DISP2_DAT12__USBH3_DATA4 0x384 0x78c 0xa0c 0x3 0x1 | ||
| 667 | #define MX51_PAD_DISP2_DAT13__AUD6_TXC 0x388 0x790 0x8fc 0x4 0x1 | ||
| 668 | #define MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x388 0x790 0x000 0x0 0x0 | ||
| 669 | #define MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x388 0x790 0x974 0x2 0x1 | ||
| 670 | #define MX51_PAD_DISP2_DAT13__USBH3_DATA5 0x388 0x790 0xa10 0x3 0x1 | ||
| 671 | #define MX51_PAD_DISP2_DAT14__AUD6_TXFS 0x38c 0x794 0x900 0x4 0x1 | ||
| 672 | #define MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x38c 0x794 0x000 0x0 0x0 | ||
| 673 | #define MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x38c 0x794 0x958 0x2 0x1 | ||
| 674 | #define MX51_PAD_DISP2_DAT14__USBH3_DATA6 0x38c 0x794 0xa14 0x3 0x1 | ||
| 675 | #define MX51_PAD_DISP2_DAT15__AUD6_RXFS 0x390 0x798 0x8f8 0x4 0x1 | ||
| 676 | #define MX51_PAD_DISP2_DAT15__DISP1_SER_CS 0x390 0x798 0x000 0x5 0x0 | ||
| 677 | #define MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x390 0x798 0x000 0x0 0x0 | ||
| 678 | #define MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x390 0x798 0x000 0x2 0x0 | ||
| 679 | #define MX51_PAD_DISP2_DAT15__USBH3_DATA7 0x390 0x798 0xa18 0x3 0x1 | ||
| 680 | #define MX51_PAD_SD1_CMD__AUD5_RXFS 0x394 0x79c 0x8e0 0x1 0x1 | ||
| 681 | #define MX51_PAD_SD1_CMD__CSPI_MOSI 0x394 0x79c 0x91c 0x2 0x2 | ||
| 682 | #define MX51_PAD_SD1_CMD__SD1_CMD 0x394 0x79c 0x000 0x0 0x0 | ||
| 683 | #define MX51_PAD_SD1_CLK__AUD5_RXC 0x398 0x7a0 0x8dc 0x1 0x1 | ||
| 684 | #define MX51_PAD_SD1_CLK__CSPI_SCLK 0x398 0x7a0 0x914 0x2 0x2 | ||
| 685 | #define MX51_PAD_SD1_CLK__SD1_CLK 0x398 0x7a0 0x000 0x0 0x0 | ||
| 686 | #define MX51_PAD_SD1_DATA0__AUD5_TXD 0x39c 0x7a4 0x8d8 0x1 0x2 | ||
| 687 | #define MX51_PAD_SD1_DATA0__CSPI_MISO 0x39c 0x7a4 0x918 0x2 0x1 | ||
| 688 | #define MX51_PAD_SD1_DATA0__SD1_DATA0 0x39c 0x7a4 0x000 0x0 0x0 | ||
| 689 | #define MX51_PAD_EIM_DA0__EIM_DA0 0x01c 0x000 0x000 0x0 0x0 | ||
| 690 | #define MX51_PAD_EIM_DA1__EIM_DA1 0x020 0x000 0x000 0x0 0x0 | ||
| 691 | #define MX51_PAD_EIM_DA2__EIM_DA2 0x024 0x000 0x000 0x0 0x0 | ||
| 692 | #define MX51_PAD_EIM_DA3__EIM_DA3 0x028 0x000 0x000 0x0 0x0 | ||
| 693 | #define MX51_PAD_SD1_DATA1__AUD5_RXD 0x3a0 0x7a8 0x8d4 0x1 0x2 | ||
| 694 | #define MX51_PAD_SD1_DATA1__SD1_DATA1 0x3a0 0x7a8 0x000 0x0 0x0 | ||
| 695 | #define MX51_PAD_EIM_DA4__EIM_DA4 0x02c 0x000 0x000 0x0 0x0 | ||
| 696 | #define MX51_PAD_EIM_DA5__EIM_DA5 0x030 0x000 0x000 0x0 0x0 | ||
| 697 | #define MX51_PAD_EIM_DA6__EIM_DA6 0x034 0x000 0x000 0x0 0x0 | ||
| 698 | #define MX51_PAD_EIM_DA7__EIM_DA7 0x038 0x000 0x000 0x0 0x0 | ||
| 699 | #define MX51_PAD_SD1_DATA2__AUD5_TXC 0x3a4 0x7ac 0x8e4 0x1 0x2 | ||
| 700 | #define MX51_PAD_SD1_DATA2__SD1_DATA2 0x3a4 0x7ac 0x000 0x0 0x0 | ||
| 701 | #define MX51_PAD_EIM_DA10__EIM_DA10 0x044 0x000 0x000 0x0 0x0 | ||
| 702 | #define MX51_PAD_EIM_DA11__EIM_DA11 0x048 0x000 0x000 0x0 0x0 | ||
| 703 | #define MX51_PAD_EIM_DA8__EIM_DA8 0x03c 0x000 0x000 0x0 0x0 | ||
| 704 | #define MX51_PAD_EIM_DA9__EIM_DA9 0x040 0x000 0x000 0x0 0x0 | ||
| 705 | #define MX51_PAD_SD1_DATA3__AUD5_TXFS 0x3a8 0x7b0 0x8e8 0x1 0x2 | ||
| 706 | #define MX51_PAD_SD1_DATA3__CSPI_SS1 0x3a8 0x7b0 0x920 0x2 0x1 | ||
| 707 | #define MX51_PAD_SD1_DATA3__SD1_DATA3 0x3a8 0x7b0 0x000 0x0 0x0 | ||
| 708 | #define MX51_PAD_GPIO1_0__CSPI_SS2 0x3ac 0x7b4 0x924 0x2 0x0 | ||
| 709 | #define MX51_PAD_GPIO1_0__GPIO1_0 0x3ac 0x7b4 0x000 0x1 0x0 | ||
| 710 | #define MX51_PAD_GPIO1_0__SD1_CD 0x3ac 0x7b4 0x000 0x0 0x0 | ||
| 711 | #define MX51_PAD_GPIO1_1__CSPI_MISO 0x3b0 0x7b8 0x918 0x2 0x2 | ||
| 712 | #define MX51_PAD_GPIO1_1__GPIO1_1 0x3b0 0x7b8 0x000 0x1 0x0 | ||
| 713 | #define MX51_PAD_GPIO1_1__SD1_WP 0x3b0 0x7b8 0x000 0x0 0x0 | ||
| 714 | #define MX51_PAD_EIM_DA12__EIM_DA12 0x04c 0x000 0x000 0x0 0x0 | ||
| 715 | #define MX51_PAD_EIM_DA13__EIM_DA13 0x050 0x000 0x000 0x0 0x0 | ||
| 716 | #define MX51_PAD_EIM_DA14__EIM_DA14 0x054 0x000 0x000 0x0 0x0 | ||
| 717 | #define MX51_PAD_EIM_DA15__EIM_DA15 0x058 0x000 0x000 0x0 0x0 | ||
| 718 | #define MX51_PAD_SD2_CMD__CSPI_MOSI 0x3b4 0x7bc 0x91c 0x2 0x3 | ||
| 719 | #define MX51_PAD_SD2_CMD__I2C1_SCL 0x3b4 0x7bc 0x9b0 0x1 0x2 | ||
| 720 | #define MX51_PAD_SD2_CMD__SD2_CMD 0x3b4 0x7bc 0x000 0x0 0x0 | ||
| 721 | #define MX51_PAD_SD2_CLK__CSPI_SCLK 0x3b8 0x7c0 0x914 0x2 0x3 | ||
| 722 | #define MX51_PAD_SD2_CLK__I2C1_SDA 0x3b8 0x7c0 0x9b4 0x1 0x2 | ||
| 723 | #define MX51_PAD_SD2_CLK__SD2_CLK 0x3b8 0x7c0 0x000 0x0 0x0 | ||
| 724 | #define MX51_PAD_SD2_DATA0__CSPI_MISO 0x3bc 0x7c4 0x918 0x2 0x3 | ||
| 725 | #define MX51_PAD_SD2_DATA0__SD1_DAT4 0x3bc 0x7c4 0x000 0x1 0x0 | ||
| 726 | #define MX51_PAD_SD2_DATA0__SD2_DATA0 0x3bc 0x7c4 0x000 0x0 0x0 | ||
| 727 | #define MX51_PAD_SD2_DATA1__SD1_DAT5 0x3c0 0x7c8 0x000 0x1 0x0 | ||
| 728 | #define MX51_PAD_SD2_DATA1__SD2_DATA1 0x3c0 0x7c8 0x000 0x0 0x0 | ||
| 729 | #define MX51_PAD_SD2_DATA1__USBH3_H2_DP 0x3c0 0x7c8 0x000 0x2 0x0 | ||
| 730 | #define MX51_PAD_SD2_DATA2__SD1_DAT6 0x3c4 0x7cc 0x000 0x1 0x0 | ||
| 731 | #define MX51_PAD_SD2_DATA2__SD2_DATA2 0x3c4 0x7cc 0x000 0x0 0x0 | ||
| 732 | #define MX51_PAD_SD2_DATA2__USBH3_H2_DM 0x3c4 0x7cc 0x000 0x2 0x0 | ||
| 733 | #define MX51_PAD_SD2_DATA3__CSPI_SS2 0x3c8 0x7d0 0x924 0x2 0x1 | ||
| 734 | #define MX51_PAD_SD2_DATA3__SD1_DAT7 0x3c8 0x7d0 0x000 0x1 0x0 | ||
| 735 | #define MX51_PAD_SD2_DATA3__SD2_DATA3 0x3c8 0x7d0 0x000 0x0 0x0 | ||
| 736 | #define MX51_PAD_GPIO1_2__CCM_OUT_2 0x3cc 0x7d4 0x000 0x5 0x0 | ||
| 737 | #define MX51_PAD_GPIO1_2__GPIO1_2 0x3cc 0x7d4 0x000 0x0 0x0 | ||
| 738 | #define MX51_PAD_GPIO1_2__I2C2_SCL 0x3cc 0x7d4 0x9b8 0x2 0x3 | ||
| 739 | #define MX51_PAD_GPIO1_2__PLL1_BYP 0x3cc 0x7d4 0x90c 0x7 0x1 | ||
| 740 | #define MX51_PAD_GPIO1_2__PWM1_PWMO 0x3cc 0x7d4 0x000 0x1 0x0 | ||
| 741 | #define MX51_PAD_GPIO1_3__GPIO1_3 0x3d0 0x7d8 0x000 0x0 0x0 | ||
| 742 | #define MX51_PAD_GPIO1_3__I2C2_SDA 0x3d0 0x7d8 0x9bc 0x2 0x3 | ||
| 743 | #define MX51_PAD_GPIO1_3__PLL2_BYP 0x3d0 0x7d8 0x910 0x7 0x1 | ||
| 744 | #define MX51_PAD_GPIO1_3__PWM2_PWMO 0x3d0 0x7d8 0x000 0x1 0x0 | ||
| 745 | #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 0x3d4 0x7fc 0x000 0x0 0x0 | ||
| 746 | #define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 0x3d4 0x7fc 0x000 0x1 0x0 | ||
| 747 | #define MX51_PAD_GPIO1_4__DISP2_EXT_CLK 0x3d8 0x804 0x908 0x4 0x1 | ||
| 748 | #define MX51_PAD_GPIO1_4__EIM_RDY 0x3d8 0x804 0x938 0x3 0x1 | ||
| 749 | #define MX51_PAD_GPIO1_4__GPIO1_4 0x3d8 0x804 0x000 0x0 0x0 | ||
| 750 | #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B 0x3d8 0x804 0x000 0x2 0x0 | ||
| 751 | #define MX51_PAD_GPIO1_5__CSI2_MCLK 0x3dc 0x808 0x000 0x6 0x0 | ||
| 752 | #define MX51_PAD_GPIO1_5__DISP2_PIN16 0x3dc 0x808 0x000 0x3 0x0 | ||
| 753 | #define MX51_PAD_GPIO1_5__GPIO1_5 0x3dc 0x808 0x000 0x0 0x0 | ||
| 754 | #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B 0x3dc 0x808 0x000 0x2 0x0 | ||
| 755 | #define MX51_PAD_GPIO1_6__DISP2_PIN17 0x3e0 0x80c 0x000 0x4 0x0 | ||
| 756 | #define MX51_PAD_GPIO1_6__GPIO1_6 0x3e0 0x80c 0x000 0x0 0x0 | ||
| 757 | #define MX51_PAD_GPIO1_6__REF_EN_B 0x3e0 0x80c 0x000 0x3 0x0 | ||
| 758 | #define MX51_PAD_GPIO1_7__CCM_OUT_0 0x3e4 0x810 0x000 0x3 0x0 | ||
| 759 | #define MX51_PAD_GPIO1_7__GPIO1_7 0x3e4 0x810 0x000 0x0 0x0 | ||
| 760 | #define MX51_PAD_GPIO1_7__SD2_WP 0x3e4 0x810 0x000 0x6 0x0 | ||
| 761 | #define MX51_PAD_GPIO1_7__SPDIF_OUT1 0x3e4 0x810 0x000 0x2 0x0 | ||
| 762 | #define MX51_PAD_GPIO1_8__CSI2_DATA_EN 0x3e8 0x814 0x99c 0x2 0x2 | ||
| 763 | #define MX51_PAD_GPIO1_8__GPIO1_8 0x3e8 0x814 0x000 0x0 0x0 | ||
| 764 | #define MX51_PAD_GPIO1_8__SD2_CD 0x3e8 0x814 0x000 0x6 0x0 | ||
| 765 | #define MX51_PAD_GPIO1_8__USBH3_PWR 0x3e8 0x814 0x000 0x1 0x0 | ||
| 766 | #define MX51_PAD_GPIO1_9__CCM_OUT_1 0x3ec 0x818 0x000 0x3 0x0 | ||
| 767 | #define MX51_PAD_GPIO1_9__DISP2_D1_CS 0x3ec 0x818 0x000 0x2 0x0 | ||
| 768 | #define MX51_PAD_GPIO1_9__DISP2_SER_CS 0x3ec 0x818 0x000 0x7 0x0 | ||
| 769 | #define MX51_PAD_GPIO1_9__GPIO1_9 0x3ec 0x818 0x000 0x0 0x0 | ||
| 770 | #define MX51_PAD_GPIO1_9__SD2_LCTL 0x3ec 0x818 0x000 0x6 0x0 | ||
| 771 | #define MX51_PAD_GPIO1_9__USBH3_OC 0x3ec 0x818 0x000 0x1 0x0 | ||
| 772 | |||
| 773 | #endif /* __DTS_IMX51_PINFUNC_H */ | ||
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index fcf035bf7c5a..21bb786c5b31 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi | |||
| @@ -10,7 +10,8 @@ | |||
| 10 | * http://www.gnu.org/copyleft/gpl.html | 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /include/ "skeleton.dtsi" | 13 | #include "skeleton.dtsi" |
| 14 | #include "imx51-pinfunc.h" | ||
| 14 | 15 | ||
| 15 | / { | 16 | / { |
| 16 | aliases { | 17 | aliases { |
| @@ -55,6 +56,24 @@ | |||
| 55 | }; | 56 | }; |
| 56 | }; | 57 | }; |
| 57 | 58 | ||
| 59 | cpus { | ||
| 60 | #address-cells = <1>; | ||
| 61 | #size-cells = <0>; | ||
| 62 | cpu@0 { | ||
| 63 | device_type = "cpu"; | ||
| 64 | compatible = "arm,cortex-a8"; | ||
| 65 | reg = <0>; | ||
| 66 | clock-latency = <61036>; /* two CLK32 periods */ | ||
| 67 | clocks = <&clks 24>; | ||
| 68 | clock-names = "cpu"; | ||
| 69 | operating-points = < | ||
| 70 | /* kHz uV (No regulator support) */ | ||
| 71 | 160000 0 | ||
| 72 | 800000 0 | ||
| 73 | >; | ||
| 74 | }; | ||
| 75 | }; | ||
| 76 | |||
| 58 | soc { | 77 | soc { |
| 59 | #address-cells = <1>; | 78 | #address-cells = <1>; |
| 60 | #size-cells = <1>; | 79 | #size-cells = <1>; |
| @@ -67,6 +86,9 @@ | |||
| 67 | compatible = "fsl,imx51-ipu"; | 86 | compatible = "fsl,imx51-ipu"; |
| 68 | reg = <0x40000000 0x20000000>; | 87 | reg = <0x40000000 0x20000000>; |
| 69 | interrupts = <11 10>; | 88 | interrupts = <11 10>; |
| 89 | clocks = <&clks 59>, <&clks 110>, <&clks 61>; | ||
| 90 | clock-names = "bus", "di0", "di1"; | ||
| 91 | resets = <&src 2>; | ||
| 70 | }; | 92 | }; |
| 71 | 93 | ||
| 72 | aips@70000000 { /* AIPS1 */ | 94 | aips@70000000 { /* AIPS1 */ |
| @@ -244,6 +266,14 @@ | |||
| 244 | status = "disabled"; | 266 | status = "disabled"; |
| 245 | }; | 267 | }; |
| 246 | 268 | ||
| 269 | gpt: timer@73fa0000 { | ||
| 270 | compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; | ||
| 271 | reg = <0x73fa0000 0x4000>; | ||
| 272 | interrupts = <39>; | ||
| 273 | clocks = <&clks 36>, <&clks 41>; | ||
| 274 | clock-names = "ipg", "per"; | ||
| 275 | }; | ||
| 276 | |||
| 247 | iomuxc: iomuxc@73fa8000 { | 277 | iomuxc: iomuxc@73fa8000 { |
| 248 | compatible = "fsl,imx51-iomuxc"; | 278 | compatible = "fsl,imx51-iomuxc"; |
| 249 | reg = <0x73fa8000 0x4000>; | 279 | reg = <0x73fa8000 0x4000>; |
| @@ -251,10 +281,10 @@ | |||
| 251 | audmux { | 281 | audmux { |
| 252 | pinctrl_audmux_1: audmuxgrp-1 { | 282 | pinctrl_audmux_1: audmuxgrp-1 { |
| 253 | fsl,pins = < | 283 | fsl,pins = < |
| 254 | 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */ | 284 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 |
| 255 | 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */ | 285 | MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 |
| 256 | 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */ | 286 | MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 |
| 257 | 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */ | 287 | MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 |
| 258 | >; | 288 | >; |
| 259 | }; | 289 | }; |
| 260 | }; | 290 | }; |
| @@ -262,46 +292,46 @@ | |||
| 262 | fec { | 292 | fec { |
| 263 | pinctrl_fec_1: fecgrp-1 { | 293 | pinctrl_fec_1: fecgrp-1 { |
| 264 | fsl,pins = < | 294 | fsl,pins = < |
| 265 | 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */ | 295 | MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 |
| 266 | 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */ | 296 | MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 |
| 267 | 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */ | 297 | MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 |
| 268 | 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */ | 298 | MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 |
| 269 | 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */ | 299 | MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 |
| 270 | 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */ | 300 | MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 |
| 271 | 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */ | 301 | MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 |
| 272 | 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */ | 302 | MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 |
| 273 | 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */ | 303 | MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 |
| 274 | 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */ | 304 | MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 |
| 275 | 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */ | 305 | MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 |
| 276 | 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */ | 306 | MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 |
| 277 | 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */ | 307 | MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 |
| 278 | 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */ | 308 | MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 |
| 279 | 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */ | 309 | MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 |
| 280 | 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */ | 310 | MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 |
| 281 | 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */ | 311 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 |
| 282 | >; | 312 | >; |
| 283 | }; | 313 | }; |
| 284 | 314 | ||
| 285 | pinctrl_fec_2: fecgrp-2 { | 315 | pinctrl_fec_2: fecgrp-2 { |
| 286 | fsl,pins = < | 316 | fsl,pins = < |
| 287 | 589 0x80000000 /* MX51_PAD_DI_GP3__FEC_TX_ER */ | 317 | MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 |
| 288 | 592 0x80000000 /* MX51_PAD_DI2_PIN4__FEC_CRS */ | 318 | MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 |
| 289 | 594 0x80000000 /* MX51_PAD_DI2_PIN2__FEC_MDC */ | 319 | MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 |
| 290 | 596 0x80000000 /* MX51_PAD_DI2_PIN3__FEC_MDIO */ | 320 | MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 |
| 291 | 598 0x80000000 /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */ | 321 | MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 |
| 292 | 602 0x80000000 /* MX51_PAD_DI_GP4__FEC_RDATA2 */ | 322 | MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 |
| 293 | 604 0x80000000 /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */ | 323 | MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 |
| 294 | 609 0x80000000 /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */ | 324 | MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 |
| 295 | 618 0x80000000 /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */ | 325 | MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 |
| 296 | 623 0x80000000 /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */ | 326 | MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 |
| 297 | 628 0x80000000 /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */ | 327 | MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 |
| 298 | 634 0x80000000 /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */ | 328 | MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 |
| 299 | 639 0x80000000 /* MX51_PAD_DISP2_DAT10__FEC_COL */ | 329 | MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 |
| 300 | 644 0x80000000 /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */ | 330 | MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 |
| 301 | 649 0x80000000 /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */ | 331 | MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 |
| 302 | 653 0x80000000 /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */ | 332 | MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 |
| 303 | 657 0x80000000 /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */ | 333 | MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 |
| 304 | 662 0x80000000 /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */ | 334 | MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 |
| 305 | >; | 335 | >; |
| 306 | }; | 336 | }; |
| 307 | }; | 337 | }; |
| @@ -309,9 +339,19 @@ | |||
| 309 | ecspi1 { | 339 | ecspi1 { |
| 310 | pinctrl_ecspi1_1: ecspi1grp-1 { | 340 | pinctrl_ecspi1_1: ecspi1grp-1 { |
| 311 | fsl,pins = < | 341 | fsl,pins = < |
| 312 | 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */ | 342 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 |
| 313 | 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */ | 343 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 |
| 314 | 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */ | 344 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 |
| 345 | >; | ||
| 346 | }; | ||
| 347 | }; | ||
| 348 | |||
| 349 | ecspi2 { | ||
| 350 | pinctrl_ecspi2_1: ecspi2grp-1 { | ||
| 351 | fsl,pins = < | ||
| 352 | MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 | ||
| 353 | MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 | ||
| 354 | MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 | ||
| 315 | >; | 355 | >; |
| 316 | }; | 356 | }; |
| 317 | }; | 357 | }; |
| @@ -319,12 +359,12 @@ | |||
| 319 | esdhc1 { | 359 | esdhc1 { |
| 320 | pinctrl_esdhc1_1: esdhc1grp-1 { | 360 | pinctrl_esdhc1_1: esdhc1grp-1 { |
| 321 | fsl,pins = < | 361 | fsl,pins = < |
| 322 | 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */ | 362 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 |
| 323 | 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */ | 363 | MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 |
| 324 | 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */ | 364 | MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 |
| 325 | 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */ | 365 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 |
| 326 | 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */ | 366 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 |
| 327 | 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */ | 367 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 |
| 328 | >; | 368 | >; |
| 329 | }; | 369 | }; |
| 330 | }; | 370 | }; |
| @@ -332,12 +372,12 @@ | |||
| 332 | esdhc2 { | 372 | esdhc2 { |
| 333 | pinctrl_esdhc2_1: esdhc2grp-1 { | 373 | pinctrl_esdhc2_1: esdhc2grp-1 { |
| 334 | fsl,pins = < | 374 | fsl,pins = < |
| 335 | 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */ | 375 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 |
| 336 | 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */ | 376 | MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 |
| 337 | 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */ | 377 | MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 |
| 338 | 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */ | 378 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 |
| 339 | 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */ | 379 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 |
| 340 | 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */ | 380 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 |
| 341 | >; | 381 | >; |
| 342 | }; | 382 | }; |
| 343 | }; | 383 | }; |
| @@ -345,8 +385,15 @@ | |||
| 345 | i2c2 { | 385 | i2c2 { |
| 346 | pinctrl_i2c2_1: i2c2grp-1 { | 386 | pinctrl_i2c2_1: i2c2grp-1 { |
| 347 | fsl,pins = < | 387 | fsl,pins = < |
| 348 | 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */ | 388 | MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed |
| 349 | 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */ | 389 | MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed |
| 390 | >; | ||
| 391 | }; | ||
| 392 | |||
| 393 | pinctrl_i2c2_2: i2c2grp-2 { | ||
| 394 | fsl,pins = < | ||
| 395 | MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed | ||
| 396 | MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed | ||
| 350 | >; | 397 | >; |
| 351 | }; | 398 | }; |
| 352 | }; | 399 | }; |
| @@ -354,32 +401,32 @@ | |||
| 354 | ipu_disp1 { | 401 | ipu_disp1 { |
| 355 | pinctrl_ipu_disp1_1: ipudisp1grp-1 { | 402 | pinctrl_ipu_disp1_1: ipudisp1grp-1 { |
| 356 | fsl,pins = < | 403 | fsl,pins = < |
| 357 | 528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */ | 404 | MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 |
| 358 | 529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */ | 405 | MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 |
| 359 | 530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */ | 406 | MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 |
| 360 | 531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */ | 407 | MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 |
| 361 | 532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */ | 408 | MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 |
| 362 | 533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */ | 409 | MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 |
| 363 | 535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */ | 410 | MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 |
| 364 | 537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */ | 411 | MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 |
| 365 | 539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */ | 412 | MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 |
| 366 | 541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */ | 413 | MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 |
| 367 | 543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */ | 414 | MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 |
| 368 | 545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */ | 415 | MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 |
| 369 | 547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */ | 416 | MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 |
| 370 | 549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */ | 417 | MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 |
| 371 | 551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */ | 418 | MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 |
| 372 | 553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */ | 419 | MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 |
| 373 | 555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */ | 420 | MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 |
| 374 | 557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */ | 421 | MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 |
| 375 | 559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */ | 422 | MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 |
| 376 | 563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */ | 423 | MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 |
| 377 | 567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */ | 424 | MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 |
| 378 | 571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */ | 425 | MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 |
| 379 | 575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */ | 426 | MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 |
| 380 | 579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */ | 427 | MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 |
| 381 | 584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */ | 428 | MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */ |
| 382 | 583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */ | 429 | MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */ |
| 383 | >; | 430 | >; |
| 384 | }; | 431 | }; |
| 385 | }; | 432 | }; |
| @@ -387,26 +434,62 @@ | |||
| 387 | ipu_disp2 { | 434 | ipu_disp2 { |
| 388 | pinctrl_ipu_disp2_1: ipudisp2grp-1 { | 435 | pinctrl_ipu_disp2_1: ipudisp2grp-1 { |
| 389 | fsl,pins = < | 436 | fsl,pins = < |
| 390 | 603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */ | 437 | MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 |
| 391 | 608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */ | 438 | MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 |
| 392 | 613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */ | 439 | MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 |
| 393 | 614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */ | 440 | MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 |
| 394 | 615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */ | 441 | MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 |
| 395 | 616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */ | 442 | MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 |
| 396 | 617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */ | 443 | MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 |
| 397 | 622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */ | 444 | MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 |
| 398 | 627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */ | 445 | MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 |
| 399 | 633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */ | 446 | MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 |
| 400 | 637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */ | 447 | MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 |
| 401 | 643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */ | 448 | MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 |
| 402 | 648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */ | 449 | MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 |
| 403 | 652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */ | 450 | MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 |
| 404 | 656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */ | 451 | MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 |
| 405 | 661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */ | 452 | MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 |
| 406 | 593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */ | 453 | MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */ |
| 407 | 595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */ | 454 | MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */ |
| 408 | 597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */ | 455 | MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 |
| 409 | 599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */ | 456 | MX51_PAD_DI_GP4__DI2_PIN15 0x5 |
| 457 | >; | ||
| 458 | }; | ||
| 459 | }; | ||
| 460 | |||
| 461 | pata { | ||
| 462 | pinctrl_pata_1: patagrp-1 { | ||
| 463 | fsl,pins = < | ||
| 464 | MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004 | ||
| 465 | MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004 | ||
| 466 | MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004 | ||
| 467 | MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004 | ||
| 468 | MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004 | ||
| 469 | MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004 | ||
| 470 | MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004 | ||
| 471 | MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004 | ||
| 472 | MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004 | ||
| 473 | MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004 | ||
| 474 | MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004 | ||
| 475 | MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004 | ||
| 476 | MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004 | ||
| 477 | MX51_PAD_NANDF_D15__PATA_DATA15 0x2004 | ||
| 478 | MX51_PAD_NANDF_D14__PATA_DATA14 0x2004 | ||
| 479 | MX51_PAD_NANDF_D13__PATA_DATA13 0x2004 | ||
| 480 | MX51_PAD_NANDF_D12__PATA_DATA12 0x2004 | ||
| 481 | MX51_PAD_NANDF_D11__PATA_DATA11 0x2004 | ||
| 482 | MX51_PAD_NANDF_D10__PATA_DATA10 0x2004 | ||
| 483 | MX51_PAD_NANDF_D9__PATA_DATA9 0x2004 | ||
| 484 | MX51_PAD_NANDF_D8__PATA_DATA8 0x2004 | ||
| 485 | MX51_PAD_NANDF_D7__PATA_DATA7 0x2004 | ||
| 486 | MX51_PAD_NANDF_D6__PATA_DATA6 0x2004 | ||
| 487 | MX51_PAD_NANDF_D5__PATA_DATA5 0x2004 | ||
| 488 | MX51_PAD_NANDF_D4__PATA_DATA4 0x2004 | ||
| 489 | MX51_PAD_NANDF_D3__PATA_DATA3 0x2004 | ||
| 490 | MX51_PAD_NANDF_D2__PATA_DATA2 0x2004 | ||
| 491 | MX51_PAD_NANDF_D1__PATA_DATA1 0x2004 | ||
| 492 | MX51_PAD_NANDF_D0__PATA_DATA0 0x2004 | ||
| 410 | >; | 493 | >; |
| 411 | }; | 494 | }; |
| 412 | }; | 495 | }; |
| @@ -414,10 +497,10 @@ | |||
| 414 | uart1 { | 497 | uart1 { |
| 415 | pinctrl_uart1_1: uart1grp-1 { | 498 | pinctrl_uart1_1: uart1grp-1 { |
| 416 | fsl,pins = < | 499 | fsl,pins = < |
| 417 | 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */ | 500 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 |
| 418 | 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */ | 501 | MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 |
| 419 | 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */ | 502 | MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 |
| 420 | 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */ | 503 | MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 |
| 421 | >; | 504 | >; |
| 422 | }; | 505 | }; |
| 423 | }; | 506 | }; |
| @@ -425,8 +508,8 @@ | |||
| 425 | uart2 { | 508 | uart2 { |
| 426 | pinctrl_uart2_1: uart2grp-1 { | 509 | pinctrl_uart2_1: uart2grp-1 { |
| 427 | fsl,pins = < | 510 | fsl,pins = < |
| 428 | 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */ | 511 | MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 |
| 429 | 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */ | 512 | MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 |
| 430 | >; | 513 | >; |
| 431 | }; | 514 | }; |
| 432 | }; | 515 | }; |
| @@ -434,17 +517,17 @@ | |||
| 434 | uart3 { | 517 | uart3 { |
| 435 | pinctrl_uart3_1: uart3grp-1 { | 518 | pinctrl_uart3_1: uart3grp-1 { |
| 436 | fsl,pins = < | 519 | fsl,pins = < |
| 437 | 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */ | 520 | MX51_PAD_EIM_D25__UART3_RXD 0x1c5 |
| 438 | 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */ | 521 | MX51_PAD_EIM_D26__UART3_TXD 0x1c5 |
| 439 | 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */ | 522 | MX51_PAD_EIM_D27__UART3_RTS 0x1c5 |
| 440 | 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */ | 523 | MX51_PAD_EIM_D24__UART3_CTS 0x1c5 |
| 441 | >; | 524 | >; |
| 442 | }; | 525 | }; |
| 443 | 526 | ||
| 444 | pinctrl_uart3_2: uart3grp-2 { | 527 | pinctrl_uart3_2: uart3grp-2 { |
| 445 | fsl,pins = < | 528 | fsl,pins = < |
| 446 | 434 0x1c5 /* MX51_PAD_UART3_RXD__UART3_RXD */ | 529 | MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 |
| 447 | 430 0x1c5 /* MX51_PAD_UART3_TXD__UART3_TXD */ | 530 | MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 |
| 448 | >; | 531 | >; |
| 449 | }; | 532 | }; |
| 450 | }; | 533 | }; |
| @@ -452,14 +535,14 @@ | |||
| 452 | kpp { | 535 | kpp { |
| 453 | pinctrl_kpp_1: kppgrp-1 { | 536 | pinctrl_kpp_1: kppgrp-1 { |
| 454 | fsl,pins = < | 537 | fsl,pins = < |
| 455 | 438 0xe0 /* MX51_PAD_KEY_ROW0__KEY_ROW0 */ | 538 | MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 |
| 456 | 439 0xe0 /* MX51_PAD_KEY_ROW1__KEY_ROW1 */ | 539 | MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 |
| 457 | 440 0xe0 /* MX51_PAD_KEY_ROW2__KEY_ROW2 */ | 540 | MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 |
| 458 | 441 0xe0 /* MX51_PAD_KEY_ROW3__KEY_ROW3 */ | 541 | MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 |
| 459 | 442 0xe8 /* MX51_PAD_KEY_COL0__KEY_COL0 */ | 542 | MX51_PAD_KEY_COL0__KEY_COL0 0xe8 |
| 460 | 444 0xe8 /* MX51_PAD_KEY_COL1__KEY_COL1 */ | 543 | MX51_PAD_KEY_COL1__KEY_COL1 0xe8 |
| 461 | 446 0xe8 /* MX51_PAD_KEY_COL2__KEY_COL2 */ | 544 | MX51_PAD_KEY_COL2__KEY_COL2 0xe8 |
| 462 | 448 0xe8 /* MX51_PAD_KEY_COL3__KEY_COL3 */ | 545 | MX51_PAD_KEY_COL3__KEY_COL3 0xe8 |
| 463 | >; | 546 | >; |
| 464 | }; | 547 | }; |
| 465 | }; | 548 | }; |
| @@ -501,6 +584,12 @@ | |||
| 501 | status = "disabled"; | 584 | status = "disabled"; |
| 502 | }; | 585 | }; |
| 503 | 586 | ||
| 587 | src: src@73fd0000 { | ||
| 588 | compatible = "fsl,imx51-src"; | ||
| 589 | reg = <0x73fd0000 0x4000>; | ||
| 590 | #reset-cells = <1>; | ||
| 591 | }; | ||
| 592 | |||
| 504 | clks: ccm@73fd4000{ | 593 | clks: ccm@73fd4000{ |
| 505 | compatible = "fsl,imx51-ccm"; | 594 | compatible = "fsl,imx51-ccm"; |
| 506 | reg = <0x73fd4000 0x4000>; | 595 | reg = <0x73fd4000 0x4000>; |
| @@ -591,6 +680,14 @@ | |||
| 591 | status = "disabled"; | 680 | status = "disabled"; |
| 592 | }; | 681 | }; |
| 593 | 682 | ||
| 683 | pata: pata@83fe0000 { | ||
| 684 | compatible = "fsl,imx51-pata", "fsl,imx27-pata"; | ||
| 685 | reg = <0x83fe0000 0x4000>; | ||
| 686 | interrupts = <70>; | ||
| 687 | clocks = <&clks 161>; | ||
| 688 | status = "disabled"; | ||
| 689 | }; | ||
| 690 | |||
| 594 | ssi3: ssi@83fe8000 { | 691 | ssi3: ssi@83fe8000 { |
| 595 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; | 692 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; |
| 596 | reg = <0x83fe8000 0x4000>; | 693 | reg = <0x83fe8000 0x4000>; |
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts index e049fd0319e8..174f86938c89 100644 --- a/arch/arm/boot/dts/imx53-ard.dts +++ b/arch/arm/boot/dts/imx53-ard.dts | |||
| @@ -11,7 +11,7 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /dts-v1/; | 13 | /dts-v1/; |
| 14 | /include/ "imx53.dtsi" | 14 | #include "imx53.dtsi" |
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | model = "Freescale i.MX53 Automotive Reference Design Board"; | 17 | model = "Freescale i.MX53 Automotive Reference Design Board"; |
| @@ -112,40 +112,40 @@ | |||
| 112 | hog { | 112 | hog { |
| 113 | pinctrl_hog: hoggrp { | 113 | pinctrl_hog: hoggrp { |
| 114 | fsl,pins = < | 114 | fsl,pins = < |
| 115 | 1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */ | 115 | MX53_PAD_GPIO_1__GPIO1_1 0x80000000 |
| 116 | 1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */ | 116 | MX53_PAD_GPIO_9__GPIO1_9 0x80000000 |
| 117 | 486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */ | 117 | MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 |
| 118 | 739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */ | 118 | MX53_PAD_GPIO_10__GPIO4_0 0x80000000 |
| 119 | 218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */ | 119 | MX53_PAD_DISP0_DAT16__GPIO5_10 0x80000000 |
| 120 | 226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */ | 120 | MX53_PAD_DISP0_DAT17__GPIO5_11 0x80000000 |
| 121 | 233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */ | 121 | MX53_PAD_DISP0_DAT18__GPIO5_12 0x80000000 |
| 122 | 241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */ | 122 | MX53_PAD_DISP0_DAT19__GPIO5_13 0x80000000 |
| 123 | 429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */ | 123 | MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x80000000 |
| 124 | 435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */ | 124 | MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x80000000 |
| 125 | 441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */ | 125 | MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x80000000 |
| 126 | 448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */ | 126 | MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x80000000 |
| 127 | 456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */ | 127 | MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x80000000 |
| 128 | 464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */ | 128 | MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x80000000 |
| 129 | 471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */ | 129 | MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x80000000 |
| 130 | 477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */ | 130 | MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x80000000 |
| 131 | 492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */ | 131 | MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x80000000 |
| 132 | 500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */ | 132 | MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x80000000 |
| 133 | 508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */ | 133 | MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x80000000 |
| 134 | 516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */ | 134 | MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x80000000 |
| 135 | 524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */ | 135 | MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x80000000 |
| 136 | 532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */ | 136 | MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x80000000 |
| 137 | 540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */ | 137 | MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x80000000 |
| 138 | 548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */ | 138 | MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x80000000 |
| 139 | 637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */ | 139 | MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x80000000 |
| 140 | 642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */ | 140 | MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x80000000 |
| 141 | 647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */ | 141 | MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x80000000 |
| 142 | 652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */ | 142 | MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x80000000 |
| 143 | 657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */ | 143 | MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x80000000 |
| 144 | 662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */ | 144 | MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x80000000 |
| 145 | 667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */ | 145 | MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x80000000 |
| 146 | 611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */ | 146 | MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000 |
| 147 | 616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */ | 147 | MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000 |
| 148 | 607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */ | 148 | MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 |
| 149 | >; | 149 | >; |
| 150 | }; | 150 | }; |
| 151 | }; | 151 | }; |
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts index 85a89b52f9b8..801fda728ed6 100644 --- a/arch/arm/boot/dts/imx53-evk.dts +++ b/arch/arm/boot/dts/imx53-evk.dts | |||
| @@ -11,7 +11,7 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /dts-v1/; | 13 | /dts-v1/; |
| 14 | /include/ "imx53.dtsi" | 14 | #include "imx53.dtsi" |
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | model = "Freescale i.MX53 Evaluation Kit"; | 17 | model = "Freescale i.MX53 Evaluation Kit"; |
| @@ -82,14 +82,14 @@ | |||
| 82 | hog { | 82 | hog { |
| 83 | pinctrl_hog: hoggrp { | 83 | pinctrl_hog: hoggrp { |
| 84 | fsl,pins = < | 84 | fsl,pins = < |
| 85 | 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */ | 85 | MX53_PAD_EIM_EB2__GPIO2_30 0x80000000 |
| 86 | 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */ | 86 | MX53_PAD_EIM_D19__GPIO3_19 0x80000000 |
| 87 | 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */ | 87 | MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 |
| 88 | 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ | 88 | MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 |
| 89 | 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ | 89 | MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 |
| 90 | 705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */ | 90 | MX53_PAD_EIM_DA14__GPIO3_14 0x80000000 |
| 91 | 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ | 91 | MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 |
| 92 | 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ | 92 | MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 |
| 93 | >; | 93 | >; |
| 94 | }; | 94 | }; |
| 95 | }; | 95 | }; |
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts index 468c0a1d48d9..445a01119cc5 100644 --- a/arch/arm/boot/dts/imx53-mba53.dts +++ b/arch/arm/boot/dts/imx53-mba53.dts | |||
| @@ -11,7 +11,7 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /dts-v1/; | 13 | /dts-v1/; |
| 14 | /include/ "imx53-tqma53.dtsi" | 14 | #include "imx53-tqma53.dtsi" |
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | model = "TQ MBa53 starter kit"; | 17 | model = "TQ MBa53 starter kit"; |
| @@ -21,51 +21,57 @@ | |||
| 21 | &iomuxc { | 21 | &iomuxc { |
| 22 | lvds1 { | 22 | lvds1 { |
| 23 | pinctrl_lvds1_1: lvds1-grp1 { | 23 | pinctrl_lvds1_1: lvds1-grp1 { |
| 24 | fsl,pins = <730 0x10000 /* LVDS0_TX3 */ | 24 | fsl,pins = < |
| 25 | 732 0x10000 /* LVDS0_CLK */ | 25 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000 |
| 26 | 734 0x10000 /* LVDS0_TX2 */ | 26 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000 |
| 27 | 736 0x10000 /* LVDS0_TX1 */ | 27 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000 |
| 28 | 738 0x10000>; /* LVDS0_TX0 */ | 28 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000 |
| 29 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000 | ||
| 30 | >; | ||
| 29 | }; | 31 | }; |
| 30 | 32 | ||
| 31 | pinctrl_lvds1_2: lvds1-grp2 { | 33 | pinctrl_lvds1_2: lvds1-grp2 { |
| 32 | fsl,pins = <720 0x10000 /* LVDS1_TX3 */ | 34 | fsl,pins = < |
| 33 | 722 0x10000 /* LVDS1_TX2 */ | 35 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000 |
| 34 | 724 0x10000 /* LVDS1_CLK */ | 36 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000 |
| 35 | 726 0x10000 /* LVDS1_TX1 */ | 37 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000 |
| 36 | 728 0x10000>; /* LVDS1_TX0 */ | 38 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000 |
| 39 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000 | ||
| 40 | >; | ||
| 37 | }; | 41 | }; |
| 38 | }; | 42 | }; |
| 39 | 43 | ||
| 40 | disp1 { | 44 | disp1 { |
| 41 | pinctrl_disp1_1: disp1-grp1 { | 45 | pinctrl_disp1_1: disp1-grp1 { |
| 42 | fsl,pins = <689 0x10000 /* DISP1_DRDY */ | 46 | fsl,pins = < |
| 43 | 482 0x10000 /* DISP1_HSYNC */ | 47 | MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x10000 /* DISP1_DRDY */ |
| 44 | 489 0x10000 /* DISP1_VSYNC */ | 48 | MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x10000 /* DISP1_HSYNC */ |
| 45 | 515 0x10000 /* DISP1_DAT_22 */ | 49 | MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x10000 /* DISP1_VSYNC */ |
| 46 | 523 0x10000 /* DISP1_DAT_23 */ | 50 | MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000 |
| 47 | 545 0x10000 /* DISP1_DAT_21 */ | 51 | MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000 |
| 48 | 553 0x10000 /* DISP1_DAT_20 */ | 52 | MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000 |
| 49 | 558 0x10000 /* DISP1_DAT_19 */ | 53 | MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000 |
| 50 | 564 0x10000 /* DISP1_DAT_18 */ | 54 | MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000 |
| 51 | 570 0x10000 /* DISP1_DAT_17 */ | 55 | MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000 |
| 52 | 575 0x10000 /* DISP1_DAT_16 */ | 56 | MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000 |
| 53 | 580 0x10000 /* DISP1_DAT_15 */ | 57 | MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000 |
| 54 | 585 0x10000 /* DISP1_DAT_14 */ | 58 | MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000 |
| 55 | 590 0x10000 /* DISP1_DAT_13 */ | 59 | MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000 |
| 56 | 595 0x10000 /* DISP1_DAT_12 */ | 60 | MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000 |
| 57 | 628 0x10000 /* DISP1_DAT_11 */ | 61 | MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000 |
| 58 | 634 0x10000 /* DISP1_DAT_10 */ | 62 | MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000 |
| 59 | 639 0x10000 /* DISP1_DAT_9 */ | 63 | MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000 |
| 60 | 644 0x10000 /* DISP1_DAT_8 */ | 64 | MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x10000 |
| 61 | 649 0x10000 /* DISP1_DAT_7 */ | 65 | MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x10000 |
| 62 | 654 0x10000 /* DISP1_DAT_6 */ | 66 | MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x10000 |
| 63 | 659 0x10000 /* DISP1_DAT_5 */ | 67 | MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x10000 |
| 64 | 664 0x10000 /* DISP1_DAT_4 */ | 68 | MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x10000 |
| 65 | 669 0x10000 /* DISP1_DAT_3 */ | 69 | MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x10000 |
| 66 | 674 0x10000 /* DISP1_DAT_2 */ | 70 | MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x10000 |
| 67 | 679 0x10000 /* DISP1_DAT_1 */ | 71 | MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x10000 |
| 68 | 684 0x10000>; /* DISP1_DAT_0 */ | 72 | MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x10000 |
| 73 | MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x10000 | ||
| 74 | >; | ||
| 69 | }; | 75 | }; |
| 70 | }; | 76 | }; |
| 71 | }; | 77 | }; |
diff --git a/arch/arm/boot/dts/imx53-pinfunc.h b/arch/arm/boot/dts/imx53-pinfunc.h new file mode 100644 index 000000000000..aec406bc65eb --- /dev/null +++ b/arch/arm/boot/dts/imx53-pinfunc.h | |||
| @@ -0,0 +1,1189 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __DTS_IMX53_PINFUNC_H | ||
| 11 | #define __DTS_IMX53_PINFUNC_H | ||
| 12 | |||
| 13 | /* | ||
| 14 | * The pin function ID is a tuple of | ||
| 15 | * <mux_reg conf_reg input_reg mux_mode input_val> | ||
| 16 | */ | ||
| 17 | #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0 | ||
| 18 | #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0 | ||
| 19 | #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0 | ||
| 20 | #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 | ||
| 21 | #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0 | ||
| 22 | #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 | ||
| 23 | #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0 | ||
| 24 | #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0 | ||
| 25 | #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0 | ||
| 26 | #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0 | ||
| 27 | #define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x024 0x34c 0x758 0x2 0x0 | ||
| 28 | #define MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x024 0x34c 0x000 0x4 0x0 | ||
| 29 | #define MX53_PAD_KEY_COL0__ECSPI1_SCLK 0x024 0x34c 0x79c 0x5 0x0 | ||
| 30 | #define MX53_PAD_KEY_COL0__FEC_RDATA_3 0x024 0x34c 0x000 0x6 0x0 | ||
| 31 | #define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 0x024 0x34c 0x000 0x7 0x0 | ||
| 32 | #define MX53_PAD_KEY_ROW0__KPP_ROW_0 0x028 0x350 0x000 0x0 0x0 | ||
| 33 | #define MX53_PAD_KEY_ROW0__GPIO4_7 0x028 0x350 0x000 0x1 0x0 | ||
| 34 | #define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x028 0x350 0x74c 0x2 0x0 | ||
| 35 | #define MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x028 0x350 0x890 0x4 0x1 | ||
| 36 | #define MX53_PAD_KEY_ROW0__ECSPI1_MOSI 0x028 0x350 0x7a4 0x5 0x0 | ||
| 37 | #define MX53_PAD_KEY_ROW0__FEC_TX_ER 0x028 0x350 0x000 0x6 0x0 | ||
| 38 | #define MX53_PAD_KEY_COL1__KPP_COL_1 0x02c 0x354 0x000 0x0 0x0 | ||
| 39 | #define MX53_PAD_KEY_COL1__GPIO4_8 0x02c 0x354 0x000 0x1 0x0 | ||
| 40 | #define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x02c 0x354 0x75c 0x2 0x0 | ||
| 41 | #define MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x02c 0x354 0x000 0x4 0x0 | ||
| 42 | #define MX53_PAD_KEY_COL1__ECSPI1_MISO 0x02c 0x354 0x7a0 0x5 0x0 | ||
| 43 | #define MX53_PAD_KEY_COL1__FEC_RX_CLK 0x02c 0x354 0x808 0x6 0x0 | ||
| 44 | #define MX53_PAD_KEY_COL1__USBPHY1_TXREADY 0x02c 0x354 0x000 0x7 0x0 | ||
| 45 | #define MX53_PAD_KEY_ROW1__KPP_ROW_1 0x030 0x358 0x000 0x0 0x0 | ||
| 46 | #define MX53_PAD_KEY_ROW1__GPIO4_9 0x030 0x358 0x000 0x1 0x0 | ||
| 47 | #define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x030 0x358 0x748 0x2 0x0 | ||
| 48 | #define MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x030 0x358 0x898 0x4 0x1 | ||
| 49 | #define MX53_PAD_KEY_ROW1__ECSPI1_SS0 0x030 0x358 0x7a8 0x5 0x0 | ||
| 50 | #define MX53_PAD_KEY_ROW1__FEC_COL 0x030 0x358 0x800 0x6 0x0 | ||
| 51 | #define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 0x030 0x358 0x000 0x7 0x0 | ||
| 52 | #define MX53_PAD_KEY_COL2__KPP_COL_2 0x034 0x35c 0x000 0x0 0x0 | ||
| 53 | #define MX53_PAD_KEY_COL2__GPIO4_10 0x034 0x35c 0x000 0x1 0x0 | ||
| 54 | #define MX53_PAD_KEY_COL2__CAN1_TXCAN 0x034 0x35c 0x000 0x2 0x0 | ||
| 55 | #define MX53_PAD_KEY_COL2__FEC_MDIO 0x034 0x35c 0x804 0x4 0x0 | ||
| 56 | #define MX53_PAD_KEY_COL2__ECSPI1_SS1 0x034 0x35c 0x7ac 0x5 0x0 | ||
| 57 | #define MX53_PAD_KEY_COL2__FEC_RDATA_2 0x034 0x35c 0x000 0x6 0x0 | ||
| 58 | #define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 0x034 0x35c 0x000 0x7 0x0 | ||
| 59 | #define MX53_PAD_KEY_ROW2__KPP_ROW_2 0x038 0x360 0x000 0x0 0x0 | ||
| 60 | #define MX53_PAD_KEY_ROW2__GPIO4_11 0x038 0x360 0x000 0x1 0x0 | ||
| 61 | #define MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x038 0x360 0x760 0x2 0x0 | ||
| 62 | #define MX53_PAD_KEY_ROW2__FEC_MDC 0x038 0x360 0x000 0x4 0x0 | ||
| 63 | #define MX53_PAD_KEY_ROW2__ECSPI1_SS2 0x038 0x360 0x7b0 0x5 0x0 | ||
| 64 | #define MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x038 0x360 0x000 0x6 0x0 | ||
| 65 | #define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 0x038 0x360 0x000 0x7 0x0 | ||
| 66 | #define MX53_PAD_KEY_COL3__KPP_COL_3 0x03c 0x364 0x000 0x0 0x0 | ||
| 67 | #define MX53_PAD_KEY_COL3__GPIO4_12 0x03c 0x364 0x000 0x1 0x0 | ||
| 68 | #define MX53_PAD_KEY_COL3__USBOH3_H2_DP 0x03c 0x364 0x000 0x2 0x0 | ||
| 69 | #define MX53_PAD_KEY_COL3__SPDIF_IN1 0x03c 0x364 0x870 0x3 0x0 | ||
| 70 | #define MX53_PAD_KEY_COL3__I2C2_SCL 0x03c 0x364 0x81c 0x4 0x0 | ||
| 71 | #define MX53_PAD_KEY_COL3__ECSPI1_SS3 0x03c 0x364 0x7b4 0x5 0x0 | ||
| 72 | #define MX53_PAD_KEY_COL3__FEC_CRS 0x03c 0x364 0x000 0x6 0x0 | ||
| 73 | #define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 0x03c 0x364 0x000 0x7 0x0 | ||
| 74 | #define MX53_PAD_KEY_ROW3__KPP_ROW_3 0x040 0x368 0x000 0x0 0x0 | ||
| 75 | #define MX53_PAD_KEY_ROW3__GPIO4_13 0x040 0x368 0x000 0x1 0x0 | ||
| 76 | #define MX53_PAD_KEY_ROW3__USBOH3_H2_DM 0x040 0x368 0x000 0x2 0x0 | ||
| 77 | #define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 0x040 0x368 0x768 0x3 0x0 | ||
| 78 | #define MX53_PAD_KEY_ROW3__I2C2_SDA 0x040 0x368 0x820 0x4 0x0 | ||
| 79 | #define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 0x040 0x368 0x000 0x5 0x0 | ||
| 80 | #define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 0x040 0x368 0x77c 0x6 0x0 | ||
| 81 | #define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 0x040 0x368 0x000 0x7 0x0 | ||
| 82 | #define MX53_PAD_KEY_COL4__KPP_COL_4 0x044 0x36c 0x000 0x0 0x0 | ||
| 83 | #define MX53_PAD_KEY_COL4__GPIO4_14 0x044 0x36c 0x000 0x1 0x0 | ||
| 84 | #define MX53_PAD_KEY_COL4__CAN2_TXCAN 0x044 0x36c 0x000 0x2 0x0 | ||
| 85 | #define MX53_PAD_KEY_COL4__IPU_SISG_4 0x044 0x36c 0x000 0x3 0x0 | ||
| 86 | #define MX53_PAD_KEY_COL4__UART5_RTS 0x044 0x36c 0x894 0x4 0x0 | ||
| 87 | #define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x044 0x36c 0x89c 0x5 0x0 | ||
| 88 | #define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 0x044 0x36c 0x000 0x7 0x0 | ||
| 89 | #define MX53_PAD_KEY_ROW4__KPP_ROW_4 0x048 0x370 0x000 0x0 0x0 | ||
| 90 | #define MX53_PAD_KEY_ROW4__GPIO4_15 0x048 0x370 0x000 0x1 0x0 | ||
| 91 | #define MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x048 0x370 0x764 0x2 0x0 | ||
| 92 | #define MX53_PAD_KEY_ROW4__IPU_SISG_5 0x048 0x370 0x000 0x3 0x0 | ||
| 93 | #define MX53_PAD_KEY_ROW4__UART5_CTS 0x048 0x370 0x000 0x4 0x0 | ||
| 94 | #define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 0x048 0x370 0x000 0x5 0x0 | ||
| 95 | #define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 0x048 0x370 0x000 0x7 0x0 | ||
| 96 | #define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x04c 0x378 0x000 0x0 0x0 | ||
| 97 | #define MX53_PAD_DI0_DISP_CLK__GPIO4_16 0x04c 0x378 0x000 0x1 0x0 | ||
| 98 | #define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x04c 0x378 0x000 0x2 0x0 | ||
| 99 | #define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 0x04c 0x378 0x000 0x5 0x0 | ||
| 100 | #define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 0x04c 0x378 0x000 0x6 0x0 | ||
| 101 | #define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 0x04c 0x378 0x000 0x7 0x0 | ||
| 102 | #define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x050 0x37c 0x000 0x0 0x0 | ||
| 103 | #define MX53_PAD_DI0_PIN15__GPIO4_17 0x050 0x37c 0x000 0x1 0x0 | ||
| 104 | #define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x050 0x37c 0x000 0x2 0x0 | ||
| 105 | #define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 0x050 0x37c 0x000 0x5 0x0 | ||
| 106 | #define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 0x050 0x37c 0x000 0x6 0x0 | ||
| 107 | #define MX53_PAD_DI0_PIN15__USBPHY1_BVALID 0x050 0x37c 0x000 0x7 0x0 | ||
| 108 | #define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x054 0x380 0x000 0x0 0x0 | ||
| 109 | #define MX53_PAD_DI0_PIN2__GPIO4_18 0x054 0x380 0x000 0x1 0x0 | ||
| 110 | #define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x054 0x380 0x000 0x2 0x0 | ||
| 111 | #define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 0x054 0x380 0x000 0x5 0x0 | ||
| 112 | #define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 0x054 0x380 0x000 0x6 0x0 | ||
| 113 | #define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 0x054 0x380 0x000 0x7 0x0 | ||
| 114 | #define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x058 0x384 0x000 0x0 0x0 | ||
| 115 | #define MX53_PAD_DI0_PIN3__GPIO4_19 0x058 0x384 0x000 0x1 0x0 | ||
| 116 | #define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x058 0x384 0x000 0x2 0x0 | ||
| 117 | #define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 0x058 0x384 0x000 0x5 0x0 | ||
| 118 | #define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 0x058 0x384 0x000 0x6 0x0 | ||
| 119 | #define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 0x058 0x384 0x000 0x7 0x0 | ||
| 120 | #define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x05c 0x388 0x000 0x0 0x0 | ||
| 121 | #define MX53_PAD_DI0_PIN4__GPIO4_20 0x05c 0x388 0x000 0x1 0x0 | ||
| 122 | #define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x05c 0x388 0x000 0x2 0x0 | ||
| 123 | #define MX53_PAD_DI0_PIN4__ESDHC1_WP 0x05c 0x388 0x7fc 0x3 0x0 | ||
| 124 | #define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 0x05c 0x388 0x000 0x5 0x0 | ||
| 125 | #define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 0x05c 0x388 0x000 0x6 0x0 | ||
| 126 | #define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 0x05c 0x388 0x000 0x7 0x0 | ||
| 127 | #define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x060 0x38c 0x000 0x0 0x0 | ||
| 128 | #define MX53_PAD_DISP0_DAT0__GPIO4_21 0x060 0x38c 0x000 0x1 0x0 | ||
| 129 | #define MX53_PAD_DISP0_DAT0__CSPI_SCLK 0x060 0x38c 0x780 0x2 0x0 | ||
| 130 | #define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x060 0x38c 0x000 0x3 0x0 | ||
| 131 | #define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 0x060 0x38c 0x000 0x5 0x0 | ||
| 132 | #define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 0x060 0x38c 0x000 0x6 0x0 | ||
| 133 | #define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 0x060 0x38c 0x000 0x7 0x0 | ||
| 134 | #define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x064 0x390 0x000 0x0 0x0 | ||
| 135 | #define MX53_PAD_DISP0_DAT1__GPIO4_22 0x064 0x390 0x000 0x1 0x0 | ||
| 136 | #define MX53_PAD_DISP0_DAT1__CSPI_MOSI 0x064 0x390 0x788 0x2 0x0 | ||
| 137 | #define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x064 0x390 0x000 0x3 0x0 | ||
| 138 | #define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x064 0x390 0x000 0x5 0x0 | ||
| 139 | #define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 0x064 0x390 0x000 0x6 0x0 | ||
| 140 | #define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 0x064 0x390 0x000 0x7 0x0 | ||
| 141 | #define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x068 0x394 0x000 0x0 0x0 | ||
| 142 | #define MX53_PAD_DISP0_DAT2__GPIO4_23 0x068 0x394 0x000 0x1 0x0 | ||
| 143 | #define MX53_PAD_DISP0_DAT2__CSPI_MISO 0x068 0x394 0x784 0x2 0x0 | ||
| 144 | #define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x068 0x394 0x000 0x3 0x0 | ||
| 145 | #define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 0x068 0x394 0x000 0x5 0x0 | ||
| 146 | #define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 0x068 0x394 0x000 0x6 0x0 | ||
| 147 | #define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 0x068 0x394 0x000 0x7 0x0 | ||
| 148 | #define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x06c 0x398 0x000 0x0 0x0 | ||
| 149 | #define MX53_PAD_DISP0_DAT3__GPIO4_24 0x06c 0x398 0x000 0x1 0x0 | ||
| 150 | #define MX53_PAD_DISP0_DAT3__CSPI_SS0 0x06c 0x398 0x78c 0x2 0x0 | ||
| 151 | #define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x06c 0x398 0x000 0x3 0x0 | ||
| 152 | #define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 0x06c 0x398 0x000 0x5 0x0 | ||
| 153 | #define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 0x06c 0x398 0x000 0x6 0x0 | ||
| 154 | #define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 0x06c 0x398 0x000 0x7 0x0 | ||
| 155 | #define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x070 0x39c 0x000 0x0 0x0 | ||
| 156 | #define MX53_PAD_DISP0_DAT4__GPIO4_25 0x070 0x39c 0x000 0x1 0x0 | ||
| 157 | #define MX53_PAD_DISP0_DAT4__CSPI_SS1 0x070 0x39c 0x790 0x2 0x0 | ||
| 158 | #define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x070 0x39c 0x000 0x3 0x0 | ||
| 159 | #define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 0x070 0x39c 0x000 0x5 0x0 | ||
| 160 | #define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 0x070 0x39c 0x000 0x6 0x0 | ||
| 161 | #define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 0x070 0x39c 0x000 0x7 0x0 | ||
| 162 | #define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x074 0x3a0 0x000 0x0 0x0 | ||
| 163 | #define MX53_PAD_DISP0_DAT5__GPIO4_26 0x074 0x3a0 0x000 0x1 0x0 | ||
| 164 | #define MX53_PAD_DISP0_DAT5__CSPI_SS2 0x074 0x3a0 0x794 0x2 0x0 | ||
| 165 | #define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x074 0x3a0 0x000 0x3 0x0 | ||
| 166 | #define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 0x074 0x3a0 0x000 0x5 0x0 | ||
| 167 | #define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 0x074 0x3a0 0x000 0x6 0x0 | ||
| 168 | #define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 0x074 0x3a0 0x000 0x7 0x0 | ||
| 169 | #define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x078 0x3a4 0x000 0x0 0x0 | ||
| 170 | #define MX53_PAD_DISP0_DAT6__GPIO4_27 0x078 0x3a4 0x000 0x1 0x0 | ||
| 171 | #define MX53_PAD_DISP0_DAT6__CSPI_SS3 0x078 0x3a4 0x798 0x2 0x0 | ||
| 172 | #define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x078 0x3a4 0x000 0x3 0x0 | ||
| 173 | #define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 0x078 0x3a4 0x000 0x5 0x0 | ||
| 174 | #define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 0x078 0x3a4 0x000 0x6 0x0 | ||
| 175 | #define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 0x078 0x3a4 0x000 0x7 0x0 | ||
| 176 | #define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x07c 0x3a8 0x000 0x0 0x0 | ||
| 177 | #define MX53_PAD_DISP0_DAT7__GPIO4_28 0x07c 0x3a8 0x000 0x1 0x0 | ||
| 178 | #define MX53_PAD_DISP0_DAT7__CSPI_RDY 0x07c 0x3a8 0x000 0x2 0x0 | ||
| 179 | #define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x07c 0x3a8 0x000 0x3 0x0 | ||
| 180 | #define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 0x07c 0x3a8 0x000 0x5 0x0 | ||
| 181 | #define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 0x07c 0x3a8 0x000 0x6 0x0 | ||
| 182 | #define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 0x07c 0x3a8 0x000 0x7 0x0 | ||
| 183 | #define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x080 0x3ac 0x000 0x0 0x0 | ||
| 184 | #define MX53_PAD_DISP0_DAT8__GPIO4_29 0x080 0x3ac 0x000 0x1 0x0 | ||
| 185 | #define MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x080 0x3ac 0x000 0x2 0x0 | ||
| 186 | #define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 0x080 0x3ac 0x000 0x3 0x0 | ||
| 187 | #define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 0x080 0x3ac 0x000 0x5 0x0 | ||
| 188 | #define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 0x080 0x3ac 0x000 0x6 0x0 | ||
| 189 | #define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 0x080 0x3ac 0x000 0x7 0x0 | ||
| 190 | #define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x084 0x3b0 0x000 0x0 0x0 | ||
| 191 | #define MX53_PAD_DISP0_DAT9__GPIO4_30 0x084 0x3b0 0x000 0x1 0x0 | ||
| 192 | #define MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x084 0x3b0 0x000 0x2 0x0 | ||
| 193 | #define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 0x084 0x3b0 0x000 0x3 0x0 | ||
| 194 | #define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 0x084 0x3b0 0x000 0x5 0x0 | ||
| 195 | #define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 0x084 0x3b0 0x000 0x6 0x0 | ||
| 196 | #define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 0x084 0x3b0 0x000 0x7 0x0 | ||
| 197 | #define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x088 0x3b4 0x000 0x0 0x0 | ||
| 198 | #define MX53_PAD_DISP0_DAT10__GPIO4_31 0x088 0x3b4 0x000 0x1 0x0 | ||
| 199 | #define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x088 0x3b4 0x000 0x2 0x0 | ||
| 200 | #define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 0x088 0x3b4 0x000 0x5 0x0 | ||
| 201 | #define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 0x088 0x3b4 0x000 0x6 0x0 | ||
| 202 | #define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 0x088 0x3b4 0x000 0x7 0x0 | ||
| 203 | #define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x08c 0x3b8 0x000 0x0 0x0 | ||
| 204 | #define MX53_PAD_DISP0_DAT11__GPIO5_5 0x08c 0x3b8 0x000 0x1 0x0 | ||
| 205 | #define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x08c 0x3b8 0x000 0x2 0x0 | ||
| 206 | #define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 0x08c 0x3b8 0x000 0x5 0x0 | ||
| 207 | #define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 0x08c 0x3b8 0x000 0x6 0x0 | ||
| 208 | #define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 0x08c 0x3b8 0x000 0x7 0x0 | ||
| 209 | #define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x090 0x3bc 0x000 0x0 0x0 | ||
| 210 | #define MX53_PAD_DISP0_DAT12__GPIO5_6 0x090 0x3bc 0x000 0x1 0x0 | ||
| 211 | #define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x090 0x3bc 0x000 0x2 0x0 | ||
| 212 | #define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 0x090 0x3bc 0x000 0x5 0x0 | ||
| 213 | #define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 0x090 0x3bc 0x000 0x6 0x0 | ||
| 214 | #define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 0x090 0x3bc 0x000 0x7 0x0 | ||
| 215 | #define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x094 0x3c0 0x000 0x0 0x0 | ||
| 216 | #define MX53_PAD_DISP0_DAT13__GPIO5_7 0x094 0x3c0 0x000 0x1 0x0 | ||
| 217 | #define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 0x094 0x3c0 0x754 0x3 0x0 | ||
| 218 | #define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 0x094 0x3c0 0x000 0x5 0x0 | ||
| 219 | #define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 0x094 0x3c0 0x000 0x6 0x0 | ||
| 220 | #define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 0x094 0x3c0 0x000 0x7 0x0 | ||
| 221 | #define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x098 0x3c4 0x000 0x0 0x0 | ||
| 222 | #define MX53_PAD_DISP0_DAT14__GPIO5_8 0x098 0x3c4 0x000 0x1 0x0 | ||
| 223 | #define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 0x098 0x3c4 0x750 0x3 0x0 | ||
| 224 | #define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 0x098 0x3c4 0x000 0x5 0x0 | ||
| 225 | #define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 0x098 0x3c4 0x000 0x6 0x0 | ||
| 226 | #define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 0x098 0x3c4 0x000 0x7 0x0 | ||
| 227 | #define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x09c 0x3c8 0x000 0x0 0x0 | ||
| 228 | #define MX53_PAD_DISP0_DAT15__GPIO5_9 0x09c 0x3c8 0x000 0x1 0x0 | ||
| 229 | #define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 0x09c 0x3c8 0x7ac 0x2 0x1 | ||
| 230 | #define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 0x09c 0x3c8 0x7c8 0x3 0x0 | ||
| 231 | #define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 0x09c 0x3c8 0x000 0x5 0x0 | ||
| 232 | #define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 0x09c 0x3c8 0x000 0x6 0x0 | ||
| 233 | #define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 0x09c 0x3c8 0x000 0x7 0x0 | ||
| 234 | #define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x0a0 0x3cc 0x000 0x0 0x0 | ||
| 235 | #define MX53_PAD_DISP0_DAT16__GPIO5_10 0x0a0 0x3cc 0x000 0x1 0x0 | ||
| 236 | #define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0a0 0x3cc 0x7c0 0x2 0x0 | ||
| 237 | #define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x0a0 0x3cc 0x758 0x3 0x1 | ||
| 238 | #define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 0x0a0 0x3cc 0x868 0x4 0x0 | ||
| 239 | #define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 0x0a0 0x3cc 0x000 0x5 0x0 | ||
| 240 | #define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 0x0a0 0x3cc 0x000 0x6 0x0 | ||
| 241 | #define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 0x0a0 0x3cc 0x000 0x7 0x0 | ||
| 242 | #define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x0a4 0x3d0 0x000 0x0 0x0 | ||
| 243 | #define MX53_PAD_DISP0_DAT17__GPIO5_11 0x0a4 0x3d0 0x000 0x1 0x0 | ||
| 244 | #define MX53_PAD_DISP0_DAT17__ECSPI2_MISO 0x0a4 0x3d0 0x7bc 0x2 0x0 | ||
| 245 | #define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x0a4 0x3d0 0x74c 0x3 0x1 | ||
| 246 | #define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 0x0a4 0x3d0 0x86c 0x4 0x0 | ||
| 247 | #define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 0x0a4 0x3d0 0x000 0x5 0x0 | ||
| 248 | #define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 0x0a4 0x3d0 0x000 0x6 0x0 | ||
| 249 | #define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x0a8 0x3d4 0x000 0x0 0x0 | ||
| 250 | #define MX53_PAD_DISP0_DAT18__GPIO5_12 0x0a8 0x3d4 0x000 0x1 0x0 | ||
| 251 | #define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 0x0a8 0x3d4 0x7c4 0x2 0x0 | ||
| 252 | #define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x0a8 0x3d4 0x75c 0x3 0x1 | ||
| 253 | #define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 0x0a8 0x3d4 0x73c 0x4 0x0 | ||
| 254 | #define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 0x0a8 0x3d4 0x000 0x5 0x0 | ||
| 255 | #define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 0x0a8 0x3d4 0x000 0x6 0x0 | ||
| 256 | #define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 0x0a8 0x3d4 0x000 0x7 0x0 | ||
| 257 | #define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x0ac 0x3d8 0x000 0x0 0x0 | ||
| 258 | #define MX53_PAD_DISP0_DAT19__GPIO5_13 0x0ac 0x3d8 0x000 0x1 0x0 | ||
| 259 | #define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0ac 0x3d8 0x7b8 0x2 0x0 | ||
| 260 | #define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x0ac 0x3d8 0x748 0x3 0x1 | ||
| 261 | #define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 0x0ac 0x3d8 0x738 0x4 0x0 | ||
| 262 | #define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 0x0ac 0x3d8 0x000 0x5 0x0 | ||
| 263 | #define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 0x0ac 0x3d8 0x000 0x6 0x0 | ||
| 264 | #define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 0x0ac 0x3d8 0x000 0x7 0x0 | ||
| 265 | #define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x0b0 0x3dc 0x000 0x0 0x0 | ||
| 266 | #define MX53_PAD_DISP0_DAT20__GPIO5_14 0x0b0 0x3dc 0x000 0x1 0x0 | ||
| 267 | #define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0b0 0x3dc 0x79c 0x2 0x1 | ||
| 268 | #define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 0x0b0 0x3dc 0x740 0x3 0x0 | ||
| 269 | #define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 0x0b0 0x3dc 0x000 0x5 0x0 | ||
| 270 | #define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 0x0b0 0x3dc 0x000 0x6 0x0 | ||
| 271 | #define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 0x0b0 0x3dc 0x000 0x7 0x0 | ||
| 272 | #define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x0b4 0x3e0 0x000 0x0 0x0 | ||
| 273 | #define MX53_PAD_DISP0_DAT21__GPIO5_15 0x0b4 0x3e0 0x000 0x1 0x0 | ||
| 274 | #define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0b4 0x3e0 0x7a4 0x2 0x1 | ||
| 275 | #define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 0x0b4 0x3e0 0x734 0x3 0x0 | ||
| 276 | #define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 0x0b4 0x3e0 0x000 0x5 0x0 | ||
| 277 | #define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 0x0b4 0x3e0 0x000 0x6 0x0 | ||
| 278 | #define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 0x0b4 0x3e0 0x000 0x7 0x0 | ||
| 279 | #define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x0b8 0x3e4 0x000 0x0 0x0 | ||
| 280 | #define MX53_PAD_DISP0_DAT22__GPIO5_16 0x0b8 0x3e4 0x000 0x1 0x0 | ||
| 281 | #define MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x0b8 0x3e4 0x7a0 0x2 0x1 | ||
| 282 | #define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 0x0b8 0x3e4 0x744 0x3 0x0 | ||
| 283 | #define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 0x0b8 0x3e4 0x000 0x5 0x0 | ||
| 284 | #define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 0x0b8 0x3e4 0x000 0x6 0x0 | ||
| 285 | #define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 0x0b8 0x3e4 0x000 0x7 0x0 | ||
| 286 | #define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x0bc 0x3e8 0x000 0x0 0x0 | ||
| 287 | #define MX53_PAD_DISP0_DAT23__GPIO5_17 0x0bc 0x3e8 0x000 0x1 0x0 | ||
| 288 | #define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 0x0bc 0x3e8 0x7a8 0x2 0x1 | ||
| 289 | #define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 0x0bc 0x3e8 0x730 0x3 0x0 | ||
| 290 | #define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 0x0bc 0x3e8 0x000 0x5 0x0 | ||
| 291 | #define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 0x0bc 0x3e8 0x000 0x6 0x0 | ||
| 292 | #define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 0x0bc 0x3e8 0x000 0x7 0x0 | ||
| 293 | #define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x0c0 0x3ec 0x000 0x0 0x0 | ||
| 294 | #define MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0c0 0x3ec 0x000 0x1 0x0 | ||
| 295 | #define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 0x0c0 0x3ec 0x000 0x5 0x0 | ||
| 296 | #define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 0x0c0 0x3ec 0x000 0x6 0x0 | ||
| 297 | #define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x0c4 0x3f0 0x000 0x0 0x0 | ||
| 298 | #define MX53_PAD_CSI0_MCLK__GPIO5_19 0x0c4 0x3f0 0x000 0x1 0x0 | ||
| 299 | #define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x0c4 0x3f0 0x000 0x2 0x0 | ||
| 300 | #define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 0x0c4 0x3f0 0x000 0x5 0x0 | ||
| 301 | #define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 0x0c4 0x3f0 0x000 0x6 0x0 | ||
| 302 | #define MX53_PAD_CSI0_MCLK__TPIU_TRCTL 0x0c4 0x3f0 0x000 0x7 0x0 | ||
| 303 | #define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x0c8 0x3f4 0x000 0x0 0x0 | ||
| 304 | #define MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0c8 0x3f4 0x000 0x1 0x0 | ||
| 305 | #define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 0x0c8 0x3f4 0x000 0x5 0x0 | ||
| 306 | #define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 0x0c8 0x3f4 0x000 0x6 0x0 | ||
| 307 | #define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 0x0c8 0x3f4 0x000 0x7 0x0 | ||
| 308 | #define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x0cc 0x3f8 0x000 0x0 0x0 | ||
| 309 | #define MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0cc 0x3f8 0x000 0x1 0x0 | ||
| 310 | #define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 0x0cc 0x3f8 0x000 0x5 0x0 | ||
| 311 | #define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 0x0cc 0x3f8 0x000 0x6 0x0 | ||
| 312 | #define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 0x0cc 0x3f8 0x000 0x7 0x0 | ||
| 313 | #define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x0d0 0x3fc 0x000 0x0 0x0 | ||
| 314 | #define MX53_PAD_CSI0_DAT4__GPIO5_22 0x0d0 0x3fc 0x000 0x1 0x0 | ||
| 315 | #define MX53_PAD_CSI0_DAT4__KPP_COL_5 0x0d0 0x3fc 0x840 0x2 0x1 | ||
| 316 | #define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 0x0d0 0x3fc 0x79c 0x3 0x2 | ||
| 317 | #define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x0d0 0x3fc 0x000 0x4 0x0 | ||
| 318 | #define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x0d0 0x3fc 0x000 0x5 0x0 | ||
| 319 | #define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 0x0d0 0x3fc 0x000 0x6 0x0 | ||
| 320 | #define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 0x0d0 0x3fc 0x000 0x7 0x0 | ||
| 321 | #define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x0d4 0x400 0x000 0x0 0x0 | ||
| 322 | #define MX53_PAD_CSI0_DAT5__GPIO5_23 0x0d4 0x400 0x000 0x1 0x0 | ||
| 323 | #define MX53_PAD_CSI0_DAT5__KPP_ROW_5 0x0d4 0x400 0x84c 0x2 0x0 | ||
| 324 | #define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 0x0d4 0x400 0x7a4 0x3 0x2 | ||
| 325 | #define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x0d4 0x400 0x000 0x4 0x0 | ||
| 326 | #define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x0d4 0x400 0x000 0x5 0x0 | ||
| 327 | #define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 0x0d4 0x400 0x000 0x6 0x0 | ||
| 328 | #define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 0x0d4 0x400 0x000 0x7 0x0 | ||
| 329 | #define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x0d8 0x404 0x000 0x0 0x0 | ||
| 330 | #define MX53_PAD_CSI0_DAT6__GPIO5_24 0x0d8 0x404 0x000 0x1 0x0 | ||
| 331 | #define MX53_PAD_CSI0_DAT6__KPP_COL_6 0x0d8 0x404 0x844 0x2 0x0 | ||
| 332 | #define MX53_PAD_CSI0_DAT6__ECSPI1_MISO 0x0d8 0x404 0x7a0 0x3 0x2 | ||
| 333 | #define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x0d8 0x404 0x000 0x4 0x0 | ||
| 334 | #define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x0d8 0x404 0x000 0x5 0x0 | ||
| 335 | #define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 0x0d8 0x404 0x000 0x6 0x0 | ||
| 336 | #define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 0x0d8 0x404 0x000 0x7 0x0 | ||
| 337 | #define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x0dc 0x408 0x000 0x0 0x0 | ||
| 338 | #define MX53_PAD_CSI0_DAT7__GPIO5_25 0x0dc 0x408 0x000 0x1 0x0 | ||
| 339 | #define MX53_PAD_CSI0_DAT7__KPP_ROW_6 0x0dc 0x408 0x850 0x2 0x0 | ||
| 340 | #define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 0x0dc 0x408 0x7a8 0x3 0x2 | ||
| 341 | #define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x0dc 0x408 0x000 0x4 0x0 | ||
| 342 | #define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x0dc 0x408 0x000 0x5 0x0 | ||
| 343 | #define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 0x0dc 0x408 0x000 0x6 0x0 | ||
| 344 | #define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 0x0dc 0x408 0x000 0x7 0x0 | ||
| 345 | #define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x0e0 0x40c 0x000 0x0 0x0 | ||
| 346 | #define MX53_PAD_CSI0_DAT8__GPIO5_26 0x0e0 0x40c 0x000 0x1 0x0 | ||
| 347 | #define MX53_PAD_CSI0_DAT8__KPP_COL_7 0x0e0 0x40c 0x848 0x2 0x0 | ||
| 348 | #define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 0x0e0 0x40c 0x7b8 0x3 0x1 | ||
| 349 | #define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x0e0 0x40c 0x000 0x4 0x0 | ||
| 350 | #define MX53_PAD_CSI0_DAT8__I2C1_SDA 0x0e0 0x40c 0x818 0x5 0x0 | ||
| 351 | #define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 0x0e0 0x40c 0x000 0x6 0x0 | ||
| 352 | #define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 0x0e0 0x40c 0x000 0x7 0x0 | ||
| 353 | #define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x0e4 0x410 0x000 0x0 0x0 | ||
| 354 | #define MX53_PAD_CSI0_DAT9__GPIO5_27 0x0e4 0x410 0x000 0x1 0x0 | ||
| 355 | #define MX53_PAD_CSI0_DAT9__KPP_ROW_7 0x0e4 0x410 0x854 0x2 0x0 | ||
| 356 | #define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x0e4 0x410 0x7c0 0x3 0x1 | ||
| 357 | #define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 0x0e4 0x410 0x000 0x4 0x0 | ||
| 358 | #define MX53_PAD_CSI0_DAT9__I2C1_SCL 0x0e4 0x410 0x814 0x5 0x0 | ||
| 359 | #define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 0x0e4 0x410 0x000 0x6 0x0 | ||
| 360 | #define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 0x0e4 0x410 0x000 0x7 0x0 | ||
| 361 | #define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x0e8 0x414 0x000 0x0 0x0 | ||
| 362 | #define MX53_PAD_CSI0_DAT10__GPIO5_28 0x0e8 0x414 0x000 0x1 0x0 | ||
| 363 | #define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x0e8 0x414 0x000 0x2 0x0 | ||
| 364 | #define MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x0e8 0x414 0x7bc 0x3 0x1 | ||
| 365 | #define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 0x0e8 0x414 0x000 0x4 0x0 | ||
| 366 | #define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 0x0e8 0x414 0x000 0x5 0x0 | ||
| 367 | #define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 0x0e8 0x414 0x000 0x6 0x0 | ||
| 368 | #define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 0x0e8 0x414 0x000 0x7 0x0 | ||
| 369 | #define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x0ec 0x418 0x000 0x0 0x0 | ||
| 370 | #define MX53_PAD_CSI0_DAT11__GPIO5_29 0x0ec 0x418 0x000 0x1 0x0 | ||
| 371 | #define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x0ec 0x418 0x878 0x2 0x1 | ||
| 372 | #define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 0x0ec 0x418 0x7c4 0x3 0x1 | ||
| 373 | #define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 0x0ec 0x418 0x000 0x4 0x0 | ||
| 374 | #define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 0x0ec 0x418 0x000 0x5 0x0 | ||
| 375 | #define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 0x0ec 0x418 0x000 0x6 0x0 | ||
| 376 | #define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 0x0ec 0x418 0x000 0x7 0x0 | ||
| 377 | #define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x0f0 0x41c 0x000 0x0 0x0 | ||
| 378 | #define MX53_PAD_CSI0_DAT12__GPIO5_30 0x0f0 0x41c 0x000 0x1 0x0 | ||
| 379 | #define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x0f0 0x41c 0x000 0x2 0x0 | ||
| 380 | #define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x0f0 0x41c 0x000 0x4 0x0 | ||
| 381 | #define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 0x0f0 0x41c 0x000 0x5 0x0 | ||
| 382 | #define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 0x0f0 0x41c 0x000 0x6 0x0 | ||
| 383 | #define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 0x0f0 0x41c 0x000 0x7 0x0 | ||
| 384 | #define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x0f4 0x420 0x000 0x0 0x0 | ||
| 385 | #define MX53_PAD_CSI0_DAT13__GPIO5_31 0x0f4 0x420 0x000 0x1 0x0 | ||
| 386 | #define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x0f4 0x420 0x890 0x2 0x3 | ||
| 387 | #define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x0f4 0x420 0x000 0x4 0x0 | ||
| 388 | #define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 0x0f4 0x420 0x000 0x5 0x0 | ||
| 389 | #define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 0x0f4 0x420 0x000 0x6 0x0 | ||
| 390 | #define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 0x0f4 0x420 0x000 0x7 0x0 | ||
| 391 | #define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x0f8 0x424 0x000 0x0 0x0 | ||
| 392 | #define MX53_PAD_CSI0_DAT14__GPIO6_0 0x0f8 0x424 0x000 0x1 0x0 | ||
| 393 | #define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 0x0f8 0x424 0x000 0x2 0x0 | ||
| 394 | #define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x0f8 0x424 0x000 0x4 0x0 | ||
| 395 | #define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 0x0f8 0x424 0x000 0x5 0x0 | ||
| 396 | #define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 0x0f8 0x424 0x000 0x6 0x0 | ||
| 397 | #define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 0x0f8 0x424 0x000 0x7 0x0 | ||
| 398 | #define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x0fc 0x428 0x000 0x0 0x0 | ||
| 399 | #define MX53_PAD_CSI0_DAT15__GPIO6_1 0x0fc 0x428 0x000 0x1 0x0 | ||
| 400 | #define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 0x0fc 0x428 0x898 0x2 0x3 | ||
| 401 | #define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x0fc 0x428 0x000 0x4 0x0 | ||
| 402 | #define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 0x0fc 0x428 0x000 0x5 0x0 | ||
| 403 | #define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 0x0fc 0x428 0x000 0x6 0x0 | ||
| 404 | #define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 0x0fc 0x428 0x000 0x7 0x0 | ||
| 405 | #define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x100 0x42c 0x000 0x0 0x0 | ||
| 406 | #define MX53_PAD_CSI0_DAT16__GPIO6_2 0x100 0x42c 0x000 0x1 0x0 | ||
| 407 | #define MX53_PAD_CSI0_DAT16__UART4_RTS 0x100 0x42c 0x88c 0x2 0x0 | ||
| 408 | #define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x100 0x42c 0x000 0x4 0x0 | ||
| 409 | #define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 0x100 0x42c 0x000 0x5 0x0 | ||
| 410 | #define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 0x100 0x42c 0x000 0x6 0x0 | ||
| 411 | #define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 0x100 0x42c 0x000 0x7 0x0 | ||
| 412 | #define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x104 0x430 0x000 0x0 0x0 | ||
| 413 | #define MX53_PAD_CSI0_DAT17__GPIO6_3 0x104 0x430 0x000 0x1 0x0 | ||
| 414 | #define MX53_PAD_CSI0_DAT17__UART4_CTS 0x104 0x430 0x000 0x2 0x0 | ||
| 415 | #define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x104 0x430 0x000 0x4 0x0 | ||
| 416 | #define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 0x104 0x430 0x000 0x5 0x0 | ||
| 417 | #define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 0x104 0x430 0x000 0x6 0x0 | ||
| 418 | #define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 0x104 0x430 0x000 0x7 0x0 | ||
| 419 | #define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x108 0x434 0x000 0x0 0x0 | ||
| 420 | #define MX53_PAD_CSI0_DAT18__GPIO6_4 0x108 0x434 0x000 0x1 0x0 | ||
| 421 | #define MX53_PAD_CSI0_DAT18__UART5_RTS 0x108 0x434 0x894 0x2 0x2 | ||
| 422 | #define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x108 0x434 0x000 0x4 0x0 | ||
| 423 | #define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 0x108 0x434 0x000 0x5 0x0 | ||
| 424 | #define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 0x108 0x434 0x000 0x6 0x0 | ||
| 425 | #define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 0x108 0x434 0x000 0x7 0x0 | ||
| 426 | #define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x10c 0x438 0x000 0x0 0x0 | ||
| 427 | #define MX53_PAD_CSI0_DAT19__GPIO6_5 0x10c 0x438 0x000 0x1 0x0 | ||
| 428 | #define MX53_PAD_CSI0_DAT19__UART5_CTS 0x10c 0x438 0x000 0x2 0x0 | ||
| 429 | #define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x10c 0x438 0x000 0x4 0x0 | ||
| 430 | #define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 0x10c 0x438 0x000 0x5 0x0 | ||
| 431 | #define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 0x10c 0x438 0x000 0x6 0x0 | ||
| 432 | #define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 0x10c 0x438 0x000 0x7 0x0 | ||
| 433 | #define MX53_PAD_EIM_A25__EMI_WEIM_A_25 0x110 0x458 0x000 0x0 0x0 | ||
| 434 | #define MX53_PAD_EIM_A25__GPIO5_2 0x110 0x458 0x000 0x1 0x0 | ||
| 435 | #define MX53_PAD_EIM_A25__ECSPI2_RDY 0x110 0x458 0x000 0x2 0x0 | ||
| 436 | #define MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x110 0x458 0x000 0x3 0x0 | ||
| 437 | #define MX53_PAD_EIM_A25__CSPI_SS1 0x110 0x458 0x790 0x4 0x1 | ||
| 438 | #define MX53_PAD_EIM_A25__IPU_DI0_D1_CS 0x110 0x458 0x000 0x6 0x0 | ||
| 439 | #define MX53_PAD_EIM_A25__USBPHY1_BISTOK 0x110 0x458 0x000 0x7 0x0 | ||
| 440 | #define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x114 0x45c 0x000 0x0 0x0 | ||
| 441 | #define MX53_PAD_EIM_EB2__GPIO2_30 0x114 0x45c 0x000 0x1 0x0 | ||
| 442 | #define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 0x114 0x45c 0x76c 0x2 0x0 | ||
| 443 | #define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 0x114 0x45c 0x000 0x3 0x0 | ||
| 444 | #define MX53_PAD_EIM_EB2__ECSPI1_SS0 0x114 0x45c 0x7a8 0x4 0x3 | ||
| 445 | #define MX53_PAD_EIM_EB2__I2C2_SCL 0x114 0x45c 0x81c 0x5 0x1 | ||
| 446 | #define MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x118 0x460 0x000 0x0 0x0 | ||
| 447 | #define MX53_PAD_EIM_D16__GPIO3_16 0x118 0x460 0x000 0x1 0x0 | ||
| 448 | #define MX53_PAD_EIM_D16__IPU_DI0_PIN5 0x118 0x460 0x000 0x2 0x0 | ||
| 449 | #define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 0x118 0x460 0x000 0x3 0x0 | ||
| 450 | #define MX53_PAD_EIM_D16__ECSPI1_SCLK 0x118 0x460 0x79c 0x4 0x3 | ||
| 451 | #define MX53_PAD_EIM_D16__I2C2_SDA 0x118 0x460 0x820 0x5 0x1 | ||
| 452 | #define MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x11c 0x464 0x000 0x0 0x0 | ||
| 453 | #define MX53_PAD_EIM_D17__GPIO3_17 0x11c 0x464 0x000 0x1 0x0 | ||
| 454 | #define MX53_PAD_EIM_D17__IPU_DI0_PIN6 0x11c 0x464 0x000 0x2 0x0 | ||
| 455 | #define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 0x11c 0x464 0x830 0x3 0x0 | ||
| 456 | #define MX53_PAD_EIM_D17__ECSPI1_MISO 0x11c 0x464 0x7a0 0x4 0x3 | ||
| 457 | #define MX53_PAD_EIM_D17__I2C3_SCL 0x11c 0x464 0x824 0x5 0x0 | ||
| 458 | #define MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x120 0x468 0x000 0x0 0x0 | ||
| 459 | #define MX53_PAD_EIM_D18__GPIO3_18 0x120 0x468 0x000 0x1 0x0 | ||
| 460 | #define MX53_PAD_EIM_D18__IPU_DI0_PIN7 0x120 0x468 0x000 0x2 0x0 | ||
| 461 | #define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 0x120 0x468 0x830 0x3 0x1 | ||
| 462 | #define MX53_PAD_EIM_D18__ECSPI1_MOSI 0x120 0x468 0x7a4 0x4 0x3 | ||
| 463 | #define MX53_PAD_EIM_D18__I2C3_SDA 0x120 0x468 0x828 0x5 0x0 | ||
| 464 | #define MX53_PAD_EIM_D18__IPU_DI1_D0_CS 0x120 0x468 0x000 0x6 0x0 | ||
| 465 | #define MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x124 0x46c 0x000 0x0 0x0 | ||
| 466 | #define MX53_PAD_EIM_D19__GPIO3_19 0x124 0x46c 0x000 0x1 0x0 | ||
| 467 | #define MX53_PAD_EIM_D19__IPU_DI0_PIN8 0x124 0x46c 0x000 0x2 0x0 | ||
| 468 | #define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 0x124 0x46c 0x000 0x3 0x0 | ||
| 469 | #define MX53_PAD_EIM_D19__ECSPI1_SS1 0x124 0x46c 0x7ac 0x4 0x2 | ||
| 470 | #define MX53_PAD_EIM_D19__EPIT1_EPITO 0x124 0x46c 0x000 0x5 0x0 | ||
| 471 | #define MX53_PAD_EIM_D19__UART1_CTS 0x124 0x46c 0x000 0x6 0x0 | ||
| 472 | #define MX53_PAD_EIM_D19__USBOH3_USBH2_OC 0x124 0x46c 0x8a4 0x7 0x0 | ||
| 473 | #define MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x128 0x470 0x000 0x0 0x0 | ||
| 474 | #define MX53_PAD_EIM_D20__GPIO3_20 0x128 0x470 0x000 0x1 0x0 | ||
| 475 | #define MX53_PAD_EIM_D20__IPU_DI0_PIN16 0x128 0x470 0x000 0x2 0x0 | ||
| 476 | #define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 0x128 0x470 0x000 0x3 0x0 | ||
| 477 | #define MX53_PAD_EIM_D20__CSPI_SS0 0x128 0x470 0x78c 0x4 0x1 | ||
| 478 | #define MX53_PAD_EIM_D20__EPIT2_EPITO 0x128 0x470 0x000 0x5 0x0 | ||
| 479 | #define MX53_PAD_EIM_D20__UART1_RTS 0x128 0x470 0x874 0x6 0x1 | ||
| 480 | #define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 0x128 0x470 0x000 0x7 0x0 | ||
| 481 | #define MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x12c 0x474 0x000 0x0 0x0 | ||
| 482 | #define MX53_PAD_EIM_D21__GPIO3_21 0x12c 0x474 0x000 0x1 0x0 | ||
| 483 | #define MX53_PAD_EIM_D21__IPU_DI0_PIN17 0x12c 0x474 0x000 0x2 0x0 | ||
| 484 | #define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 0x12c 0x474 0x000 0x3 0x0 | ||
| 485 | #define MX53_PAD_EIM_D21__CSPI_SCLK 0x12c 0x474 0x780 0x4 0x1 | ||
| 486 | #define MX53_PAD_EIM_D21__I2C1_SCL 0x12c 0x474 0x814 0x5 0x1 | ||
| 487 | #define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 0x12c 0x474 0x89c 0x6 0x1 | ||
| 488 | #define MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x130 0x478 0x000 0x0 0x0 | ||
| 489 | #define MX53_PAD_EIM_D22__GPIO3_22 0x130 0x478 0x000 0x1 0x0 | ||
| 490 | #define MX53_PAD_EIM_D22__IPU_DI0_PIN1 0x130 0x478 0x000 0x2 0x0 | ||
| 491 | #define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 0x130 0x478 0x82c 0x3 0x0 | ||
| 492 | #define MX53_PAD_EIM_D22__CSPI_MISO 0x130 0x478 0x784 0x4 0x1 | ||
| 493 | #define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 0x130 0x478 0x000 0x6 0x0 | ||
| 494 | #define MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x134 0x47c 0x000 0x0 0x0 | ||
| 495 | #define MX53_PAD_EIM_D23__GPIO3_23 0x134 0x47c 0x000 0x1 0x0 | ||
| 496 | #define MX53_PAD_EIM_D23__UART3_CTS 0x134 0x47c 0x000 0x2 0x0 | ||
| 497 | #define MX53_PAD_EIM_D23__UART1_DCD 0x134 0x47c 0x000 0x3 0x0 | ||
| 498 | #define MX53_PAD_EIM_D23__IPU_DI0_D0_CS 0x134 0x47c 0x000 0x4 0x0 | ||
| 499 | #define MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x134 0x47c 0x000 0x5 0x0 | ||
| 500 | #define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 0x134 0x47c 0x834 0x6 0x0 | ||
| 501 | #define MX53_PAD_EIM_D23__IPU_DI1_PIN14 0x134 0x47c 0x000 0x7 0x0 | ||
| 502 | #define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x138 0x480 0x000 0x0 0x0 | ||
| 503 | #define MX53_PAD_EIM_EB3__GPIO2_31 0x138 0x480 0x000 0x1 0x0 | ||
| 504 | #define MX53_PAD_EIM_EB3__UART3_RTS 0x138 0x480 0x884 0x2 0x1 | ||
| 505 | #define MX53_PAD_EIM_EB3__UART1_RI 0x138 0x480 0x000 0x3 0x0 | ||
| 506 | #define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x138 0x480 0x000 0x5 0x0 | ||
| 507 | #define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 0x138 0x480 0x838 0x6 0x0 | ||
| 508 | #define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 0x138 0x480 0x000 0x7 0x0 | ||
| 509 | #define MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x13c 0x484 0x000 0x0 0x0 | ||
| 510 | #define MX53_PAD_EIM_D24__GPIO3_24 0x13c 0x484 0x000 0x1 0x0 | ||
| 511 | #define MX53_PAD_EIM_D24__UART3_TXD_MUX 0x13c 0x484 0x000 0x2 0x0 | ||
| 512 | #define MX53_PAD_EIM_D24__ECSPI1_SS2 0x13c 0x484 0x7b0 0x3 0x1 | ||
| 513 | #define MX53_PAD_EIM_D24__CSPI_SS2 0x13c 0x484 0x794 0x4 0x1 | ||
| 514 | #define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 0x13c 0x484 0x754 0x5 0x1 | ||
| 515 | #define MX53_PAD_EIM_D24__ECSPI2_SS2 0x13c 0x484 0x000 0x6 0x0 | ||
| 516 | #define MX53_PAD_EIM_D24__UART1_DTR 0x13c 0x484 0x000 0x7 0x0 | ||
| 517 | #define MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x140 0x488 0x000 0x0 0x0 | ||
| 518 | #define MX53_PAD_EIM_D25__GPIO3_25 0x140 0x488 0x000 0x1 0x0 | ||
| 519 | #define MX53_PAD_EIM_D25__UART3_RXD_MUX 0x140 0x488 0x888 0x2 0x1 | ||
| 520 | #define MX53_PAD_EIM_D25__ECSPI1_SS3 0x140 0x488 0x7b4 0x3 0x1 | ||
| 521 | #define MX53_PAD_EIM_D25__CSPI_SS3 0x140 0x488 0x798 0x4 0x1 | ||
| 522 | #define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 0x140 0x488 0x750 0x5 0x1 | ||
| 523 | #define MX53_PAD_EIM_D25__ECSPI2_SS3 0x140 0x488 0x000 0x6 0x0 | ||
| 524 | #define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0 | ||
| 525 | #define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0 | ||
| 526 | #define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0 | ||
| 527 | #define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0 | ||
| 528 | #define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0 | ||
| 529 | #define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0 | ||
| 530 | #define MX53_PAD_EIM_D26__IPU_DI1_PIN11 0x144 0x48c 0x000 0x5 0x0 | ||
| 531 | #define MX53_PAD_EIM_D26__IPU_SISG_2 0x144 0x48c 0x000 0x6 0x0 | ||
| 532 | #define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x144 0x48c 0x000 0x7 0x0 | ||
| 533 | #define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0 | ||
| 534 | #define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0 | ||
| 535 | #define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1 | ||
| 536 | #define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0 | ||
| 537 | #define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0 | ||
| 538 | #define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0 | ||
| 539 | #define MX53_PAD_EIM_D27__IPU_SISG_3 0x148 0x490 0x000 0x6 0x0 | ||
| 540 | #define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x148 0x490 0x000 0x7 0x0 | ||
| 541 | #define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0 | ||
| 542 | #define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0 | ||
| 543 | #define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0 | ||
| 544 | #define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1 | ||
| 545 | #define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1 | ||
| 546 | #define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1 | ||
| 547 | #define MX53_PAD_EIM_D28__IPU_EXT_TRIG 0x14c 0x494 0x000 0x6 0x0 | ||
| 548 | #define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0 | ||
| 549 | #define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0 | ||
| 550 | #define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0 | ||
| 551 | #define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1 | ||
| 552 | #define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0 | ||
| 553 | #define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2 | ||
| 554 | #define MX53_PAD_EIM_D29__IPU_DI1_PIN15 0x150 0x498 0x000 0x5 0x0 | ||
| 555 | #define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 0x150 0x498 0x83c 0x6 0x0 | ||
| 556 | #define MX53_PAD_EIM_D29__IPU_DI0_PIN14 0x150 0x498 0x000 0x7 0x0 | ||
| 557 | #define MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x154 0x49c 0x000 0x0 0x0 | ||
| 558 | #define MX53_PAD_EIM_D30__GPIO3_30 0x154 0x49c 0x000 0x1 0x0 | ||
| 559 | #define MX53_PAD_EIM_D30__UART3_CTS 0x154 0x49c 0x000 0x2 0x0 | ||
| 560 | #define MX53_PAD_EIM_D30__IPU_CSI0_D_3 0x154 0x49c 0x000 0x3 0x0 | ||
| 561 | #define MX53_PAD_EIM_D30__IPU_DI0_PIN11 0x154 0x49c 0x000 0x4 0x0 | ||
| 562 | #define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x154 0x49c 0x000 0x5 0x0 | ||
| 563 | #define MX53_PAD_EIM_D30__USBOH3_USBH1_OC 0x154 0x49c 0x8a0 0x6 0x0 | ||
| 564 | #define MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x154 0x49c 0x8a4 0x7 0x1 | ||
| 565 | #define MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x158 0x4a0 0x000 0x0 0x0 | ||
| 566 | #define MX53_PAD_EIM_D31__GPIO3_31 0x158 0x4a0 0x000 0x1 0x0 | ||
| 567 | #define MX53_PAD_EIM_D31__UART3_RTS 0x158 0x4a0 0x884 0x2 0x3 | ||
| 568 | #define MX53_PAD_EIM_D31__IPU_CSI0_D_2 0x158 0x4a0 0x000 0x3 0x0 | ||
| 569 | #define MX53_PAD_EIM_D31__IPU_DI0_PIN12 0x158 0x4a0 0x000 0x4 0x0 | ||
| 570 | #define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x158 0x4a0 0x000 0x5 0x0 | ||
| 571 | #define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 0x158 0x4a0 0x000 0x6 0x0 | ||
| 572 | #define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 0x158 0x4a0 0x000 0x7 0x0 | ||
| 573 | #define MX53_PAD_EIM_A24__EMI_WEIM_A_24 0x15c 0x4a8 0x000 0x0 0x0 | ||
| 574 | #define MX53_PAD_EIM_A24__GPIO5_4 0x15c 0x4a8 0x000 0x1 0x0 | ||
| 575 | #define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x15c 0x4a8 0x000 0x2 0x0 | ||
| 576 | #define MX53_PAD_EIM_A24__IPU_CSI1_D_19 0x15c 0x4a8 0x000 0x3 0x0 | ||
| 577 | #define MX53_PAD_EIM_A24__IPU_SISG_2 0x15c 0x4a8 0x000 0x6 0x0 | ||
| 578 | #define MX53_PAD_EIM_A24__USBPHY2_BVALID 0x15c 0x4a8 0x000 0x7 0x0 | ||
| 579 | #define MX53_PAD_EIM_A23__EMI_WEIM_A_23 0x160 0x4ac 0x000 0x0 0x0 | ||
| 580 | #define MX53_PAD_EIM_A23__GPIO6_6 0x160 0x4ac 0x000 0x1 0x0 | ||
| 581 | #define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x160 0x4ac 0x000 0x2 0x0 | ||
| 582 | #define MX53_PAD_EIM_A23__IPU_CSI1_D_18 0x160 0x4ac 0x000 0x3 0x0 | ||
| 583 | #define MX53_PAD_EIM_A23__IPU_SISG_3 0x160 0x4ac 0x000 0x6 0x0 | ||
| 584 | #define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 0x160 0x4ac 0x000 0x7 0x0 | ||
| 585 | #define MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x164 0x4b0 0x000 0x0 0x0 | ||
| 586 | #define MX53_PAD_EIM_A22__GPIO2_16 0x164 0x4b0 0x000 0x1 0x0 | ||
| 587 | #define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x164 0x4b0 0x000 0x2 0x0 | ||
| 588 | #define MX53_PAD_EIM_A22__IPU_CSI1_D_17 0x164 0x4b0 0x000 0x3 0x0 | ||
| 589 | #define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 0x164 0x4b0 0x000 0x7 0x0 | ||
| 590 | #define MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x168 0x4b4 0x000 0x0 0x0 | ||
| 591 | #define MX53_PAD_EIM_A21__GPIO2_17 0x168 0x4b4 0x000 0x1 0x0 | ||
| 592 | #define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x168 0x4b4 0x000 0x2 0x0 | ||
| 593 | #define MX53_PAD_EIM_A21__IPU_CSI1_D_16 0x168 0x4b4 0x000 0x3 0x0 | ||
| 594 | #define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 0x168 0x4b4 0x000 0x7 0x0 | ||
| 595 | #define MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x16c 0x4b8 0x000 0x0 0x0 | ||
| 596 | #define MX53_PAD_EIM_A20__GPIO2_18 0x16c 0x4b8 0x000 0x1 0x0 | ||
| 597 | #define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x16c 0x4b8 0x000 0x2 0x0 | ||
| 598 | #define MX53_PAD_EIM_A20__IPU_CSI1_D_15 0x16c 0x4b8 0x000 0x3 0x0 | ||
| 599 | #define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 0x16c 0x4b8 0x000 0x7 0x0 | ||
| 600 | #define MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x170 0x4bc 0x000 0x0 0x0 | ||
| 601 | #define MX53_PAD_EIM_A19__GPIO2_19 0x170 0x4bc 0x000 0x1 0x0 | ||
| 602 | #define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x170 0x4bc 0x000 0x2 0x0 | ||
| 603 | #define MX53_PAD_EIM_A19__IPU_CSI1_D_14 0x170 0x4bc 0x000 0x3 0x0 | ||
| 604 | #define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 0x170 0x4bc 0x000 0x7 0x0 | ||
| 605 | #define MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x174 0x4c0 0x000 0x0 0x0 | ||
| 606 | #define MX53_PAD_EIM_A18__GPIO2_20 0x174 0x4c0 0x000 0x1 0x0 | ||
| 607 | #define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x174 0x4c0 0x000 0x2 0x0 | ||
| 608 | #define MX53_PAD_EIM_A18__IPU_CSI1_D_13 0x174 0x4c0 0x000 0x3 0x0 | ||
| 609 | #define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 0x174 0x4c0 0x000 0x7 0x0 | ||
| 610 | #define MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x178 0x4c4 0x000 0x0 0x0 | ||
| 611 | #define MX53_PAD_EIM_A17__GPIO2_21 0x178 0x4c4 0x000 0x1 0x0 | ||
| 612 | #define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x178 0x4c4 0x000 0x2 0x0 | ||
| 613 | #define MX53_PAD_EIM_A17__IPU_CSI1_D_12 0x178 0x4c4 0x000 0x3 0x0 | ||
| 614 | #define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 0x178 0x4c4 0x000 0x7 0x0 | ||
| 615 | #define MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x17c 0x4c8 0x000 0x0 0x0 | ||
| 616 | #define MX53_PAD_EIM_A16__GPIO2_22 0x17c 0x4c8 0x000 0x1 0x0 | ||
| 617 | #define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x17c 0x4c8 0x000 0x2 0x0 | ||
| 618 | #define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 0x17c 0x4c8 0x000 0x3 0x0 | ||
| 619 | #define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 0x17c 0x4c8 0x000 0x7 0x0 | ||
| 620 | #define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x180 0x4cc 0x000 0x0 0x0 | ||
| 621 | #define MX53_PAD_EIM_CS0__GPIO2_23 0x180 0x4cc 0x000 0x1 0x0 | ||
| 622 | #define MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x180 0x4cc 0x7b8 0x2 0x2 | ||
| 623 | #define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 0x180 0x4cc 0x000 0x3 0x0 | ||
| 624 | #define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x184 0x4d0 0x000 0x0 0x0 | ||
| 625 | #define MX53_PAD_EIM_CS1__GPIO2_24 0x184 0x4d0 0x000 0x1 0x0 | ||
| 626 | #define MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x184 0x4d0 0x7c0 0x2 0x2 | ||
| 627 | #define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x184 0x4d0 0x000 0x3 0x0 | ||
| 628 | #define MX53_PAD_EIM_OE__EMI_WEIM_OE 0x188 0x4d4 0x000 0x0 0x0 | ||
| 629 | #define MX53_PAD_EIM_OE__GPIO2_25 0x188 0x4d4 0x000 0x1 0x0 | ||
| 630 | #define MX53_PAD_EIM_OE__ECSPI2_MISO 0x188 0x4d4 0x7bc 0x2 0x2 | ||
| 631 | #define MX53_PAD_EIM_OE__IPU_DI1_PIN7 0x188 0x4d4 0x000 0x3 0x0 | ||
| 632 | #define MX53_PAD_EIM_OE__USBPHY2_IDDIG 0x188 0x4d4 0x000 0x7 0x0 | ||
| 633 | #define MX53_PAD_EIM_RW__EMI_WEIM_RW 0x18c 0x4d8 0x000 0x0 0x0 | ||
| 634 | #define MX53_PAD_EIM_RW__GPIO2_26 0x18c 0x4d8 0x000 0x1 0x0 | ||
| 635 | #define MX53_PAD_EIM_RW__ECSPI2_SS0 0x18c 0x4d8 0x7c4 0x2 0x2 | ||
| 636 | #define MX53_PAD_EIM_RW__IPU_DI1_PIN8 0x18c 0x4d8 0x000 0x3 0x0 | ||
| 637 | #define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 0x18c 0x4d8 0x000 0x7 0x0 | ||
| 638 | #define MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x190 0x4dc 0x000 0x0 0x0 | ||
| 639 | #define MX53_PAD_EIM_LBA__GPIO2_27 0x190 0x4dc 0x000 0x1 0x0 | ||
| 640 | #define MX53_PAD_EIM_LBA__ECSPI2_SS1 0x190 0x4dc 0x7c8 0x2 0x1 | ||
| 641 | #define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 0x190 0x4dc 0x000 0x3 0x0 | ||
| 642 | #define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 0x190 0x4dc 0x000 0x7 0x0 | ||
| 643 | #define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x194 0x4e4 0x000 0x0 0x0 | ||
| 644 | #define MX53_PAD_EIM_EB0__GPIO2_28 0x194 0x4e4 0x000 0x1 0x0 | ||
| 645 | #define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x194 0x4e4 0x000 0x3 0x0 | ||
| 646 | #define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 0x194 0x4e4 0x000 0x4 0x0 | ||
| 647 | #define MX53_PAD_EIM_EB0__GPC_PMIC_RDY 0x194 0x4e4 0x810 0x5 0x0 | ||
| 648 | #define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 0x194 0x4e4 0x000 0x7 0x0 | ||
| 649 | #define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x198 0x4e8 0x000 0x0 0x0 | ||
| 650 | #define MX53_PAD_EIM_EB1__GPIO2_29 0x198 0x4e8 0x000 0x1 0x0 | ||
| 651 | #define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x198 0x4e8 0x000 0x3 0x0 | ||
| 652 | #define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 0x198 0x4e8 0x000 0x4 0x0 | ||
| 653 | #define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 0x198 0x4e8 0x000 0x7 0x0 | ||
| 654 | #define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x19c 0x4ec 0x000 0x0 0x0 | ||
| 655 | #define MX53_PAD_EIM_DA0__GPIO3_0 0x19c 0x4ec 0x000 0x1 0x0 | ||
| 656 | #define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x19c 0x4ec 0x000 0x3 0x0 | ||
| 657 | #define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 0x19c 0x4ec 0x000 0x4 0x0 | ||
| 658 | #define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 0x19c 0x4ec 0x000 0x7 0x0 | ||
| 659 | #define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x1a0 0x4f0 0x000 0x0 0x0 | ||
| 660 | #define MX53_PAD_EIM_DA1__GPIO3_1 0x1a0 0x4f0 0x000 0x1 0x0 | ||
| 661 | #define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x1a0 0x4f0 0x000 0x3 0x0 | ||
| 662 | #define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 0x1a0 0x4f0 0x000 0x4 0x0 | ||
| 663 | #define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 0x1a0 0x4f0 0x000 0x7 0x0 | ||
| 664 | #define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x1a4 0x4f4 0x000 0x0 0x0 | ||
| 665 | #define MX53_PAD_EIM_DA2__GPIO3_2 0x1a4 0x4f4 0x000 0x1 0x0 | ||
| 666 | #define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x1a4 0x4f4 0x000 0x3 0x0 | ||
| 667 | #define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 0x1a4 0x4f4 0x000 0x4 0x0 | ||
| 668 | #define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 0x1a4 0x4f4 0x000 0x7 0x0 | ||
| 669 | #define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x1a8 0x4f8 0x000 0x0 0x0 | ||
| 670 | #define MX53_PAD_EIM_DA3__GPIO3_3 0x1a8 0x4f8 0x000 0x1 0x0 | ||
| 671 | #define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x1a8 0x4f8 0x000 0x3 0x0 | ||
| 672 | #define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 0x1a8 0x4f8 0x000 0x4 0x0 | ||
| 673 | #define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 0x1a8 0x4f8 0x000 0x7 0x0 | ||
| 674 | #define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x1ac 0x4fc 0x000 0x0 0x0 | ||
| 675 | #define MX53_PAD_EIM_DA4__GPIO3_4 0x1ac 0x4fc 0x000 0x1 0x0 | ||
| 676 | #define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x1ac 0x4fc 0x000 0x3 0x0 | ||
| 677 | #define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 0x1ac 0x4fc 0x000 0x4 0x0 | ||
| 678 | #define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 0x1ac 0x4fc 0x000 0x7 0x0 | ||
| 679 | #define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x1b0 0x500 0x000 0x0 0x0 | ||
| 680 | #define MX53_PAD_EIM_DA5__GPIO3_5 0x1b0 0x500 0x000 0x1 0x0 | ||
| 681 | #define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x1b0 0x500 0x000 0x3 0x0 | ||
| 682 | #define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 0x1b0 0x500 0x000 0x4 0x0 | ||
| 683 | #define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 0x1b0 0x500 0x000 0x7 0x0 | ||
| 684 | #define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x1b4 0x504 0x000 0x0 0x0 | ||
| 685 | #define MX53_PAD_EIM_DA6__GPIO3_6 0x1b4 0x504 0x000 0x1 0x0 | ||
| 686 | #define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x1b4 0x504 0x000 0x3 0x0 | ||
| 687 | #define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 0x1b4 0x504 0x000 0x4 0x0 | ||
| 688 | #define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 0x1b4 0x504 0x000 0x7 0x0 | ||
| 689 | #define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0x1b8 0x508 0x000 0x0 0x0 | ||
| 690 | #define MX53_PAD_EIM_DA7__GPIO3_7 0x1b8 0x508 0x000 0x1 0x0 | ||
| 691 | #define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x1b8 0x508 0x000 0x3 0x0 | ||
| 692 | #define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 0x1b8 0x508 0x000 0x4 0x0 | ||
| 693 | #define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 0x1b8 0x508 0x000 0x7 0x0 | ||
| 694 | #define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0x1bc 0x50c 0x000 0x0 0x0 | ||
| 695 | #define MX53_PAD_EIM_DA8__GPIO3_8 0x1bc 0x50c 0x000 0x1 0x0 | ||
| 696 | #define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x1bc 0x50c 0x000 0x3 0x0 | ||
| 697 | #define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 0x1bc 0x50c 0x000 0x4 0x0 | ||
| 698 | #define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 0x1bc 0x50c 0x000 0x7 0x0 | ||
| 699 | #define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0x1c0 0x510 0x000 0x0 0x0 | ||
| 700 | #define MX53_PAD_EIM_DA9__GPIO3_9 0x1c0 0x510 0x000 0x1 0x0 | ||
| 701 | #define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x1c0 0x510 0x000 0x3 0x0 | ||
| 702 | #define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 0x1c0 0x510 0x000 0x4 0x0 | ||
| 703 | #define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 0x1c0 0x510 0x000 0x7 0x0 | ||
| 704 | #define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0x1c4 0x514 0x000 0x0 0x0 | ||
| 705 | #define MX53_PAD_EIM_DA10__GPIO3_10 0x1c4 0x514 0x000 0x1 0x0 | ||
| 706 | #define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x1c4 0x514 0x000 0x3 0x0 | ||
| 707 | #define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 0x1c4 0x514 0x834 0x4 0x1 | ||
| 708 | #define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 0x1c4 0x514 0x000 0x7 0x0 | ||
| 709 | #define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0x1c8 0x518 0x000 0x0 0x0 | ||
| 710 | #define MX53_PAD_EIM_DA11__GPIO3_11 0x1c8 0x518 0x000 0x1 0x0 | ||
| 711 | #define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x1c8 0x518 0x000 0x3 0x0 | ||
| 712 | #define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 0x1c8 0x518 0x838 0x4 0x1 | ||
| 713 | #define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0x1cc 0x51c 0x000 0x0 0x0 | ||
| 714 | #define MX53_PAD_EIM_DA12__GPIO3_12 0x1cc 0x51c 0x000 0x1 0x0 | ||
| 715 | #define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x1cc 0x51c 0x000 0x3 0x0 | ||
| 716 | #define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 0x1cc 0x51c 0x83c 0x4 0x1 | ||
| 717 | #define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0x1d0 0x520 0x000 0x0 0x0 | ||
| 718 | #define MX53_PAD_EIM_DA13__GPIO3_13 0x1d0 0x520 0x000 0x1 0x0 | ||
| 719 | #define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x1d0 0x520 0x000 0x3 0x0 | ||
| 720 | #define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 0x1d0 0x520 0x76c 0x4 0x1 | ||
| 721 | #define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0x1d4 0x524 0x000 0x0 0x0 | ||
| 722 | #define MX53_PAD_EIM_DA14__GPIO3_14 0x1d4 0x524 0x000 0x1 0x0 | ||
| 723 | #define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x1d4 0x524 0x000 0x3 0x0 | ||
| 724 | #define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 0x1d4 0x524 0x000 0x4 0x0 | ||
| 725 | #define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0x1d8 0x528 0x000 0x0 0x0 | ||
| 726 | #define MX53_PAD_EIM_DA15__GPIO3_15 0x1d8 0x528 0x000 0x1 0x0 | ||
| 727 | #define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x1d8 0x528 0x000 0x3 0x0 | ||
| 728 | #define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x1d8 0x528 0x000 0x4 0x0 | ||
| 729 | #define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x1dc 0x52c 0x000 0x0 0x0 | ||
| 730 | #define MX53_PAD_NANDF_WE_B__GPIO6_12 0x1dc 0x52c 0x000 0x1 0x0 | ||
| 731 | #define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x1e0 0x530 0x000 0x0 0x0 | ||
| 732 | #define MX53_PAD_NANDF_RE_B__GPIO6_13 0x1e0 0x530 0x000 0x1 0x0 | ||
| 733 | #define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x1e4 0x534 0x000 0x0 0x0 | ||
| 734 | #define MX53_PAD_EIM_WAIT__GPIO5_0 0x1e4 0x534 0x000 0x1 0x0 | ||
| 735 | #define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 0x1e4 0x534 0x000 0x2 0x0 | ||
| 736 | #define MX53_PAD_LVDS1_TX3_P__GPIO6_22 0x1ec 0x000 0x000 0x0 0x0 | ||
| 737 | #define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x1ec 0x000 0x000 0x1 0x0 | ||
| 738 | #define MX53_PAD_LVDS1_TX2_P__GPIO6_24 0x1f0 0x000 0x000 0x0 0x0 | ||
| 739 | #define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x1f0 0x000 0x000 0x1 0x0 | ||
| 740 | #define MX53_PAD_LVDS1_CLK_P__GPIO6_26 0x1f4 0x000 0x000 0x0 0x0 | ||
| 741 | #define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x1f4 0x000 0x000 0x1 0x0 | ||
| 742 | #define MX53_PAD_LVDS1_TX1_P__GPIO6_28 0x1f8 0x000 0x000 0x0 0x0 | ||
| 743 | #define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x1f8 0x000 0x000 0x1 0x0 | ||
| 744 | #define MX53_PAD_LVDS1_TX0_P__GPIO6_30 0x1fc 0x000 0x000 0x0 0x0 | ||
| 745 | #define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x1fc 0x000 0x000 0x1 0x0 | ||
| 746 | #define MX53_PAD_LVDS0_TX3_P__GPIO7_22 0x200 0x000 0x000 0x0 0x0 | ||
| 747 | #define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x200 0x000 0x000 0x1 0x0 | ||
| 748 | #define MX53_PAD_LVDS0_CLK_P__GPIO7_24 0x204 0x000 0x000 0x0 0x0 | ||
| 749 | #define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x204 0x000 0x000 0x1 0x0 | ||
| 750 | #define MX53_PAD_LVDS0_TX2_P__GPIO7_26 0x208 0x000 0x000 0x0 0x0 | ||
| 751 | #define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x208 0x000 0x000 0x1 0x0 | ||
| 752 | #define MX53_PAD_LVDS0_TX1_P__GPIO7_28 0x20c 0x000 0x000 0x0 0x0 | ||
| 753 | #define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x20c 0x000 0x000 0x1 0x0 | ||
| 754 | #define MX53_PAD_LVDS0_TX0_P__GPIO7_30 0x210 0x000 0x000 0x0 0x0 | ||
| 755 | #define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x210 0x000 0x000 0x1 0x0 | ||
| 756 | #define MX53_PAD_GPIO_10__GPIO4_0 0x214 0x540 0x000 0x0 0x0 | ||
| 757 | #define MX53_PAD_GPIO_10__OSC32k_32K_OUT 0x214 0x540 0x000 0x1 0x0 | ||
| 758 | #define MX53_PAD_GPIO_11__GPIO4_1 0x218 0x544 0x000 0x0 0x0 | ||
| 759 | #define MX53_PAD_GPIO_12__GPIO4_2 0x21c 0x548 0x000 0x0 0x0 | ||
| 760 | #define MX53_PAD_GPIO_13__GPIO4_3 0x220 0x54c 0x000 0x0 0x0 | ||
| 761 | #define MX53_PAD_GPIO_14__GPIO4_4 0x224 0x550 0x000 0x0 0x0 | ||
| 762 | #define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x228 0x5a0 0x000 0x0 0x0 | ||
| 763 | #define MX53_PAD_NANDF_CLE__GPIO6_7 0x228 0x5a0 0x000 0x1 0x0 | ||
| 764 | #define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 0x228 0x5a0 0x000 0x7 0x0 | ||
| 765 | #define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x22c 0x5a4 0x000 0x0 0x0 | ||
| 766 | #define MX53_PAD_NANDF_ALE__GPIO6_8 0x22c 0x5a4 0x000 0x1 0x0 | ||
| 767 | #define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 0x22c 0x5a4 0x000 0x7 0x0 | ||
| 768 | #define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0x230 0x5a8 0x000 0x0 0x0 | ||
| 769 | #define MX53_PAD_NANDF_WP_B__GPIO6_9 0x230 0x5a8 0x000 0x1 0x0 | ||
| 770 | #define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 0x230 0x5a8 0x000 0x7 0x0 | ||
| 771 | #define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0x234 0x5ac 0x000 0x0 0x0 | ||
| 772 | #define MX53_PAD_NANDF_RB0__GPIO6_10 0x234 0x5ac 0x000 0x1 0x0 | ||
| 773 | #define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 0x234 0x5ac 0x000 0x7 0x0 | ||
| 774 | #define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x238 0x5b0 0x000 0x0 0x0 | ||
| 775 | #define MX53_PAD_NANDF_CS0__GPIO6_11 0x238 0x5b0 0x000 0x1 0x0 | ||
| 776 | #define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 0x238 0x5b0 0x000 0x7 0x0 | ||
| 777 | #define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x23c 0x5b4 0x000 0x0 0x0 | ||
| 778 | #define MX53_PAD_NANDF_CS1__GPIO6_14 0x23c 0x5b4 0x000 0x1 0x0 | ||
| 779 | #define MX53_PAD_NANDF_CS1__MLB_MLBCLK 0x23c 0x5b4 0x858 0x6 0x0 | ||
| 780 | #define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 0x23c 0x5b4 0x000 0x7 0x0 | ||
| 781 | #define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x240 0x5b8 0x000 0x0 0x0 | ||
| 782 | #define MX53_PAD_NANDF_CS2__GPIO6_15 0x240 0x5b8 0x000 0x1 0x0 | ||
| 783 | #define MX53_PAD_NANDF_CS2__IPU_SISG_0 0x240 0x5b8 0x000 0x2 0x0 | ||
| 784 | #define MX53_PAD_NANDF_CS2__ESAI1_TX0 0x240 0x5b8 0x7e4 0x3 0x0 | ||
| 785 | #define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 0x240 0x5b8 0x000 0x4 0x0 | ||
| 786 | #define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 0x240 0x5b8 0x000 0x5 0x0 | ||
| 787 | #define MX53_PAD_NANDF_CS2__MLB_MLBSIG 0x240 0x5b8 0x860 0x6 0x0 | ||
| 788 | #define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 0x240 0x5b8 0x000 0x7 0x0 | ||
| 789 | #define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x244 0x5bc 0x000 0x0 0x0 | ||
| 790 | #define MX53_PAD_NANDF_CS3__GPIO6_16 0x244 0x5bc 0x000 0x1 0x0 | ||
| 791 | #define MX53_PAD_NANDF_CS3__IPU_SISG_1 0x244 0x5bc 0x000 0x2 0x0 | ||
| 792 | #define MX53_PAD_NANDF_CS3__ESAI1_TX1 0x244 0x5bc 0x7e8 0x3 0x0 | ||
| 793 | #define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 0x244 0x5bc 0x000 0x4 0x0 | ||
| 794 | #define MX53_PAD_NANDF_CS3__MLB_MLBDAT 0x244 0x5bc 0x85c 0x6 0x0 | ||
| 795 | #define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 0x244 0x5bc 0x000 0x7 0x0 | ||
| 796 | #define MX53_PAD_FEC_MDIO__FEC_MDIO 0x248 0x5c4 0x804 0x0 0x1 | ||
| 797 | #define MX53_PAD_FEC_MDIO__GPIO1_22 0x248 0x5c4 0x000 0x1 0x0 | ||
| 798 | #define MX53_PAD_FEC_MDIO__ESAI1_SCKR 0x248 0x5c4 0x7dc 0x2 0x0 | ||
| 799 | #define MX53_PAD_FEC_MDIO__FEC_COL 0x248 0x5c4 0x800 0x3 0x1 | ||
| 800 | #define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 0x248 0x5c4 0x000 0x4 0x0 | ||
| 801 | #define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 0x248 0x5c4 0x000 0x5 0x0 | ||
| 802 | #define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 0x248 0x5c4 0x000 0x6 0x0 | ||
| 803 | #define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x24c 0x5c8 0x000 0x0 0x0 | ||
| 804 | #define MX53_PAD_FEC_REF_CLK__GPIO1_23 0x24c 0x5c8 0x000 0x1 0x0 | ||
| 805 | #define MX53_PAD_FEC_REF_CLK__ESAI1_FSR 0x24c 0x5c8 0x7cc 0x2 0x0 | ||
| 806 | #define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 0x24c 0x5c8 0x000 0x5 0x0 | ||
| 807 | #define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 0x24c 0x5c8 0x000 0x6 0x0 | ||
| 808 | #define MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x250 0x5cc 0x000 0x0 0x0 | ||
| 809 | #define MX53_PAD_FEC_RX_ER__GPIO1_24 0x250 0x5cc 0x000 0x1 0x0 | ||
| 810 | #define MX53_PAD_FEC_RX_ER__ESAI1_HCKR 0x250 0x5cc 0x7d4 0x2 0x0 | ||
| 811 | #define MX53_PAD_FEC_RX_ER__FEC_RX_CLK 0x250 0x5cc 0x808 0x3 0x1 | ||
| 812 | #define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 0x250 0x5cc 0x000 0x4 0x0 | ||
| 813 | #define MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x254 0x5d0 0x000 0x0 0x0 | ||
| 814 | #define MX53_PAD_FEC_CRS_DV__GPIO1_25 0x254 0x5d0 0x000 0x1 0x0 | ||
| 815 | #define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 0x254 0x5d0 0x7e0 0x2 0x0 | ||
| 816 | #define MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x258 0x5d4 0x000 0x0 0x0 | ||
| 817 | #define MX53_PAD_FEC_RXD1__GPIO1_26 0x258 0x5d4 0x000 0x1 0x0 | ||
| 818 | #define MX53_PAD_FEC_RXD1__ESAI1_FST 0x258 0x5d4 0x7d0 0x2 0x0 | ||
| 819 | #define MX53_PAD_FEC_RXD1__MLB_MLBSIG 0x258 0x5d4 0x860 0x3 0x1 | ||
| 820 | #define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 0x258 0x5d4 0x000 0x4 0x0 | ||
| 821 | #define MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x25c 0x5d8 0x000 0x0 0x0 | ||
| 822 | #define MX53_PAD_FEC_RXD0__GPIO1_27 0x25c 0x5d8 0x000 0x1 0x0 | ||
| 823 | #define MX53_PAD_FEC_RXD0__ESAI1_HCKT 0x25c 0x5d8 0x7d8 0x2 0x0 | ||
| 824 | #define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 0x25c 0x5d8 0x000 0x3 0x0 | ||
| 825 | #define MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x260 0x5dc 0x000 0x0 0x0 | ||
| 826 | #define MX53_PAD_FEC_TX_EN__GPIO1_28 0x260 0x5dc 0x000 0x1 0x0 | ||
| 827 | #define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 0x260 0x5dc 0x7f0 0x2 0x0 | ||
| 828 | #define MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x264 0x5e0 0x000 0x0 0x0 | ||
| 829 | #define MX53_PAD_FEC_TXD1__GPIO1_29 0x264 0x5e0 0x000 0x1 0x0 | ||
| 830 | #define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 0x264 0x5e0 0x7ec 0x2 0x0 | ||
| 831 | #define MX53_PAD_FEC_TXD1__MLB_MLBCLK 0x264 0x5e0 0x858 0x3 0x1 | ||
| 832 | #define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 0x264 0x5e0 0x000 0x4 0x0 | ||
| 833 | #define MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x268 0x5e4 0x000 0x0 0x0 | ||
| 834 | #define MX53_PAD_FEC_TXD0__GPIO1_30 0x268 0x5e4 0x000 0x1 0x0 | ||
| 835 | #define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 0x268 0x5e4 0x7f4 0x2 0x0 | ||
| 836 | #define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 0x268 0x5e4 0x000 0x7 0x0 | ||
| 837 | #define MX53_PAD_FEC_MDC__FEC_MDC 0x26c 0x5e8 0x000 0x0 0x0 | ||
| 838 | #define MX53_PAD_FEC_MDC__GPIO1_31 0x26c 0x5e8 0x000 0x1 0x0 | ||
| 839 | #define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 0x26c 0x5e8 0x7f8 0x2 0x0 | ||
| 840 | #define MX53_PAD_FEC_MDC__MLB_MLBDAT 0x26c 0x5e8 0x85c 0x3 0x1 | ||
| 841 | #define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 0x26c 0x5e8 0x000 0x4 0x0 | ||
| 842 | #define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 0x26c 0x5e8 0x000 0x7 0x0 | ||
| 843 | #define MX53_PAD_PATA_DIOW__PATA_DIOW 0x270 0x5f0 0x000 0x0 0x0 | ||
| 844 | #define MX53_PAD_PATA_DIOW__GPIO6_17 0x270 0x5f0 0x000 0x1 0x0 | ||
| 845 | #define MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x270 0x5f0 0x000 0x3 0x0 | ||
| 846 | #define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 0x270 0x5f0 0x000 0x7 0x0 | ||
| 847 | #define MX53_PAD_PATA_DMACK__PATA_DMACK 0x274 0x5f4 0x000 0x0 0x0 | ||
| 848 | #define MX53_PAD_PATA_DMACK__GPIO6_18 0x274 0x5f4 0x000 0x1 0x0 | ||
| 849 | #define MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x274 0x5f4 0x878 0x3 0x3 | ||
| 850 | #define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 0x274 0x5f4 0x000 0x7 0x0 | ||
| 851 | #define MX53_PAD_PATA_DMARQ__PATA_DMARQ 0x278 0x5f8 0x000 0x0 0x0 | ||
| 852 | #define MX53_PAD_PATA_DMARQ__GPIO7_0 0x278 0x5f8 0x000 0x1 0x0 | ||
| 853 | #define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x278 0x5f8 0x000 0x3 0x0 | ||
| 854 | #define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 0x278 0x5f8 0x000 0x5 0x0 | ||
| 855 | #define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 0x278 0x5f8 0x000 0x7 0x0 | ||
| 856 | #define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 0x27c 0x5fc 0x000 0x0 0x0 | ||
| 857 | #define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 0x27c 0x5fc 0x000 0x1 0x0 | ||
| 858 | #define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x27c 0x5fc 0x880 0x3 0x3 | ||
| 859 | #define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 0x27c 0x5fc 0x000 0x5 0x0 | ||
| 860 | #define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 0x27c 0x5fc 0x000 0x7 0x0 | ||
| 861 | #define MX53_PAD_PATA_INTRQ__PATA_INTRQ 0x280 0x600 0x000 0x0 0x0 | ||
| 862 | #define MX53_PAD_PATA_INTRQ__GPIO7_2 0x280 0x600 0x000 0x1 0x0 | ||
| 863 | #define MX53_PAD_PATA_INTRQ__UART2_CTS 0x280 0x600 0x000 0x3 0x0 | ||
| 864 | #define MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x280 0x600 0x000 0x4 0x0 | ||
| 865 | #define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 0x280 0x600 0x000 0x5 0x0 | ||
| 866 | #define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 0x280 0x600 0x000 0x7 0x0 | ||
| 867 | #define MX53_PAD_PATA_DIOR__PATA_DIOR 0x284 0x604 0x000 0x0 0x0 | ||
| 868 | #define MX53_PAD_PATA_DIOR__GPIO7_3 0x284 0x604 0x000 0x1 0x0 | ||
| 869 | #define MX53_PAD_PATA_DIOR__UART2_RTS 0x284 0x604 0x87c 0x3 0x3 | ||
| 870 | #define MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x284 0x604 0x760 0x4 0x1 | ||
| 871 | #define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 0x284 0x604 0x000 0x7 0x0 | ||
| 872 | #define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 0x288 0x608 0x000 0x0 0x0 | ||
| 873 | #define MX53_PAD_PATA_RESET_B__GPIO7_4 0x288 0x608 0x000 0x1 0x0 | ||
| 874 | #define MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x288 0x608 0x000 0x2 0x0 | ||
| 875 | #define MX53_PAD_PATA_RESET_B__UART1_CTS 0x288 0x608 0x000 0x3 0x0 | ||
| 876 | #define MX53_PAD_PATA_RESET_B__CAN2_TXCAN 0x288 0x608 0x000 0x4 0x0 | ||
| 877 | #define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 0x288 0x608 0x000 0x7 0x0 | ||
| 878 | #define MX53_PAD_PATA_IORDY__PATA_IORDY 0x28c 0x60c 0x000 0x0 0x0 | ||
| 879 | #define MX53_PAD_PATA_IORDY__GPIO7_5 0x28c 0x60c 0x000 0x1 0x0 | ||
| 880 | #define MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x28c 0x60c 0x000 0x2 0x0 | ||
| 881 | #define MX53_PAD_PATA_IORDY__UART1_RTS 0x28c 0x60c 0x874 0x3 0x3 | ||
| 882 | #define MX53_PAD_PATA_IORDY__CAN2_RXCAN 0x28c 0x60c 0x764 0x4 0x1 | ||
| 883 | #define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 0x28c 0x60c 0x000 0x7 0x0 | ||
| 884 | #define MX53_PAD_PATA_DA_0__PATA_DA_0 0x290 0x610 0x000 0x0 0x0 | ||
| 885 | #define MX53_PAD_PATA_DA_0__GPIO7_6 0x290 0x610 0x000 0x1 0x0 | ||
| 886 | #define MX53_PAD_PATA_DA_0__ESDHC3_RST 0x290 0x610 0x000 0x2 0x0 | ||
| 887 | #define MX53_PAD_PATA_DA_0__OWIRE_LINE 0x290 0x610 0x864 0x4 0x0 | ||
| 888 | #define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 0x290 0x610 0x000 0x7 0x0 | ||
| 889 | #define MX53_PAD_PATA_DA_1__PATA_DA_1 0x294 0x614 0x000 0x0 0x0 | ||
| 890 | #define MX53_PAD_PATA_DA_1__GPIO7_7 0x294 0x614 0x000 0x1 0x0 | ||
| 891 | #define MX53_PAD_PATA_DA_1__ESDHC4_CMD 0x294 0x614 0x000 0x2 0x0 | ||
| 892 | #define MX53_PAD_PATA_DA_1__UART3_CTS 0x294 0x614 0x000 0x4 0x0 | ||
| 893 | #define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 0x294 0x614 0x000 0x7 0x0 | ||
| 894 | #define MX53_PAD_PATA_DA_2__PATA_DA_2 0x298 0x618 0x000 0x0 0x0 | ||
| 895 | #define MX53_PAD_PATA_DA_2__GPIO7_8 0x298 0x618 0x000 0x1 0x0 | ||
| 896 | #define MX53_PAD_PATA_DA_2__ESDHC4_CLK 0x298 0x618 0x000 0x2 0x0 | ||
| 897 | #define MX53_PAD_PATA_DA_2__UART3_RTS 0x298 0x618 0x884 0x4 0x5 | ||
| 898 | #define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 0x298 0x618 0x000 0x7 0x0 | ||
| 899 | #define MX53_PAD_PATA_CS_0__PATA_CS_0 0x29c 0x61c 0x000 0x0 0x0 | ||
| 900 | #define MX53_PAD_PATA_CS_0__GPIO7_9 0x29c 0x61c 0x000 0x1 0x0 | ||
| 901 | #define MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x29c 0x61c 0x000 0x4 0x0 | ||
| 902 | #define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 0x29c 0x61c 0x000 0x7 0x0 | ||
| 903 | #define MX53_PAD_PATA_CS_1__PATA_CS_1 0x2a0 0x620 0x000 0x0 0x0 | ||
| 904 | #define MX53_PAD_PATA_CS_1__GPIO7_10 0x2a0 0x620 0x000 0x1 0x0 | ||
| 905 | #define MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x2a0 0x620 0x888 0x4 0x3 | ||
| 906 | #define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 0x2a0 0x620 0x000 0x7 0x0 | ||
| 907 | #define MX53_PAD_PATA_DATA0__PATA_DATA_0 0x2a4 0x628 0x000 0x0 0x0 | ||
| 908 | #define MX53_PAD_PATA_DATA0__GPIO2_0 0x2a4 0x628 0x000 0x1 0x0 | ||
| 909 | #define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0x2a4 0x628 0x000 0x3 0x0 | ||
| 910 | #define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x2a4 0x628 0x000 0x4 0x0 | ||
| 911 | #define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 0x2a4 0x628 0x000 0x5 0x0 | ||
| 912 | #define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 0x2a4 0x628 0x000 0x6 0x0 | ||
| 913 | #define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 0x2a4 0x628 0x000 0x7 0x0 | ||
| 914 | #define MX53_PAD_PATA_DATA1__PATA_DATA_1 0x2a8 0x62c 0x000 0x0 0x0 | ||
| 915 | #define MX53_PAD_PATA_DATA1__GPIO2_1 0x2a8 0x62c 0x000 0x1 0x0 | ||
| 916 | #define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0x2a8 0x62c 0x000 0x3 0x0 | ||
| 917 | #define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x2a8 0x62c 0x000 0x4 0x0 | ||
| 918 | #define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 0x2a8 0x62c 0x000 0x5 0x0 | ||
| 919 | #define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 0x2a8 0x62c 0x000 0x6 0x0 | ||
| 920 | #define MX53_PAD_PATA_DATA2__PATA_DATA_2 0x2ac 0x630 0x000 0x0 0x0 | ||
| 921 | #define MX53_PAD_PATA_DATA2__GPIO2_2 0x2ac 0x630 0x000 0x1 0x0 | ||
| 922 | #define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0x2ac 0x630 0x000 0x3 0x0 | ||
| 923 | #define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x2ac 0x630 0x000 0x4 0x0 | ||
| 924 | #define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 0x2ac 0x630 0x000 0x5 0x0 | ||
| 925 | #define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 0x2ac 0x630 0x000 0x6 0x0 | ||
| 926 | #define MX53_PAD_PATA_DATA3__PATA_DATA_3 0x2b0 0x634 0x000 0x0 0x0 | ||
| 927 | #define MX53_PAD_PATA_DATA3__GPIO2_3 0x2b0 0x634 0x000 0x1 0x0 | ||
| 928 | #define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0x2b0 0x634 0x000 0x3 0x0 | ||
| 929 | #define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x2b0 0x634 0x000 0x4 0x0 | ||
| 930 | #define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 0x2b0 0x634 0x000 0x5 0x0 | ||
| 931 | #define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 0x2b0 0x634 0x000 0x6 0x0 | ||
| 932 | #define MX53_PAD_PATA_DATA4__PATA_DATA_4 0x2b4 0x638 0x000 0x0 0x0 | ||
| 933 | #define MX53_PAD_PATA_DATA4__GPIO2_4 0x2b4 0x638 0x000 0x1 0x0 | ||
| 934 | #define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0x2b4 0x638 0x000 0x3 0x0 | ||
| 935 | #define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 0x2b4 0x638 0x000 0x4 0x0 | ||
| 936 | #define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 0x2b4 0x638 0x000 0x5 0x0 | ||
| 937 | #define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 0x2b4 0x638 0x000 0x6 0x0 | ||
| 938 | #define MX53_PAD_PATA_DATA5__PATA_DATA_5 0x2b8 0x63c 0x000 0x0 0x0 | ||
| 939 | #define MX53_PAD_PATA_DATA5__GPIO2_5 0x2b8 0x63c 0x000 0x1 0x0 | ||
| 940 | #define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0x2b8 0x63c 0x000 0x3 0x0 | ||
| 941 | #define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 0x2b8 0x63c 0x000 0x4 0x0 | ||
| 942 | #define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 0x2b8 0x63c 0x000 0x5 0x0 | ||
| 943 | #define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 0x2b8 0x63c 0x000 0x6 0x0 | ||
| 944 | #define MX53_PAD_PATA_DATA6__PATA_DATA_6 0x2bc 0x640 0x000 0x0 0x0 | ||
| 945 | #define MX53_PAD_PATA_DATA6__GPIO2_6 0x2bc 0x640 0x000 0x1 0x0 | ||
| 946 | #define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0x2bc 0x640 0x000 0x3 0x0 | ||
| 947 | #define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 0x2bc 0x640 0x000 0x4 0x0 | ||
| 948 | #define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 0x2bc 0x640 0x000 0x5 0x0 | ||
| 949 | #define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 0x2bc 0x640 0x000 0x6 0x0 | ||
| 950 | #define MX53_PAD_PATA_DATA7__PATA_DATA_7 0x2c0 0x644 0x000 0x0 0x0 | ||
| 951 | #define MX53_PAD_PATA_DATA7__GPIO2_7 0x2c0 0x644 0x000 0x1 0x0 | ||
| 952 | #define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0x2c0 0x644 0x000 0x3 0x0 | ||
| 953 | #define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 0x2c0 0x644 0x000 0x4 0x0 | ||
| 954 | #define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 0x2c0 0x644 0x000 0x5 0x0 | ||
| 955 | #define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 0x2c0 0x644 0x000 0x6 0x0 | ||
| 956 | #define MX53_PAD_PATA_DATA8__PATA_DATA_8 0x2c4 0x648 0x000 0x0 0x0 | ||
| 957 | #define MX53_PAD_PATA_DATA8__GPIO2_8 0x2c4 0x648 0x000 0x1 0x0 | ||
| 958 | #define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x2c4 0x648 0x000 0x2 0x0 | ||
| 959 | #define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0x2c4 0x648 0x000 0x3 0x0 | ||
| 960 | #define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x2c4 0x648 0x000 0x4 0x0 | ||
| 961 | #define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 0x2c4 0x648 0x000 0x5 0x0 | ||
| 962 | #define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 0x2c4 0x648 0x000 0x6 0x0 | ||
| 963 | #define MX53_PAD_PATA_DATA9__PATA_DATA_9 0x2c8 0x64c 0x000 0x0 0x0 | ||
| 964 | #define MX53_PAD_PATA_DATA9__GPIO2_9 0x2c8 0x64c 0x000 0x1 0x0 | ||
| 965 | #define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x2c8 0x64c 0x000 0x2 0x0 | ||
| 966 | #define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0x2c8 0x64c 0x000 0x3 0x0 | ||
| 967 | #define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x2c8 0x64c 0x000 0x4 0x0 | ||
| 968 | #define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 0x2c8 0x64c 0x000 0x5 0x0 | ||
| 969 | #define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 0x2c8 0x64c 0x000 0x6 0x0 | ||
| 970 | #define MX53_PAD_PATA_DATA10__PATA_DATA_10 0x2cc 0x650 0x000 0x0 0x0 | ||
| 971 | #define MX53_PAD_PATA_DATA10__GPIO2_10 0x2cc 0x650 0x000 0x1 0x0 | ||
| 972 | #define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x2cc 0x650 0x000 0x2 0x0 | ||
| 973 | #define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0x2cc 0x650 0x000 0x3 0x0 | ||
| 974 | #define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x2cc 0x650 0x000 0x4 0x0 | ||
| 975 | #define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 0x2cc 0x650 0x000 0x5 0x0 | ||
| 976 | #define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 0x2cc 0x650 0x000 0x6 0x0 | ||
| 977 | #define MX53_PAD_PATA_DATA11__PATA_DATA_11 0x2d0 0x654 0x000 0x0 0x0 | ||
| 978 | #define MX53_PAD_PATA_DATA11__GPIO2_11 0x2d0 0x654 0x000 0x1 0x0 | ||
| 979 | #define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x2d0 0x654 0x000 0x2 0x0 | ||
| 980 | #define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0x2d0 0x654 0x000 0x3 0x0 | ||
| 981 | #define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x2d0 0x654 0x000 0x4 0x0 | ||
| 982 | #define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 0x2d0 0x654 0x000 0x5 0x0 | ||
| 983 | #define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 0x2d0 0x654 0x000 0x6 0x0 | ||
| 984 | #define MX53_PAD_PATA_DATA12__PATA_DATA_12 0x2d4 0x658 0x000 0x0 0x0 | ||
| 985 | #define MX53_PAD_PATA_DATA12__GPIO2_12 0x2d4 0x658 0x000 0x1 0x0 | ||
| 986 | #define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 0x2d4 0x658 0x000 0x2 0x0 | ||
| 987 | #define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0x2d4 0x658 0x000 0x3 0x0 | ||
| 988 | #define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 0x2d4 0x658 0x000 0x4 0x0 | ||
| 989 | #define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 0x2d4 0x658 0x000 0x5 0x0 | ||
| 990 | #define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 0x2d4 0x658 0x000 0x6 0x0 | ||
| 991 | #define MX53_PAD_PATA_DATA13__PATA_DATA_13 0x2d8 0x65c 0x000 0x0 0x0 | ||
| 992 | #define MX53_PAD_PATA_DATA13__GPIO2_13 0x2d8 0x65c 0x000 0x1 0x0 | ||
| 993 | #define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 0x2d8 0x65c 0x000 0x2 0x0 | ||
| 994 | #define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0x2d8 0x65c 0x000 0x3 0x0 | ||
| 995 | #define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 0x2d8 0x65c 0x000 0x4 0x0 | ||
| 996 | #define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 0x2d8 0x65c 0x000 0x5 0x0 | ||
| 997 | #define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 0x2d8 0x65c 0x000 0x6 0x0 | ||
| 998 | #define MX53_PAD_PATA_DATA14__PATA_DATA_14 0x2dc 0x660 0x000 0x0 0x0 | ||
| 999 | #define MX53_PAD_PATA_DATA14__GPIO2_14 0x2dc 0x660 0x000 0x1 0x0 | ||
| 1000 | #define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 0x2dc 0x660 0x000 0x2 0x0 | ||
| 1001 | #define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0x2dc 0x660 0x000 0x3 0x0 | ||
| 1002 | #define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 0x2dc 0x660 0x000 0x4 0x0 | ||
| 1003 | #define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 0x2dc 0x660 0x000 0x5 0x0 | ||
| 1004 | #define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 0x2dc 0x660 0x000 0x6 0x0 | ||
| 1005 | #define MX53_PAD_PATA_DATA15__PATA_DATA_15 0x2e0 0x664 0x000 0x0 0x0 | ||
| 1006 | #define MX53_PAD_PATA_DATA15__GPIO2_15 0x2e0 0x664 0x000 0x1 0x0 | ||
| 1007 | #define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 0x2e0 0x664 0x000 0x2 0x0 | ||
| 1008 | #define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0x2e0 0x664 0x000 0x3 0x0 | ||
| 1009 | #define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 0x2e0 0x664 0x000 0x4 0x0 | ||
| 1010 | #define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 0x2e0 0x664 0x000 0x5 0x0 | ||
| 1011 | #define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 0x2e0 0x664 0x000 0x6 0x0 | ||
| 1012 | #define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x2e4 0x66c 0x000 0x0 0x0 | ||
| 1013 | #define MX53_PAD_SD1_DATA0__GPIO1_16 0x2e4 0x66c 0x000 0x1 0x0 | ||
| 1014 | #define MX53_PAD_SD1_DATA0__GPT_CAPIN1 0x2e4 0x66c 0x000 0x3 0x0 | ||
| 1015 | #define MX53_PAD_SD1_DATA0__CSPI_MISO 0x2e4 0x66c 0x784 0x5 0x2 | ||
| 1016 | #define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 0x2e4 0x66c 0x778 0x7 0x0 | ||
| 1017 | #define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x2e8 0x670 0x000 0x0 0x0 | ||
| 1018 | #define MX53_PAD_SD1_DATA1__GPIO1_17 0x2e8 0x670 0x000 0x1 0x0 | ||
| 1019 | #define MX53_PAD_SD1_DATA1__GPT_CAPIN2 0x2e8 0x670 0x000 0x3 0x0 | ||
| 1020 | #define MX53_PAD_SD1_DATA1__CSPI_SS0 0x2e8 0x670 0x78c 0x5 0x3 | ||
| 1021 | #define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 0x2e8 0x670 0x77c 0x7 0x1 | ||
| 1022 | #define MX53_PAD_SD1_CMD__ESDHC1_CMD 0x2ec 0x674 0x000 0x0 0x0 | ||
| 1023 | #define MX53_PAD_SD1_CMD__GPIO1_18 0x2ec 0x674 0x000 0x1 0x0 | ||
| 1024 | #define MX53_PAD_SD1_CMD__GPT_CMPOUT1 0x2ec 0x674 0x000 0x3 0x0 | ||
| 1025 | #define MX53_PAD_SD1_CMD__CSPI_MOSI 0x2ec 0x674 0x788 0x5 0x2 | ||
| 1026 | #define MX53_PAD_SD1_CMD__CCM_PLL1_BYP 0x2ec 0x674 0x770 0x7 0x0 | ||
| 1027 | #define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x2f0 0x678 0x000 0x0 0x0 | ||
| 1028 | #define MX53_PAD_SD1_DATA2__GPIO1_19 0x2f0 0x678 0x000 0x1 0x0 | ||
| 1029 | #define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 0x2f0 0x678 0x000 0x2 0x0 | ||
| 1030 | #define MX53_PAD_SD1_DATA2__PWM2_PWMO 0x2f0 0x678 0x000 0x3 0x0 | ||
| 1031 | #define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 0x2f0 0x678 0x000 0x4 0x0 | ||
| 1032 | #define MX53_PAD_SD1_DATA2__CSPI_SS1 0x2f0 0x678 0x790 0x5 0x2 | ||
| 1033 | #define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 0x2f0 0x678 0x000 0x6 0x0 | ||
| 1034 | #define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 0x2f0 0x678 0x774 0x7 0x0 | ||
| 1035 | #define MX53_PAD_SD1_CLK__ESDHC1_CLK 0x2f4 0x67c 0x000 0x0 0x0 | ||
| 1036 | #define MX53_PAD_SD1_CLK__GPIO1_20 0x2f4 0x67c 0x000 0x1 0x0 | ||
| 1037 | #define MX53_PAD_SD1_CLK__OSC32k_32K_OUT 0x2f4 0x67c 0x000 0x2 0x0 | ||
| 1038 | #define MX53_PAD_SD1_CLK__GPT_CLKIN 0x2f4 0x67c 0x000 0x3 0x0 | ||
| 1039 | #define MX53_PAD_SD1_CLK__CSPI_SCLK 0x2f4 0x67c 0x780 0x5 0x2 | ||
| 1040 | #define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 0x2f4 0x67c 0x000 0x7 0x0 | ||
| 1041 | #define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x2f8 0x680 0x000 0x0 0x0 | ||
| 1042 | #define MX53_PAD_SD1_DATA3__GPIO1_21 0x2f8 0x680 0x000 0x1 0x0 | ||
| 1043 | #define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 0x2f8 0x680 0x000 0x2 0x0 | ||
| 1044 | #define MX53_PAD_SD1_DATA3__PWM1_PWMO 0x2f8 0x680 0x000 0x3 0x0 | ||
| 1045 | #define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 0x2f8 0x680 0x000 0x4 0x0 | ||
| 1046 | #define MX53_PAD_SD1_DATA3__CSPI_SS2 0x2f8 0x680 0x794 0x5 0x2 | ||
| 1047 | #define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 0x2f8 0x680 0x000 0x6 0x0 | ||
| 1048 | #define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 0x2f8 0x680 0x000 0x7 0x0 | ||
| 1049 | #define MX53_PAD_SD2_CLK__ESDHC2_CLK 0x2fc 0x688 0x000 0x0 0x0 | ||
| 1050 | #define MX53_PAD_SD2_CLK__GPIO1_10 0x2fc 0x688 0x000 0x1 0x0 | ||
| 1051 | #define MX53_PAD_SD2_CLK__KPP_COL_5 0x2fc 0x688 0x840 0x2 0x2 | ||
| 1052 | #define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 0x2fc 0x688 0x73c 0x3 0x1 | ||
| 1053 | #define MX53_PAD_SD2_CLK__CSPI_SCLK 0x2fc 0x688 0x780 0x5 0x3 | ||
| 1054 | #define MX53_PAD_SD2_CLK__SCC_RANDOM_V 0x2fc 0x688 0x000 0x7 0x0 | ||
| 1055 | #define MX53_PAD_SD2_CMD__ESDHC2_CMD 0x300 0x68c 0x000 0x0 0x0 | ||
| 1056 | #define MX53_PAD_SD2_CMD__GPIO1_11 0x300 0x68c 0x000 0x1 0x0 | ||
| 1057 | #define MX53_PAD_SD2_CMD__KPP_ROW_5 0x300 0x68c 0x84c 0x2 0x1 | ||
| 1058 | #define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 0x300 0x68c 0x738 0x3 0x1 | ||
| 1059 | #define MX53_PAD_SD2_CMD__CSPI_MOSI 0x300 0x68c 0x788 0x5 0x3 | ||
| 1060 | #define MX53_PAD_SD2_CMD__SCC_RANDOM 0x300 0x68c 0x000 0x7 0x0 | ||
| 1061 | #define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x304 0x690 0x000 0x0 0x0 | ||
| 1062 | #define MX53_PAD_SD2_DATA3__GPIO1_12 0x304 0x690 0x000 0x1 0x0 | ||
| 1063 | #define MX53_PAD_SD2_DATA3__KPP_COL_6 0x304 0x690 0x844 0x2 0x1 | ||
| 1064 | #define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x304 0x690 0x740 0x3 0x1 | ||
| 1065 | #define MX53_PAD_SD2_DATA3__CSPI_SS2 0x304 0x690 0x794 0x5 0x3 | ||
| 1066 | #define MX53_PAD_SD2_DATA3__SJC_DONE 0x304 0x690 0x000 0x7 0x0 | ||
| 1067 | #define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x308 0x694 0x000 0x0 0x0 | ||
| 1068 | #define MX53_PAD_SD2_DATA2__GPIO1_13 0x308 0x694 0x000 0x1 0x0 | ||
| 1069 | #define MX53_PAD_SD2_DATA2__KPP_ROW_6 0x308 0x694 0x850 0x2 0x1 | ||
| 1070 | #define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x308 0x694 0x734 0x3 0x1 | ||
| 1071 | #define MX53_PAD_SD2_DATA2__CSPI_SS1 0x308 0x694 0x790 0x5 0x3 | ||
| 1072 | #define MX53_PAD_SD2_DATA2__SJC_FAIL 0x308 0x694 0x000 0x7 0x0 | ||
| 1073 | #define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x30c 0x698 0x000 0x0 0x0 | ||
| 1074 | #define MX53_PAD_SD2_DATA1__GPIO1_14 0x30c 0x698 0x000 0x1 0x0 | ||
| 1075 | #define MX53_PAD_SD2_DATA1__KPP_COL_7 0x30c 0x698 0x848 0x2 0x1 | ||
| 1076 | #define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x30c 0x698 0x744 0x3 0x1 | ||
| 1077 | #define MX53_PAD_SD2_DATA1__CSPI_SS0 0x30c 0x698 0x78c 0x5 0x4 | ||
| 1078 | #define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 0x30c 0x698 0x000 0x7 0x0 | ||
| 1079 | #define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x310 0x69c 0x000 0x0 0x0 | ||
| 1080 | #define MX53_PAD_SD2_DATA0__GPIO1_15 0x310 0x69c 0x000 0x1 0x0 | ||
| 1081 | #define MX53_PAD_SD2_DATA0__KPP_ROW_7 0x310 0x69c 0x854 0x2 0x1 | ||
| 1082 | #define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x310 0x69c 0x730 0x3 0x1 | ||
| 1083 | #define MX53_PAD_SD2_DATA0__CSPI_MISO 0x310 0x69c 0x784 0x5 0x3 | ||
| 1084 | #define MX53_PAD_SD2_DATA0__RTIC_DONE_INT 0x310 0x69c 0x000 0x7 0x0 | ||
| 1085 | #define MX53_PAD_GPIO_0__CCM_CLKO 0x314 0x6a4 0x000 0x0 0x0 | ||
| 1086 | #define MX53_PAD_GPIO_0__GPIO1_0 0x314 0x6a4 0x000 0x1 0x0 | ||
| 1087 | #define MX53_PAD_GPIO_0__KPP_COL_5 0x314 0x6a4 0x840 0x2 0x3 | ||
| 1088 | #define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x314 0x6a4 0x000 0x3 0x0 | ||
| 1089 | #define MX53_PAD_GPIO_0__EPIT1_EPITO 0x314 0x6a4 0x000 0x4 0x0 | ||
| 1090 | #define MX53_PAD_GPIO_0__SRTC_ALARM_DEB 0x314 0x6a4 0x000 0x5 0x0 | ||
| 1091 | #define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 0x314 0x6a4 0x000 0x6 0x0 | ||
| 1092 | #define MX53_PAD_GPIO_0__CSU_TD 0x314 0x6a4 0x000 0x7 0x0 | ||
| 1093 | #define MX53_PAD_GPIO_1__ESAI1_SCKR 0x318 0x6a8 0x7dc 0x0 0x1 | ||
| 1094 | #define MX53_PAD_GPIO_1__GPIO1_1 0x318 0x6a8 0x000 0x1 0x0 | ||
| 1095 | #define MX53_PAD_GPIO_1__KPP_ROW_5 0x318 0x6a8 0x84c 0x2 0x2 | ||
| 1096 | #define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 0x318 0x6a8 0x000 0x3 0x0 | ||
| 1097 | #define MX53_PAD_GPIO_1__PWM2_PWMO 0x318 0x6a8 0x000 0x4 0x0 | ||
| 1098 | #define MX53_PAD_GPIO_1__WDOG2_WDOG_B 0x318 0x6a8 0x000 0x5 0x0 | ||
| 1099 | #define MX53_PAD_GPIO_1__ESDHC1_CD 0x318 0x6a8 0x000 0x6 0x0 | ||
| 1100 | #define MX53_PAD_GPIO_1__SRC_TESTER_ACK 0x318 0x6a8 0x000 0x7 0x0 | ||
| 1101 | #define MX53_PAD_GPIO_9__ESAI1_FSR 0x31c 0x6ac 0x7cc 0x0 0x1 | ||
| 1102 | #define MX53_PAD_GPIO_9__GPIO1_9 0x31c 0x6ac 0x000 0x1 0x0 | ||
| 1103 | #define MX53_PAD_GPIO_9__KPP_COL_6 0x31c 0x6ac 0x844 0x2 0x2 | ||
| 1104 | #define MX53_PAD_GPIO_9__CCM_REF_EN_B 0x31c 0x6ac 0x000 0x3 0x0 | ||
| 1105 | #define MX53_PAD_GPIO_9__PWM1_PWMO 0x31c 0x6ac 0x000 0x4 0x0 | ||
| 1106 | #define MX53_PAD_GPIO_9__WDOG1_WDOG_B 0x31c 0x6ac 0x000 0x5 0x0 | ||
| 1107 | #define MX53_PAD_GPIO_9__ESDHC1_WP 0x31c 0x6ac 0x7fc 0x6 0x1 | ||
| 1108 | #define MX53_PAD_GPIO_9__SCC_FAIL_STATE 0x31c 0x6ac 0x000 0x7 0x0 | ||
| 1109 | #define MX53_PAD_GPIO_3__ESAI1_HCKR 0x320 0x6b0 0x7d4 0x0 0x1 | ||
| 1110 | #define MX53_PAD_GPIO_3__GPIO1_3 0x320 0x6b0 0x000 0x1 0x0 | ||
| 1111 | #define MX53_PAD_GPIO_3__I2C3_SCL 0x320 0x6b0 0x824 0x2 0x1 | ||
| 1112 | #define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 0x320 0x6b0 0x000 0x3 0x0 | ||
| 1113 | #define MX53_PAD_GPIO_3__CCM_CLKO2 0x320 0x6b0 0x000 0x4 0x0 | ||
| 1114 | #define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 0x320 0x6b0 0x000 0x5 0x0 | ||
| 1115 | #define MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x320 0x6b0 0x8a0 0x6 0x1 | ||
| 1116 | #define MX53_PAD_GPIO_3__MLB_MLBCLK 0x320 0x6b0 0x858 0x7 0x2 | ||
| 1117 | #define MX53_PAD_GPIO_6__ESAI1_SCKT 0x324 0x6b4 0x7e0 0x0 0x1 | ||
| 1118 | #define MX53_PAD_GPIO_6__GPIO1_6 0x324 0x6b4 0x000 0x1 0x0 | ||
| 1119 | #define MX53_PAD_GPIO_6__I2C3_SDA 0x324 0x6b4 0x828 0x2 0x1 | ||
| 1120 | #define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 0x324 0x6b4 0x000 0x3 0x0 | ||
| 1121 | #define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 0x324 0x6b4 0x000 0x4 0x0 | ||
| 1122 | #define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 0x324 0x6b4 0x000 0x5 0x0 | ||
| 1123 | #define MX53_PAD_GPIO_6__ESDHC2_LCTL 0x324 0x6b4 0x000 0x6 0x0 | ||
| 1124 | #define MX53_PAD_GPIO_6__MLB_MLBSIG 0x324 0x6b4 0x860 0x7 0x2 | ||
| 1125 | #define MX53_PAD_GPIO_2__ESAI1_FST 0x328 0x6b8 0x7d0 0x0 0x1 | ||
| 1126 | #define MX53_PAD_GPIO_2__GPIO1_2 0x328 0x6b8 0x000 0x1 0x0 | ||
| 1127 | #define MX53_PAD_GPIO_2__KPP_ROW_6 0x328 0x6b8 0x850 0x2 0x2 | ||
| 1128 | #define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 0x328 0x6b8 0x000 0x3 0x0 | ||
| 1129 | #define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 0x328 0x6b8 0x000 0x4 0x0 | ||
| 1130 | #define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 0x328 0x6b8 0x000 0x5 0x0 | ||
| 1131 | #define MX53_PAD_GPIO_2__ESDHC2_WP 0x328 0x6b8 0x000 0x6 0x0 | ||
| 1132 | #define MX53_PAD_GPIO_2__MLB_MLBDAT 0x328 0x6b8 0x85c 0x7 0x2 | ||
| 1133 | #define MX53_PAD_GPIO_4__ESAI1_HCKT 0x32c 0x6bc 0x7d8 0x0 0x1 | ||
| 1134 | #define MX53_PAD_GPIO_4__GPIO1_4 0x32c 0x6bc 0x000 0x1 0x0 | ||
| 1135 | #define MX53_PAD_GPIO_4__KPP_COL_7 0x32c 0x6bc 0x848 0x2 0x2 | ||
| 1136 | #define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 0x32c 0x6bc 0x000 0x3 0x0 | ||
| 1137 | #define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 0x32c 0x6bc 0x000 0x4 0x0 | ||
| 1138 | #define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 0x32c 0x6bc 0x000 0x5 0x0 | ||
| 1139 | #define MX53_PAD_GPIO_4__ESDHC2_CD 0x32c 0x6bc 0x000 0x6 0x0 | ||
| 1140 | #define MX53_PAD_GPIO_4__SCC_SEC_STATE 0x32c 0x6bc 0x000 0x7 0x0 | ||
| 1141 | #define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 0x330 0x6c0 0x7ec 0x0 0x1 | ||
| 1142 | #define MX53_PAD_GPIO_5__GPIO1_5 0x330 0x6c0 0x000 0x1 0x0 | ||
| 1143 | #define MX53_PAD_GPIO_5__KPP_ROW_7 0x330 0x6c0 0x854 0x2 0x2 | ||
| 1144 | #define MX53_PAD_GPIO_5__CCM_CLKO 0x330 0x6c0 0x000 0x3 0x0 | ||
| 1145 | #define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 0x330 0x6c0 0x000 0x4 0x0 | ||
| 1146 | #define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 0x330 0x6c0 0x000 0x5 0x0 | ||
| 1147 | #define MX53_PAD_GPIO_5__I2C3_SCL 0x330 0x6c0 0x824 0x6 0x2 | ||
| 1148 | #define MX53_PAD_GPIO_5__CCM_PLL1_BYP 0x330 0x6c0 0x770 0x7 0x1 | ||
| 1149 | #define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 0x334 0x6c4 0x7f4 0x0 0x1 | ||
| 1150 | #define MX53_PAD_GPIO_7__GPIO1_7 0x334 0x6c4 0x000 0x1 0x0 | ||
| 1151 | #define MX53_PAD_GPIO_7__EPIT1_EPITO 0x334 0x6c4 0x000 0x2 0x0 | ||
| 1152 | #define MX53_PAD_GPIO_7__CAN1_TXCAN 0x334 0x6c4 0x000 0x3 0x0 | ||
| 1153 | #define MX53_PAD_GPIO_7__UART2_TXD_MUX 0x334 0x6c4 0x000 0x4 0x0 | ||
| 1154 | #define MX53_PAD_GPIO_7__FIRI_RXD 0x334 0x6c4 0x80c 0x5 0x1 | ||
| 1155 | #define MX53_PAD_GPIO_7__SPDIF_PLOCK 0x334 0x6c4 0x000 0x6 0x0 | ||
| 1156 | #define MX53_PAD_GPIO_7__CCM_PLL2_BYP 0x334 0x6c4 0x774 0x7 0x1 | ||
| 1157 | #define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 0x338 0x6c8 0x7f8 0x0 0x1 | ||
| 1158 | #define MX53_PAD_GPIO_8__GPIO1_8 0x338 0x6c8 0x000 0x1 0x0 | ||
| 1159 | #define MX53_PAD_GPIO_8__EPIT2_EPITO 0x338 0x6c8 0x000 0x2 0x0 | ||
| 1160 | #define MX53_PAD_GPIO_8__CAN1_RXCAN 0x338 0x6c8 0x760 0x3 0x2 | ||
| 1161 | #define MX53_PAD_GPIO_8__UART2_RXD_MUX 0x338 0x6c8 0x880 0x4 0x5 | ||
| 1162 | #define MX53_PAD_GPIO_8__FIRI_TXD 0x338 0x6c8 0x000 0x5 0x0 | ||
| 1163 | #define MX53_PAD_GPIO_8__SPDIF_SRCLK 0x338 0x6c8 0x000 0x6 0x0 | ||
| 1164 | #define MX53_PAD_GPIO_8__CCM_PLL3_BYP 0x338 0x6c8 0x778 0x7 0x1 | ||
| 1165 | #define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 0x33c 0x6cc 0x7f0 0x0 0x1 | ||
| 1166 | #define MX53_PAD_GPIO_16__GPIO7_11 0x33c 0x6cc 0x000 0x1 0x0 | ||
| 1167 | #define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 0x33c 0x6cc 0x000 0x2 0x0 | ||
| 1168 | #define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 0x33c 0x6cc 0x000 0x4 0x0 | ||
| 1169 | #define MX53_PAD_GPIO_16__SPDIF_IN1 0x33c 0x6cc 0x870 0x5 0x1 | ||
| 1170 | #define MX53_PAD_GPIO_16__I2C3_SDA 0x33c 0x6cc 0x828 0x6 0x2 | ||
| 1171 | #define MX53_PAD_GPIO_16__SJC_DE_B 0x33c 0x6cc 0x000 0x7 0x0 | ||
| 1172 | #define MX53_PAD_GPIO_17__ESAI1_TX0 0x340 0x6d0 0x7e4 0x0 0x1 | ||
| 1173 | #define MX53_PAD_GPIO_17__GPIO7_12 0x340 0x6d0 0x000 0x1 0x0 | ||
| 1174 | #define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 0x340 0x6d0 0x868 0x2 0x1 | ||
| 1175 | #define MX53_PAD_GPIO_17__GPC_PMIC_RDY 0x340 0x6d0 0x810 0x3 0x1 | ||
| 1176 | #define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 0x340 0x6d0 0x000 0x4 0x0 | ||
| 1177 | #define MX53_PAD_GPIO_17__SPDIF_OUT1 0x340 0x6d0 0x000 0x5 0x0 | ||
| 1178 | #define MX53_PAD_GPIO_17__IPU_SNOOP2 0x340 0x6d0 0x000 0x6 0x0 | ||
| 1179 | #define MX53_PAD_GPIO_17__SJC_JTAG_ACT 0x340 0x6d0 0x000 0x7 0x0 | ||
| 1180 | #define MX53_PAD_GPIO_18__ESAI1_TX1 0x344 0x6d4 0x7e8 0x0 0x1 | ||
| 1181 | #define MX53_PAD_GPIO_18__GPIO7_13 0x344 0x6d4 0x000 0x1 0x0 | ||
| 1182 | #define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 0x344 0x6d4 0x86c 0x2 0x1 | ||
| 1183 | #define MX53_PAD_GPIO_18__OWIRE_LINE 0x344 0x6d4 0x864 0x3 0x1 | ||
| 1184 | #define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 0x344 0x6d4 0x000 0x4 0x0 | ||
| 1185 | #define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 0x344 0x6d4 0x768 0x5 0x1 | ||
| 1186 | #define MX53_PAD_GPIO_18__ESDHC1_LCTL 0x344 0x6d4 0x000 0x6 0x0 | ||
| 1187 | #define MX53_PAD_GPIO_18__SRC_SYSTEM_RST 0x344 0x6d4 0x000 0x7 0x0 | ||
| 1188 | |||
| 1189 | #endif /* __DTS_IMX53_PINFUNC_H */ | ||
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index 05cc5620436b..8f0e9ae0e3e6 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts | |||
| @@ -11,7 +11,7 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /dts-v1/; | 13 | /dts-v1/; |
| 14 | /include/ "imx53.dtsi" | 14 | #include "imx53.dtsi" |
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | model = "Freescale i.MX53 Quick Start Board"; | 17 | model = "Freescale i.MX53 Quick Start Board"; |
| @@ -110,21 +110,21 @@ | |||
| 110 | hog { | 110 | hog { |
| 111 | pinctrl_hog: hoggrp { | 111 | pinctrl_hog: hoggrp { |
| 112 | fsl,pins = < | 112 | fsl,pins = < |
| 113 | 1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */ | 113 | MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 |
| 114 | 1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */ | 114 | MX53_PAD_GPIO_8__GPIO1_8 0x80000000 |
| 115 | 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */ | 115 | MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 |
| 116 | 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */ | 116 | MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 |
| 117 | 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */ | 117 | MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 |
| 118 | 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ | 118 | MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 |
| 119 | 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ | 119 | MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 |
| 120 | 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ | 120 | MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 |
| 121 | 1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */ | 121 | MX53_PAD_GPIO_16__GPIO7_11 0x80000000 |
| 122 | >; | 122 | >; |
| 123 | }; | 123 | }; |
| 124 | 124 | ||
| 125 | led_pin_gpio7_7: led_gpio7_7@0 { | 125 | led_pin_gpio7_7: led_gpio7_7@0 { |
| 126 | fsl,pins = < | 126 | fsl,pins = < |
| 127 | 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ | 127 | MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 |
| 128 | >; | 128 | >; |
| 129 | }; | 129 | }; |
| 130 | }; | 130 | }; |
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 995554c324b8..a9b6e10de0a5 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts | |||
| @@ -11,7 +11,7 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /dts-v1/; | 13 | /dts-v1/; |
| 14 | /include/ "imx53.dtsi" | 14 | #include "imx53.dtsi" |
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | model = "Freescale i.MX53 Smart Mobile Reference Design Board"; | 17 | model = "Freescale i.MX53 Smart Mobile Reference Design Board"; |
| @@ -107,13 +107,13 @@ | |||
| 107 | hog { | 107 | hog { |
| 108 | pinctrl_hog: hoggrp { | 108 | pinctrl_hog: hoggrp { |
| 109 | fsl,pins = < | 109 | fsl,pins = < |
| 110 | 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */ | 110 | MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 |
| 111 | 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */ | 111 | MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 |
| 112 | 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */ | 112 | MX53_PAD_EIM_EB2__GPIO2_30 0x80000000 |
| 113 | 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ | 113 | MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 |
| 114 | 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */ | 114 | MX53_PAD_EIM_D19__GPIO3_19 0x80000000 |
| 115 | 43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */ | 115 | MX53_PAD_KEY_ROW2__GPIO4_11 0x80000000 |
| 116 | 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ | 116 | MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 |
| 117 | >; | 117 | >; |
| 118 | }; | 118 | }; |
| 119 | }; | 119 | }; |
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi index 8278ec5ec222..38bed3ed7c1a 100644 --- a/arch/arm/boot/dts/imx53-tqma53.dtsi +++ b/arch/arm/boot/dts/imx53-tqma53.dtsi | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | * http://www.gnu.org/copyleft/gpl.html | 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /include/ "imx53.dtsi" | 13 | #include "imx53.dtsi" |
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | model = "TQ TQMa53"; | 16 | model = "TQ TQMa53"; |
| @@ -72,11 +72,11 @@ | |||
| 72 | i2s { | 72 | i2s { |
| 73 | pinctrl_i2s_1: i2s-grp1 { | 73 | pinctrl_i2s_1: i2s-grp1 { |
| 74 | fsl,pins = < | 74 | fsl,pins = < |
| 75 | 1 0x10000 /* I2S_MCLK */ | 75 | MX53_PAD_GPIO_19__GPIO4_5 0x10000 /* I2S_MCLK */ |
| 76 | 10 0x10000 /* I2S_SCLK */ | 76 | MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x10000 /* I2S_SCLK */ |
| 77 | 17 0x10000 /* I2S_DOUT */ | 77 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x10000 /* I2S_DOUT */ |
| 78 | 23 0x10000 /* I2S_LRCLK*/ | 78 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x10000 /* I2S_LRCLK */ |
| 79 | 30 0x10000 /* I2S_DIN */ | 79 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x10000 /* I2S_DIN */ |
| 80 | >; | 80 | >; |
| 81 | }; | 81 | }; |
| 82 | }; | 82 | }; |
| @@ -84,16 +84,16 @@ | |||
| 84 | hog { | 84 | hog { |
| 85 | pinctrl_hog: hoggrp { | 85 | pinctrl_hog: hoggrp { |
| 86 | fsl,pins = < | 86 | fsl,pins = < |
| 87 | 610 0x10000 /* MX53_PAD_EIM_CS1__IPU_DI1_PIN6 (VSYNC)*/ | 87 | MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x10000 /* VSYNC */ |
| 88 | 711 0x10000 /* MX53_PAD_EIM_DA15__IPU_DI1_PIN4 (HSYNC)*/ | 88 | MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x10000 /* HSYNC */ |
| 89 | 873 0x10000 /* MX53_PAD_PATA_DA_1__GPIO7_7 (LCD_BLT_EN)*/ | 89 | MX53_PAD_PATA_DA_1__GPIO7_7 0x10000 /* LCD_BLT_EN */ |
| 90 | 878 0x10000 /* MX53_PAD_PATA_DA_2__GPIO7_8 (LCD_RESET)*/ | 90 | MX53_PAD_PATA_DA_2__GPIO7_8 0x10000 /* LCD_RESET */ |
| 91 | 922 0x10000 /* MX53_PAD_PATA_DATA5__GPIO2_5 (LCD_POWER)*/ | 91 | MX53_PAD_PATA_DATA5__GPIO2_5 0x10000 /* LCD_POWER */ |
| 92 | 928 0x10000 /* MX53_PAD_PATA_DATA6__GPIO2_6 (PMIC_INT)*/ | 92 | MX53_PAD_PATA_DATA6__GPIO2_6 0x10000 /* PMIC_INT */ |
| 93 | 982 0x10000 /* MX53_PAD_PATA_DATA14__GPIO2_14 (CSI_RST)*/ | 93 | MX53_PAD_PATA_DATA14__GPIO2_14 0x10000 /* CSI_RST */ |
| 94 | 989 0x10000 /* MX53_PAD_PATA_DATA15__GPIO2_15 (CSI_PWDN)*/ | 94 | MX53_PAD_PATA_DATA15__GPIO2_15 0x10000 /* CSI_PWDN */ |
| 95 | 1069 0x10000 /* MX53_PAD_GPIO_0__GPIO1_0 (SYSTEM_DOWN)*/ | 95 | MX53_PAD_GPIO_0__GPIO1_0 0x10000 /* SYSTEM_DOWN */ |
| 96 | 1093 0x10000 /* MX53_PAD_GPIO_3__GPIO1_3 */ | 96 | MX53_PAD_GPIO_3__GPIO1_3 0x10000 |
| 97 | >; | 97 | >; |
| 98 | }; | 98 | }; |
| 99 | }; | 99 | }; |
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index d05aa215c7f9..845982eaac22 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi | |||
| @@ -10,7 +10,8 @@ | |||
| 10 | * http://www.gnu.org/copyleft/gpl.html | 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /include/ "skeleton.dtsi" | 13 | #include "skeleton.dtsi" |
| 14 | #include "imx53-pinfunc.h" | ||
| 14 | 15 | ||
| 15 | / { | 16 | / { |
| 16 | aliases { | 17 | aliases { |
| @@ -72,6 +73,9 @@ | |||
| 72 | compatible = "fsl,imx53-ipu"; | 73 | compatible = "fsl,imx53-ipu"; |
| 73 | reg = <0x18000000 0x080000000>; | 74 | reg = <0x18000000 0x080000000>; |
| 74 | interrupts = <11 10>; | 75 | interrupts = <11 10>; |
| 76 | clocks = <&clks 59>, <&clks 110>, <&clks 61>; | ||
| 77 | clock-names = "bus", "di0", "di1"; | ||
| 78 | resets = <&src 2>; | ||
| 75 | }; | 79 | }; |
| 76 | 80 | ||
| 77 | aips@50000000 { /* AIPS1 */ | 81 | aips@50000000 { /* AIPS1 */ |
| @@ -242,6 +246,14 @@ | |||
| 242 | status = "disabled"; | 246 | status = "disabled"; |
| 243 | }; | 247 | }; |
| 244 | 248 | ||
| 249 | gpt: timer@53fa0000 { | ||
| 250 | compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; | ||
| 251 | reg = <0x53fa0000 0x4000>; | ||
| 252 | interrupts = <39>; | ||
| 253 | clocks = <&clks 36>, <&clks 41>; | ||
| 254 | clock-names = "ipg", "per"; | ||
| 255 | }; | ||
| 256 | |||
| 245 | iomuxc: iomuxc@53fa8000 { | 257 | iomuxc: iomuxc@53fa8000 { |
| 246 | compatible = "fsl,imx53-iomuxc"; | 258 | compatible = "fsl,imx53-iomuxc"; |
| 247 | reg = <0x53fa8000 0x4000>; | 259 | reg = <0x53fa8000 0x4000>; |
| @@ -249,10 +261,10 @@ | |||
| 249 | audmux { | 261 | audmux { |
| 250 | pinctrl_audmux_1: audmuxgrp-1 { | 262 | pinctrl_audmux_1: audmuxgrp-1 { |
| 251 | fsl,pins = < | 263 | fsl,pins = < |
| 252 | 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ | 264 | MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 |
| 253 | 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ | 265 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 |
| 254 | 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ | 266 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 |
| 255 | 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ | 267 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 |
| 256 | >; | 268 | >; |
| 257 | }; | 269 | }; |
| 258 | }; | 270 | }; |
| @@ -260,16 +272,16 @@ | |||
| 260 | fec { | 272 | fec { |
| 261 | pinctrl_fec_1: fecgrp-1 { | 273 | pinctrl_fec_1: fecgrp-1 { |
| 262 | fsl,pins = < | 274 | fsl,pins = < |
| 263 | 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */ | 275 | MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 |
| 264 | 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */ | 276 | MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 |
| 265 | 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */ | 277 | MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 |
| 266 | 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */ | 278 | MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 |
| 267 | 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */ | 279 | MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 |
| 268 | 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */ | 280 | MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 |
| 269 | 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */ | 281 | MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 |
| 270 | 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */ | 282 | MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 |
| 271 | 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */ | 283 | MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 |
| 272 | 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */ | 284 | MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 |
| 273 | >; | 285 | >; |
| 274 | }; | 286 | }; |
| 275 | }; | 287 | }; |
| @@ -277,27 +289,27 @@ | |||
| 277 | csi { | 289 | csi { |
| 278 | pinctrl_csi_1: csigrp-1 { | 290 | pinctrl_csi_1: csigrp-1 { |
| 279 | fsl,pins = < | 291 | fsl,pins = < |
| 280 | 286 0x1d5 /* MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN */ | 292 | MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5 |
| 281 | 291 0x1d5 /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */ | 293 | MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5 |
| 282 | 280 0x1d5 /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */ | 294 | MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5 |
| 283 | 276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */ | 295 | MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 |
| 284 | 409 0x1d5 /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */ | 296 | MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5 |
| 285 | 402 0x1d5 /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */ | 297 | MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5 |
| 286 | 395 0x1d5 /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */ | 298 | MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5 |
| 287 | 388 0x1d5 /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */ | 299 | MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5 |
| 288 | 381 0x1d5 /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */ | 300 | MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5 |
| 289 | 374 0x1d5 /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */ | 301 | MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5 |
| 290 | 367 0x1d5 /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */ | 302 | MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5 |
| 291 | 360 0x1d5 /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */ | 303 | MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5 |
| 292 | 352 0x1d5 /* MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 */ | 304 | MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5 |
| 293 | 344 0x1d5 /* MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 */ | 305 | MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5 |
| 294 | 336 0x1d5 /* MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 */ | 306 | MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5 |
| 295 | 328 0x1d5 /* MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 */ | 307 | MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5 |
| 296 | 320 0x1d5 /* MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 */ | 308 | MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5 |
| 297 | 312 0x1d5 /* MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 */ | 309 | MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5 |
| 298 | 304 0x1d5 /* MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 */ | 310 | MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5 |
| 299 | 296 0x1d5 /* MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 */ | 311 | MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5 |
| 300 | 276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */ | 312 | MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 |
| 301 | >; | 313 | >; |
| 302 | }; | 314 | }; |
| 303 | }; | 315 | }; |
| @@ -305,9 +317,9 @@ | |||
| 305 | cspi { | 317 | cspi { |
| 306 | pinctrl_cspi_1: cspigrp-1 { | 318 | pinctrl_cspi_1: cspigrp-1 { |
| 307 | fsl,pins = < | 319 | fsl,pins = < |
| 308 | 998 0x1d5 /* MX53_PAD_SD1_DATA0__CSPI_MISO */ | 320 | MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5 |
| 309 | 1008 0x1d5 /* MX53_PAD_SD1_CMD__CSPI_MOSI */ | 321 | MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5 |
| 310 | 1022 0x1d5 /* MX53_PAD_SD1_CLK__CSPI_SCLK */ | 322 | MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 |
| 311 | >; | 323 | >; |
| 312 | }; | 324 | }; |
| 313 | }; | 325 | }; |
| @@ -315,9 +327,9 @@ | |||
| 315 | ecspi1 { | 327 | ecspi1 { |
| 316 | pinctrl_ecspi1_1: ecspi1grp-1 { | 328 | pinctrl_ecspi1_1: ecspi1grp-1 { |
| 317 | fsl,pins = < | 329 | fsl,pins = < |
| 318 | 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */ | 330 | MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 |
| 319 | 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */ | 331 | MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 |
| 320 | 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */ | 332 | MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 |
| 321 | >; | 333 | >; |
| 322 | }; | 334 | }; |
| 323 | }; | 335 | }; |
| @@ -325,27 +337,27 @@ | |||
| 325 | esdhc1 { | 337 | esdhc1 { |
| 326 | pinctrl_esdhc1_1: esdhc1grp-1 { | 338 | pinctrl_esdhc1_1: esdhc1grp-1 { |
| 327 | fsl,pins = < | 339 | fsl,pins = < |
| 328 | 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ | 340 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 |
| 329 | 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ | 341 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 |
| 330 | 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ | 342 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 |
| 331 | 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ | 343 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 |
| 332 | 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ | 344 | MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 |
| 333 | 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ | 345 | MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 |
| 334 | >; | 346 | >; |
| 335 | }; | 347 | }; |
| 336 | 348 | ||
| 337 | pinctrl_esdhc1_2: esdhc1grp-2 { | 349 | pinctrl_esdhc1_2: esdhc1grp-2 { |
| 338 | fsl,pins = < | 350 | fsl,pins = < |
| 339 | 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ | 351 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 |
| 340 | 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ | 352 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 |
| 341 | 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ | 353 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 |
| 342 | 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ | 354 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 |
| 343 | 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */ | 355 | MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 |
| 344 | 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */ | 356 | MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 |
| 345 | 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */ | 357 | MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 |
| 346 | 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */ | 358 | MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 |
| 347 | 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ | 359 | MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 |
| 348 | 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ | 360 | MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 |
| 349 | >; | 361 | >; |
| 350 | }; | 362 | }; |
| 351 | }; | 363 | }; |
| @@ -353,12 +365,12 @@ | |||
| 353 | esdhc2 { | 365 | esdhc2 { |
| 354 | pinctrl_esdhc2_1: esdhc2grp-1 { | 366 | pinctrl_esdhc2_1: esdhc2grp-1 { |
| 355 | fsl,pins = < | 367 | fsl,pins = < |
| 356 | 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */ | 368 | MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 |
| 357 | 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */ | 369 | MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 |
| 358 | 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */ | 370 | MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 |
| 359 | 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */ | 371 | MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 |
| 360 | 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */ | 372 | MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 |
| 361 | 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */ | 373 | MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 |
| 362 | >; | 374 | >; |
| 363 | }; | 375 | }; |
| 364 | }; | 376 | }; |
| @@ -366,16 +378,16 @@ | |||
| 366 | esdhc3 { | 378 | esdhc3 { |
| 367 | pinctrl_esdhc3_1: esdhc3grp-1 { | 379 | pinctrl_esdhc3_1: esdhc3grp-1 { |
| 368 | fsl,pins = < | 380 | fsl,pins = < |
| 369 | 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */ | 381 | MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 |
| 370 | 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */ | 382 | MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 |
| 371 | 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */ | 383 | MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 |
| 372 | 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */ | 384 | MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 |
| 373 | 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */ | 385 | MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 |
| 374 | 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */ | 386 | MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 |
| 375 | 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */ | 387 | MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 |
| 376 | 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */ | 388 | MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 |
| 377 | 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */ | 389 | MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 |
| 378 | 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */ | 390 | MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 |
| 379 | >; | 391 | >; |
| 380 | }; | 392 | }; |
| 381 | }; | 393 | }; |
| @@ -383,15 +395,15 @@ | |||
| 383 | can1 { | 395 | can1 { |
| 384 | pinctrl_can1_1: can1grp-1 { | 396 | pinctrl_can1_1: can1grp-1 { |
| 385 | fsl,pins = < | 397 | fsl,pins = < |
| 386 | 847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */ | 398 | MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000 |
| 387 | 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */ | 399 | MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000 |
| 388 | >; | 400 | >; |
| 389 | }; | 401 | }; |
| 390 | 402 | ||
| 391 | pinctrl_can1_2: can1grp-2 { | 403 | pinctrl_can1_2: can1grp-2 { |
| 392 | fsl,pins = < | 404 | fsl,pins = < |
| 393 | 37 0x80000000 /* MX53_PAD_KEY_COL2__CAN1_TXCAN */ | 405 | MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000 |
| 394 | 44 0x80000000 /* MX53_PAD_KEY_ROW2__CAN1_RXCAN */ | 406 | MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 |
| 395 | >; | 407 | >; |
| 396 | }; | 408 | }; |
| 397 | }; | 409 | }; |
| @@ -399,8 +411,8 @@ | |||
| 399 | can2 { | 411 | can2 { |
| 400 | pinctrl_can2_1: can2grp-1 { | 412 | pinctrl_can2_1: can2grp-1 { |
| 401 | fsl,pins = < | 413 | fsl,pins = < |
| 402 | 67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */ | 414 | MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 |
| 403 | 74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */ | 415 | MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 |
| 404 | >; | 416 | >; |
| 405 | }; | 417 | }; |
| 406 | }; | 418 | }; |
| @@ -408,8 +420,8 @@ | |||
| 408 | i2c1 { | 420 | i2c1 { |
| 409 | pinctrl_i2c1_1: i2c1grp-1 { | 421 | pinctrl_i2c1_1: i2c1grp-1 { |
| 410 | fsl,pins = < | 422 | fsl,pins = < |
| 411 | 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */ | 423 | MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 |
| 412 | 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */ | 424 | MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 |
| 413 | >; | 425 | >; |
| 414 | }; | 426 | }; |
| 415 | }; | 427 | }; |
| @@ -417,8 +429,8 @@ | |||
| 417 | i2c2 { | 429 | i2c2 { |
| 418 | pinctrl_i2c2_1: i2c2grp-1 { | 430 | pinctrl_i2c2_1: i2c2grp-1 { |
| 419 | fsl,pins = < | 431 | fsl,pins = < |
| 420 | 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */ | 432 | MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 |
| 421 | 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */ | 433 | MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 |
| 422 | >; | 434 | >; |
| 423 | }; | 435 | }; |
| 424 | }; | 436 | }; |
| @@ -426,8 +438,8 @@ | |||
| 426 | i2c3 { | 438 | i2c3 { |
| 427 | pinctrl_i2c3_1: i2c3grp-1 { | 439 | pinctrl_i2c3_1: i2c3grp-1 { |
| 428 | fsl,pins = < | 440 | fsl,pins = < |
| 429 | 1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */ | 441 | MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 |
| 430 | 1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */ | 442 | MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 |
| 431 | >; | 443 | >; |
| 432 | }; | 444 | }; |
| 433 | }; | 445 | }; |
| @@ -435,7 +447,7 @@ | |||
| 435 | owire { | 447 | owire { |
| 436 | pinctrl_owire_1: owiregrp-1 { | 448 | pinctrl_owire_1: owiregrp-1 { |
| 437 | fsl,pins = < | 449 | fsl,pins = < |
| 438 | 1166 0x80000000 /* MX53_PAD_GPIO_18__OWIRE_LINE */ | 450 | MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000 |
| 439 | >; | 451 | >; |
| 440 | }; | 452 | }; |
| 441 | }; | 453 | }; |
| @@ -443,15 +455,15 @@ | |||
| 443 | uart1 { | 455 | uart1 { |
| 444 | pinctrl_uart1_1: uart1grp-1 { | 456 | pinctrl_uart1_1: uart1grp-1 { |
| 445 | fsl,pins = < | 457 | fsl,pins = < |
| 446 | 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */ | 458 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5 |
| 447 | 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */ | 459 | MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5 |
| 448 | >; | 460 | >; |
| 449 | }; | 461 | }; |
| 450 | 462 | ||
| 451 | pinctrl_uart1_2: uart1grp-2 { | 463 | pinctrl_uart1_2: uart1grp-2 { |
| 452 | fsl,pins = < | 464 | fsl,pins = < |
| 453 | 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */ | 465 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5 |
| 454 | 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */ | 466 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5 |
| 455 | >; | 467 | >; |
| 456 | }; | 468 | }; |
| 457 | }; | 469 | }; |
| @@ -459,8 +471,8 @@ | |||
| 459 | uart2 { | 471 | uart2 { |
| 460 | pinctrl_uart2_1: uart2grp-1 { | 472 | pinctrl_uart2_1: uart2grp-1 { |
| 461 | fsl,pins = < | 473 | fsl,pins = < |
| 462 | 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */ | 474 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 |
| 463 | 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */ | 475 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 |
| 464 | >; | 476 | >; |
| 465 | }; | 477 | }; |
| 466 | }; | 478 | }; |
| @@ -468,17 +480,17 @@ | |||
| 468 | uart3 { | 480 | uart3 { |
| 469 | pinctrl_uart3_1: uart3grp-1 { | 481 | pinctrl_uart3_1: uart3grp-1 { |
| 470 | fsl,pins = < | 482 | fsl,pins = < |
| 471 | 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */ | 483 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5 |
| 472 | 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */ | 484 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5 |
| 473 | 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */ | 485 | MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5 |
| 474 | 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */ | 486 | MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5 |
| 475 | >; | 487 | >; |
| 476 | }; | 488 | }; |
| 477 | 489 | ||
| 478 | pinctrl_uart3_2: uart3grp-2 { | 490 | pinctrl_uart3_2: uart3grp-2 { |
| 479 | fsl,pins = < | 491 | fsl,pins = < |
| 480 | 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */ | 492 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5 |
| 481 | 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */ | 493 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5 |
| 482 | >; | 494 | >; |
| 483 | }; | 495 | }; |
| 484 | 496 | ||
| @@ -487,8 +499,8 @@ | |||
| 487 | uart4 { | 499 | uart4 { |
| 488 | pinctrl_uart4_1: uart4grp-1 { | 500 | pinctrl_uart4_1: uart4grp-1 { |
| 489 | fsl,pins = < | 501 | fsl,pins = < |
| 490 | 11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */ | 502 | MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5 |
| 491 | 18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */ | 503 | MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5 |
| 492 | >; | 504 | >; |
| 493 | }; | 505 | }; |
| 494 | }; | 506 | }; |
| @@ -496,14 +508,46 @@ | |||
| 496 | uart5 { | 508 | uart5 { |
| 497 | pinctrl_uart5_1: uart5grp-1 { | 509 | pinctrl_uart5_1: uart5grp-1 { |
| 498 | fsl,pins = < | 510 | fsl,pins = < |
| 499 | 24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */ | 511 | MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5 |
| 500 | 31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */ | 512 | MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5 |
| 501 | >; | 513 | >; |
| 502 | }; | 514 | }; |
| 503 | }; | 515 | }; |
| 504 | 516 | ||
| 505 | }; | 517 | }; |
| 506 | 518 | ||
| 519 | gpr: iomuxc-gpr@53fa8000 { | ||
| 520 | compatible = "fsl,imx53-iomuxc-gpr", "syscon"; | ||
| 521 | reg = <0x53fa8000 0xc>; | ||
| 522 | }; | ||
| 523 | |||
| 524 | ldb: ldb@53fa8008 { | ||
| 525 | #address-cells = <1>; | ||
| 526 | #size-cells = <0>; | ||
| 527 | compatible = "fsl,imx53-ldb"; | ||
| 528 | reg = <0x53fa8008 0x4>; | ||
| 529 | gpr = <&gpr>; | ||
| 530 | clocks = <&clks 122>, <&clks 120>, | ||
| 531 | <&clks 115>, <&clks 116>, | ||
| 532 | <&clks 123>, <&clks 85>; | ||
| 533 | clock-names = "di0_pll", "di1_pll", | ||
| 534 | "di0_sel", "di1_sel", | ||
| 535 | "di0", "di1"; | ||
| 536 | status = "disabled"; | ||
| 537 | |||
| 538 | lvds-channel@0 { | ||
| 539 | reg = <0>; | ||
| 540 | crtcs = <&ipu 0>; | ||
| 541 | status = "disabled"; | ||
| 542 | }; | ||
| 543 | |||
| 544 | lvds-channel@1 { | ||
| 545 | reg = <1>; | ||
| 546 | crtcs = <&ipu 1>; | ||
| 547 | status = "disabled"; | ||
| 548 | }; | ||
| 549 | }; | ||
| 550 | |||
| 507 | pwm1: pwm@53fb4000 { | 551 | pwm1: pwm@53fb4000 { |
| 508 | #pwm-cells = <2>; | 552 | #pwm-cells = <2>; |
| 509 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | 553 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; |
| @@ -558,6 +602,12 @@ | |||
| 558 | status = "disabled"; | 602 | status = "disabled"; |
| 559 | }; | 603 | }; |
| 560 | 604 | ||
| 605 | src: src@53fd0000 { | ||
| 606 | compatible = "fsl,imx53-src", "fsl,imx51-src"; | ||
| 607 | reg = <0x53fd0000 0x4000>; | ||
| 608 | #reset-cells = <1>; | ||
| 609 | }; | ||
| 610 | |||
| 561 | clks: ccm@53fd4000{ | 611 | clks: ccm@53fd4000{ |
| 562 | compatible = "fsl,imx53-ccm"; | 612 | compatible = "fsl,imx53-ccm"; |
| 563 | reg = <0x53fd4000 0x4000>; | 613 | reg = <0x53fd4000 0x4000>; |
diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h new file mode 100644 index 000000000000..9aab950ec269 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-pinfunc.h | |||
| @@ -0,0 +1,1085 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __DTS_IMX6DL_PINFUNC_H | ||
| 11 | #define __DTS_IMX6DL_PINFUNC_H | ||
| 12 | |||
| 13 | /* | ||
| 14 | * The pin function ID is a tuple of | ||
| 15 | * <mux_reg conf_reg input_reg mux_mode input_val> | ||
| 16 | */ | ||
| 17 | #define MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 | ||
| 18 | #define MX6DL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 | ||
| 19 | #define MX6DL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 | ||
| 20 | #define MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 | ||
| 21 | #define MX6DL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 | ||
| 22 | #define MX6DL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 | ||
| 23 | #define MX6DL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 | ||
| 24 | #define MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 | ||
| 25 | #define MX6DL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 | ||
| 26 | #define MX6DL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 | ||
| 27 | #define MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1 | ||
| 28 | #define MX6DL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0 | ||
| 29 | #define MX6DL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0 | ||
| 30 | #define MX6DL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0 | ||
| 31 | #define MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0 | ||
| 32 | #define MX6DL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0 | ||
| 33 | #define MX6DL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0 | ||
| 34 | #define MX6DL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0 | ||
| 35 | #define MX6DL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0 | ||
| 36 | #define MX6DL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0 | ||
| 37 | #define MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0 | ||
| 38 | #define MX6DL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0 | ||
| 39 | #define MX6DL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1 | ||
| 40 | #define MX6DL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0 | ||
| 41 | #define MX6DL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0 | ||
| 42 | #define MX6DL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0 | ||
| 43 | #define MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0 | ||
| 44 | #define MX6DL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0 | ||
| 45 | #define MX6DL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0 | ||
| 46 | #define MX6DL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0 | ||
| 47 | #define MX6DL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0 | ||
| 48 | #define MX6DL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0 | ||
| 49 | #define MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0 | ||
| 50 | #define MX6DL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0 | ||
| 51 | #define MX6DL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1 | ||
| 52 | #define MX6DL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0 | ||
| 53 | #define MX6DL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0 | ||
| 54 | #define MX6DL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0 | ||
| 55 | #define MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0 | ||
| 56 | #define MX6DL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0 | ||
| 57 | #define MX6DL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0 | ||
| 58 | #define MX6DL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0 | ||
| 59 | #define MX6DL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0 | ||
| 60 | #define MX6DL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0 | ||
| 61 | #define MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0 | ||
| 62 | #define MX6DL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0 | ||
| 63 | #define MX6DL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0 | ||
| 64 | #define MX6DL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1 | ||
| 65 | #define MX6DL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0 | ||
| 66 | #define MX6DL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0 | ||
| 67 | #define MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0 | ||
| 68 | #define MX6DL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0 | ||
| 69 | #define MX6DL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0 | ||
| 70 | #define MX6DL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0 | ||
| 71 | #define MX6DL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0 | ||
| 72 | #define MX6DL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0 | ||
| 73 | #define MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0 | ||
| 74 | #define MX6DL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0 | ||
| 75 | #define MX6DL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0 | ||
| 76 | #define MX6DL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1 | ||
| 77 | #define MX6DL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0 | ||
| 78 | #define MX6DL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0 | ||
| 79 | #define MX6DL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0 | ||
| 80 | #define MX6DL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0 | ||
| 81 | #define MX6DL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0 | ||
| 82 | #define MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0 | ||
| 83 | #define MX6DL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0 | ||
| 84 | #define MX6DL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0 | ||
| 85 | #define MX6DL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0 | ||
| 86 | #define MX6DL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0 | ||
| 87 | #define MX6DL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0 | ||
| 88 | #define MX6DL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0 | ||
| 89 | #define MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0 | ||
| 90 | #define MX6DL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0 | ||
| 91 | #define MX6DL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0 | ||
| 92 | #define MX6DL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0 | ||
| 93 | #define MX6DL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0 | ||
| 94 | #define MX6DL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0 | ||
| 95 | #define MX6DL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0 | ||
| 96 | #define MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0 | ||
| 97 | #define MX6DL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0 | ||
| 98 | #define MX6DL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0 | ||
| 99 | #define MX6DL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0 | ||
| 100 | #define MX6DL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0 | ||
| 101 | #define MX6DL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0 | ||
| 102 | #define MX6DL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0 | ||
| 103 | #define MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0 | ||
| 104 | #define MX6DL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0 | ||
| 105 | #define MX6DL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0 | ||
| 106 | #define MX6DL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0 | ||
| 107 | #define MX6DL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0 | ||
| 108 | #define MX6DL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0 | ||
| 109 | #define MX6DL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0 | ||
| 110 | #define MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0 | ||
| 111 | #define MX6DL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0 | ||
| 112 | #define MX6DL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0 | ||
| 113 | #define MX6DL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0 | ||
| 114 | #define MX6DL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0 | ||
| 115 | #define MX6DL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0 | ||
| 116 | #define MX6DL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0 | ||
| 117 | #define MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0 | ||
| 118 | #define MX6DL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0 | ||
| 119 | #define MX6DL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0 | ||
| 120 | #define MX6DL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0 | ||
| 121 | #define MX6DL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0 | ||
| 122 | #define MX6DL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0 | ||
| 123 | #define MX6DL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0 | ||
| 124 | #define MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0 | ||
| 125 | #define MX6DL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0 | ||
| 126 | #define MX6DL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0 | ||
| 127 | #define MX6DL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0 | ||
| 128 | #define MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0 | ||
| 129 | #define MX6DL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0 | ||
| 130 | #define MX6DL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0 | ||
| 131 | #define MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0 | ||
| 132 | #define MX6DL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0 | ||
| 133 | #define MX6DL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0 | ||
| 134 | #define MX6DL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0 | ||
| 135 | #define MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0 | ||
| 136 | #define MX6DL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0 | ||
| 137 | #define MX6DL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0 | ||
| 138 | #define MX6DL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0 | ||
| 139 | #define MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0 | ||
| 140 | #define MX6DL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0 | ||
| 141 | #define MX6DL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0 | ||
| 142 | #define MX6DL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0 | ||
| 143 | #define MX6DL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0 | ||
| 144 | #define MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0 | ||
| 145 | #define MX6DL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0 | ||
| 146 | #define MX6DL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0 | ||
| 147 | #define MX6DL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0 | ||
| 148 | #define MX6DL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0 | ||
| 149 | #define MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0 | ||
| 150 | #define MX6DL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0 | ||
| 151 | #define MX6DL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0 | ||
| 152 | #define MX6DL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0 | ||
| 153 | #define MX6DL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0 | ||
| 154 | #define MX6DL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0 | ||
| 155 | #define MX6DL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1 | ||
| 156 | #define MX6DL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0 | ||
| 157 | #define MX6DL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0 | ||
| 158 | #define MX6DL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0 | ||
| 159 | #define MX6DL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0 | ||
| 160 | #define MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0 | ||
| 161 | #define MX6DL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0 | ||
| 162 | #define MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0 | ||
| 163 | #define MX6DL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0 | ||
| 164 | #define MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0 | ||
| 165 | #define MX6DL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0 | ||
| 166 | #define MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0 | ||
| 167 | #define MX6DL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0 | ||
| 168 | #define MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0 | ||
| 169 | #define MX6DL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0 | ||
| 170 | #define MX6DL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0 | ||
| 171 | #define MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0 | ||
| 172 | #define MX6DL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0 | ||
| 173 | #define MX6DL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0 | ||
| 174 | #define MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0 | ||
| 175 | #define MX6DL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0 | ||
| 176 | #define MX6DL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0 | ||
| 177 | #define MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0 | ||
| 178 | #define MX6DL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0 | ||
| 179 | #define MX6DL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0 | ||
| 180 | #define MX6DL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0 | ||
| 181 | #define MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0 | ||
| 182 | #define MX6DL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0 | ||
| 183 | #define MX6DL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0 | ||
| 184 | #define MX6DL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0 | ||
| 185 | #define MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0 | ||
| 186 | #define MX6DL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0 | ||
| 187 | #define MX6DL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0 | ||
| 188 | #define MX6DL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0 | ||
| 189 | #define MX6DL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0 | ||
| 190 | #define MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0 | ||
| 191 | #define MX6DL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0 | ||
| 192 | #define MX6DL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1 | ||
| 193 | #define MX6DL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0 | ||
| 194 | #define MX6DL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0 | ||
| 195 | #define MX6DL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0 | ||
| 196 | #define MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0 | ||
| 197 | #define MX6DL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0 | ||
| 198 | #define MX6DL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1 | ||
| 199 | #define MX6DL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0 | ||
| 200 | #define MX6DL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0 | ||
| 201 | #define MX6DL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0 | ||
| 202 | #define MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0 | ||
| 203 | #define MX6DL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 | ||
| 204 | #define MX6DL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1 | ||
| 205 | #define MX6DL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0 | ||
| 206 | #define MX6DL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0 | ||
| 207 | #define MX6DL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0 | ||
| 208 | #define MX6DL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0 | ||
| 209 | #define MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0 | ||
| 210 | #define MX6DL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0 | ||
| 211 | #define MX6DL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1 | ||
| 212 | #define MX6DL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0 | ||
| 213 | #define MX6DL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0 | ||
| 214 | #define MX6DL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0 | ||
| 215 | #define MX6DL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0 | ||
| 216 | #define MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0 | ||
| 217 | #define MX6DL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0 | ||
| 218 | #define MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0 | ||
| 219 | #define MX6DL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0 | ||
| 220 | #define MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0 | ||
| 221 | #define MX6DL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0 | ||
| 222 | #define MX6DL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1 | ||
| 223 | #define MX6DL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0 | ||
| 224 | #define MX6DL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0 | ||
| 225 | #define MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0 | ||
| 226 | #define MX6DL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0 | ||
| 227 | #define MX6DL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1 | ||
| 228 | #define MX6DL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0 | ||
| 229 | #define MX6DL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0 | ||
| 230 | #define MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0 | ||
| 231 | #define MX6DL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0 | ||
| 232 | #define MX6DL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1 | ||
| 233 | #define MX6DL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0 | ||
| 234 | #define MX6DL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0 | ||
| 235 | #define MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0 | ||
| 236 | #define MX6DL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0 | ||
| 237 | #define MX6DL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1 | ||
| 238 | #define MX6DL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0 | ||
| 239 | #define MX6DL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0 | ||
| 240 | #define MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0 | ||
| 241 | #define MX6DL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0 | ||
| 242 | #define MX6DL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0 | ||
| 243 | #define MX6DL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0 | ||
| 244 | #define MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0 | ||
| 245 | #define MX6DL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0 | ||
| 246 | #define MX6DL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0 | ||
| 247 | #define MX6DL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0 | ||
| 248 | #define MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0 | ||
| 249 | #define MX6DL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0 | ||
| 250 | #define MX6DL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0 | ||
| 251 | #define MX6DL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0 | ||
| 252 | #define MX6DL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0 | ||
| 253 | #define MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0 | ||
| 254 | #define MX6DL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0 | ||
| 255 | #define MX6DL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0 | ||
| 256 | #define MX6DL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0 | ||
| 257 | #define MX6DL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0 | ||
| 258 | #define MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0 | ||
| 259 | #define MX6DL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0 | ||
| 260 | #define MX6DL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0 | ||
| 261 | #define MX6DL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0 | ||
| 262 | #define MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0 | ||
| 263 | #define MX6DL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0 | ||
| 264 | #define MX6DL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0 | ||
| 265 | #define MX6DL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0 | ||
| 266 | #define MX6DL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0 | ||
| 267 | #define MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0 | ||
| 268 | #define MX6DL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0 | ||
| 269 | #define MX6DL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0 | ||
| 270 | #define MX6DL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0 | ||
| 271 | #define MX6DL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0 | ||
| 272 | #define MX6DL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0 | ||
| 273 | #define MX6DL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0 | ||
| 274 | #define MX6DL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0 | ||
| 275 | #define MX6DL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0 | ||
| 276 | #define MX6DL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0 | ||
| 277 | #define MX6DL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0 | ||
| 278 | #define MX6DL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0 | ||
| 279 | #define MX6DL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0 | ||
| 280 | #define MX6DL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0 | ||
| 281 | #define MX6DL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0 | ||
| 282 | #define MX6DL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0 | ||
| 283 | #define MX6DL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0 | ||
| 284 | #define MX6DL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0 | ||
| 285 | #define MX6DL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0 | ||
| 286 | #define MX6DL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0 | ||
| 287 | #define MX6DL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0 | ||
| 288 | #define MX6DL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0 | ||
| 289 | #define MX6DL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0 | ||
| 290 | #define MX6DL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0 | ||
| 291 | #define MX6DL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0 | ||
| 292 | #define MX6DL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0 | ||
| 293 | #define MX6DL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0 | ||
| 294 | #define MX6DL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0 | ||
| 295 | #define MX6DL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0 | ||
| 296 | #define MX6DL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0 | ||
| 297 | #define MX6DL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0 | ||
| 298 | #define MX6DL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0 | ||
| 299 | #define MX6DL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0 | ||
| 300 | #define MX6DL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0 | ||
| 301 | #define MX6DL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0 | ||
| 302 | #define MX6DL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0 | ||
| 303 | #define MX6DL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0 | ||
| 304 | #define MX6DL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0 | ||
| 305 | #define MX6DL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0 | ||
| 306 | #define MX6DL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0 | ||
| 307 | #define MX6DL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0 | ||
| 308 | #define MX6DL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0 | ||
| 309 | #define MX6DL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0 | ||
| 310 | #define MX6DL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0 | ||
| 311 | #define MX6DL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0 | ||
| 312 | #define MX6DL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0 | ||
| 313 | #define MX6DL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0 | ||
| 314 | #define MX6DL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0 | ||
| 315 | #define MX6DL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0 | ||
| 316 | #define MX6DL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0 | ||
| 317 | #define MX6DL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0 | ||
| 318 | #define MX6DL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0 | ||
| 319 | #define MX6DL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0 | ||
| 320 | #define MX6DL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0 | ||
| 321 | #define MX6DL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0 | ||
| 322 | #define MX6DL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0 | ||
| 323 | #define MX6DL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0 | ||
| 324 | #define MX6DL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0 | ||
| 325 | #define MX6DL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0 | ||
| 326 | #define MX6DL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0 | ||
| 327 | #define MX6DL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0 | ||
| 328 | #define MX6DL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0 | ||
| 329 | #define MX6DL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0 | ||
| 330 | #define MX6DL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0 | ||
| 331 | #define MX6DL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0 | ||
| 332 | #define MX6DL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0 | ||
| 333 | #define MX6DL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0 | ||
| 334 | #define MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0 | ||
| 335 | #define MX6DL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0 | ||
| 336 | #define MX6DL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0 | ||
| 337 | #define MX6DL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0 | ||
| 338 | #define MX6DL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0 | ||
| 339 | #define MX6DL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0 | ||
| 340 | #define MX6DL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0 | ||
| 341 | #define MX6DL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0 | ||
| 342 | #define MX6DL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0 | ||
| 343 | #define MX6DL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2 | ||
| 344 | #define MX6DL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0 | ||
| 345 | #define MX6DL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0 | ||
| 346 | #define MX6DL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0 | ||
| 347 | #define MX6DL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0 | ||
| 348 | #define MX6DL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2 | ||
| 349 | #define MX6DL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0 | ||
| 350 | #define MX6DL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0 | ||
| 351 | #define MX6DL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0 | ||
| 352 | #define MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2 | ||
| 353 | #define MX6DL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0 | ||
| 354 | #define MX6DL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1 | ||
| 355 | #define MX6DL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0 | ||
| 356 | #define MX6DL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0 | ||
| 357 | #define MX6DL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0 | ||
| 358 | #define MX6DL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0 | ||
| 359 | #define MX6DL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0 | ||
| 360 | #define MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2 | ||
| 361 | #define MX6DL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0 | ||
| 362 | #define MX6DL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1 | ||
| 363 | #define MX6DL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0 | ||
| 364 | #define MX6DL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0 | ||
| 365 | #define MX6DL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0 | ||
| 366 | #define MX6DL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0 | ||
| 367 | #define MX6DL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0 | ||
| 368 | #define MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2 | ||
| 369 | #define MX6DL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0 | ||
| 370 | #define MX6DL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1 | ||
| 371 | #define MX6DL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0 | ||
| 372 | #define MX6DL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0 | ||
| 373 | #define MX6DL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0 | ||
| 374 | #define MX6DL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0 | ||
| 375 | #define MX6DL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0 | ||
| 376 | #define MX6DL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1 | ||
| 377 | #define MX6DL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0 | ||
| 378 | #define MX6DL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1 | ||
| 379 | #define MX6DL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0 | ||
| 380 | #define MX6DL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0 | ||
| 381 | #define MX6DL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0 | ||
| 382 | #define MX6DL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0 | ||
| 383 | #define MX6DL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0 | ||
| 384 | #define MX6DL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0 | ||
| 385 | #define MX6DL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0 | ||
| 386 | #define MX6DL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0 | ||
| 387 | #define MX6DL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1 | ||
| 388 | #define MX6DL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1 | ||
| 389 | #define MX6DL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0 | ||
| 390 | #define MX6DL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0 | ||
| 391 | #define MX6DL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0 | ||
| 392 | #define MX6DL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0 | ||
| 393 | #define MX6DL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0 | ||
| 394 | #define MX6DL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0 | ||
| 395 | #define MX6DL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0 | ||
| 396 | #define MX6DL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0 | ||
| 397 | #define MX6DL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0 | ||
| 398 | #define MX6DL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1 | ||
| 399 | #define MX6DL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0 | ||
| 400 | #define MX6DL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0 | ||
| 401 | #define MX6DL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0 | ||
| 402 | #define MX6DL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0 | ||
| 403 | #define MX6DL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0 | ||
| 404 | #define MX6DL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0 | ||
| 405 | #define MX6DL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0 | ||
| 406 | #define MX6DL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0 | ||
| 407 | #define MX6DL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0 | ||
| 408 | #define MX6DL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0 | ||
| 409 | #define MX6DL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0 | ||
| 410 | #define MX6DL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0 | ||
| 411 | #define MX6DL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0 | ||
| 412 | #define MX6DL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0 | ||
| 413 | #define MX6DL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0 | ||
| 414 | #define MX6DL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0 | ||
| 415 | #define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0 | ||
| 416 | #define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0 | ||
| 417 | #define MX6DL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0 | ||
| 418 | #define MX6DL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0 | ||
| 419 | #define MX6DL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0 | ||
| 420 | #define MX6DL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0 | ||
| 421 | #define MX6DL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0 | ||
| 422 | #define MX6DL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0 | ||
| 423 | #define MX6DL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0 | ||
| 424 | #define MX6DL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0 | ||
| 425 | #define MX6DL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1 | ||
| 426 | #define MX6DL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0 | ||
| 427 | #define MX6DL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0 | ||
| 428 | #define MX6DL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0 | ||
| 429 | #define MX6DL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0 | ||
| 430 | #define MX6DL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1 | ||
| 431 | #define MX6DL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0 | ||
| 432 | #define MX6DL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0 | ||
| 433 | #define MX6DL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0 | ||
| 434 | #define MX6DL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0 | ||
| 435 | #define MX6DL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1 | ||
| 436 | #define MX6DL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0 | ||
| 437 | #define MX6DL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0 | ||
| 438 | #define MX6DL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0 | ||
| 439 | #define MX6DL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0 | ||
| 440 | #define MX6DL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0 | ||
| 441 | #define MX6DL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1 | ||
| 442 | #define MX6DL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0 | ||
| 443 | #define MX6DL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0 | ||
| 444 | #define MX6DL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0 | ||
| 445 | #define MX6DL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0 | ||
| 446 | #define MX6DL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0 | ||
| 447 | #define MX6DL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0 | ||
| 448 | #define MX6DL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0 | ||
| 449 | #define MX6DL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0 | ||
| 450 | #define MX6DL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0 | ||
| 451 | #define MX6DL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1 | ||
| 452 | #define MX6DL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1 | ||
| 453 | #define MX6DL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0 | ||
| 454 | #define MX6DL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0 | ||
| 455 | #define MX6DL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0 | ||
| 456 | #define MX6DL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0 | ||
| 457 | #define MX6DL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0 | ||
| 458 | #define MX6DL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0 | ||
| 459 | #define MX6DL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1 | ||
| 460 | #define MX6DL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0 | ||
| 461 | #define MX6DL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1 | ||
| 462 | #define MX6DL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0 | ||
| 463 | #define MX6DL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0 | ||
| 464 | #define MX6DL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0 | ||
| 465 | #define MX6DL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0 | ||
| 466 | #define MX6DL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0 | ||
| 467 | #define MX6DL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0 | ||
| 468 | #define MX6DL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0 | ||
| 469 | #define MX6DL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0 | ||
| 470 | #define MX6DL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1 | ||
| 471 | #define MX6DL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1 | ||
| 472 | #define MX6DL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0 | ||
| 473 | #define MX6DL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0 | ||
| 474 | #define MX6DL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0 | ||
| 475 | #define MX6DL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0 | ||
| 476 | #define MX6DL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0 | ||
| 477 | #define MX6DL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0 | ||
| 478 | #define MX6DL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0 | ||
| 479 | #define MX6DL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0 | ||
| 480 | #define MX6DL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0 | ||
| 481 | #define MX6DL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0 | ||
| 482 | #define MX6DL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1 | ||
| 483 | #define MX6DL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0 | ||
| 484 | #define MX6DL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0 | ||
| 485 | #define MX6DL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0 | ||
| 486 | #define MX6DL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0 | ||
| 487 | #define MX6DL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0 | ||
| 488 | #define MX6DL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0 | ||
| 489 | #define MX6DL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0 | ||
| 490 | #define MX6DL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2 | ||
| 491 | #define MX6DL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0 | ||
| 492 | #define MX6DL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0 | ||
| 493 | #define MX6DL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0 | ||
| 494 | #define MX6DL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0 | ||
| 495 | #define MX6DL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0 | ||
| 496 | #define MX6DL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0 | ||
| 497 | #define MX6DL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0 | ||
| 498 | #define MX6DL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0 | ||
| 499 | #define MX6DL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0 | ||
| 500 | #define MX6DL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0 | ||
| 501 | #define MX6DL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0 | ||
| 502 | #define MX6DL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0 | ||
| 503 | #define MX6DL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0 | ||
| 504 | #define MX6DL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0 | ||
| 505 | #define MX6DL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0 | ||
| 506 | #define MX6DL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0 | ||
| 507 | #define MX6DL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0 | ||
| 508 | #define MX6DL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0 | ||
| 509 | #define MX6DL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0 | ||
| 510 | #define MX6DL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1 | ||
| 511 | #define MX6DL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0 | ||
| 512 | #define MX6DL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0 | ||
| 513 | #define MX6DL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0 | ||
| 514 | #define MX6DL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0 | ||
| 515 | #define MX6DL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0 | ||
| 516 | #define MX6DL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0 | ||
| 517 | #define MX6DL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0 | ||
| 518 | #define MX6DL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0 | ||
| 519 | #define MX6DL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0 | ||
| 520 | #define MX6DL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0 | ||
| 521 | #define MX6DL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0 | ||
| 522 | #define MX6DL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1 | ||
| 523 | #define MX6DL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0 | ||
| 524 | #define MX6DL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0 | ||
| 525 | #define MX6DL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0 | ||
| 526 | #define MX6DL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0 | ||
| 527 | #define MX6DL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0 | ||
| 528 | #define MX6DL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0 | ||
| 529 | #define MX6DL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0 | ||
| 530 | #define MX6DL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0 | ||
| 531 | #define MX6DL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0 | ||
| 532 | #define MX6DL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0 | ||
| 533 | #define MX6DL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0 | ||
| 534 | #define MX6DL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0 | ||
| 535 | #define MX6DL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0 | ||
| 536 | #define MX6DL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0 | ||
| 537 | #define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0 | ||
| 538 | #define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0 | ||
| 539 | #define MX6DL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0 | ||
| 540 | #define MX6DL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0 | ||
| 541 | #define MX6DL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0 | ||
| 542 | #define MX6DL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0 | ||
| 543 | #define MX6DL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0 | ||
| 544 | #define MX6DL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0 | ||
| 545 | #define MX6DL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0 | ||
| 546 | #define MX6DL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0 | ||
| 547 | #define MX6DL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0 | ||
| 548 | #define MX6DL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0 | ||
| 549 | #define MX6DL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0 | ||
| 550 | #define MX6DL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0 | ||
| 551 | #define MX6DL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0 | ||
| 552 | #define MX6DL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0 | ||
| 553 | #define MX6DL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0 | ||
| 554 | #define MX6DL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0 | ||
| 555 | #define MX6DL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0 | ||
| 556 | #define MX6DL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0 | ||
| 557 | #define MX6DL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0 | ||
| 558 | #define MX6DL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0 | ||
| 559 | #define MX6DL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0 | ||
| 560 | #define MX6DL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0 | ||
| 561 | #define MX6DL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0 | ||
| 562 | #define MX6DL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0 | ||
| 563 | #define MX6DL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0 | ||
| 564 | #define MX6DL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0 | ||
| 565 | #define MX6DL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0 | ||
| 566 | #define MX6DL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0 | ||
| 567 | #define MX6DL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0 | ||
| 568 | #define MX6DL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0 | ||
| 569 | #define MX6DL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0 | ||
| 570 | #define MX6DL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0 | ||
| 571 | #define MX6DL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0 | ||
| 572 | #define MX6DL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0 | ||
| 573 | #define MX6DL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0 | ||
| 574 | #define MX6DL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0 | ||
| 575 | #define MX6DL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0 | ||
| 576 | #define MX6DL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0 | ||
| 577 | #define MX6DL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0 | ||
| 578 | #define MX6DL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0 | ||
| 579 | #define MX6DL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0 | ||
| 580 | #define MX6DL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0 | ||
| 581 | #define MX6DL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0 | ||
| 582 | #define MX6DL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0 | ||
| 583 | #define MX6DL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0 | ||
| 584 | #define MX6DL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0 | ||
| 585 | #define MX6DL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0 | ||
| 586 | #define MX6DL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0 | ||
| 587 | #define MX6DL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0 | ||
| 588 | #define MX6DL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0 | ||
| 589 | #define MX6DL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0 | ||
| 590 | #define MX6DL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0 | ||
| 591 | #define MX6DL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0 | ||
| 592 | #define MX6DL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1 | ||
| 593 | #define MX6DL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0 | ||
| 594 | #define MX6DL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0 | ||
| 595 | #define MX6DL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0 | ||
| 596 | #define MX6DL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0 | ||
| 597 | #define MX6DL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0 | ||
| 598 | #define MX6DL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0 | ||
| 599 | #define MX6DL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1 | ||
| 600 | #define MX6DL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0 | ||
| 601 | #define MX6DL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0 | ||
| 602 | #define MX6DL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0 | ||
| 603 | #define MX6DL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0 | ||
| 604 | #define MX6DL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2 | ||
| 605 | #define MX6DL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1 | ||
| 606 | #define MX6DL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0 | ||
| 607 | #define MX6DL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0 | ||
| 608 | #define MX6DL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0 | ||
| 609 | #define MX6DL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0 | ||
| 610 | #define MX6DL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0 | ||
| 611 | #define MX6DL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0 | ||
| 612 | #define MX6DL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0 | ||
| 613 | #define MX6DL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3 | ||
| 614 | #define MX6DL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0 | ||
| 615 | #define MX6DL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0 | ||
| 616 | #define MX6DL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1 | ||
| 617 | #define MX6DL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0 | ||
| 618 | #define MX6DL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0 | ||
| 619 | #define MX6DL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0 | ||
| 620 | #define MX6DL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0 | ||
| 621 | #define MX6DL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0 | ||
| 622 | #define MX6DL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0 | ||
| 623 | #define MX6DL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0 | ||
| 624 | #define MX6DL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1 | ||
| 625 | #define MX6DL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0 | ||
| 626 | #define MX6DL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0 | ||
| 627 | #define MX6DL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0 | ||
| 628 | #define MX6DL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0 | ||
| 629 | #define MX6DL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0 | ||
| 630 | #define MX6DL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2 | ||
| 631 | #define MX6DL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0 | ||
| 632 | #define MX6DL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0 | ||
| 633 | #define MX6DL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0 | ||
| 634 | #define MX6DL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0 | ||
| 635 | #define MX6DL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2 | ||
| 636 | #define MX6DL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0 | ||
| 637 | #define MX6DL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0 | ||
| 638 | #define MX6DL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0 | ||
| 639 | #define MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0 | ||
| 640 | #define MX6DL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0 | ||
| 641 | #define MX6DL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0 | ||
| 642 | #define MX6DL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0 | ||
| 643 | #define MX6DL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0 | ||
| 644 | #define MX6DL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0 | ||
| 645 | #define MX6DL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0 | ||
| 646 | #define MX6DL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0 | ||
| 647 | #define MX6DL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0 | ||
| 648 | #define MX6DL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0 | ||
| 649 | #define MX6DL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0 | ||
| 650 | #define MX6DL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0 | ||
| 651 | #define MX6DL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0 | ||
| 652 | #define MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0 | ||
| 653 | #define MX6DL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0 | ||
| 654 | #define MX6DL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0 | ||
| 655 | #define MX6DL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0 | ||
| 656 | #define MX6DL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0 | ||
| 657 | #define MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0 | ||
| 658 | #define MX6DL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0 | ||
| 659 | #define MX6DL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0 | ||
| 660 | #define MX6DL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0 | ||
| 661 | #define MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0 | ||
| 662 | #define MX6DL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0 | ||
| 663 | #define MX6DL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0 | ||
| 664 | #define MX6DL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1 | ||
| 665 | #define MX6DL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0 | ||
| 666 | #define MX6DL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0 | ||
| 667 | #define MX6DL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0 | ||
| 668 | #define MX6DL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0 | ||
| 669 | #define MX6DL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0 | ||
| 670 | #define MX6DL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0 | ||
| 671 | #define MX6DL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0 | ||
| 672 | #define MX6DL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0 | ||
| 673 | #define MX6DL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0 | ||
| 674 | #define MX6DL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0 | ||
| 675 | #define MX6DL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0 | ||
| 676 | #define MX6DL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0 | ||
| 677 | #define MX6DL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0 | ||
| 678 | #define MX6DL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0 | ||
| 679 | #define MX6DL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0 | ||
| 680 | #define MX6DL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0 | ||
| 681 | #define MX6DL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0 | ||
| 682 | #define MX6DL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0 | ||
| 683 | #define MX6DL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0 | ||
| 684 | #define MX6DL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0 | ||
| 685 | #define MX6DL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0 | ||
| 686 | #define MX6DL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0 | ||
| 687 | #define MX6DL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0 | ||
| 688 | #define MX6DL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0 | ||
| 689 | #define MX6DL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0 | ||
| 690 | #define MX6DL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1 | ||
| 691 | #define MX6DL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0 | ||
| 692 | #define MX6DL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0 | ||
| 693 | #define MX6DL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0 | ||
| 694 | #define MX6DL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0 | ||
| 695 | #define MX6DL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0 | ||
| 696 | #define MX6DL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1 | ||
| 697 | #define MX6DL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0 | ||
| 698 | #define MX6DL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1 | ||
| 699 | #define MX6DL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1 | ||
| 700 | #define MX6DL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0 | ||
| 701 | #define MX6DL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0 | ||
| 702 | #define MX6DL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0 | ||
| 703 | #define MX6DL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1 | ||
| 704 | #define MX6DL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0 | ||
| 705 | #define MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0 | ||
| 706 | #define MX6DL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0 | ||
| 707 | #define MX6DL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2 | ||
| 708 | #define MX6DL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0 | ||
| 709 | #define MX6DL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1 | ||
| 710 | #define MX6DL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0 | ||
| 711 | #define MX6DL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0 | ||
| 712 | #define MX6DL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0 | ||
| 713 | #define MX6DL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1 | ||
| 714 | #define MX6DL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1 | ||
| 715 | #define MX6DL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0 | ||
| 716 | #define MX6DL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0 | ||
| 717 | #define MX6DL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0 | ||
| 718 | #define MX6DL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0 | ||
| 719 | #define MX6DL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0 | ||
| 720 | #define MX6DL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1 | ||
| 721 | #define MX6DL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1 | ||
| 722 | #define MX6DL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0 | ||
| 723 | #define MX6DL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0 | ||
| 724 | #define MX6DL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2 | ||
| 725 | #define MX6DL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0 | ||
| 726 | #define MX6DL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0 | ||
| 727 | #define MX6DL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0 | ||
| 728 | #define MX6DL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0 | ||
| 729 | #define MX6DL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0 | ||
| 730 | #define MX6DL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0 | ||
| 731 | #define MX6DL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1 | ||
| 732 | #define MX6DL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1 | ||
| 733 | #define MX6DL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0 | ||
| 734 | #define MX6DL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0 | ||
| 735 | #define MX6DL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1 | ||
| 736 | #define MX6DL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1 | ||
| 737 | #define MX6DL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1 | ||
| 738 | #define MX6DL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0 | ||
| 739 | #define MX6DL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0 | ||
| 740 | #define MX6DL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0 | ||
| 741 | #define MX6DL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1 | ||
| 742 | #define MX6DL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1 | ||
| 743 | #define MX6DL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1 | ||
| 744 | #define MX6DL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1 | ||
| 745 | #define MX6DL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0 | ||
| 746 | #define MX6DL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0 | ||
| 747 | #define MX6DL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1 | ||
| 748 | #define MX6DL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1 | ||
| 749 | #define MX6DL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0 | ||
| 750 | #define MX6DL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0 | ||
| 751 | #define MX6DL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 | ||
| 752 | #define MX6DL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 | ||
| 753 | #define MX6DL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 | ||
| 754 | #define MX6DL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 | ||
| 755 | #define MX6DL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 | ||
| 756 | #define MX6DL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 | ||
| 757 | #define MX6DL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1 | ||
| 758 | #define MX6DL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1 | ||
| 759 | #define MX6DL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0 | ||
| 760 | #define MX6DL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0 | ||
| 761 | #define MX6DL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0 | ||
| 762 | #define MX6DL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2 | ||
| 763 | #define MX6DL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0 | ||
| 764 | #define MX6DL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0 | ||
| 765 | #define MX6DL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0 | ||
| 766 | #define MX6DL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1 | ||
| 767 | #define MX6DL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1 | ||
| 768 | #define MX6DL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0 | ||
| 769 | #define MX6DL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0 | ||
| 770 | #define MX6DL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0 | ||
| 771 | #define MX6DL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3 | ||
| 772 | #define MX6DL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0 | ||
| 773 | #define MX6DL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0 | ||
| 774 | #define MX6DL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0 | ||
| 775 | #define MX6DL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0 | ||
| 776 | #define MX6DL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1 | ||
| 777 | #define MX6DL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1 | ||
| 778 | #define MX6DL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0 | ||
| 779 | #define MX6DL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1 | ||
| 780 | #define MX6DL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0 | ||
| 781 | #define MX6DL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0 | ||
| 782 | #define MX6DL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0 | ||
| 783 | #define MX6DL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1 | ||
| 784 | #define MX6DL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3 | ||
| 785 | #define MX6DL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0 | ||
| 786 | #define MX6DL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1 | ||
| 787 | #define MX6DL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0 | ||
| 788 | #define MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0 | ||
| 789 | #define MX6DL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2 | ||
| 790 | #define MX6DL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0 | ||
| 791 | #define MX6DL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0 | ||
| 792 | #define MX6DL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3 | ||
| 793 | #define MX6DL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1 | ||
| 794 | #define MX6DL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1 | ||
| 795 | #define MX6DL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0 | ||
| 796 | #define MX6DL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0 | ||
| 797 | #define MX6DL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2 | ||
| 798 | #define MX6DL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0 | ||
| 799 | #define MX6DL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0 | ||
| 800 | #define MX6DL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2 | ||
| 801 | #define MX6DL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0 | ||
| 802 | #define MX6DL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0 | ||
| 803 | #define MX6DL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0 | ||
| 804 | #define MX6DL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0 | ||
| 805 | #define MX6DL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0 | ||
| 806 | #define MX6DL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0 | ||
| 807 | #define MX6DL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1 | ||
| 808 | #define MX6DL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0 | ||
| 809 | #define MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1 | ||
| 810 | #define MX6DL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0 | ||
| 811 | #define MX6DL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1 | ||
| 812 | #define MX6DL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0 | ||
| 813 | #define MX6DL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3 | ||
| 814 | #define MX6DL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0 | ||
| 815 | #define MX6DL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0 | ||
| 816 | #define MX6DL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1 | ||
| 817 | #define MX6DL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0 | ||
| 818 | #define MX6DL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2 | ||
| 819 | #define MX6DL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0 | ||
| 820 | #define MX6DL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0 | ||
| 821 | #define MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3 | ||
| 822 | #define MX6DL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0 | ||
| 823 | #define MX6DL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1 | ||
| 824 | #define MX6DL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0 | ||
| 825 | #define MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3 | ||
| 826 | #define MX6DL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0 | ||
| 827 | #define MX6DL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0 | ||
| 828 | #define MX6DL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0 | ||
| 829 | #define MX6DL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3 | ||
| 830 | #define MX6DL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0 | ||
| 831 | #define MX6DL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1 | ||
| 832 | #define MX6DL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0 | ||
| 833 | #define MX6DL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3 | ||
| 834 | #define MX6DL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0 | ||
| 835 | #define MX6DL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0 | ||
| 836 | #define MX6DL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0 | ||
| 837 | #define MX6DL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1 | ||
| 838 | #define MX6DL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0 | ||
| 839 | #define MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1 | ||
| 840 | #define MX6DL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0 | ||
| 841 | #define MX6DL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0 | ||
| 842 | #define MX6DL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0 | ||
| 843 | #define MX6DL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1 | ||
| 844 | #define MX6DL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2 | ||
| 845 | #define MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1 | ||
| 846 | #define MX6DL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0 | ||
| 847 | #define MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1 | ||
| 848 | #define MX6DL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0 | ||
| 849 | #define MX6DL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0 | ||
| 850 | #define MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0 | ||
| 851 | #define MX6DL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0 | ||
| 852 | #define MX6DL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0 | ||
| 853 | #define MX6DL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0 | ||
| 854 | #define MX6DL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0 | ||
| 855 | #define MX6DL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3 | ||
| 856 | #define MX6DL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0 | ||
| 857 | #define MX6DL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0 | ||
| 858 | #define MX6DL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0 | ||
| 859 | #define MX6DL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0 | ||
| 860 | #define MX6DL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0 | ||
| 861 | #define MX6DL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0 | ||
| 862 | #define MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0 | ||
| 863 | #define MX6DL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0 | ||
| 864 | #define MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0 | ||
| 865 | #define MX6DL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0 | ||
| 866 | #define MX6DL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0 | ||
| 867 | #define MX6DL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0 | ||
| 868 | #define MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0 | ||
| 869 | #define MX6DL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0 | ||
| 870 | #define MX6DL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1 | ||
| 871 | #define MX6DL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0 | ||
| 872 | #define MX6DL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0 | ||
| 873 | #define MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0 | ||
| 874 | #define MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0 | ||
| 875 | #define MX6DL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0 | ||
| 876 | #define MX6DL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1 | ||
| 877 | #define MX6DL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0 | ||
| 878 | #define MX6DL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0 | ||
| 879 | #define MX6DL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2 | ||
| 880 | #define MX6DL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0 | ||
| 881 | #define MX6DL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0 | ||
| 882 | #define MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0 | ||
| 883 | #define MX6DL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0 | ||
| 884 | #define MX6DL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0 | ||
| 885 | #define MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0 | ||
| 886 | #define MX6DL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0 | ||
| 887 | #define MX6DL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0 | ||
| 888 | #define MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0 | ||
| 889 | #define MX6DL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0 | ||
| 890 | #define MX6DL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0 | ||
| 891 | #define MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0 | ||
| 892 | #define MX6DL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0 | ||
| 893 | #define MX6DL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0 | ||
| 894 | #define MX6DL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0 | ||
| 895 | #define MX6DL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0 | ||
| 896 | #define MX6DL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0 | ||
| 897 | #define MX6DL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0 | ||
| 898 | #define MX6DL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0 | ||
| 899 | #define MX6DL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0 | ||
| 900 | #define MX6DL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0 | ||
| 901 | #define MX6DL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0 | ||
| 902 | #define MX6DL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0 | ||
| 903 | #define MX6DL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0 | ||
| 904 | #define MX6DL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0 | ||
| 905 | #define MX6DL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0 | ||
| 906 | #define MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0 | ||
| 907 | #define MX6DL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0 | ||
| 908 | #define MX6DL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2 | ||
| 909 | #define MX6DL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0 | ||
| 910 | #define MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1 | ||
| 911 | #define MX6DL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0 | ||
| 912 | #define MX6DL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0 | ||
| 913 | #define MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1 | ||
| 914 | #define MX6DL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0 | ||
| 915 | #define MX6DL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0 | ||
| 916 | #define MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1 | ||
| 917 | #define MX6DL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0 | ||
| 918 | #define MX6DL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0 | ||
| 919 | #define MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1 | ||
| 920 | #define MX6DL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0 | ||
| 921 | #define MX6DL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0 | ||
| 922 | #define MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1 | ||
| 923 | #define MX6DL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0 | ||
| 924 | #define MX6DL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0 | ||
| 925 | #define MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1 | ||
| 926 | #define MX6DL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0 | ||
| 927 | #define MX6DL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0 | ||
| 928 | #define MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0 | ||
| 929 | #define MX6DL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0 | ||
| 930 | #define MX6DL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0 | ||
| 931 | #define MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0 | ||
| 932 | #define MX6DL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0 | ||
| 933 | #define MX6DL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0 | ||
| 934 | #define MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0 | ||
| 935 | #define MX6DL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0 | ||
| 936 | #define MX6DL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0 | ||
| 937 | #define MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0 | ||
| 938 | #define MX6DL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0 | ||
| 939 | #define MX6DL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0 | ||
| 940 | #define MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0 | ||
| 941 | #define MX6DL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0 | ||
| 942 | #define MX6DL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1 | ||
| 943 | #define MX6DL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0 | ||
| 944 | #define MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0 | ||
| 945 | #define MX6DL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1 | ||
| 946 | #define MX6DL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 | ||
| 947 | #define MX6DL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 | ||
| 948 | #define MX6DL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 | ||
| 949 | #define MX6DL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 | ||
| 950 | #define MX6DL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 | ||
| 951 | #define MX6DL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 | ||
| 952 | #define MX6DL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0 | ||
| 953 | #define MX6DL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0 | ||
| 954 | #define MX6DL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0 | ||
| 955 | #define MX6DL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0 | ||
| 956 | #define MX6DL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0 | ||
| 957 | #define MX6DL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0 | ||
| 958 | #define MX6DL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0 | ||
| 959 | #define MX6DL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0 | ||
| 960 | #define MX6DL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0 | ||
| 961 | #define MX6DL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0 | ||
| 962 | #define MX6DL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0 | ||
| 963 | #define MX6DL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0 | ||
| 964 | #define MX6DL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0 | ||
| 965 | #define MX6DL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0 | ||
| 966 | #define MX6DL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0 | ||
| 967 | #define MX6DL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0 | ||
| 968 | #define MX6DL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0 | ||
| 969 | #define MX6DL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0 | ||
| 970 | #define MX6DL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0 | ||
| 971 | #define MX6DL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0 | ||
| 972 | #define MX6DL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0 | ||
| 973 | #define MX6DL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0 | ||
| 974 | #define MX6DL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1 | ||
| 975 | #define MX6DL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3 | ||
| 976 | #define MX6DL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1 | ||
| 977 | #define MX6DL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0 | ||
| 978 | #define MX6DL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0 | ||
| 979 | #define MX6DL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2 | ||
| 980 | #define MX6DL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1 | ||
| 981 | #define MX6DL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0 | ||
| 982 | #define MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0 | ||
| 983 | #define MX6DL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1 | ||
| 984 | #define MX6DL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2 | ||
| 985 | #define MX6DL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0 | ||
| 986 | #define MX6DL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0 | ||
| 987 | #define MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0 | ||
| 988 | #define MX6DL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0 | ||
| 989 | #define MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1 | ||
| 990 | #define MX6DL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2 | ||
| 991 | #define MX6DL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0 | ||
| 992 | #define MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0 | ||
| 993 | #define MX6DL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0 | ||
| 994 | #define MX6DL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1 | ||
| 995 | #define MX6DL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2 | ||
| 996 | #define MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0 | ||
| 997 | #define MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0 | ||
| 998 | #define MX6DL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2 | ||
| 999 | #define MX6DL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1 | ||
| 1000 | #define MX6DL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0 | ||
| 1001 | #define MX6DL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1 | ||
| 1002 | #define MX6DL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2 | ||
| 1003 | #define MX6DL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0 | ||
| 1004 | #define MX6DL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2 | ||
| 1005 | #define MX6DL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0 | ||
| 1006 | #define MX6DL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0 | ||
| 1007 | #define MX6DL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0 | ||
| 1008 | #define MX6DL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3 | ||
| 1009 | #define MX6DL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0 | ||
| 1010 | #define MX6DL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0 | ||
| 1011 | #define MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0 | ||
| 1012 | #define MX6DL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0 | ||
| 1013 | #define MX6DL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2 | ||
| 1014 | #define MX6DL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0 | ||
| 1015 | #define MX6DL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0 | ||
| 1016 | #define MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0 | ||
| 1017 | #define MX6DL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3 | ||
| 1018 | #define MX6DL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0 | ||
| 1019 | #define MX6DL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1 | ||
| 1020 | #define MX6DL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0 | ||
| 1021 | #define MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0 | ||
| 1022 | #define MX6DL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0 | ||
| 1023 | #define MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0 | ||
| 1024 | #define MX6DL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0 | ||
| 1025 | #define MX6DL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4 | ||
| 1026 | #define MX6DL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0 | ||
| 1027 | #define MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0 | ||
| 1028 | #define MX6DL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4 | ||
| 1029 | #define MX6DL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0 | ||
| 1030 | #define MX6DL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0 | ||
| 1031 | #define MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0 | ||
| 1032 | #define MX6DL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0 | ||
| 1033 | #define MX6DL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5 | ||
| 1034 | #define MX6DL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0 | ||
| 1035 | #define MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0 | ||
| 1036 | #define MX6DL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2 | ||
| 1037 | #define MX6DL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0 | ||
| 1038 | #define MX6DL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0 | ||
| 1039 | #define MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0 | ||
| 1040 | #define MX6DL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0 | ||
| 1041 | #define MX6DL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3 | ||
| 1042 | #define MX6DL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0 | ||
| 1043 | #define MX6DL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0 | ||
| 1044 | #define MX6DL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5 | ||
| 1045 | #define MX6DL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0 | ||
| 1046 | #define MX6DL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0 | ||
| 1047 | #define MX6DL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1 | ||
| 1048 | #define MX6DL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0 | ||
| 1049 | #define MX6DL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2 | ||
| 1050 | #define MX6DL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0 | ||
| 1051 | #define MX6DL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0 | ||
| 1052 | #define MX6DL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0 | ||
| 1053 | #define MX6DL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0 | ||
| 1054 | #define MX6DL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0 | ||
| 1055 | #define MX6DL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3 | ||
| 1056 | #define MX6DL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0 | ||
| 1057 | #define MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0 | ||
| 1058 | #define MX6DL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0 | ||
| 1059 | #define MX6DL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0 | ||
| 1060 | #define MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0 | ||
| 1061 | #define MX6DL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0 | ||
| 1062 | #define MX6DL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0 | ||
| 1063 | #define MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0 | ||
| 1064 | #define MX6DL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 | ||
| 1065 | #define MX6DL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0 | ||
| 1066 | #define MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0 | ||
| 1067 | #define MX6DL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0 | ||
| 1068 | #define MX6DL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0 | ||
| 1069 | #define MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6 | ||
| 1070 | #define MX6DL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0 | ||
| 1071 | #define MX6DL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0 | ||
| 1072 | #define MX6DL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0 | ||
| 1073 | #define MX6DL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4 | ||
| 1074 | #define MX6DL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0 | ||
| 1075 | #define MX6DL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0 | ||
| 1076 | #define MX6DL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0 | ||
| 1077 | #define MX6DL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0 | ||
| 1078 | #define MX6DL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5 | ||
| 1079 | #define MX6DL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0 | ||
| 1080 | #define MX6DL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0 | ||
| 1081 | #define MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0 | ||
| 1082 | #define MX6DL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7 | ||
| 1083 | #define MX6DL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0 | ||
| 1084 | |||
| 1085 | #endif /* __DTS_IMX6DL_PINFUNC_H */ | ||
diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts new file mode 100644 index 000000000000..7adcec360213 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /dts-v1/; | ||
| 10 | |||
| 11 | #include "imx6dl.dtsi" | ||
| 12 | #include "imx6qdl-sabreauto.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; | ||
| 16 | compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; | ||
| 17 | }; | ||
| 18 | |||
| 19 | &iomuxc { | ||
| 20 | pinctrl-names = "default"; | ||
| 21 | pinctrl-0 = <&pinctrl_hog>; | ||
| 22 | |||
| 23 | hog { | ||
| 24 | pinctrl_hog: hoggrp { | ||
| 25 | fsl,pins = < | ||
| 26 | MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 | ||
| 27 | MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 | ||
| 28 | >; | ||
| 29 | }; | ||
| 30 | }; | ||
| 31 | }; | ||
diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts new file mode 100644 index 000000000000..7efb05db4783 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabresd.dts | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /dts-v1/; | ||
| 10 | |||
| 11 | #include "imx6dl.dtsi" | ||
| 12 | #include "imx6qdl-sabresd.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; | ||
| 16 | compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; | ||
| 17 | }; | ||
| 18 | |||
| 19 | &iomuxc { | ||
| 20 | pinctrl-names = "default"; | ||
| 21 | pinctrl-0 = <&pinctrl_hog>; | ||
| 22 | |||
| 23 | hog { | ||
| 24 | pinctrl_hog: hoggrp { | ||
| 25 | fsl,pins = < | ||
| 26 | MX6DL_PAD_GPIO_4__GPIO1_IO04 0x80000000 | ||
| 27 | MX6DL_PAD_GPIO_5__GPIO1_IO05 0x80000000 | ||
| 28 | MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 | ||
| 29 | MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 | ||
| 30 | MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 | ||
| 31 | MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 | ||
| 32 | >; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | }; | ||
diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts new file mode 100644 index 000000000000..bfc59c3566a4 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-wandboard.dts | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | /dts-v1/; | ||
| 12 | #include "imx6dl.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "Wandboard i.MX6 Dual Lite Board"; | ||
| 16 | compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; | ||
| 17 | |||
| 18 | memory { | ||
| 19 | reg = <0x10000000 0x40000000>; | ||
| 20 | }; | ||
| 21 | }; | ||
| 22 | |||
| 23 | &fec { | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | pinctrl-0 = <&pinctrl_enet_1>; | ||
| 26 | phy-mode = "rgmii"; | ||
| 27 | status = "okay"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | &uart1 { | ||
| 31 | pinctrl-names = "default"; | ||
| 32 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | &usbh1 { | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | |||
| 40 | &usdhc3 { | ||
| 41 | pinctrl-names = "default"; | ||
| 42 | pinctrl-0 = <&pinctrl_usdhc3_2>; | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 63fafe2a606c..5bcdf3a90bb3 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi | |||
| @@ -1,3 +1,4 @@ | |||
| 1 | |||
| 1 | /* | 2 | /* |
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. | 3 | * Copyright 2013 Freescale Semiconductor, Inc. |
| 3 | * | 4 | * |
| @@ -7,7 +8,8 @@ | |||
| 7 | * | 8 | * |
| 8 | */ | 9 | */ |
| 9 | 10 | ||
| 10 | /include/ "imx6qdl.dtsi" | 11 | #include "imx6qdl.dtsi" |
| 12 | #include "imx6dl-pinfunc.h" | ||
| 11 | 13 | ||
| 12 | / { | 14 | / { |
| 13 | cpus { | 15 | cpus { |
| @@ -29,6 +31,127 @@ | |||
| 29 | 31 | ||
| 30 | soc { | 32 | soc { |
| 31 | aips1: aips-bus@02000000 { | 33 | aips1: aips-bus@02000000 { |
| 34 | iomuxc: iomuxc@020e0000 { | ||
| 35 | compatible = "fsl,imx6dl-iomuxc"; | ||
| 36 | reg = <0x020e0000 0x4000>; | ||
| 37 | |||
| 38 | enet { | ||
| 39 | pinctrl_enet_1: enetgrp-1 { | ||
| 40 | fsl,pins = < | ||
| 41 | MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 42 | MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 43 | MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 44 | MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 45 | MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 46 | MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 47 | MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 48 | MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 49 | MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 50 | MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 51 | MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 52 | MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 53 | MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 54 | MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 55 | MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 56 | MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 57 | >; | ||
| 58 | }; | ||
| 59 | |||
| 60 | pinctrl_enet_2: enetgrp-2 { | ||
| 61 | fsl,pins = < | ||
| 62 | MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 | ||
| 63 | MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 | ||
| 64 | MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 65 | MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 66 | MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 67 | MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 68 | MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 69 | MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 70 | MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 71 | MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 72 | MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 73 | MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 74 | MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 75 | MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 76 | MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 77 | >; | ||
| 78 | }; | ||
| 79 | }; | ||
| 80 | |||
| 81 | uart1 { | ||
| 82 | pinctrl_uart1_1: uart1grp-1 { | ||
| 83 | fsl,pins = < | ||
| 84 | MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | ||
| 85 | MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | ||
| 86 | >; | ||
| 87 | }; | ||
| 88 | }; | ||
| 89 | |||
| 90 | uart4 { | ||
| 91 | pinctrl_uart4_1: uart4grp-1 { | ||
| 92 | fsl,pins = < | ||
| 93 | MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | ||
| 94 | MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | ||
| 95 | >; | ||
| 96 | }; | ||
| 97 | }; | ||
| 98 | |||
| 99 | usbotg { | ||
| 100 | pinctrl_usbotg_2: usbotggrp-2 { | ||
| 101 | fsl,pins = < | ||
| 102 | MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | ||
| 103 | >; | ||
| 104 | }; | ||
| 105 | }; | ||
| 106 | |||
| 107 | usdhc2 { | ||
| 108 | pinctrl_usdhc2_1: usdhc2grp-1 { | ||
| 109 | fsl,pins = < | ||
| 110 | MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 111 | MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 112 | MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 113 | MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 114 | MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 115 | MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 116 | MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059 | ||
| 117 | MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059 | ||
| 118 | MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059 | ||
| 119 | MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059 | ||
| 120 | >; | ||
| 121 | }; | ||
| 122 | }; | ||
| 123 | |||
| 124 | usdhc3 { | ||
| 125 | pinctrl_usdhc3_1: usdhc3grp-1 { | ||
| 126 | fsl,pins = < | ||
| 127 | MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 128 | MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 129 | MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 130 | MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 131 | MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 132 | MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 133 | MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059 | ||
| 134 | MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059 | ||
| 135 | MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059 | ||
| 136 | MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059 | ||
| 137 | >; | ||
| 138 | }; | ||
| 139 | |||
| 140 | pinctrl_usdhc3_2: usdhc3grp_2 { | ||
| 141 | fsl,pins = < | ||
| 142 | MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 143 | MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 144 | MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 145 | MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 146 | MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 147 | MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 148 | >; | ||
| 149 | }; | ||
| 150 | }; | ||
| 151 | |||
| 152 | |||
| 153 | }; | ||
| 154 | |||
| 32 | pxp: pxp@020f0000 { | 155 | pxp: pxp@020f0000 { |
| 33 | reg = <0x020f0000 0x4000>; | 156 | reg = <0x020f0000 0x4000>; |
| 34 | interrupts = <0 98 0x04>; | 157 | interrupts = <0 98 0x04>; |
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index 53eb241fa5ad..4e54fde591bd 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts | |||
| @@ -11,7 +11,7 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /dts-v1/; | 13 | /dts-v1/; |
| 14 | /include/ "imx6q.dtsi" | 14 | #include "imx6q.dtsi" |
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | model = "Freescale i.MX6 Quad Armadillo2 Board"; | 17 | model = "Freescale i.MX6 Quad Armadillo2 Board"; |
| @@ -57,7 +57,7 @@ | |||
| 57 | hog { | 57 | hog { |
| 58 | pinctrl_hog: hoggrp { | 58 | pinctrl_hog: hoggrp { |
| 59 | fsl,pins = < | 59 | fsl,pins = < |
| 60 | 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */ | 60 | MX6Q_PAD_EIM_D25__GPIO3_IO25 0x80000000 |
| 61 | >; | 61 | >; |
| 62 | }; | 62 | }; |
| 63 | }; | 63 | }; |
| @@ -65,8 +65,8 @@ | |||
| 65 | arm2 { | 65 | arm2 { |
| 66 | pinctrl_usdhc3_arm2: usdhc3grp-arm2 { | 66 | pinctrl_usdhc3_arm2: usdhc3grp-arm2 { |
| 67 | fsl,pins = < | 67 | fsl,pins = < |
| 68 | 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */ | 68 | MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 |
| 69 | 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */ | 69 | MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 |
| 70 | >; | 70 | >; |
| 71 | }; | 71 | }; |
| 72 | }; | 72 | }; |
diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h new file mode 100644 index 000000000000..faea6e1ada00 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-pinfunc.h | |||
| @@ -0,0 +1,1041 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __DTS_IMX6Q_PINFUNC_H | ||
| 11 | #define __DTS_IMX6Q_PINFUNC_H | ||
| 12 | |||
| 13 | /* | ||
| 14 | * The pin function ID is a tuple of | ||
| 15 | * <mux_reg conf_reg input_reg mux_mode input_val> | ||
| 16 | */ | ||
| 17 | #define MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 | ||
| 18 | #define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 | ||
| 19 | #define MX6Q_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 | ||
| 20 | #define MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 | ||
| 21 | #define MX6Q_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 | ||
| 22 | #define MX6Q_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 | ||
| 23 | #define MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 | ||
| 24 | #define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 | ||
| 25 | #define MX6Q_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 | ||
| 26 | #define MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 | ||
| 27 | #define MX6Q_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0 | ||
| 28 | #define MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0 | ||
| 29 | #define MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0 | ||
| 30 | #define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0 | ||
| 31 | #define MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0 | ||
| 32 | #define MX6Q_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0 | ||
| 33 | #define MX6Q_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0 | ||
| 34 | #define MX6Q_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0 | ||
| 35 | #define MX6Q_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0 | ||
| 36 | #define MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0 | ||
| 37 | #define MX6Q_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0 | ||
| 38 | #define MX6Q_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0 | ||
| 39 | #define MX6Q_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0 | ||
| 40 | #define MX6Q_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0 | ||
| 41 | #define MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0 | ||
| 42 | #define MX6Q_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0 | ||
| 43 | #define MX6Q_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0 | ||
| 44 | #define MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0 | ||
| 45 | #define MX6Q_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0 | ||
| 46 | #define MX6Q_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0 | ||
| 47 | #define MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0 | ||
| 48 | #define MX6Q_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0 | ||
| 49 | #define MX6Q_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0 | ||
| 50 | #define MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0 | ||
| 51 | #define MX6Q_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0 | ||
| 52 | #define MX6Q_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0 | ||
| 53 | #define MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0 | ||
| 54 | #define MX6Q_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0 | ||
| 55 | #define MX6Q_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0 | ||
| 56 | #define MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0 | ||
| 57 | #define MX6Q_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0 | ||
| 58 | #define MX6Q_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0 | ||
| 59 | #define MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0 | ||
| 60 | #define MX6Q_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0 | ||
| 61 | #define MX6Q_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0 | ||
| 62 | #define MX6Q_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0 | ||
| 63 | #define MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0 | ||
| 64 | #define MX6Q_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0 | ||
| 65 | #define MX6Q_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0 | ||
| 66 | #define MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0 | ||
| 67 | #define MX6Q_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0 | ||
| 68 | #define MX6Q_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0 | ||
| 69 | #define MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0 | ||
| 70 | #define MX6Q_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0 | ||
| 71 | #define MX6Q_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0 | ||
| 72 | #define MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0 | ||
| 73 | #define MX6Q_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0 | ||
| 74 | #define MX6Q_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0 | ||
| 75 | #define MX6Q_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0 | ||
| 76 | #define MX6Q_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0 | ||
| 77 | #define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0 | ||
| 78 | #define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0 | ||
| 79 | #define MX6Q_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0 | ||
| 80 | #define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0 | ||
| 81 | #define MX6Q_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0 | ||
| 82 | #define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0 | ||
| 83 | #define MX6Q_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0 | ||
| 84 | #define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0 | ||
| 85 | #define MX6Q_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0 | ||
| 86 | #define MX6Q_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0 | ||
| 87 | #define MX6Q_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0 | ||
| 88 | #define MX6Q_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0 | ||
| 89 | #define MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0 | ||
| 90 | #define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0 | ||
| 91 | #define MX6Q_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0 | ||
| 92 | #define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0 | ||
| 93 | #define MX6Q_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0 | ||
| 94 | #define MX6Q_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0 | ||
| 95 | #define MX6Q_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0 | ||
| 96 | #define MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0 | ||
| 97 | #define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0 | ||
| 98 | #define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0 | ||
| 99 | #define MX6Q_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0 | ||
| 100 | #define MX6Q_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0 | ||
| 101 | #define MX6Q_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0 | ||
| 102 | #define MX6Q_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0 | ||
| 103 | #define MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0 | ||
| 104 | #define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0 | ||
| 105 | #define MX6Q_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0 | ||
| 106 | #define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0 | ||
| 107 | #define MX6Q_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0 | ||
| 108 | #define MX6Q_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0 | ||
| 109 | #define MX6Q_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0 | ||
| 110 | #define MX6Q_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0 | ||
| 111 | #define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0 | ||
| 112 | #define MX6Q_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0 | ||
| 113 | #define MX6Q_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0 | ||
| 114 | #define MX6Q_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0 | ||
| 115 | #define MX6Q_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0 | ||
| 116 | #define MX6Q_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0 | ||
| 117 | #define MX6Q_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0 | ||
| 118 | #define MX6Q_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0 | ||
| 119 | #define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0 | ||
| 120 | #define MX6Q_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0 | ||
| 121 | #define MX6Q_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1 | ||
| 122 | #define MX6Q_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0 | ||
| 123 | #define MX6Q_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0 | ||
| 124 | #define MX6Q_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0 | ||
| 125 | #define MX6Q_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0 | ||
| 126 | #define MX6Q_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0 | ||
| 127 | #define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0 | ||
| 128 | #define MX6Q_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0 | ||
| 129 | #define MX6Q_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0 | ||
| 130 | #define MX6Q_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0 | ||
| 131 | #define MX6Q_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0 | ||
| 132 | #define MX6Q_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0 | ||
| 133 | #define MX6Q_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0 | ||
| 134 | #define MX6Q_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0 | ||
| 135 | #define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0 | ||
| 136 | #define MX6Q_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0 | ||
| 137 | #define MX6Q_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0 | ||
| 138 | #define MX6Q_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0 | ||
| 139 | #define MX6Q_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0 | ||
| 140 | #define MX6Q_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0 | ||
| 141 | #define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0 | ||
| 142 | #define MX6Q_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0 | ||
| 143 | #define MX6Q_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0 | ||
| 144 | #define MX6Q_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0 | ||
| 145 | #define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0 | ||
| 146 | #define MX6Q_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0 | ||
| 147 | #define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0 | ||
| 148 | #define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0 | ||
| 149 | #define MX6Q_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0 | ||
| 150 | #define MX6Q_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0 | ||
| 151 | #define MX6Q_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1 | ||
| 152 | #define MX6Q_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0 | ||
| 153 | #define MX6Q_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0 | ||
| 154 | #define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0 | ||
| 155 | #define MX6Q_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0 | ||
| 156 | #define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0 | ||
| 157 | #define MX6Q_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0 | ||
| 158 | #define MX6Q_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0 | ||
| 159 | #define MX6Q_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0 | ||
| 160 | #define MX6Q_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0 | ||
| 161 | #define MX6Q_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0 | ||
| 162 | #define MX6Q_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0 | ||
| 163 | #define MX6Q_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0 | ||
| 164 | #define MX6Q_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0 | ||
| 165 | #define MX6Q_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0 | ||
| 166 | #define MX6Q_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0 | ||
| 167 | #define MX6Q_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0 | ||
| 168 | #define MX6Q_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0 | ||
| 169 | #define MX6Q_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1 | ||
| 170 | #define MX6Q_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0 | ||
| 171 | #define MX6Q_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0 | ||
| 172 | #define MX6Q_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0 | ||
| 173 | #define MX6Q_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0 | ||
| 174 | #define MX6Q_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0 | ||
| 175 | #define MX6Q_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0 | ||
| 176 | #define MX6Q_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0 | ||
| 177 | #define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0 | ||
| 178 | #define MX6Q_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0 | ||
| 179 | #define MX6Q_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0 | ||
| 180 | #define MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0 | ||
| 181 | #define MX6Q_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0 | ||
| 182 | #define MX6Q_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0 | ||
| 183 | #define MX6Q_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0 | ||
| 184 | #define MX6Q_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0 | ||
| 185 | #define MX6Q_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0 | ||
| 186 | #define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0 | ||
| 187 | #define MX6Q_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0 | ||
| 188 | #define MX6Q_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0 | ||
| 189 | #define MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1 | ||
| 190 | #define MX6Q_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0 | ||
| 191 | #define MX6Q_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0 | ||
| 192 | #define MX6Q_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0 | ||
| 193 | #define MX6Q_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0 | ||
| 194 | #define MX6Q_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0 | ||
| 195 | #define MX6Q_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0 | ||
| 196 | #define MX6Q_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0 | ||
| 197 | #define MX6Q_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0 | ||
| 198 | #define MX6Q_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0 | ||
| 199 | #define MX6Q_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0 | ||
| 200 | #define MX6Q_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0 | ||
| 201 | #define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0 | ||
| 202 | #define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0 | ||
| 203 | #define MX6Q_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0 | ||
| 204 | #define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0 | ||
| 205 | #define MX6Q_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1 | ||
| 206 | #define MX6Q_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1 | ||
| 207 | #define MX6Q_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0 | ||
| 208 | #define MX6Q_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0 | ||
| 209 | #define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0 | ||
| 210 | #define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0 | ||
| 211 | #define MX6Q_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0 | ||
| 212 | #define MX6Q_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0 | ||
| 213 | #define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0 | ||
| 214 | #define MX6Q_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0 | ||
| 215 | #define MX6Q_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0 | ||
| 216 | #define MX6Q_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2 | ||
| 217 | #define MX6Q_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0 | ||
| 218 | #define MX6Q_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0 | ||
| 219 | #define MX6Q_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0 | ||
| 220 | #define MX6Q_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0 | ||
| 221 | #define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0 | ||
| 222 | #define MX6Q_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0 | ||
| 223 | #define MX6Q_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3 | ||
| 224 | #define MX6Q_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0 | ||
| 225 | #define MX6Q_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0 | ||
| 226 | #define MX6Q_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0 | ||
| 227 | #define MX6Q_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0 | ||
| 228 | #define MX6Q_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0 | ||
| 229 | #define MX6Q_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1 | ||
| 230 | #define MX6Q_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0 | ||
| 231 | #define MX6Q_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0 | ||
| 232 | #define MX6Q_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0 | ||
| 233 | #define MX6Q_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0 | ||
| 234 | #define MX6Q_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0 | ||
| 235 | #define MX6Q_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 | ||
| 236 | #define MX6Q_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1 | ||
| 237 | #define MX6Q_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0 | ||
| 238 | #define MX6Q_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0 | ||
| 239 | #define MX6Q_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0 | ||
| 240 | #define MX6Q_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0 | ||
| 241 | #define MX6Q_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0 | ||
| 242 | #define MX6Q_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0 | ||
| 243 | #define MX6Q_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1 | ||
| 244 | #define MX6Q_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0 | ||
| 245 | #define MX6Q_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0 | ||
| 246 | #define MX6Q_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0 | ||
| 247 | #define MX6Q_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0 | ||
| 248 | #define MX6Q_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1 | ||
| 249 | #define MX6Q_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0 | ||
| 250 | #define MX6Q_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0 | ||
| 251 | #define MX6Q_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0 | ||
| 252 | #define MX6Q_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0 | ||
| 253 | #define MX6Q_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1 | ||
| 254 | #define MX6Q_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0 | ||
| 255 | #define MX6Q_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0 | ||
| 256 | #define MX6Q_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0 | ||
| 257 | #define MX6Q_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0 | ||
| 258 | #define MX6Q_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1 | ||
| 259 | #define MX6Q_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0 | ||
| 260 | #define MX6Q_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0 | ||
| 261 | #define MX6Q_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0 | ||
| 262 | #define MX6Q_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0 | ||
| 263 | #define MX6Q_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1 | ||
| 264 | #define MX6Q_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0 | ||
| 265 | #define MX6Q_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0 | ||
| 266 | #define MX6Q_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0 | ||
| 267 | #define MX6Q_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0 | ||
| 268 | #define MX6Q_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1 | ||
| 269 | #define MX6Q_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0 | ||
| 270 | #define MX6Q_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0 | ||
| 271 | #define MX6Q_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0 | ||
| 272 | #define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0 | ||
| 273 | #define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1 | ||
| 274 | #define MX6Q_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0 | ||
| 275 | #define MX6Q_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0 | ||
| 276 | #define MX6Q_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0 | ||
| 277 | #define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0 | ||
| 278 | #define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0 | ||
| 279 | #define MX6Q_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0 | ||
| 280 | #define MX6Q_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0 | ||
| 281 | #define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0 | ||
| 282 | #define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0 | ||
| 283 | #define MX6Q_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0 | ||
| 284 | #define MX6Q_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0 | ||
| 285 | #define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0 | ||
| 286 | #define MX6Q_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0 | ||
| 287 | #define MX6Q_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0 | ||
| 288 | #define MX6Q_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0 | ||
| 289 | #define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0 | ||
| 290 | #define MX6Q_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0 | ||
| 291 | #define MX6Q_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0 | ||
| 292 | #define MX6Q_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0 | ||
| 293 | #define MX6Q_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0 | ||
| 294 | #define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0 | ||
| 295 | #define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0 | ||
| 296 | #define MX6Q_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0 | ||
| 297 | #define MX6Q_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0 | ||
| 298 | #define MX6Q_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0 | ||
| 299 | #define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0 | ||
| 300 | #define MX6Q_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1 | ||
| 301 | #define MX6Q_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0 | ||
| 302 | #define MX6Q_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0 | ||
| 303 | #define MX6Q_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0 | ||
| 304 | #define MX6Q_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0 | ||
| 305 | #define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0 | ||
| 306 | #define MX6Q_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1 | ||
| 307 | #define MX6Q_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0 | ||
| 308 | #define MX6Q_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0 | ||
| 309 | #define MX6Q_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0 | ||
| 310 | #define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0 | ||
| 311 | #define MX6Q_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0 | ||
| 312 | #define MX6Q_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0 | ||
| 313 | #define MX6Q_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0 | ||
| 314 | #define MX6Q_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0 | ||
| 315 | #define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0 | ||
| 316 | #define MX6Q_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0 | ||
| 317 | #define MX6Q_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0 | ||
| 318 | #define MX6Q_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0 | ||
| 319 | #define MX6Q_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0 | ||
| 320 | #define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0 | ||
| 321 | #define MX6Q_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0 | ||
| 322 | #define MX6Q_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0 | ||
| 323 | #define MX6Q_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0 | ||
| 324 | #define MX6Q_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0 | ||
| 325 | #define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0 | ||
| 326 | #define MX6Q_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0 | ||
| 327 | #define MX6Q_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0 | ||
| 328 | #define MX6Q_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0 | ||
| 329 | #define MX6Q_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0 | ||
| 330 | #define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0 | ||
| 331 | #define MX6Q_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0 | ||
| 332 | #define MX6Q_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0 | ||
| 333 | #define MX6Q_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0 | ||
| 334 | #define MX6Q_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0 | ||
| 335 | #define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0 | ||
| 336 | #define MX6Q_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0 | ||
| 337 | #define MX6Q_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0 | ||
| 338 | #define MX6Q_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0 | ||
| 339 | #define MX6Q_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0 | ||
| 340 | #define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0 | ||
| 341 | #define MX6Q_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0 | ||
| 342 | #define MX6Q_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0 | ||
| 343 | #define MX6Q_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0 | ||
| 344 | #define MX6Q_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0 | ||
| 345 | #define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0 | ||
| 346 | #define MX6Q_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0 | ||
| 347 | #define MX6Q_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0 | ||
| 348 | #define MX6Q_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0 | ||
| 349 | #define MX6Q_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0 | ||
| 350 | #define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0 | ||
| 351 | #define MX6Q_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0 | ||
| 352 | #define MX6Q_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0 | ||
| 353 | #define MX6Q_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0 | ||
| 354 | #define MX6Q_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0 | ||
| 355 | #define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0 | ||
| 356 | #define MX6Q_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0 | ||
| 357 | #define MX6Q_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0 | ||
| 358 | #define MX6Q_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0 | ||
| 359 | #define MX6Q_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0 | ||
| 360 | #define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0 | ||
| 361 | #define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1 | ||
| 362 | #define MX6Q_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0 | ||
| 363 | #define MX6Q_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0 | ||
| 364 | #define MX6Q_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0 | ||
| 365 | #define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0 | ||
| 366 | #define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1 | ||
| 367 | #define MX6Q_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0 | ||
| 368 | #define MX6Q_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0 | ||
| 369 | #define MX6Q_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0 | ||
| 370 | #define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0 | ||
| 371 | #define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1 | ||
| 372 | #define MX6Q_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0 | ||
| 373 | #define MX6Q_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0 | ||
| 374 | #define MX6Q_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0 | ||
| 375 | #define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0 | ||
| 376 | #define MX6Q_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0 | ||
| 377 | #define MX6Q_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0 | ||
| 378 | #define MX6Q_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0 | ||
| 379 | #define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0 | ||
| 380 | #define MX6Q_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0 | ||
| 381 | #define MX6Q_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0 | ||
| 382 | #define MX6Q_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0 | ||
| 383 | #define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0 | ||
| 384 | #define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0 | ||
| 385 | #define MX6Q_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0 | ||
| 386 | #define MX6Q_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0 | ||
| 387 | #define MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0 | ||
| 388 | #define MX6Q_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0 | ||
| 389 | #define MX6Q_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0 | ||
| 390 | #define MX6Q_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0 | ||
| 391 | #define MX6Q_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0 | ||
| 392 | #define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0 | ||
| 393 | #define MX6Q_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0 | ||
| 394 | #define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0 | ||
| 395 | #define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0 | ||
| 396 | #define MX6Q_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0 | ||
| 397 | #define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0 | ||
| 398 | #define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0 | ||
| 399 | #define MX6Q_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0 | ||
| 400 | #define MX6Q_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0 | ||
| 401 | #define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0 | ||
| 402 | #define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0 | ||
| 403 | #define MX6Q_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0 | ||
| 404 | #define MX6Q_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0 | ||
| 405 | #define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0 | ||
| 406 | #define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0 | ||
| 407 | #define MX6Q_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0 | ||
| 408 | #define MX6Q_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0 | ||
| 409 | #define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0 | ||
| 410 | #define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0 | ||
| 411 | #define MX6Q_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0 | ||
| 412 | #define MX6Q_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0 | ||
| 413 | #define MX6Q_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0 | ||
| 414 | #define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0 | ||
| 415 | #define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0 | ||
| 416 | #define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0 | ||
| 417 | #define MX6Q_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0 | ||
| 418 | #define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0 | ||
| 419 | #define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0 | ||
| 420 | #define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0 | ||
| 421 | #define MX6Q_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0 | ||
| 422 | #define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0 | ||
| 423 | #define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0 | ||
| 424 | #define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0 | ||
| 425 | #define MX6Q_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0 | ||
| 426 | #define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0 | ||
| 427 | #define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0 | ||
| 428 | #define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0 | ||
| 429 | #define MX6Q_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0 | ||
| 430 | #define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0 | ||
| 431 | #define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0 | ||
| 432 | #define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0 | ||
| 433 | #define MX6Q_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0 | ||
| 434 | #define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0 | ||
| 435 | #define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0 | ||
| 436 | #define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0 | ||
| 437 | #define MX6Q_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0 | ||
| 438 | #define MX6Q_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0 | ||
| 439 | #define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0 | ||
| 440 | #define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0 | ||
| 441 | #define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0 | ||
| 442 | #define MX6Q_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0 | ||
| 443 | #define MX6Q_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0 | ||
| 444 | #define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0 | ||
| 445 | #define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0 | ||
| 446 | #define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0 | ||
| 447 | #define MX6Q_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0 | ||
| 448 | #define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0 | ||
| 449 | #define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0 | ||
| 450 | #define MX6Q_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0 | ||
| 451 | #define MX6Q_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0 | ||
| 452 | #define MX6Q_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0 | ||
| 453 | #define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0 | ||
| 454 | #define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0 | ||
| 455 | #define MX6Q_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0 | ||
| 456 | #define MX6Q_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0 | ||
| 457 | #define MX6Q_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0 | ||
| 458 | #define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0 | ||
| 459 | #define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0 | ||
| 460 | #define MX6Q_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0 | ||
| 461 | #define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0 | ||
| 462 | #define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0 | ||
| 463 | #define MX6Q_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0 | ||
| 464 | #define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0 | ||
| 465 | #define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0 | ||
| 466 | #define MX6Q_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0 | ||
| 467 | #define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0 | ||
| 468 | #define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0 | ||
| 469 | #define MX6Q_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1 | ||
| 470 | #define MX6Q_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0 | ||
| 471 | #define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0 | ||
| 472 | #define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0 | ||
| 473 | #define MX6Q_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1 | ||
| 474 | #define MX6Q_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0 | ||
| 475 | #define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0 | ||
| 476 | #define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0 | ||
| 477 | #define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1 | ||
| 478 | #define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1 | ||
| 479 | #define MX6Q_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0 | ||
| 480 | #define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0 | ||
| 481 | #define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0 | ||
| 482 | #define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1 | ||
| 483 | #define MX6Q_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0 | ||
| 484 | #define MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0 | ||
| 485 | #define MX6Q_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0 | ||
| 486 | #define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0 | ||
| 487 | #define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0 | ||
| 488 | #define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1 | ||
| 489 | #define MX6Q_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0 | ||
| 490 | #define MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0 | ||
| 491 | #define MX6Q_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0 | ||
| 492 | #define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0 | ||
| 493 | #define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0 | ||
| 494 | #define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1 | ||
| 495 | #define MX6Q_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0 | ||
| 496 | #define MX6Q_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0 | ||
| 497 | #define MX6Q_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0 | ||
| 498 | #define MX6Q_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0 | ||
| 499 | #define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0 | ||
| 500 | #define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0 | ||
| 501 | #define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1 | ||
| 502 | #define MX6Q_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0 | ||
| 503 | #define MX6Q_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0 | ||
| 504 | #define MX6Q_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0 | ||
| 505 | #define MX6Q_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0 | ||
| 506 | #define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0 | ||
| 507 | #define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0 | ||
| 508 | #define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1 | ||
| 509 | #define MX6Q_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0 | ||
| 510 | #define MX6Q_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0 | ||
| 511 | #define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0 | ||
| 512 | #define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0 | ||
| 513 | #define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1 | ||
| 514 | #define MX6Q_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1 | ||
| 515 | #define MX6Q_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0 | ||
| 516 | #define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0 | ||
| 517 | #define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0 | ||
| 518 | #define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1 | ||
| 519 | #define MX6Q_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1 | ||
| 520 | #define MX6Q_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0 | ||
| 521 | #define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0 | ||
| 522 | #define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0 | ||
| 523 | #define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1 | ||
| 524 | #define MX6Q_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1 | ||
| 525 | #define MX6Q_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0 | ||
| 526 | #define MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0 | ||
| 527 | #define MX6Q_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0 | ||
| 528 | #define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0 | ||
| 529 | #define MX6Q_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0 | ||
| 530 | #define MX6Q_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0 | ||
| 531 | #define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0 | ||
| 532 | #define MX6Q_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 | ||
| 533 | #define MX6Q_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 | ||
| 534 | #define MX6Q_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 | ||
| 535 | #define MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0 | ||
| 536 | #define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 | ||
| 537 | #define MX6Q_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 | ||
| 538 | #define MX6Q_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 | ||
| 539 | #define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0 | ||
| 540 | #define MX6Q_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0 | ||
| 541 | #define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1 | ||
| 542 | #define MX6Q_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0 | ||
| 543 | #define MX6Q_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1 | ||
| 544 | #define MX6Q_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0 | ||
| 545 | #define MX6Q_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0 | ||
| 546 | #define MX6Q_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1 | ||
| 547 | #define MX6Q_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0 | ||
| 548 | #define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0 | ||
| 549 | #define MX6Q_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0 | ||
| 550 | #define MX6Q_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1 | ||
| 551 | #define MX6Q_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0 | ||
| 552 | #define MX6Q_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0 | ||
| 553 | #define MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0 | ||
| 554 | #define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0 | ||
| 555 | #define MX6Q_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0 | ||
| 556 | #define MX6Q_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0 | ||
| 557 | #define MX6Q_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0 | ||
| 558 | #define MX6Q_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0 | ||
| 559 | #define MX6Q_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0 | ||
| 560 | #define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0 | ||
| 561 | #define MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0 | ||
| 562 | #define MX6Q_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0 | ||
| 563 | #define MX6Q_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0 | ||
| 564 | #define MX6Q_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0 | ||
| 565 | #define MX6Q_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0 | ||
| 566 | #define MX6Q_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0 | ||
| 567 | #define MX6Q_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0 | ||
| 568 | #define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0 | ||
| 569 | #define MX6Q_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0 | ||
| 570 | #define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2 | ||
| 571 | #define MX6Q_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1 | ||
| 572 | #define MX6Q_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1 | ||
| 573 | #define MX6Q_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0 | ||
| 574 | #define MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0 | ||
| 575 | #define MX6Q_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0 | ||
| 576 | #define MX6Q_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0 | ||
| 577 | #define MX6Q_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0 | ||
| 578 | #define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2 | ||
| 579 | #define MX6Q_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0 | ||
| 580 | #define MX6Q_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1 | ||
| 581 | #define MX6Q_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0 | ||
| 582 | #define MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1 | ||
| 583 | #define MX6Q_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0 | ||
| 584 | #define MX6Q_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0 | ||
| 585 | #define MX6Q_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0 | ||
| 586 | #define MX6Q_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2 | ||
| 587 | #define MX6Q_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1 | ||
| 588 | #define MX6Q_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1 | ||
| 589 | #define MX6Q_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0 | ||
| 590 | #define MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0 | ||
| 591 | #define MX6Q_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0 | ||
| 592 | #define MX6Q_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0 | ||
| 593 | #define MX6Q_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0 | ||
| 594 | #define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2 | ||
| 595 | #define MX6Q_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0 | ||
| 596 | #define MX6Q_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1 | ||
| 597 | #define MX6Q_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0 | ||
| 598 | #define MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1 | ||
| 599 | #define MX6Q_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0 | ||
| 600 | #define MX6Q_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0 | ||
| 601 | #define MX6Q_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0 | ||
| 602 | #define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2 | ||
| 603 | #define MX6Q_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1 | ||
| 604 | #define MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0 | ||
| 605 | #define MX6Q_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0 | ||
| 606 | #define MX6Q_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0 | ||
| 607 | #define MX6Q_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0 | ||
| 608 | #define MX6Q_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0 | ||
| 609 | #define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1 | ||
| 610 | #define MX6Q_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0 | ||
| 611 | #define MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0 | ||
| 612 | #define MX6Q_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0 | ||
| 613 | #define MX6Q_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0 | ||
| 614 | #define MX6Q_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0 | ||
| 615 | #define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1 | ||
| 616 | #define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1 | ||
| 617 | #define MX6Q_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0 | ||
| 618 | #define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1 | ||
| 619 | #define MX6Q_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0 | ||
| 620 | #define MX6Q_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1 | ||
| 621 | #define MX6Q_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0 | ||
| 622 | #define MX6Q_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2 | ||
| 623 | #define MX6Q_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0 | ||
| 624 | #define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1 | ||
| 625 | #define MX6Q_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0 | ||
| 626 | #define MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1 | ||
| 627 | #define MX6Q_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0 | ||
| 628 | #define MX6Q_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0 | ||
| 629 | #define MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0 | ||
| 630 | #define MX6Q_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0 | ||
| 631 | #define MX6Q_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1 | ||
| 632 | #define MX6Q_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0 | ||
| 633 | #define MX6Q_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0 | ||
| 634 | #define MX6Q_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0 | ||
| 635 | #define MX6Q_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0 | ||
| 636 | #define MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0 | ||
| 637 | #define MX6Q_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0 | ||
| 638 | #define MX6Q_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0 | ||
| 639 | #define MX6Q_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0 | ||
| 640 | #define MX6Q_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0 | ||
| 641 | #define MX6Q_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1 | ||
| 642 | #define MX6Q_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0 | ||
| 643 | #define MX6Q_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0 | ||
| 644 | #define MX6Q_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0 | ||
| 645 | #define MX6Q_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1 | ||
| 646 | #define MX6Q_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0 | ||
| 647 | #define MX6Q_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0 | ||
| 648 | #define MX6Q_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0 | ||
| 649 | #define MX6Q_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0 | ||
| 650 | #define MX6Q_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 | ||
| 651 | #define MX6Q_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 | ||
| 652 | #define MX6Q_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 | ||
| 653 | #define MX6Q_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0 | ||
| 654 | #define MX6Q_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 | ||
| 655 | #define MX6Q_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 | ||
| 656 | #define MX6Q_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 | ||
| 657 | #define MX6Q_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1 | ||
| 658 | #define MX6Q_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0 | ||
| 659 | #define MX6Q_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0 | ||
| 660 | #define MX6Q_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0 | ||
| 661 | #define MX6Q_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0 | ||
| 662 | #define MX6Q_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0 | ||
| 663 | #define MX6Q_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1 | ||
| 664 | #define MX6Q_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1 | ||
| 665 | #define MX6Q_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1 | ||
| 666 | #define MX6Q_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0 | ||
| 667 | #define MX6Q_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0 | ||
| 668 | #define MX6Q_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0 | ||
| 669 | #define MX6Q_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 | ||
| 670 | #define MX6Q_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 | ||
| 671 | #define MX6Q_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 | ||
| 672 | #define MX6Q_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 | ||
| 673 | #define MX6Q_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 | ||
| 674 | #define MX6Q_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 | ||
| 675 | #define MX6Q_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1 | ||
| 676 | #define MX6Q_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1 | ||
| 677 | #define MX6Q_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1 | ||
| 678 | #define MX6Q_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0 | ||
| 679 | #define MX6Q_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0 | ||
| 680 | #define MX6Q_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1 | ||
| 681 | #define MX6Q_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1 | ||
| 682 | #define MX6Q_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1 | ||
| 683 | #define MX6Q_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0 | ||
| 684 | #define MX6Q_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0 | ||
| 685 | #define MX6Q_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1 | ||
| 686 | #define MX6Q_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1 | ||
| 687 | #define MX6Q_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0 | ||
| 688 | #define MX6Q_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0 | ||
| 689 | #define MX6Q_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2 | ||
| 690 | #define MX6Q_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0 | ||
| 691 | #define MX6Q_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1 | ||
| 692 | #define MX6Q_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0 | ||
| 693 | #define MX6Q_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0 | ||
| 694 | #define MX6Q_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0 | ||
| 695 | #define MX6Q_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0 | ||
| 696 | #define MX6Q_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2 | ||
| 697 | #define MX6Q_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0 | ||
| 698 | #define MX6Q_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0 | ||
| 699 | #define MX6Q_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0 | ||
| 700 | #define MX6Q_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1 | ||
| 701 | #define MX6Q_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0 | ||
| 702 | #define MX6Q_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0 | ||
| 703 | #define MX6Q_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1 | ||
| 704 | #define MX6Q_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3 | ||
| 705 | #define MX6Q_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0 | ||
| 706 | #define MX6Q_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0 | ||
| 707 | #define MX6Q_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0 | ||
| 708 | #define MX6Q_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0 | ||
| 709 | #define MX6Q_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1 | ||
| 710 | #define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0 | ||
| 711 | #define MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1 | ||
| 712 | #define MX6Q_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0 | ||
| 713 | #define MX6Q_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3 | ||
| 714 | #define MX6Q_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0 | ||
| 715 | #define MX6Q_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2 | ||
| 716 | #define MX6Q_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0 | ||
| 717 | #define MX6Q_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0 | ||
| 718 | #define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0 | ||
| 719 | #define MX6Q_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1 | ||
| 720 | #define MX6Q_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1 | ||
| 721 | #define MX6Q_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0 | ||
| 722 | #define MX6Q_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0 | ||
| 723 | #define MX6Q_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0 | ||
| 724 | #define MX6Q_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1 | ||
| 725 | #define MX6Q_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0 | ||
| 726 | #define MX6Q_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1 | ||
| 727 | #define MX6Q_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2 | ||
| 728 | #define MX6Q_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0 | ||
| 729 | #define MX6Q_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0 | ||
| 730 | #define MX6Q_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1 | ||
| 731 | #define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0 | ||
| 732 | #define MX6Q_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0 | ||
| 733 | #define MX6Q_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0 | ||
| 734 | #define MX6Q_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0 | ||
| 735 | #define MX6Q_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0 | ||
| 736 | #define MX6Q_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0 | ||
| 737 | #define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0 | ||
| 738 | #define MX6Q_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0 | ||
| 739 | #define MX6Q_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0 | ||
| 740 | #define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0 | ||
| 741 | #define MX6Q_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0 | ||
| 742 | #define MX6Q_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0 | ||
| 743 | #define MX6Q_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0 | ||
| 744 | #define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0 | ||
| 745 | #define MX6Q_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0 | ||
| 746 | #define MX6Q_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0 | ||
| 747 | #define MX6Q_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0 | ||
| 748 | #define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0 | ||
| 749 | #define MX6Q_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0 | ||
| 750 | #define MX6Q_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0 | ||
| 751 | #define MX6Q_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0 | ||
| 752 | #define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0 | ||
| 753 | #define MX6Q_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0 | ||
| 754 | #define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3 | ||
| 755 | #define MX6Q_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2 | ||
| 756 | #define MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0 | ||
| 757 | #define MX6Q_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0 | ||
| 758 | #define MX6Q_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0 | ||
| 759 | #define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0 | ||
| 760 | #define MX6Q_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0 | ||
| 761 | #define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3 | ||
| 762 | #define MX6Q_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1 | ||
| 763 | #define MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0 | ||
| 764 | #define MX6Q_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0 | ||
| 765 | #define MX6Q_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0 | ||
| 766 | #define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0 | ||
| 767 | #define MX6Q_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0 | ||
| 768 | #define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3 | ||
| 769 | #define MX6Q_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1 | ||
| 770 | #define MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0 | ||
| 771 | #define MX6Q_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0 | ||
| 772 | #define MX6Q_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0 | ||
| 773 | #define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0 | ||
| 774 | #define MX6Q_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0 | ||
| 775 | #define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3 | ||
| 776 | #define MX6Q_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2 | ||
| 777 | #define MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0 | ||
| 778 | #define MX6Q_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0 | ||
| 779 | #define MX6Q_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0 | ||
| 780 | #define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0 | ||
| 781 | #define MX6Q_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0 | ||
| 782 | #define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2 | ||
| 783 | #define MX6Q_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2 | ||
| 784 | #define MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1 | ||
| 785 | #define MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0 | ||
| 786 | #define MX6Q_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0 | ||
| 787 | #define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0 | ||
| 788 | #define MX6Q_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0 | ||
| 789 | #define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2 | ||
| 790 | #define MX6Q_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2 | ||
| 791 | #define MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1 | ||
| 792 | #define MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0 | ||
| 793 | #define MX6Q_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0 | ||
| 794 | #define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0 | ||
| 795 | #define MX6Q_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0 | ||
| 796 | #define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2 | ||
| 797 | #define MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0 | ||
| 798 | #define MX6Q_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0 | ||
| 799 | #define MX6Q_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0 | ||
| 800 | #define MX6Q_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0 | ||
| 801 | #define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0 | ||
| 802 | #define MX6Q_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0 | ||
| 803 | #define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2 | ||
| 804 | #define MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1 | ||
| 805 | #define MX6Q_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0 | ||
| 806 | #define MX6Q_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0 | ||
| 807 | #define MX6Q_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0 | ||
| 808 | #define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0 | ||
| 809 | #define MX6Q_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0 | ||
| 810 | #define MX6Q_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0 | ||
| 811 | #define MX6Q_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2 | ||
| 812 | #define MX6Q_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0 | ||
| 813 | #define MX6Q_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0 | ||
| 814 | #define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0 | ||
| 815 | #define MX6Q_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0 | ||
| 816 | #define MX6Q_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3 | ||
| 817 | #define MX6Q_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0 | ||
| 818 | #define MX6Q_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0 | ||
| 819 | #define MX6Q_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0 | ||
| 820 | #define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0 | ||
| 821 | #define MX6Q_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0 | ||
| 822 | #define MX6Q_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0 | ||
| 823 | #define MX6Q_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2 | ||
| 824 | #define MX6Q_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0 | ||
| 825 | #define MX6Q_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0 | ||
| 826 | #define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0 | ||
| 827 | #define MX6Q_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0 | ||
| 828 | #define MX6Q_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3 | ||
| 829 | #define MX6Q_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0 | ||
| 830 | #define MX6Q_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0 | ||
| 831 | #define MX6Q_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0 | ||
| 832 | #define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0 | ||
| 833 | #define MX6Q_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0 | ||
| 834 | #define MX6Q_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0 | ||
| 835 | #define MX6Q_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0 | ||
| 836 | #define MX6Q_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0 | ||
| 837 | #define MX6Q_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0 | ||
| 838 | #define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0 | ||
| 839 | #define MX6Q_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0 | ||
| 840 | #define MX6Q_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0 | ||
| 841 | #define MX6Q_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1 | ||
| 842 | #define MX6Q_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0 | ||
| 843 | #define MX6Q_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0 | ||
| 844 | #define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0 | ||
| 845 | #define MX6Q_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0 | ||
| 846 | #define MX6Q_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2 | ||
| 847 | #define MX6Q_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0 | ||
| 848 | #define MX6Q_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0 | ||
| 849 | #define MX6Q_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0 | ||
| 850 | #define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0 | ||
| 851 | #define MX6Q_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0 | ||
| 852 | #define MX6Q_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0 | ||
| 853 | #define MX6Q_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3 | ||
| 854 | #define MX6Q_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0 | ||
| 855 | #define MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0 | ||
| 856 | #define MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0 | ||
| 857 | #define MX6Q_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2 | ||
| 858 | #define MX6Q_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0 | ||
| 859 | #define MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0 | ||
| 860 | #define MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3 | ||
| 861 | #define MX6Q_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0 | ||
| 862 | #define MX6Q_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0 | ||
| 863 | #define MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0 | ||
| 864 | #define MX6Q_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0 | ||
| 865 | #define MX6Q_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4 | ||
| 866 | #define MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0 | ||
| 867 | #define MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0 | ||
| 868 | #define MX6Q_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5 | ||
| 869 | #define MX6Q_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0 | ||
| 870 | #define MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0 | ||
| 871 | #define MX6Q_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0 | ||
| 872 | #define MX6Q_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0 | ||
| 873 | #define MX6Q_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2 | ||
| 874 | #define MX6Q_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0 | ||
| 875 | #define MX6Q_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0 | ||
| 876 | #define MX6Q_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0 | ||
| 877 | #define MX6Q_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3 | ||
| 878 | #define MX6Q_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0 | ||
| 879 | #define MX6Q_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2 | ||
| 880 | #define MX6Q_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0 | ||
| 881 | #define MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0 | ||
| 882 | #define MX6Q_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0 | ||
| 883 | #define MX6Q_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2 | ||
| 884 | #define MX6Q_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0 | ||
| 885 | #define MX6Q_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0 | ||
| 886 | #define MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0 | ||
| 887 | #define MX6Q_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3 | ||
| 888 | #define MX6Q_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0 | ||
| 889 | #define MX6Q_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1 | ||
| 890 | #define MX6Q_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0 | ||
| 891 | #define MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0 | ||
| 892 | #define MX6Q_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0 | ||
| 893 | #define MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0 | ||
| 894 | #define MX6Q_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0 | ||
| 895 | #define MX6Q_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4 | ||
| 896 | #define MX6Q_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0 | ||
| 897 | #define MX6Q_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0 | ||
| 898 | #define MX6Q_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5 | ||
| 899 | #define MX6Q_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0 | ||
| 900 | #define MX6Q_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0 | ||
| 901 | #define MX6Q_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0 | ||
| 902 | #define MX6Q_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0 | ||
| 903 | #define MX6Q_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0 | ||
| 904 | #define MX6Q_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0 | ||
| 905 | #define MX6Q_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0 | ||
| 906 | #define MX6Q_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0 | ||
| 907 | #define MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0 | ||
| 908 | #define MX6Q_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0 | ||
| 909 | #define MX6Q_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0 | ||
| 910 | #define MX6Q_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0 | ||
| 911 | #define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0 | ||
| 912 | #define MX6Q_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0 | ||
| 913 | #define MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0 | ||
| 914 | #define MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0 | ||
| 915 | #define MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0 | ||
| 916 | #define MX6Q_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0 | ||
| 917 | #define MX6Q_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0 | ||
| 918 | #define MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0 | ||
| 919 | #define MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0 | ||
| 920 | #define MX6Q_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0 | ||
| 921 | #define MX6Q_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1 | ||
| 922 | #define MX6Q_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0 | ||
| 923 | #define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0 | ||
| 924 | #define MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0 | ||
| 925 | #define MX6Q_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0 | ||
| 926 | #define MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0 | ||
| 927 | #define MX6Q_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0 | ||
| 928 | #define MX6Q_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1 | ||
| 929 | #define MX6Q_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0 | ||
| 930 | #define MX6Q_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0 | ||
| 931 | #define MX6Q_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0 | ||
| 932 | #define MX6Q_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0 | ||
| 933 | #define MX6Q_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0 | ||
| 934 | #define MX6Q_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0 | ||
| 935 | #define MX6Q_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2 | ||
| 936 | #define MX6Q_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0 | ||
| 937 | #define MX6Q_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0 | ||
| 938 | #define MX6Q_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0 | ||
| 939 | #define MX6Q_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3 | ||
| 940 | #define MX6Q_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0 | ||
| 941 | #define MX6Q_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0 | ||
| 942 | #define MX6Q_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0 | ||
| 943 | #define MX6Q_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0 | ||
| 944 | #define MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0 | ||
| 945 | #define MX6Q_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0 | ||
| 946 | #define MX6Q_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0 | ||
| 947 | #define MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0 | ||
| 948 | #define MX6Q_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0 | ||
| 949 | #define MX6Q_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0 | ||
| 950 | #define MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0 | ||
| 951 | #define MX6Q_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0 | ||
| 952 | #define MX6Q_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0 | ||
| 953 | #define MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0 | ||
| 954 | #define MX6Q_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0 | ||
| 955 | #define MX6Q_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0 | ||
| 956 | #define MX6Q_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0 | ||
| 957 | #define MX6Q_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0 | ||
| 958 | #define MX6Q_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0 | ||
| 959 | #define MX6Q_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0 | ||
| 960 | #define MX6Q_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0 | ||
| 961 | #define MX6Q_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0 | ||
| 962 | #define MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0 | ||
| 963 | #define MX6Q_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0 | ||
| 964 | #define MX6Q_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0 | ||
| 965 | #define MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0 | ||
| 966 | #define MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0 | ||
| 967 | #define MX6Q_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0 | ||
| 968 | #define MX6Q_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0 | ||
| 969 | #define MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0 | ||
| 970 | #define MX6Q_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0 | ||
| 971 | #define MX6Q_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0 | ||
| 972 | #define MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0 | ||
| 973 | #define MX6Q_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0 | ||
| 974 | #define MX6Q_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0 | ||
| 975 | #define MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0 | ||
| 976 | #define MX6Q_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0 | ||
| 977 | #define MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0 | ||
| 978 | #define MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6 | ||
| 979 | #define MX6Q_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0 | ||
| 980 | #define MX6Q_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0 | ||
| 981 | #define MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0 | ||
| 982 | #define MX6Q_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4 | ||
| 983 | #define MX6Q_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0 | ||
| 984 | #define MX6Q_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0 | ||
| 985 | #define MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0 | ||
| 986 | #define MX6Q_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0 | ||
| 987 | #define MX6Q_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5 | ||
| 988 | #define MX6Q_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0 | ||
| 989 | #define MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0 | ||
| 990 | #define MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0 | ||
| 991 | #define MX6Q_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7 | ||
| 992 | #define MX6Q_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0 | ||
| 993 | #define MX6Q_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0 | ||
| 994 | #define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1 | ||
| 995 | #define MX6Q_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0 | ||
| 996 | #define MX6Q_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0 | ||
| 997 | #define MX6Q_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0 | ||
| 998 | #define MX6Q_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0 | ||
| 999 | #define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1 | ||
| 1000 | #define MX6Q_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0 | ||
| 1001 | #define MX6Q_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0 | ||
| 1002 | #define MX6Q_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0 | ||
| 1003 | #define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0 | ||
| 1004 | #define MX6Q_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0 | ||
| 1005 | #define MX6Q_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0 | ||
| 1006 | #define MX6Q_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0 | ||
| 1007 | #define MX6Q_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0 | ||
| 1008 | #define MX6Q_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0 | ||
| 1009 | #define MX6Q_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0 | ||
| 1010 | #define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0 | ||
| 1011 | #define MX6Q_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 | ||
| 1012 | #define MX6Q_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0 | ||
| 1013 | #define MX6Q_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0 | ||
| 1014 | #define MX6Q_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0 | ||
| 1015 | #define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1 | ||
| 1016 | #define MX6Q_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0 | ||
| 1017 | #define MX6Q_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0 | ||
| 1018 | #define MX6Q_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0 | ||
| 1019 | #define MX6Q_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0 | ||
| 1020 | #define MX6Q_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 | ||
| 1021 | #define MX6Q_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 | ||
| 1022 | #define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 | ||
| 1023 | #define MX6Q_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 | ||
| 1024 | #define MX6Q_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 | ||
| 1025 | #define MX6Q_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 | ||
| 1026 | #define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1 | ||
| 1027 | #define MX6Q_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3 | ||
| 1028 | #define MX6Q_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1 | ||
| 1029 | #define MX6Q_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0 | ||
| 1030 | #define MX6Q_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0 | ||
| 1031 | #define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1 | ||
| 1032 | #define MX6Q_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2 | ||
| 1033 | #define MX6Q_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1 | ||
| 1034 | #define MX6Q_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0 | ||
| 1035 | #define MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0 | ||
| 1036 | #define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0 | ||
| 1037 | #define MX6Q_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2 | ||
| 1038 | #define MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1 | ||
| 1039 | #define MX6Q_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0 | ||
| 1040 | |||
| 1041 | #endif /* __DTS_IMX6Q_PINFUNC_H */ | ||
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts index 656d489122fe..49d6f2831ec9 100644 --- a/arch/arm/boot/dts/imx6q-sabreauto.dts +++ b/arch/arm/boot/dts/imx6q-sabreauto.dts | |||
| @@ -11,15 +11,13 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /dts-v1/; | 13 | /dts-v1/; |
| 14 | /include/ "imx6q.dtsi" | 14 | |
| 15 | #include "imx6q.dtsi" | ||
| 16 | #include "imx6qdl-sabreauto.dtsi" | ||
| 15 | 17 | ||
| 16 | / { | 18 | / { |
| 17 | model = "Freescale i.MX6 Quad SABRE Automotive Board"; | 19 | model = "Freescale i.MX6 Quad SABRE Automotive Board"; |
| 18 | compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; | 20 | compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; |
| 19 | |||
| 20 | memory { | ||
| 21 | reg = <0x10000000 0x80000000>; | ||
| 22 | }; | ||
| 23 | }; | 21 | }; |
| 24 | 22 | ||
| 25 | &iomuxc { | 23 | &iomuxc { |
| @@ -29,30 +27,9 @@ | |||
| 29 | hog { | 27 | hog { |
| 30 | pinctrl_hog: hoggrp { | 28 | pinctrl_hog: hoggrp { |
| 31 | fsl,pins = < | 29 | fsl,pins = < |
| 32 | 1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */ | 30 | MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 |
| 33 | 13 0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */ | 31 | MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 |
| 34 | >; | 32 | >; |
| 35 | }; | 33 | }; |
| 36 | }; | 34 | }; |
| 37 | }; | 35 | }; |
| 38 | |||
| 39 | &uart4 { | ||
| 40 | pinctrl-names = "default"; | ||
| 41 | pinctrl-0 = <&pinctrl_uart4_1>; | ||
| 42 | status = "okay"; | ||
| 43 | }; | ||
| 44 | |||
| 45 | &fec { | ||
| 46 | pinctrl-names = "default"; | ||
| 47 | pinctrl-0 = <&pinctrl_enet_2>; | ||
| 48 | phy-mode = "rgmii"; | ||
| 49 | status = "okay"; | ||
| 50 | }; | ||
| 51 | |||
| 52 | &usdhc3 { | ||
| 53 | pinctrl-names = "default"; | ||
| 54 | pinctrl-0 = <&pinctrl_usdhc3_1>; | ||
| 55 | cd-gpios = <&gpio6 15 0>; | ||
| 56 | wp-gpios = <&gpio1 13 0>; | ||
| 57 | status = "okay"; | ||
| 58 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 2ce355cd05e5..6a000666c147 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts | |||
| @@ -11,7 +11,7 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /dts-v1/; | 13 | /dts-v1/; |
| 14 | /include/ "imx6q.dtsi" | 14 | #include "imx6q.dtsi" |
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | model = "Freescale i.MX6 Quad SABRE Lite Board"; | 17 | model = "Freescale i.MX6 Quad SABRE Lite Board"; |
| @@ -91,14 +91,14 @@ | |||
| 91 | hog { | 91 | hog { |
| 92 | pinctrl_hog: hoggrp { | 92 | pinctrl_hog: hoggrp { |
| 93 | fsl,pins = < | 93 | fsl,pins = < |
| 94 | 1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */ | 94 | MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000 |
| 95 | 1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */ | 95 | MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000 |
| 96 | 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ | 96 | MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 |
| 97 | 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ | 97 | MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000 |
| 98 | 152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */ | 98 | MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000 |
| 99 | 1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */ | 99 | MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 |
| 100 | 1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */ | 100 | MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 |
| 101 | 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */ | 101 | MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000 |
| 102 | >; | 102 | >; |
| 103 | }; | 103 | }; |
| 104 | }; | 104 | }; |
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts index 2dea304a7980..442051350225 100644 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/arch/arm/boot/dts/imx6q-sabresd.dts | |||
| @@ -11,37 +11,13 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /dts-v1/; | 13 | /dts-v1/; |
| 14 | /include/ "imx6q.dtsi" | 14 | |
| 15 | #include "imx6q.dtsi" | ||
| 16 | #include "imx6qdl-sabresd.dtsi" | ||
| 15 | 17 | ||
| 16 | / { | 18 | / { |
| 17 | model = "Freescale i.MX6Q SABRE Smart Device Board"; | 19 | model = "Freescale i.MX6 Quad SABRE Smart Device Board"; |
| 18 | compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; | 20 | compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; |
| 19 | |||
| 20 | memory { | ||
| 21 | reg = <0x10000000 0x40000000>; | ||
| 22 | }; | ||
| 23 | |||
| 24 | gpio-keys { | ||
| 25 | compatible = "gpio-keys"; | ||
| 26 | |||
| 27 | volume-up { | ||
| 28 | label = "Volume Up"; | ||
| 29 | gpios = <&gpio1 4 0>; | ||
| 30 | linux,code = <115>; /* KEY_VOLUMEUP */ | ||
| 31 | }; | ||
| 32 | |||
| 33 | volume-down { | ||
| 34 | label = "Volume Down"; | ||
| 35 | gpios = <&gpio1 5 0>; | ||
| 36 | linux,code = <114>; /* KEY_VOLUMEDOWN */ | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | &uart1 { | ||
| 42 | pinctrl-names = "default"; | ||
| 43 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 44 | status = "okay"; | ||
| 45 | }; | 21 | }; |
| 46 | 22 | ||
| 47 | &iomuxc { | 23 | &iomuxc { |
| @@ -51,36 +27,13 @@ | |||
| 51 | hog { | 27 | hog { |
| 52 | pinctrl_hog: hoggrp { | 28 | pinctrl_hog: hoggrp { |
| 53 | fsl,pins = < | 29 | fsl,pins = < |
| 54 | 1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */ | 30 | MX6Q_PAD_GPIO_4__GPIO1_IO04 0x80000000 |
| 55 | 1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */ | 31 | MX6Q_PAD_GPIO_5__GPIO1_IO05 0x80000000 |
| 56 | 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */ | 32 | MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x80000000 |
| 57 | 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */ | 33 | MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000 |
| 58 | 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */ | 34 | MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000 |
| 59 | 1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */ | 35 | MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000 |
| 60 | >; | 36 | >; |
| 61 | }; | 37 | }; |
| 62 | }; | 38 | }; |
| 63 | }; | 39 | }; |
| 64 | |||
| 65 | &fec { | ||
| 66 | pinctrl-names = "default"; | ||
| 67 | pinctrl-0 = <&pinctrl_enet_1>; | ||
| 68 | phy-mode = "rgmii"; | ||
| 69 | status = "okay"; | ||
| 70 | }; | ||
| 71 | |||
| 72 | &usdhc2 { | ||
| 73 | pinctrl-names = "default"; | ||
| 74 | pinctrl-0 = <&pinctrl_usdhc2_1>; | ||
| 75 | cd-gpios = <&gpio2 2 0>; | ||
| 76 | wp-gpios = <&gpio2 3 0>; | ||
| 77 | status = "okay"; | ||
| 78 | }; | ||
| 79 | |||
| 80 | &usdhc3 { | ||
| 81 | pinctrl-names = "default"; | ||
| 82 | pinctrl-0 = <&pinctrl_usdhc3_1>; | ||
| 83 | cd-gpios = <&gpio2 0 0>; | ||
| 84 | wp-gpios = <&gpio2 1 0>; | ||
| 85 | status = "okay"; | ||
| 86 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/imx6q-sbc6x.dts new file mode 100644 index 000000000000..ee6addf149af --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sbc6x.dts | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Pavel Machek <pavel@denx.de> | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License V2. | ||
| 6 | */ | ||
| 7 | |||
| 8 | /dts-v1/; | ||
| 9 | #include "imx6q.dtsi" | ||
| 10 | |||
| 11 | / { | ||
| 12 | model = "MicroSys sbc6x board"; | ||
| 13 | compatible = "microsys,sbc6x", "fsl,imx6q"; | ||
| 14 | |||
| 15 | memory { | ||
| 16 | reg = <0x10000000 0x80000000>; | ||
| 17 | }; | ||
| 18 | }; | ||
| 19 | |||
| 20 | &fec { | ||
| 21 | pinctrl-names = "default"; | ||
| 22 | pinctrl-0 = <&pinctrl_enet_1>; | ||
| 23 | phy-mode = "rgmii"; | ||
| 24 | status = "okay"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | &uart1 { | ||
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | &usbotg { | ||
| 34 | pinctrl-names = "default"; | ||
| 35 | pinctrl-0 = <&pinctrl_usbotg_1>; | ||
| 36 | disable-over-current; | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | |||
| 40 | &usdhc3 { | ||
| 41 | pinctrl-names = "default"; | ||
| 42 | pinctrl-0 = <&pinctrl_usdhc3_2>; | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index cba021eb035e..21e675848bd1 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi | |||
| @@ -8,7 +8,8 @@ | |||
| 8 | * | 8 | * |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | /include/ "imx6qdl.dtsi" | 11 | #include "imx6qdl.dtsi" |
| 12 | #include "imx6q-pinfunc.h" | ||
| 12 | 13 | ||
| 13 | / { | 14 | / { |
| 14 | cpus { | 15 | cpus { |
| @@ -78,10 +79,19 @@ | |||
| 78 | audmux { | 79 | audmux { |
| 79 | pinctrl_audmux_1: audmux-1 { | 80 | pinctrl_audmux_1: audmux-1 { |
| 80 | fsl,pins = < | 81 | fsl,pins = < |
| 81 | 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ | 82 | MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000 |
| 82 | 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ | 83 | MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000 |
| 83 | 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ | 84 | MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000 |
| 84 | 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ | 85 | MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000 |
| 86 | >; | ||
| 87 | }; | ||
| 88 | |||
| 89 | pinctrl_audmux_2: audmux-2 { | ||
| 90 | fsl,pins = < | ||
| 91 | MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 | ||
| 92 | MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 | ||
| 93 | MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 | ||
| 94 | MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 | ||
| 85 | >; | 95 | >; |
| 86 | }; | 96 | }; |
| 87 | }; | 97 | }; |
| @@ -89,9 +99,19 @@ | |||
| 89 | ecspi1 { | 99 | ecspi1 { |
| 90 | pinctrl_ecspi1_1: ecspi1grp-1 { | 100 | pinctrl_ecspi1_1: ecspi1grp-1 { |
| 91 | fsl,pins = < | 101 | fsl,pins = < |
| 92 | 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ | 102 | MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1 |
| 93 | 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ | 103 | MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 |
| 94 | 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ | 104 | MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 |
| 105 | >; | ||
| 106 | }; | ||
| 107 | }; | ||
| 108 | |||
| 109 | ecspi3 { | ||
| 110 | pinctrl_ecspi3_1: ecspi3grp-1 { | ||
| 111 | fsl,pins = < | ||
| 112 | MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 | ||
| 113 | MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 | ||
| 114 | MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 | ||
| 95 | >; | 115 | >; |
| 96 | }; | 116 | }; |
| 97 | }; | 117 | }; |
| @@ -99,42 +119,42 @@ | |||
| 99 | enet { | 119 | enet { |
| 100 | pinctrl_enet_1: enetgrp-1 { | 120 | pinctrl_enet_1: enetgrp-1 { |
| 101 | fsl,pins = < | 121 | fsl,pins = < |
| 102 | 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */ | 122 | MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 |
| 103 | 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */ | 123 | MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0 |
| 104 | 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ | 124 | MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 |
| 105 | 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ | 125 | MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 |
| 106 | 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ | 126 | MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 |
| 107 | 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ | 127 | MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 |
| 108 | 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ | 128 | MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 |
| 109 | 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ | 129 | MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 |
| 110 | 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ | 130 | MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 |
| 111 | 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ | 131 | MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 |
| 112 | 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ | 132 | MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 |
| 113 | 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ | 133 | MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 |
| 114 | 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ | 134 | MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 |
| 115 | 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ | 135 | MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 |
| 116 | 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ | 136 | MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 |
| 117 | 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/ | 137 | MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 |
| 118 | >; | 138 | >; |
| 119 | }; | 139 | }; |
| 120 | 140 | ||
| 121 | pinctrl_enet_2: enetgrp-2 { | 141 | pinctrl_enet_2: enetgrp-2 { |
| 122 | fsl,pins = < | 142 | fsl,pins = < |
| 123 | 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */ | 143 | MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 |
| 124 | 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */ | 144 | MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0 |
| 125 | 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ | 145 | MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 |
| 126 | 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ | 146 | MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 |
| 127 | 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ | 147 | MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 |
| 128 | 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ | 148 | MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 |
| 129 | 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ | 149 | MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 |
| 130 | 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ | 150 | MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 |
| 131 | 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ | 151 | MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 |
| 132 | 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ | 152 | MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 |
| 133 | 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ | 153 | MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 |
| 134 | 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ | 154 | MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 |
| 135 | 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ | 155 | MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 |
| 136 | 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ | 156 | MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 |
| 137 | 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ | 157 | MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 |
| 138 | >; | 158 | >; |
| 139 | }; | 159 | }; |
| 140 | }; | 160 | }; |
| @@ -142,25 +162,25 @@ | |||
| 142 | gpmi-nand { | 162 | gpmi-nand { |
| 143 | pinctrl_gpmi_nand_1: gpmi-nand-1 { | 163 | pinctrl_gpmi_nand_1: gpmi-nand-1 { |
| 144 | fsl,pins = < | 164 | fsl,pins = < |
| 145 | 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ | 165 | MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1 |
| 146 | 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ | 166 | MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1 |
| 147 | 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ | 167 | MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 |
| 148 | 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ | 168 | MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000 |
| 149 | 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ | 169 | MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 |
| 150 | 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ | 170 | MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 |
| 151 | 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ | 171 | MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 |
| 152 | 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ | 172 | MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 |
| 153 | 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ | 173 | MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1 |
| 154 | 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ | 174 | MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1 |
| 155 | 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ | 175 | MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1 |
| 156 | 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ | 176 | MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1 |
| 157 | 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ | 177 | MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1 |
| 158 | 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ | 178 | MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1 |
| 159 | 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ | 179 | MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1 |
| 160 | 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ | 180 | MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1 |
| 161 | 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ | 181 | MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1 |
| 162 | 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ | 182 | MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1 |
| 163 | 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ | 183 | MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1 |
| 164 | >; | 184 | >; |
| 165 | }; | 185 | }; |
| 166 | }; | 186 | }; |
| @@ -168,8 +188,26 @@ | |||
| 168 | i2c1 { | 188 | i2c1 { |
| 169 | pinctrl_i2c1_1: i2c1grp-1 { | 189 | pinctrl_i2c1_1: i2c1grp-1 { |
| 170 | fsl,pins = < | 190 | fsl,pins = < |
| 171 | 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ | 191 | MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 |
| 172 | 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */ | 192 | MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 |
| 193 | >; | ||
| 194 | }; | ||
| 195 | }; | ||
| 196 | |||
| 197 | i2c2 { | ||
| 198 | pinctrl_i2c2_1: i2c2grp-1 { | ||
| 199 | fsl,pins = < | ||
| 200 | MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | ||
| 201 | MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 | ||
| 202 | >; | ||
| 203 | }; | ||
| 204 | }; | ||
| 205 | |||
| 206 | i2c3 { | ||
| 207 | pinctrl_i2c3_1: i2c3grp-1 { | ||
| 208 | fsl,pins = < | ||
| 209 | MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 | ||
| 210 | MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | ||
| 173 | >; | 211 | >; |
| 174 | }; | 212 | }; |
| 175 | }; | 213 | }; |
| @@ -177,8 +215,8 @@ | |||
| 177 | uart1 { | 215 | uart1 { |
| 178 | pinctrl_uart1_1: uart1grp-1 { | 216 | pinctrl_uart1_1: uart1grp-1 { |
| 179 | fsl,pins = < | 217 | fsl,pins = < |
| 180 | 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ | 218 | MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 |
| 181 | 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ | 219 | MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 |
| 182 | >; | 220 | >; |
| 183 | }; | 221 | }; |
| 184 | }; | 222 | }; |
| @@ -186,8 +224,8 @@ | |||
| 186 | uart2 { | 224 | uart2 { |
| 187 | pinctrl_uart2_1: uart2grp-1 { | 225 | pinctrl_uart2_1: uart2grp-1 { |
| 188 | fsl,pins = < | 226 | fsl,pins = < |
| 189 | 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ | 227 | MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 |
| 190 | 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */ | 228 | MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 |
| 191 | >; | 229 | >; |
| 192 | }; | 230 | }; |
| 193 | }; | 231 | }; |
| @@ -195,8 +233,8 @@ | |||
| 195 | uart4 { | 233 | uart4 { |
| 196 | pinctrl_uart4_1: uart4grp-1 { | 234 | pinctrl_uart4_1: uart4grp-1 { |
| 197 | fsl,pins = < | 235 | fsl,pins = < |
| 198 | 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */ | 236 | MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 |
| 199 | 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */ | 237 | MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 |
| 200 | >; | 238 | >; |
| 201 | }; | 239 | }; |
| 202 | }; | 240 | }; |
| @@ -204,7 +242,13 @@ | |||
| 204 | usbotg { | 242 | usbotg { |
| 205 | pinctrl_usbotg_1: usbotggrp-1 { | 243 | pinctrl_usbotg_1: usbotggrp-1 { |
| 206 | fsl,pins = < | 244 | fsl,pins = < |
| 207 | 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */ | 245 | MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059 |
| 246 | >; | ||
| 247 | }; | ||
| 248 | |||
| 249 | pinctrl_usbotg_2: usbotggrp-2 { | ||
| 250 | fsl,pins = < | ||
| 251 | MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | ||
| 208 | >; | 252 | >; |
| 209 | }; | 253 | }; |
| 210 | }; | 254 | }; |
| @@ -212,16 +256,16 @@ | |||
| 212 | usdhc2 { | 256 | usdhc2 { |
| 213 | pinctrl_usdhc2_1: usdhc2grp-1 { | 257 | pinctrl_usdhc2_1: usdhc2grp-1 { |
| 214 | fsl,pins = < | 258 | fsl,pins = < |
| 215 | 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ | 259 | MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059 |
| 216 | 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ | 260 | MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059 |
| 217 | 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ | 261 | MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059 |
| 218 | 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ | 262 | MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059 |
| 219 | 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ | 263 | MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059 |
| 220 | 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ | 264 | MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059 |
| 221 | 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ | 265 | MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059 |
| 222 | 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ | 266 | MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059 |
| 223 | 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ | 267 | MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059 |
| 224 | 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ | 268 | MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059 |
| 225 | >; | 269 | >; |
| 226 | }; | 270 | }; |
| 227 | }; | 271 | }; |
| @@ -229,27 +273,27 @@ | |||
| 229 | usdhc3 { | 273 | usdhc3 { |
| 230 | pinctrl_usdhc3_1: usdhc3grp-1 { | 274 | pinctrl_usdhc3_1: usdhc3grp-1 { |
| 231 | fsl,pins = < | 275 | fsl,pins = < |
| 232 | 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ | 276 | MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059 |
| 233 | 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ | 277 | MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059 |
| 234 | 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ | 278 | MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
| 235 | 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ | 279 | MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
| 236 | 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ | 280 | MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
| 237 | 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ | 281 | MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
| 238 | 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ | 282 | MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059 |
| 239 | 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ | 283 | MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059 |
| 240 | 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ | 284 | MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059 |
| 241 | 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ | 285 | MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059 |
| 242 | >; | 286 | >; |
| 243 | }; | 287 | }; |
| 244 | 288 | ||
| 245 | pinctrl_usdhc3_2: usdhc3grp-2 { | 289 | pinctrl_usdhc3_2: usdhc3grp-2 { |
| 246 | fsl,pins = < | 290 | fsl,pins = < |
| 247 | 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ | 291 | MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059 |
| 248 | 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ | 292 | MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059 |
| 249 | 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ | 293 | MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
| 250 | 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ | 294 | MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
| 251 | 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ | 295 | MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
| 252 | 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ | 296 | MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
| 253 | >; | 297 | >; |
| 254 | }; | 298 | }; |
| 255 | }; | 299 | }; |
| @@ -257,27 +301,27 @@ | |||
| 257 | usdhc4 { | 301 | usdhc4 { |
| 258 | pinctrl_usdhc4_1: usdhc4grp-1 { | 302 | pinctrl_usdhc4_1: usdhc4grp-1 { |
| 259 | fsl,pins = < | 303 | fsl,pins = < |
| 260 | 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ | 304 | MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059 |
| 261 | 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ | 305 | MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059 |
| 262 | 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ | 306 | MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059 |
| 263 | 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ | 307 | MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059 |
| 264 | 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ | 308 | MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059 |
| 265 | 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ | 309 | MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059 |
| 266 | 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ | 310 | MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059 |
| 267 | 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ | 311 | MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059 |
| 268 | 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ | 312 | MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059 |
| 269 | 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ | 313 | MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059 |
| 270 | >; | 314 | >; |
| 271 | }; | 315 | }; |
| 272 | 316 | ||
| 273 | pinctrl_usdhc4_2: usdhc4grp-2 { | 317 | pinctrl_usdhc4_2: usdhc4grp-2 { |
| 274 | fsl,pins = < | 318 | fsl,pins = < |
| 275 | 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ | 319 | MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059 |
| 276 | 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ | 320 | MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059 |
| 277 | 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ | 321 | MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059 |
| 278 | 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ | 322 | MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059 |
| 279 | 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ | 323 | MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059 |
| 280 | 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ | 324 | MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059 |
| 281 | >; | 325 | >; |
| 282 | }; | 326 | }; |
| 283 | }; | 327 | }; |
| @@ -291,6 +335,24 @@ | |||
| 291 | interrupts = <0 8 0x4 0 7 0x4>; | 335 | interrupts = <0 8 0x4 0 7 0x4>; |
| 292 | clocks = <&clks 133>, <&clks 134>, <&clks 137>; | 336 | clocks = <&clks 133>, <&clks 134>, <&clks 137>; |
| 293 | clock-names = "bus", "di0", "di1"; | 337 | clock-names = "bus", "di0", "di1"; |
| 338 | resets = <&src 4>; | ||
| 294 | }; | 339 | }; |
| 295 | }; | 340 | }; |
| 296 | }; | 341 | }; |
| 342 | |||
| 343 | &ldb { | ||
| 344 | clocks = <&clks 33>, <&clks 34>, | ||
| 345 | <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>, | ||
| 346 | <&clks 135>, <&clks 136>; | ||
| 347 | clock-names = "di0_pll", "di1_pll", | ||
| 348 | "di0_sel", "di1_sel", "di2_sel", "di3_sel", | ||
| 349 | "di0", "di1"; | ||
| 350 | |||
| 351 | lvds-channel@0 { | ||
| 352 | crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; | ||
| 353 | }; | ||
| 354 | |||
| 355 | lvds-channel@1 { | ||
| 356 | crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; | ||
| 357 | }; | ||
| 358 | }; | ||
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi new file mode 100644 index 000000000000..4d237cffcc41 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | |||
| @@ -0,0 +1,38 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2012 Freescale Semiconductor, Inc. | ||
| 3 | * Copyright 2011 Linaro Ltd. | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | / { | ||
| 14 | memory { | ||
| 15 | reg = <0x10000000 0x80000000>; | ||
| 16 | }; | ||
| 17 | }; | ||
| 18 | |||
| 19 | &fec { | ||
| 20 | pinctrl-names = "default"; | ||
| 21 | pinctrl-0 = <&pinctrl_enet_2>; | ||
| 22 | phy-mode = "rgmii"; | ||
| 23 | status = "okay"; | ||
| 24 | }; | ||
| 25 | |||
| 26 | &uart4 { | ||
| 27 | pinctrl-names = "default"; | ||
| 28 | pinctrl-0 = <&pinctrl_uart4_1>; | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
| 31 | |||
| 32 | &usdhc3 { | ||
| 33 | pinctrl-names = "default"; | ||
| 34 | pinctrl-0 = <&pinctrl_usdhc3_1>; | ||
| 35 | cd-gpios = <&gpio6 15 0>; | ||
| 36 | wp-gpios = <&gpio1 13 0>; | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi new file mode 100644 index 000000000000..e21f6a89cf0f --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi | |||
| @@ -0,0 +1,87 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2012 Freescale Semiconductor, Inc. | ||
| 3 | * Copyright 2011 Linaro Ltd. | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | / { | ||
| 14 | memory { | ||
| 15 | reg = <0x10000000 0x40000000>; | ||
| 16 | }; | ||
| 17 | |||
| 18 | regulators { | ||
| 19 | compatible = "simple-bus"; | ||
| 20 | |||
| 21 | reg_usb_otg_vbus: usb_otg_vbus { | ||
| 22 | compatible = "regulator-fixed"; | ||
| 23 | regulator-name = "usb_otg_vbus"; | ||
| 24 | regulator-min-microvolt = <5000000>; | ||
| 25 | regulator-max-microvolt = <5000000>; | ||
| 26 | gpio = <&gpio3 22 0>; | ||
| 27 | enable-active-high; | ||
| 28 | }; | ||
| 29 | }; | ||
| 30 | |||
| 31 | gpio-keys { | ||
| 32 | compatible = "gpio-keys"; | ||
| 33 | |||
| 34 | volume-up { | ||
| 35 | label = "Volume Up"; | ||
| 36 | gpios = <&gpio1 4 0>; | ||
| 37 | linux,code = <115>; /* KEY_VOLUMEUP */ | ||
| 38 | }; | ||
| 39 | |||
| 40 | volume-down { | ||
| 41 | label = "Volume Down"; | ||
| 42 | gpios = <&gpio1 5 0>; | ||
| 43 | linux,code = <114>; /* KEY_VOLUMEDOWN */ | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | |||
| 48 | &fec { | ||
| 49 | pinctrl-names = "default"; | ||
| 50 | pinctrl-0 = <&pinctrl_enet_1>; | ||
| 51 | phy-mode = "rgmii"; | ||
| 52 | status = "okay"; | ||
| 53 | }; | ||
| 54 | |||
| 55 | &uart1 { | ||
| 56 | pinctrl-names = "default"; | ||
| 57 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 58 | status = "okay"; | ||
| 59 | }; | ||
| 60 | |||
| 61 | &usbh1 { | ||
| 62 | status = "okay"; | ||
| 63 | }; | ||
| 64 | |||
| 65 | &usbotg { | ||
| 66 | vbus-supply = <®_usb_otg_vbus>; | ||
| 67 | pinctrl-names = "default"; | ||
| 68 | pinctrl-0 = <&pinctrl_usbotg_2>; | ||
| 69 | disable-over-current; | ||
| 70 | status = "okay"; | ||
| 71 | }; | ||
| 72 | |||
| 73 | &usdhc2 { | ||
| 74 | pinctrl-names = "default"; | ||
| 75 | pinctrl-0 = <&pinctrl_usdhc2_1>; | ||
| 76 | cd-gpios = <&gpio2 2 0>; | ||
| 77 | wp-gpios = <&gpio2 3 0>; | ||
| 78 | status = "okay"; | ||
| 79 | }; | ||
| 80 | |||
| 81 | &usdhc3 { | ||
| 82 | pinctrl-names = "default"; | ||
| 83 | pinctrl-0 = <&pinctrl_usdhc3_1>; | ||
| 84 | cd-gpios = <&gpio2 0 0>; | ||
| 85 | wp-gpios = <&gpio2 1 0>; | ||
| 86 | status = "okay"; | ||
| 87 | }; | ||
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 281a223591ff..3cca7d39529d 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | * http://www.gnu.org/copyleft/gpl.html | 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /include/ "skeleton.dtsi" | 13 | #include "skeleton.dtsi" |
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | aliases { | 16 | aliases { |
| @@ -102,6 +102,11 @@ | |||
| 102 | cache-level = <2>; | 102 | cache-level = <2>; |
| 103 | }; | 103 | }; |
| 104 | 104 | ||
| 105 | pmu { | ||
| 106 | compatible = "arm,cortex-a9-pmu"; | ||
| 107 | interrupts = <0 94 0x04>; | ||
| 108 | }; | ||
| 109 | |||
| 105 | aips-bus@02000000 { /* AIPS1 */ | 110 | aips-bus@02000000 { /* AIPS1 */ |
| 106 | compatible = "fsl,aips-bus", "simple-bus"; | 111 | compatible = "fsl,aips-bus", "simple-bus"; |
| 107 | #address-cells = <1>; | 112 | #address-cells = <1>; |
| @@ -278,6 +283,8 @@ | |||
| 278 | compatible = "fsl,imx6q-gpt"; | 283 | compatible = "fsl,imx6q-gpt"; |
| 279 | reg = <0x02098000 0x4000>; | 284 | reg = <0x02098000 0x4000>; |
| 280 | interrupts = <0 55 0x04>; | 285 | interrupts = <0 55 0x04>; |
| 286 | clocks = <&clks 119>, <&clks 120>; | ||
| 287 | clock-names = "ipg", "per"; | ||
| 281 | }; | 288 | }; |
| 282 | 289 | ||
| 283 | gpio1: gpio@0209c000 { | 290 | gpio1: gpio@0209c000 { |
| @@ -514,9 +521,10 @@ | |||
| 514 | }; | 521 | }; |
| 515 | 522 | ||
| 516 | src: src@020d8000 { | 523 | src: src@020d8000 { |
| 517 | compatible = "fsl,imx6q-src"; | 524 | compatible = "fsl,imx6q-src", "fsl,imx51-src"; |
| 518 | reg = <0x020d8000 0x4000>; | 525 | reg = <0x020d8000 0x4000>; |
| 519 | interrupts = <0 91 0x04 0 96 0x04>; | 526 | interrupts = <0 91 0x04 0 96 0x04>; |
| 527 | #reset-cells = <1>; | ||
| 520 | }; | 528 | }; |
| 521 | 529 | ||
| 522 | gpc: gpc@020dc000 { | 530 | gpc: gpc@020dc000 { |
| @@ -530,6 +538,26 @@ | |||
| 530 | reg = <0x020e0000 0x38>; | 538 | reg = <0x020e0000 0x38>; |
| 531 | }; | 539 | }; |
| 532 | 540 | ||
| 541 | ldb: ldb@020e0008 { | ||
| 542 | #address-cells = <1>; | ||
| 543 | #size-cells = <0>; | ||
| 544 | compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; | ||
| 545 | gpr = <&gpr>; | ||
| 546 | status = "disabled"; | ||
| 547 | |||
| 548 | lvds-channel@0 { | ||
| 549 | reg = <0>; | ||
| 550 | crtcs = <&ipu1 0>; | ||
| 551 | status = "disabled"; | ||
| 552 | }; | ||
| 553 | |||
| 554 | lvds-channel@1 { | ||
| 555 | reg = <1>; | ||
| 556 | crtcs = <&ipu1 1>; | ||
| 557 | status = "disabled"; | ||
| 558 | }; | ||
| 559 | }; | ||
| 560 | |||
| 533 | dcic1: dcic@020e4000 { | 561 | dcic1: dcic@020e4000 { |
| 534 | reg = <0x020e4000 0x4000>; | 562 | reg = <0x020e4000 0x4000>; |
| 535 | interrupts = <0 124 0x04>; | 563 | interrupts = <0 124 0x04>; |
| @@ -796,6 +824,7 @@ | |||
| 796 | interrupts = <0 6 0x4 0 5 0x4>; | 824 | interrupts = <0 6 0x4 0 5 0x4>; |
| 797 | clocks = <&clks 130>, <&clks 131>, <&clks 132>; | 825 | clocks = <&clks 130>, <&clks 131>, <&clks 132>; |
| 798 | clock-names = "bus", "di0", "di1"; | 826 | clock-names = "bus", "di0", "di1"; |
| 827 | resets = <&src 2>; | ||
| 799 | }; | 828 | }; |
| 800 | }; | 829 | }; |
| 801 | }; | 830 | }; |
diff --git a/arch/arm/boot/dts/imx6sl-pinfunc.h b/arch/arm/boot/dts/imx6sl-pinfunc.h new file mode 100644 index 000000000000..77b17bcc7b70 --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-pinfunc.h | |||
| @@ -0,0 +1,1077 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __DTS_IMX6SL_PINFUNC_H | ||
| 11 | #define __DTS_IMX6SL_PINFUNC_H | ||
| 12 | |||
| 13 | /* | ||
| 14 | * The pin function ID is a tuple of | ||
| 15 | * <mux_reg conf_reg input_reg mux_mode input_val> | ||
| 16 | */ | ||
| 17 | #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 | ||
| 18 | #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 | ||
| 19 | #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 | ||
| 20 | #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 | ||
| 21 | #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 | ||
| 22 | #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 | ||
| 23 | #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 | ||
| 24 | #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 | ||
| 25 | #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 | ||
| 26 | #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 | ||
| 27 | #define MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x050 0x2a8 0x80c 0x2 0x0 | ||
| 28 | #define MX6SL_PAD_AUD_RXC__FEC_TX_CLK 0x050 0x2a8 0x70c 0x3 0x0 | ||
| 29 | #define MX6SL_PAD_AUD_RXC__I2C3_SDA 0x050 0x2a8 0x730 0x4 0x0 | ||
| 30 | #define MX6SL_PAD_AUD_RXC__GPIO1_IO01 0x050 0x2a8 0x000 0x5 0x0 | ||
| 31 | #define MX6SL_PAD_AUD_RXC__ECSPI3_SS1 0x050 0x2a8 0x6c4 0x6 0x0 | ||
| 32 | #define MX6SL_PAD_AUD_RXD__AUD3_RXD 0x054 0x2ac 0x000 0x0 0x0 | ||
| 33 | #define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI 0x054 0x2ac 0x6bc 0x1 0x0 | ||
| 34 | #define MX6SL_PAD_AUD_RXD__UART4_RX_DATA 0x054 0x2ac 0x814 0x2 0x0 | ||
| 35 | #define MX6SL_PAD_AUD_RXD__UART4_TX_DATA 0x054 0x2ac 0x000 0x2 0x0 | ||
| 36 | #define MX6SL_PAD_AUD_RXD__FEC_RX_ER 0x054 0x2ac 0x708 0x3 0x0 | ||
| 37 | #define MX6SL_PAD_AUD_RXD__SD1_LCTL 0x054 0x2ac 0x000 0x4 0x0 | ||
| 38 | #define MX6SL_PAD_AUD_RXD__GPIO1_IO02 0x054 0x2ac 0x000 0x5 0x0 | ||
| 39 | #define MX6SL_PAD_AUD_RXFS__AUD3_RXFS 0x058 0x2b0 0x000 0x0 0x0 | ||
| 40 | #define MX6SL_PAD_AUD_RXFS__I2C1_SCL 0x058 0x2b0 0x71c 0x1 0x0 | ||
| 41 | #define MX6SL_PAD_AUD_RXFS__UART3_RX_DATA 0x058 0x2b0 0x80c 0x2 0x1 | ||
| 42 | #define MX6SL_PAD_AUD_RXFS__UART3_TX_DATA 0x058 0x2b0 0x000 0x2 0x0 | ||
| 43 | #define MX6SL_PAD_AUD_RXFS__FEC_MDIO 0x058 0x2b0 0x6f4 0x3 0x0 | ||
| 44 | #define MX6SL_PAD_AUD_RXFS__I2C3_SCL 0x058 0x2b0 0x72c 0x4 0x0 | ||
| 45 | #define MX6SL_PAD_AUD_RXFS__GPIO1_IO00 0x058 0x2b0 0x000 0x5 0x0 | ||
| 46 | #define MX6SL_PAD_AUD_RXFS__ECSPI3_SS0 0x058 0x2b0 0x6c0 0x6 0x0 | ||
| 47 | #define MX6SL_PAD_AUD_TXC__AUD3_TXC 0x05c 0x2b4 0x000 0x0 0x0 | ||
| 48 | #define MX6SL_PAD_AUD_TXC__ECSPI3_MISO 0x05c 0x2b4 0x6b8 0x1 0x0 | ||
| 49 | #define MX6SL_PAD_AUD_TXC__UART4_TX_DATA 0x05c 0x2b4 0x000 0x2 0x0 | ||
| 50 | #define MX6SL_PAD_AUD_TXC__UART4_RX_DATA 0x05c 0x2b4 0x814 0x2 0x1 | ||
| 51 | #define MX6SL_PAD_AUD_TXC__FEC_RX_DV 0x05c 0x2b4 0x704 0x3 0x0 | ||
| 52 | #define MX6SL_PAD_AUD_TXC__SD2_LCTL 0x05c 0x2b4 0x000 0x4 0x0 | ||
| 53 | #define MX6SL_PAD_AUD_TXC__GPIO1_IO03 0x05c 0x2b4 0x000 0x5 0x0 | ||
| 54 | #define MX6SL_PAD_AUD_TXD__AUD3_TXD 0x060 0x2b8 0x000 0x0 0x0 | ||
| 55 | #define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK 0x060 0x2b8 0x6b0 0x1 0x0 | ||
| 56 | #define MX6SL_PAD_AUD_TXD__UART4_CTS_B 0x060 0x2b8 0x000 0x2 0x0 | ||
| 57 | #define MX6SL_PAD_AUD_TXD__UART4_RTS_B 0x060 0x2b8 0x810 0x2 0x0 | ||
| 58 | #define MX6SL_PAD_AUD_TXD__FEC_TX_DATA0 0x060 0x2b8 0x000 0x3 0x0 | ||
| 59 | #define MX6SL_PAD_AUD_TXD__SD4_LCTL 0x060 0x2b8 0x000 0x4 0x0 | ||
| 60 | #define MX6SL_PAD_AUD_TXD__GPIO1_IO05 0x060 0x2b8 0x000 0x5 0x0 | ||
| 61 | #define MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x064 0x2bc 0x000 0x0 0x0 | ||
| 62 | #define MX6SL_PAD_AUD_TXFS__PWM3_OUT 0x064 0x2bc 0x000 0x1 0x0 | ||
| 63 | #define MX6SL_PAD_AUD_TXFS__UART4_RTS_B 0x064 0x2bc 0x810 0x2 0x1 | ||
| 64 | #define MX6SL_PAD_AUD_TXFS__UART4_CTS_B 0x064 0x2bc 0x000 0x2 0x0 | ||
| 65 | #define MX6SL_PAD_AUD_TXFS__FEC_RX_DATA1 0x064 0x2bc 0x6fc 0x3 0x0 | ||
| 66 | #define MX6SL_PAD_AUD_TXFS__SD3_LCTL 0x064 0x2bc 0x000 0x4 0x0 | ||
| 67 | #define MX6SL_PAD_AUD_TXFS__GPIO1_IO04 0x064 0x2bc 0x000 0x5 0x0 | ||
| 68 | #define MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x068 0x358 0x684 0x0 0x0 | ||
| 69 | #define MX6SL_PAD_ECSPI1_MISO__AUD4_TXFS 0x068 0x358 0x5f8 0x1 0x0 | ||
| 70 | #define MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x068 0x358 0x818 0x2 0x0 | ||
| 71 | #define MX6SL_PAD_ECSPI1_MISO__UART5_CTS_B 0x068 0x358 0x000 0x2 0x0 | ||
| 72 | #define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR0 0x068 0x358 0x000 0x3 0x0 | ||
| 73 | #define MX6SL_PAD_ECSPI1_MISO__SD2_WP 0x068 0x358 0x834 0x4 0x0 | ||
| 74 | #define MX6SL_PAD_ECSPI1_MISO__GPIO4_IO10 0x068 0x358 0x000 0x5 0x0 | ||
| 75 | #define MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x06c 0x35c 0x688 0x0 0x0 | ||
| 76 | #define MX6SL_PAD_ECSPI1_MOSI__AUD4_TXC 0x06c 0x35c 0x5f4 0x1 0x0 | ||
| 77 | #define MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x06c 0x35c 0x000 0x2 0x0 | ||
| 78 | #define MX6SL_PAD_ECSPI1_MOSI__UART5_RX_DATA 0x06c 0x35c 0x81c 0x2 0x0 | ||
| 79 | #define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x06c 0x35c 0x000 0x3 0x0 | ||
| 80 | #define MX6SL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x06c 0x35c 0x000 0x4 0x0 | ||
| 81 | #define MX6SL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x06c 0x35c 0x000 0x5 0x0 | ||
| 82 | #define MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x070 0x360 0x67c 0x0 0x0 | ||
| 83 | #define MX6SL_PAD_ECSPI1_SCLK__AUD4_TXD 0x070 0x360 0x5e8 0x1 0x0 | ||
| 84 | #define MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x070 0x360 0x81c 0x2 0x1 | ||
| 85 | #define MX6SL_PAD_ECSPI1_SCLK__UART5_TX_DATA 0x070 0x360 0x000 0x2 0x0 | ||
| 86 | #define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x070 0x360 0x000 0x3 0x0 | ||
| 87 | #define MX6SL_PAD_ECSPI1_SCLK__SD2_RESET 0x070 0x360 0x000 0x4 0x0 | ||
| 88 | #define MX6SL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x070 0x360 0x000 0x5 0x0 | ||
| 89 | #define MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x070 0x360 0x820 0x6 0x0 | ||
| 90 | #define MX6SL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x074 0x364 0x68c 0x0 0x0 | ||
| 91 | #define MX6SL_PAD_ECSPI1_SS0__AUD4_RXD 0x074 0x364 0x5e4 0x1 0x0 | ||
| 92 | #define MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x074 0x364 0x000 0x2 0x0 | ||
| 93 | #define MX6SL_PAD_ECSPI1_SS0__UART5_RTS_B 0x074 0x364 0x818 0x2 0x1 | ||
| 94 | #define MX6SL_PAD_ECSPI1_SS0__EPDC_BDR1 0x074 0x364 0x000 0x3 0x0 | ||
| 95 | #define MX6SL_PAD_ECSPI1_SS0__SD2_CD_B 0x074 0x364 0x830 0x4 0x0 | ||
| 96 | #define MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x074 0x364 0x000 0x5 0x0 | ||
| 97 | #define MX6SL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x074 0x364 0x000 0x6 0x0 | ||
| 98 | #define MX6SL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x078 0x368 0x6a0 0x0 0x0 | ||
| 99 | #define MX6SL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x078 0x368 0x000 0x1 0x0 | ||
| 100 | #define MX6SL_PAD_ECSPI2_MISO__UART3_RTS_B 0x078 0x368 0x808 0x2 0x0 | ||
| 101 | #define MX6SL_PAD_ECSPI2_MISO__UART3_CTS_B 0x078 0x368 0x000 0x2 0x0 | ||
| 102 | #define MX6SL_PAD_ECSPI2_MISO__CSI_MCLK 0x078 0x368 0x000 0x3 0x0 | ||
| 103 | #define MX6SL_PAD_ECSPI2_MISO__SD1_WP 0x078 0x368 0x82c 0x4 0x0 | ||
| 104 | #define MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x078 0x368 0x000 0x5 0x0 | ||
| 105 | #define MX6SL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x078 0x368 0x824 0x6 0x0 | ||
| 106 | #define MX6SL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x07c 0x36c 0x6a4 0x0 0x0 | ||
| 107 | #define MX6SL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x07c 0x36c 0x000 0x1 0x0 | ||
| 108 | #define MX6SL_PAD_ECSPI2_MOSI__UART3_TX_DATA 0x07c 0x36c 0x000 0x2 0x0 | ||
| 109 | #define MX6SL_PAD_ECSPI2_MOSI__UART3_RX_DATA 0x07c 0x36c 0x80c 0x2 0x2 | ||
| 110 | #define MX6SL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x07c 0x36c 0x670 0x3 0x0 | ||
| 111 | #define MX6SL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x07c 0x36c 0x000 0x4 0x0 | ||
| 112 | #define MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x07c 0x36c 0x000 0x5 0x0 | ||
| 113 | #define MX6SL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x080 0x370 0x69c 0x0 0x0 | ||
| 114 | #define MX6SL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x080 0x370 0x7f4 0x1 0x1 | ||
| 115 | #define MX6SL_PAD_ECSPI2_SCLK__UART3_RX_DATA 0x080 0x370 0x80c 0x2 0x3 | ||
| 116 | #define MX6SL_PAD_ECSPI2_SCLK__UART3_TX_DATA 0x080 0x370 0x000 0x2 0x0 | ||
| 117 | #define MX6SL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x080 0x370 0x674 0x3 0x0 | ||
| 118 | #define MX6SL_PAD_ECSPI2_SCLK__SD1_RESET 0x080 0x370 0x000 0x4 0x0 | ||
| 119 | #define MX6SL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x080 0x370 0x000 0x5 0x0 | ||
| 120 | #define MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x080 0x370 0x820 0x6 0x1 | ||
| 121 | #define MX6SL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x084 0x374 0x6a8 0x0 0x0 | ||
| 122 | #define MX6SL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x084 0x374 0x698 0x1 0x0 | ||
| 123 | #define MX6SL_PAD_ECSPI2_SS0__UART3_CTS_B 0x084 0x374 0x000 0x2 0x0 | ||
| 124 | #define MX6SL_PAD_ECSPI2_SS0__UART3_RTS_B 0x084 0x374 0x808 0x2 0x1 | ||
| 125 | #define MX6SL_PAD_ECSPI2_SS0__CSI_VSYNC 0x084 0x374 0x678 0x3 0x0 | ||
| 126 | #define MX6SL_PAD_ECSPI2_SS0__SD1_CD_B 0x084 0x374 0x828 0x4 0x0 | ||
| 127 | #define MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x084 0x374 0x000 0x5 0x0 | ||
| 128 | #define MX6SL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x084 0x374 0x000 0x6 0x0 | ||
| 129 | #define MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x088 0x378 0x000 0x0 0x0 | ||
| 130 | #define MX6SL_PAD_EPDC_BDR0__SD4_CLK 0x088 0x378 0x850 0x1 0x0 | ||
| 131 | #define MX6SL_PAD_EPDC_BDR0__UART3_RTS_B 0x088 0x378 0x808 0x2 0x2 | ||
| 132 | #define MX6SL_PAD_EPDC_BDR0__UART3_CTS_B 0x088 0x378 0x000 0x2 0x0 | ||
| 133 | #define MX6SL_PAD_EPDC_BDR0__EIM_ADDR26 0x088 0x378 0x000 0x3 0x0 | ||
| 134 | #define MX6SL_PAD_EPDC_BDR0__SPDC_RL 0x088 0x378 0x000 0x4 0x0 | ||
| 135 | #define MX6SL_PAD_EPDC_BDR0__GPIO2_IO05 0x088 0x378 0x000 0x5 0x0 | ||
| 136 | #define MX6SL_PAD_EPDC_BDR0__EPDC_SDCE7 0x088 0x378 0x000 0x6 0x0 | ||
| 137 | #define MX6SL_PAD_EPDC_BDR1__EPDC_BDR1 0x08c 0x37c 0x000 0x0 0x0 | ||
| 138 | #define MX6SL_PAD_EPDC_BDR1__SD4_CMD 0x08c 0x37c 0x858 0x1 0x0 | ||
| 139 | #define MX6SL_PAD_EPDC_BDR1__UART3_CTS_B 0x08c 0x37c 0x000 0x2 0x0 | ||
| 140 | #define MX6SL_PAD_EPDC_BDR1__UART3_RTS_B 0x08c 0x37c 0x808 0x2 0x3 | ||
| 141 | #define MX6SL_PAD_EPDC_BDR1__EIM_CRE 0x08c 0x37c 0x000 0x3 0x0 | ||
| 142 | #define MX6SL_PAD_EPDC_BDR1__SPDC_UD 0x08c 0x37c 0x000 0x4 0x0 | ||
| 143 | #define MX6SL_PAD_EPDC_BDR1__GPIO2_IO06 0x08c 0x37c 0x000 0x5 0x0 | ||
| 144 | #define MX6SL_PAD_EPDC_BDR1__EPDC_SDCE8 0x08c 0x37c 0x000 0x6 0x0 | ||
| 145 | #define MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x090 0x380 0x000 0x0 0x0 | ||
| 146 | #define MX6SL_PAD_EPDC_D0__ECSPI4_MOSI 0x090 0x380 0x6d8 0x1 0x0 | ||
| 147 | #define MX6SL_PAD_EPDC_D0__LCD_DATA24 0x090 0x380 0x000 0x2 0x0 | ||
| 148 | #define MX6SL_PAD_EPDC_D0__CSI_DATA00 0x090 0x380 0x630 0x3 0x0 | ||
| 149 | #define MX6SL_PAD_EPDC_D0__SPDC_DATA00 0x090 0x380 0x000 0x4 0x0 | ||
| 150 | #define MX6SL_PAD_EPDC_D0__GPIO1_IO07 0x090 0x380 0x000 0x5 0x0 | ||
| 151 | #define MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x094 0x384 0x000 0x0 0x0 | ||
| 152 | #define MX6SL_PAD_EPDC_D1__ECSPI4_MISO 0x094 0x384 0x6d4 0x1 0x0 | ||
| 153 | #define MX6SL_PAD_EPDC_D1__LCD_DATA25 0x094 0x384 0x000 0x2 0x0 | ||
| 154 | #define MX6SL_PAD_EPDC_D1__CSI_DATA01 0x094 0x384 0x634 0x3 0x0 | ||
| 155 | #define MX6SL_PAD_EPDC_D1__SPDC_DATA01 0x094 0x384 0x000 0x4 0x0 | ||
| 156 | #define MX6SL_PAD_EPDC_D1__GPIO1_IO08 0x094 0x384 0x000 0x5 0x0 | ||
| 157 | #define MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x098 0x388 0x000 0x0 0x0 | ||
| 158 | #define MX6SL_PAD_EPDC_D10__ECSPI3_SS0 0x098 0x388 0x6c0 0x1 0x1 | ||
| 159 | #define MX6SL_PAD_EPDC_D10__EPDC_PWR_CTRL2 0x098 0x388 0x000 0x2 0x0 | ||
| 160 | #define MX6SL_PAD_EPDC_D10__EIM_ADDR18 0x098 0x388 0x000 0x3 0x0 | ||
| 161 | #define MX6SL_PAD_EPDC_D10__SPDC_DATA10 0x098 0x388 0x000 0x4 0x0 | ||
| 162 | #define MX6SL_PAD_EPDC_D10__GPIO1_IO17 0x098 0x388 0x000 0x5 0x0 | ||
| 163 | #define MX6SL_PAD_EPDC_D10__SD4_WP 0x098 0x388 0x87c 0x6 0x0 | ||
| 164 | #define MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x09c 0x38c 0x000 0x0 0x0 | ||
| 165 | #define MX6SL_PAD_EPDC_D11__ECSPI3_SCLK 0x09c 0x38c 0x6b0 0x1 0x1 | ||
| 166 | #define MX6SL_PAD_EPDC_D11__EPDC_PWR_CTRL3 0x09c 0x38c 0x000 0x2 0x0 | ||
| 167 | #define MX6SL_PAD_EPDC_D11__EIM_ADDR19 0x09c 0x38c 0x000 0x3 0x0 | ||
| 168 | #define MX6SL_PAD_EPDC_D11__SPDC_DATA11 0x09c 0x38c 0x000 0x4 0x0 | ||
| 169 | #define MX6SL_PAD_EPDC_D11__GPIO1_IO18 0x09c 0x38c 0x000 0x5 0x0 | ||
| 170 | #define MX6SL_PAD_EPDC_D11__SD4_CD_B 0x09c 0x38c 0x854 0x6 0x0 | ||
| 171 | #define MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x0a0 0x390 0x000 0x0 0x0 | ||
| 172 | #define MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x0a0 0x390 0x804 0x1 0x0 | ||
| 173 | #define MX6SL_PAD_EPDC_D12__UART2_TX_DATA 0x0a0 0x390 0x000 0x1 0x0 | ||
| 174 | #define MX6SL_PAD_EPDC_D12__EPDC_PWR_COM 0x0a0 0x390 0x000 0x2 0x0 | ||
| 175 | #define MX6SL_PAD_EPDC_D12__EIM_ADDR20 0x0a0 0x390 0x000 0x3 0x0 | ||
| 176 | #define MX6SL_PAD_EPDC_D12__SPDC_DATA12 0x0a0 0x390 0x000 0x4 0x0 | ||
| 177 | #define MX6SL_PAD_EPDC_D12__GPIO1_IO19 0x0a0 0x390 0x000 0x5 0x0 | ||
| 178 | #define MX6SL_PAD_EPDC_D12__ECSPI3_SS1 0x0a0 0x390 0x6c4 0x6 0x1 | ||
| 179 | #define MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x0a4 0x394 0x000 0x0 0x0 | ||
| 180 | #define MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x0a4 0x394 0x000 0x1 0x0 | ||
| 181 | #define MX6SL_PAD_EPDC_D13__UART2_RX_DATA 0x0a4 0x394 0x804 0x1 0x1 | ||
| 182 | #define MX6SL_PAD_EPDC_D13__EPDC_PWR_IRQ 0x0a4 0x394 0x6e8 0x2 0x0 | ||
| 183 | #define MX6SL_PAD_EPDC_D13__EIM_ADDR21 0x0a4 0x394 0x000 0x3 0x0 | ||
| 184 | #define MX6SL_PAD_EPDC_D13__SPDC_DATA13 0x0a4 0x394 0x000 0x4 0x0 | ||
| 185 | #define MX6SL_PAD_EPDC_D13__GPIO1_IO20 0x0a4 0x394 0x000 0x5 0x0 | ||
| 186 | #define MX6SL_PAD_EPDC_D13__ECSPI3_SS2 0x0a4 0x394 0x6c8 0x6 0x0 | ||
| 187 | #define MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x0a8 0x398 0x000 0x0 0x0 | ||
| 188 | #define MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x0a8 0x398 0x800 0x1 0x0 | ||
| 189 | #define MX6SL_PAD_EPDC_D14__UART2_CTS_B 0x0a8 0x398 0x000 0x1 0x0 | ||
| 190 | #define MX6SL_PAD_EPDC_D14__EPDC_PWR_STAT 0x0a8 0x398 0x6ec 0x2 0x0 | ||
| 191 | #define MX6SL_PAD_EPDC_D14__EIM_ADDR22 0x0a8 0x398 0x000 0x3 0x0 | ||
| 192 | #define MX6SL_PAD_EPDC_D14__SPDC_DATA14 0x0a8 0x398 0x000 0x4 0x0 | ||
| 193 | #define MX6SL_PAD_EPDC_D14__GPIO1_IO21 0x0a8 0x398 0x000 0x5 0x0 | ||
| 194 | #define MX6SL_PAD_EPDC_D14__ECSPI3_SS3 0x0a8 0x398 0x6cc 0x6 0x0 | ||
| 195 | #define MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x0ac 0x39c 0x000 0x0 0x0 | ||
| 196 | #define MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x0ac 0x39c 0x000 0x1 0x0 | ||
| 197 | #define MX6SL_PAD_EPDC_D15__UART2_RTS_B 0x0ac 0x39c 0x800 0x1 0x1 | ||
| 198 | #define MX6SL_PAD_EPDC_D15__EPDC_PWR_WAKE 0x0ac 0x39c 0x000 0x2 0x0 | ||
| 199 | #define MX6SL_PAD_EPDC_D15__EIM_ADDR23 0x0ac 0x39c 0x000 0x3 0x0 | ||
| 200 | #define MX6SL_PAD_EPDC_D15__SPDC_DATA15 0x0ac 0x39c 0x000 0x4 0x0 | ||
| 201 | #define MX6SL_PAD_EPDC_D15__GPIO1_IO22 0x0ac 0x39c 0x000 0x5 0x0 | ||
| 202 | #define MX6SL_PAD_EPDC_D15__ECSPI3_RDY 0x0ac 0x39c 0x6b4 0x6 0x1 | ||
| 203 | #define MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x0b0 0x3a0 0x000 0x0 0x0 | ||
| 204 | #define MX6SL_PAD_EPDC_D2__ECSPI4_SS0 0x0b0 0x3a0 0x6dc 0x1 0x0 | ||
| 205 | #define MX6SL_PAD_EPDC_D2__LCD_DATA26 0x0b0 0x3a0 0x000 0x2 0x0 | ||
| 206 | #define MX6SL_PAD_EPDC_D2__CSI_DATA02 0x0b0 0x3a0 0x638 0x3 0x0 | ||
| 207 | #define MX6SL_PAD_EPDC_D2__SPDC_DATA02 0x0b0 0x3a0 0x000 0x4 0x0 | ||
| 208 | #define MX6SL_PAD_EPDC_D2__GPIO1_IO09 0x0b0 0x3a0 0x000 0x5 0x0 | ||
| 209 | #define MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x0b4 0x3a4 0x000 0x0 0x0 | ||
| 210 | #define MX6SL_PAD_EPDC_D3__ECSPI4_SCLK 0x0b4 0x3a4 0x6d0 0x1 0x0 | ||
| 211 | #define MX6SL_PAD_EPDC_D3__LCD_DATA27 0x0b4 0x3a4 0x000 0x2 0x0 | ||
| 212 | #define MX6SL_PAD_EPDC_D3__CSI_DATA03 0x0b4 0x3a4 0x63c 0x3 0x0 | ||
| 213 | #define MX6SL_PAD_EPDC_D3__SPDC_DATA03 0x0b4 0x3a4 0x000 0x4 0x0 | ||
| 214 | #define MX6SL_PAD_EPDC_D3__GPIO1_IO10 0x0b4 0x3a4 0x000 0x5 0x0 | ||
| 215 | #define MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x0b8 0x3a8 0x000 0x0 0x0 | ||
| 216 | #define MX6SL_PAD_EPDC_D4__ECSPI4_SS1 0x0b8 0x3a8 0x6e0 0x1 0x0 | ||
| 217 | #define MX6SL_PAD_EPDC_D4__LCD_DATA28 0x0b8 0x3a8 0x000 0x2 0x0 | ||
| 218 | #define MX6SL_PAD_EPDC_D4__CSI_DATA04 0x0b8 0x3a8 0x640 0x3 0x0 | ||
| 219 | #define MX6SL_PAD_EPDC_D4__SPDC_DATA04 0x0b8 0x3a8 0x000 0x4 0x0 | ||
| 220 | #define MX6SL_PAD_EPDC_D4__GPIO1_IO11 0x0b8 0x3a8 0x000 0x5 0x0 | ||
| 221 | #define MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x0bc 0x3ac 0x000 0x0 0x0 | ||
| 222 | #define MX6SL_PAD_EPDC_D5__ECSPI4_SS2 0x0bc 0x3ac 0x6e4 0x1 0x0 | ||
| 223 | #define MX6SL_PAD_EPDC_D5__LCD_DATA29 0x0bc 0x3ac 0x000 0x2 0x0 | ||
| 224 | #define MX6SL_PAD_EPDC_D5__CSI_DATA05 0x0bc 0x3ac 0x644 0x3 0x0 | ||
| 225 | #define MX6SL_PAD_EPDC_D5__SPDC_DATA05 0x0bc 0x3ac 0x000 0x4 0x0 | ||
| 226 | #define MX6SL_PAD_EPDC_D5__GPIO1_IO12 0x0bc 0x3ac 0x000 0x5 0x0 | ||
| 227 | #define MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x0c0 0x3b0 0x000 0x0 0x0 | ||
| 228 | #define MX6SL_PAD_EPDC_D6__ECSPI4_SS3 0x0c0 0x3b0 0x000 0x1 0x0 | ||
| 229 | #define MX6SL_PAD_EPDC_D6__LCD_DATA30 0x0c0 0x3b0 0x000 0x2 0x0 | ||
| 230 | #define MX6SL_PAD_EPDC_D6__CSI_DATA06 0x0c0 0x3b0 0x648 0x3 0x0 | ||
| 231 | #define MX6SL_PAD_EPDC_D6__SPDC_DATA06 0x0c0 0x3b0 0x000 0x4 0x0 | ||
| 232 | #define MX6SL_PAD_EPDC_D6__GPIO1_IO13 0x0c0 0x3b0 0x000 0x5 0x0 | ||
| 233 | #define MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x0c4 0x3b4 0x000 0x0 0x0 | ||
| 234 | #define MX6SL_PAD_EPDC_D7__ECSPI4_RDY 0x0c4 0x3b4 0x000 0x1 0x0 | ||
| 235 | #define MX6SL_PAD_EPDC_D7__LCD_DATA31 0x0c4 0x3b4 0x000 0x2 0x0 | ||
| 236 | #define MX6SL_PAD_EPDC_D7__CSI_DATA07 0x0c4 0x3b4 0x64c 0x3 0x0 | ||
| 237 | #define MX6SL_PAD_EPDC_D7__SPDC_DATA07 0x0c4 0x3b4 0x000 0x4 0x0 | ||
| 238 | #define MX6SL_PAD_EPDC_D7__GPIO1_IO14 0x0c4 0x3b4 0x000 0x5 0x0 | ||
| 239 | #define MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x0c8 0x3b8 0x000 0x0 0x0 | ||
| 240 | #define MX6SL_PAD_EPDC_D8__ECSPI3_MOSI 0x0c8 0x3b8 0x6bc 0x1 0x1 | ||
| 241 | #define MX6SL_PAD_EPDC_D8__EPDC_PWR_CTRL0 0x0c8 0x3b8 0x000 0x2 0x0 | ||
| 242 | #define MX6SL_PAD_EPDC_D8__EIM_ADDR16 0x0c8 0x3b8 0x000 0x3 0x0 | ||
| 243 | #define MX6SL_PAD_EPDC_D8__SPDC_DATA08 0x0c8 0x3b8 0x000 0x4 0x0 | ||
| 244 | #define MX6SL_PAD_EPDC_D8__GPIO1_IO15 0x0c8 0x3b8 0x000 0x5 0x0 | ||
| 245 | #define MX6SL_PAD_EPDC_D8__SD4_RESET 0x0c8 0x3b8 0x000 0x6 0x0 | ||
| 246 | #define MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x0cc 0x3bc 0x000 0x0 0x0 | ||
| 247 | #define MX6SL_PAD_EPDC_D9__ECSPI3_MISO 0x0cc 0x3bc 0x6b8 0x1 0x1 | ||
| 248 | #define MX6SL_PAD_EPDC_D9__EPDC_PWR_CTRL1 0x0cc 0x3bc 0x000 0x2 0x0 | ||
| 249 | #define MX6SL_PAD_EPDC_D9__EIM_ADDR17 0x0cc 0x3bc 0x000 0x3 0x0 | ||
| 250 | #define MX6SL_PAD_EPDC_D9__SPDC_DATA09 0x0cc 0x3bc 0x000 0x4 0x0 | ||
| 251 | #define MX6SL_PAD_EPDC_D9__GPIO1_IO16 0x0cc 0x3bc 0x000 0x5 0x0 | ||
| 252 | #define MX6SL_PAD_EPDC_D9__SD4_VSELECT 0x0cc 0x3bc 0x000 0x6 0x0 | ||
| 253 | #define MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0d0 0x3c0 0x000 0x0 0x0 | ||
| 254 | #define MX6SL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x0d0 0x3c0 0x000 0x1 0x0 | ||
| 255 | #define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKR 0x0d0 0x3c0 0x000 0x2 0x0 | ||
| 256 | #define MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x0d0 0x3c0 0x674 0x3 0x1 | ||
| 257 | #define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKL 0x0d0 0x3c0 0x000 0x4 0x0 | ||
| 258 | #define MX6SL_PAD_EPDC_GDCLK__GPIO1_IO31 0x0d0 0x3c0 0x000 0x5 0x0 | ||
| 259 | #define MX6SL_PAD_EPDC_GDCLK__SD2_RESET 0x0d0 0x3c0 0x000 0x6 0x0 | ||
| 260 | #define MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x0d4 0x3c4 0x000 0x0 0x0 | ||
| 261 | #define MX6SL_PAD_EPDC_GDOE__ECSPI2_SS3 0x0d4 0x3c4 0x000 0x1 0x0 | ||
| 262 | #define MX6SL_PAD_EPDC_GDOE__SPDC_YOER 0x0d4 0x3c4 0x000 0x2 0x0 | ||
| 263 | #define MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x0d4 0x3c4 0x670 0x3 0x1 | ||
| 264 | #define MX6SL_PAD_EPDC_GDOE__SPDC_YOEL 0x0d4 0x3c4 0x000 0x4 0x0 | ||
| 265 | #define MX6SL_PAD_EPDC_GDOE__GPIO2_IO00 0x0d4 0x3c4 0x000 0x5 0x0 | ||
| 266 | #define MX6SL_PAD_EPDC_GDOE__SD2_VSELECT 0x0d4 0x3c4 0x000 0x6 0x0 | ||
| 267 | #define MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x0d8 0x3c8 0x000 0x0 0x0 | ||
| 268 | #define MX6SL_PAD_EPDC_GDRL__ECSPI2_RDY 0x0d8 0x3c8 0x000 0x1 0x0 | ||
| 269 | #define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUR 0x0d8 0x3c8 0x000 0x2 0x0 | ||
| 270 | #define MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x0d8 0x3c8 0x000 0x3 0x0 | ||
| 271 | #define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUL 0x0d8 0x3c8 0x000 0x4 0x0 | ||
| 272 | #define MX6SL_PAD_EPDC_GDRL__GPIO2_IO01 0x0d8 0x3c8 0x000 0x5 0x0 | ||
| 273 | #define MX6SL_PAD_EPDC_GDRL__SD2_WP 0x0d8 0x3c8 0x834 0x6 0x1 | ||
| 274 | #define MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x0dc 0x3cc 0x000 0x0 0x0 | ||
| 275 | #define MX6SL_PAD_EPDC_GDSP__PWM4_OUT 0x0dc 0x3cc 0x000 0x1 0x0 | ||
| 276 | #define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODR 0x0dc 0x3cc 0x000 0x2 0x0 | ||
| 277 | #define MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x0dc 0x3cc 0x678 0x3 0x1 | ||
| 278 | #define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODL 0x0dc 0x3cc 0x000 0x4 0x0 | ||
| 279 | #define MX6SL_PAD_EPDC_GDSP__GPIO2_IO02 0x0dc 0x3cc 0x000 0x5 0x0 | ||
| 280 | #define MX6SL_PAD_EPDC_GDSP__SD2_CD_B 0x0dc 0x3cc 0x830 0x6 0x1 | ||
| 281 | #define MX6SL_PAD_EPDC_PWRCOM__EPDC_PWR_COM 0x0e0 0x3d0 0x000 0x0 0x0 | ||
| 282 | #define MX6SL_PAD_EPDC_PWRCOM__SD4_DATA0 0x0e0 0x3d0 0x85c 0x1 0x0 | ||
| 283 | #define MX6SL_PAD_EPDC_PWRCOM__LCD_DATA20 0x0e0 0x3d0 0x7c8 0x2 0x0 | ||
| 284 | #define MX6SL_PAD_EPDC_PWRCOM__EIM_BCLK 0x0e0 0x3d0 0x000 0x3 0x0 | ||
| 285 | #define MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x0e0 0x3d0 0x5dc 0x4 0x0 | ||
| 286 | #define MX6SL_PAD_EPDC_PWRCOM__GPIO2_IO11 0x0e0 0x3d0 0x000 0x5 0x0 | ||
| 287 | #define MX6SL_PAD_EPDC_PWRCOM__SD3_RESET 0x0e0 0x3d0 0x000 0x6 0x0 | ||
| 288 | #define MX6SL_PAD_EPDC_PWRCTRL0__EPDC_PWR_CTRL0 0x0e4 0x3d4 0x000 0x0 0x0 | ||
| 289 | #define MX6SL_PAD_EPDC_PWRCTRL0__AUD5_RXC 0x0e4 0x3d4 0x604 0x1 0x0 | ||
| 290 | #define MX6SL_PAD_EPDC_PWRCTRL0__LCD_DATA16 0x0e4 0x3d4 0x7b8 0x2 0x0 | ||
| 291 | #define MX6SL_PAD_EPDC_PWRCTRL0__EIM_RW 0x0e4 0x3d4 0x000 0x3 0x0 | ||
| 292 | #define MX6SL_PAD_EPDC_PWRCTRL0__SPDC_YCKL 0x0e4 0x3d4 0x000 0x4 0x0 | ||
| 293 | #define MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x0e4 0x3d4 0x000 0x5 0x0 | ||
| 294 | #define MX6SL_PAD_EPDC_PWRCTRL0__SD4_RESET 0x0e4 0x3d4 0x000 0x6 0x0 | ||
| 295 | #define MX6SL_PAD_EPDC_PWRCTRL1__EPDC_PWR_CTRL1 0x0e8 0x3d8 0x000 0x0 0x0 | ||
| 296 | #define MX6SL_PAD_EPDC_PWRCTRL1__AUD5_TXFS 0x0e8 0x3d8 0x610 0x1 0x0 | ||
| 297 | #define MX6SL_PAD_EPDC_PWRCTRL1__LCD_DATA17 0x0e8 0x3d8 0x7bc 0x2 0x0 | ||
| 298 | #define MX6SL_PAD_EPDC_PWRCTRL1__EIM_OE_B 0x0e8 0x3d8 0x000 0x3 0x0 | ||
| 299 | #define MX6SL_PAD_EPDC_PWRCTRL1__SPDC_YOEL 0x0e8 0x3d8 0x000 0x4 0x0 | ||
| 300 | #define MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x0e8 0x3d8 0x000 0x5 0x0 | ||
| 301 | #define MX6SL_PAD_EPDC_PWRCTRL1__SD4_VSELECT 0x0e8 0x3d8 0x000 0x6 0x0 | ||
| 302 | #define MX6SL_PAD_EPDC_PWRCTRL2__EPDC_PWR_CTRL2 0x0ec 0x3dc 0x000 0x0 0x0 | ||
| 303 | #define MX6SL_PAD_EPDC_PWRCTRL2__AUD5_TXD 0x0ec 0x3dc 0x600 0x1 0x0 | ||
| 304 | #define MX6SL_PAD_EPDC_PWRCTRL2__LCD_DATA18 0x0ec 0x3dc 0x7c0 0x2 0x0 | ||
| 305 | #define MX6SL_PAD_EPDC_PWRCTRL2__EIM_CS0_B 0x0ec 0x3dc 0x000 0x3 0x0 | ||
| 306 | #define MX6SL_PAD_EPDC_PWRCTRL2__SPDC_YDIOUL 0x0ec 0x3dc 0x000 0x4 0x0 | ||
| 307 | #define MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x0ec 0x3dc 0x000 0x5 0x0 | ||
| 308 | #define MX6SL_PAD_EPDC_PWRCTRL2__SD4_WP 0x0ec 0x3dc 0x87c 0x6 0x1 | ||
| 309 | #define MX6SL_PAD_EPDC_PWRCTRL3__EPDC_PWR_CTRL3 0x0f0 0x3e0 0x000 0x0 0x0 | ||
| 310 | #define MX6SL_PAD_EPDC_PWRCTRL3__AUD5_TXC 0x0f0 0x3e0 0x60c 0x1 0x0 | ||
| 311 | #define MX6SL_PAD_EPDC_PWRCTRL3__LCD_DATA19 0x0f0 0x3e0 0x7c4 0x2 0x0 | ||
| 312 | #define MX6SL_PAD_EPDC_PWRCTRL3__EIM_CS1_B 0x0f0 0x3e0 0x000 0x3 0x0 | ||
| 313 | #define MX6SL_PAD_EPDC_PWRCTRL3__SPDC_YDIODL 0x0f0 0x3e0 0x000 0x4 0x0 | ||
| 314 | #define MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x0f0 0x3e0 0x000 0x5 0x0 | ||
| 315 | #define MX6SL_PAD_EPDC_PWRCTRL3__SD4_CD_B 0x0f0 0x3e0 0x854 0x6 0x1 | ||
| 316 | #define MX6SL_PAD_EPDC_PWRINT__EPDC_PWR_IRQ 0x0f4 0x3e4 0x6e8 0x0 0x1 | ||
| 317 | #define MX6SL_PAD_EPDC_PWRINT__SD4_DATA1 0x0f4 0x3e4 0x860 0x1 0x0 | ||
| 318 | #define MX6SL_PAD_EPDC_PWRINT__LCD_DATA21 0x0f4 0x3e4 0x7cc 0x2 0x0 | ||
| 319 | #define MX6SL_PAD_EPDC_PWRINT__EIM_ACLK_FREERUN 0x0f4 0x3e4 0x000 0x3 0x0 | ||
| 320 | #define MX6SL_PAD_EPDC_PWRINT__USB_OTG2_ID 0x0f4 0x3e4 0x5e0 0x4 0x0 | ||
| 321 | #define MX6SL_PAD_EPDC_PWRINT__GPIO2_IO12 0x0f4 0x3e4 0x000 0x5 0x0 | ||
| 322 | #define MX6SL_PAD_EPDC_PWRINT__SD3_VSELECT 0x0f4 0x3e4 0x000 0x6 0x0 | ||
| 323 | #define MX6SL_PAD_EPDC_PWRSTAT__EPDC_PWR_STAT 0x0f8 0x3e8 0x6ec 0x0 0x1 | ||
| 324 | #define MX6SL_PAD_EPDC_PWRSTAT__SD4_DATA2 0x0f8 0x3e8 0x864 0x1 0x0 | ||
| 325 | #define MX6SL_PAD_EPDC_PWRSTAT__LCD_DATA22 0x0f8 0x3e8 0x7d0 0x2 0x0 | ||
| 326 | #define MX6SL_PAD_EPDC_PWRSTAT__EIM_WAIT_B 0x0f8 0x3e8 0x884 0x3 0x0 | ||
| 327 | #define MX6SL_PAD_EPDC_PWRSTAT__ARM_EVENTI 0x0f8 0x3e8 0x000 0x4 0x0 | ||
| 328 | #define MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x0f8 0x3e8 0x000 0x5 0x0 | ||
| 329 | #define MX6SL_PAD_EPDC_PWRSTAT__SD3_WP 0x0f8 0x3e8 0x84c 0x6 0x0 | ||
| 330 | #define MX6SL_PAD_EPDC_PWRWAKEUP__EPDC_PWR_WAKE 0x0fc 0x3ec 0x000 0x0 0x0 | ||
| 331 | #define MX6SL_PAD_EPDC_PWRWAKEUP__SD4_DATA3 0x0fc 0x3ec 0x868 0x1 0x0 | ||
| 332 | #define MX6SL_PAD_EPDC_PWRWAKEUP__LCD_DATA23 0x0fc 0x3ec 0x7d4 0x2 0x0 | ||
| 333 | #define MX6SL_PAD_EPDC_PWRWAKEUP__EIM_DTACK_B 0x0fc 0x3ec 0x880 0x3 0x0 | ||
| 334 | #define MX6SL_PAD_EPDC_PWRWAKEUP__ARM_EVENTO 0x0fc 0x3ec 0x000 0x4 0x0 | ||
| 335 | #define MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x0fc 0x3ec 0x000 0x5 0x0 | ||
| 336 | #define MX6SL_PAD_EPDC_PWRWAKEUP__SD3_CD_B 0x0fc 0x3ec 0x838 0x6 0x0 | ||
| 337 | #define MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100 0x3f0 0x000 0x0 0x0 | ||
| 338 | #define MX6SL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x100 0x3f0 0x6ac 0x1 0x0 | ||
| 339 | #define MX6SL_PAD_EPDC_SDCE0__PWM3_OUT 0x100 0x3f0 0x000 0x2 0x0 | ||
| 340 | #define MX6SL_PAD_EPDC_SDCE0__EIM_CS2_B 0x100 0x3f0 0x000 0x3 0x0 | ||
| 341 | #define MX6SL_PAD_EPDC_SDCE0__SPDC_YCKR 0x100 0x3f0 0x000 0x4 0x0 | ||
| 342 | #define MX6SL_PAD_EPDC_SDCE0__GPIO1_IO27 0x100 0x3f0 0x000 0x5 0x0 | ||
| 343 | #define MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x104 0x3f4 0x000 0x0 0x0 | ||
| 344 | #define MX6SL_PAD_EPDC_SDCE1__WDOG2_B 0x104 0x3f4 0x000 0x1 0x0 | ||
| 345 | #define MX6SL_PAD_EPDC_SDCE1__PWM4_OUT 0x104 0x3f4 0x000 0x2 0x0 | ||
| 346 | #define MX6SL_PAD_EPDC_SDCE1__EIM_LBA_B 0x104 0x3f4 0x000 0x3 0x0 | ||
| 347 | #define MX6SL_PAD_EPDC_SDCE1__SPDC_YOER 0x104 0x3f4 0x000 0x4 0x0 | ||
| 348 | #define MX6SL_PAD_EPDC_SDCE1__GPIO1_IO28 0x104 0x3f4 0x000 0x5 0x0 | ||
| 349 | #define MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x108 0x3f8 0x000 0x0 0x0 | ||
| 350 | #define MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x108 0x3f8 0x72c 0x1 0x1 | ||
| 351 | #define MX6SL_PAD_EPDC_SDCE2__PWM1_OUT 0x108 0x3f8 0x000 0x2 0x0 | ||
| 352 | #define MX6SL_PAD_EPDC_SDCE2__EIM_EB0_B 0x108 0x3f8 0x000 0x3 0x0 | ||
| 353 | #define MX6SL_PAD_EPDC_SDCE2__SPDC_YDIOUR 0x108 0x3f8 0x000 0x4 0x0 | ||
| 354 | #define MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x108 0x3f8 0x000 0x5 0x0 | ||
| 355 | #define MX6SL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x10c 0x3fc 0x000 0x0 0x0 | ||
| 356 | #define MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x10c 0x3fc 0x730 0x1 0x1 | ||
| 357 | #define MX6SL_PAD_EPDC_SDCE3__PWM2_OUT 0x10c 0x3fc 0x000 0x2 0x0 | ||
| 358 | #define MX6SL_PAD_EPDC_SDCE3__EIM_EB1_B 0x10c 0x3fc 0x000 0x3 0x0 | ||
| 359 | #define MX6SL_PAD_EPDC_SDCE3__SPDC_YDIODR 0x10c 0x3fc 0x000 0x4 0x0 | ||
| 360 | #define MX6SL_PAD_EPDC_SDCE3__GPIO1_IO30 0x10c 0x3fc 0x000 0x5 0x0 | ||
| 361 | #define MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x110 0x400 0x000 0x0 0x0 | ||
| 362 | #define MX6SL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x110 0x400 0x6a4 0x1 0x1 | ||
| 363 | #define MX6SL_PAD_EPDC_SDCLK__I2C2_SCL 0x110 0x400 0x724 0x2 0x0 | ||
| 364 | #define MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110 0x400 0x650 0x3 0x0 | ||
| 365 | #define MX6SL_PAD_EPDC_SDCLK__SPDC_CL 0x110 0x400 0x000 0x4 0x0 | ||
| 366 | #define MX6SL_PAD_EPDC_SDCLK__GPIO1_IO23 0x110 0x400 0x000 0x5 0x0 | ||
| 367 | #define MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x114 0x404 0x000 0x0 0x0 | ||
| 368 | #define MX6SL_PAD_EPDC_SDLE__ECSPI2_MISO 0x114 0x404 0x6a0 0x1 0x1 | ||
| 369 | #define MX6SL_PAD_EPDC_SDLE__I2C2_SDA 0x114 0x404 0x728 0x2 0x0 | ||
| 370 | #define MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x114 0x404 0x654 0x3 0x0 | ||
| 371 | #define MX6SL_PAD_EPDC_SDLE__SPDC_LD 0x114 0x404 0x000 0x4 0x0 | ||
| 372 | #define MX6SL_PAD_EPDC_SDLE__GPIO1_IO24 0x114 0x404 0x000 0x5 0x0 | ||
| 373 | #define MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x118 0x408 0x000 0x0 0x0 | ||
| 374 | #define MX6SL_PAD_EPDC_SDOE__ECSPI2_SS0 0x118 0x408 0x6a8 0x1 0x1 | ||
| 375 | #define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOR 0x118 0x408 0x000 0x2 0x0 | ||
| 376 | #define MX6SL_PAD_EPDC_SDOE__CSI_DATA10 0x118 0x408 0x658 0x3 0x0 | ||
| 377 | #define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOL 0x118 0x408 0x000 0x4 0x0 | ||
| 378 | #define MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x118 0x408 0x000 0x5 0x0 | ||
| 379 | #define MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x11c 0x40c 0x000 0x0 0x0 | ||
| 380 | #define MX6SL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x11c 0x40c 0x69c 0x1 0x1 | ||
| 381 | #define MX6SL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x11c 0x40c 0x000 0x2 0x0 | ||
| 382 | #define MX6SL_PAD_EPDC_SDSHR__CSI_DATA11 0x11c 0x40c 0x65c 0x3 0x0 | ||
| 383 | #define MX6SL_PAD_EPDC_SDSHR__SPDC_XDIOR 0x11c 0x40c 0x000 0x4 0x0 | ||
| 384 | #define MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x11c 0x40c 0x000 0x5 0x0 | ||
| 385 | #define MX6SL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x120 0x410 0x000 0x0 0x0 | ||
| 386 | #define MX6SL_PAD_EPDC_VCOM0__AUD5_RXFS 0x120 0x410 0x608 0x1 0x0 | ||
| 387 | #define MX6SL_PAD_EPDC_VCOM0__UART3_RX_DATA 0x120 0x410 0x80c 0x2 0x4 | ||
| 388 | #define MX6SL_PAD_EPDC_VCOM0__UART3_TX_DATA 0x120 0x410 0x000 0x2 0x0 | ||
| 389 | #define MX6SL_PAD_EPDC_VCOM0__EIM_ADDR24 0x120 0x410 0x000 0x3 0x0 | ||
| 390 | #define MX6SL_PAD_EPDC_VCOM0__SPDC_VCOM0 0x120 0x410 0x000 0x4 0x0 | ||
| 391 | #define MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x120 0x410 0x000 0x5 0x0 | ||
| 392 | #define MX6SL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x120 0x410 0x000 0x6 0x0 | ||
| 393 | #define MX6SL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x124 0x414 0x000 0x0 0x0 | ||
| 394 | #define MX6SL_PAD_EPDC_VCOM1__AUD5_RXD 0x124 0x414 0x5fc 0x1 0x0 | ||
| 395 | #define MX6SL_PAD_EPDC_VCOM1__UART3_TX_DATA 0x124 0x414 0x000 0x2 0x0 | ||
| 396 | #define MX6SL_PAD_EPDC_VCOM1__UART3_RX_DATA 0x124 0x414 0x80c 0x2 0x5 | ||
| 397 | #define MX6SL_PAD_EPDC_VCOM1__EIM_ADDR25 0x124 0x414 0x000 0x3 0x0 | ||
| 398 | #define MX6SL_PAD_EPDC_VCOM1__SPDC_VCOM1 0x124 0x414 0x000 0x4 0x0 | ||
| 399 | #define MX6SL_PAD_EPDC_VCOM1__GPIO2_IO04 0x124 0x414 0x000 0x5 0x0 | ||
| 400 | #define MX6SL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x124 0x414 0x000 0x6 0x0 | ||
| 401 | #define MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x128 0x418 0x704 0x0 0x1 | ||
| 402 | #define MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x128 0x418 0x860 0x1 0x1 | ||
| 403 | #define MX6SL_PAD_FEC_CRS_DV__AUD6_TXC 0x128 0x418 0x624 0x2 0x0 | ||
| 404 | #define MX6SL_PAD_FEC_CRS_DV__ECSPI4_MISO 0x128 0x418 0x6d4 0x3 0x1 | ||
| 405 | #define MX6SL_PAD_FEC_CRS_DV__GPT_COMPARE2 0x128 0x418 0x000 0x4 0x0 | ||
| 406 | #define MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x128 0x418 0x000 0x5 0x0 | ||
| 407 | #define MX6SL_PAD_FEC_CRS_DV__ARM_TRACE31 0x128 0x418 0x000 0x6 0x0 | ||
| 408 | #define MX6SL_PAD_FEC_MDC__FEC_MDC 0x12c 0x41c 0x000 0x0 0x0 | ||
| 409 | #define MX6SL_PAD_FEC_MDC__SD4_DATA4 0x12c 0x41c 0x86c 0x1 0x0 | ||
| 410 | #define MX6SL_PAD_FEC_MDC__AUDIO_CLK_OUT 0x12c 0x41c 0x000 0x2 0x0 | ||
| 411 | #define MX6SL_PAD_FEC_MDC__SD1_RESET 0x12c 0x41c 0x000 0x3 0x0 | ||
| 412 | #define MX6SL_PAD_FEC_MDC__SD3_RESET 0x12c 0x41c 0x000 0x4 0x0 | ||
| 413 | #define MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x12c 0x41c 0x000 0x5 0x0 | ||
| 414 | #define MX6SL_PAD_FEC_MDC__ARM_TRACE29 0x12c 0x41c 0x000 0x6 0x0 | ||
| 415 | #define MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x130 0x420 0x6f4 0x0 0x1 | ||
| 416 | #define MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130 0x420 0x850 0x1 0x1 | ||
| 417 | #define MX6SL_PAD_FEC_MDIO__AUD6_RXFS 0x130 0x420 0x620 0x2 0x0 | ||
| 418 | #define MX6SL_PAD_FEC_MDIO__ECSPI4_SS0 0x130 0x420 0x6dc 0x3 0x1 | ||
| 419 | #define MX6SL_PAD_FEC_MDIO__GPT_CAPTURE1 0x130 0x420 0x710 0x4 0x0 | ||
| 420 | #define MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x130 0x420 0x000 0x5 0x0 | ||
| 421 | #define MX6SL_PAD_FEC_MDIO__ARM_TRACE26 0x130 0x420 0x000 0x6 0x0 | ||
| 422 | #define MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x134 0x424 0x000 0x0 0x0 | ||
| 423 | #define MX6SL_PAD_FEC_REF_CLK__SD4_RESET 0x134 0x424 0x000 0x1 0x0 | ||
| 424 | #define MX6SL_PAD_FEC_REF_CLK__WDOG1_B 0x134 0x424 0x000 0x2 0x0 | ||
| 425 | #define MX6SL_PAD_FEC_REF_CLK__PWM4_OUT 0x134 0x424 0x000 0x3 0x0 | ||
| 426 | #define MX6SL_PAD_FEC_REF_CLK__CCM_PMIC_READY 0x134 0x424 0x62c 0x4 0x0 | ||
| 427 | #define MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x134 0x424 0x000 0x5 0x0 | ||
| 428 | #define MX6SL_PAD_FEC_REF_CLK__SPDIF_EXT_CLK 0x134 0x424 0x7f4 0x6 0x2 | ||
| 429 | #define MX6SL_PAD_FEC_RX_ER__FEC_RX_ER 0x138 0x428 0x708 0x0 0x1 | ||
| 430 | #define MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x138 0x428 0x85c 0x1 0x1 | ||
| 431 | #define MX6SL_PAD_FEC_RX_ER__AUD6_RXD 0x138 0x428 0x614 0x2 0x0 | ||
| 432 | #define MX6SL_PAD_FEC_RX_ER__ECSPI4_MOSI 0x138 0x428 0x6d8 0x3 0x1 | ||
| 433 | #define MX6SL_PAD_FEC_RX_ER__GPT_COMPARE1 0x138 0x428 0x000 0x4 0x0 | ||
| 434 | #define MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x138 0x428 0x000 0x5 0x0 | ||
| 435 | #define MX6SL_PAD_FEC_RX_ER__ARM_TRACE25 0x138 0x428 0x000 0x6 0x0 | ||
| 436 | #define MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x13c 0x42c 0x6f8 0x0 0x0 | ||
| 437 | #define MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x13c 0x42c 0x870 0x1 0x0 | ||
| 438 | #define MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x13c 0x42c 0x5dc 0x2 0x1 | ||
| 439 | #define MX6SL_PAD_FEC_RXD0__SD1_VSELECT 0x13c 0x42c 0x000 0x3 0x0 | ||
| 440 | #define MX6SL_PAD_FEC_RXD0__SD3_VSELECT 0x13c 0x42c 0x000 0x4 0x0 | ||
| 441 | #define MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x13c 0x42c 0x000 0x5 0x0 | ||
| 442 | #define MX6SL_PAD_FEC_RXD0__ARM_TRACE24 0x13c 0x42c 0x000 0x6 0x0 | ||
| 443 | #define MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x140 0x430 0x6fc 0x0 0x1 | ||
| 444 | #define MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x140 0x430 0x864 0x1 0x1 | ||
| 445 | #define MX6SL_PAD_FEC_RXD1__AUD6_TXFS 0x140 0x430 0x628 0x2 0x0 | ||
| 446 | #define MX6SL_PAD_FEC_RXD1__ECSPI4_SS1 0x140 0x430 0x6e0 0x3 0x1 | ||
| 447 | #define MX6SL_PAD_FEC_RXD1__GPT_COMPARE3 0x140 0x430 0x000 0x4 0x0 | ||
| 448 | #define MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x140 0x430 0x000 0x5 0x0 | ||
| 449 | #define MX6SL_PAD_FEC_RXD1__FEC_COL 0x140 0x430 0x6f0 0x6 0x0 | ||
| 450 | #define MX6SL_PAD_FEC_TX_CLK__FEC_TX_CLK 0x144 0x434 0x70c 0x0 0x1 | ||
| 451 | #define MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x144 0x434 0x858 0x1 0x1 | ||
| 452 | #define MX6SL_PAD_FEC_TX_CLK__AUD6_RXC 0x144 0x434 0x61c 0x2 0x0 | ||
| 453 | #define MX6SL_PAD_FEC_TX_CLK__ECSPI4_SCLK 0x144 0x434 0x6d0 0x3 0x1 | ||
| 454 | #define MX6SL_PAD_FEC_TX_CLK__GPT_CAPTURE2 0x144 0x434 0x714 0x4 0x0 | ||
| 455 | #define MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x144 0x434 0x000 0x5 0x0 | ||
| 456 | #define MX6SL_PAD_FEC_TX_CLK__ARM_TRACE27 0x144 0x434 0x000 0x6 0x0 | ||
| 457 | #define MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x148 0x438 0x000 0x0 0x0 | ||
| 458 | #define MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x148 0x438 0x874 0x1 0x0 | ||
| 459 | #define MX6SL_PAD_FEC_TX_EN__SPDIF_IN 0x148 0x438 0x7f0 0x2 0x0 | ||
| 460 | #define MX6SL_PAD_FEC_TX_EN__SD1_WP 0x148 0x438 0x82c 0x3 0x1 | ||
| 461 | #define MX6SL_PAD_FEC_TX_EN__SD3_WP 0x148 0x438 0x84c 0x4 0x1 | ||
| 462 | #define MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x148 0x438 0x000 0x5 0x0 | ||
| 463 | #define MX6SL_PAD_FEC_TX_EN__ARM_TRACE28 0x148 0x438 0x000 0x6 0x0 | ||
| 464 | #define MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x14c 0x43c 0x000 0x0 0x0 | ||
| 465 | #define MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x14c 0x43c 0x868 0x1 0x1 | ||
| 466 | #define MX6SL_PAD_FEC_TXD0__AUD6_TXD 0x14c 0x43c 0x618 0x2 0x0 | ||
| 467 | #define MX6SL_PAD_FEC_TXD0__ECSPI4_SS2 0x14c 0x43c 0x6e4 0x3 0x1 | ||
| 468 | #define MX6SL_PAD_FEC_TXD0__GPT_CLKIN 0x14c 0x43c 0x718 0x4 0x0 | ||
| 469 | #define MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x14c 0x43c 0x000 0x5 0x0 | ||
| 470 | #define MX6SL_PAD_FEC_TXD0__ARM_TRACE30 0x14c 0x43c 0x000 0x6 0x0 | ||
| 471 | #define MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x150 0x440 0x000 0x0 0x0 | ||
| 472 | #define MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x150 0x440 0x878 0x1 0x0 | ||
| 473 | #define MX6SL_PAD_FEC_TXD1__SPDIF_OUT 0x150 0x440 0x000 0x2 0x0 | ||
| 474 | #define MX6SL_PAD_FEC_TXD1__SD1_CD_B 0x150 0x440 0x828 0x3 0x1 | ||
| 475 | #define MX6SL_PAD_FEC_TXD1__SD3_CD_B 0x150 0x440 0x838 0x4 0x1 | ||
| 476 | #define MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x150 0x440 0x000 0x5 0x0 | ||
| 477 | #define MX6SL_PAD_FEC_TXD1__FEC_RX_CLK 0x150 0x440 0x700 0x6 0x0 | ||
| 478 | #define MX6SL_PAD_HSIC_DAT__USB_H_DATA 0x154 0x444 0x000 0x0 0x0 | ||
| 479 | #define MX6SL_PAD_HSIC_DAT__I2C1_SCL 0x154 0x444 0x71c 0x1 0x1 | ||
| 480 | #define MX6SL_PAD_HSIC_DAT__PWM1_OUT 0x154 0x444 0x000 0x2 0x0 | ||
| 481 | #define MX6SL_PAD_HSIC_DAT__XTALOSC_REF_CLK_24M 0x154 0x444 0x000 0x3 0x0 | ||
| 482 | #define MX6SL_PAD_HSIC_DAT__GPIO3_IO19 0x154 0x444 0x000 0x5 0x0 | ||
| 483 | #define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE 0x158 0x448 0x000 0x0 0x0 | ||
| 484 | #define MX6SL_PAD_HSIC_STROBE__I2C1_SDA 0x158 0x448 0x720 0x1 0x1 | ||
| 485 | #define MX6SL_PAD_HSIC_STROBE__PWM2_OUT 0x158 0x448 0x000 0x2 0x0 | ||
| 486 | #define MX6SL_PAD_HSIC_STROBE__XTALOSC_REF_CLK_32K 0x158 0x448 0x000 0x3 0x0 | ||
| 487 | #define MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x158 0x448 0x000 0x5 0x0 | ||
| 488 | #define MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x15c 0x44c 0x71c 0x0 0x2 | ||
| 489 | #define MX6SL_PAD_I2C1_SCL__UART1_RTS_B 0x15c 0x44c 0x7f8 0x1 0x0 | ||
| 490 | #define MX6SL_PAD_I2C1_SCL__UART1_CTS_B 0x15c 0x44c 0x000 0x1 0x0 | ||
| 491 | #define MX6SL_PAD_I2C1_SCL__ECSPI3_SS2 0x15c 0x44c 0x6c8 0x2 0x1 | ||
| 492 | #define MX6SL_PAD_I2C1_SCL__FEC_RX_DATA0 0x15c 0x44c 0x6f8 0x3 0x1 | ||
| 493 | #define MX6SL_PAD_I2C1_SCL__SD3_RESET 0x15c 0x44c 0x000 0x4 0x0 | ||
| 494 | #define MX6SL_PAD_I2C1_SCL__GPIO3_IO12 0x15c 0x44c 0x000 0x5 0x0 | ||
| 495 | #define MX6SL_PAD_I2C1_SCL__ECSPI1_SS1 0x15c 0x44c 0x690 0x6 0x0 | ||
| 496 | #define MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x160 0x450 0x720 0x0 0x2 | ||
| 497 | #define MX6SL_PAD_I2C1_SDA__UART1_CTS_B 0x160 0x450 0x000 0x1 0x0 | ||
| 498 | #define MX6SL_PAD_I2C1_SDA__UART1_RTS_B 0x160 0x450 0x7f8 0x1 0x1 | ||
| 499 | #define MX6SL_PAD_I2C1_SDA__ECSPI3_SS3 0x160 0x450 0x6cc 0x2 0x1 | ||
| 500 | #define MX6SL_PAD_I2C1_SDA__FEC_TX_EN 0x160 0x450 0x000 0x3 0x0 | ||
| 501 | #define MX6SL_PAD_I2C1_SDA__SD3_VSELECT 0x160 0x450 0x000 0x4 0x0 | ||
| 502 | #define MX6SL_PAD_I2C1_SDA__GPIO3_IO13 0x160 0x450 0x000 0x5 0x0 | ||
| 503 | #define MX6SL_PAD_I2C1_SDA__ECSPI1_SS2 0x160 0x450 0x694 0x6 0x0 | ||
| 504 | #define MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x164 0x454 0x724 0x0 0x1 | ||
| 505 | #define MX6SL_PAD_I2C2_SCL__AUD4_RXFS 0x164 0x454 0x5f0 0x1 0x0 | ||
| 506 | #define MX6SL_PAD_I2C2_SCL__SPDIF_IN 0x164 0x454 0x7f0 0x2 0x1 | ||
| 507 | #define MX6SL_PAD_I2C2_SCL__FEC_TX_DATA1 0x164 0x454 0x000 0x3 0x0 | ||
| 508 | #define MX6SL_PAD_I2C2_SCL__SD3_WP 0x164 0x454 0x84c 0x4 0x2 | ||
| 509 | #define MX6SL_PAD_I2C2_SCL__GPIO3_IO14 0x164 0x454 0x000 0x5 0x0 | ||
| 510 | #define MX6SL_PAD_I2C2_SCL__ECSPI1_RDY 0x164 0x454 0x680 0x6 0x0 | ||
| 511 | #define MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x168 0x458 0x728 0x0 0x1 | ||
| 512 | #define MX6SL_PAD_I2C2_SDA__AUD4_RXC 0x168 0x458 0x5ec 0x1 0x0 | ||
| 513 | #define MX6SL_PAD_I2C2_SDA__SPDIF_OUT 0x168 0x458 0x000 0x2 0x0 | ||
| 514 | #define MX6SL_PAD_I2C2_SDA__FEC_REF_OUT 0x168 0x458 0x000 0x3 0x0 | ||
| 515 | #define MX6SL_PAD_I2C2_SDA__SD3_CD_B 0x168 0x458 0x838 0x4 0x2 | ||
| 516 | #define MX6SL_PAD_I2C2_SDA__GPIO3_IO15 0x168 0x458 0x000 0x5 0x0 | ||
| 517 | #define MX6SL_PAD_KEY_COL0__KEY_COL0 0x16c 0x474 0x734 0x0 0x0 | ||
| 518 | #define MX6SL_PAD_KEY_COL0__I2C2_SCL 0x16c 0x474 0x724 0x1 0x2 | ||
| 519 | #define MX6SL_PAD_KEY_COL0__LCD_DATA00 0x16c 0x474 0x778 0x2 0x0 | ||
| 520 | #define MX6SL_PAD_KEY_COL0__EIM_AD00 0x16c 0x474 0x000 0x3 0x0 | ||
| 521 | #define MX6SL_PAD_KEY_COL0__SD1_CD_B 0x16c 0x474 0x828 0x4 0x2 | ||
| 522 | #define MX6SL_PAD_KEY_COL0__GPIO3_IO24 0x16c 0x474 0x000 0x5 0x0 | ||
| 523 | #define MX6SL_PAD_KEY_COL1__KEY_COL1 0x170 0x478 0x738 0x0 0x0 | ||
| 524 | #define MX6SL_PAD_KEY_COL1__ECSPI4_MOSI 0x170 0x478 0x6d8 0x1 0x2 | ||
| 525 | #define MX6SL_PAD_KEY_COL1__LCD_DATA02 0x170 0x478 0x780 0x2 0x0 | ||
| 526 | #define MX6SL_PAD_KEY_COL1__EIM_AD02 0x170 0x478 0x000 0x3 0x0 | ||
| 527 | #define MX6SL_PAD_KEY_COL1__SD3_DATA4 0x170 0x478 0x83c 0x4 0x0 | ||
| 528 | #define MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x170 0x478 0x000 0x5 0x0 | ||
| 529 | #define MX6SL_PAD_KEY_COL2__KEY_COL2 0x174 0x47c 0x73c 0x0 0x0 | ||
| 530 | #define MX6SL_PAD_KEY_COL2__ECSPI4_SS0 0x174 0x47c 0x6dc 0x1 0x2 | ||
| 531 | #define MX6SL_PAD_KEY_COL2__LCD_DATA04 0x174 0x47c 0x788 0x2 0x0 | ||
| 532 | #define MX6SL_PAD_KEY_COL2__EIM_AD04 0x174 0x47c 0x000 0x3 0x0 | ||
| 533 | #define MX6SL_PAD_KEY_COL2__SD3_DATA6 0x174 0x47c 0x844 0x4 0x0 | ||
| 534 | #define MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x174 0x47c 0x000 0x5 0x0 | ||
| 535 | #define MX6SL_PAD_KEY_COL3__KEY_COL3 0x178 0x480 0x740 0x0 0x0 | ||
| 536 | #define MX6SL_PAD_KEY_COL3__AUD6_RXFS 0x178 0x480 0x620 0x1 0x1 | ||
| 537 | #define MX6SL_PAD_KEY_COL3__LCD_DATA06 0x178 0x480 0x790 0x2 0x0 | ||
| 538 | #define MX6SL_PAD_KEY_COL3__EIM_AD06 0x178 0x480 0x000 0x3 0x0 | ||
| 539 | #define MX6SL_PAD_KEY_COL3__SD4_DATA6 0x178 0x480 0x874 0x4 0x1 | ||
| 540 | #define MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x178 0x480 0x000 0x5 0x0 | ||
| 541 | #define MX6SL_PAD_KEY_COL3__SD1_RESET 0x178 0x480 0x000 0x6 0x0 | ||
| 542 | #define MX6SL_PAD_KEY_COL4__KEY_COL4 0x17c 0x484 0x744 0x0 0x0 | ||
| 543 | #define MX6SL_PAD_KEY_COL4__AUD6_RXD 0x17c 0x484 0x614 0x1 0x1 | ||
| 544 | #define MX6SL_PAD_KEY_COL4__LCD_DATA08 0x17c 0x484 0x798 0x2 0x0 | ||
| 545 | #define MX6SL_PAD_KEY_COL4__EIM_AD08 0x17c 0x484 0x000 0x3 0x0 | ||
| 546 | #define MX6SL_PAD_KEY_COL4__SD4_CLK 0x17c 0x484 0x850 0x4 0x2 | ||
| 547 | #define MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x17c 0x484 0x000 0x5 0x0 | ||
| 548 | #define MX6SL_PAD_KEY_COL4__USB_OTG1_PWR 0x17c 0x484 0x000 0x6 0x0 | ||
| 549 | #define MX6SL_PAD_KEY_COL5__KEY_COL5 0x180 0x488 0x748 0x0 0x0 | ||
| 550 | #define MX6SL_PAD_KEY_COL5__AUD6_TXFS 0x180 0x488 0x628 0x1 0x1 | ||
| 551 | #define MX6SL_PAD_KEY_COL5__LCD_DATA10 0x180 0x488 0x7a0 0x2 0x0 | ||
| 552 | #define MX6SL_PAD_KEY_COL5__EIM_AD10 0x180 0x488 0x000 0x3 0x0 | ||
| 553 | #define MX6SL_PAD_KEY_COL5__SD4_DATA0 0x180 0x488 0x85c 0x4 0x2 | ||
| 554 | #define MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x180 0x488 0x000 0x5 0x0 | ||
| 555 | #define MX6SL_PAD_KEY_COL5__USB_OTG2_PWR 0x180 0x488 0x000 0x6 0x0 | ||
| 556 | #define MX6SL_PAD_KEY_COL6__KEY_COL6 0x184 0x48c 0x74c 0x0 0x0 | ||
| 557 | #define MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x184 0x48c 0x814 0x1 0x2 | ||
| 558 | #define MX6SL_PAD_KEY_COL6__UART4_TX_DATA 0x184 0x48c 0x000 0x1 0x0 | ||
| 559 | #define MX6SL_PAD_KEY_COL6__LCD_DATA12 0x184 0x48c 0x7a8 0x2 0x0 | ||
| 560 | #define MX6SL_PAD_KEY_COL6__EIM_AD12 0x184 0x48c 0x000 0x3 0x0 | ||
| 561 | #define MX6SL_PAD_KEY_COL6__SD4_DATA2 0x184 0x48c 0x864 0x4 0x2 | ||
| 562 | #define MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x184 0x48c 0x000 0x5 0x0 | ||
| 563 | #define MX6SL_PAD_KEY_COL6__SD3_RESET 0x184 0x48c 0x000 0x6 0x0 | ||
| 564 | #define MX6SL_PAD_KEY_COL7__KEY_COL7 0x188 0x490 0x750 0x0 0x0 | ||
| 565 | #define MX6SL_PAD_KEY_COL7__UART4_RTS_B 0x188 0x490 0x810 0x1 0x2 | ||
| 566 | #define MX6SL_PAD_KEY_COL7__UART4_CTS_B 0x188 0x490 0x000 0x1 0x0 | ||
| 567 | #define MX6SL_PAD_KEY_COL7__LCD_DATA14 0x188 0x490 0x7b0 0x2 0x0 | ||
| 568 | #define MX6SL_PAD_KEY_COL7__EIM_AD14 0x188 0x490 0x000 0x3 0x0 | ||
| 569 | #define MX6SL_PAD_KEY_COL7__SD4_DATA4 0x188 0x490 0x86c 0x4 0x1 | ||
| 570 | #define MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x188 0x490 0x000 0x5 0x0 | ||
| 571 | #define MX6SL_PAD_KEY_COL7__SD1_WP 0x188 0x490 0x82c 0x6 0x2 | ||
| 572 | #define MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x18c 0x494 0x754 0x0 0x0 | ||
| 573 | #define MX6SL_PAD_KEY_ROW0__I2C2_SDA 0x18c 0x494 0x728 0x1 0x2 | ||
| 574 | #define MX6SL_PAD_KEY_ROW0__LCD_DATA01 0x18c 0x494 0x77c 0x2 0x0 | ||
| 575 | #define MX6SL_PAD_KEY_ROW0__EIM_AD01 0x18c 0x494 0x000 0x3 0x0 | ||
| 576 | #define MX6SL_PAD_KEY_ROW0__SD1_WP 0x18c 0x494 0x82c 0x4 0x3 | ||
| 577 | #define MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x18c 0x494 0x000 0x5 0x0 | ||
| 578 | #define MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x190 0x498 0x758 0x0 0x0 | ||
| 579 | #define MX6SL_PAD_KEY_ROW1__ECSPI4_MISO 0x190 0x498 0x6d4 0x1 0x2 | ||
| 580 | #define MX6SL_PAD_KEY_ROW1__LCD_DATA03 0x190 0x498 0x784 0x2 0x0 | ||
| 581 | #define MX6SL_PAD_KEY_ROW1__EIM_AD03 0x190 0x498 0x000 0x3 0x0 | ||
| 582 | #define MX6SL_PAD_KEY_ROW1__SD3_DATA5 0x190 0x498 0x840 0x4 0x0 | ||
| 583 | #define MX6SL_PAD_KEY_ROW1__GPIO3_IO27 0x190 0x498 0x000 0x5 0x0 | ||
| 584 | #define MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x194 0x49c 0x75c 0x0 0x0 | ||
| 585 | #define MX6SL_PAD_KEY_ROW2__ECSPI4_SCLK 0x194 0x49c 0x6d0 0x1 0x2 | ||
| 586 | #define MX6SL_PAD_KEY_ROW2__LCD_DATA05 0x194 0x49c 0x78c 0x2 0x0 | ||
| 587 | #define MX6SL_PAD_KEY_ROW2__EIM_AD05 0x194 0x49c 0x000 0x3 0x0 | ||
| 588 | #define MX6SL_PAD_KEY_ROW2__SD3_DATA7 0x194 0x49c 0x848 0x4 0x0 | ||
| 589 | #define MX6SL_PAD_KEY_ROW2__GPIO3_IO29 0x194 0x49c 0x000 0x5 0x0 | ||
| 590 | #define MX6SL_PAD_KEY_ROW3__KEY_ROW3 0x198 0x4a0 0x760 0x0 0x0 | ||
| 591 | #define MX6SL_PAD_KEY_ROW3__AUD6_RXC 0x198 0x4a0 0x61c 0x1 0x1 | ||
| 592 | #define MX6SL_PAD_KEY_ROW3__LCD_DATA07 0x198 0x4a0 0x794 0x2 0x0 | ||
| 593 | #define MX6SL_PAD_KEY_ROW3__EIM_AD07 0x198 0x4a0 0x000 0x3 0x0 | ||
| 594 | #define MX6SL_PAD_KEY_ROW3__SD4_DATA7 0x198 0x4a0 0x878 0x4 0x1 | ||
| 595 | #define MX6SL_PAD_KEY_ROW3__GPIO3_IO31 0x198 0x4a0 0x000 0x5 0x0 | ||
| 596 | #define MX6SL_PAD_KEY_ROW3__SD1_VSELECT 0x198 0x4a0 0x000 0x6 0x0 | ||
| 597 | #define MX6SL_PAD_KEY_ROW4__KEY_ROW4 0x19c 0x4a4 0x764 0x0 0x0 | ||
| 598 | #define MX6SL_PAD_KEY_ROW4__AUD6_TXC 0x19c 0x4a4 0x624 0x1 0x1 | ||
| 599 | #define MX6SL_PAD_KEY_ROW4__LCD_DATA09 0x19c 0x4a4 0x79c 0x2 0x0 | ||
| 600 | #define MX6SL_PAD_KEY_ROW4__EIM_AD09 0x19c 0x4a4 0x000 0x3 0x0 | ||
| 601 | #define MX6SL_PAD_KEY_ROW4__SD4_CMD 0x19c 0x4a4 0x858 0x4 0x2 | ||
| 602 | #define MX6SL_PAD_KEY_ROW4__GPIO4_IO01 0x19c 0x4a4 0x000 0x5 0x0 | ||
| 603 | #define MX6SL_PAD_KEY_ROW4__USB_OTG1_OC 0x19c 0x4a4 0x824 0x6 0x1 | ||
| 604 | #define MX6SL_PAD_KEY_ROW5__KEY_ROW5 0x1a0 0x4a8 0x768 0x0 0x0 | ||
| 605 | #define MX6SL_PAD_KEY_ROW5__AUD6_TXD 0x1a0 0x4a8 0x618 0x1 0x1 | ||
| 606 | #define MX6SL_PAD_KEY_ROW5__LCD_DATA11 0x1a0 0x4a8 0x7a4 0x2 0x0 | ||
| 607 | #define MX6SL_PAD_KEY_ROW5__EIM_AD11 0x1a0 0x4a8 0x000 0x3 0x0 | ||
| 608 | #define MX6SL_PAD_KEY_ROW5__SD4_DATA1 0x1a0 0x4a8 0x860 0x4 0x2 | ||
| 609 | #define MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x1a0 0x4a8 0x000 0x5 0x0 | ||
| 610 | #define MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x1a0 0x4a8 0x820 0x6 0x2 | ||
| 611 | #define MX6SL_PAD_KEY_ROW6__KEY_ROW6 0x1a4 0x4ac 0x76c 0x0 0x0 | ||
| 612 | #define MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1a4 0x4ac 0x000 0x1 0x0 | ||
| 613 | #define MX6SL_PAD_KEY_ROW6__UART4_RX_DATA 0x1a4 0x4ac 0x814 0x1 0x3 | ||
| 614 | #define MX6SL_PAD_KEY_ROW6__LCD_DATA13 0x1a4 0x4ac 0x7ac 0x2 0x0 | ||
| 615 | #define MX6SL_PAD_KEY_ROW6__EIM_AD13 0x1a4 0x4ac 0x000 0x3 0x0 | ||
| 616 | #define MX6SL_PAD_KEY_ROW6__SD4_DATA3 0x1a4 0x4ac 0x868 0x4 0x2 | ||
| 617 | #define MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x1a4 0x4ac 0x000 0x5 0x0 | ||
| 618 | #define MX6SL_PAD_KEY_ROW6__SD3_VSELECT 0x1a4 0x4ac 0x000 0x6 0x0 | ||
| 619 | #define MX6SL_PAD_KEY_ROW7__KEY_ROW7 0x1a8 0x4b0 0x770 0x0 0x0 | ||
| 620 | #define MX6SL_PAD_KEY_ROW7__UART4_CTS_B 0x1a8 0x4b0 0x000 0x1 0x0 | ||
| 621 | #define MX6SL_PAD_KEY_ROW7__UART4_RTS_B 0x1a8 0x4b0 0x810 0x1 0x3 | ||
| 622 | #define MX6SL_PAD_KEY_ROW7__LCD_DATA15 0x1a8 0x4b0 0x7b4 0x2 0x0 | ||
| 623 | #define MX6SL_PAD_KEY_ROW7__EIM_AD15 0x1a8 0x4b0 0x000 0x3 0x0 | ||
| 624 | #define MX6SL_PAD_KEY_ROW7__SD4_DATA5 0x1a8 0x4b0 0x870 0x4 0x1 | ||
| 625 | #define MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x1a8 0x4b0 0x000 0x5 0x0 | ||
| 626 | #define MX6SL_PAD_KEY_ROW7__SD1_CD_B 0x1a8 0x4b0 0x828 0x6 0x3 | ||
| 627 | #define MX6SL_PAD_LCD_CLK__LCD_CLK 0x1ac 0x4b4 0x000 0x0 0x0 | ||
| 628 | #define MX6SL_PAD_LCD_CLK__SD4_DATA4 0x1ac 0x4b4 0x86c 0x1 0x2 | ||
| 629 | #define MX6SL_PAD_LCD_CLK__LCD_WR_RWN 0x1ac 0x4b4 0x000 0x2 0x0 | ||
| 630 | #define MX6SL_PAD_LCD_CLK__EIM_RW 0x1ac 0x4b4 0x000 0x3 0x0 | ||
| 631 | #define MX6SL_PAD_LCD_CLK__PWM4_OUT 0x1ac 0x4b4 0x000 0x4 0x0 | ||
| 632 | #define MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x1ac 0x4b4 0x000 0x5 0x0 | ||
| 633 | #define MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0 0x4b8 0x778 0x0 0x1 | ||
| 634 | #define MX6SL_PAD_LCD_DAT0__ECSPI1_MOSI 0x1b0 0x4b8 0x688 0x1 0x1 | ||
| 635 | #define MX6SL_PAD_LCD_DAT0__USB_OTG2_ID 0x1b0 0x4b8 0x5e0 0x2 0x1 | ||
| 636 | #define MX6SL_PAD_LCD_DAT0__PWM1_OUT 0x1b0 0x4b8 0x000 0x3 0x0 | ||
| 637 | #define MX6SL_PAD_LCD_DAT0__UART5_DTR_B 0x1b0 0x4b8 0x000 0x4 0x0 | ||
| 638 | #define MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x1b0 0x4b8 0x000 0x5 0x0 | ||
| 639 | #define MX6SL_PAD_LCD_DAT0__ARM_TRACE00 0x1b0 0x4b8 0x000 0x6 0x0 | ||
| 640 | #define MX6SL_PAD_LCD_DAT0__SRC_BOOT_CFG00 0x1b0 0x4b8 0x000 0x7 0x0 | ||
| 641 | #define MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b4 0x4bc 0x77c 0x0 0x1 | ||
| 642 | #define MX6SL_PAD_LCD_DAT1__ECSPI1_MISO 0x1b4 0x4bc 0x684 0x1 0x1 | ||
| 643 | #define MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x1b4 0x4bc 0x5dc 0x2 0x2 | ||
| 644 | #define MX6SL_PAD_LCD_DAT1__PWM2_OUT 0x1b4 0x4bc 0x000 0x3 0x0 | ||
| 645 | #define MX6SL_PAD_LCD_DAT1__AUD4_RXFS 0x1b4 0x4bc 0x5f0 0x4 0x1 | ||
| 646 | #define MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x1b4 0x4bc 0x000 0x5 0x0 | ||
| 647 | #define MX6SL_PAD_LCD_DAT1__ARM_TRACE01 0x1b4 0x4bc 0x000 0x6 0x0 | ||
| 648 | #define MX6SL_PAD_LCD_DAT1__SRC_BOOT_CFG01 0x1b4 0x4bc 0x000 0x7 0x0 | ||
| 649 | #define MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b8 0x4c0 0x7a0 0x0 0x1 | ||
| 650 | #define MX6SL_PAD_LCD_DAT10__KEY_COL1 0x1b8 0x4c0 0x738 0x1 0x1 | ||
| 651 | #define MX6SL_PAD_LCD_DAT10__CSI_DATA07 0x1b8 0x4c0 0x64c 0x2 0x1 | ||
| 652 | #define MX6SL_PAD_LCD_DAT10__EIM_DATA04 0x1b8 0x4c0 0x000 0x3 0x0 | ||
| 653 | #define MX6SL_PAD_LCD_DAT10__ECSPI2_MISO 0x1b8 0x4c0 0x6a0 0x4 0x2 | ||
| 654 | #define MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x1b8 0x4c0 0x000 0x5 0x0 | ||
| 655 | #define MX6SL_PAD_LCD_DAT10__ARM_TRACE10 0x1b8 0x4c0 0x000 0x6 0x0 | ||
| 656 | #define MX6SL_PAD_LCD_DAT10__SRC_BOOT_CFG10 0x1b8 0x4c0 0x000 0x7 0x0 | ||
| 657 | #define MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1bc 0x4c4 0x7a4 0x0 0x1 | ||
| 658 | #define MX6SL_PAD_LCD_DAT11__KEY_ROW1 0x1bc 0x4c4 0x758 0x1 0x1 | ||
| 659 | #define MX6SL_PAD_LCD_DAT11__CSI_DATA06 0x1bc 0x4c4 0x648 0x2 0x1 | ||
| 660 | #define MX6SL_PAD_LCD_DAT11__EIM_DATA05 0x1bc 0x4c4 0x000 0x3 0x0 | ||
| 661 | #define MX6SL_PAD_LCD_DAT11__ECSPI2_SS1 0x1bc 0x4c4 0x6ac 0x4 0x1 | ||
| 662 | #define MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x1bc 0x4c4 0x000 0x5 0x0 | ||
| 663 | #define MX6SL_PAD_LCD_DAT11__ARM_TRACE11 0x1bc 0x4c4 0x000 0x6 0x0 | ||
| 664 | #define MX6SL_PAD_LCD_DAT11__SRC_BOOT_CFG11 0x1bc 0x4c4 0x000 0x7 0x0 | ||
| 665 | #define MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1c0 0x4c8 0x7a8 0x0 0x1 | ||
| 666 | #define MX6SL_PAD_LCD_DAT12__KEY_COL2 0x1c0 0x4c8 0x73c 0x1 0x1 | ||
| 667 | #define MX6SL_PAD_LCD_DAT12__CSI_DATA05 0x1c0 0x4c8 0x644 0x2 0x1 | ||
| 668 | #define MX6SL_PAD_LCD_DAT12__EIM_DATA06 0x1c0 0x4c8 0x000 0x3 0x0 | ||
| 669 | #define MX6SL_PAD_LCD_DAT12__UART5_RTS_B 0x1c0 0x4c8 0x818 0x4 0x2 | ||
| 670 | #define MX6SL_PAD_LCD_DAT12__UART5_CTS_B 0x1c0 0x4c8 0x000 0x4 0x0 | ||
| 671 | #define MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x1c0 0x4c8 0x000 0x5 0x0 | ||
| 672 | #define MX6SL_PAD_LCD_DAT12__ARM_TRACE12 0x1c0 0x4c8 0x000 0x6 0x0 | ||
| 673 | #define MX6SL_PAD_LCD_DAT12__SRC_BOOT_CFG12 0x1c0 0x4c8 0x000 0x7 0x0 | ||
| 674 | #define MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1c4 0x4cc 0x7ac 0x0 0x1 | ||
| 675 | #define MX6SL_PAD_LCD_DAT13__KEY_ROW2 0x1c4 0x4cc 0x75c 0x1 0x1 | ||
| 676 | #define MX6SL_PAD_LCD_DAT13__CSI_DATA04 0x1c4 0x4cc 0x640 0x2 0x1 | ||
| 677 | #define MX6SL_PAD_LCD_DAT13__EIM_DATA07 0x1c4 0x4cc 0x000 0x3 0x0 | ||
| 678 | #define MX6SL_PAD_LCD_DAT13__UART5_CTS_B 0x1c4 0x4cc 0x000 0x4 0x0 | ||
| 679 | #define MX6SL_PAD_LCD_DAT13__UART5_RTS_B 0x1c4 0x4cc 0x818 0x4 0x3 | ||
| 680 | #define MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x1c4 0x4cc 0x000 0x5 0x0 | ||
| 681 | #define MX6SL_PAD_LCD_DAT13__ARM_TRACE13 0x1c4 0x4cc 0x000 0x6 0x0 | ||
| 682 | #define MX6SL_PAD_LCD_DAT13__SRC_BOOT_CFG13 0x1c4 0x4cc 0x000 0x7 0x0 | ||
| 683 | #define MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1c8 0x4d0 0x7b0 0x0 0x1 | ||
| 684 | #define MX6SL_PAD_LCD_DAT14__KEY_COL3 0x1c8 0x4d0 0x740 0x1 0x1 | ||
| 685 | #define MX6SL_PAD_LCD_DAT14__CSI_DATA03 0x1c8 0x4d0 0x63c 0x2 0x1 | ||
| 686 | #define MX6SL_PAD_LCD_DAT14__EIM_DATA08 0x1c8 0x4d0 0x000 0x3 0x0 | ||
| 687 | #define MX6SL_PAD_LCD_DAT14__UART5_RX_DATA 0x1c8 0x4d0 0x81c 0x4 0x2 | ||
| 688 | #define MX6SL_PAD_LCD_DAT14__UART5_TX_DATA 0x1c8 0x4d0 0x000 0x4 0x0 | ||
| 689 | #define MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x1c8 0x4d0 0x000 0x5 0x0 | ||
| 690 | #define MX6SL_PAD_LCD_DAT14__ARM_TRACE14 0x1c8 0x4d0 0x000 0x6 0x0 | ||
| 691 | #define MX6SL_PAD_LCD_DAT14__SRC_BOOT_CFG14 0x1c8 0x4d0 0x000 0x7 0x0 | ||
| 692 | #define MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1cc 0x4d4 0x7b4 0x0 0x1 | ||
| 693 | #define MX6SL_PAD_LCD_DAT15__KEY_ROW3 0x1cc 0x4d4 0x760 0x1 0x1 | ||
| 694 | #define MX6SL_PAD_LCD_DAT15__CSI_DATA02 0x1cc 0x4d4 0x638 0x2 0x1 | ||
| 695 | #define MX6SL_PAD_LCD_DAT15__EIM_DATA09 0x1cc 0x4d4 0x000 0x3 0x0 | ||
| 696 | #define MX6SL_PAD_LCD_DAT15__UART5_TX_DATA 0x1cc 0x4d4 0x000 0x4 0x0 | ||
| 697 | #define MX6SL_PAD_LCD_DAT15__UART5_RX_DATA 0x1cc 0x4d4 0x81c 0x4 0x3 | ||
| 698 | #define MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x1cc 0x4d4 0x000 0x5 0x0 | ||
| 699 | #define MX6SL_PAD_LCD_DAT15__ARM_TRACE15 0x1cc 0x4d4 0x000 0x6 0x0 | ||
| 700 | #define MX6SL_PAD_LCD_DAT15__SRC_BOOT_CFG15 0x1cc 0x4d4 0x000 0x7 0x0 | ||
| 701 | #define MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1d0 0x4d8 0x7b8 0x0 0x1 | ||
| 702 | #define MX6SL_PAD_LCD_DAT16__KEY_COL4 0x1d0 0x4d8 0x744 0x1 0x1 | ||
| 703 | #define MX6SL_PAD_LCD_DAT16__CSI_DATA01 0x1d0 0x4d8 0x634 0x2 0x1 | ||
| 704 | #define MX6SL_PAD_LCD_DAT16__EIM_DATA10 0x1d0 0x4d8 0x000 0x3 0x0 | ||
| 705 | #define MX6SL_PAD_LCD_DAT16__I2C2_SCL 0x1d0 0x4d8 0x724 0x4 0x3 | ||
| 706 | #define MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x1d0 0x4d8 0x000 0x5 0x0 | ||
| 707 | #define MX6SL_PAD_LCD_DAT16__ARM_TRACE16 0x1d0 0x4d8 0x000 0x6 0x0 | ||
| 708 | #define MX6SL_PAD_LCD_DAT16__SRC_BOOT_CFG24 0x1d0 0x4d8 0x000 0x7 0x0 | ||
| 709 | #define MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1d4 0x4dc 0x7bc 0x0 0x1 | ||
| 710 | #define MX6SL_PAD_LCD_DAT17__KEY_ROW4 0x1d4 0x4dc 0x764 0x1 0x1 | ||
| 711 | #define MX6SL_PAD_LCD_DAT17__CSI_DATA00 0x1d4 0x4dc 0x630 0x2 0x1 | ||
| 712 | #define MX6SL_PAD_LCD_DAT17__EIM_DATA11 0x1d4 0x4dc 0x000 0x3 0x0 | ||
| 713 | #define MX6SL_PAD_LCD_DAT17__I2C2_SDA 0x1d4 0x4dc 0x728 0x4 0x3 | ||
| 714 | #define MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x1d4 0x4dc 0x000 0x5 0x0 | ||
| 715 | #define MX6SL_PAD_LCD_DAT17__ARM_TRACE17 0x1d4 0x4dc 0x000 0x6 0x0 | ||
| 716 | #define MX6SL_PAD_LCD_DAT17__SRC_BOOT_CFG25 0x1d4 0x4dc 0x000 0x7 0x0 | ||
| 717 | #define MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1d8 0x4e0 0x7c0 0x0 0x1 | ||
| 718 | #define MX6SL_PAD_LCD_DAT18__KEY_COL5 0x1d8 0x4e0 0x748 0x1 0x1 | ||
| 719 | #define MX6SL_PAD_LCD_DAT18__CSI_DATA15 0x1d8 0x4e0 0x66c 0x2 0x0 | ||
| 720 | #define MX6SL_PAD_LCD_DAT18__EIM_DATA12 0x1d8 0x4e0 0x000 0x3 0x0 | ||
| 721 | #define MX6SL_PAD_LCD_DAT18__GPT_CAPTURE1 0x1d8 0x4e0 0x710 0x4 0x1 | ||
| 722 | #define MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x1d8 0x4e0 0x000 0x5 0x0 | ||
| 723 | #define MX6SL_PAD_LCD_DAT18__ARM_TRACE18 0x1d8 0x4e0 0x000 0x6 0x0 | ||
| 724 | #define MX6SL_PAD_LCD_DAT18__SRC_BOOT_CFG26 0x1d8 0x4e0 0x000 0x7 0x0 | ||
| 725 | #define MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1dc 0x4e4 0x7c4 0x0 0x1 | ||
| 726 | #define MX6SL_PAD_LCD_DAT19__KEY_ROW5 0x1dc 0x4e4 0x768 0x1 0x1 | ||
| 727 | #define MX6SL_PAD_LCD_DAT19__CSI_DATA14 0x1dc 0x4e4 0x668 0x2 0x0 | ||
| 728 | #define MX6SL_PAD_LCD_DAT19__EIM_DATA13 0x1dc 0x4e4 0x000 0x3 0x0 | ||
| 729 | #define MX6SL_PAD_LCD_DAT19__GPT_CAPTURE2 0x1dc 0x4e4 0x714 0x4 0x1 | ||
| 730 | #define MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x1dc 0x4e4 0x000 0x5 0x0 | ||
| 731 | #define MX6SL_PAD_LCD_DAT19__ARM_TRACE19 0x1dc 0x4e4 0x000 0x6 0x0 | ||
| 732 | #define MX6SL_PAD_LCD_DAT19__SRC_BOOT_CFG27 0x1dc 0x4e4 0x000 0x7 0x0 | ||
| 733 | #define MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1e0 0x4e8 0x780 0x0 0x1 | ||
| 734 | #define MX6SL_PAD_LCD_DAT2__ECSPI1_SS0 0x1e0 0x4e8 0x68c 0x1 0x1 | ||
| 735 | #define MX6SL_PAD_LCD_DAT2__EPIT2_OUT 0x1e0 0x4e8 0x000 0x2 0x0 | ||
| 736 | #define MX6SL_PAD_LCD_DAT2__PWM3_OUT 0x1e0 0x4e8 0x000 0x3 0x0 | ||
| 737 | #define MX6SL_PAD_LCD_DAT2__AUD4_RXC 0x1e0 0x4e8 0x5ec 0x4 0x1 | ||
| 738 | #define MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x1e0 0x4e8 0x000 0x5 0x0 | ||
| 739 | #define MX6SL_PAD_LCD_DAT2__ARM_TRACE02 0x1e0 0x4e8 0x000 0x6 0x0 | ||
| 740 | #define MX6SL_PAD_LCD_DAT2__SRC_BOOT_CFG02 0x1e0 0x4e8 0x000 0x7 0x0 | ||
| 741 | #define MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1e4 0x4ec 0x7c8 0x0 0x1 | ||
| 742 | #define MX6SL_PAD_LCD_DAT20__KEY_COL6 0x1e4 0x4ec 0x74c 0x1 0x1 | ||
| 743 | #define MX6SL_PAD_LCD_DAT20__CSI_DATA13 0x1e4 0x4ec 0x664 0x2 0x0 | ||
| 744 | #define MX6SL_PAD_LCD_DAT20__EIM_DATA14 0x1e4 0x4ec 0x000 0x3 0x0 | ||
| 745 | #define MX6SL_PAD_LCD_DAT20__GPT_COMPARE1 0x1e4 0x4ec 0x000 0x4 0x0 | ||
| 746 | #define MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x1e4 0x4ec 0x000 0x5 0x0 | ||
| 747 | #define MX6SL_PAD_LCD_DAT20__ARM_TRACE20 0x1e4 0x4ec 0x000 0x6 0x0 | ||
| 748 | #define MX6SL_PAD_LCD_DAT20__SRC_BOOT_CFG28 0x1e4 0x4ec 0x000 0x7 0x0 | ||
| 749 | #define MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1e8 0x4f0 0x7cc 0x0 0x1 | ||
| 750 | #define MX6SL_PAD_LCD_DAT21__KEY_ROW6 0x1e8 0x4f0 0x76c 0x1 0x1 | ||
| 751 | #define MX6SL_PAD_LCD_DAT21__CSI_DATA12 0x1e8 0x4f0 0x660 0x2 0x0 | ||
| 752 | #define MX6SL_PAD_LCD_DAT21__EIM_DATA15 0x1e8 0x4f0 0x000 0x3 0x0 | ||
| 753 | #define MX6SL_PAD_LCD_DAT21__GPT_COMPARE2 0x1e8 0x4f0 0x000 0x4 0x0 | ||
| 754 | #define MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x1e8 0x4f0 0x000 0x5 0x0 | ||
| 755 | #define MX6SL_PAD_LCD_DAT21__ARM_TRACE21 0x1e8 0x4f0 0x000 0x6 0x0 | ||
| 756 | #define MX6SL_PAD_LCD_DAT21__SRC_BOOT_CFG29 0x1e8 0x4f0 0x000 0x7 0x0 | ||
| 757 | #define MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1ec 0x4f4 0x7d0 0x0 0x1 | ||
| 758 | #define MX6SL_PAD_LCD_DAT22__KEY_COL7 0x1ec 0x4f4 0x750 0x1 0x1 | ||
| 759 | #define MX6SL_PAD_LCD_DAT22__CSI_DATA11 0x1ec 0x4f4 0x65c 0x2 0x1 | ||
| 760 | #define MX6SL_PAD_LCD_DAT22__EIM_EB3_B 0x1ec 0x4f4 0x000 0x3 0x0 | ||
| 761 | #define MX6SL_PAD_LCD_DAT22__GPT_COMPARE3 0x1ec 0x4f4 0x000 0x4 0x0 | ||
| 762 | #define MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x1ec 0x4f4 0x000 0x5 0x0 | ||
| 763 | #define MX6SL_PAD_LCD_DAT22__ARM_TRACE22 0x1ec 0x4f4 0x000 0x6 0x0 | ||
| 764 | #define MX6SL_PAD_LCD_DAT22__SRC_BOOT_CFG30 0x1ec 0x4f4 0x000 0x7 0x0 | ||
| 765 | #define MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1f0 0x4f8 0x7d4 0x0 0x1 | ||
| 766 | #define MX6SL_PAD_LCD_DAT23__KEY_ROW7 0x1f0 0x4f8 0x770 0x1 0x1 | ||
| 767 | #define MX6SL_PAD_LCD_DAT23__CSI_DATA10 0x1f0 0x4f8 0x658 0x2 0x1 | ||
| 768 | #define MX6SL_PAD_LCD_DAT23__EIM_EB2_B 0x1f0 0x4f8 0x000 0x3 0x0 | ||
| 769 | #define MX6SL_PAD_LCD_DAT23__GPT_CLKIN 0x1f0 0x4f8 0x718 0x4 0x1 | ||
| 770 | #define MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x1f0 0x4f8 0x000 0x5 0x0 | ||
| 771 | #define MX6SL_PAD_LCD_DAT23__ARM_TRACE23 0x1f0 0x4f8 0x000 0x6 0x0 | ||
| 772 | #define MX6SL_PAD_LCD_DAT23__SRC_BOOT_CFG31 0x1f0 0x4f8 0x000 0x7 0x0 | ||
| 773 | #define MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1f4 0x4fc 0x784 0x0 0x1 | ||
| 774 | #define MX6SL_PAD_LCD_DAT3__ECSPI1_SCLK 0x1f4 0x4fc 0x67c 0x1 0x1 | ||
| 775 | #define MX6SL_PAD_LCD_DAT3__UART5_DSR_B 0x1f4 0x4fc 0x000 0x2 0x0 | ||
| 776 | #define MX6SL_PAD_LCD_DAT3__PWM4_OUT 0x1f4 0x4fc 0x000 0x3 0x0 | ||
| 777 | #define MX6SL_PAD_LCD_DAT3__AUD4_RXD 0x1f4 0x4fc 0x5e4 0x4 0x1 | ||
| 778 | #define MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x1f4 0x4fc 0x000 0x5 0x0 | ||
| 779 | #define MX6SL_PAD_LCD_DAT3__ARM_TRACE03 0x1f4 0x4fc 0x000 0x6 0x0 | ||
| 780 | #define MX6SL_PAD_LCD_DAT3__SRC_BOOT_CFG03 0x1f4 0x4fc 0x000 0x7 0x0 | ||
| 781 | #define MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1f8 0x500 0x788 0x0 0x1 | ||
| 782 | #define MX6SL_PAD_LCD_DAT4__ECSPI1_SS1 0x1f8 0x500 0x690 0x1 0x1 | ||
| 783 | #define MX6SL_PAD_LCD_DAT4__CSI_VSYNC 0x1f8 0x500 0x678 0x2 0x2 | ||
| 784 | #define MX6SL_PAD_LCD_DAT4__WDOG2_RESET_B_DEB 0x1f8 0x500 0x000 0x3 0x0 | ||
| 785 | #define MX6SL_PAD_LCD_DAT4__AUD4_TXC 0x1f8 0x500 0x5f4 0x4 0x1 | ||
| 786 | #define MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x1f8 0x500 0x000 0x5 0x0 | ||
| 787 | #define MX6SL_PAD_LCD_DAT4__ARM_TRACE04 0x1f8 0x500 0x000 0x6 0x0 | ||
| 788 | #define MX6SL_PAD_LCD_DAT4__SRC_BOOT_CFG04 0x1f8 0x500 0x000 0x7 0x0 | ||
| 789 | #define MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1fc 0x504 0x78c 0x0 0x1 | ||
| 790 | #define MX6SL_PAD_LCD_DAT5__ECSPI1_SS2 0x1fc 0x504 0x694 0x1 0x1 | ||
| 791 | #define MX6SL_PAD_LCD_DAT5__CSI_HSYNC 0x1fc 0x504 0x670 0x2 0x2 | ||
| 792 | #define MX6SL_PAD_LCD_DAT5__EIM_CS3_B 0x1fc 0x504 0x000 0x3 0x0 | ||
| 793 | #define MX6SL_PAD_LCD_DAT5__AUD4_TXFS 0x1fc 0x504 0x5f8 0x4 0x1 | ||
| 794 | #define MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x1fc 0x504 0x000 0x5 0x0 | ||
| 795 | #define MX6SL_PAD_LCD_DAT5__ARM_TRACE05 0x1fc 0x504 0x000 0x6 0x0 | ||
| 796 | #define MX6SL_PAD_LCD_DAT5__SRC_BOOT_CFG05 0x1fc 0x504 0x000 0x7 0x0 | ||
| 797 | #define MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x200 0x508 0x790 0x0 0x1 | ||
| 798 | #define MX6SL_PAD_LCD_DAT6__ECSPI1_SS3 0x200 0x508 0x698 0x1 0x1 | ||
| 799 | #define MX6SL_PAD_LCD_DAT6__CSI_PIXCLK 0x200 0x508 0x674 0x2 0x2 | ||
| 800 | #define MX6SL_PAD_LCD_DAT6__EIM_DATA00 0x200 0x508 0x000 0x3 0x0 | ||
| 801 | #define MX6SL_PAD_LCD_DAT6__AUD4_TXD 0x200 0x508 0x5e8 0x4 0x1 | ||
| 802 | #define MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x200 0x508 0x000 0x5 0x0 | ||
| 803 | #define MX6SL_PAD_LCD_DAT6__ARM_TRACE06 0x200 0x508 0x000 0x6 0x0 | ||
| 804 | #define MX6SL_PAD_LCD_DAT6__SRC_BOOT_CFG06 0x200 0x508 0x000 0x7 0x0 | ||
| 805 | #define MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x204 0x50c 0x794 0x0 0x1 | ||
| 806 | #define MX6SL_PAD_LCD_DAT7__ECSPI1_RDY 0x204 0x50c 0x680 0x1 0x1 | ||
| 807 | #define MX6SL_PAD_LCD_DAT7__CSI_MCLK 0x204 0x50c 0x000 0x2 0x0 | ||
| 808 | #define MX6SL_PAD_LCD_DAT7__EIM_DATA01 0x204 0x50c 0x000 0x3 0x0 | ||
| 809 | #define MX6SL_PAD_LCD_DAT7__AUDIO_CLK_OUT 0x204 0x50c 0x000 0x4 0x0 | ||
| 810 | #define MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x204 0x50c 0x000 0x5 0x0 | ||
| 811 | #define MX6SL_PAD_LCD_DAT7__ARM_TRACE07 0x204 0x50c 0x000 0x6 0x0 | ||
| 812 | #define MX6SL_PAD_LCD_DAT7__SRC_BOOT_CFG07 0x204 0x50c 0x000 0x7 0x0 | ||
| 813 | #define MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x208 0x510 0x798 0x0 0x1 | ||
| 814 | #define MX6SL_PAD_LCD_DAT8__KEY_COL0 0x208 0x510 0x734 0x1 0x1 | ||
| 815 | #define MX6SL_PAD_LCD_DAT8__CSI_DATA09 0x208 0x510 0x654 0x2 0x1 | ||
| 816 | #define MX6SL_PAD_LCD_DAT8__EIM_DATA02 0x208 0x510 0x000 0x3 0x0 | ||
| 817 | #define MX6SL_PAD_LCD_DAT8__ECSPI2_SCLK 0x208 0x510 0x69c 0x4 0x2 | ||
| 818 | #define MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x208 0x510 0x000 0x5 0x0 | ||
| 819 | #define MX6SL_PAD_LCD_DAT8__ARM_TRACE08 0x208 0x510 0x000 0x6 0x0 | ||
| 820 | #define MX6SL_PAD_LCD_DAT8__SRC_BOOT_CFG08 0x208 0x510 0x000 0x7 0x0 | ||
| 821 | #define MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x20c 0x514 0x79c 0x0 0x1 | ||
| 822 | #define MX6SL_PAD_LCD_DAT9__KEY_ROW0 0x20c 0x514 0x754 0x1 0x1 | ||
| 823 | #define MX6SL_PAD_LCD_DAT9__CSI_DATA08 0x20c 0x514 0x650 0x2 0x1 | ||
| 824 | #define MX6SL_PAD_LCD_DAT9__EIM_DATA03 0x20c 0x514 0x000 0x3 0x0 | ||
| 825 | #define MX6SL_PAD_LCD_DAT9__ECSPI2_MOSI 0x20c 0x514 0x6a4 0x4 0x2 | ||
| 826 | #define MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x20c 0x514 0x000 0x5 0x0 | ||
| 827 | #define MX6SL_PAD_LCD_DAT9__ARM_TRACE09 0x20c 0x514 0x000 0x6 0x0 | ||
| 828 | #define MX6SL_PAD_LCD_DAT9__SRC_BOOT_CFG09 0x20c 0x514 0x000 0x7 0x0 | ||
| 829 | #define MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x210 0x518 0x000 0x0 0x0 | ||
| 830 | #define MX6SL_PAD_LCD_ENABLE__SD4_DATA5 0x210 0x518 0x870 0x1 0x2 | ||
| 831 | #define MX6SL_PAD_LCD_ENABLE__LCD_RD_E 0x210 0x518 0x000 0x2 0x0 | ||
| 832 | #define MX6SL_PAD_LCD_ENABLE__EIM_OE_B 0x210 0x518 0x000 0x3 0x0 | ||
| 833 | #define MX6SL_PAD_LCD_ENABLE__UART2_RX_DATA 0x210 0x518 0x804 0x4 0x2 | ||
| 834 | #define MX6SL_PAD_LCD_ENABLE__UART2_TX_DATA 0x210 0x518 0x000 0x4 0x0 | ||
| 835 | #define MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x210 0x518 0x000 0x5 0x0 | ||
| 836 | #define MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x214 0x51c 0x774 0x0 0x0 | ||
| 837 | #define MX6SL_PAD_LCD_HSYNC__SD4_DATA6 0x214 0x51c 0x874 0x1 0x2 | ||
| 838 | #define MX6SL_PAD_LCD_HSYNC__LCD_CS 0x214 0x51c 0x000 0x2 0x0 | ||
| 839 | #define MX6SL_PAD_LCD_HSYNC__EIM_CS0_B 0x214 0x51c 0x000 0x3 0x0 | ||
| 840 | #define MX6SL_PAD_LCD_HSYNC__UART2_TX_DATA 0x214 0x51c 0x000 0x4 0x0 | ||
| 841 | #define MX6SL_PAD_LCD_HSYNC__UART2_RX_DATA 0x214 0x51c 0x804 0x4 0x3 | ||
| 842 | #define MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x214 0x51c 0x000 0x5 0x0 | ||
| 843 | #define MX6SL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x214 0x51c 0x000 0x6 0x0 | ||
| 844 | #define MX6SL_PAD_LCD_RESET__LCD_RESET 0x218 0x520 0x000 0x0 0x0 | ||
| 845 | #define MX6SL_PAD_LCD_RESET__EIM_DTACK_B 0x218 0x520 0x880 0x1 0x1 | ||
| 846 | #define MX6SL_PAD_LCD_RESET__LCD_BUSY 0x218 0x520 0x774 0x2 0x1 | ||
| 847 | #define MX6SL_PAD_LCD_RESET__EIM_WAIT_B 0x218 0x520 0x884 0x3 0x1 | ||
| 848 | #define MX6SL_PAD_LCD_RESET__UART2_CTS_B 0x218 0x520 0x000 0x4 0x0 | ||
| 849 | #define MX6SL_PAD_LCD_RESET__UART2_RTS_B 0x218 0x520 0x800 0x4 0x2 | ||
| 850 | #define MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x218 0x520 0x000 0x5 0x0 | ||
| 851 | #define MX6SL_PAD_LCD_RESET__CCM_PMIC_READY 0x218 0x520 0x62c 0x6 0x1 | ||
| 852 | #define MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x21c 0x524 0x000 0x0 0x0 | ||
| 853 | #define MX6SL_PAD_LCD_VSYNC__SD4_DATA7 0x21c 0x524 0x878 0x1 0x2 | ||
| 854 | #define MX6SL_PAD_LCD_VSYNC__LCD_RS 0x21c 0x524 0x000 0x2 0x0 | ||
| 855 | #define MX6SL_PAD_LCD_VSYNC__EIM_CS1_B 0x21c 0x524 0x000 0x3 0x0 | ||
| 856 | #define MX6SL_PAD_LCD_VSYNC__UART2_RTS_B 0x21c 0x524 0x800 0x4 0x3 | ||
| 857 | #define MX6SL_PAD_LCD_VSYNC__UART2_CTS_B 0x21c 0x524 0x000 0x4 0x0 | ||
| 858 | #define MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x21c 0x524 0x000 0x5 0x0 | ||
| 859 | #define MX6SL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x21c 0x524 0x000 0x6 0x0 | ||
| 860 | #define MX6SL_PAD_PWM1__PWM1_OUT 0x220 0x528 0x000 0x0 0x0 | ||
| 861 | #define MX6SL_PAD_PWM1__CCM_CLKO 0x220 0x528 0x000 0x1 0x0 | ||
| 862 | #define MX6SL_PAD_PWM1__AUDIO_CLK_OUT 0x220 0x528 0x000 0x2 0x0 | ||
| 863 | #define MX6SL_PAD_PWM1__FEC_REF_OUT 0x220 0x528 0x000 0x3 0x0 | ||
| 864 | #define MX6SL_PAD_PWM1__CSI_MCLK 0x220 0x528 0x000 0x4 0x0 | ||
| 865 | #define MX6SL_PAD_PWM1__GPIO3_IO23 0x220 0x528 0x000 0x5 0x0 | ||
| 866 | #define MX6SL_PAD_PWM1__EPIT1_OUT 0x220 0x528 0x000 0x6 0x0 | ||
| 867 | #define MX6SL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x224 0x52c 0x000 0x0 0x0 | ||
| 868 | #define MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x224 0x52c 0x72c 0x1 0x2 | ||
| 869 | #define MX6SL_PAD_REF_CLK_24M__PWM3_OUT 0x224 0x52c 0x000 0x2 0x0 | ||
| 870 | #define MX6SL_PAD_REF_CLK_24M__USB_OTG2_ID 0x224 0x52c 0x5e0 0x3 0x2 | ||
| 871 | #define MX6SL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x224 0x52c 0x62c 0x4 0x2 | ||
| 872 | #define MX6SL_PAD_REF_CLK_24M__GPIO3_IO21 0x224 0x52c 0x000 0x5 0x0 | ||
| 873 | #define MX6SL_PAD_REF_CLK_24M__SD3_WP 0x224 0x52c 0x84c 0x6 0x3 | ||
| 874 | #define MX6SL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x228 0x530 0x000 0x0 0x0 | ||
| 875 | #define MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x228 0x530 0x730 0x1 0x2 | ||
| 876 | #define MX6SL_PAD_REF_CLK_32K__PWM4_OUT 0x228 0x530 0x000 0x2 0x0 | ||
| 877 | #define MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x228 0x530 0x5dc 0x3 0x3 | ||
| 878 | #define MX6SL_PAD_REF_CLK_32K__SD1_LCTL 0x228 0x530 0x000 0x4 0x0 | ||
| 879 | #define MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x228 0x530 0x000 0x5 0x0 | ||
| 880 | #define MX6SL_PAD_REF_CLK_32K__SD3_CD_B 0x228 0x530 0x838 0x6 0x3 | ||
| 881 | #define MX6SL_PAD_SD1_CLK__SD1_CLK 0x22c 0x534 0x000 0x0 0x0 | ||
| 882 | #define MX6SL_PAD_SD1_CLK__FEC_MDIO 0x22c 0x534 0x6f4 0x1 0x2 | ||
| 883 | #define MX6SL_PAD_SD1_CLK__KEY_COL0 0x22c 0x534 0x734 0x2 0x2 | ||
| 884 | #define MX6SL_PAD_SD1_CLK__EPDC_SDCE4 0x22c 0x534 0x000 0x3 0x0 | ||
| 885 | #define MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x22c 0x534 0x000 0x5 0x0 | ||
| 886 | #define MX6SL_PAD_SD1_CMD__SD1_CMD 0x230 0x538 0x000 0x0 0x0 | ||
| 887 | #define MX6SL_PAD_SD1_CMD__FEC_TX_CLK 0x230 0x538 0x70c 0x1 0x2 | ||
| 888 | #define MX6SL_PAD_SD1_CMD__KEY_ROW0 0x230 0x538 0x754 0x2 0x2 | ||
| 889 | #define MX6SL_PAD_SD1_CMD__EPDC_SDCE5 0x230 0x538 0x000 0x3 0x0 | ||
| 890 | #define MX6SL_PAD_SD1_CMD__GPIO5_IO14 0x230 0x538 0x000 0x5 0x0 | ||
| 891 | #define MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x234 0x53c 0x000 0x0 0x0 | ||
| 892 | #define MX6SL_PAD_SD1_DAT0__FEC_RX_ER 0x234 0x53c 0x708 0x1 0x2 | ||
| 893 | #define MX6SL_PAD_SD1_DAT0__KEY_COL1 0x234 0x53c 0x738 0x2 0x2 | ||
| 894 | #define MX6SL_PAD_SD1_DAT0__EPDC_SDCE6 0x234 0x53c 0x000 0x3 0x0 | ||
| 895 | #define MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x234 0x53c 0x000 0x5 0x0 | ||
| 896 | #define MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x238 0x540 0x000 0x0 0x0 | ||
| 897 | #define MX6SL_PAD_SD1_DAT1__FEC_RX_DV 0x238 0x540 0x704 0x1 0x2 | ||
| 898 | #define MX6SL_PAD_SD1_DAT1__KEY_ROW1 0x238 0x540 0x758 0x2 0x2 | ||
| 899 | #define MX6SL_PAD_SD1_DAT1__EPDC_SDCE7 0x238 0x540 0x000 0x3 0x0 | ||
| 900 | #define MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x238 0x540 0x000 0x5 0x0 | ||
| 901 | #define MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x23c 0x544 0x000 0x0 0x0 | ||
| 902 | #define MX6SL_PAD_SD1_DAT2__FEC_RX_DATA1 0x23c 0x544 0x6fc 0x1 0x2 | ||
| 903 | #define MX6SL_PAD_SD1_DAT2__KEY_COL2 0x23c 0x544 0x73c 0x2 0x2 | ||
| 904 | #define MX6SL_PAD_SD1_DAT2__EPDC_SDCE8 0x23c 0x544 0x000 0x3 0x0 | ||
| 905 | #define MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x23c 0x544 0x000 0x5 0x0 | ||
| 906 | #define MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x240 0x548 0x000 0x0 0x0 | ||
| 907 | #define MX6SL_PAD_SD1_DAT3__FEC_TX_DATA0 0x240 0x548 0x000 0x1 0x0 | ||
| 908 | #define MX6SL_PAD_SD1_DAT3__KEY_ROW2 0x240 0x548 0x75c 0x2 0x2 | ||
| 909 | #define MX6SL_PAD_SD1_DAT3__EPDC_SDCE9 0x240 0x548 0x000 0x3 0x0 | ||
| 910 | #define MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x240 0x548 0x000 0x5 0x0 | ||
| 911 | #define MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x244 0x54c 0x000 0x0 0x0 | ||
| 912 | #define MX6SL_PAD_SD1_DAT4__FEC_MDC 0x244 0x54c 0x000 0x1 0x0 | ||
| 913 | #define MX6SL_PAD_SD1_DAT4__KEY_COL3 0x244 0x54c 0x740 0x2 0x2 | ||
| 914 | #define MX6SL_PAD_SD1_DAT4__EPDC_SDCLK_N 0x244 0x54c 0x000 0x3 0x0 | ||
| 915 | #define MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x244 0x54c 0x814 0x4 0x4 | ||
| 916 | #define MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x244 0x54c 0x000 0x4 0x0 | ||
| 917 | #define MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x244 0x54c 0x000 0x5 0x0 | ||
| 918 | #define MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x248 0x550 0x000 0x0 0x0 | ||
| 919 | #define MX6SL_PAD_SD1_DAT5__FEC_RX_DATA0 0x248 0x550 0x6f8 0x1 0x2 | ||
| 920 | #define MX6SL_PAD_SD1_DAT5__KEY_ROW3 0x248 0x550 0x760 0x2 0x2 | ||
| 921 | #define MX6SL_PAD_SD1_DAT5__EPDC_SDOED 0x248 0x550 0x000 0x3 0x0 | ||
| 922 | #define MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x248 0x550 0x000 0x4 0x0 | ||
| 923 | #define MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x248 0x550 0x814 0x4 0x5 | ||
| 924 | #define MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x248 0x550 0x000 0x5 0x0 | ||
| 925 | #define MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x24c 0x554 0x000 0x0 0x0 | ||
| 926 | #define MX6SL_PAD_SD1_DAT6__FEC_TX_EN 0x24c 0x554 0x000 0x1 0x0 | ||
| 927 | #define MX6SL_PAD_SD1_DAT6__KEY_COL4 0x24c 0x554 0x744 0x2 0x2 | ||
| 928 | #define MX6SL_PAD_SD1_DAT6__EPDC_SDOEZ 0x24c 0x554 0x000 0x3 0x0 | ||
| 929 | #define MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x24c 0x554 0x810 0x4 0x4 | ||
| 930 | #define MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x24c 0x554 0x000 0x4 0x0 | ||
| 931 | #define MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x24c 0x554 0x000 0x5 0x0 | ||
| 932 | #define MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x250 0x558 0x000 0x0 0x0 | ||
| 933 | #define MX6SL_PAD_SD1_DAT7__FEC_TX_DATA1 0x250 0x558 0x000 0x1 0x0 | ||
| 934 | #define MX6SL_PAD_SD1_DAT7__KEY_ROW4 0x250 0x558 0x764 0x2 0x2 | ||
| 935 | #define MX6SL_PAD_SD1_DAT7__CCM_PMIC_READY 0x250 0x558 0x62c 0x3 0x3 | ||
| 936 | #define MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x250 0x558 0x000 0x4 0x0 | ||
| 937 | #define MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x250 0x558 0x810 0x4 0x5 | ||
| 938 | #define MX6SL_PAD_SD1_DAT7__GPIO5_IO10 0x250 0x558 0x000 0x5 0x0 | ||
| 939 | #define MX6SL_PAD_SD2_CLK__SD2_CLK 0x254 0x55c 0x000 0x0 0x0 | ||
| 940 | #define MX6SL_PAD_SD2_CLK__AUD4_RXFS 0x254 0x55c 0x5f0 0x1 0x2 | ||
| 941 | #define MX6SL_PAD_SD2_CLK__ECSPI3_SCLK 0x254 0x55c 0x6b0 0x2 0x2 | ||
| 942 | #define MX6SL_PAD_SD2_CLK__CSI_DATA00 0x254 0x55c 0x630 0x3 0x2 | ||
| 943 | #define MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x254 0x55c 0x000 0x5 0x0 | ||
| 944 | #define MX6SL_PAD_SD2_CMD__SD2_CMD 0x258 0x560 0x000 0x0 0x0 | ||
| 945 | #define MX6SL_PAD_SD2_CMD__AUD4_RXC 0x258 0x560 0x5ec 0x1 0x2 | ||
| 946 | #define MX6SL_PAD_SD2_CMD__ECSPI3_SS0 0x258 0x560 0x6c0 0x2 0x2 | ||
| 947 | #define MX6SL_PAD_SD2_CMD__CSI_DATA01 0x258 0x560 0x634 0x3 0x2 | ||
| 948 | #define MX6SL_PAD_SD2_CMD__EPIT1_OUT 0x258 0x560 0x000 0x4 0x0 | ||
| 949 | #define MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x258 0x560 0x000 0x5 0x0 | ||
| 950 | #define MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x25c 0x564 0x000 0x0 0x0 | ||
| 951 | #define MX6SL_PAD_SD2_DAT0__AUD4_RXD 0x25c 0x564 0x5e4 0x1 0x2 | ||
| 952 | #define MX6SL_PAD_SD2_DAT0__ECSPI3_MOSI 0x25c 0x564 0x6bc 0x2 0x2 | ||
| 953 | #define MX6SL_PAD_SD2_DAT0__CSI_DATA02 0x25c 0x564 0x638 0x3 0x2 | ||
| 954 | #define MX6SL_PAD_SD2_DAT0__UART5_RTS_B 0x25c 0x564 0x818 0x4 0x4 | ||
| 955 | #define MX6SL_PAD_SD2_DAT0__UART5_CTS_B 0x25c 0x564 0x000 0x4 0x0 | ||
| 956 | #define MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x25c 0x564 0x000 0x5 0x0 | ||
| 957 | #define MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x260 0x568 0x000 0x0 0x0 | ||
| 958 | #define MX6SL_PAD_SD2_DAT1__AUD4_TXC 0x260 0x568 0x5f4 0x1 0x2 | ||
| 959 | #define MX6SL_PAD_SD2_DAT1__ECSPI3_MISO 0x260 0x568 0x6b8 0x2 0x2 | ||
| 960 | #define MX6SL_PAD_SD2_DAT1__CSI_DATA03 0x260 0x568 0x63c 0x3 0x2 | ||
| 961 | #define MX6SL_PAD_SD2_DAT1__UART5_CTS_B 0x260 0x568 0x000 0x4 0x0 | ||
| 962 | #define MX6SL_PAD_SD2_DAT1__UART5_RTS_B 0x260 0x568 0x818 0x4 0x5 | ||
| 963 | #define MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x260 0x568 0x000 0x5 0x0 | ||
| 964 | #define MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x264 0x56c 0x000 0x0 0x0 | ||
| 965 | #define MX6SL_PAD_SD2_DAT2__AUD4_TXFS 0x264 0x56c 0x5f8 0x1 0x2 | ||
| 966 | #define MX6SL_PAD_SD2_DAT2__FEC_COL 0x264 0x56c 0x6f0 0x2 0x1 | ||
| 967 | #define MX6SL_PAD_SD2_DAT2__CSI_DATA04 0x264 0x56c 0x640 0x3 0x2 | ||
| 968 | #define MX6SL_PAD_SD2_DAT2__UART5_RX_DATA 0x264 0x56c 0x81c 0x4 0x4 | ||
| 969 | #define MX6SL_PAD_SD2_DAT2__UART5_TX_DATA 0x264 0x56c 0x000 0x4 0x0 | ||
| 970 | #define MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x264 0x56c 0x000 0x5 0x0 | ||
| 971 | #define MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x268 0x570 0x000 0x0 0x0 | ||
| 972 | #define MX6SL_PAD_SD2_DAT3__AUD4_TXD 0x268 0x570 0x5e8 0x1 0x2 | ||
| 973 | #define MX6SL_PAD_SD2_DAT3__FEC_RX_CLK 0x268 0x570 0x700 0x2 0x1 | ||
| 974 | #define MX6SL_PAD_SD2_DAT3__CSI_DATA05 0x268 0x570 0x644 0x3 0x2 | ||
| 975 | #define MX6SL_PAD_SD2_DAT3__UART5_TX_DATA 0x268 0x570 0x000 0x4 0x0 | ||
| 976 | #define MX6SL_PAD_SD2_DAT3__UART5_RX_DATA 0x268 0x570 0x81c 0x4 0x5 | ||
| 977 | #define MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x268 0x570 0x000 0x5 0x0 | ||
| 978 | #define MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x26c 0x574 0x000 0x0 0x0 | ||
| 979 | #define MX6SL_PAD_SD2_DAT4__SD3_DATA4 0x26c 0x574 0x83c 0x1 0x1 | ||
| 980 | #define MX6SL_PAD_SD2_DAT4__UART2_RX_DATA 0x26c 0x574 0x804 0x2 0x4 | ||
| 981 | #define MX6SL_PAD_SD2_DAT4__UART2_TX_DATA 0x26c 0x574 0x000 0x2 0x0 | ||
| 982 | #define MX6SL_PAD_SD2_DAT4__CSI_DATA06 0x26c 0x574 0x648 0x3 0x2 | ||
| 983 | #define MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x26c 0x574 0x000 0x4 0x0 | ||
| 984 | #define MX6SL_PAD_SD2_DAT4__GPIO5_IO02 0x26c 0x574 0x000 0x5 0x0 | ||
| 985 | #define MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x270 0x578 0x000 0x0 0x0 | ||
| 986 | #define MX6SL_PAD_SD2_DAT5__SD3_DATA5 0x270 0x578 0x840 0x1 0x1 | ||
| 987 | #define MX6SL_PAD_SD2_DAT5__UART2_TX_DATA 0x270 0x578 0x000 0x2 0x0 | ||
| 988 | #define MX6SL_PAD_SD2_DAT5__UART2_RX_DATA 0x270 0x578 0x804 0x2 0x5 | ||
| 989 | #define MX6SL_PAD_SD2_DAT5__CSI_DATA07 0x270 0x578 0x64c 0x3 0x2 | ||
| 990 | #define MX6SL_PAD_SD2_DAT5__SPDIF_IN 0x270 0x578 0x7f0 0x4 0x2 | ||
| 991 | #define MX6SL_PAD_SD2_DAT5__GPIO4_IO31 0x270 0x578 0x000 0x5 0x0 | ||
| 992 | #define MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x274 0x57c 0x000 0x0 0x0 | ||
| 993 | #define MX6SL_PAD_SD2_DAT6__SD3_DATA6 0x274 0x57c 0x844 0x1 0x1 | ||
| 994 | #define MX6SL_PAD_SD2_DAT6__UART2_RTS_B 0x274 0x57c 0x800 0x2 0x4 | ||
| 995 | #define MX6SL_PAD_SD2_DAT6__UART2_CTS_B 0x274 0x57c 0x000 0x2 0x0 | ||
| 996 | #define MX6SL_PAD_SD2_DAT6__CSI_DATA08 0x274 0x57c 0x650 0x3 0x2 | ||
| 997 | #define MX6SL_PAD_SD2_DAT6__SD2_WP 0x274 0x57c 0x834 0x4 0x2 | ||
| 998 | #define MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x274 0x57c 0x000 0x5 0x0 | ||
| 999 | #define MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x278 0x580 0x000 0x0 0x0 | ||
| 1000 | #define MX6SL_PAD_SD2_DAT7__SD3_DATA7 0x278 0x580 0x848 0x1 0x1 | ||
| 1001 | #define MX6SL_PAD_SD2_DAT7__UART2_CTS_B 0x278 0x580 0x000 0x2 0x0 | ||
| 1002 | #define MX6SL_PAD_SD2_DAT7__UART2_RTS_B 0x278 0x580 0x800 0x2 0x5 | ||
| 1003 | #define MX6SL_PAD_SD2_DAT7__CSI_DATA09 0x278 0x580 0x654 0x3 0x2 | ||
| 1004 | #define MX6SL_PAD_SD2_DAT7__SD2_CD_B 0x278 0x580 0x830 0x4 0x2 | ||
| 1005 | #define MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x278 0x580 0x000 0x5 0x0 | ||
| 1006 | #define MX6SL_PAD_SD2_RST__SD2_RESET 0x27c 0x584 0x000 0x0 0x0 | ||
| 1007 | #define MX6SL_PAD_SD2_RST__FEC_REF_OUT 0x27c 0x584 0x000 0x1 0x0 | ||
| 1008 | #define MX6SL_PAD_SD2_RST__WDOG2_B 0x27c 0x584 0x000 0x2 0x0 | ||
| 1009 | #define MX6SL_PAD_SD2_RST__SPDIF_OUT 0x27c 0x584 0x000 0x3 0x0 | ||
| 1010 | #define MX6SL_PAD_SD2_RST__CSI_MCLK 0x27c 0x584 0x000 0x4 0x0 | ||
| 1011 | #define MX6SL_PAD_SD2_RST__GPIO4_IO27 0x27c 0x584 0x000 0x5 0x0 | ||
| 1012 | #define MX6SL_PAD_SD3_CLK__SD3_CLK 0x280 0x588 0x000 0x0 0x0 | ||
| 1013 | #define MX6SL_PAD_SD3_CLK__AUD5_RXFS 0x280 0x588 0x608 0x1 0x1 | ||
| 1014 | #define MX6SL_PAD_SD3_CLK__KEY_COL5 0x280 0x588 0x748 0x2 0x2 | ||
| 1015 | #define MX6SL_PAD_SD3_CLK__CSI_DATA10 0x280 0x588 0x658 0x3 0x2 | ||
| 1016 | #define MX6SL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x280 0x588 0x000 0x4 0x0 | ||
| 1017 | #define MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x280 0x588 0x000 0x5 0x0 | ||
| 1018 | #define MX6SL_PAD_SD3_CLK__USB_OTG1_PWR 0x280 0x588 0x000 0x6 0x0 | ||
| 1019 | #define MX6SL_PAD_SD3_CMD__SD3_CMD 0x284 0x58c 0x000 0x0 0x0 | ||
| 1020 | #define MX6SL_PAD_SD3_CMD__AUD5_RXC 0x284 0x58c 0x604 0x1 0x1 | ||
| 1021 | #define MX6SL_PAD_SD3_CMD__KEY_ROW5 0x284 0x58c 0x768 0x2 0x2 | ||
| 1022 | #define MX6SL_PAD_SD3_CMD__CSI_DATA11 0x284 0x58c 0x65c 0x3 0x2 | ||
| 1023 | #define MX6SL_PAD_SD3_CMD__USB_OTG2_ID 0x284 0x58c 0x5e0 0x4 0x3 | ||
| 1024 | #define MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x284 0x58c 0x000 0x5 0x0 | ||
| 1025 | #define MX6SL_PAD_SD3_CMD__USB_OTG2_PWR 0x284 0x58c 0x000 0x6 0x0 | ||
| 1026 | #define MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x288 0x590 0x000 0x0 0x0 | ||
| 1027 | #define MX6SL_PAD_SD3_DAT0__AUD5_RXD 0x288 0x590 0x5fc 0x1 0x1 | ||
| 1028 | #define MX6SL_PAD_SD3_DAT0__KEY_COL6 0x288 0x590 0x74c 0x2 0x2 | ||
| 1029 | #define MX6SL_PAD_SD3_DAT0__CSI_DATA12 0x288 0x590 0x660 0x3 0x1 | ||
| 1030 | #define MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x288 0x590 0x5dc 0x4 0x4 | ||
| 1031 | #define MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x288 0x590 0x000 0x5 0x0 | ||
| 1032 | #define MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x28c 0x594 0x000 0x0 0x0 | ||
| 1033 | #define MX6SL_PAD_SD3_DAT1__AUD5_TXC 0x28c 0x594 0x60c 0x1 0x1 | ||
| 1034 | #define MX6SL_PAD_SD3_DAT1__KEY_ROW6 0x28c 0x594 0x76c 0x2 0x2 | ||
| 1035 | #define MX6SL_PAD_SD3_DAT1__CSI_DATA13 0x28c 0x594 0x664 0x3 0x1 | ||
| 1036 | #define MX6SL_PAD_SD3_DAT1__SD1_VSELECT 0x28c 0x594 0x000 0x4 0x0 | ||
| 1037 | #define MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x28c 0x594 0x000 0x5 0x0 | ||
| 1038 | #define MX6SL_PAD_SD3_DAT1__JTAG_DE_B 0x28c 0x594 0x000 0x6 0x0 | ||
| 1039 | #define MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x290 0x598 0x000 0x0 0x0 | ||
| 1040 | #define MX6SL_PAD_SD3_DAT2__AUD5_TXFS 0x290 0x598 0x610 0x1 0x1 | ||
| 1041 | #define MX6SL_PAD_SD3_DAT2__KEY_COL7 0x290 0x598 0x750 0x2 0x2 | ||
| 1042 | #define MX6SL_PAD_SD3_DAT2__CSI_DATA14 0x290 0x598 0x668 0x3 0x1 | ||
| 1043 | #define MX6SL_PAD_SD3_DAT2__EPIT1_OUT 0x290 0x598 0x000 0x4 0x0 | ||
| 1044 | #define MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x290 0x598 0x000 0x5 0x0 | ||
| 1045 | #define MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x290 0x598 0x820 0x6 0x3 | ||
| 1046 | #define MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x294 0x59c 0x000 0x0 0x0 | ||
| 1047 | #define MX6SL_PAD_SD3_DAT3__AUD5_TXD 0x294 0x59c 0x600 0x1 0x1 | ||
| 1048 | #define MX6SL_PAD_SD3_DAT3__KEY_ROW7 0x294 0x59c 0x770 0x2 0x2 | ||
| 1049 | #define MX6SL_PAD_SD3_DAT3__CSI_DATA15 0x294 0x59c 0x66c 0x3 0x1 | ||
| 1050 | #define MX6SL_PAD_SD3_DAT3__EPIT2_OUT 0x294 0x59c 0x000 0x4 0x0 | ||
| 1051 | #define MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x294 0x59c 0x000 0x5 0x0 | ||
| 1052 | #define MX6SL_PAD_SD3_DAT3__USB_OTG1_OC 0x294 0x59c 0x824 0x6 0x2 | ||
| 1053 | #define MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x298 0x5a0 0x7fc 0x0 0x0 | ||
| 1054 | #define MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x298 0x5a0 0x000 0x0 0x0 | ||
| 1055 | #define MX6SL_PAD_UART1_RXD__PWM1_OUT 0x298 0x5a0 0x000 0x1 0x0 | ||
| 1056 | #define MX6SL_PAD_UART1_RXD__UART4_RX_DATA 0x298 0x5a0 0x814 0x2 0x6 | ||
| 1057 | #define MX6SL_PAD_UART1_RXD__UART4_TX_DATA 0x298 0x5a0 0x000 0x2 0x0 | ||
| 1058 | #define MX6SL_PAD_UART1_RXD__FEC_COL 0x298 0x5a0 0x6f0 0x3 0x2 | ||
| 1059 | #define MX6SL_PAD_UART1_RXD__UART5_RX_DATA 0x298 0x5a0 0x81c 0x4 0x6 | ||
| 1060 | #define MX6SL_PAD_UART1_RXD__UART5_TX_DATA 0x298 0x5a0 0x000 0x4 0x0 | ||
| 1061 | #define MX6SL_PAD_UART1_RXD__GPIO3_IO16 0x298 0x5a0 0x000 0x5 0x0 | ||
| 1062 | #define MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x29c 0x5a4 0x000 0x0 0x0 | ||
| 1063 | #define MX6SL_PAD_UART1_TXD__UART1_RX_DATA 0x29c 0x5a4 0x7fc 0x0 0x1 | ||
| 1064 | #define MX6SL_PAD_UART1_TXD__PWM2_OUT 0x29c 0x5a4 0x000 0x1 0x0 | ||
| 1065 | #define MX6SL_PAD_UART1_TXD__UART4_TX_DATA 0x29c 0x5a4 0x000 0x2 0x0 | ||
| 1066 | #define MX6SL_PAD_UART1_TXD__UART4_RX_DATA 0x29c 0x5a4 0x814 0x2 0x7 | ||
| 1067 | #define MX6SL_PAD_UART1_TXD__FEC_RX_CLK 0x29c 0x5a4 0x700 0x3 0x2 | ||
| 1068 | #define MX6SL_PAD_UART1_TXD__UART5_TX_DATA 0x29c 0x5a4 0x000 0x4 0x0 | ||
| 1069 | #define MX6SL_PAD_UART1_TXD__UART5_RX_DATA 0x29c 0x5a4 0x81c 0x4 0x7 | ||
| 1070 | #define MX6SL_PAD_UART1_TXD__GPIO3_IO17 0x29c 0x5a4 0x000 0x5 0x0 | ||
| 1071 | #define MX6SL_PAD_UART1_TXD__UART5_DCD_B 0x29c 0x5a4 0x000 0x7 0x0 | ||
| 1072 | #define MX6SL_PAD_WDOG_B__WDOG1_B 0x2a0 0x5a8 0x000 0x0 0x0 | ||
| 1073 | #define MX6SL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x2a0 0x5a8 0x000 0x1 0x0 | ||
| 1074 | #define MX6SL_PAD_WDOG_B__UART5_RI_B 0x2a0 0x5a8 0x000 0x2 0x0 | ||
| 1075 | #define MX6SL_PAD_WDOG_B__GPIO3_IO18 0x2a0 0x5a8 0x000 0x5 0x0 | ||
| 1076 | |||
| 1077 | #endif /* __DTS_IMX6SL_PINFUNC_H */ | ||
diff --git a/arch/arm/boot/dts/include/dt-bindings b/arch/arm/boot/dts/include/dt-bindings new file mode 120000 index 000000000000..08c00e4972fa --- /dev/null +++ b/arch/arm/boot/dts/include/dt-bindings | |||
| @@ -0,0 +1 @@ | |||
| ../../../../../include/dt-bindings \ No newline at end of file | |||
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index 192cf76fbf93..23991e45bc55 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi | |||
| @@ -49,6 +49,12 @@ | |||
| 49 | }; | 49 | }; |
| 50 | }; | 50 | }; |
| 51 | 51 | ||
| 52 | thermal@10078 { | ||
| 53 | compatible = "marvell,kirkwood-thermal"; | ||
| 54 | reg = <0x10078 0x4>; | ||
| 55 | status = "okay"; | ||
| 56 | }; | ||
| 57 | |||
| 52 | i2c@11100 { | 58 | i2c@11100 { |
| 53 | compatible = "marvell,mv64xxx-i2c"; | 59 | compatible = "marvell,mv64xxx-i2c"; |
| 54 | reg = <0x11100 0x20>; | 60 | reg = <0x11100 0x20>; |
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index 9555a86297c2..44fd97dfc1f3 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts | |||
| @@ -69,6 +69,10 @@ | |||
| 69 | status = "okay"; | 69 | status = "okay"; |
| 70 | nr-ports = <1>; | 70 | nr-ports = <1>; |
| 71 | }; | 71 | }; |
| 72 | |||
| 73 | mvsdio@90000 { | ||
| 74 | status = "okay"; | ||
| 75 | }; | ||
| 72 | }; | 76 | }; |
| 73 | 77 | ||
| 74 | gpio-leds { | 78 | gpio-leds { |
diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts new file mode 100644 index 000000000000..317300875f34 --- /dev/null +++ b/arch/arm/boot/dts/mpa1600.dts | |||
| @@ -0,0 +1,69 @@ | |||
| 1 | /* | ||
| 2 | * mpa1600.dts - Device Tree file for Phontech MPA 1600 | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Joachim Eastwood <manabian@gmail.com> | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 only | ||
| 7 | */ | ||
| 8 | /dts-v1/; | ||
| 9 | /include/ "at91rm9200.dtsi" | ||
| 10 | |||
| 11 | / { | ||
| 12 | model = "Phontech MPA 1600"; | ||
| 13 | compatible = "phontech,mpa1600", "atmel,at91rm9200"; | ||
| 14 | |||
| 15 | memory { | ||
| 16 | reg = <0x20000000 0x4000000>; | ||
| 17 | }; | ||
| 18 | |||
| 19 | clocks { | ||
| 20 | #address-cells = <1>; | ||
| 21 | #size-cells = <1>; | ||
| 22 | ranges; | ||
| 23 | |||
| 24 | main_clock: clock@0 { | ||
| 25 | compatible = "atmel,osc", "fixed-clock"; | ||
| 26 | clock-frequency = <18432000>; | ||
| 27 | }; | ||
| 28 | }; | ||
| 29 | |||
| 30 | ahb { | ||
| 31 | apb { | ||
| 32 | dbgu: serial@fffff200 { | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | macb0: ethernet@fffbc000 { | ||
| 37 | phy-mode = "rmii"; | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | ssc0: ssc@fffd0000 { | ||
| 42 | status = "okay"; | ||
| 43 | }; | ||
| 44 | |||
| 45 | ssc1: ssc@fffd4000 { | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
| 48 | }; | ||
| 49 | |||
| 50 | usb0: ohci@00300000 { | ||
| 51 | num-ports = <1>; | ||
| 52 | status = "okay"; | ||
| 53 | }; | ||
| 54 | }; | ||
| 55 | |||
| 56 | i2c@0 { | ||
| 57 | status = "okay"; | ||
| 58 | }; | ||
| 59 | |||
| 60 | gpio_keys { | ||
| 61 | compatible = "gpio-keys"; | ||
| 62 | |||
| 63 | monitor_mute { | ||
| 64 | label = "Monitor mute"; | ||
| 65 | gpios = <&pioC 1 1>; | ||
| 66 | linux,code = <113>; | ||
| 67 | }; | ||
| 68 | }; | ||
| 69 | }; | ||
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts index 31f2157cd7d7..9bf49b3826ea 100644 --- a/arch/arm/boot/dts/msm8660-surf.dts +++ b/arch/arm/boot/dts/msm8660-surf.dts | |||
| @@ -16,19 +16,13 @@ | |||
| 16 | }; | 16 | }; |
| 17 | 17 | ||
| 18 | timer@2000004 { | 18 | timer@2000004 { |
| 19 | compatible = "qcom,msm-gpt", "qcom,msm-timer"; | 19 | compatible = "qcom,scss-timer", "qcom,msm-timer"; |
| 20 | interrupts = <1 1 0x301>; | 20 | interrupts = <1 0 0x301>, |
| 21 | reg = <0x02000004 0x10>; | 21 | <1 1 0x301>, |
| 22 | clock-frequency = <32768>; | 22 | <1 2 0x301>; |
| 23 | cpu-offset = <0x40000>; | 23 | reg = <0x02000000 0x100>; |
| 24 | }; | 24 | clock-frequency = <27000000>, |
| 25 | 25 | <32768>; | |
| 26 | timer@2000024 { | ||
| 27 | compatible = "qcom,msm-dgt", "qcom,msm-timer"; | ||
| 28 | interrupts = <1 0 0x301>; | ||
| 29 | reg = <0x02000024 0x10>, | ||
| 30 | <0x02000034 0x4>; | ||
| 31 | clock-frequency = <6750000>; | ||
| 32 | cpu-offset = <0x40000>; | 26 | cpu-offset = <0x40000>; |
| 33 | }; | 27 | }; |
| 34 | 28 | ||
| @@ -38,4 +32,10 @@ | |||
| 38 | <0x19c00000 0x1000>; | 32 | <0x19c00000 0x1000>; |
| 39 | interrupts = <0 195 0x0>; | 33 | interrupts = <0 195 0x0>; |
| 40 | }; | 34 | }; |
| 35 | |||
| 36 | qcom,ssbi@500000 { | ||
| 37 | compatible = "qcom,ssbi"; | ||
| 38 | reg = <0x500000 0x1000>; | ||
| 39 | qcom,controller-type = "pmic-arbiter"; | ||
| 40 | }; | ||
| 41 | }; | 41 | }; |
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts index 9e621b5ad3dd..2e4d87a125d6 100644 --- a/arch/arm/boot/dts/msm8960-cdp.dts +++ b/arch/arm/boot/dts/msm8960-cdp.dts | |||
| @@ -15,20 +15,14 @@ | |||
| 15 | < 0x02002000 0x1000 >; | 15 | < 0x02002000 0x1000 >; |
| 16 | }; | 16 | }; |
| 17 | 17 | ||
| 18 | timer@200a004 { | 18 | timer@200a000 { |
| 19 | compatible = "qcom,msm-gpt", "qcom,msm-timer"; | 19 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; |
| 20 | interrupts = <1 2 0x301>; | 20 | interrupts = <1 1 0x301>, |
| 21 | reg = <0x0200a004 0x10>; | 21 | <1 2 0x301>, |
| 22 | clock-frequency = <32768>; | 22 | <1 3 0x301>; |
| 23 | cpu-offset = <0x80000>; | 23 | reg = <0x0200a000 0x100>; |
| 24 | }; | 24 | clock-frequency = <27000000>, |
| 25 | 25 | <32768>; | |
| 26 | timer@200a024 { | ||
| 27 | compatible = "qcom,msm-dgt", "qcom,msm-timer"; | ||
| 28 | interrupts = <1 1 0x301>; | ||
| 29 | reg = <0x0200a024 0x10>, | ||
| 30 | <0x0200a034 0x4>; | ||
| 31 | clock-frequency = <6750000>; | ||
| 32 | cpu-offset = <0x80000>; | 26 | cpu-offset = <0x80000>; |
| 33 | }; | 27 | }; |
| 34 | 28 | ||
| @@ -38,4 +32,10 @@ | |||
| 38 | <0x16400000 0x1000>; | 32 | <0x16400000 0x1000>; |
| 39 | interrupts = <0 154 0x0>; | 33 | interrupts = <0 154 0x0>; |
| 40 | }; | 34 | }; |
| 35 | |||
| 36 | qcom,ssbi@500000 { | ||
| 37 | compatible = "qcom,ssbi"; | ||
| 38 | reg = <0x500000 0x1000>; | ||
| 39 | qcom,controller-type = "pmic-arbiter"; | ||
| 40 | }; | ||
| 41 | }; | 41 | }; |
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index f7bec3b1ba32..892c64e3f1e1 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi | |||
| @@ -74,6 +74,20 @@ | |||
| 74 | status = "okay"; | 74 | status = "okay"; |
| 75 | }; | 75 | }; |
| 76 | 76 | ||
| 77 | ehci@50000 { | ||
| 78 | compatible = "marvell,orion-ehci"; | ||
| 79 | reg = <0x50000 0x1000>; | ||
| 80 | interrupts = <17>; | ||
| 81 | status = "disabled"; | ||
| 82 | }; | ||
| 83 | |||
| 84 | ehci@a0000 { | ||
| 85 | compatible = "marvell,orion-ehci"; | ||
| 86 | reg = <0xa0000 0x1000>; | ||
| 87 | interrupts = <12>; | ||
| 88 | status = "disabled"; | ||
| 89 | }; | ||
| 90 | |||
| 77 | sata@80000 { | 91 | sata@80000 { |
| 78 | compatible = "marvell,orion-sata"; | 92 | compatible = "marvell,orion-sata"; |
| 79 | reg = <0x80000 0x5000>; | 93 | reg = <0x80000 0x5000>; |
| @@ -91,6 +105,25 @@ | |||
| 91 | status = "disabled"; | 105 | status = "disabled"; |
| 92 | }; | 106 | }; |
| 93 | 107 | ||
| 108 | xor@60900 { | ||
| 109 | compatible = "marvell,orion-xor"; | ||
| 110 | reg = <0x60900 0x100 | ||
| 111 | 0x60b00 0x100>; | ||
| 112 | status = "okay"; | ||
| 113 | |||
| 114 | xor00 { | ||
| 115 | interrupts = <30>; | ||
| 116 | dmacap,memcpy; | ||
| 117 | dmacap,xor; | ||
| 118 | }; | ||
| 119 | xor01 { | ||
| 120 | interrupts = <31>; | ||
| 121 | dmacap,memcpy; | ||
| 122 | dmacap,xor; | ||
| 123 | dmacap,memset; | ||
| 124 | }; | ||
| 125 | }; | ||
| 126 | |||
| 94 | crypto@90000 { | 127 | crypto@90000 { |
| 95 | compatible = "marvell,orion-crypto"; | 128 | compatible = "marvell,orion-crypto"; |
| 96 | reg = <0x90000 0x10000>, | 129 | reg = <0x90000 0x10000>, |
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi new file mode 100644 index 000000000000..fe5c6f213271 --- /dev/null +++ b/arch/arm/boot/dts/r8a7779.dtsi | |||
| @@ -0,0 +1,98 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree Source for Renesas r8a7779 | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Renesas Solutions Corp. | ||
| 5 | * Copyright (C) 2013 Simon Horman | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public License | ||
| 8 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 9 | * kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /include/ "skeleton.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | compatible = "renesas,r8a7779"; | ||
| 16 | |||
| 17 | cpus { | ||
| 18 | #address-cells = <1>; | ||
| 19 | #size-cells = <0>; | ||
| 20 | |||
| 21 | cpu@0 { | ||
| 22 | device_type = "cpu"; | ||
| 23 | compatible = "arm,cortex-a9"; | ||
| 24 | reg = <0>; | ||
| 25 | }; | ||
| 26 | cpu@1 { | ||
| 27 | device_type = "cpu"; | ||
| 28 | compatible = "arm,cortex-a9"; | ||
| 29 | reg = <1>; | ||
| 30 | }; | ||
| 31 | cpu@2 { | ||
| 32 | device_type = "cpu"; | ||
| 33 | compatible = "arm,cortex-a9"; | ||
| 34 | reg = <2>; | ||
| 35 | }; | ||
| 36 | cpu@3 { | ||
| 37 | device_type = "cpu"; | ||
| 38 | compatible = "arm,cortex-a9"; | ||
| 39 | reg = <3>; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | |||
| 43 | gic: interrupt-controller@f0001000 { | ||
| 44 | compatible = "arm,cortex-a9-gic"; | ||
| 45 | #interrupt-cells = <3>; | ||
| 46 | interrupt-controller; | ||
| 47 | reg = <0xf0001000 0x1000>, | ||
| 48 | <0xf0000100 0x100>; | ||
| 49 | }; | ||
| 50 | |||
| 51 | i2c0: i2c@0xffc70000 { | ||
| 52 | #address-cells = <1>; | ||
| 53 | #size-cells = <0>; | ||
| 54 | compatible = "renesas,rmobile-iic"; | ||
| 55 | reg = <0xffc70000 0x1000>; | ||
| 56 | interrupt-parent = <&gic>; | ||
| 57 | interrupts = <0 79 0x4>; | ||
| 58 | }; | ||
| 59 | |||
| 60 | i2c1: i2c@0xffc71000 { | ||
| 61 | #address-cells = <1>; | ||
| 62 | #size-cells = <0>; | ||
| 63 | compatible = "renesas,rmobile-iic"; | ||
| 64 | reg = <0xffc71000 0x1000>; | ||
| 65 | interrupt-parent = <&gic>; | ||
| 66 | interrupts = <0 82 0x4>; | ||
| 67 | }; | ||
| 68 | |||
| 69 | i2c2: i2c@0xffc72000 { | ||
| 70 | #address-cells = <1>; | ||
| 71 | #size-cells = <0>; | ||
| 72 | compatible = "renesas,rmobile-iic"; | ||
| 73 | reg = <0xffc72000 0x1000>; | ||
| 74 | interrupt-parent = <&gic>; | ||
| 75 | interrupts = <0 80 0x4>; | ||
| 76 | }; | ||
| 77 | |||
| 78 | i2c3: i2c@0xffc73000 { | ||
| 79 | #address-cells = <1>; | ||
| 80 | #size-cells = <0>; | ||
| 81 | compatible = "renesas,rmobile-iic"; | ||
| 82 | reg = <0xffc73000 0x1000>; | ||
| 83 | interrupt-parent = <&gic>; | ||
| 84 | interrupts = <0 81 0x4>; | ||
| 85 | }; | ||
| 86 | |||
| 87 | thermal@ffc48000 { | ||
| 88 | compatible = "renesas,rcar-thermal"; | ||
| 89 | reg = <0xffc48000 0x38>; | ||
| 90 | }; | ||
| 91 | |||
| 92 | sata: sata@fc600000 { | ||
| 93 | compatible = "renesas,rcar-sata"; | ||
| 94 | reg = <0xfc600000 0x2000>; | ||
| 95 | interrupt-parent = <&gic>; | ||
| 96 | interrupts = <0 100 0x4>; | ||
| 97 | }; | ||
| 98 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi new file mode 100644 index 000000000000..39b0458d365a --- /dev/null +++ b/arch/arm/boot/dts/sama5d3.dtsi | |||
| @@ -0,0 +1,1031 @@ | |||
| 1 | /* | ||
| 2 | * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC | ||
| 3 | * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC | ||
| 4 | * | ||
| 5 | * Copyright (C) 2013 Atmel, | ||
| 6 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 7 | * | ||
| 8 | * Licensed under GPLv2 or later. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /include/ "skeleton.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Atmel SAMA5D3 family SoC"; | ||
| 15 | compatible = "atmel,sama5d3", "atmel,sama5"; | ||
| 16 | interrupt-parent = <&aic>; | ||
| 17 | |||
| 18 | aliases { | ||
| 19 | serial0 = &dbgu; | ||
| 20 | serial1 = &usart0; | ||
| 21 | serial2 = &usart1; | ||
| 22 | serial3 = &usart2; | ||
| 23 | serial4 = &usart3; | ||
| 24 | gpio0 = &pioA; | ||
| 25 | gpio1 = &pioB; | ||
| 26 | gpio2 = &pioC; | ||
| 27 | gpio3 = &pioD; | ||
| 28 | gpio4 = &pioE; | ||
| 29 | tcb0 = &tcb0; | ||
| 30 | tcb1 = &tcb1; | ||
| 31 | i2c0 = &i2c0; | ||
| 32 | i2c1 = &i2c1; | ||
| 33 | i2c2 = &i2c2; | ||
| 34 | ssc0 = &ssc0; | ||
| 35 | ssc1 = &ssc1; | ||
| 36 | }; | ||
| 37 | cpus { | ||
| 38 | cpu@0 { | ||
| 39 | compatible = "arm,cortex-a5"; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | |||
| 43 | memory { | ||
| 44 | reg = <0x20000000 0x8000000>; | ||
| 45 | }; | ||
| 46 | |||
| 47 | ahb { | ||
| 48 | compatible = "simple-bus"; | ||
| 49 | #address-cells = <1>; | ||
| 50 | #size-cells = <1>; | ||
| 51 | ranges; | ||
| 52 | |||
| 53 | apb { | ||
| 54 | compatible = "simple-bus"; | ||
| 55 | #address-cells = <1>; | ||
| 56 | #size-cells = <1>; | ||
| 57 | ranges; | ||
| 58 | |||
| 59 | mmc0: mmc@f0000000 { | ||
| 60 | compatible = "atmel,hsmci"; | ||
| 61 | reg = <0xf0000000 0x600>; | ||
| 62 | interrupts = <21 4 0>; | ||
| 63 | pinctrl-names = "default"; | ||
| 64 | pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; | ||
| 65 | status = "disabled"; | ||
| 66 | #address-cells = <1>; | ||
| 67 | #size-cells = <0>; | ||
| 68 | }; | ||
| 69 | |||
| 70 | spi0: spi@f0004000 { | ||
| 71 | #address-cells = <1>; | ||
| 72 | #size-cells = <0>; | ||
| 73 | compatible = "atmel,at91sam9x5-spi"; | ||
| 74 | reg = <0xf0004000 0x100>; | ||
| 75 | interrupts = <24 4 3>; | ||
| 76 | cs-gpios = <&pioD 13 0 | ||
| 77 | &pioD 14 0 /* conflicts with SCK0 and CANRX0 */ | ||
| 78 | &pioD 15 0 /* conflicts with CTS0 and CANTX0 */ | ||
| 79 | &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */ | ||
| 80 | >; | ||
| 81 | pinctrl-names = "default"; | ||
| 82 | pinctrl-0 = <&pinctrl_spi0>; | ||
| 83 | status = "disabled"; | ||
| 84 | }; | ||
| 85 | |||
| 86 | ssc0: ssc@f0008000 { | ||
| 87 | compatible = "atmel,at91sam9g45-ssc"; | ||
| 88 | reg = <0xf0008000 0x4000>; | ||
| 89 | interrupts = <38 4 4>; | ||
| 90 | pinctrl-names = "default"; | ||
| 91 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | ||
| 92 | status = "disabled"; | ||
| 93 | }; | ||
| 94 | |||
| 95 | can0: can@f000c000 { | ||
| 96 | compatible = "atmel,at91sam9x5-can"; | ||
| 97 | reg = <0xf000c000 0x300>; | ||
| 98 | interrupts = <40 4 3>; | ||
| 99 | pinctrl-names = "default"; | ||
| 100 | pinctrl-0 = <&pinctrl_can0_rx_tx>; | ||
| 101 | status = "disabled"; | ||
| 102 | }; | ||
| 103 | |||
| 104 | tcb0: timer@f0010000 { | ||
| 105 | compatible = "atmel,at91sam9x5-tcb"; | ||
| 106 | reg = <0xf0010000 0x100>; | ||
| 107 | interrupts = <26 4 0>; | ||
| 108 | }; | ||
| 109 | |||
| 110 | i2c0: i2c@f0014000 { | ||
| 111 | compatible = "atmel,at91sam9x5-i2c"; | ||
| 112 | reg = <0xf0014000 0x4000>; | ||
| 113 | interrupts = <18 4 6>; | ||
| 114 | pinctrl-names = "default"; | ||
| 115 | pinctrl-0 = <&pinctrl_i2c0>; | ||
| 116 | #address-cells = <1>; | ||
| 117 | #size-cells = <0>; | ||
| 118 | status = "disabled"; | ||
| 119 | }; | ||
| 120 | |||
| 121 | i2c1: i2c@f0018000 { | ||
| 122 | compatible = "atmel,at91sam9x5-i2c"; | ||
| 123 | reg = <0xf0018000 0x4000>; | ||
| 124 | interrupts = <19 4 6>; | ||
| 125 | pinctrl-names = "default"; | ||
| 126 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 127 | #address-cells = <1>; | ||
| 128 | #size-cells = <0>; | ||
| 129 | status = "disabled"; | ||
| 130 | }; | ||
| 131 | |||
| 132 | usart0: serial@f001c000 { | ||
| 133 | compatible = "atmel,at91sam9260-usart"; | ||
| 134 | reg = <0xf001c000 0x100>; | ||
| 135 | interrupts = <12 4 5>; | ||
| 136 | pinctrl-names = "default"; | ||
| 137 | pinctrl-0 = <&pinctrl_usart0>; | ||
| 138 | status = "disabled"; | ||
| 139 | }; | ||
| 140 | |||
| 141 | usart1: serial@f0020000 { | ||
| 142 | compatible = "atmel,at91sam9260-usart"; | ||
| 143 | reg = <0xf0020000 0x100>; | ||
| 144 | interrupts = <13 4 5>; | ||
| 145 | pinctrl-names = "default"; | ||
| 146 | pinctrl-0 = <&pinctrl_usart1>; | ||
| 147 | status = "disabled"; | ||
| 148 | }; | ||
| 149 | |||
| 150 | macb0: ethernet@f0028000 { | ||
| 151 | compatible = "cnds,pc302-gem", "cdns,gem"; | ||
| 152 | reg = <0xf0028000 0x100>; | ||
| 153 | interrupts = <34 4 3>; | ||
| 154 | pinctrl-names = "default"; | ||
| 155 | pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; | ||
| 156 | status = "disabled"; | ||
| 157 | }; | ||
| 158 | |||
| 159 | isi: isi@f0034000 { | ||
| 160 | compatible = "atmel,at91sam9g45-isi"; | ||
| 161 | reg = <0xf0034000 0x4000>; | ||
| 162 | interrupts = <37 4 5>; | ||
| 163 | status = "disabled"; | ||
| 164 | }; | ||
| 165 | |||
| 166 | mmc1: mmc@f8000000 { | ||
| 167 | compatible = "atmel,hsmci"; | ||
| 168 | reg = <0xf8000000 0x600>; | ||
| 169 | interrupts = <22 4 0>; | ||
| 170 | pinctrl-names = "default"; | ||
| 171 | pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; | ||
| 172 | status = "disabled"; | ||
| 173 | #address-cells = <1>; | ||
| 174 | #size-cells = <0>; | ||
| 175 | }; | ||
| 176 | |||
| 177 | mmc2: mmc@f8004000 { | ||
| 178 | compatible = "atmel,hsmci"; | ||
| 179 | reg = <0xf8004000 0x600>; | ||
| 180 | interrupts = <23 4 0>; | ||
| 181 | pinctrl-names = "default"; | ||
| 182 | pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; | ||
| 183 | status = "disabled"; | ||
| 184 | #address-cells = <1>; | ||
| 185 | #size-cells = <0>; | ||
| 186 | }; | ||
| 187 | |||
| 188 | spi1: spi@f8008000 { | ||
| 189 | #address-cells = <1>; | ||
| 190 | #size-cells = <0>; | ||
| 191 | compatible = "atmel,at91sam9x5-spi"; | ||
| 192 | reg = <0xf8008000 0x100>; | ||
| 193 | interrupts = <25 4 3>; | ||
| 194 | cs-gpios = <&pioC 25 0 | ||
| 195 | &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */ | ||
| 196 | &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */ | ||
| 197 | &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */ | ||
| 198 | >; | ||
| 199 | pinctrl-names = "default"; | ||
| 200 | pinctrl-0 = <&pinctrl_spi1>; | ||
| 201 | status = "disabled"; | ||
| 202 | }; | ||
| 203 | |||
| 204 | ssc1: ssc@f800c000 { | ||
| 205 | compatible = "atmel,at91sam9g45-ssc"; | ||
| 206 | reg = <0xf800c000 0x4000>; | ||
| 207 | interrupts = <39 4 4>; | ||
| 208 | pinctrl-names = "default"; | ||
| 209 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | ||
| 210 | status = "disabled"; | ||
| 211 | }; | ||
| 212 | |||
| 213 | can1: can@f8010000 { | ||
| 214 | compatible = "atmel,at91sam9x5-can"; | ||
| 215 | reg = <0xf8010000 0x300>; | ||
| 216 | interrupts = <41 4 3>; | ||
| 217 | pinctrl-names = "default"; | ||
| 218 | pinctrl-0 = <&pinctrl_can1_rx_tx>; | ||
| 219 | }; | ||
| 220 | |||
| 221 | tcb1: timer@f8014000 { | ||
| 222 | compatible = "atmel,at91sam9x5-tcb"; | ||
| 223 | reg = <0xf8014000 0x100>; | ||
| 224 | interrupts = <27 4 0>; | ||
| 225 | }; | ||
| 226 | |||
| 227 | adc0: adc@f8018000 { | ||
| 228 | compatible = "atmel,at91sam9260-adc"; | ||
| 229 | reg = <0xf8018000 0x100>; | ||
| 230 | interrupts = <29 4 5>; | ||
| 231 | pinctrl-names = "default"; | ||
| 232 | pinctrl-0 = < | ||
| 233 | &pinctrl_adc0_adtrg | ||
| 234 | &pinctrl_adc0_ad0 | ||
| 235 | &pinctrl_adc0_ad1 | ||
| 236 | &pinctrl_adc0_ad2 | ||
| 237 | &pinctrl_adc0_ad3 | ||
| 238 | &pinctrl_adc0_ad4 | ||
| 239 | &pinctrl_adc0_ad5 | ||
| 240 | &pinctrl_adc0_ad6 | ||
| 241 | &pinctrl_adc0_ad7 | ||
| 242 | &pinctrl_adc0_ad8 | ||
| 243 | &pinctrl_adc0_ad9 | ||
| 244 | &pinctrl_adc0_ad10 | ||
| 245 | &pinctrl_adc0_ad11 | ||
| 246 | >; | ||
| 247 | atmel,adc-channel-base = <0x50>; | ||
| 248 | atmel,adc-channels-used = <0xfff>; | ||
| 249 | atmel,adc-drdy-mask = <0x1000000>; | ||
| 250 | atmel,adc-num-channels = <12>; | ||
| 251 | atmel,adc-startup-time = <40>; | ||
| 252 | atmel,adc-status-register = <0x30>; | ||
| 253 | atmel,adc-trigger-register = <0xc0>; | ||
| 254 | atmel,adc-use-external; | ||
| 255 | atmel,adc-vref = <3000>; | ||
| 256 | atmel,adc-res = <10 12>; | ||
| 257 | atmel,adc-res-names = "lowres", "highres"; | ||
| 258 | status = "disabled"; | ||
| 259 | |||
| 260 | trigger@0 { | ||
| 261 | trigger-name = "external-rising"; | ||
| 262 | trigger-value = <0x1>; | ||
| 263 | trigger-external; | ||
| 264 | }; | ||
| 265 | trigger@1 { | ||
| 266 | trigger-name = "external-falling"; | ||
| 267 | trigger-value = <0x2>; | ||
| 268 | trigger-external; | ||
| 269 | }; | ||
| 270 | trigger@2 { | ||
| 271 | trigger-name = "external-any"; | ||
| 272 | trigger-value = <0x3>; | ||
| 273 | trigger-external; | ||
| 274 | }; | ||
| 275 | trigger@3 { | ||
| 276 | trigger-name = "continuous"; | ||
| 277 | trigger-value = <0x6>; | ||
| 278 | }; | ||
| 279 | }; | ||
| 280 | |||
| 281 | tsadcc: tsadcc@f8018000 { | ||
| 282 | compatible = "atmel,at91sam9x5-tsadcc"; | ||
| 283 | reg = <0xf8018000 0x4000>; | ||
| 284 | interrupts = <29 4 5>; | ||
| 285 | atmel,tsadcc_clock = <300000>; | ||
| 286 | atmel,filtering_average = <0x03>; | ||
| 287 | atmel,pendet_debounce = <0x08>; | ||
| 288 | atmel,pendet_sensitivity = <0x02>; | ||
| 289 | atmel,ts_sample_hold_time = <0x0a>; | ||
| 290 | status = "disabled"; | ||
| 291 | }; | ||
| 292 | |||
| 293 | i2c2: i2c@f801c000 { | ||
| 294 | compatible = "atmel,at91sam9x5-i2c"; | ||
| 295 | reg = <0xf801c000 0x4000>; | ||
| 296 | interrupts = <20 4 6>; | ||
| 297 | #address-cells = <1>; | ||
| 298 | #size-cells = <0>; | ||
| 299 | status = "disabled"; | ||
| 300 | }; | ||
| 301 | |||
| 302 | usart2: serial@f8020000 { | ||
| 303 | compatible = "atmel,at91sam9260-usart"; | ||
| 304 | reg = <0xf8020000 0x100>; | ||
| 305 | interrupts = <14 4 5>; | ||
| 306 | pinctrl-names = "default"; | ||
| 307 | pinctrl-0 = <&pinctrl_usart2>; | ||
| 308 | status = "disabled"; | ||
| 309 | }; | ||
| 310 | |||
| 311 | usart3: serial@f8024000 { | ||
| 312 | compatible = "atmel,at91sam9260-usart"; | ||
| 313 | reg = <0xf8024000 0x100>; | ||
| 314 | interrupts = <15 4 5>; | ||
| 315 | pinctrl-names = "default"; | ||
| 316 | pinctrl-0 = <&pinctrl_usart3>; | ||
| 317 | status = "disabled"; | ||
| 318 | }; | ||
| 319 | |||
| 320 | macb1: ethernet@f802c000 { | ||
| 321 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | ||
| 322 | reg = <0xf802c000 0x100>; | ||
| 323 | interrupts = <35 4 3>; | ||
| 324 | pinctrl-names = "default"; | ||
| 325 | pinctrl-0 = <&pinctrl_macb1_rmii>; | ||
| 326 | status = "disabled"; | ||
| 327 | }; | ||
| 328 | |||
| 329 | sha@f8034000 { | ||
| 330 | compatible = "atmel,sam9g46-sha"; | ||
| 331 | reg = <0xf8034000 0x100>; | ||
| 332 | interrupts = <42 4 0>; | ||
| 333 | }; | ||
| 334 | |||
| 335 | aes@f8038000 { | ||
| 336 | compatible = "atmel,sam9g46-aes"; | ||
| 337 | reg = <0xf8038000 0x100>; | ||
| 338 | interrupts = <43 4 0>; | ||
| 339 | }; | ||
| 340 | |||
| 341 | tdes@f803c000 { | ||
| 342 | compatible = "atmel,sam9g46-tdes"; | ||
| 343 | reg = <0xf803c000 0x100>; | ||
| 344 | interrupts = <44 4 0>; | ||
| 345 | }; | ||
| 346 | |||
| 347 | dma0: dma-controller@ffffe600 { | ||
| 348 | compatible = "atmel,at91sam9g45-dma"; | ||
| 349 | reg = <0xffffe600 0x200>; | ||
| 350 | interrupts = <30 4 0>; | ||
| 351 | #dma-cells = <1>; | ||
| 352 | }; | ||
| 353 | |||
| 354 | dma1: dma-controller@ffffe800 { | ||
| 355 | compatible = "atmel,at91sam9g45-dma"; | ||
| 356 | reg = <0xffffe800 0x200>; | ||
| 357 | interrupts = <31 4 0>; | ||
| 358 | #dma-cells = <1>; | ||
| 359 | }; | ||
| 360 | |||
| 361 | ramc0: ramc@ffffea00 { | ||
| 362 | compatible = "atmel,at91sam9g45-ddramc"; | ||
| 363 | reg = <0xffffea00 0x200>; | ||
| 364 | }; | ||
| 365 | |||
| 366 | dbgu: serial@ffffee00 { | ||
| 367 | compatible = "atmel,at91sam9260-usart"; | ||
| 368 | reg = <0xffffee00 0x200>; | ||
| 369 | interrupts = <2 4 7>; | ||
| 370 | pinctrl-names = "default"; | ||
| 371 | pinctrl-0 = <&pinctrl_dbgu>; | ||
| 372 | status = "disabled"; | ||
| 373 | }; | ||
| 374 | |||
| 375 | aic: interrupt-controller@fffff000 { | ||
| 376 | #interrupt-cells = <3>; | ||
| 377 | compatible = "atmel,sama5d3-aic"; | ||
| 378 | interrupt-controller; | ||
| 379 | reg = <0xfffff000 0x200>; | ||
| 380 | atmel,external-irqs = <47>; | ||
| 381 | }; | ||
| 382 | |||
| 383 | pinctrl@fffff200 { | ||
| 384 | #address-cells = <1>; | ||
| 385 | #size-cells = <1>; | ||
| 386 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; | ||
| 387 | ranges = <0xfffff200 0xfffff200 0xa00>; | ||
| 388 | atmel,mux-mask = < | ||
| 389 | /* A B C */ | ||
| 390 | 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ | ||
| 391 | 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ | ||
| 392 | 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ | ||
| 393 | 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ | ||
| 394 | 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ | ||
| 395 | >; | ||
| 396 | |||
| 397 | /* shared pinctrl settings */ | ||
| 398 | adc0 { | ||
| 399 | pinctrl_adc0_adtrg: adc0_adtrg { | ||
| 400 | atmel,pins = | ||
| 401 | <3 19 0x1 0x0>; /* PD19 periph A ADTRG */ | ||
| 402 | }; | ||
| 403 | pinctrl_adc0_ad0: adc0_ad0 { | ||
| 404 | atmel,pins = | ||
| 405 | <3 20 0x1 0x0>; /* PD20 periph A AD0 */ | ||
| 406 | }; | ||
| 407 | pinctrl_adc0_ad1: adc0_ad1 { | ||
| 408 | atmel,pins = | ||
| 409 | <3 21 0x1 0x0>; /* PD21 periph A AD1 */ | ||
| 410 | }; | ||
| 411 | pinctrl_adc0_ad2: adc0_ad2 { | ||
| 412 | atmel,pins = | ||
| 413 | <3 22 0x1 0x0>; /* PD22 periph A AD2 */ | ||
| 414 | }; | ||
| 415 | pinctrl_adc0_ad3: adc0_ad3 { | ||
| 416 | atmel,pins = | ||
| 417 | <3 23 0x1 0x0>; /* PD23 periph A AD3 */ | ||
| 418 | }; | ||
| 419 | pinctrl_adc0_ad4: adc0_ad4 { | ||
| 420 | atmel,pins = | ||
| 421 | <3 24 0x1 0x0>; /* PD24 periph A AD4 */ | ||
| 422 | }; | ||
| 423 | pinctrl_adc0_ad5: adc0_ad5 { | ||
| 424 | atmel,pins = | ||
| 425 | <3 25 0x1 0x0>; /* PD25 periph A AD5 */ | ||
| 426 | }; | ||
| 427 | pinctrl_adc0_ad6: adc0_ad6 { | ||
| 428 | atmel,pins = | ||
| 429 | <3 26 0x1 0x0>; /* PD26 periph A AD6 */ | ||
| 430 | }; | ||
| 431 | pinctrl_adc0_ad7: adc0_ad7 { | ||
| 432 | atmel,pins = | ||
| 433 | <3 27 0x1 0x0>; /* PD27 periph A AD7 */ | ||
| 434 | }; | ||
| 435 | pinctrl_adc0_ad8: adc0_ad8 { | ||
| 436 | atmel,pins = | ||
| 437 | <3 28 0x1 0x0>; /* PD28 periph A AD8 */ | ||
| 438 | }; | ||
| 439 | pinctrl_adc0_ad9: adc0_ad9 { | ||
| 440 | atmel,pins = | ||
| 441 | <3 29 0x1 0x0>; /* PD29 periph A AD9 */ | ||
| 442 | }; | ||
| 443 | pinctrl_adc0_ad10: adc0_ad10 { | ||
| 444 | atmel,pins = | ||
| 445 | <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */ | ||
| 446 | }; | ||
| 447 | pinctrl_adc0_ad11: adc0_ad11 { | ||
| 448 | atmel,pins = | ||
| 449 | <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */ | ||
| 450 | }; | ||
| 451 | }; | ||
| 452 | |||
| 453 | can0 { | ||
| 454 | pinctrl_can0_rx_tx: can0_rx_tx { | ||
| 455 | atmel,pins = | ||
| 456 | <3 14 0x3 0x0 /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ | ||
| 457 | 3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ | ||
| 458 | }; | ||
| 459 | }; | ||
| 460 | |||
| 461 | can1 { | ||
| 462 | pinctrl_can1_rx_tx: can1_rx_tx { | ||
| 463 | atmel,pins = | ||
| 464 | <1 14 0x2 0x0 /* PB14 periph B RX, conflicts with GCRS */ | ||
| 465 | 1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */ | ||
| 466 | }; | ||
| 467 | }; | ||
| 468 | |||
| 469 | dbgu { | ||
| 470 | pinctrl_dbgu: dbgu-0 { | ||
| 471 | atmel,pins = | ||
| 472 | <1 30 0x1 0x0 /* PB30 periph A */ | ||
| 473 | 1 31 0x1 0x1>; /* PB31 periph A with pullup */ | ||
| 474 | }; | ||
| 475 | }; | ||
| 476 | |||
| 477 | i2c0 { | ||
| 478 | pinctrl_i2c0: i2c0-0 { | ||
| 479 | atmel,pins = | ||
| 480 | <0 30 0x1 0x0 /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ | ||
| 481 | 0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ | ||
| 482 | }; | ||
| 483 | }; | ||
| 484 | |||
| 485 | i2c1 { | ||
| 486 | pinctrl_i2c1: i2c1-0 { | ||
| 487 | atmel,pins = | ||
| 488 | <2 26 0x2 0x0 /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ | ||
| 489 | 2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ | ||
| 490 | }; | ||
| 491 | }; | ||
| 492 | |||
| 493 | isi { | ||
| 494 | pinctrl_isi: isi-0 { | ||
| 495 | atmel,pins = | ||
| 496 | <0 16 0x3 0x0 /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ | ||
| 497 | 0 17 0x3 0x0 /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ | ||
| 498 | 0 18 0x3 0x0 /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ | ||
| 499 | 0 19 0x3 0x0 /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ | ||
| 500 | 0 20 0x3 0x0 /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ | ||
| 501 | 0 21 0x3 0x0 /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ | ||
| 502 | 0 22 0x3 0x0 /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ | ||
| 503 | 0 23 0x3 0x0 /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ | ||
| 504 | 2 30 0x3 0x0 /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ | ||
| 505 | 0 31 0x3 0x0 /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ | ||
| 506 | 0 30 0x3 0x0 /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ | ||
| 507 | 2 29 0x3 0x0 /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ | ||
| 508 | 2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ | ||
| 509 | }; | ||
| 510 | pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 { | ||
| 511 | atmel,pins = | ||
| 512 | <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */ | ||
| 513 | }; | ||
| 514 | }; | ||
| 515 | |||
| 516 | lcd { | ||
| 517 | pinctrl_lcd: lcd-0 { | ||
| 518 | atmel,pins = | ||
| 519 | <0 24 0x1 0x0 /* PA24 periph A LCDPWM */ | ||
| 520 | 0 26 0x1 0x0 /* PA26 periph A LCDVSYNC */ | ||
| 521 | 0 27 0x1 0x0 /* PA27 periph A LCDHSYNC */ | ||
| 522 | 0 25 0x1 0x0 /* PA25 periph A LCDDISP */ | ||
| 523 | 0 29 0x1 0x0 /* PA29 periph A LCDDEN */ | ||
| 524 | 0 28 0x1 0x0 /* PA28 periph A LCDPCK */ | ||
| 525 | 0 0 0x1 0x0 /* PA0 periph A LCDD0 pin */ | ||
| 526 | 0 1 0x1 0x0 /* PA1 periph A LCDD1 pin */ | ||
| 527 | 0 2 0x1 0x0 /* PA2 periph A LCDD2 pin */ | ||
| 528 | 0 3 0x1 0x0 /* PA3 periph A LCDD3 pin */ | ||
| 529 | 0 4 0x1 0x0 /* PA4 periph A LCDD4 pin */ | ||
| 530 | 0 5 0x1 0x0 /* PA5 periph A LCDD5 pin */ | ||
| 531 | 0 6 0x1 0x0 /* PA6 periph A LCDD6 pin */ | ||
| 532 | 0 7 0x1 0x0 /* PA7 periph A LCDD7 pin */ | ||
| 533 | 0 8 0x1 0x0 /* PA8 periph A LCDD8 pin */ | ||
| 534 | 0 9 0x1 0x0 /* PA9 periph A LCDD9 pin */ | ||
| 535 | 0 10 0x1 0x0 /* PA10 periph A LCDD10 pin */ | ||
| 536 | 0 11 0x1 0x0 /* PA11 periph A LCDD11 pin */ | ||
| 537 | 0 12 0x1 0x0 /* PA12 periph A LCDD12 pin */ | ||
| 538 | 0 13 0x1 0x0 /* PA13 periph A LCDD13 pin */ | ||
| 539 | 0 14 0x1 0x0 /* PA14 periph A LCDD14 pin */ | ||
| 540 | 0 15 0x1 0x0 /* PA15 periph A LCDD15 pin */ | ||
| 541 | 2 14 0x3 0x0 /* PC14 periph C LCDD16 pin */ | ||
| 542 | 2 13 0x3 0x0 /* PC13 periph C LCDD17 pin */ | ||
| 543 | 2 12 0x3 0x0 /* PC12 periph C LCDD18 pin */ | ||
| 544 | 2 11 0x3 0x0 /* PC11 periph C LCDD19 pin */ | ||
| 545 | 2 10 0x3 0x0 /* PC10 periph C LCDD20 pin */ | ||
| 546 | 2 15 0x3 0x0 /* PC15 periph C LCDD21 pin */ | ||
| 547 | 4 27 0x3 0x0 /* PE27 periph C LCDD22 pin */ | ||
| 548 | 4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */ | ||
| 549 | }; | ||
| 550 | }; | ||
| 551 | |||
| 552 | macb0 { | ||
| 553 | pinctrl_macb0_data_rgmii: macb0_data_rgmii { | ||
| 554 | atmel,pins = | ||
| 555 | <1 0 0x1 0x0 /* PB0 periph A GTX0, conflicts with PWMH0 */ | ||
| 556 | 1 1 0x1 0x0 /* PB1 periph A GTX1, conflicts with PWML0 */ | ||
| 557 | 1 2 0x1 0x0 /* PB2 periph A GTX2, conflicts with TK1 */ | ||
| 558 | 1 3 0x1 0x0 /* PB3 periph A GTX3, conflicts with TF1 */ | ||
| 559 | 1 4 0x1 0x0 /* PB4 periph A GRX0, conflicts with PWMH1 */ | ||
| 560 | 1 5 0x1 0x0 /* PB5 periph A GRX1, conflicts with PWML1 */ | ||
| 561 | 1 6 0x1 0x0 /* PB6 periph A GRX2, conflicts with TD1 */ | ||
| 562 | 1 7 0x1 0x0>; /* PB7 periph A GRX3, conflicts with RK1 */ | ||
| 563 | }; | ||
| 564 | pinctrl_macb0_data_gmii: macb0_data_gmii { | ||
| 565 | atmel,pins = | ||
| 566 | <1 19 0x2 0x0 /* PB19 periph B GTX4, conflicts with MCI1_CDA */ | ||
| 567 | 1 20 0x2 0x0 /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ | ||
| 568 | 1 21 0x2 0x0 /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ | ||
| 569 | 1 22 0x2 0x0 /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ | ||
| 570 | 1 23 0x2 0x0 /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ | ||
| 571 | 1 24 0x2 0x0 /* PB24 periph B GRX5, conflicts with MCI1_CK */ | ||
| 572 | 1 25 0x2 0x0 /* PB25 periph B GRX6, conflicts with SCK1 */ | ||
| 573 | 1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */ | ||
| 574 | }; | ||
| 575 | pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { | ||
| 576 | atmel,pins = | ||
| 577 | <1 8 0x1 0x0 /* PB8 periph A GTXCK, conflicts with PWMH2 */ | ||
| 578 | 1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ | ||
| 579 | 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ | ||
| 580 | 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ | ||
| 581 | 1 16 0x1 0x0 /* PB16 periph A GMDC */ | ||
| 582 | 1 17 0x1 0x0 /* PB17 periph A GMDIO */ | ||
| 583 | 1 18 0x1 0x0>; /* PB18 periph A G125CK */ | ||
| 584 | }; | ||
| 585 | pinctrl_macb0_signal_gmii: macb0_signal_gmii { | ||
| 586 | atmel,pins = | ||
| 587 | <1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ | ||
| 588 | 1 10 0x1 0x0 /* PB10 periph A GTXER, conflicts with RF1 */ | ||
| 589 | 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ | ||
| 590 | 1 12 0x1 0x0 /* PB12 periph A GRXDV, conflicts with PWMH3 */ | ||
| 591 | 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ | ||
| 592 | 1 14 0x1 0x0 /* PB14 periph A GCRS, conflicts with CANRX1 */ | ||
| 593 | 1 15 0x1 0x0 /* PB15 periph A GCOL, conflicts with CANTX1 */ | ||
| 594 | 1 16 0x1 0x0 /* PB16 periph A GMDC */ | ||
| 595 | 1 17 0x1 0x0 /* PB17 periph A GMDIO */ | ||
| 596 | 1 27 0x2 0x0>; /* PB27 periph B G125CKO */ | ||
| 597 | }; | ||
| 598 | |||
| 599 | }; | ||
| 600 | |||
| 601 | macb1 { | ||
| 602 | pinctrl_macb1_rmii: macb1_rmii-0 { | ||
| 603 | atmel,pins = | ||
| 604 | <2 0 0x1 0x0 /* PC0 periph A ETX0, conflicts with TIOA3 */ | ||
| 605 | 2 1 0x1 0x0 /* PC1 periph A ETX1, conflicts with TIOB3 */ | ||
| 606 | 2 2 0x1 0x0 /* PC2 periph A ERX0, conflicts with TCLK3 */ | ||
| 607 | 2 3 0x1 0x0 /* PC3 periph A ERX1, conflicts with TIOA4 */ | ||
| 608 | 2 4 0x1 0x0 /* PC4 periph A ETXEN, conflicts with TIOB4 */ | ||
| 609 | 2 5 0x1 0x0 /* PC5 periph A ECRSDV,conflicts with TCLK4 */ | ||
| 610 | 2 6 0x1 0x0 /* PC6 periph A ERXER, conflicts with TIOA5 */ | ||
| 611 | 2 7 0x1 0x0 /* PC7 periph A EREFCK, conflicts with TIOB5 */ | ||
| 612 | 2 8 0x1 0x0 /* PC8 periph A EMDC, conflicts with TCLK5 */ | ||
| 613 | 2 9 0x1 0x0>; /* PC9 periph A EMDIO */ | ||
| 614 | }; | ||
| 615 | }; | ||
| 616 | |||
| 617 | mmc0 { | ||
| 618 | pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { | ||
| 619 | atmel,pins = | ||
| 620 | <3 9 0x1 0x0 /* PD9 periph A MCI0_CK */ | ||
| 621 | 3 0 0x1 0x1 /* PD0 periph A MCI0_CDA with pullup */ | ||
| 622 | 3 1 0x1 0x1>; /* PD1 periph A MCI0_DA0 with pullup */ | ||
| 623 | }; | ||
| 624 | pinctrl_mmc0_dat1_3: mmc0_dat1_3 { | ||
| 625 | atmel,pins = | ||
| 626 | <3 2 0x1 0x1 /* PD2 periph A MCI0_DA1 with pullup */ | ||
| 627 | 3 3 0x1 0x1 /* PD3 periph A MCI0_DA2 with pullup */ | ||
| 628 | 3 4 0x1 0x1>; /* PD4 periph A MCI0_DA3 with pullup */ | ||
| 629 | }; | ||
| 630 | pinctrl_mmc0_dat4_7: mmc0_dat4_7 { | ||
| 631 | atmel,pins = | ||
| 632 | <3 5 0x1 0x1 /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ | ||
| 633 | 3 6 0x1 0x1 /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ | ||
| 634 | 3 7 0x1 0x1 /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ | ||
| 635 | 3 8 0x1 0x1>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ | ||
| 636 | }; | ||
| 637 | }; | ||
| 638 | |||
| 639 | mmc1 { | ||
| 640 | pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { | ||
| 641 | atmel,pins = | ||
| 642 | <1 24 0x1 0x0 /* PB24 periph A MCI1_CK, conflicts with GRX5 */ | ||
| 643 | 1 19 0x1 0x1 /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ | ||
| 644 | 1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ | ||
| 645 | }; | ||
| 646 | pinctrl_mmc1_dat1_3: mmc1_dat1_3 { | ||
| 647 | atmel,pins = | ||
| 648 | <1 21 0x1 0x1 /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ | ||
| 649 | 1 22 0x1 0x1 /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ | ||
| 650 | 1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ | ||
| 651 | }; | ||
| 652 | }; | ||
| 653 | |||
| 654 | mmc2 { | ||
| 655 | pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { | ||
| 656 | atmel,pins = | ||
| 657 | <2 15 0x1 0x0 /* PC15 periph A MCI2_CK, conflicts with PCK2 */ | ||
| 658 | 2 10 0x1 0x1 /* PC10 periph A MCI2_CDA with pullup */ | ||
| 659 | 2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */ | ||
| 660 | }; | ||
| 661 | pinctrl_mmc2_dat1_3: mmc2_dat1_3 { | ||
| 662 | atmel,pins = | ||
| 663 | <2 12 0x1 0x0 /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ | ||
| 664 | 2 13 0x1 0x0 /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ | ||
| 665 | 2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ | ||
| 666 | }; | ||
| 667 | }; | ||
| 668 | |||
| 669 | nand0 { | ||
| 670 | pinctrl_nand0_ale_cle: nand0_ale_cle-0 { | ||
| 671 | atmel,pins = | ||
| 672 | <4 21 0x1 0x1 /* PE21 periph A with pullup */ | ||
| 673 | 4 22 0x1 0x1>; /* PE22 periph A with pullup */ | ||
| 674 | }; | ||
| 675 | }; | ||
| 676 | |||
| 677 | pioA: gpio@fffff200 { | ||
| 678 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 679 | reg = <0xfffff200 0x100>; | ||
| 680 | interrupts = <6 4 1>; | ||
| 681 | #gpio-cells = <2>; | ||
| 682 | gpio-controller; | ||
| 683 | interrupt-controller; | ||
| 684 | #interrupt-cells = <2>; | ||
| 685 | }; | ||
| 686 | |||
| 687 | pioB: gpio@fffff400 { | ||
| 688 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 689 | reg = <0xfffff400 0x100>; | ||
| 690 | interrupts = <7 4 1>; | ||
| 691 | #gpio-cells = <2>; | ||
| 692 | gpio-controller; | ||
| 693 | interrupt-controller; | ||
| 694 | #interrupt-cells = <2>; | ||
| 695 | }; | ||
| 696 | |||
| 697 | pioC: gpio@fffff600 { | ||
| 698 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 699 | reg = <0xfffff600 0x100>; | ||
| 700 | interrupts = <8 4 1>; | ||
| 701 | #gpio-cells = <2>; | ||
| 702 | gpio-controller; | ||
| 703 | interrupt-controller; | ||
| 704 | #interrupt-cells = <2>; | ||
| 705 | }; | ||
| 706 | |||
| 707 | pioD: gpio@fffff800 { | ||
| 708 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 709 | reg = <0xfffff800 0x100>; | ||
| 710 | interrupts = <9 4 1>; | ||
| 711 | #gpio-cells = <2>; | ||
| 712 | gpio-controller; | ||
| 713 | interrupt-controller; | ||
| 714 | #interrupt-cells = <2>; | ||
| 715 | }; | ||
| 716 | |||
| 717 | pioE: gpio@fffffa00 { | ||
| 718 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 719 | reg = <0xfffffa00 0x100>; | ||
| 720 | interrupts = <10 4 1>; | ||
| 721 | #gpio-cells = <2>; | ||
| 722 | gpio-controller; | ||
| 723 | interrupt-controller; | ||
| 724 | #interrupt-cells = <2>; | ||
| 725 | }; | ||
| 726 | |||
| 727 | spi0 { | ||
| 728 | pinctrl_spi0: spi0-0 { | ||
| 729 | atmel,pins = | ||
| 730 | <3 10 0x1 0x0 /* PD10 periph A SPI0_MISO pin */ | ||
| 731 | 3 11 0x1 0x0 /* PD11 periph A SPI0_MOSI pin */ | ||
| 732 | 3 12 0x1 0x0 /* PD12 periph A SPI0_SPCK pin */ | ||
| 733 | 3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */ | ||
| 734 | }; | ||
| 735 | }; | ||
| 736 | |||
| 737 | spi1 { | ||
| 738 | pinctrl_spi1: spi1-0 { | ||
| 739 | atmel,pins = | ||
| 740 | <2 22 0x1 0x0 /* PC22 periph A SPI1_MISO pin */ | ||
| 741 | 2 23 0x1 0x0 /* PC23 periph A SPI1_MOSI pin */ | ||
| 742 | 2 24 0x1 0x0 /* PC24 periph A SPI1_SPCK pin */ | ||
| 743 | 2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */ | ||
| 744 | }; | ||
| 745 | }; | ||
| 746 | |||
| 747 | ssc0 { | ||
| 748 | pinctrl_ssc0_tx: ssc0_tx { | ||
| 749 | atmel,pins = | ||
| 750 | <2 16 0x1 0x0 /* PC16 periph A TK0 */ | ||
| 751 | 2 17 0x1 0x0 /* PC17 periph A TF0 */ | ||
| 752 | 2 18 0x1 0x0>; /* PC18 periph A TD0 */ | ||
| 753 | }; | ||
| 754 | |||
| 755 | pinctrl_ssc0_rx: ssc0_rx { | ||
| 756 | atmel,pins = | ||
| 757 | <2 19 0x1 0x0 /* PC19 periph A RK0 */ | ||
| 758 | 2 20 0x1 0x0 /* PC20 periph A RF0 */ | ||
| 759 | 2 21 0x1 0x0>; /* PC21 periph A RD0 */ | ||
| 760 | }; | ||
| 761 | }; | ||
| 762 | |||
| 763 | ssc1 { | ||
| 764 | pinctrl_ssc1_tx: ssc1_tx { | ||
| 765 | atmel,pins = | ||
| 766 | <1 2 0x2 0x0 /* PB2 periph B TK1, conflicts with GTX2 */ | ||
| 767 | 1 3 0x2 0x0 /* PB3 periph B TF1, conflicts with GTX3 */ | ||
| 768 | 1 6 0x2 0x0>; /* PB6 periph B TD1, conflicts with TD1 */ | ||
| 769 | }; | ||
| 770 | |||
| 771 | pinctrl_ssc1_rx: ssc1_rx { | ||
| 772 | atmel,pins = | ||
| 773 | <1 7 0x2 0x0 /* PB7 periph B RK1, conflicts with EREFCK */ | ||
| 774 | 1 10 0x2 0x0 /* PB10 periph B RF1, conflicts with GTXER */ | ||
| 775 | 1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */ | ||
| 776 | }; | ||
| 777 | }; | ||
| 778 | |||
| 779 | uart0 { | ||
| 780 | pinctrl_uart0: uart0-0 { | ||
| 781 | atmel,pins = | ||
| 782 | <2 29 0x1 0x0 /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ | ||
| 783 | 2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ | ||
| 784 | }; | ||
| 785 | }; | ||
| 786 | |||
| 787 | uart1 { | ||
| 788 | pinctrl_uart1: uart1-0 { | ||
| 789 | atmel,pins = | ||
| 790 | <0 30 0x2 0x0 /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ | ||
| 791 | 0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ | ||
| 792 | }; | ||
| 793 | }; | ||
| 794 | |||
| 795 | usart0 { | ||
| 796 | pinctrl_usart0: usart0-0 { | ||
| 797 | atmel,pins = | ||
| 798 | <3 17 0x1 0x0 /* PD17 periph A */ | ||
| 799 | 3 18 0x1 0x1>; /* PD18 periph A with pullup */ | ||
| 800 | }; | ||
| 801 | |||
| 802 | pinctrl_usart0_rts_cts: usart0_rts_cts-0 { | ||
| 803 | atmel,pins = | ||
| 804 | <3 15 0x1 0x0 /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ | ||
| 805 | 3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ | ||
| 806 | }; | ||
| 807 | }; | ||
| 808 | |||
| 809 | usart1 { | ||
| 810 | pinctrl_usart1: usart1-0 { | ||
| 811 | atmel,pins = | ||
| 812 | <1 28 0x1 0x0 /* PB28 periph A */ | ||
| 813 | 1 29 0x1 0x1>; /* PB29 periph A with pullup */ | ||
| 814 | }; | ||
| 815 | |||
| 816 | pinctrl_usart1_rts_cts: usart1_rts_cts-0 { | ||
| 817 | atmel,pins = | ||
| 818 | <1 26 0x1 0x0 /* PB26 periph A, conflicts with GRX7 */ | ||
| 819 | 1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */ | ||
| 820 | }; | ||
| 821 | }; | ||
| 822 | |||
| 823 | usart2 { | ||
| 824 | pinctrl_usart2: usart2-0 { | ||
| 825 | atmel,pins = | ||
| 826 | <4 25 0x2 0x0 /* PE25 periph B, conflicts with A25 */ | ||
| 827 | 4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */ | ||
| 828 | }; | ||
| 829 | |||
| 830 | pinctrl_usart2_rts_cts: usart2_rts_cts-0 { | ||
| 831 | atmel,pins = | ||
| 832 | <4 23 0x2 0x0 /* PE23 periph B, conflicts with A23 */ | ||
| 833 | 4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */ | ||
| 834 | }; | ||
| 835 | }; | ||
| 836 | |||
| 837 | usart3 { | ||
| 838 | pinctrl_usart3: usart3-0 { | ||
| 839 | atmel,pins = | ||
| 840 | <4 18 0x2 0x0 /* PE18 periph B, conflicts with A18 */ | ||
| 841 | 4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */ | ||
| 842 | }; | ||
| 843 | |||
| 844 | pinctrl_usart3_rts_cts: usart3_rts_cts-0 { | ||
| 845 | atmel,pins = | ||
| 846 | <4 16 0x2 0x0 /* PE16 periph B, conflicts with A16 */ | ||
| 847 | 4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */ | ||
| 848 | }; | ||
| 849 | }; | ||
| 850 | }; | ||
| 851 | |||
| 852 | pmc: pmc@fffffc00 { | ||
| 853 | compatible = "atmel,at91rm9200-pmc"; | ||
| 854 | reg = <0xfffffc00 0x120>; | ||
| 855 | }; | ||
| 856 | |||
| 857 | rstc@fffffe00 { | ||
| 858 | compatible = "atmel,at91sam9g45-rstc"; | ||
| 859 | reg = <0xfffffe00 0x10>; | ||
| 860 | }; | ||
| 861 | |||
| 862 | pit: timer@fffffe30 { | ||
| 863 | compatible = "atmel,at91sam9260-pit"; | ||
| 864 | reg = <0xfffffe30 0xf>; | ||
| 865 | interrupts = <3 4 5>; | ||
| 866 | }; | ||
| 867 | |||
| 868 | watchdog@fffffe40 { | ||
| 869 | compatible = "atmel,at91sam9260-wdt"; | ||
| 870 | reg = <0xfffffe40 0x10>; | ||
| 871 | status = "disabled"; | ||
| 872 | }; | ||
| 873 | |||
| 874 | rtc@fffffeb0 { | ||
| 875 | compatible = "atmel,at91rm9200-rtc"; | ||
| 876 | reg = <0xfffffeb0 0x30>; | ||
| 877 | interrupts = <1 4 7>; | ||
| 878 | }; | ||
| 879 | }; | ||
| 880 | |||
| 881 | usb0: gadget@00500000 { | ||
| 882 | #address-cells = <1>; | ||
| 883 | #size-cells = <0>; | ||
| 884 | compatible = "atmel,at91sam9rl-udc"; | ||
| 885 | reg = <0x00500000 0x100000 | ||
| 886 | 0xf8030000 0x4000>; | ||
| 887 | interrupts = <33 4 2>; | ||
| 888 | status = "disabled"; | ||
| 889 | |||
| 890 | ep0 { | ||
| 891 | reg = <0>; | ||
| 892 | atmel,fifo-size = <64>; | ||
| 893 | atmel,nb-banks = <1>; | ||
| 894 | }; | ||
| 895 | |||
| 896 | ep1 { | ||
| 897 | reg = <1>; | ||
| 898 | atmel,fifo-size = <1024>; | ||
| 899 | atmel,nb-banks = <3>; | ||
| 900 | atmel,can-dma; | ||
| 901 | atmel,can-isoc; | ||
| 902 | }; | ||
| 903 | |||
| 904 | ep2 { | ||
| 905 | reg = <2>; | ||
| 906 | atmel,fifo-size = <1024>; | ||
| 907 | atmel,nb-banks = <3>; | ||
| 908 | atmel,can-dma; | ||
| 909 | atmel,can-isoc; | ||
| 910 | }; | ||
| 911 | |||
| 912 | ep3 { | ||
| 913 | reg = <3>; | ||
| 914 | atmel,fifo-size = <1024>; | ||
| 915 | atmel,nb-banks = <2>; | ||
| 916 | atmel,can-dma; | ||
| 917 | }; | ||
| 918 | |||
| 919 | ep4 { | ||
| 920 | reg = <4>; | ||
| 921 | atmel,fifo-size = <1024>; | ||
| 922 | atmel,nb-banks = <2>; | ||
| 923 | atmel,can-dma; | ||
| 924 | }; | ||
| 925 | |||
| 926 | ep5 { | ||
| 927 | reg = <5>; | ||
| 928 | atmel,fifo-size = <1024>; | ||
| 929 | atmel,nb-banks = <2>; | ||
| 930 | atmel,can-dma; | ||
| 931 | }; | ||
| 932 | |||
| 933 | ep6 { | ||
| 934 | reg = <6>; | ||
| 935 | atmel,fifo-size = <1024>; | ||
| 936 | atmel,nb-banks = <2>; | ||
| 937 | atmel,can-dma; | ||
| 938 | }; | ||
| 939 | |||
| 940 | ep7 { | ||
| 941 | reg = <7>; | ||
| 942 | atmel,fifo-size = <1024>; | ||
| 943 | atmel,nb-banks = <2>; | ||
| 944 | atmel,can-dma; | ||
| 945 | }; | ||
| 946 | |||
| 947 | ep8 { | ||
| 948 | reg = <8>; | ||
| 949 | atmel,fifo-size = <1024>; | ||
| 950 | atmel,nb-banks = <2>; | ||
| 951 | }; | ||
| 952 | |||
| 953 | ep9 { | ||
| 954 | reg = <9>; | ||
| 955 | atmel,fifo-size = <1024>; | ||
| 956 | atmel,nb-banks = <2>; | ||
| 957 | }; | ||
| 958 | |||
| 959 | ep10 { | ||
| 960 | reg = <10>; | ||
| 961 | atmel,fifo-size = <1024>; | ||
| 962 | atmel,nb-banks = <2>; | ||
| 963 | }; | ||
| 964 | |||
| 965 | ep11 { | ||
| 966 | reg = <11>; | ||
| 967 | atmel,fifo-size = <1024>; | ||
| 968 | atmel,nb-banks = <2>; | ||
| 969 | }; | ||
| 970 | |||
| 971 | ep12 { | ||
| 972 | reg = <12>; | ||
| 973 | atmel,fifo-size = <1024>; | ||
| 974 | atmel,nb-banks = <2>; | ||
| 975 | }; | ||
| 976 | |||
| 977 | ep13 { | ||
| 978 | reg = <13>; | ||
| 979 | atmel,fifo-size = <1024>; | ||
| 980 | atmel,nb-banks = <2>; | ||
| 981 | }; | ||
| 982 | |||
| 983 | ep14 { | ||
| 984 | reg = <14>; | ||
| 985 | atmel,fifo-size = <1024>; | ||
| 986 | atmel,nb-banks = <2>; | ||
| 987 | }; | ||
| 988 | |||
| 989 | ep15 { | ||
| 990 | reg = <15>; | ||
| 991 | atmel,fifo-size = <1024>; | ||
| 992 | atmel,nb-banks = <2>; | ||
| 993 | }; | ||
| 994 | }; | ||
| 995 | |||
| 996 | usb1: ohci@00600000 { | ||
| 997 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | ||
| 998 | reg = <0x00600000 0x100000>; | ||
| 999 | interrupts = <32 4 2>; | ||
| 1000 | status = "disabled"; | ||
| 1001 | }; | ||
| 1002 | |||
| 1003 | usb2: ehci@00700000 { | ||
| 1004 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | ||
| 1005 | reg = <0x00700000 0x100000>; | ||
| 1006 | interrupts = <32 4 2>; | ||
| 1007 | status = "disabled"; | ||
| 1008 | }; | ||
| 1009 | |||
| 1010 | nand0: nand@60000000 { | ||
| 1011 | compatible = "atmel,at91rm9200-nand"; | ||
| 1012 | #address-cells = <1>; | ||
| 1013 | #size-cells = <1>; | ||
| 1014 | reg = < 0x60000000 0x01000000 /* EBI CS3 */ | ||
| 1015 | 0xffffc070 0x00000490 /* SMC PMECC regs */ | ||
| 1016 | 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ | ||
| 1017 | 0x00100000 0x00100000 /* ROM code */ | ||
| 1018 | 0x70000000 0x10000000 /* NFC Command Registers */ | ||
| 1019 | 0xffffc000 0x00000070 /* NFC HSMC regs */ | ||
| 1020 | 0x00200000 0x00100000 /* NFC SRAM banks */ | ||
| 1021 | >; | ||
| 1022 | interrupts = <5 4 6>; | ||
| 1023 | atmel,nand-addr-offset = <21>; | ||
| 1024 | atmel,nand-cmd-offset = <22>; | ||
| 1025 | pinctrl-names = "default"; | ||
| 1026 | pinctrl-0 = <&pinctrl_nand0_ale_cle>; | ||
| 1027 | atmel,pmecc-lookup-table-offset = <0x10000 0x18000>; | ||
| 1028 | status = "disabled"; | ||
| 1029 | }; | ||
| 1030 | }; | ||
| 1031 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts new file mode 100644 index 000000000000..fa5d216f1db7 --- /dev/null +++ b/arch/arm/boot/dts/sama5d31ek.dts | |||
| @@ -0,0 +1,51 @@ | |||
| 1 | /* | ||
| 2 | * sama5d31ek.dts - Device Tree file for SAMA5D31-EK board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /dts-v1/; | ||
| 10 | /include/ "sama5d3xmb.dtsi" | ||
| 11 | /include/ "sama5d3xdm.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Atmel SAMA5D31-EK"; | ||
| 15 | compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 16 | |||
| 17 | ahb { | ||
| 18 | apb { | ||
| 19 | spi0: spi@f0004000 { | ||
| 20 | status = "okay"; | ||
| 21 | }; | ||
| 22 | |||
| 23 | ssc0: ssc@f0008000 { | ||
| 24 | status = "okay"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | i2c0: i2c@f0014000 { | ||
| 28 | status = "okay"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | i2c1: i2c@f0018000 { | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | macb1: ethernet@f802c000 { | ||
| 36 | status = "okay"; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | leds { | ||
| 42 | d3 { | ||
| 43 | label = "d3"; | ||
| 44 | gpios = <&pioE 24 0>; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | |||
| 48 | sound { | ||
| 49 | status = "okay"; | ||
| 50 | }; | ||
| 51 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts new file mode 100644 index 000000000000..c38c9433d7a5 --- /dev/null +++ b/arch/arm/boot/dts/sama5d33ek.dts | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * sama5d33ek.dts - Device Tree file for SAMA5D33-EK board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /dts-v1/; | ||
| 10 | /include/ "sama5d3xmb.dtsi" | ||
| 11 | /include/ "sama5d3xdm.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Atmel SAMA5D33-EK"; | ||
| 15 | compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 16 | |||
| 17 | ahb { | ||
| 18 | apb { | ||
| 19 | spi0: spi@f0004000 { | ||
| 20 | status = "okay"; | ||
| 21 | }; | ||
| 22 | |||
| 23 | ssc0: ssc@f0008000 { | ||
| 24 | status = "okay"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | i2c0: i2c@f0014000 { | ||
| 28 | status = "okay"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | i2c1: i2c@f0018000 { | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | macb0: ethernet@f0028000 { | ||
| 36 | status = "okay"; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | sound { | ||
| 42 | status = "okay"; | ||
| 43 | }; | ||
| 44 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts new file mode 100644 index 000000000000..d2739f8d7ae9 --- /dev/null +++ b/arch/arm/boot/dts/sama5d34ek.dts | |||
| @@ -0,0 +1,61 @@ | |||
| 1 | /* | ||
| 2 | * sama5d34ek.dts - Device Tree file for SAMA5D34-EK board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /dts-v1/; | ||
| 10 | /include/ "sama5d3xmb.dtsi" | ||
| 11 | /include/ "sama5d3xdm.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Atmel SAMA5D34-EK"; | ||
| 15 | compatible = "atmel,sama5d34ek", "atmel,sama5ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 16 | |||
| 17 | ahb { | ||
| 18 | apb { | ||
| 19 | spi0: spi@f0004000 { | ||
| 20 | status = "okay"; | ||
| 21 | }; | ||
| 22 | |||
| 23 | ssc0: ssc@f0008000 { | ||
| 24 | status = "okay"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | can0: can@f000c000 { | ||
| 28 | status = "okay"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | i2c0: i2c@f0014000 { | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | i2c1: i2c@f0018000 { | ||
| 36 | status = "okay"; | ||
| 37 | |||
| 38 | 24c256@50 { | ||
| 39 | compatible = "24c256"; | ||
| 40 | reg = <0x50>; | ||
| 41 | pagesize = <64>; | ||
| 42 | }; | ||
| 43 | }; | ||
| 44 | |||
| 45 | macb0: ethernet@f0028000 { | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | leds { | ||
| 52 | d3 { | ||
| 53 | label = "d3"; | ||
| 54 | gpios = <&pioE 24 0>; | ||
| 55 | }; | ||
| 56 | }; | ||
| 57 | |||
| 58 | sound { | ||
| 59 | status = "okay"; | ||
| 60 | }; | ||
| 61 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts new file mode 100644 index 000000000000..a488fc4e9777 --- /dev/null +++ b/arch/arm/boot/dts/sama5d35ek.dts | |||
| @@ -0,0 +1,56 @@ | |||
| 1 | /* | ||
| 2 | * sama5d35ek.dts - Device Tree file for SAMA5D35-EK board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /dts-v1/; | ||
| 10 | /include/ "sama5d3xmb.dtsi" | ||
| 11 | |||
| 12 | / { | ||
| 13 | model = "Atmel SAMA5D35-EK"; | ||
| 14 | compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 15 | |||
| 16 | ahb { | ||
| 17 | apb { | ||
| 18 | spi0: spi@f0004000 { | ||
| 19 | status = "okay"; | ||
| 20 | }; | ||
| 21 | |||
| 22 | can0: can@f000c000 { | ||
| 23 | status = "okay"; | ||
| 24 | }; | ||
| 25 | |||
| 26 | i2c1: i2c@f0018000 { | ||
| 27 | status = "okay"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | macb0: ethernet@f0028000 { | ||
| 31 | status = "okay"; | ||
| 32 | }; | ||
| 33 | |||
| 34 | isi: isi@f0034000 { | ||
| 35 | status = "okay"; | ||
| 36 | }; | ||
| 37 | |||
| 38 | macb1: ethernet@f802c000 { | ||
| 39 | status = "okay"; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | |||
| 44 | gpio_keys { | ||
| 45 | compatible = "gpio-keys"; | ||
| 46 | #address-cells = <1>; | ||
| 47 | #size-cells = <0>; | ||
| 48 | |||
| 49 | pb_user1 { | ||
| 50 | label = "pb_user1"; | ||
| 51 | gpios = <&pioE 27 0>; | ||
| 52 | linux,code = <0x100>; | ||
| 53 | gpio-key,wakeup; | ||
| 54 | }; | ||
| 55 | }; | ||
| 56 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi new file mode 100644 index 000000000000..1f8ed404626c --- /dev/null +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi | |||
| @@ -0,0 +1,91 @@ | |||
| 1 | /* | ||
| 2 | * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /include/ "sama5d3.dtsi" | ||
| 10 | |||
| 11 | / { | ||
| 12 | compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 13 | |||
| 14 | chosen { | ||
| 15 | bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; | ||
| 16 | }; | ||
| 17 | |||
| 18 | memory { | ||
| 19 | reg = <0x20000000 0x20000000>; | ||
| 20 | }; | ||
| 21 | |||
| 22 | clocks { | ||
| 23 | #address-cells = <1>; | ||
| 24 | #size-cells = <1>; | ||
| 25 | ranges; | ||
| 26 | |||
| 27 | main_clock: clock@0 { | ||
| 28 | compatible = "atmel,osc", "fixed-clock"; | ||
| 29 | clock-frequency = <12000000>; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | |||
| 33 | ahb { | ||
| 34 | apb { | ||
| 35 | macb0: ethernet@f0028000 { | ||
| 36 | phy-mode = "rgmii"; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | |||
| 40 | nand0: nand@60000000 { | ||
| 41 | nand-bus-width = <8>; | ||
| 42 | nand-ecc-mode = "hw"; | ||
| 43 | atmel,has-pmecc; | ||
| 44 | atmel,pmecc-cap = <4>; | ||
| 45 | atmel,pmecc-sector-size = <512>; | ||
| 46 | atmel,has-nfc; | ||
| 47 | atmel,use-nfc-sram; | ||
| 48 | nand-on-flash-bbt; | ||
| 49 | status = "okay"; | ||
| 50 | |||
| 51 | at91bootstrap@0 { | ||
| 52 | label = "at91bootstrap"; | ||
| 53 | reg = <0x0 0x40000>; | ||
| 54 | }; | ||
| 55 | |||
| 56 | bootloader@40000 { | ||
| 57 | label = "bootloader"; | ||
| 58 | reg = <0x40000 0x80000>; | ||
| 59 | }; | ||
| 60 | |||
| 61 | bootloaderenv@c0000 { | ||
| 62 | label = "bootloader env"; | ||
| 63 | reg = <0xc0000 0xc0000>; | ||
| 64 | }; | ||
| 65 | |||
| 66 | dtb@180000 { | ||
| 67 | label = "device tree"; | ||
| 68 | reg = <0x180000 0x80000>; | ||
| 69 | }; | ||
| 70 | |||
| 71 | kernel@200000 { | ||
| 72 | label = "kernel"; | ||
| 73 | reg = <0x200000 0x600000>; | ||
| 74 | }; | ||
| 75 | |||
| 76 | rootfs@800000 { | ||
| 77 | label = "rootfs"; | ||
| 78 | reg = <0x800000 0x0f800000>; | ||
| 79 | }; | ||
| 80 | }; | ||
| 81 | }; | ||
| 82 | |||
| 83 | leds { | ||
| 84 | compatible = "gpio-leds"; | ||
| 85 | |||
| 86 | d2 { | ||
| 87 | label = "d2"; | ||
| 88 | gpios = <&pioE 25 1>; /* PE25, conflicts with A25, RXD2 */ | ||
| 89 | }; | ||
| 90 | }; | ||
| 91 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi new file mode 100644 index 000000000000..4b8830eb2060 --- /dev/null +++ b/arch/arm/boot/dts/sama5d3xdm.dtsi | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | /* | ||
| 2 | * sama5d3dm.dtsi - Device Tree file for SAMA5 display module | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | |||
| 10 | / { | ||
| 11 | ahb { | ||
| 12 | apb { | ||
| 13 | i2c1: i2c@f0018000 { | ||
| 14 | qt1070: keyboard@1b { | ||
| 15 | compatible = "qt1070"; | ||
| 16 | reg = <0x1b>; | ||
| 17 | interrupt-parent = <&pioE>; | ||
| 18 | interrupts = <31 0x0>; | ||
| 19 | pinctrl-names = "default"; | ||
| 20 | pinctrl-0 = <&pinctrl_qt1070_irq>; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | |||
| 24 | adc0: adc@f8018000 { | ||
| 25 | status = "disabled"; | ||
| 26 | }; | ||
| 27 | |||
| 28 | tsadcc: tsadcc@f8018000 { | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
| 31 | |||
| 32 | pinctrl@fffff200 { | ||
| 33 | board { | ||
| 34 | pinctrl_qt1070_irq: qt1070_irq { | ||
| 35 | atmel,pins = | ||
| 36 | <4 31 0x0 0x5>; /* PE31 GPIO with pull up deglith */ | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi new file mode 100644 index 000000000000..661d7ca9c309 --- /dev/null +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi | |||
| @@ -0,0 +1,166 @@ | |||
| 1 | /* | ||
| 2 | * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /include/ "sama5d3xcm.dtsi" | ||
| 10 | |||
| 11 | / { | ||
| 12 | compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 13 | |||
| 14 | ahb { | ||
| 15 | apb { | ||
| 16 | mmc0: mmc@f0000000 { | ||
| 17 | pinctrl-names = "default"; | ||
| 18 | pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; | ||
| 19 | status = "okay"; | ||
| 20 | slot@0 { | ||
| 21 | reg = <0>; | ||
| 22 | bus-width = <4>; | ||
| 23 | cd-gpios = <&pioD 17 0>; | ||
| 24 | }; | ||
| 25 | }; | ||
| 26 | |||
| 27 | spi0: spi@f0004000 { | ||
| 28 | m25p80@0 { | ||
| 29 | compatible = "atmel,at25df321a"; | ||
| 30 | spi-max-frequency = <50000000>; | ||
| 31 | reg = <0>; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | |||
| 35 | /* | ||
| 36 | * i2c0 conflicts with ISI: | ||
| 37 | * disable it to allow the use of ISI | ||
| 38 | * can not enable audio when i2c0 disabled | ||
| 39 | */ | ||
| 40 | i2c0: i2c@f0014000 { | ||
| 41 | wm8904: wm8904@1a { | ||
| 42 | compatible = "wm8904"; | ||
| 43 | reg = <0x1a>; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | |||
| 47 | usart1: serial@f0020000 { | ||
| 48 | pinctrl-names = "default"; | ||
| 49 | pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; | ||
| 50 | status = "okay"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | isi: isi@f0034000 { | ||
| 54 | pinctrl-names = "default"; | ||
| 55 | pinctrl-0 = <&pinctrl_isi &pinctrl_isi_pck_as_mck &pinctrl_isi_power &pinctrl_isi_reset>; | ||
| 56 | }; | ||
| 57 | |||
| 58 | mmc1: mmc@f8000000 { | ||
| 59 | pinctrl-names = "default"; | ||
| 60 | pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; | ||
| 61 | status = "okay"; | ||
| 62 | slot@0 { | ||
| 63 | reg = <0>; | ||
| 64 | bus-width = <4>; | ||
| 65 | cd-gpios = <&pioD 18 0>; | ||
| 66 | }; | ||
| 67 | }; | ||
| 68 | |||
| 69 | adc0: adc@f8018000 { | ||
| 70 | pinctrl-names = "default"; | ||
| 71 | pinctrl-0 = < | ||
| 72 | &pinctrl_adc0_adtrg | ||
| 73 | &pinctrl_adc0_ad0 | ||
| 74 | &pinctrl_adc0_ad1 | ||
| 75 | &pinctrl_adc0_ad2 | ||
| 76 | &pinctrl_adc0_ad3 | ||
| 77 | &pinctrl_adc0_ad4 | ||
| 78 | >; | ||
| 79 | status = "okay"; | ||
| 80 | }; | ||
| 81 | |||
| 82 | macb1: ethernet@f802c000 { | ||
| 83 | phy-mode = "rmii"; | ||
| 84 | }; | ||
| 85 | |||
| 86 | pinctrl@fffff200 { | ||
| 87 | board { | ||
| 88 | pinctrl_mmc0_cd: mmc0_cd { | ||
| 89 | atmel,pins = | ||
| 90 | <3 17 0x0 0x5>; /* PD17 GPIO with pullup deglitch */ | ||
| 91 | }; | ||
| 92 | |||
| 93 | pinctrl_mmc1_cd: mmc1_cd { | ||
| 94 | atmel,pins = | ||
| 95 | <3 18 0x0 0x5>; /* PD18 GPIO with pullup deglitch */ | ||
| 96 | }; | ||
| 97 | |||
| 98 | pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { | ||
| 99 | atmel,pins = | ||
| 100 | <3 30 0x2 0x0>; /* PD30 periph B */ | ||
| 101 | }; | ||
| 102 | |||
| 103 | pinctrl_isi_reset: isi_reset-0 { | ||
| 104 | atmel,pins = | ||
| 105 | <4 24 0x0 0x0>; /* PE24 gpio */ | ||
| 106 | }; | ||
| 107 | |||
| 108 | pinctrl_isi_power: isi_power-0 { | ||
| 109 | atmel,pins = | ||
| 110 | <4 29 0x0 0x0>; /* PE29 gpio */ | ||
| 111 | }; | ||
| 112 | |||
| 113 | pinctrl_usba_vbus: usba_vbus { | ||
| 114 | atmel,pins = | ||
| 115 | <3 29 0x0 0x4>; /* PD29 GPIO with deglitch */ | ||
| 116 | }; | ||
| 117 | }; | ||
| 118 | }; | ||
| 119 | |||
| 120 | dbgu: serial@ffffee00 { | ||
| 121 | status = "okay"; | ||
| 122 | }; | ||
| 123 | |||
| 124 | watchdog@fffffe40 { | ||
| 125 | status = "okay"; | ||
| 126 | }; | ||
| 127 | }; | ||
| 128 | |||
| 129 | usb0: gadget@00500000 { | ||
| 130 | atmel,vbus-gpio = <&pioD 29 0>; | ||
| 131 | pinctrl-names = "default"; | ||
| 132 | pinctrl-0 = <&pinctrl_usba_vbus>; | ||
| 133 | status = "okay"; | ||
| 134 | }; | ||
| 135 | |||
| 136 | usb1: ohci@00600000 { | ||
| 137 | num-ports = <3>; | ||
| 138 | atmel,vbus-gpio = <&pioD 25 0 | ||
| 139 | &pioD 26 1 | ||
| 140 | &pioD 27 1 | ||
| 141 | >; | ||
| 142 | status = "okay"; | ||
| 143 | }; | ||
| 144 | |||
| 145 | usb2: ehci@00700000 { | ||
| 146 | status = "okay"; | ||
| 147 | }; | ||
| 148 | }; | ||
| 149 | |||
| 150 | sound { | ||
| 151 | compatible = "atmel,sama5d3ek-wm8904"; | ||
| 152 | pinctrl-names = "default"; | ||
| 153 | pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; | ||
| 154 | |||
| 155 | atmel,model = "wm8904 @ SAMA5D3EK"; | ||
| 156 | atmel,audio-routing = | ||
| 157 | "Headphone Jack", "HPOUTL", | ||
| 158 | "Headphone Jack", "HPOUTR", | ||
| 159 | "IN2L", "Line In Jack", | ||
| 160 | "IN2R", "Line In Jack", | ||
| 161 | "IN1L", "Mic"; | ||
| 162 | |||
| 163 | atmel,ssc-controller = <&ssc0>; | ||
| 164 | atmel,audio-codec = <&wm8904>; | ||
| 165 | }; | ||
| 166 | }; | ||
diff --git a/arch/arm/boot/dts/skeleton64.dtsi b/arch/arm/boot/dts/skeleton64.dtsi new file mode 100644 index 000000000000..15994158a998 --- /dev/null +++ b/arch/arm/boot/dts/skeleton64.dtsi | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | /* | ||
| 2 | * Skeleton device tree in the 64 bits version; the bare minimum | ||
| 3 | * needed to boot; just include and add a compatible value. The | ||
| 4 | * bootloader will typically populate the memory node. | ||
| 5 | */ | ||
| 6 | |||
| 7 | / { | ||
| 8 | #address-cells = <2>; | ||
| 9 | #size-cells = <2>; | ||
| 10 | chosen { }; | ||
| 11 | aliases { }; | ||
| 12 | memory { device_type = "memory"; reg = <0 0>; }; | ||
| 13 | }; | ||
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index d3ec32f6b790..db5db24fd544 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts | |||
| @@ -299,6 +299,10 @@ | |||
| 299 | }; | 299 | }; |
| 300 | 300 | ||
| 301 | ab8500 { | 301 | ab8500 { |
| 302 | ab8500-gpio { | ||
| 303 | compatible = "stericsson,ab8500-gpio"; | ||
| 304 | }; | ||
| 305 | |||
| 302 | ab8500-regulators { | 306 | ab8500-regulators { |
| 303 | ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { | 307 | ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { |
| 304 | regulator-name = "V-DISPLAY"; | 308 | regulator-name = "V-DISPLAY"; |
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 7e8769bd5977..16a6e13e08b4 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi | |||
| @@ -81,6 +81,163 @@ | |||
| 81 | }; | 81 | }; |
| 82 | }; | 82 | }; |
| 83 | 83 | ||
| 84 | clkmgr@ffd04000 { | ||
| 85 | compatible = "altr,clk-mgr"; | ||
| 86 | reg = <0xffd04000 0x1000>; | ||
| 87 | |||
| 88 | clocks { | ||
| 89 | #address-cells = <1>; | ||
| 90 | #size-cells = <0>; | ||
| 91 | |||
| 92 | osc: osc1 { | ||
| 93 | #clock-cells = <0>; | ||
| 94 | compatible = "fixed-clock"; | ||
| 95 | }; | ||
| 96 | |||
| 97 | main_pll: main_pll { | ||
| 98 | #address-cells = <1>; | ||
| 99 | #size-cells = <0>; | ||
| 100 | #clock-cells = <0>; | ||
| 101 | compatible = "altr,socfpga-pll-clock"; | ||
| 102 | clocks = <&osc>; | ||
| 103 | reg = <0x40>; | ||
| 104 | |||
| 105 | mpuclk: mpuclk { | ||
| 106 | #clock-cells = <0>; | ||
| 107 | compatible = "altr,socfpga-perip-clk"; | ||
| 108 | clocks = <&main_pll>; | ||
| 109 | fixed-divider = <2>; | ||
| 110 | reg = <0x48>; | ||
| 111 | }; | ||
| 112 | |||
| 113 | mainclk: mainclk { | ||
| 114 | #clock-cells = <0>; | ||
| 115 | compatible = "altr,socfpga-perip-clk"; | ||
| 116 | clocks = <&main_pll>; | ||
| 117 | fixed-divider = <4>; | ||
| 118 | reg = <0x4C>; | ||
| 119 | }; | ||
| 120 | |||
| 121 | dbg_base_clk: dbg_base_clk { | ||
| 122 | #clock-cells = <0>; | ||
| 123 | compatible = "altr,socfpga-perip-clk"; | ||
| 124 | clocks = <&main_pll>; | ||
| 125 | fixed-divider = <4>; | ||
| 126 | reg = <0x50>; | ||
| 127 | }; | ||
| 128 | |||
| 129 | main_qspi_clk: main_qspi_clk { | ||
| 130 | #clock-cells = <0>; | ||
| 131 | compatible = "altr,socfpga-perip-clk"; | ||
| 132 | clocks = <&main_pll>; | ||
| 133 | reg = <0x54>; | ||
| 134 | }; | ||
| 135 | |||
| 136 | main_nand_sdmmc_clk: main_nand_sdmmc_clk { | ||
| 137 | #clock-cells = <0>; | ||
| 138 | compatible = "altr,socfpga-perip-clk"; | ||
| 139 | clocks = <&main_pll>; | ||
| 140 | reg = <0x58>; | ||
| 141 | }; | ||
| 142 | |||
| 143 | cfg_s2f_usr0_clk: cfg_s2f_usr0_clk { | ||
| 144 | #clock-cells = <0>; | ||
| 145 | compatible = "altr,socfpga-perip-clk"; | ||
| 146 | clocks = <&main_pll>; | ||
| 147 | reg = <0x5C>; | ||
| 148 | }; | ||
| 149 | }; | ||
| 150 | |||
| 151 | periph_pll: periph_pll { | ||
| 152 | #address-cells = <1>; | ||
| 153 | #size-cells = <0>; | ||
| 154 | #clock-cells = <0>; | ||
| 155 | compatible = "altr,socfpga-pll-clock"; | ||
| 156 | clocks = <&osc>; | ||
| 157 | reg = <0x80>; | ||
| 158 | |||
| 159 | emac0_clk: emac0_clk { | ||
| 160 | #clock-cells = <0>; | ||
| 161 | compatible = "altr,socfpga-perip-clk"; | ||
| 162 | clocks = <&periph_pll>; | ||
| 163 | reg = <0x88>; | ||
| 164 | }; | ||
| 165 | |||
| 166 | emac1_clk: emac1_clk { | ||
| 167 | #clock-cells = <0>; | ||
| 168 | compatible = "altr,socfpga-perip-clk"; | ||
| 169 | clocks = <&periph_pll>; | ||
| 170 | reg = <0x8C>; | ||
| 171 | }; | ||
| 172 | |||
| 173 | per_qspi_clk: per_qsi_clk { | ||
| 174 | #clock-cells = <0>; | ||
| 175 | compatible = "altr,socfpga-perip-clk"; | ||
| 176 | clocks = <&periph_pll>; | ||
| 177 | reg = <0x90>; | ||
| 178 | }; | ||
| 179 | |||
| 180 | per_nand_mmc_clk: per_nand_mmc_clk { | ||
| 181 | #clock-cells = <0>; | ||
| 182 | compatible = "altr,socfpga-perip-clk"; | ||
| 183 | clocks = <&periph_pll>; | ||
| 184 | reg = <0x94>; | ||
| 185 | }; | ||
| 186 | |||
| 187 | per_base_clk: per_base_clk { | ||
| 188 | #clock-cells = <0>; | ||
| 189 | compatible = "altr,socfpga-perip-clk"; | ||
| 190 | clocks = <&periph_pll>; | ||
| 191 | reg = <0x98>; | ||
| 192 | }; | ||
| 193 | |||
| 194 | s2f_usr1_clk: s2f_usr1_clk { | ||
| 195 | #clock-cells = <0>; | ||
| 196 | compatible = "altr,socfpga-perip-clk"; | ||
| 197 | clocks = <&periph_pll>; | ||
| 198 | reg = <0x9C>; | ||
| 199 | }; | ||
| 200 | }; | ||
| 201 | |||
| 202 | sdram_pll: sdram_pll { | ||
| 203 | #address-cells = <1>; | ||
| 204 | #size-cells = <0>; | ||
| 205 | #clock-cells = <0>; | ||
| 206 | compatible = "altr,socfpga-pll-clock"; | ||
| 207 | clocks = <&osc>; | ||
| 208 | reg = <0xC0>; | ||
| 209 | |||
| 210 | ddr_dqs_clk: ddr_dqs_clk { | ||
| 211 | #clock-cells = <0>; | ||
| 212 | compatible = "altr,socfpga-perip-clk"; | ||
| 213 | clocks = <&sdram_pll>; | ||
| 214 | reg = <0xC8>; | ||
| 215 | }; | ||
| 216 | |||
| 217 | ddr_2x_dqs_clk: ddr_2x_dqs_clk { | ||
| 218 | #clock-cells = <0>; | ||
| 219 | compatible = "altr,socfpga-perip-clk"; | ||
| 220 | clocks = <&sdram_pll>; | ||
| 221 | reg = <0xCC>; | ||
| 222 | }; | ||
| 223 | |||
| 224 | ddr_dq_clk: ddr_dq_clk { | ||
| 225 | #clock-cells = <0>; | ||
| 226 | compatible = "altr,socfpga-perip-clk"; | ||
| 227 | clocks = <&sdram_pll>; | ||
| 228 | reg = <0xD0>; | ||
| 229 | }; | ||
| 230 | |||
| 231 | s2f_usr2_clk: s2f_usr2_clk { | ||
| 232 | #clock-cells = <0>; | ||
| 233 | compatible = "altr,socfpga-perip-clk"; | ||
| 234 | clocks = <&sdram_pll>; | ||
| 235 | reg = <0xD4>; | ||
| 236 | }; | ||
| 237 | }; | ||
| 238 | }; | ||
| 239 | }; | ||
| 240 | |||
| 84 | gmac0: stmmac@ff700000 { | 241 | gmac0: stmmac@ff700000 { |
| 85 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; | 242 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; |
| 86 | reg = <0xff700000 0x2000>; | 243 | reg = <0xff700000 0x2000>; |
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts index 3ae8a83a0875..2495958f1016 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts | |||
| @@ -33,6 +33,14 @@ | |||
| 33 | }; | 33 | }; |
| 34 | 34 | ||
| 35 | soc { | 35 | soc { |
| 36 | clkmgr@ffd04000 { | ||
| 37 | clocks { | ||
| 38 | osc1 { | ||
| 39 | clock-frequency = <25000000>; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | |||
| 36 | timer0@ffc08000 { | 44 | timer0@ffc08000 { |
| 37 | clock-frequency = <100000000>; | 45 | clock-frequency = <100000000>; |
| 38 | }; | 46 | }; |
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index 1036eba40bbf..0bf035d607f0 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts | |||
| @@ -33,6 +33,14 @@ | |||
| 33 | }; | 33 | }; |
| 34 | 34 | ||
| 35 | soc { | 35 | soc { |
| 36 | clkmgr@ffd04000 { | ||
| 37 | clocks { | ||
| 38 | osc1 { | ||
| 39 | clock-frequency = <10000000>; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | |||
| 36 | timer0@ffc08000 { | 44 | timer0@ffc08000 { |
| 37 | clock-frequency = <7000000>; | 45 | clock-frequency = <7000000>; |
| 38 | }; | 46 | }; |
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi index 1513c1927cc8..122ae94076c8 100644 --- a/arch/arm/boot/dts/spear1310.dtsi +++ b/arch/arm/boot/dts/spear1310.dtsi | |||
| @@ -89,7 +89,7 @@ | |||
| 89 | pinmux: pinmux@e0700000 { | 89 | pinmux: pinmux@e0700000 { |
| 90 | compatible = "st,spear1310-pinmux"; | 90 | compatible = "st,spear1310-pinmux"; |
| 91 | reg = <0xe0700000 0x1000>; | 91 | reg = <0xe0700000 0x1000>; |
| 92 | #gpio-range-cells = <2>; | 92 | #gpio-range-cells = <3>; |
| 93 | }; | 93 | }; |
| 94 | 94 | ||
| 95 | apb { | 95 | apb { |
| @@ -212,7 +212,7 @@ | |||
| 212 | interrupt-controller; | 212 | interrupt-controller; |
| 213 | gpio-controller; | 213 | gpio-controller; |
| 214 | #gpio-cells = <2>; | 214 | #gpio-cells = <2>; |
| 215 | gpio-ranges = <&pinmux 0 246>; | 215 | gpio-ranges = <&pinmux 0 0 246>; |
| 216 | status = "disabled"; | 216 | status = "disabled"; |
| 217 | 217 | ||
| 218 | st-plgpio,ngpio = <246>; | 218 | st-plgpio,ngpio = <246>; |
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi index 34da11aa6795..c511c4772efd 100644 --- a/arch/arm/boot/dts/spear1340.dtsi +++ b/arch/arm/boot/dts/spear1340.dtsi | |||
| @@ -63,7 +63,7 @@ | |||
| 63 | pinmux: pinmux@e0700000 { | 63 | pinmux: pinmux@e0700000 { |
| 64 | compatible = "st,spear1340-pinmux"; | 64 | compatible = "st,spear1340-pinmux"; |
| 65 | reg = <0xe0700000 0x1000>; | 65 | reg = <0xe0700000 0x1000>; |
| 66 | #gpio-range-cells = <2>; | 66 | #gpio-range-cells = <3>; |
| 67 | }; | 67 | }; |
| 68 | 68 | ||
| 69 | pwm: pwm@e0180000 { | 69 | pwm: pwm@e0180000 { |
| @@ -127,7 +127,7 @@ | |||
| 127 | interrupt-controller; | 127 | interrupt-controller; |
| 128 | gpio-controller; | 128 | gpio-controller; |
| 129 | #gpio-cells = <2>; | 129 | #gpio-cells = <2>; |
| 130 | gpio-ranges = <&pinmux 0 252>; | 130 | gpio-ranges = <&pinmux 0 0 252>; |
| 131 | status = "disabled"; | 131 | status = "disabled"; |
| 132 | 132 | ||
| 133 | st-plgpio,ngpio = <250>; | 133 | st-plgpio,ngpio = <250>; |
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi index ab45b8c81982..95372080eea6 100644 --- a/arch/arm/boot/dts/spear310.dtsi +++ b/arch/arm/boot/dts/spear310.dtsi | |||
| @@ -25,7 +25,7 @@ | |||
| 25 | pinmux: pinmux@b4000000 { | 25 | pinmux: pinmux@b4000000 { |
| 26 | compatible = "st,spear310-pinmux"; | 26 | compatible = "st,spear310-pinmux"; |
| 27 | reg = <0xb4000000 0x1000>; | 27 | reg = <0xb4000000 0x1000>; |
| 28 | #gpio-range-cells = <2>; | 28 | #gpio-range-cells = <3>; |
| 29 | }; | 29 | }; |
| 30 | 30 | ||
| 31 | fsmc: flash@44000000 { | 31 | fsmc: flash@44000000 { |
| @@ -102,7 +102,7 @@ | |||
| 102 | interrupt-controller; | 102 | interrupt-controller; |
| 103 | gpio-controller; | 103 | gpio-controller; |
| 104 | #gpio-cells = <2>; | 104 | #gpio-cells = <2>; |
| 105 | gpio-ranges = <&pinmux 0 102>; | 105 | gpio-ranges = <&pinmux 0 0 102>; |
| 106 | status = "disabled"; | 106 | status = "disabled"; |
| 107 | 107 | ||
| 108 | st-plgpio,ngpio = <102>; | 108 | st-plgpio,ngpio = <102>; |
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi index caa5520b1fd4..ffea342aeec9 100644 --- a/arch/arm/boot/dts/spear320.dtsi +++ b/arch/arm/boot/dts/spear320.dtsi | |||
| @@ -24,7 +24,7 @@ | |||
| 24 | pinmux: pinmux@b3000000 { | 24 | pinmux: pinmux@b3000000 { |
| 25 | compatible = "st,spear320-pinmux"; | 25 | compatible = "st,spear320-pinmux"; |
| 26 | reg = <0xb3000000 0x1000>; | 26 | reg = <0xb3000000 0x1000>; |
| 27 | #gpio-range-cells = <2>; | 27 | #gpio-range-cells = <3>; |
| 28 | }; | 28 | }; |
| 29 | 29 | ||
| 30 | clcd@90000000 { | 30 | clcd@90000000 { |
| @@ -130,7 +130,7 @@ | |||
| 130 | interrupt-controller; | 130 | interrupt-controller; |
| 131 | gpio-controller; | 131 | gpio-controller; |
| 132 | #gpio-cells = <2>; | 132 | #gpio-cells = <2>; |
| 133 | gpio-ranges = <&pinmux 0 102>; | 133 | gpio-ranges = <&pinmux 0 0 102>; |
| 134 | status = "disabled"; | 134 | status = "disabled"; |
| 135 | 135 | ||
| 136 | st-plgpio,ngpio = <102>; | 136 | st-plgpio,ngpio = <102>; |
diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi index 39446a247e79..615392a75676 100644 --- a/arch/arm/boot/dts/stuib.dtsi +++ b/arch/arm/boot/dts/stuib.dtsi | |||
| @@ -15,7 +15,7 @@ | |||
| 15 | stmpe1601: stmpe1601@40 { | 15 | stmpe1601: stmpe1601@40 { |
| 16 | compatible = "st,stmpe1601"; | 16 | compatible = "st,stmpe1601"; |
| 17 | reg = <0x40>; | 17 | reg = <0x40>; |
| 18 | interrupts = <26 0x1>; | 18 | interrupts = <26 0x2>; |
| 19 | interrupt-parent = <&gpio6>; | 19 | interrupt-parent = <&gpio6>; |
| 20 | interrupt-controller; | 20 | interrupt-controller; |
| 21 | 21 | ||
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 5cab82540437..b70fe0db6bb7 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts | |||
| @@ -26,13 +26,37 @@ | |||
| 26 | bootargs = "earlyprintk console=ttyS0,115200"; | 26 | bootargs = "earlyprintk console=ttyS0,115200"; |
| 27 | }; | 27 | }; |
| 28 | 28 | ||
| 29 | soc { | 29 | soc@01c20000 { |
| 30 | uart0: uart@01c28000 { | 30 | pinctrl@01c20800 { |
| 31 | status = "okay"; | 31 | led_pins_cubieboard: led_pins@0 { |
| 32 | allwinner,pins = "PH20", "PH21"; | ||
| 33 | allwinner,function = "gpio_out"; | ||
| 34 | allwinner,drive = <1>; | ||
| 35 | allwinner,pull = <0>; | ||
| 36 | }; | ||
| 32 | }; | 37 | }; |
| 33 | 38 | ||
| 34 | uart1: uart@01c28400 { | 39 | uart0: serial@01c28000 { |
| 40 | pinctrl-names = "default"; | ||
| 41 | pinctrl-0 = <&uart0_pins_a>; | ||
| 35 | status = "okay"; | 42 | status = "okay"; |
| 36 | }; | 43 | }; |
| 37 | }; | 44 | }; |
| 45 | |||
| 46 | leds { | ||
| 47 | compatible = "gpio-leds"; | ||
| 48 | pinctrl-names = "default"; | ||
| 49 | pinctrl-0 = <&led_pins_cubieboard>; | ||
| 50 | |||
| 51 | blue { | ||
| 52 | label = "cubieboard::blue"; | ||
| 53 | gpios = <&pio 7 21 0>; /* LED1 */ | ||
| 54 | }; | ||
| 55 | |||
| 56 | green { | ||
| 57 | label = "cubieboard::green"; | ||
| 58 | gpios = <&pio 7 20 0>; /* LED2 */ | ||
| 59 | linux,default-trigger = "heartbeat"; | ||
| 60 | }; | ||
| 61 | }; | ||
| 38 | }; | 62 | }; |
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index f84549ad791e..b9efac100c85 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts | |||
| @@ -22,8 +22,10 @@ | |||
| 22 | bootargs = "earlyprintk console=ttyS0,115200"; | 22 | bootargs = "earlyprintk console=ttyS0,115200"; |
| 23 | }; | 23 | }; |
| 24 | 24 | ||
| 25 | soc { | 25 | soc@01c20000 { |
| 26 | uart0: uart@01c28000 { | 26 | uart0: serial@01c28000 { |
| 27 | pinctrl-names = "default"; | ||
| 28 | pinctrl-0 = <&uart0_pins_a>; | ||
| 27 | status = "okay"; | 29 | status = "okay"; |
| 28 | }; | 30 | }; |
| 29 | }; | 31 | }; |
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts new file mode 100644 index 000000000000..4a7c35d6726a --- /dev/null +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2012 Maxime Ripard | ||
| 3 | * | ||
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | ||
| 5 | * | ||
| 6 | * The code contained herein is licensed under the GNU General Public | ||
| 7 | * License. You may obtain a copy of the GNU General Public License | ||
| 8 | * Version 2 or later at the following locations: | ||
| 9 | * | ||
| 10 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 11 | * http://www.gnu.org/copyleft/gpl.html | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | /include/ "sun4i-a10.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | model = "PineRiver Mini X-Plus"; | ||
| 19 | compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; | ||
| 20 | |||
| 21 | chosen { | ||
| 22 | bootargs = "earlyprintk console=ttyS0,115200"; | ||
| 23 | }; | ||
| 24 | |||
| 25 | soc { | ||
| 26 | uart0: uart@01c28000 { | ||
| 27 | pinctrl-names = "default"; | ||
| 28 | pinctrl-0 = <&uart0_pins_a>; | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | }; | ||
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index f99f60dadf5d..e7ef619a70a2 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi | |||
| @@ -10,19 +10,174 @@ | |||
| 10 | * http://www.gnu.org/copyleft/gpl.html | 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /include/ "sunxi.dtsi" | 13 | /include/ "skeleton.dtsi" |
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | interrupt-parent = <&intc>; | ||
| 17 | |||
| 18 | cpus { | ||
| 19 | cpu@0 { | ||
| 20 | compatible = "arm,cortex-a8"; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | |||
| 16 | memory { | 24 | memory { |
| 17 | reg = <0x40000000 0x80000000>; | 25 | reg = <0x40000000 0x80000000>; |
| 18 | }; | 26 | }; |
| 19 | 27 | ||
| 20 | soc { | 28 | clocks { |
| 21 | pinctrl@01c20800 { | 29 | #address-cells = <1>; |
| 30 | #size-cells = <1>; | ||
| 31 | ranges; | ||
| 32 | |||
| 33 | /* | ||
| 34 | * This is a dummy clock, to be used as placeholder on | ||
| 35 | * other mux clocks when a specific parent clock is not | ||
| 36 | * yet implemented. It should be dropped when the driver | ||
| 37 | * is complete. | ||
| 38 | */ | ||
| 39 | dummy: dummy { | ||
| 40 | #clock-cells = <0>; | ||
| 41 | compatible = "fixed-clock"; | ||
| 42 | clock-frequency = <0>; | ||
| 43 | }; | ||
| 44 | |||
| 45 | osc24M: osc24M@01c20050 { | ||
| 46 | #clock-cells = <0>; | ||
| 47 | compatible = "allwinner,sun4i-osc-clk"; | ||
| 48 | reg = <0x01c20050 0x4>; | ||
| 49 | clock-frequency = <24000000>; | ||
| 50 | }; | ||
| 51 | |||
| 52 | osc32k: osc32k { | ||
| 53 | #clock-cells = <0>; | ||
| 54 | compatible = "fixed-clock"; | ||
| 55 | clock-frequency = <32768>; | ||
| 56 | }; | ||
| 57 | |||
| 58 | pll1: pll1@01c20000 { | ||
| 59 | #clock-cells = <0>; | ||
| 60 | compatible = "allwinner,sun4i-pll1-clk"; | ||
| 61 | reg = <0x01c20000 0x4>; | ||
| 62 | clocks = <&osc24M>; | ||
| 63 | }; | ||
| 64 | |||
| 65 | /* dummy is 200M */ | ||
| 66 | cpu: cpu@01c20054 { | ||
| 67 | #clock-cells = <0>; | ||
| 68 | compatible = "allwinner,sun4i-cpu-clk"; | ||
| 69 | reg = <0x01c20054 0x4>; | ||
| 70 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | ||
| 71 | }; | ||
| 72 | |||
| 73 | axi: axi@01c20054 { | ||
| 74 | #clock-cells = <0>; | ||
| 75 | compatible = "allwinner,sun4i-axi-clk"; | ||
| 76 | reg = <0x01c20054 0x4>; | ||
| 77 | clocks = <&cpu>; | ||
| 78 | }; | ||
| 79 | |||
| 80 | axi_gates: axi_gates@01c2005c { | ||
| 81 | #clock-cells = <1>; | ||
| 82 | compatible = "allwinner,sun4i-axi-gates-clk"; | ||
| 83 | reg = <0x01c2005c 0x4>; | ||
| 84 | clocks = <&axi>; | ||
| 85 | clock-output-names = "axi_dram"; | ||
| 86 | }; | ||
| 87 | |||
| 88 | ahb: ahb@01c20054 { | ||
| 89 | #clock-cells = <0>; | ||
| 90 | compatible = "allwinner,sun4i-ahb-clk"; | ||
| 91 | reg = <0x01c20054 0x4>; | ||
| 92 | clocks = <&axi>; | ||
| 93 | }; | ||
| 94 | |||
| 95 | ahb_gates: ahb_gates@01c20060 { | ||
| 96 | #clock-cells = <1>; | ||
| 97 | compatible = "allwinner,sun4i-ahb-gates-clk"; | ||
| 98 | reg = <0x01c20060 0x8>; | ||
| 99 | clocks = <&ahb>; | ||
| 100 | clock-output-names = "ahb_usb0", "ahb_ehci0", | ||
| 101 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", | ||
| 102 | "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", | ||
| 103 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", | ||
| 104 | "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", | ||
| 105 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", | ||
| 106 | "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", | ||
| 107 | "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", | ||
| 108 | "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", | ||
| 109 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | ||
| 110 | "ahb_de_fe1", "ahb_mp", "ahb_mali400"; | ||
| 111 | }; | ||
| 112 | |||
| 113 | apb0: apb0@01c20054 { | ||
| 114 | #clock-cells = <0>; | ||
| 115 | compatible = "allwinner,sun4i-apb0-clk"; | ||
| 116 | reg = <0x01c20054 0x4>; | ||
| 117 | clocks = <&ahb>; | ||
| 118 | }; | ||
| 119 | |||
| 120 | apb0_gates: apb0_gates@01c20068 { | ||
| 121 | #clock-cells = <1>; | ||
| 122 | compatible = "allwinner,sun4i-apb0-gates-clk"; | ||
| 123 | reg = <0x01c20068 0x4>; | ||
| 124 | clocks = <&apb0>; | ||
| 125 | clock-output-names = "apb0_codec", "apb0_spdif", | ||
| 126 | "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", | ||
| 127 | "apb0_ir1", "apb0_keypad"; | ||
| 128 | }; | ||
| 129 | |||
| 130 | /* dummy is pll62 */ | ||
| 131 | apb1_mux: apb1_mux@01c20058 { | ||
| 132 | #clock-cells = <0>; | ||
| 133 | compatible = "allwinner,sun4i-apb1-mux-clk"; | ||
| 134 | reg = <0x01c20058 0x4>; | ||
| 135 | clocks = <&osc24M>, <&dummy>, <&osc32k>; | ||
| 136 | }; | ||
| 137 | |||
| 138 | apb1: apb1@01c20058 { | ||
| 139 | #clock-cells = <0>; | ||
| 140 | compatible = "allwinner,sun4i-apb1-clk"; | ||
| 141 | reg = <0x01c20058 0x4>; | ||
| 142 | clocks = <&apb1_mux>; | ||
| 143 | }; | ||
| 144 | |||
| 145 | apb1_gates: apb1_gates@01c2006c { | ||
| 146 | #clock-cells = <1>; | ||
| 147 | compatible = "allwinner,sun4i-apb1-gates-clk"; | ||
| 148 | reg = <0x01c2006c 0x4>; | ||
| 149 | clocks = <&apb1>; | ||
| 150 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | ||
| 151 | "apb1_i2c2", "apb1_can", "apb1_scr", | ||
| 152 | "apb1_ps20", "apb1_ps21", "apb1_uart0", | ||
| 153 | "apb1_uart1", "apb1_uart2", "apb1_uart3", | ||
| 154 | "apb1_uart4", "apb1_uart5", "apb1_uart6", | ||
| 155 | "apb1_uart7"; | ||
| 156 | }; | ||
| 157 | }; | ||
| 158 | |||
| 159 | soc@01c20000 { | ||
| 160 | compatible = "simple-bus"; | ||
| 161 | #address-cells = <1>; | ||
| 162 | #size-cells = <1>; | ||
| 163 | reg = <0x01c20000 0x300000>; | ||
| 164 | ranges; | ||
| 165 | |||
| 166 | intc: interrupt-controller@01c20400 { | ||
| 167 | compatible = "allwinner,sun4i-ic"; | ||
| 168 | reg = <0x01c20400 0x400>; | ||
| 169 | interrupt-controller; | ||
| 170 | #interrupt-cells = <1>; | ||
| 171 | }; | ||
| 172 | |||
| 173 | pio: pinctrl@01c20800 { | ||
| 22 | compatible = "allwinner,sun4i-a10-pinctrl"; | 174 | compatible = "allwinner,sun4i-a10-pinctrl"; |
| 23 | reg = <0x01c20800 0x400>; | 175 | reg = <0x01c20800 0x400>; |
| 176 | clocks = <&apb0_gates 5>; | ||
| 177 | gpio-controller; | ||
| 24 | #address-cells = <1>; | 178 | #address-cells = <1>; |
| 25 | #size-cells = <0>; | 179 | #size-cells = <0>; |
| 180 | #gpio-cells = <3>; | ||
| 26 | 181 | ||
| 27 | uart0_pins_a: uart0@0 { | 182 | uart0_pins_a: uart0@0 { |
| 28 | allwinner,pins = "PB22", "PB23"; | 183 | allwinner,pins = "PB22", "PB23"; |
| @@ -45,5 +200,97 @@ | |||
| 45 | allwinner,pull = <0>; | 200 | allwinner,pull = <0>; |
| 46 | }; | 201 | }; |
| 47 | }; | 202 | }; |
| 203 | |||
| 204 | timer@01c20c00 { | ||
| 205 | compatible = "allwinner,sun4i-timer"; | ||
| 206 | reg = <0x01c20c00 0x90>; | ||
| 207 | interrupts = <22>; | ||
| 208 | clocks = <&osc24M>; | ||
| 209 | }; | ||
| 210 | |||
| 211 | wdt: watchdog@01c20c90 { | ||
| 212 | compatible = "allwinner,sun4i-wdt"; | ||
| 213 | reg = <0x01c20c90 0x10>; | ||
| 214 | }; | ||
| 215 | |||
| 216 | uart0: serial@01c28000 { | ||
| 217 | compatible = "snps,dw-apb-uart"; | ||
| 218 | reg = <0x01c28000 0x400>; | ||
| 219 | interrupts = <1>; | ||
| 220 | reg-shift = <2>; | ||
| 221 | reg-io-width = <4>; | ||
| 222 | clocks = <&apb1_gates 16>; | ||
| 223 | status = "disabled"; | ||
| 224 | }; | ||
| 225 | |||
| 226 | uart1: serial@01c28400 { | ||
| 227 | compatible = "snps,dw-apb-uart"; | ||
| 228 | reg = <0x01c28400 0x400>; | ||
| 229 | interrupts = <2>; | ||
| 230 | reg-shift = <2>; | ||
| 231 | reg-io-width = <4>; | ||
| 232 | clocks = <&apb1_gates 17>; | ||
| 233 | status = "disabled"; | ||
| 234 | }; | ||
| 235 | |||
| 236 | uart2: serial@01c28800 { | ||
| 237 | compatible = "snps,dw-apb-uart"; | ||
| 238 | reg = <0x01c28800 0x400>; | ||
| 239 | interrupts = <3>; | ||
| 240 | reg-shift = <2>; | ||
| 241 | reg-io-width = <4>; | ||
| 242 | clocks = <&apb1_gates 18>; | ||
| 243 | status = "disabled"; | ||
| 244 | }; | ||
| 245 | |||
| 246 | uart3: serial@01c28c00 { | ||
| 247 | compatible = "snps,dw-apb-uart"; | ||
| 248 | reg = <0x01c28c00 0x400>; | ||
| 249 | interrupts = <4>; | ||
| 250 | reg-shift = <2>; | ||
| 251 | reg-io-width = <4>; | ||
| 252 | clocks = <&apb1_gates 19>; | ||
| 253 | status = "disabled"; | ||
| 254 | }; | ||
| 255 | |||
| 256 | uart4: serial@01c29000 { | ||
| 257 | compatible = "snps,dw-apb-uart"; | ||
| 258 | reg = <0x01c29000 0x400>; | ||
| 259 | interrupts = <17>; | ||
| 260 | reg-shift = <2>; | ||
| 261 | reg-io-width = <4>; | ||
| 262 | clocks = <&apb1_gates 20>; | ||
| 263 | status = "disabled"; | ||
| 264 | }; | ||
| 265 | |||
| 266 | uart5: serial@01c29400 { | ||
| 267 | compatible = "snps,dw-apb-uart"; | ||
| 268 | reg = <0x01c29400 0x400>; | ||
| 269 | interrupts = <18>; | ||
| 270 | reg-shift = <2>; | ||
| 271 | reg-io-width = <4>; | ||
| 272 | clocks = <&apb1_gates 21>; | ||
| 273 | status = "disabled"; | ||
| 274 | }; | ||
| 275 | |||
| 276 | uart6: serial@01c29800 { | ||
| 277 | compatible = "snps,dw-apb-uart"; | ||
| 278 | reg = <0x01c29800 0x400>; | ||
| 279 | interrupts = <19>; | ||
| 280 | reg-shift = <2>; | ||
| 281 | reg-io-width = <4>; | ||
| 282 | clocks = <&apb1_gates 22>; | ||
| 283 | status = "disabled"; | ||
| 284 | }; | ||
| 285 | |||
| 286 | uart7: serial@01c29c00 { | ||
| 287 | compatible = "snps,dw-apb-uart"; | ||
| 288 | reg = <0x01c29c00 0x400>; | ||
| 289 | interrupts = <20>; | ||
| 290 | reg-shift = <2>; | ||
| 291 | reg-io-width = <4>; | ||
| 292 | clocks = <&apb1_gates 23>; | ||
| 293 | status = "disabled"; | ||
| 294 | }; | ||
| 48 | }; | 295 | }; |
| 49 | }; | 296 | }; |
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 4a1e45d4aace..3ca55067f868 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts | |||
| @@ -22,11 +22,31 @@ | |||
| 22 | bootargs = "earlyprintk console=ttyS0,115200"; | 22 | bootargs = "earlyprintk console=ttyS0,115200"; |
| 23 | }; | 23 | }; |
| 24 | 24 | ||
| 25 | soc { | 25 | soc@01c20000 { |
| 26 | uart1: uart@01c28400 { | 26 | pinctrl@01c20800 { |
| 27 | led_pins_olinuxino: led_pins@0 { | ||
| 28 | allwinner,pins = "PG9"; | ||
| 29 | allwinner,function = "gpio_out"; | ||
| 30 | allwinner,drive = <1>; | ||
| 31 | allwinner,pull = <0>; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | |||
| 35 | uart1: serial@01c28400 { | ||
| 27 | pinctrl-names = "default"; | 36 | pinctrl-names = "default"; |
| 28 | pinctrl-0 = <&uart1_pins_b>; | 37 | pinctrl-0 = <&uart1_pins_b>; |
| 29 | status = "okay"; | 38 | status = "okay"; |
| 30 | }; | 39 | }; |
| 31 | }; | 40 | }; |
| 41 | |||
| 42 | leds { | ||
| 43 | compatible = "gpio-leds"; | ||
| 44 | pinctrl-names = "default"; | ||
| 45 | pinctrl-0 = <&led_pins_olinuxino>; | ||
| 46 | |||
| 47 | power { | ||
| 48 | gpios = <&pio 6 9 0>; | ||
| 49 | default-state = "on"; | ||
| 50 | }; | ||
| 51 | }; | ||
| 32 | }; | 52 | }; |
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index e1121890fb29..31fa38f8cc98 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi | |||
| @@ -11,19 +11,174 @@ | |||
| 11 | * http://www.gnu.org/copyleft/gpl.html | 11 | * http://www.gnu.org/copyleft/gpl.html |
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | /include/ "sunxi.dtsi" | 14 | /include/ "skeleton.dtsi" |
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | interrupt-parent = <&intc>; | ||
| 18 | |||
| 19 | cpus { | ||
| 20 | cpu@0 { | ||
| 21 | compatible = "arm,cortex-a8"; | ||
| 22 | }; | ||
| 23 | }; | ||
| 24 | |||
| 17 | memory { | 25 | memory { |
| 18 | reg = <0x40000000 0x20000000>; | 26 | reg = <0x40000000 0x20000000>; |
| 19 | }; | 27 | }; |
| 20 | 28 | ||
| 21 | soc { | 29 | clocks { |
| 22 | pinctrl@01c20800 { | 30 | #address-cells = <1>; |
| 31 | #size-cells = <1>; | ||
| 32 | ranges; | ||
| 33 | |||
| 34 | /* | ||
| 35 | * This is a dummy clock, to be used as placeholder on | ||
| 36 | * other mux clocks when a specific parent clock is not | ||
| 37 | * yet implemented. It should be dropped when the driver | ||
| 38 | * is complete. | ||
| 39 | */ | ||
| 40 | dummy: dummy { | ||
| 41 | #clock-cells = <0>; | ||
| 42 | compatible = "fixed-clock"; | ||
| 43 | clock-frequency = <0>; | ||
| 44 | }; | ||
| 45 | |||
| 46 | osc24M: osc24M@01c20050 { | ||
| 47 | #clock-cells = <0>; | ||
| 48 | compatible = "allwinner,sun4i-osc-clk"; | ||
| 49 | reg = <0x01c20050 0x4>; | ||
| 50 | clock-frequency = <24000000>; | ||
| 51 | }; | ||
| 52 | |||
| 53 | osc32k: osc32k { | ||
| 54 | #clock-cells = <0>; | ||
| 55 | compatible = "fixed-clock"; | ||
| 56 | clock-frequency = <32768>; | ||
| 57 | }; | ||
| 58 | |||
| 59 | pll1: pll1@01c20000 { | ||
| 60 | #clock-cells = <0>; | ||
| 61 | compatible = "allwinner,sun4i-pll1-clk"; | ||
| 62 | reg = <0x01c20000 0x4>; | ||
| 63 | clocks = <&osc24M>; | ||
| 64 | }; | ||
| 65 | |||
| 66 | /* dummy is 200M */ | ||
| 67 | cpu: cpu@01c20054 { | ||
| 68 | #clock-cells = <0>; | ||
| 69 | compatible = "allwinner,sun4i-cpu-clk"; | ||
| 70 | reg = <0x01c20054 0x4>; | ||
| 71 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | ||
| 72 | }; | ||
| 73 | |||
| 74 | axi: axi@01c20054 { | ||
| 75 | #clock-cells = <0>; | ||
| 76 | compatible = "allwinner,sun4i-axi-clk"; | ||
| 77 | reg = <0x01c20054 0x4>; | ||
| 78 | clocks = <&cpu>; | ||
| 79 | }; | ||
| 80 | |||
| 81 | axi_gates: axi_gates@01c2005c { | ||
| 82 | #clock-cells = <1>; | ||
| 83 | compatible = "allwinner,sun4i-axi-gates-clk"; | ||
| 84 | reg = <0x01c2005c 0x4>; | ||
| 85 | clocks = <&axi>; | ||
| 86 | clock-output-names = "axi_dram"; | ||
| 87 | }; | ||
| 88 | |||
| 89 | ahb: ahb@01c20054 { | ||
| 90 | #clock-cells = <0>; | ||
| 91 | compatible = "allwinner,sun4i-ahb-clk"; | ||
| 92 | reg = <0x01c20054 0x4>; | ||
| 93 | clocks = <&axi>; | ||
| 94 | }; | ||
| 95 | |||
| 96 | ahb_gates: ahb_gates@01c20060 { | ||
| 97 | #clock-cells = <1>; | ||
| 98 | compatible = "allwinner,sun4i-ahb-gates-clk"; | ||
| 99 | reg = <0x01c20060 0x8>; | ||
| 100 | clocks = <&ahb>; | ||
| 101 | clock-output-names = "ahb_usb0", "ahb_ehci0", | ||
| 102 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", | ||
| 103 | "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", | ||
| 104 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", | ||
| 105 | "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", | ||
| 106 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", | ||
| 107 | "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", | ||
| 108 | "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", | ||
| 109 | "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", | ||
| 110 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | ||
| 111 | "ahb_de_fe1", "ahb_mp", "ahb_mali400"; | ||
| 112 | }; | ||
| 113 | |||
| 114 | apb0: apb0@01c20054 { | ||
| 115 | #clock-cells = <0>; | ||
| 116 | compatible = "allwinner,sun4i-apb0-clk"; | ||
| 117 | reg = <0x01c20054 0x4>; | ||
| 118 | clocks = <&ahb>; | ||
| 119 | }; | ||
| 120 | |||
| 121 | apb0_gates: apb0_gates@01c20068 { | ||
| 122 | #clock-cells = <1>; | ||
| 123 | compatible = "allwinner,sun4i-apb0-gates-clk"; | ||
| 124 | reg = <0x01c20068 0x4>; | ||
| 125 | clocks = <&apb0>; | ||
| 126 | clock-output-names = "apb0_codec", "apb0_spdif", | ||
| 127 | "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", | ||
| 128 | "apb0_ir1", "apb0_keypad"; | ||
| 129 | }; | ||
| 130 | |||
| 131 | /* dummy is pll62 */ | ||
| 132 | apb1_mux: apb1_mux@01c20058 { | ||
| 133 | #clock-cells = <0>; | ||
| 134 | compatible = "allwinner,sun4i-apb1-mux-clk"; | ||
| 135 | reg = <0x01c20058 0x4>; | ||
| 136 | clocks = <&osc24M>, <&dummy>, <&osc32k>; | ||
| 137 | }; | ||
| 138 | |||
| 139 | apb1: apb1@01c20058 { | ||
| 140 | #clock-cells = <0>; | ||
| 141 | compatible = "allwinner,sun4i-apb1-clk"; | ||
| 142 | reg = <0x01c20058 0x4>; | ||
| 143 | clocks = <&apb1_mux>; | ||
| 144 | }; | ||
| 145 | |||
| 146 | apb1_gates: apb1_gates@01c2006c { | ||
| 147 | #clock-cells = <1>; | ||
| 148 | compatible = "allwinner,sun4i-apb1-gates-clk"; | ||
| 149 | reg = <0x01c2006c 0x4>; | ||
| 150 | clocks = <&apb1>; | ||
| 151 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | ||
| 152 | "apb1_i2c2", "apb1_can", "apb1_scr", | ||
| 153 | "apb1_ps20", "apb1_ps21", "apb1_uart0", | ||
| 154 | "apb1_uart1", "apb1_uart2", "apb1_uart3", | ||
| 155 | "apb1_uart4", "apb1_uart5", "apb1_uart6", | ||
| 156 | "apb1_uart7"; | ||
| 157 | }; | ||
| 158 | }; | ||
| 159 | |||
| 160 | soc@01c20000 { | ||
| 161 | compatible = "simple-bus"; | ||
| 162 | #address-cells = <1>; | ||
| 163 | #size-cells = <1>; | ||
| 164 | reg = <0x01c20000 0x300000>; | ||
| 165 | ranges; | ||
| 166 | |||
| 167 | intc: interrupt-controller@01c20400 { | ||
| 168 | compatible = "allwinner,sun4i-ic"; | ||
| 169 | reg = <0x01c20400 0x400>; | ||
| 170 | interrupt-controller; | ||
| 171 | #interrupt-cells = <1>; | ||
| 172 | }; | ||
| 173 | |||
| 174 | pio: pinctrl@01c20800 { | ||
| 23 | compatible = "allwinner,sun5i-a13-pinctrl"; | 175 | compatible = "allwinner,sun5i-a13-pinctrl"; |
| 24 | reg = <0x01c20800 0x400>; | 176 | reg = <0x01c20800 0x400>; |
| 177 | clocks = <&apb0_gates 5>; | ||
| 178 | gpio-controller; | ||
| 25 | #address-cells = <1>; | 179 | #address-cells = <1>; |
| 26 | #size-cells = <0>; | 180 | #size-cells = <0>; |
| 181 | #gpio-cells = <3>; | ||
| 27 | 182 | ||
| 28 | uart1_pins_a: uart1@0 { | 183 | uart1_pins_a: uart1@0 { |
| 29 | allwinner,pins = "PE10", "PE11"; | 184 | allwinner,pins = "PE10", "PE11"; |
| @@ -39,5 +194,37 @@ | |||
| 39 | allwinner,pull = <0>; | 194 | allwinner,pull = <0>; |
| 40 | }; | 195 | }; |
| 41 | }; | 196 | }; |
| 197 | |||
| 198 | timer@01c20c00 { | ||
| 199 | compatible = "allwinner,sun4i-timer"; | ||
| 200 | reg = <0x01c20c00 0x90>; | ||
| 201 | interrupts = <22>; | ||
| 202 | clocks = <&osc24M>; | ||
| 203 | }; | ||
| 204 | |||
| 205 | wdt: watchdog@01c20c90 { | ||
| 206 | compatible = "allwinner,sun4i-wdt"; | ||
| 207 | reg = <0x01c20c90 0x10>; | ||
| 208 | }; | ||
| 209 | |||
| 210 | uart1: serial@01c28400 { | ||
| 211 | compatible = "snps,dw-apb-uart"; | ||
| 212 | reg = <0x01c28400 0x400>; | ||
| 213 | interrupts = <2>; | ||
| 214 | reg-shift = <2>; | ||
| 215 | reg-io-width = <4>; | ||
| 216 | clocks = <&apb1_gates 17>; | ||
| 217 | status = "disabled"; | ||
| 218 | }; | ||
| 219 | |||
| 220 | uart3: serial@01c28c00 { | ||
| 221 | compatible = "snps,dw-apb-uart"; | ||
| 222 | reg = <0x01c28c00 0x400>; | ||
| 223 | interrupts = <4>; | ||
| 224 | reg-shift = <2>; | ||
| 225 | reg-io-width = <4>; | ||
| 226 | clocks = <&apb1_gates 19>; | ||
| 227 | status = "disabled"; | ||
| 228 | }; | ||
| 42 | }; | 229 | }; |
| 43 | }; | 230 | }; |
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi deleted file mode 100644 index 8b36abea9f2e..000000000000 --- a/arch/arm/boot/dts/sunxi.dtsi +++ /dev/null | |||
| @@ -1,82 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2012 Maxime Ripard | ||
| 3 | * | ||
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | ||
| 5 | * | ||
| 6 | * The code contained herein is licensed under the GNU General Public | ||
| 7 | * License. You may obtain a copy of the GNU General Public License | ||
| 8 | * Version 2 or later at the following locations: | ||
| 9 | * | ||
| 10 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 11 | * http://www.gnu.org/copyleft/gpl.html | ||
| 12 | */ | ||
| 13 | |||
| 14 | /include/ "skeleton.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | interrupt-parent = <&intc>; | ||
| 18 | |||
| 19 | cpus { | ||
| 20 | cpu@0 { | ||
| 21 | compatible = "arm,cortex-a8"; | ||
| 22 | }; | ||
| 23 | }; | ||
| 24 | |||
| 25 | clocks { | ||
| 26 | #address-cells = <1>; | ||
| 27 | #size-cells = <0>; | ||
| 28 | |||
| 29 | osc: oscillator { | ||
| 30 | #clock-cells = <0>; | ||
| 31 | compatible = "fixed-clock"; | ||
| 32 | clock-frequency = <24000000>; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | |||
| 36 | soc { | ||
| 37 | compatible = "simple-bus"; | ||
| 38 | #address-cells = <1>; | ||
| 39 | #size-cells = <1>; | ||
| 40 | reg = <0x01c20000 0x300000>; | ||
| 41 | ranges; | ||
| 42 | |||
| 43 | timer@01c20c00 { | ||
| 44 | compatible = "allwinner,sunxi-timer"; | ||
| 45 | reg = <0x01c20c00 0x90>; | ||
| 46 | interrupts = <22>; | ||
| 47 | clocks = <&osc>; | ||
| 48 | }; | ||
| 49 | |||
| 50 | wdt: watchdog@01c20c90 { | ||
| 51 | compatible = "allwinner,sunxi-wdt"; | ||
| 52 | reg = <0x01c20c90 0x10>; | ||
| 53 | }; | ||
| 54 | |||
| 55 | intc: interrupt-controller@01c20400 { | ||
| 56 | compatible = "allwinner,sunxi-ic"; | ||
| 57 | reg = <0x01c20400 0x400>; | ||
| 58 | interrupt-controller; | ||
| 59 | #interrupt-cells = <1>; | ||
| 60 | }; | ||
| 61 | |||
| 62 | uart0: uart@01c28000 { | ||
| 63 | compatible = "snps,dw-apb-uart"; | ||
| 64 | reg = <0x01c28000 0x400>; | ||
| 65 | interrupts = <1>; | ||
| 66 | reg-shift = <2>; | ||
| 67 | reg-io-width = <4>; | ||
| 68 | clock-frequency = <24000000>; | ||
| 69 | status = "disabled"; | ||
| 70 | }; | ||
| 71 | |||
| 72 | uart1: uart@01c28400 { | ||
| 73 | compatible = "snps,dw-apb-uart"; | ||
| 74 | reg = <0x01c28400 0x400>; | ||
| 75 | interrupts = <2>; | ||
| 76 | reg-shift = <2>; | ||
| 77 | reg-io-width = <4>; | ||
| 78 | clock-frequency = <24000000>; | ||
| 79 | status = "disabled"; | ||
| 80 | }; | ||
| 81 | }; | ||
| 82 | }; | ||
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index a30aca62658a..6ebc1b704190 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts | |||
| @@ -18,4 +18,17 @@ | |||
| 18 | pmc { | 18 | pmc { |
| 19 | nvidia,invert-interrupt; | 19 | nvidia,invert-interrupt; |
| 20 | }; | 20 | }; |
| 21 | |||
| 22 | clocks { | ||
| 23 | compatible = "simple-bus"; | ||
| 24 | #address-cells = <1>; | ||
| 25 | #size-cells = <0>; | ||
| 26 | |||
| 27 | clk32k_in: clock { | ||
| 28 | compatible = "fixed-clock"; | ||
| 29 | reg=<0>; | ||
| 30 | #clock-cells = <0>; | ||
| 31 | clock-frequency = <32768>; | ||
| 32 | }; | ||
| 33 | }; | ||
| 21 | }; | 34 | }; |
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts index 9bea8f57aa47..5deb8692b350 100644 --- a/arch/arm/boot/dts/tegra114-pluto.dts +++ b/arch/arm/boot/dts/tegra114-pluto.dts | |||
| @@ -18,4 +18,17 @@ | |||
| 18 | pmc { | 18 | pmc { |
| 19 | nvidia,invert-interrupt; | 19 | nvidia,invert-interrupt; |
| 20 | }; | 20 | }; |
| 21 | |||
| 22 | clocks { | ||
| 23 | compatible = "simple-bus"; | ||
| 24 | #address-cells = <1>; | ||
| 25 | #size-cells = <0>; | ||
| 26 | |||
| 27 | clk32k_in: clock { | ||
| 28 | compatible = "fixed-clock"; | ||
| 29 | reg=<0>; | ||
| 30 | #clock-cells = <0>; | ||
| 31 | clock-frequency = <32768>; | ||
| 32 | }; | ||
| 33 | }; | ||
| 21 | }; | 34 | }; |
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 1dfaf2874c57..c0b527d15fda 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi | |||
| @@ -99,8 +99,10 @@ | |||
| 99 | }; | 99 | }; |
| 100 | 100 | ||
| 101 | pmc { | 101 | pmc { |
| 102 | compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc"; | 102 | compatible = "nvidia,tegra114-pmc"; |
| 103 | reg = <0x7000e400 0x400>; | 103 | reg = <0x7000e400 0x400>; |
| 104 | clocks = <&tegra_car 261>, <&clk32k_in>; | ||
| 105 | clock-names = "pclk", "clk32k_in"; | ||
| 104 | }; | 106 | }; |
| 105 | 107 | ||
| 106 | iommu { | 108 | iommu { |
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index 444162090042..4e3afdef28a8 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi | |||
| @@ -444,7 +444,20 @@ | |||
| 444 | }; | 444 | }; |
| 445 | 445 | ||
| 446 | sdhci@c8000600 { | 446 | sdhci@c8000600 { |
| 447 | cd-gpios = <&gpio 23 0>; /* gpio PC7 */ | 447 | cd-gpios = <&gpio 23 1>; /* gpio PC7 */ |
| 448 | }; | ||
| 449 | |||
| 450 | clocks { | ||
| 451 | compatible = "simple-bus"; | ||
| 452 | #address-cells = <1>; | ||
| 453 | #size-cells = <0>; | ||
| 454 | |||
| 455 | clk32k_in: clock { | ||
| 456 | compatible = "fixed-clock"; | ||
| 457 | reg=<0>; | ||
| 458 | #clock-cells = <0>; | ||
| 459 | clock-frequency = <32768>; | ||
| 460 | }; | ||
| 448 | }; | 461 | }; |
| 449 | 462 | ||
| 450 | sound { | 463 | sound { |
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 61d027f03617..ae9d5a20834e 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts | |||
| @@ -437,7 +437,7 @@ | |||
| 437 | 437 | ||
| 438 | sdhci@c8000200 { | 438 | sdhci@c8000200 { |
| 439 | status = "okay"; | 439 | status = "okay"; |
| 440 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | 440 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ |
| 441 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | 441 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ |
| 442 | power-gpios = <&gpio 155 0>; /* gpio PT3 */ | 442 | power-gpios = <&gpio 155 0>; /* gpio PT3 */ |
| 443 | bus-width = <4>; | 443 | bus-width = <4>; |
| @@ -445,12 +445,25 @@ | |||
| 445 | 445 | ||
| 446 | sdhci@c8000600 { | 446 | sdhci@c8000600 { |
| 447 | status = "okay"; | 447 | status = "okay"; |
| 448 | cd-gpios = <&gpio 58 0>; /* gpio PH2 */ | 448 | cd-gpios = <&gpio 58 1>; /* gpio PH2 */ |
| 449 | wp-gpios = <&gpio 59 0>; /* gpio PH3 */ | 449 | wp-gpios = <&gpio 59 0>; /* gpio PH3 */ |
| 450 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ | 450 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ |
| 451 | bus-width = <8>; | 451 | bus-width = <8>; |
| 452 | }; | 452 | }; |
| 453 | 453 | ||
| 454 | clocks { | ||
| 455 | compatible = "simple-bus"; | ||
| 456 | #address-cells = <1>; | ||
| 457 | #size-cells = <0>; | ||
| 458 | |||
| 459 | clk32k_in: clock { | ||
| 460 | compatible = "fixed-clock"; | ||
| 461 | reg=<0>; | ||
| 462 | #clock-cells = <0>; | ||
| 463 | clock-frequency = <32768>; | ||
| 464 | }; | ||
| 465 | }; | ||
| 466 | |||
| 454 | kbc { | 467 | kbc { |
| 455 | status = "okay"; | 468 | status = "okay"; |
| 456 | nvidia,debounce-delay-ms = <2>; | 469 | nvidia,debounce-delay-ms = <2>; |
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 54d6fce00a59..fd60940e4063 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts | |||
| @@ -436,7 +436,7 @@ | |||
| 436 | 436 | ||
| 437 | sdhci@c8000000 { | 437 | sdhci@c8000000 { |
| 438 | status = "okay"; | 438 | status = "okay"; |
| 439 | cd-gpios = <&gpio 173 0>; /* gpio PV5 */ | 439 | cd-gpios = <&gpio 173 1>; /* gpio PV5 */ |
| 440 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | 440 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ |
| 441 | power-gpios = <&gpio 169 0>; /* gpio PV1 */ | 441 | power-gpios = <&gpio 169 0>; /* gpio PV1 */ |
| 442 | bus-width = <4>; | 442 | bus-width = <4>; |
| @@ -447,6 +447,19 @@ | |||
| 447 | bus-width = <8>; | 447 | bus-width = <8>; |
| 448 | }; | 448 | }; |
| 449 | 449 | ||
| 450 | clocks { | ||
| 451 | compatible = "simple-bus"; | ||
| 452 | #address-cells = <1>; | ||
| 453 | #size-cells = <0>; | ||
| 454 | |||
| 455 | clk32k_in: clock { | ||
| 456 | compatible = "fixed-clock"; | ||
| 457 | reg=<0>; | ||
| 458 | #clock-cells = <0>; | ||
| 459 | clock-frequency = <32768>; | ||
| 460 | }; | ||
| 461 | }; | ||
| 462 | |||
| 450 | gpio-keys { | 463 | gpio-keys { |
| 451 | compatible = "gpio-keys"; | 464 | compatible = "gpio-keys"; |
| 452 | 465 | ||
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 37b3a57ec0f1..4ee700a33ca5 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts | |||
| @@ -584,7 +584,7 @@ | |||
| 584 | 584 | ||
| 585 | sdhci@c8000400 { | 585 | sdhci@c8000400 { |
| 586 | status = "okay"; | 586 | status = "okay"; |
| 587 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | 587 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ |
| 588 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | 588 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ |
| 589 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ | 589 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ |
| 590 | bus-width = <4>; | 590 | bus-width = <4>; |
| @@ -595,6 +595,19 @@ | |||
| 595 | bus-width = <8>; | 595 | bus-width = <8>; |
| 596 | }; | 596 | }; |
| 597 | 597 | ||
| 598 | clocks { | ||
| 599 | compatible = "simple-bus"; | ||
| 600 | #address-cells = <1>; | ||
| 601 | #size-cells = <0>; | ||
| 602 | |||
| 603 | clk32k_in: clock { | ||
| 604 | compatible = "fixed-clock"; | ||
| 605 | reg=<0>; | ||
| 606 | #clock-cells = <0>; | ||
| 607 | clock-frequency = <32768>; | ||
| 608 | }; | ||
| 609 | }; | ||
| 610 | |||
| 598 | gpio-keys { | 611 | gpio-keys { |
| 599 | compatible = "gpio-keys"; | 612 | compatible = "gpio-keys"; |
| 600 | 613 | ||
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 4766abae7a72..c19025725918 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi | |||
| @@ -465,12 +465,25 @@ | |||
| 465 | }; | 465 | }; |
| 466 | 466 | ||
| 467 | sdhci@c8000600 { | 467 | sdhci@c8000600 { |
| 468 | cd-gpios = <&gpio 58 0>; /* gpio PH2 */ | 468 | cd-gpios = <&gpio 58 1>; /* gpio PH2 */ |
| 469 | wp-gpios = <&gpio 59 0>; /* gpio PH3 */ | 469 | wp-gpios = <&gpio 59 0>; /* gpio PH3 */ |
| 470 | bus-width = <4>; | 470 | bus-width = <4>; |
| 471 | status = "okay"; | 471 | status = "okay"; |
| 472 | }; | 472 | }; |
| 473 | 473 | ||
| 474 | clocks { | ||
| 475 | compatible = "simple-bus"; | ||
| 476 | #address-cells = <1>; | ||
| 477 | #size-cells = <0>; | ||
| 478 | |||
| 479 | clk32k_in: clock { | ||
| 480 | compatible = "fixed-clock"; | ||
| 481 | reg=<0>; | ||
| 482 | #clock-cells = <0>; | ||
| 483 | clock-frequency = <32768>; | ||
| 484 | }; | ||
| 485 | }; | ||
| 486 | |||
| 474 | regulators { | 487 | regulators { |
| 475 | compatible = "simple-bus"; | 488 | compatible = "simple-bus"; |
| 476 | 489 | ||
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 5d79e4fc49a6..a9f3f06580f5 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts | |||
| @@ -325,11 +325,24 @@ | |||
| 325 | 325 | ||
| 326 | sdhci@c8000600 { | 326 | sdhci@c8000600 { |
| 327 | status = "okay"; | 327 | status = "okay"; |
| 328 | cd-gpios = <&gpio 121 0>; /* gpio PP1 */ | 328 | cd-gpios = <&gpio 121 1>; /* gpio PP1 */ |
| 329 | wp-gpios = <&gpio 122 0>; /* gpio PP2 */ | 329 | wp-gpios = <&gpio 122 0>; /* gpio PP2 */ |
| 330 | bus-width = <4>; | 330 | bus-width = <4>; |
| 331 | }; | 331 | }; |
| 332 | 332 | ||
| 333 | clocks { | ||
| 334 | compatible = "simple-bus"; | ||
| 335 | #address-cells = <1>; | ||
| 336 | #size-cells = <0>; | ||
| 337 | |||
| 338 | clk32k_in: clock { | ||
| 339 | compatible = "fixed-clock"; | ||
| 340 | reg=<0>; | ||
| 341 | #clock-cells = <0>; | ||
| 342 | clock-frequency = <32768>; | ||
| 343 | }; | ||
| 344 | }; | ||
| 345 | |||
| 333 | poweroff { | 346 | poweroff { |
| 334 | compatible = "gpio-poweroff"; | 347 | compatible = "gpio-poweroff"; |
| 335 | gpios = <&gpio 191 1>; /* gpio PX7, active low */ | 348 | gpios = <&gpio 191 1>; /* gpio PX7, active low */ |
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 425c89000c20..f544806e9618 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts | |||
| @@ -520,7 +520,7 @@ | |||
| 520 | 520 | ||
| 521 | sdhci@c8000400 { | 521 | sdhci@c8000400 { |
| 522 | status = "okay"; | 522 | status = "okay"; |
| 523 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | 523 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ |
| 524 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | 524 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ |
| 525 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ | 525 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ |
| 526 | bus-width = <4>; | 526 | bus-width = <4>; |
| @@ -531,6 +531,19 @@ | |||
| 531 | bus-width = <8>; | 531 | bus-width = <8>; |
| 532 | }; | 532 | }; |
| 533 | 533 | ||
| 534 | clocks { | ||
| 535 | compatible = "simple-bus"; | ||
| 536 | #address-cells = <1>; | ||
| 537 | #size-cells = <0>; | ||
| 538 | |||
| 539 | clk32k_in: clock { | ||
| 540 | compatible = "fixed-clock"; | ||
| 541 | reg=<0>; | ||
| 542 | #clock-cells = <0>; | ||
| 543 | clock-frequency = <32768>; | ||
| 544 | }; | ||
| 545 | }; | ||
| 546 | |||
| 534 | regulators { | 547 | regulators { |
| 535 | compatible = "simple-bus"; | 548 | compatible = "simple-bus"; |
| 536 | #address-cells = <1>; | 549 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index ea57c0f6dcce..258cf945f515 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts | |||
| @@ -510,6 +510,7 @@ | |||
| 510 | 510 | ||
| 511 | sdhci@c8000400 { | 511 | sdhci@c8000400 { |
| 512 | status = "okay"; | 512 | status = "okay"; |
| 513 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ | ||
| 513 | wp-gpios = <&gpio 173 0>; /* gpio PV5 */ | 514 | wp-gpios = <&gpio 173 0>; /* gpio PV5 */ |
| 514 | bus-width = <8>; | 515 | bus-width = <8>; |
| 515 | }; | 516 | }; |
| @@ -519,6 +520,19 @@ | |||
| 519 | bus-width = <8>; | 520 | bus-width = <8>; |
| 520 | }; | 521 | }; |
| 521 | 522 | ||
| 523 | clocks { | ||
| 524 | compatible = "simple-bus"; | ||
| 525 | #address-cells = <1>; | ||
| 526 | #size-cells = <0>; | ||
| 527 | |||
| 528 | clk32k_in: clock { | ||
| 529 | compatible = "fixed-clock"; | ||
| 530 | reg=<0>; | ||
| 531 | #clock-cells = <0>; | ||
| 532 | clock-frequency = <32768>; | ||
| 533 | }; | ||
| 534 | }; | ||
| 535 | |||
| 522 | kbc { | 536 | kbc { |
| 523 | status = "okay"; | 537 | status = "okay"; |
| 524 | nvidia,debounce-delay-ms = <20>; | 538 | nvidia,debounce-delay-ms = <20>; |
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 3d3f64d2111a..fc7febc2b386 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi | |||
| @@ -145,6 +145,7 @@ | |||
| 145 | 0 1 0x04 | 145 | 0 1 0x04 |
| 146 | 0 41 0x04 | 146 | 0 41 0x04 |
| 147 | 0 42 0x04>; | 147 | 0 42 0x04>; |
| 148 | clocks = <&tegra_car 5>; | ||
| 148 | }; | 149 | }; |
| 149 | 150 | ||
| 150 | tegra_car: clock { | 151 | tegra_car: clock { |
| @@ -304,6 +305,7 @@ | |||
| 304 | compatible = "nvidia,tegra20-rtc"; | 305 | compatible = "nvidia,tegra20-rtc"; |
| 305 | reg = <0x7000e000 0x100>; | 306 | reg = <0x7000e000 0x100>; |
| 306 | interrupts = <0 2 0x04>; | 307 | interrupts = <0 2 0x04>; |
| 308 | clocks = <&tegra_car 4>; | ||
| 307 | }; | 309 | }; |
| 308 | 310 | ||
| 309 | i2c@7000c000 { | 311 | i2c@7000c000 { |
| @@ -416,6 +418,8 @@ | |||
| 416 | pmc { | 418 | pmc { |
| 417 | compatible = "nvidia,tegra20-pmc"; | 419 | compatible = "nvidia,tegra20-pmc"; |
| 418 | reg = <0x7000e400 0x400>; | 420 | reg = <0x7000e400 0x400>; |
| 421 | clocks = <&tegra_car 110>, <&clk32k_in>; | ||
| 422 | clock-names = "pclk", "clk32k_in"; | ||
| 419 | }; | 423 | }; |
| 420 | 424 | ||
| 421 | memory-controller@7000f000 { | 425 | memory-controller@7000f000 { |
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 8ff2ff20e4a3..6248b2445b32 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts | |||
| @@ -257,7 +257,7 @@ | |||
| 257 | 257 | ||
| 258 | sdhci@78000000 { | 258 | sdhci@78000000 { |
| 259 | status = "okay"; | 259 | status = "okay"; |
| 260 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | 260 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ |
| 261 | wp-gpios = <&gpio 155 0>; /* gpio PT3 */ | 261 | wp-gpios = <&gpio 155 0>; /* gpio PT3 */ |
| 262 | power-gpios = <&gpio 31 0>; /* gpio PD7 */ | 262 | power-gpios = <&gpio 31 0>; /* gpio PD7 */ |
| 263 | bus-width = <4>; | 263 | bus-width = <4>; |
| @@ -268,6 +268,19 @@ | |||
| 268 | bus-width = <8>; | 268 | bus-width = <8>; |
| 269 | }; | 269 | }; |
| 270 | 270 | ||
| 271 | clocks { | ||
| 272 | compatible = "simple-bus"; | ||
| 273 | #address-cells = <1>; | ||
| 274 | #size-cells = <0>; | ||
| 275 | |||
| 276 | clk32k_in: clock { | ||
| 277 | compatible = "fixed-clock"; | ||
| 278 | reg=<0>; | ||
| 279 | #clock-cells = <0>; | ||
| 280 | clock-frequency = <32768>; | ||
| 281 | }; | ||
| 282 | }; | ||
| 283 | |||
| 271 | regulators { | 284 | regulators { |
| 272 | compatible = "simple-bus"; | 285 | compatible = "simple-bus"; |
| 273 | #address-cells = <1>; | 286 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 17499272a4ef..65bf2b63174e 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi | |||
| @@ -311,7 +311,7 @@ | |||
| 311 | 311 | ||
| 312 | sdhci@78000000 { | 312 | sdhci@78000000 { |
| 313 | status = "okay"; | 313 | status = "okay"; |
| 314 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | 314 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ |
| 315 | wp-gpios = <&gpio 155 0>; /* gpio PT3 */ | 315 | wp-gpios = <&gpio 155 0>; /* gpio PT3 */ |
| 316 | power-gpios = <&gpio 31 0>; /* gpio PD7 */ | 316 | power-gpios = <&gpio 31 0>; /* gpio PD7 */ |
| 317 | bus-width = <4>; | 317 | bus-width = <4>; |
| @@ -322,6 +322,19 @@ | |||
| 322 | bus-width = <8>; | 322 | bus-width = <8>; |
| 323 | }; | 323 | }; |
| 324 | 324 | ||
| 325 | clocks { | ||
| 326 | compatible = "simple-bus"; | ||
| 327 | #address-cells = <1>; | ||
| 328 | #size-cells = <0>; | ||
| 329 | |||
| 330 | clk32k_in: clock { | ||
| 331 | compatible = "fixed-clock"; | ||
| 332 | reg=<0>; | ||
| 333 | #clock-cells = <0>; | ||
| 334 | clock-frequency = <32768>; | ||
| 335 | }; | ||
| 336 | }; | ||
| 337 | |||
| 325 | regulators { | 338 | regulators { |
| 326 | compatible = "simple-bus"; | 339 | compatible = "simple-bus"; |
| 327 | #address-cells = <1>; | 340 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index dbf46c272562..9fe7a92b4c85 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi | |||
| @@ -148,6 +148,7 @@ | |||
| 148 | 0 42 0x04 | 148 | 0 42 0x04 |
| 149 | 0 121 0x04 | 149 | 0 121 0x04 |
| 150 | 0 122 0x04>; | 150 | 0 122 0x04>; |
| 151 | clocks = <&tegra_car 5>; | ||
| 151 | }; | 152 | }; |
| 152 | 153 | ||
| 153 | tegra_car: clock { | 154 | tegra_car: clock { |
| @@ -291,6 +292,7 @@ | |||
| 291 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; | 292 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; |
| 292 | reg = <0x7000e000 0x100>; | 293 | reg = <0x7000e000 0x100>; |
| 293 | interrupts = <0 2 0x04>; | 294 | interrupts = <0 2 0x04>; |
| 295 | clocks = <&tegra_car 4>; | ||
| 294 | }; | 296 | }; |
| 295 | 297 | ||
| 296 | i2c@7000c000 { | 298 | i2c@7000c000 { |
| @@ -423,8 +425,10 @@ | |||
| 423 | }; | 425 | }; |
| 424 | 426 | ||
| 425 | pmc { | 427 | pmc { |
| 426 | compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; | 428 | compatible = "nvidia,tegra30-pmc"; |
| 427 | reg = <0x7000e400 0x400>; | 429 | reg = <0x7000e400 0x400>; |
| 430 | clocks = <&tegra_car 218>, <&clk32k_in>; | ||
| 431 | clock-names = "pclk", "clk32k_in"; | ||
| 428 | }; | 432 | }; |
| 429 | 433 | ||
| 430 | memory-controller { | 434 | memory-controller { |
diff --git a/arch/arm/boot/dts/tps6507x.dtsi b/arch/arm/boot/dts/tps6507x.dtsi new file mode 100644 index 000000000000..4c326e591e5a --- /dev/null +++ b/arch/arm/boot/dts/tps6507x.dtsi | |||
| @@ -0,0 +1,47 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* | ||
| 10 | * Integrated Power Management Chip | ||
| 11 | * http://www.ti.com/lit/ds/symlink/tps65070.pdf | ||
| 12 | */ | ||
| 13 | |||
| 14 | &tps { | ||
| 15 | compatible = "ti,tps6507x"; | ||
| 16 | |||
| 17 | regulators { | ||
| 18 | #address-cells = <1>; | ||
| 19 | #size-cells = <0>; | ||
| 20 | |||
| 21 | vdcdc1_reg: regulator@0 { | ||
| 22 | reg = <0>; | ||
| 23 | regulator-compatible = "VDCDC1"; | ||
| 24 | }; | ||
| 25 | |||
| 26 | vdcdc2_reg: regulator@1 { | ||
| 27 | reg = <1>; | ||
| 28 | regulator-compatible = "VDCDC2"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | vdcdc3_reg: regulator@2 { | ||
| 32 | reg = <2>; | ||
| 33 | regulator-compatible = "VDCDC3"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | ldo1_reg: regulator@3 { | ||
| 37 | reg = <3>; | ||
| 38 | regulator-compatible = "LDO1"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | ldo2_reg: regulator@4 { | ||
| 42 | reg = <4>; | ||
| 43 | regulator-compatible = "LDO2"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | }; | ||
| 47 | }; | ||
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts index 73187173117c..9420053acc14 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | |||
| @@ -117,7 +117,7 @@ | |||
| 117 | }; | 117 | }; |
| 118 | 118 | ||
| 119 | pmu { | 119 | pmu { |
| 120 | compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; | 120 | compatible = "arm,cortex-a15-pmu"; |
| 121 | interrupts = <0 68 4>, | 121 | interrupts = <0 68 4>, |
| 122 | <0 69 4>; | 122 | <0 69 4>; |
| 123 | }; | 123 | }; |
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index dfe371ec2749..d2803be4e1a8 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | |||
| @@ -134,7 +134,7 @@ | |||
| 134 | }; | 134 | }; |
| 135 | 135 | ||
| 136 | pmu { | 136 | pmu { |
| 137 | compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; | 137 | compatible = "arm,cortex-a15-pmu"; |
| 138 | interrupts = <0 68 4>, | 138 | interrupts = <0 68 4>, |
| 139 | <0 69 4>; | 139 | <0 69 4>; |
| 140 | }; | 140 | }; |
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts index 6328cbc71d30..c544a5504591 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts | |||
| @@ -111,7 +111,7 @@ | |||
| 111 | }; | 111 | }; |
| 112 | 112 | ||
| 113 | pmu { | 113 | pmu { |
| 114 | compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu"; | 114 | compatible = "arm,cortex-a5-pmu"; |
| 115 | interrupts = <0 68 4>, | 115 | interrupts = <0 68 4>, |
| 116 | <0 69 4>; | 116 | <0 69 4>; |
| 117 | }; | 117 | }; |
diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts index 567cf4e8ab84..877b33afa7ed 100644 --- a/arch/arm/boot/dts/vt8500-bv07.dts +++ b/arch/arm/boot/dts/vt8500-bv07.dts | |||
| @@ -11,26 +11,22 @@ | |||
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "Benign BV07 Netbook"; | 13 | model = "Benign BV07 Netbook"; |
| 14 | }; | ||
| 14 | 15 | ||
| 15 | /* | 16 | &fb { |
| 16 | * Display node is based on Sascha Hauer's patch on dri-devel. | 17 | bits-per-pixel = <16>; |
| 17 | * Added a bpp property to calculate the size of the framebuffer | 18 | display-timings { |
| 18 | * until the binding is formalized. | 19 | native-mode = <&timing0>; |
| 19 | */ | 20 | timing0: 800x480 { |
| 20 | display: display@0 { | 21 | clock-frequency = <0>; /* unused but required */ |
| 21 | modes { | 22 | hactive = <800>; |
| 22 | mode0: mode@0 { | 23 | vactive = <480>; |
| 23 | hactive = <800>; | 24 | hfront-porch = <40>; |
| 24 | vactive = <480>; | 25 | hback-porch = <88>; |
| 25 | hback-porch = <88>; | 26 | hsync-len = <0>; |
| 26 | hfront-porch = <40>; | 27 | vback-porch = <32>; |
| 27 | hsync-len = <0>; | 28 | vfront-porch = <11>; |
| 28 | vback-porch = <32>; | 29 | vsync-len = <1>; |
| 29 | vfront-porch = <11>; | ||
| 30 | vsync-len = <1>; | ||
| 31 | clock = <0>; /* unused but required */ | ||
| 32 | bpp = <16>; /* non-standard but required */ | ||
| 33 | }; | ||
| 34 | }; | 30 | }; |
| 35 | }; | 31 | }; |
| 36 | }; | 32 | }; |
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi index cf31ced46602..68c8dc644383 100644 --- a/arch/arm/boot/dts/vt8500.dtsi +++ b/arch/arm/boot/dts/vt8500.dtsi | |||
| @@ -98,12 +98,10 @@ | |||
| 98 | interrupts = <43>; | 98 | interrupts = <43>; |
| 99 | }; | 99 | }; |
| 100 | 100 | ||
| 101 | fb@d800e400 { | 101 | fb: fb@d8050800 { |
| 102 | compatible = "via,vt8500-fb"; | 102 | compatible = "via,vt8500-fb"; |
| 103 | reg = <0xd800e400 0x400>; | 103 | reg = <0xd800e400 0x400>; |
| 104 | interrupts = <12>; | 104 | interrupts = <12>; |
| 105 | display = <&display>; | ||
| 106 | default-mode = <&mode0>; | ||
| 107 | }; | 105 | }; |
| 108 | 106 | ||
| 109 | ge_rops@d8050400 { | 107 | ge_rops@d8050400 { |
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts index fd4e248074c6..edd2cec3d37f 100644 --- a/arch/arm/boot/dts/wm8505-ref.dts +++ b/arch/arm/boot/dts/wm8505-ref.dts | |||
| @@ -11,26 +11,22 @@ | |||
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "Wondermedia WM8505 Netbook"; | 13 | model = "Wondermedia WM8505 Netbook"; |
| 14 | }; | ||
| 14 | 15 | ||
| 15 | /* | 16 | &fb { |
| 16 | * Display node is based on Sascha Hauer's patch on dri-devel. | 17 | bits-per-pixel = <32>; |
| 17 | * Added a bpp property to calculate the size of the framebuffer | 18 | display-timings { |
| 18 | * until the binding is formalized. | 19 | native-mode = <&timing0>; |
| 19 | */ | 20 | timing0: 800x480 { |
| 20 | display: display@0 { | 21 | clock-frequency = <0>; /* unused but required */ |
| 21 | modes { | 22 | hactive = <800>; |
| 22 | mode0: mode@0 { | 23 | vactive = <480>; |
| 23 | hactive = <800>; | 24 | hfront-porch = <40>; |
| 24 | vactive = <480>; | 25 | hback-porch = <88>; |
| 25 | hback-porch = <88>; | 26 | hsync-len = <0>; |
| 26 | hfront-porch = <40>; | 27 | vback-porch = <32>; |
| 27 | hsync-len = <0>; | 28 | vfront-porch = <11>; |
| 28 | vback-porch = <32>; | 29 | vsync-len = <1>; |
| 29 | vfront-porch = <11>; | ||
| 30 | vsync-len = <1>; | ||
| 31 | clock = <0>; /* unused but required */ | ||
| 32 | bpp = <32>; /* non-standard but required */ | ||
| 33 | }; | ||
| 34 | }; | 30 | }; |
| 35 | }; | 31 | }; |
| 36 | }; | 32 | }; |
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index e74a1c0fb9a2..398b8bca791e 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi | |||
| @@ -60,6 +60,19 @@ | |||
| 60 | clock-frequency = <24000000>; | 60 | clock-frequency = <24000000>; |
| 61 | }; | 61 | }; |
| 62 | 62 | ||
| 63 | ref25: ref25M { | ||
| 64 | #clock-cells = <0>; | ||
| 65 | compatible = "fixed-clock"; | ||
| 66 | clock-frequency = <25000000>; | ||
| 67 | }; | ||
| 68 | |||
| 69 | pllb: pllb { | ||
| 70 | #clock-cells = <0>; | ||
| 71 | compatible = "via,vt8500-pll-clock"; | ||
| 72 | clocks = <&ref25>; | ||
| 73 | reg = <0x204>; | ||
| 74 | }; | ||
| 75 | |||
| 63 | clkuart0: uart0 { | 76 | clkuart0: uart0 { |
| 64 | #clock-cells = <0>; | 77 | #clock-cells = <0>; |
| 65 | compatible = "via,vt8500-device-clock"; | 78 | compatible = "via,vt8500-device-clock"; |
| @@ -107,6 +120,16 @@ | |||
| 107 | enable-reg = <0x250>; | 120 | enable-reg = <0x250>; |
| 108 | enable-bit = <23>; | 121 | enable-bit = <23>; |
| 109 | }; | 122 | }; |
| 123 | |||
| 124 | clksdhc: sdhc { | ||
| 125 | #clock-cells = <0>; | ||
| 126 | compatible = "via,vt8500-device-clock"; | ||
| 127 | clocks = <&pllb>; | ||
| 128 | divisor-reg = <0x328>; | ||
| 129 | divisor-mask = <0x3f>; | ||
| 130 | enable-reg = <0x254>; | ||
| 131 | enable-bit = <18>; | ||
| 132 | }; | ||
| 110 | }; | 133 | }; |
| 111 | }; | 134 | }; |
| 112 | 135 | ||
| @@ -128,11 +151,9 @@ | |||
| 128 | interrupts = <0>; | 151 | interrupts = <0>; |
| 129 | }; | 152 | }; |
| 130 | 153 | ||
| 131 | fb@d8050800 { | 154 | fb: fb@d8050800 { |
| 132 | compatible = "wm,wm8505-fb"; | 155 | compatible = "wm,wm8505-fb"; |
| 133 | reg = <0xd8050800 0x200>; | 156 | reg = <0xd8050800 0x200>; |
| 134 | display = <&display>; | ||
| 135 | default-mode = <&mode0>; | ||
| 136 | }; | 157 | }; |
| 137 | 158 | ||
| 138 | ge_rops@d8050400 { | 159 | ge_rops@d8050400 { |
| @@ -187,5 +208,13 @@ | |||
| 187 | reg = <0xd8100000 0x10000>; | 208 | reg = <0xd8100000 0x10000>; |
| 188 | interrupts = <48>; | 209 | interrupts = <48>; |
| 189 | }; | 210 | }; |
| 211 | |||
| 212 | sdhc@d800a000 { | ||
| 213 | compatible = "wm,wm8505-sdhc"; | ||
| 214 | reg = <0xd800a000 0x1000>; | ||
| 215 | interrupts = <20 21>; | ||
| 216 | clocks = <&clksdhc>; | ||
| 217 | bus-width = <4>; | ||
| 218 | }; | ||
| 190 | }; | 219 | }; |
| 191 | }; | 220 | }; |
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts index cefd938f842f..61671a0d9ede 100644 --- a/arch/arm/boot/dts/wm8650-mid.dts +++ b/arch/arm/boot/dts/wm8650-mid.dts | |||
| @@ -11,26 +11,24 @@ | |||
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "Wondermedia WM8650-MID Tablet"; | 13 | model = "Wondermedia WM8650-MID Tablet"; |
| 14 | }; | ||
| 15 | |||
| 16 | &fb { | ||
| 17 | bits-per-pixel = <16>; | ||
| 14 | 18 | ||
| 15 | /* | 19 | display-timings { |
| 16 | * Display node is based on Sascha Hauer's patch on dri-devel. | 20 | native-mode = <&timing0>; |
| 17 | * Added a bpp property to calculate the size of the framebuffer | 21 | timing0: 800x480 { |
| 18 | * until the binding is formalized. | 22 | clock-frequency = <0>; /* unused but required */ |
| 19 | */ | 23 | hactive = <800>; |
| 20 | display: display@0 { | 24 | vactive = <480>; |
| 21 | modes { | 25 | hfront-porch = <40>; |
| 22 | mode0: mode@0 { | 26 | hback-porch = <88>; |
| 23 | hactive = <800>; | 27 | hsync-len = <0>; |
| 24 | vactive = <480>; | 28 | vback-porch = <32>; |
| 25 | hback-porch = <88>; | 29 | vfront-porch = <11>; |
| 26 | hfront-porch = <40>; | 30 | vsync-len = <1>; |
| 27 | hsync-len = <0>; | ||
| 28 | vback-porch = <32>; | ||
| 29 | vfront-porch = <11>; | ||
| 30 | vsync-len = <1>; | ||
| 31 | clock = <0>; /* unused but required */ | ||
| 32 | bpp = <16>; /* non-standard but required */ | ||
| 33 | }; | ||
| 34 | }; | 31 | }; |
| 35 | }; | 32 | }; |
| 36 | }; | 33 | }; |
| 34 | |||
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi index db3c0a12e052..9313407bbc30 100644 --- a/arch/arm/boot/dts/wm8650.dtsi +++ b/arch/arm/boot/dts/wm8650.dtsi | |||
| @@ -128,11 +128,9 @@ | |||
| 128 | interrupts = <43>; | 128 | interrupts = <43>; |
| 129 | }; | 129 | }; |
| 130 | 130 | ||
| 131 | fb@d8050800 { | 131 | fb: fb@d8050800 { |
| 132 | compatible = "wm,wm8505-fb"; | 132 | compatible = "wm,wm8505-fb"; |
| 133 | reg = <0xd8050800 0x200>; | 133 | reg = <0xd8050800 0x200>; |
| 134 | display = <&display>; | ||
| 135 | default-mode = <&mode0>; | ||
| 136 | }; | 134 | }; |
| 137 | 135 | ||
| 138 | ge_rops@d8050400 { | 136 | ge_rops@d8050400 { |
diff --git a/arch/arm/boot/dts/wm8850-w70v2.dts b/arch/arm/boot/dts/wm8850-w70v2.dts index fcc660c89540..32d22532cd6c 100644 --- a/arch/arm/boot/dts/wm8850-w70v2.dts +++ b/arch/arm/boot/dts/wm8850-w70v2.dts | |||
| @@ -15,28 +15,6 @@ | |||
| 15 | / { | 15 | / { |
| 16 | model = "Wondermedia WM8850-W70v2 Tablet"; | 16 | model = "Wondermedia WM8850-W70v2 Tablet"; |
| 17 | 17 | ||
| 18 | /* | ||
| 19 | * Display node is based on Sascha Hauer's patch on dri-devel. | ||
| 20 | * Added a bpp property to calculate the size of the framebuffer | ||
| 21 | * until the binding is formalized. | ||
| 22 | */ | ||
| 23 | display: display@0 { | ||
| 24 | modes { | ||
| 25 | mode0: mode@0 { | ||
| 26 | hactive = <800>; | ||
| 27 | vactive = <480>; | ||
| 28 | hback-porch = <88>; | ||
| 29 | hfront-porch = <40>; | ||
| 30 | hsync-len = <0>; | ||
| 31 | vback-porch = <32>; | ||
| 32 | vfront-porch = <11>; | ||
| 33 | vsync-len = <1>; | ||
| 34 | clock = <0>; /* unused but required */ | ||
| 35 | bpp = <16>; /* non-standard but required */ | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | |||
| 40 | backlight { | 18 | backlight { |
| 41 | compatible = "pwm-backlight"; | 19 | compatible = "pwm-backlight"; |
| 42 | pwms = <&pwm 0 50000 1>; /* duty inverted */ | 20 | pwms = <&pwm 0 50000 1>; /* duty inverted */ |
| @@ -45,3 +23,21 @@ | |||
| 45 | default-brightness-level = <5>; | 23 | default-brightness-level = <5>; |
| 46 | }; | 24 | }; |
| 47 | }; | 25 | }; |
| 26 | |||
| 27 | &fb { | ||
| 28 | bits-per-pixel = <16>; | ||
| 29 | display-timings { | ||
| 30 | native-mode = <&timing0>; | ||
| 31 | timing0: 800x480 { | ||
| 32 | clock-frequency = <0>; /* unused but required */ | ||
| 33 | hactive = <800>; | ||
| 34 | vactive = <480>; | ||
| 35 | hfront-porch = <40>; | ||
| 36 | hback-porch = <88>; | ||
| 37 | hsync-len = <0>; | ||
| 38 | vback-porch = <32>; | ||
| 39 | vfront-porch = <11>; | ||
| 40 | vsync-len = <1>; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | }; | ||
diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi index e8cbfdc87bba..7149cd13e3b9 100644 --- a/arch/arm/boot/dts/wm8850.dtsi +++ b/arch/arm/boot/dts/wm8850.dtsi | |||
| @@ -135,11 +135,9 @@ | |||
| 135 | }; | 135 | }; |
| 136 | }; | 136 | }; |
| 137 | 137 | ||
| 138 | fb@d8051700 { | 138 | fb: fb@d8051700 { |
| 139 | compatible = "wm,wm8505-fb"; | 139 | compatible = "wm,wm8505-fb"; |
| 140 | reg = <0xd8051700 0x200>; | 140 | reg = <0xd8051700 0x200>; |
| 141 | display = <&display>; | ||
| 142 | default-mode = <&mode0>; | ||
| 143 | }; | 141 | }; |
| 144 | 142 | ||
| 145 | ge_rops@d8050400 { | 143 | ge_rops@d8050400 { |
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 5914b5654591..9e1c339c4491 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi | |||
| @@ -15,6 +15,13 @@ | |||
| 15 | / { | 15 | / { |
| 16 | compatible = "xlnx,zynq-7000"; | 16 | compatible = "xlnx,zynq-7000"; |
| 17 | 17 | ||
| 18 | pmu { | ||
| 19 | compatible = "arm,cortex-a9-pmu"; | ||
| 20 | interrupts = <0 5 4>, <0 6 4>; | ||
| 21 | interrupt-parent = <&intc>; | ||
| 22 | reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; | ||
| 23 | }; | ||
| 24 | |||
| 18 | amba { | 25 | amba { |
| 19 | compatible = "simple-bus"; | 26 | compatible = "simple-bus"; |
| 20 | #address-cells = <1>; | 27 | #address-cells = <1>; |