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-rw-r--r--arch/arm/boot/dts/am4372.dtsi11
-rw-r--r--arch/arm/boot/dts/am437x-gp-evm.dts1
-rw-r--r--arch/arm/boot/dts/am437x-sk-evm.dts1
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts1
-rw-r--r--arch/arm/boot/dts/dra7.dtsi12
-rw-r--r--arch/arm/boot/dts/dra72x.dtsi2
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi2
-rw-r--r--arch/arm/boot/dts/omap4-duovero.dtsi2
-rw-r--r--arch/arm/boot/dts/omap4-panda-common.dtsi8
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts8
-rw-r--r--arch/arm/boot/dts/omap4-var-som-om44.dtsi2
-rw-r--r--arch/arm/boot/dts/omap4.dtsi18
-rw-r--r--arch/arm/boot/dts/omap5-cm-t54.dts1
-rw-r--r--arch/arm/boot/dts/omap5-uevm.dts2
-rw-r--r--arch/arm/boot/dts/omap5.dtsi26
15 files changed, 59 insertions, 38 deletions
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 1943fc333e7c..8a099bc10c1e 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -15,7 +15,7 @@
15 15
16/ { 16/ {
17 compatible = "ti,am4372", "ti,am43"; 17 compatible = "ti,am4372", "ti,am43";
18 interrupt-parent = <&gic>; 18 interrupt-parent = <&wakeupgen>;
19 19
20 20
21 aliases { 21 aliases {
@@ -48,6 +48,15 @@
48 #interrupt-cells = <3>; 48 #interrupt-cells = <3>;
49 reg = <0x48241000 0x1000>, 49 reg = <0x48241000 0x1000>,
50 <0x48240100 0x0100>; 50 <0x48240100 0x0100>;
51 interrupt-parent = <&gic>;
52 };
53
54 wakeupgen: interrupt-controller@48281000 {
55 compatible = "ti,omap4-wugen-mpu";
56 interrupt-controller;
57 #interrupt-cells = <3>;
58 reg = <0x48281000 0x1000>;
59 interrupt-parent = <&gic>;
51 }; 60 };
52 61
53 l2-cache-controller@48242000 { 62 l2-cache-controller@48242000 {
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index f84d9715a4a9..26956cb50835 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -352,7 +352,6 @@
352 reg = <0x24>; 352 reg = <0x24>;
353 compatible = "ti,tps65218"; 353 compatible = "ti,tps65218";
354 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ 354 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
355 interrupt-parent = <&gic>;
356 interrupt-controller; 355 interrupt-controller;
357 #interrupt-cells = <2>; 356 #interrupt-cells = <2>;
358 357
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index 832d24318f62..8ae29c955c11 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -392,7 +392,6 @@
392 tps@24 { 392 tps@24 {
393 compatible = "ti,tps65218"; 393 compatible = "ti,tps65218";
394 reg = <0x24>; 394 reg = <0x24>;
395 interrupt-parent = <&gic>;
396 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 395 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
397 interrupt-controller; 396 interrupt-controller;
398 #interrupt-cells = <2>; 397 #interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 257c099c347e..1d7109196872 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -369,7 +369,6 @@
369 reg = <0x24>; 369 reg = <0x24>;
370 compatible = "ti,tps65218"; 370 compatible = "ti,tps65218";
371 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ 371 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
372 interrupt-parent = <&gic>;
373 interrupt-controller; 372 interrupt-controller;
374 #interrupt-cells = <2>; 373 #interrupt-cells = <2>;
375 374
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 850f949d409a..c65eea095afa 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -64,6 +64,14 @@
64 interrupt-parent = <&gic>; 64 interrupt-parent = <&gic>;
65 }; 65 };
66 66
67 wakeupgen: interrupt-controller@48281000 {
68 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
69 interrupt-controller;
70 #interrupt-cells = <3>;
71 reg = <0x48281000 0x1000>;
72 interrupt-parent = <&gic>;
73 };
74
67 /* 75 /*
68 * The soc node represents the soc top level view. It is used for IPs 76 * The soc node represents the soc top level view. It is used for IPs
69 * that are not memory mapped in the MPU view or for the MPU itself. 77 * that are not memory mapped in the MPU view or for the MPU itself.
@@ -92,7 +100,7 @@
92 reg = <0x44000000 0x1000000>, 100 reg = <0x44000000 0x1000000>,
93 <0x45000000 0x1000>; 101 <0x45000000 0x1000>;
94 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 102 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
95 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 103 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
96 104
97 prm: prm@4ae06000 { 105 prm: prm@4ae06000 {
98 compatible = "ti,dra7-prm"; 106 compatible = "ti,dra7-prm";
@@ -1341,7 +1349,7 @@
1341 compatible = "ti,irq-crossbar"; 1349 compatible = "ti,irq-crossbar";
1342 reg = <0x4a002a48 0x130>; 1350 reg = <0x4a002a48 0x130>;
1343 interrupt-controller; 1351 interrupt-controller;
1344 interrupt-parent = <&gic>; 1352 interrupt-parent = <&wakeupgen>;
1345 #interrupt-cells = <3>; 1353 #interrupt-cells = <3>;
1346 ti,max-irqs = <160>; 1354 ti,max-irqs = <160>;
1347 ti,max-crossbar-sources = <MAX_SOURCES>; 1355 ti,max-crossbar-sources = <MAX_SOURCES>;
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index e782bf1dd863..f7fb0d0ef25a 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -25,7 +25,7 @@
25 25
26 pmu { 26 pmu {
27 compatible = "arm,cortex-a15-pmu"; 27 compatible = "arm,cortex-a15-pmu";
28 interrupt-parent = <&gic>; 28 interrupt-parent = <&wakeupgen>;
29 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 29 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
30 }; 30 };
31}; 31};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 0fc758db55f5..00eeed789b4b 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -41,7 +41,7 @@
41 41
42 pmu { 42 pmu {
43 compatible = "arm,cortex-a15-pmu"; 43 compatible = "arm,cortex-a15-pmu";
44 interrupt-parent = <&gic>; 44 interrupt-parent = <&wakeupgen>;
45 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 45 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 46 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
47 }; 47 };
diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi
index e860ccd9d09c..f2a94fa62552 100644
--- a/arch/arm/boot/dts/omap4-duovero.dtsi
+++ b/arch/arm/boot/dts/omap4-duovero.dtsi
@@ -173,14 +173,12 @@
173 twl: twl@48 { 173 twl: twl@48 {
174 reg = <0x48>; 174 reg = <0x48>;
175 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ 175 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
176 interrupt-parent = <&gic>;
177 }; 176 };
178 177
179 twl6040: twl@4b { 178 twl6040: twl@4b {
180 compatible = "ti,twl6040"; 179 compatible = "ti,twl6040";
181 reg = <0x4b>; 180 reg = <0x4b>;
182 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ 181 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
183 interrupt-parent = <&gic>;
184 ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* gpio_160 */ 182 ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* gpio_160 */
185 183
186 vio-supply = <&v1v8>; 184 vio-supply = <&v1v8>;
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 150513506c19..7c15fb2e2fe4 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -372,7 +372,6 @@
372 reg = <0x48>; 372 reg = <0x48>;
373 /* IRQ# = 7 */ 373 /* IRQ# = 7 */
374 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ 374 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
375 interrupt-parent = <&gic>;
376 }; 375 };
377 376
378 twl6040: twl@4b { 377 twl6040: twl@4b {
@@ -384,7 +383,6 @@
384 383
385 /* IRQ# = 119 */ 384 /* IRQ# = 119 */
386 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ 385 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
387 interrupt-parent = <&gic>;
388 ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */ 386 ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */
389 387
390 vio-supply = <&v1v8>; 388 vio-supply = <&v1v8>;
@@ -479,17 +477,17 @@
479}; 477};
480 478
481&uart2 { 479&uart2 {
482 interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 480 interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
483 &omap4_pmx_core OMAP4_UART2_RX>; 481 &omap4_pmx_core OMAP4_UART2_RX>;
484}; 482};
485 483
486&uart3 { 484&uart3 {
487 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH 485 interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
488 &omap4_pmx_core OMAP4_UART3_RX>; 486 &omap4_pmx_core OMAP4_UART3_RX>;
489}; 487};
490 488
491&uart4 { 489&uart4 {
492 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 490 interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
493 &omap4_pmx_core OMAP4_UART4_RX>; 491 &omap4_pmx_core OMAP4_UART4_RX>;
494}; 492};
495 493
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 3e1da43068f6..8aca8dae968a 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -363,7 +363,6 @@
363 reg = <0x48>; 363 reg = <0x48>;
364 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ 364 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
365 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ 365 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
366 interrupt-parent = <&gic>;
367 }; 366 };
368 367
369 twl6040: twl@4b { 368 twl6040: twl@4b {
@@ -375,7 +374,6 @@
375 374
376 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ 375 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
377 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ 376 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
378 interrupt-parent = <&gic>;
379 ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */ 377 ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */
380 378
381 vio-supply = <&v1v8>; 379 vio-supply = <&v1v8>;
@@ -570,21 +568,21 @@
570}; 568};
571 569
572&uart2 { 570&uart2 {
573 interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 571 interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
574 &omap4_pmx_core OMAP4_UART2_RX>; 572 &omap4_pmx_core OMAP4_UART2_RX>;
575 pinctrl-names = "default"; 573 pinctrl-names = "default";
576 pinctrl-0 = <&uart2_pins>; 574 pinctrl-0 = <&uart2_pins>;
577}; 575};
578 576
579&uart3 { 577&uart3 {
580 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH 578 interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
581 &omap4_pmx_core OMAP4_UART3_RX>; 579 &omap4_pmx_core OMAP4_UART3_RX>;
582 pinctrl-names = "default"; 580 pinctrl-names = "default";
583 pinctrl-0 = <&uart3_pins>; 581 pinctrl-0 = <&uart3_pins>;
584}; 582};
585 583
586&uart4 { 584&uart4 {
587 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 585 interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
588 &omap4_pmx_core OMAP4_UART4_RX>; 586 &omap4_pmx_core OMAP4_UART4_RX>;
589 pinctrl-names = "default"; 587 pinctrl-names = "default";
590 pinctrl-0 = <&uart4_pins>; 588 pinctrl-0 = <&uart4_pins>;
diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi
index 062701e1a898..a4f1ba2e1903 100644
--- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi
+++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi
@@ -185,7 +185,6 @@
185 reg = <0x48>; 185 reg = <0x48>;
186 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ 186 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
187 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ 187 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
188 interrupt-parent = <&gic>;
189 }; 188 };
190 189
191 twl6040: twl@4b { 190 twl6040: twl@4b {
@@ -197,7 +196,6 @@
197 196
198 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ 197 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
199 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ 198 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
200 interrupt-parent = <&gic>;
201 ti,audpwron-gpio = <&gpio6 22 0>; /* gpio 182 */ 199 ti,audpwron-gpio = <&gpio6 22 0>; /* gpio 182 */
202 200
203 vio-supply = <&v1v8>; 201 vio-supply = <&v1v8>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 074147cebae4..7cb5236f751d 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -14,7 +14,7 @@
14 14
15/ { 15/ {
16 compatible = "ti,omap4430", "ti,omap4"; 16 compatible = "ti,omap4430", "ti,omap4";
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&wakeupgen>;
18 18
19 aliases { 19 aliases {
20 i2c0 = &i2c1; 20 i2c0 = &i2c1;
@@ -56,6 +56,7 @@
56 #interrupt-cells = <3>; 56 #interrupt-cells = <3>;
57 reg = <0x48241000 0x1000>, 57 reg = <0x48241000 0x1000>,
58 <0x48240100 0x0100>; 58 <0x48240100 0x0100>;
59 interrupt-parent = <&gic>;
59 }; 60 };
60 61
61 L2: l2-cache-controller@48242000 { 62 L2: l2-cache-controller@48242000 {
@@ -70,6 +71,15 @@
70 clocks = <&mpu_periphclk>; 71 clocks = <&mpu_periphclk>;
71 reg = <0x48240600 0x20>; 72 reg = <0x48240600 0x20>;
72 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; 73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
74 interrupt-parent = <&gic>;
75 };
76
77 wakeupgen: interrupt-controller@48281000 {
78 compatible = "ti,omap4-wugen-mpu";
79 interrupt-controller;
80 #interrupt-cells = <3>;
81 reg = <0x48281000 0x1000>;
82 interrupt-parent = <&gic>;
73 }; 83 };
74 84
75 /* 85 /*
@@ -319,7 +329,7 @@
319 uart2: serial@4806c000 { 329 uart2: serial@4806c000 {
320 compatible = "ti,omap4-uart"; 330 compatible = "ti,omap4-uart";
321 reg = <0x4806c000 0x100>; 331 reg = <0x4806c000 0x100>;
322 interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 332 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
323 ti,hwmods = "uart2"; 333 ti,hwmods = "uart2";
324 clock-frequency = <48000000>; 334 clock-frequency = <48000000>;
325 }; 335 };
@@ -327,7 +337,7 @@
327 uart3: serial@48020000 { 337 uart3: serial@48020000 {
328 compatible = "ti,omap4-uart"; 338 compatible = "ti,omap4-uart";
329 reg = <0x48020000 0x100>; 339 reg = <0x48020000 0x100>;
330 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 340 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
331 ti,hwmods = "uart3"; 341 ti,hwmods = "uart3";
332 clock-frequency = <48000000>; 342 clock-frequency = <48000000>;
333 }; 343 };
@@ -335,7 +345,7 @@
335 uart4: serial@4806e000 { 345 uart4: serial@4806e000 {
336 compatible = "ti,omap4-uart"; 346 compatible = "ti,omap4-uart";
337 reg = <0x4806e000 0x100>; 347 reg = <0x4806e000 0x100>;
338 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 348 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
339 ti,hwmods = "uart4"; 349 ti,hwmods = "uart4";
340 clock-frequency = <48000000>; 350 clock-frequency = <48000000>;
341 }; 351 };
diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts
index b54b271e153b..61ad2ea34720 100644
--- a/arch/arm/boot/dts/omap5-cm-t54.dts
+++ b/arch/arm/boot/dts/omap5-cm-t54.dts
@@ -412,7 +412,6 @@
412 palmas: palmas@48 { 412 palmas: palmas@48 {
413 compatible = "ti,palmas"; 413 compatible = "ti,palmas";
414 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ 414 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
415 interrupt-parent = <&gic>;
416 reg = <0x48>; 415 reg = <0x48>;
417 interrupt-controller; 416 interrupt-controller;
418 #interrupt-cells = <2>; 417 #interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 159720d6c956..74777a6e200a 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -311,7 +311,6 @@
311 palmas: palmas@48 { 311 palmas: palmas@48 {
312 compatible = "ti,palmas"; 312 compatible = "ti,palmas";
313 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ 313 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
314 interrupt-parent = <&gic>;
315 reg = <0x48>; 314 reg = <0x48>;
316 interrupt-controller; 315 interrupt-controller;
317 #interrupt-cells = <2>; 316 #interrupt-cells = <2>;
@@ -521,7 +520,6 @@
521 pinctrl-0 = <&twl6040_pins>; 520 pinctrl-0 = <&twl6040_pins>;
522 521
523 interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */ 522 interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
524 interrupt-parent = <&gic>;
525 ti,audpwron-gpio = <&gpio5 13 0>; /* gpio line 141 */ 523 ti,audpwron-gpio = <&gpio5 13 0>; /* gpio line 141 */
526 524
527 vio-supply = <&smps7_reg>; 525 vio-supply = <&smps7_reg>;
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index b321fdf42c9f..b056156e2a7a 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -18,7 +18,7 @@
18 #size-cells = <1>; 18 #size-cells = <1>;
19 19
20 compatible = "ti,omap5"; 20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>; 21 interrupt-parent = <&wakeupgen>;
22 22
23 aliases { 23 aliases {
24 i2c0 = &i2c1; 24 i2c0 = &i2c1;
@@ -79,6 +79,7 @@
79 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, 79 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, 80 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; 81 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
82 interrupt-parent = <&gic>;
82 }; 83 };
83 84
84 pmu { 85 pmu {
@@ -95,6 +96,15 @@
95 <0x48212000 0x1000>, 96 <0x48212000 0x1000>,
96 <0x48214000 0x2000>, 97 <0x48214000 0x2000>,
97 <0x48216000 0x2000>; 98 <0x48216000 0x2000>;
99 interrupt-parent = <&gic>;
100 };
101
102 wakeupgen: interrupt-controller@48281000 {
103 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
104 interrupt-controller;
105 #interrupt-cells = <3>;
106 reg = <0x48281000 0x1000>;
107 interrupt-parent = <&gic>;
98 }; 108 };
99 109
100 /* 110 /*
@@ -458,7 +468,7 @@
458 uart1: serial@4806a000 { 468 uart1: serial@4806a000 {
459 compatible = "ti,omap4-uart"; 469 compatible = "ti,omap4-uart";
460 reg = <0x4806a000 0x100>; 470 reg = <0x4806a000 0x100>;
461 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 471 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
462 ti,hwmods = "uart1"; 472 ti,hwmods = "uart1";
463 clock-frequency = <48000000>; 473 clock-frequency = <48000000>;
464 }; 474 };
@@ -466,7 +476,7 @@
466 uart2: serial@4806c000 { 476 uart2: serial@4806c000 {
467 compatible = "ti,omap4-uart"; 477 compatible = "ti,omap4-uart";
468 reg = <0x4806c000 0x100>; 478 reg = <0x4806c000 0x100>;
469 interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 479 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
470 ti,hwmods = "uart2"; 480 ti,hwmods = "uart2";
471 clock-frequency = <48000000>; 481 clock-frequency = <48000000>;
472 }; 482 };
@@ -474,7 +484,7 @@
474 uart3: serial@48020000 { 484 uart3: serial@48020000 {
475 compatible = "ti,omap4-uart"; 485 compatible = "ti,omap4-uart";
476 reg = <0x48020000 0x100>; 486 reg = <0x48020000 0x100>;
477 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 487 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
478 ti,hwmods = "uart3"; 488 ti,hwmods = "uart3";
479 clock-frequency = <48000000>; 489 clock-frequency = <48000000>;
480 }; 490 };
@@ -482,7 +492,7 @@
482 uart4: serial@4806e000 { 492 uart4: serial@4806e000 {
483 compatible = "ti,omap4-uart"; 493 compatible = "ti,omap4-uart";
484 reg = <0x4806e000 0x100>; 494 reg = <0x4806e000 0x100>;
485 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 495 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
486 ti,hwmods = "uart4"; 496 ti,hwmods = "uart4";
487 clock-frequency = <48000000>; 497 clock-frequency = <48000000>;
488 }; 498 };
@@ -490,7 +500,7 @@
490 uart5: serial@48066000 { 500 uart5: serial@48066000 {
491 compatible = "ti,omap4-uart"; 501 compatible = "ti,omap4-uart";
492 reg = <0x48066000 0x100>; 502 reg = <0x48066000 0x100>;
493 interrupts-extended = <&gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 503 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
494 ti,hwmods = "uart5"; 504 ti,hwmods = "uart5";
495 clock-frequency = <48000000>; 505 clock-frequency = <48000000>;
496 }; 506 };
@@ -498,7 +508,7 @@
498 uart6: serial@48068000 { 508 uart6: serial@48068000 {
499 compatible = "ti,omap4-uart"; 509 compatible = "ti,omap4-uart";
500 reg = <0x48068000 0x100>; 510 reg = <0x48068000 0x100>;
501 interrupts-extended = <&gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 511 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
502 ti,hwmods = "uart6"; 512 ti,hwmods = "uart6";
503 clock-frequency = <48000000>; 513 clock-frequency = <48000000>;
504 }; 514 };
@@ -883,14 +893,12 @@
883 usbhsohci: ohci@4a064800 { 893 usbhsohci: ohci@4a064800 {
884 compatible = "ti,ohci-omap3"; 894 compatible = "ti,ohci-omap3";
885 reg = <0x4a064800 0x400>; 895 reg = <0x4a064800 0x400>;
886 interrupt-parent = <&gic>;
887 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 896 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
888 }; 897 };
889 898
890 usbhsehci: ehci@4a064c00 { 899 usbhsehci: ehci@4a064c00 {
891 compatible = "ti,ehci-omap"; 900 compatible = "ti,ehci-omap";
892 reg = <0x4a064c00 0x400>; 901 reg = <0x4a064c00 0x400>;
893 interrupt-parent = <&gic>;
894 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 902 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
895 }; 903 };
896 }; 904 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-17 20:51:33 -0400