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-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi273
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi220
-rw-r--r--arch/arm/boot/dts/at91sam9263ek.dts156
-rw-r--r--arch/arm/boot/dts/at91sam9g20.dtsi222
-rw-r--r--arch/arm/boot/dts/at91sam9g20ek.dts29
-rw-r--r--arch/arm/boot/dts/at91sam9g20ek_2mmc.dts29
-rw-r--r--arch/arm/boot/dts/at91sam9g20ek_common.dtsi142
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi37
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi221
-rw-r--r--arch/arm/boot/dts/at91sam9n12ek.dts84
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi38
-rw-r--r--arch/arm/boot/dts/db8500.dtsi63
-rw-r--r--arch/arm/boot/dts/emev2-kzm9d.dts26
-rw-r--r--arch/arm/boot/dts/emev2.dtsi63
-rw-r--r--arch/arm/boot/dts/ethernut5.dts84
-rw-r--r--arch/arm/boot/dts/imx23-evk.dts43
-rw-r--r--arch/arm/boot/dts/imx23.dtsi295
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore.dts8
-rw-r--r--arch/arm/boot/dts/imx27.dtsi14
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts114
-rw-r--r--arch/arm/boot/dts/imx28.dtsi497
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts40
-rw-r--r--arch/arm/boot/dts/imx51.dtsi41
-rw-r--r--arch/arm/boot/dts/imx53-ard.dts6
-rw-r--r--arch/arm/boot/dts/imx53-evk.dts8
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts121
-rw-r--r--arch/arm/boot/dts/imx53-smd.dts16
-rw-r--r--arch/arm/boot/dts/imx53.dtsi45
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts15
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts50
-rw-r--r--arch/arm/boot/dts/imx6q-sabresd.dts53
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi171
-rw-r--r--arch/arm/boot/dts/kirkwood-dns320.dts64
-rw-r--r--arch/arm/boot/dts/kirkwood-dns325.dts59
-rw-r--r--arch/arm/boot/dts/kirkwood-ib62x0.dts44
-rw-r--r--arch/arm/boot/dts/kirkwood-iconnect.dts26
-rw-r--r--arch/arm/boot/dts/kirkwood.dtsi15
-rw-r--r--arch/arm/boot/dts/kizbox.dts138
-rw-r--r--arch/arm/boot/dts/lpc32xx.dtsi292
-rw-r--r--arch/arm/boot/dts/mmp2-brownstone.dts38
-rw-r--r--arch/arm/boot/dts/mmp2.dtsi220
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts49
-rw-r--r--arch/arm/boot/dts/omap3.dtsi102
-rw-r--r--arch/arm/boot/dts/omap4-panda.dts71
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts140
-rw-r--r--arch/arm/boot/dts/omap4.dtsi117
-rw-r--r--arch/arm/boot/dts/phy3250.dts145
-rw-r--r--arch/arm/boot/dts/pxa168.dtsi67
-rw-r--r--arch/arm/boot/dts/pxa910-dkb.dts38
-rw-r--r--arch/arm/boot/dts/pxa910.dtsi140
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva.dts22
-rw-r--r--arch/arm/boot/dts/sh7372.dtsi21
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g.dts22
-rw-r--r--arch/arm/boot/dts/snowball.dts40
-rw-r--r--arch/arm/boot/dts/tegra-cardhu.dts152
-rw-r--r--arch/arm/boot/dts/tegra-harmony.dts320
-rw-r--r--arch/arm/boot/dts/tegra-paz00.dts328
-rw-r--r--arch/arm/boot/dts/tegra-seaboard.dts452
-rw-r--r--arch/arm/boot/dts/tegra-trimslice.dts307
-rw-r--r--arch/arm/boot/dts/tegra-ventana.dts324
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi275
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi305
-rw-r--r--arch/arm/boot/dts/tny_a9260.dts15
-rw-r--r--arch/arm/boot/dts/tny_a9260_common.dtsi83
-rw-r--r--arch/arm/boot/dts/tny_a9263.dts97
-rw-r--r--arch/arm/boot/dts/tny_a9g20.dts15
-rw-r--r--arch/arm/boot/dts/twl4030.dtsi47
-rw-r--r--arch/arm/boot/dts/twl6030.dtsi86
-rw-r--r--arch/arm/boot/dts/usb_a9260.dts23
-rw-r--r--arch/arm/boot/dts/usb_a9260_common.dtsi117
-rw-r--r--arch/arm/boot/dts/usb_a9263.dts131
-rw-r--r--arch/arm/boot/dts/usb_a9g20.dts102
72 files changed, 7291 insertions, 982 deletions
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
new file mode 100644
index 000000000000..f449efc9825f
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -0,0 +1,273 @@
1/*
2 * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9260 family SoC";
15 compatible = "atmel,at91sam9260";
16 interrupt-parent = <&aic>;
17
18 aliases {
19 serial0 = &dbgu;
20 serial1 = &usart0;
21 serial2 = &usart1;
22 serial3 = &usart2;
23 serial4 = &usart3;
24 serial5 = &usart4;
25 serial6 = &usart5;
26 gpio0 = &pioA;
27 gpio1 = &pioB;
28 gpio2 = &pioC;
29 tcb0 = &tcb0;
30 tcb1 = &tcb1;
31 };
32 cpus {
33 cpu@0 {
34 compatible = "arm,arm926ejs";
35 };
36 };
37
38 memory {
39 reg = <0x20000000 0x04000000>;
40 };
41
42 ahb {
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 ranges;
47
48 apb {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
53
54 aic: interrupt-controller@fffff000 {
55 #interrupt-cells = <2>;
56 compatible = "atmel,at91rm9200-aic";
57 interrupt-controller;
58 reg = <0xfffff000 0x200>;
59 };
60
61 ramc0: ramc@ffffea00 {
62 compatible = "atmel,at91sam9260-sdramc";
63 reg = <0xffffea00 0x200>;
64 };
65
66 pmc: pmc@fffffc00 {
67 compatible = "atmel,at91rm9200-pmc";
68 reg = <0xfffffc00 0x100>;
69 };
70
71 rstc@fffffd00 {
72 compatible = "atmel,at91sam9260-rstc";
73 reg = <0xfffffd00 0x10>;
74 };
75
76 shdwc@fffffd10 {
77 compatible = "atmel,at91sam9260-shdwc";
78 reg = <0xfffffd10 0x10>;
79 };
80
81 pit: timer@fffffd30 {
82 compatible = "atmel,at91sam9260-pit";
83 reg = <0xfffffd30 0xf>;
84 interrupts = <1 4>;
85 };
86
87 tcb0: timer@fffa0000 {
88 compatible = "atmel,at91rm9200-tcb";
89 reg = <0xfffa0000 0x100>;
90 interrupts = <17 4 18 4 19 4>;
91 };
92
93 tcb1: timer@fffdc000 {
94 compatible = "atmel,at91rm9200-tcb";
95 reg = <0xfffdc000 0x100>;
96 interrupts = <26 4 27 4 28 4>;
97 };
98
99 pioA: gpio@fffff400 {
100 compatible = "atmel,at91rm9200-gpio";
101 reg = <0xfffff400 0x100>;
102 interrupts = <2 4>;
103 #gpio-cells = <2>;
104 gpio-controller;
105 interrupt-controller;
106 };
107
108 pioB: gpio@fffff600 {
109 compatible = "atmel,at91rm9200-gpio";
110 reg = <0xfffff600 0x100>;
111 interrupts = <3 4>;
112 #gpio-cells = <2>;
113 gpio-controller;
114 interrupt-controller;
115 };
116
117 pioC: gpio@fffff800 {
118 compatible = "atmel,at91rm9200-gpio";
119 reg = <0xfffff800 0x100>;
120 interrupts = <4 4>;
121 #gpio-cells = <2>;
122 gpio-controller;
123 interrupt-controller;
124 };
125
126 dbgu: serial@fffff200 {
127 compatible = "atmel,at91sam9260-usart";
128 reg = <0xfffff200 0x200>;
129 interrupts = <1 4>;
130 status = "disabled";
131 };
132
133 usart0: serial@fffb0000 {
134 compatible = "atmel,at91sam9260-usart";
135 reg = <0xfffb0000 0x200>;
136 interrupts = <6 4>;
137 atmel,use-dma-rx;
138 atmel,use-dma-tx;
139 status = "disabled";
140 };
141
142 usart1: serial@fffb4000 {
143 compatible = "atmel,at91sam9260-usart";
144 reg = <0xfffb4000 0x200>;
145 interrupts = <7 4>;
146 atmel,use-dma-rx;
147 atmel,use-dma-tx;
148 status = "disabled";
149 };
150
151 usart2: serial@fffb8000 {
152 compatible = "atmel,at91sam9260-usart";
153 reg = <0xfffb8000 0x200>;
154 interrupts = <8 4>;
155 atmel,use-dma-rx;
156 atmel,use-dma-tx;
157 status = "disabled";
158 };
159
160 usart3: serial@fffd0000 {
161 compatible = "atmel,at91sam9260-usart";
162 reg = <0xfffd0000 0x200>;
163 interrupts = <23 4>;
164 atmel,use-dma-rx;
165 atmel,use-dma-tx;
166 status = "disabled";
167 };
168
169 usart4: serial@fffd4000 {
170 compatible = "atmel,at91sam9260-usart";
171 reg = <0xfffd4000 0x200>;
172 interrupts = <24 4>;
173 atmel,use-dma-rx;
174 atmel,use-dma-tx;
175 status = "disabled";
176 };
177
178 usart5: serial@fffd8000 {
179 compatible = "atmel,at91sam9260-usart";
180 reg = <0xfffd8000 0x200>;
181 interrupts = <25 4>;
182 atmel,use-dma-rx;
183 atmel,use-dma-tx;
184 status = "disabled";
185 };
186
187 macb0: ethernet@fffc4000 {
188 compatible = "cdns,at32ap7000-macb", "cdns,macb";
189 reg = <0xfffc4000 0x100>;
190 interrupts = <21 4>;
191 status = "disabled";
192 };
193
194 usb1: gadget@fffa4000 {
195 compatible = "atmel,at91rm9200-udc";
196 reg = <0xfffa4000 0x4000>;
197 interrupts = <10 4>;
198 status = "disabled";
199 };
200
201 adc0: adc@fffe0000 {
202 compatible = "atmel,at91sam9260-adc";
203 reg = <0xfffe0000 0x100>;
204 interrupts = <5 4>;
205 atmel,adc-use-external-triggers;
206 atmel,adc-channels-used = <0xf>;
207 atmel,adc-vref = <3300>;
208 atmel,adc-num-channels = <4>;
209 atmel,adc-startup-time = <15>;
210 atmel,adc-channel-base = <0x30>;
211 atmel,adc-drdy-mask = <0x10000>;
212 atmel,adc-status-register = <0x1c>;
213 atmel,adc-trigger-register = <0x04>;
214
215 trigger@0 {
216 trigger-name = "timer-counter-0";
217 trigger-value = <0x1>;
218 };
219 trigger@1 {
220 trigger-name = "timer-counter-1";
221 trigger-value = <0x3>;
222 };
223
224 trigger@2 {
225 trigger-name = "timer-counter-2";
226 trigger-value = <0x5>;
227 };
228
229 trigger@3 {
230 trigger-name = "external";
231 trigger-value = <0x13>;
232 trigger-external;
233 };
234 };
235 };
236
237 nand0: nand@40000000 {
238 compatible = "atmel,at91rm9200-nand";
239 #address-cells = <1>;
240 #size-cells = <1>;
241 reg = <0x40000000 0x10000000
242 0xffffe800 0x200
243 >;
244 atmel,nand-addr-offset = <21>;
245 atmel,nand-cmd-offset = <22>;
246 gpios = <&pioC 13 0
247 &pioC 14 0
248 0
249 >;
250 status = "disabled";
251 };
252
253 usb0: ohci@00500000 {
254 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
255 reg = <0x00500000 0x100000>;
256 interrupts = <20 4>;
257 status = "disabled";
258 };
259 };
260
261 i2c@0 {
262 compatible = "i2c-gpio";
263 gpios = <&pioA 23 0 /* sda */
264 &pioA 24 0 /* scl */
265 >;
266 i2c-gpio,sda-open-drain;
267 i2c-gpio,scl-open-drain;
268 i2c-gpio,delay-us = <2>; /* ~100 kHz */
269 #address-cells = <1>;
270 #size-cells = <0>;
271 status = "disabled";
272 };
273};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
new file mode 100644
index 000000000000..0209913a65a2
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -0,0 +1,220 @@
1/*
2 * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only.
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9263 family SoC";
13 compatible = "atmel,at91sam9263";
14 interrupt-parent = <&aic>;
15
16 aliases {
17 serial0 = &dbgu;
18 serial1 = &usart0;
19 serial2 = &usart1;
20 serial3 = &usart2;
21 gpio0 = &pioA;
22 gpio1 = &pioB;
23 gpio2 = &pioC;
24 gpio3 = &pioD;
25 gpio4 = &pioE;
26 tcb0 = &tcb0;
27 };
28 cpus {
29 cpu@0 {
30 compatible = "arm,arm926ejs";
31 };
32 };
33
34 memory {
35 reg = <0x20000000 0x08000000>;
36 };
37
38 ahb {
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <1>;
42 ranges;
43
44 apb {
45 compatible = "simple-bus";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 ranges;
49
50 aic: interrupt-controller@fffff000 {
51 #interrupt-cells = <2>;
52 compatible = "atmel,at91rm9200-aic";
53 interrupt-controller;
54 reg = <0xfffff000 0x200>;
55 };
56
57 pmc: pmc@fffffc00 {
58 compatible = "atmel,at91rm9200-pmc";
59 reg = <0xfffffc00 0x100>;
60 };
61
62 ramc: ramc@ffffe200 {
63 compatible = "atmel,at91sam9260-sdramc";
64 reg = <0xffffe200 0x200
65 0xffffe800 0x200>;
66 };
67
68 pit: timer@fffffd30 {
69 compatible = "atmel,at91sam9260-pit";
70 reg = <0xfffffd30 0xf>;
71 interrupts = <1 4>;
72 };
73
74 tcb0: timer@fff7c000 {
75 compatible = "atmel,at91rm9200-tcb";
76 reg = <0xfff7c000 0x100>;
77 interrupts = <19 4>;
78 };
79
80 rstc@fffffd00 {
81 compatible = "atmel,at91sam9260-rstc";
82 reg = <0xfffffd00 0x10>;
83 };
84
85 shdwc@fffffd10 {
86 compatible = "atmel,at91sam9260-shdwc";
87 reg = <0xfffffd10 0x10>;
88 };
89
90 pioA: gpio@fffff200 {
91 compatible = "atmel,at91rm9200-gpio";
92 reg = <0xfffff200 0x100>;
93 interrupts = <2 4>;
94 #gpio-cells = <2>;
95 gpio-controller;
96 interrupt-controller;
97 };
98
99 pioB: gpio@fffff400 {
100 compatible = "atmel,at91rm9200-gpio";
101 reg = <0xfffff400 0x100>;
102 interrupts = <3 4>;
103 #gpio-cells = <2>;
104 gpio-controller;
105 interrupt-controller;
106 };
107
108 pioC: gpio@fffff600 {
109 compatible = "atmel,at91rm9200-gpio";
110 reg = <0xfffff600 0x100>;
111 interrupts = <4 4>;
112 #gpio-cells = <2>;
113 gpio-controller;
114 interrupt-controller;
115 };
116
117 pioD: gpio@fffff800 {
118 compatible = "atmel,at91rm9200-gpio";
119 reg = <0xfffff800 0x100>;
120 interrupts = <4 4>;
121 #gpio-cells = <2>;
122 gpio-controller;
123 interrupt-controller;
124 };
125
126 pioE: gpio@fffffa00 {
127 compatible = "atmel,at91rm9200-gpio";
128 reg = <0xfffffa00 0x100>;
129 interrupts = <4 4>;
130 #gpio-cells = <2>;
131 gpio-controller;
132 interrupt-controller;
133 };
134
135 dbgu: serial@ffffee00 {
136 compatible = "atmel,at91sam9260-usart";
137 reg = <0xffffee00 0x200>;
138 interrupts = <1 4>;
139 status = "disabled";
140 };
141
142 usart0: serial@fff8c000 {
143 compatible = "atmel,at91sam9260-usart";
144 reg = <0xfff8c000 0x200>;
145 interrupts = <7 4>;
146 atmel,use-dma-rx;
147 atmel,use-dma-tx;
148 status = "disabled";
149 };
150
151 usart1: serial@fff90000 {
152 compatible = "atmel,at91sam9260-usart";
153 reg = <0xfff90000 0x200>;
154 interrupts = <8 4>;
155 atmel,use-dma-rx;
156 atmel,use-dma-tx;
157 status = "disabled";
158 };
159
160 usart2: serial@fff94000 {
161 compatible = "atmel,at91sam9260-usart";
162 reg = <0xfff94000 0x200>;
163 interrupts = <9 4>;
164 atmel,use-dma-rx;
165 atmel,use-dma-tx;
166 status = "disabled";
167 };
168
169 macb0: ethernet@fffbc000 {
170 compatible = "cdns,at32ap7000-macb", "cdns,macb";
171 reg = <0xfffbc000 0x100>;
172 interrupts = <21 4>;
173 status = "disabled";
174 };
175
176 usb1: gadget@fff78000 {
177 compatible = "atmel,at91rm9200-udc";
178 reg = <0xfff78000 0x4000>;
179 interrupts = <24 4>;
180 status = "disabled";
181 };
182 };
183
184 nand0: nand@40000000 {
185 compatible = "atmel,at91rm9200-nand";
186 #address-cells = <1>;
187 #size-cells = <1>;
188 reg = <0x40000000 0x10000000
189 0xffffe000 0x200
190 >;
191 atmel,nand-addr-offset = <21>;
192 atmel,nand-cmd-offset = <22>;
193 gpios = <&pioA 22 0
194 &pioD 15 0
195 0
196 >;
197 status = "disabled";
198 };
199
200 usb0: ohci@00a00000 {
201 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
202 reg = <0x00a00000 0x100000>;
203 interrupts = <29 4>;
204 status = "disabled";
205 };
206 };
207
208 i2c@0 {
209 compatible = "i2c-gpio";
210 gpios = <&pioB 4 0 /* sda */
211 &pioB 5 0 /* scl */
212 >;
213 i2c-gpio,sda-open-drain;
214 i2c-gpio,scl-open-drain;
215 i2c-gpio,delay-us = <2>; /* ~100 kHz */
216 #address-cells = <1>;
217 #size-cells = <0>;
218 status = "disabled";
219 };
220};
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
new file mode 100644
index 000000000000..f86ac4b609fc
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -0,0 +1,156 @@
1/*
2 * at91sam9263ek.dts - Device Tree file for Atmel at91sam9263 reference board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only
7 */
8/dts-v1/;
9/include/ "at91sam9263.dtsi"
10
11/ {
12 model = "Atmel at91sam9263ek";
13 compatible = "atmel,at91sam9263ek", "atmel,at91sam9263", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
17 };
18
19 memory {
20 reg = <0x20000000 0x4000000>;
21 };
22
23 clocks {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 main_clock: clock@0 {
29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <16367660>;
31 };
32 };
33
34 ahb {
35 apb {
36 dbgu: serial@ffffee00 {
37 status = "okay";
38 };
39
40 usart0: serial@fff8c000 {
41 status = "okay";
42 };
43
44 macb0: ethernet@fffbc000 {
45 phy-mode = "rmii";
46 status = "okay";
47 };
48
49 usb1: gadget@fff78000 {
50 atmel,vbus-gpio = <&pioA 25 0>;
51 status = "okay";
52 };
53 };
54
55 nand0: nand@40000000 {
56 nand-bus-width = <8>;
57 nand-ecc-mode = "soft";
58 nand-on-flash-bbt = <1>;
59 status = "okay";
60
61 at91bootstrap@0 {
62 label = "at91bootstrap";
63 reg = <0x0 0x20000>;
64 };
65
66 barebox@20000 {
67 label = "barebox";
68 reg = <0x20000 0x40000>;
69 };
70
71 bareboxenv@60000 {
72 label = "bareboxenv";
73 reg = <0x60000 0x20000>;
74 };
75
76 bareboxenv2@80000 {
77 label = "bareboxenv2";
78 reg = <0x80000 0x20000>;
79 };
80
81 oftree@80000 {
82 label = "oftree";
83 reg = <0xa0000 0x20000>;
84 };
85
86 kernel@a0000 {
87 label = "kernel";
88 reg = <0xc0000 0x400000>;
89 };
90
91 rootfs@4a0000 {
92 label = "rootfs";
93 reg = <0x4c0000 0x7800000>;
94 };
95
96 data@7ca0000 {
97 label = "data";
98 reg = <0x7cc0000 0x8340000>;
99 };
100 };
101
102 usb0: ohci@00a00000 {
103 num-ports = <2>;
104 status = "okay";
105 atmel,vbus-gpio = <&pioA 24 0
106 &pioA 21 0
107 >;
108 };
109 };
110
111 leds {
112 compatible = "gpio-leds";
113
114 d3 {
115 label = "d3";
116 gpios = <&pioB 7 0>;
117 linux,default-trigger = "heartbeat";
118 };
119
120 d2 {
121 label = "d2";
122 gpios = <&pioC 29 1>;
123 linux,default-trigger = "nand-disk";
124 };
125 };
126
127 gpio_keys {
128 compatible = "gpio-keys";
129 #address-cells = <1>;
130 #size-cells = <0>;
131
132 left_click {
133 label = "left_click";
134 gpios = <&pioC 5 1>;
135 linux,code = <272>;
136 gpio-key,wakeup;
137 };
138
139 right_click {
140 label = "right_click";
141 gpios = <&pioC 4 1>;
142 linux,code = <273>;
143 gpio-key,wakeup;
144 };
145 };
146
147 i2c@0 {
148 status = "okay";
149
150 24c512@50 {
151 compatible = "24c512";
152 reg = <0x50>;
153 pagesize = <128>;
154 };
155 };
156};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 773ef484037a..2a1d1ca8bd86 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -1,238 +1,26 @@
1/* 1/*
2 * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC 2 * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
3 * 3 *
4 * Copyright (C) 2011 Atmel, 4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 * 5 *
8 * Licensed under GPLv2 or later. 6 * Licensed under GPLv2.
9 */ 7 */
10 8
11/include/ "skeleton.dtsi" 9/include/ "at91sam9260.dtsi"
12 10
13/ { 11/ {
14 model = "Atmel AT91SAM9G20 family SoC"; 12 model = "Atmel AT91SAM9G20 family SoC";
15 compatible = "atmel,at91sam9g20"; 13 compatible = "atmel,at91sam9g20";
16 interrupt-parent = <&aic>;
17
18 aliases {
19 serial0 = &dbgu;
20 serial1 = &usart0;
21 serial2 = &usart1;
22 serial3 = &usart2;
23 serial4 = &usart3;
24 serial5 = &usart4;
25 serial6 = &usart5;
26 gpio0 = &pioA;
27 gpio1 = &pioB;
28 gpio2 = &pioC;
29 tcb0 = &tcb0;
30 tcb1 = &tcb1;
31 };
32 cpus {
33 cpu@0 {
34 compatible = "arm,arm926ejs";
35 };
36 };
37 14
38 memory { 15 memory {
39 reg = <0x20000000 0x08000000>; 16 reg = <0x20000000 0x08000000>;
40 }; 17 };
41 18
42 ahb { 19 ahb {
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 ranges;
47
48 apb { 20 apb {
49 compatible = "simple-bus"; 21 adc0: adc@fffe0000 {
50 #address-cells = <1>; 22 atmel,adc-startup-time = <40>;
51 #size-cells = <1>;
52 ranges;
53
54 aic: interrupt-controller@fffff000 {
55 #interrupt-cells = <2>;
56 compatible = "atmel,at91rm9200-aic";
57 interrupt-controller;
58 reg = <0xfffff000 0x200>;
59 };
60
61 ramc0: ramc@ffffea00 {
62 compatible = "atmel,at91sam9260-sdramc";
63 reg = <0xffffea00 0x200>;
64 };
65
66 pmc: pmc@fffffc00 {
67 compatible = "atmel,at91rm9200-pmc";
68 reg = <0xfffffc00 0x100>;
69 };
70
71 rstc@fffffd00 {
72 compatible = "atmel,at91sam9260-rstc";
73 reg = <0xfffffd00 0x10>;
74 };
75
76 shdwc@fffffd10 {
77 compatible = "atmel,at91sam9260-shdwc";
78 reg = <0xfffffd10 0x10>;
79 };
80
81 pit: timer@fffffd30 {
82 compatible = "atmel,at91sam9260-pit";
83 reg = <0xfffffd30 0xf>;
84 interrupts = <1 4>;
85 };
86
87 tcb0: timer@fffa0000 {
88 compatible = "atmel,at91rm9200-tcb";
89 reg = <0xfffa0000 0x100>;
90 interrupts = <17 4 18 4 19 4>;
91 };
92
93 tcb1: timer@fffdc000 {
94 compatible = "atmel,at91rm9200-tcb";
95 reg = <0xfffdc000 0x100>;
96 interrupts = <26 4 27 4 28 4>;
97 };
98
99 pioA: gpio@fffff400 {
100 compatible = "atmel,at91rm9200-gpio";
101 reg = <0xfffff400 0x100>;
102 interrupts = <2 4>;
103 #gpio-cells = <2>;
104 gpio-controller;
105 interrupt-controller;
106 };
107
108 pioB: gpio@fffff600 {
109 compatible = "atmel,at91rm9200-gpio";
110 reg = <0xfffff600 0x100>;
111 interrupts = <3 4>;
112 #gpio-cells = <2>;
113 gpio-controller;
114 interrupt-controller;
115 };
116
117 pioC: gpio@fffff800 {
118 compatible = "atmel,at91rm9200-gpio";
119 reg = <0xfffff800 0x100>;
120 interrupts = <4 4>;
121 #gpio-cells = <2>;
122 gpio-controller;
123 interrupt-controller;
124 };
125
126 dbgu: serial@fffff200 {
127 compatible = "atmel,at91sam9260-usart";
128 reg = <0xfffff200 0x200>;
129 interrupts = <1 4>;
130 status = "disabled";
131 };
132
133 usart0: serial@fffb0000 {
134 compatible = "atmel,at91sam9260-usart";
135 reg = <0xfffb0000 0x200>;
136 interrupts = <6 4>;
137 atmel,use-dma-rx;
138 atmel,use-dma-tx;
139 status = "disabled";
140 };
141
142 usart1: serial@fffb4000 {
143 compatible = "atmel,at91sam9260-usart";
144 reg = <0xfffb4000 0x200>;
145 interrupts = <7 4>;
146 atmel,use-dma-rx;
147 atmel,use-dma-tx;
148 status = "disabled";
149 };
150
151 usart2: serial@fffb8000 {
152 compatible = "atmel,at91sam9260-usart";
153 reg = <0xfffb8000 0x200>;
154 interrupts = <8 4>;
155 atmel,use-dma-rx;
156 atmel,use-dma-tx;
157 status = "disabled";
158 };
159
160 usart3: serial@fffd0000 {
161 compatible = "atmel,at91sam9260-usart";
162 reg = <0xfffd0000 0x200>;
163 interrupts = <23 4>;
164 atmel,use-dma-rx;
165 atmel,use-dma-tx;
166 status = "disabled";
167 };
168
169 usart4: serial@fffd4000 {
170 compatible = "atmel,at91sam9260-usart";
171 reg = <0xfffd4000 0x200>;
172 interrupts = <24 4>;
173 atmel,use-dma-rx;
174 atmel,use-dma-tx;
175 status = "disabled";
176 };
177
178 usart5: serial@fffd8000 {
179 compatible = "atmel,at91sam9260-usart";
180 reg = <0xfffd8000 0x200>;
181 interrupts = <25 4>;
182 atmel,use-dma-rx;
183 atmel,use-dma-tx;
184 status = "disabled";
185 };
186
187 macb0: ethernet@fffc4000 {
188 compatible = "cdns,at32ap7000-macb", "cdns,macb";
189 reg = <0xfffc4000 0x100>;
190 interrupts = <21 4>;
191 status = "disabled";
192 };
193
194 usb1: gadget@fffa4000 {
195 compatible = "atmel,at91rm9200-udc";
196 reg = <0xfffa4000 0x4000>;
197 interrupts = <10 4>;
198 status = "disabled";
199 }; 23 };
200 }; 24 };
201
202 nand0: nand@40000000 {
203 compatible = "atmel,at91rm9200-nand";
204 #address-cells = <1>;
205 #size-cells = <1>;
206 reg = <0x40000000 0x10000000
207 0xffffe800 0x200
208 >;
209 atmel,nand-addr-offset = <21>;
210 atmel,nand-cmd-offset = <22>;
211 gpios = <&pioC 13 0
212 &pioC 14 0
213 0
214 >;
215 status = "disabled";
216 };
217
218 usb0: ohci@00500000 {
219 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
220 reg = <0x00500000 0x100000>;
221 interrupts = <20 4>;
222 status = "disabled";
223 };
224 };
225
226 i2c@0 {
227 compatible = "i2c-gpio";
228 gpios = <&pioA 23 0 /* sda */
229 &pioA 24 0 /* scl */
230 >;
231 i2c-gpio,sda-open-drain;
232 i2c-gpio,scl-open-drain;
233 i2c-gpio,delay-us = <2>; /* ~100 kHz */
234 #address-cells = <1>;
235 #size-cells = <0>;
236 status = "disabled";
237 }; 25 };
238}; 26};
diff --git a/arch/arm/boot/dts/at91sam9g20ek.dts b/arch/arm/boot/dts/at91sam9g20ek.dts
new file mode 100644
index 000000000000..e5324bf9d529
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g20ek.dts
@@ -0,0 +1,29 @@
1/*
2 * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8/dts-v1/;
9/include/ "at91sam9g20ek_common.dtsi"
10
11/ {
12 model = "Atmel at91sam9g20ek";
13 compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9";
14
15 leds {
16 compatible = "gpio-leds";
17
18 ds1 {
19 label = "ds1";
20 gpios = <&pioA 9 0>;
21 linux,default-trigger = "heartbeat";
22 };
23
24 ds5 {
25 label = "ds5";
26 gpios = <&pioA 6 1>;
27 };
28 };
29};
diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
new file mode 100644
index 000000000000..f1b2e148ac8c
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
@@ -0,0 +1,29 @@
1/*
2 * at91sam9g20ek_2mmc.dts - Device Tree file for Atmel at91sam9g20ek 2 MMC board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8/dts-v1/;
9/include/ "at91sam9g20ek_common.dtsi"
10
11/ {
12 model = "Atmel at91sam9g20ek 2 mmc";
13 compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9";
14
15 leds {
16 compatible = "gpio-leds";
17
18 ds1 {
19 label = "ds1";
20 gpios = <&pioB 9 0>;
21 linux,default-trigger = "heartbeat";
22 };
23
24 ds5 {
25 label = "ds5";
26 gpios = <&pioB 8 1>;
27 };
28 };
29};
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
new file mode 100644
index 000000000000..b06c0db273b1
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -0,0 +1,142 @@
1/*
2 * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8/include/ "at91sam9g20.dtsi"
9
10/ {
11
12 chosen {
13 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
14 };
15
16 memory {
17 reg = <0x20000000 0x4000000>;
18 };
19
20 clocks {
21 #address-cells = <1>;
22 #size-cells = <1>;
23 ranges;
24
25 main_clock: clock@0 {
26 compatible = "atmel,osc", "fixed-clock";
27 clock-frequency = <18432000>;
28 };
29 };
30
31 ahb {
32 apb {
33 dbgu: serial@fffff200 {
34 status = "okay";
35 };
36
37 usart0: serial@fffb0000 {
38 status = "okay";
39 };
40
41 usart1: serial@fffb4000 {
42 status = "okay";
43 };
44
45 macb0: ethernet@fffc4000 {
46 phy-mode = "rmii";
47 status = "okay";
48 };
49
50 usb1: gadget@fffa4000 {
51 atmel,vbus-gpio = <&pioC 5 0>;
52 status = "okay";
53 };
54 };
55
56 nand0: nand@40000000 {
57 nand-bus-width = <8>;
58 nand-ecc-mode = "soft";
59 nand-on-flash-bbt;
60 status = "okay";
61
62 at91bootstrap@0 {
63 label = "at91bootstrap";
64 reg = <0x0 0x20000>;
65 };
66
67 barebox@20000 {
68 label = "barebox";
69 reg = <0x20000 0x40000>;
70 };
71
72 bareboxenv@60000 {
73 label = "bareboxenv";
74 reg = <0x60000 0x20000>;
75 };
76
77 bareboxenv2@80000 {
78 label = "bareboxenv2";
79 reg = <0x80000 0x20000>;
80 };
81
82 oftree@80000 {
83 label = "oftree";
84 reg = <0xa0000 0x20000>;
85 };
86
87 kernel@a0000 {
88 label = "kernel";
89 reg = <0xc0000 0x400000>;
90 };
91
92 rootfs@4a0000 {
93 label = "rootfs";
94 reg = <0x4c0000 0x7800000>;
95 };
96
97 data@7ca0000 {
98 label = "data";
99 reg = <0x7cc0000 0x8340000>;
100 };
101 };
102
103 usb0: ohci@00500000 {
104 num-ports = <2>;
105 status = "okay";
106 };
107 };
108
109 i2c@0 {
110 status = "okay";
111
112 24c512@50 {
113 compatible = "24c512";
114 reg = <0x50>;
115 };
116
117 wm8731@1b {
118 compatible = "wm8731";
119 reg = <0x1b>;
120 };
121 };
122
123 gpio_keys {
124 compatible = "gpio-keys";
125 #address-cells = <1>;
126 #size-cells = <0>;
127
128 btn3 {
129 label = "Buttin 3";
130 gpios = <&pioA 30 1>;
131 linux,code = <0x103>;
132 gpio-key,wakeup;
133 };
134
135 btn4 {
136 label = "Buttin 4";
137 gpios = <&pioA 31 1>;
138 linux,code = <0x104>;
139 gpio-key,wakeup;
140 };
141 };
142};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index c8042147eaa2..7dbccaf199f7 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -199,6 +199,43 @@
199 interrupts = <25 4>; 199 interrupts = <25 4>;
200 status = "disabled"; 200 status = "disabled";
201 }; 201 };
202
203 adc0: adc@fffb0000 {
204 compatible = "atmel,at91sam9260-adc";
205 reg = <0xfffb0000 0x100>;
206 interrupts = <20 4>;
207 atmel,adc-use-external-triggers;
208 atmel,adc-channels-used = <0xff>;
209 atmel,adc-vref = <3300>;
210 atmel,adc-num-channels = <8>;
211 atmel,adc-startup-time = <40>;
212 atmel,adc-channel-base = <0x30>;
213 atmel,adc-drdy-mask = <0x10000>;
214 atmel,adc-status-register = <0x1c>;
215 atmel,adc-trigger-register = <0x08>;
216
217 trigger@0 {
218 trigger-name = "external-rising";
219 trigger-value = <0x1>;
220 trigger-external;
221 };
222 trigger@1 {
223 trigger-name = "external-falling";
224 trigger-value = <0x2>;
225 trigger-external;
226 };
227
228 trigger@2 {
229 trigger-name = "external-any";
230 trigger-value = <0x3>;
231 trigger-external;
232 };
233
234 trigger@3 {
235 trigger-name = "continuous";
236 trigger-value = <0x6>;
237 };
238 };
202 }; 239 };
203 240
204 nand0: nand@40000000 { 241 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
new file mode 100644
index 000000000000..cb84de791b5a
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -0,0 +1,221 @@
1/*
2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 model = "Atmel AT91SAM9N12 SoC";
14 compatible = "atmel,at91sam9n12";
15 interrupt-parent = <&aic>;
16
17 aliases {
18 serial0 = &dbgu;
19 serial1 = &usart0;
20 serial2 = &usart1;
21 serial3 = &usart2;
22 serial4 = &usart3;
23 gpio0 = &pioA;
24 gpio1 = &pioB;
25 gpio2 = &pioC;
26 gpio3 = &pioD;
27 tcb0 = &tcb0;
28 tcb1 = &tcb1;
29 };
30 cpus {
31 cpu@0 {
32 compatible = "arm,arm926ejs";
33 };
34 };
35
36 memory {
37 reg = <0x20000000 0x10000000>;
38 };
39
40 ahb {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 ranges;
45
46 apb {
47 compatible = "simple-bus";
48 #address-cells = <1>;
49 #size-cells = <1>;
50 ranges;
51
52 aic: interrupt-controller@fffff000 {
53 #interrupt-cells = <2>;
54 compatible = "atmel,at91rm9200-aic";
55 interrupt-controller;
56 reg = <0xfffff000 0x200>;
57 };
58
59 ramc0: ramc@ffffe800 {
60 compatible = "atmel,at91sam9g45-ddramc";
61 reg = <0xffffe800 0x200>;
62 };
63
64 pmc: pmc@fffffc00 {
65 compatible = "atmel,at91rm9200-pmc";
66 reg = <0xfffffc00 0x100>;
67 };
68
69 rstc@fffffe00 {
70 compatible = "atmel,at91sam9g45-rstc";
71 reg = <0xfffffe00 0x10>;
72 };
73
74 pit: timer@fffffe30 {
75 compatible = "atmel,at91sam9260-pit";
76 reg = <0xfffffe30 0xf>;
77 interrupts = <1 4>;
78 };
79
80 shdwc@fffffe10 {
81 compatible = "atmel,at91sam9x5-shdwc";
82 reg = <0xfffffe10 0x10>;
83 };
84
85 tcb0: timer@f8008000 {
86 compatible = "atmel,at91sam9x5-tcb";
87 reg = <0xf8008000 0x100>;
88 interrupts = <17 4>;
89 };
90
91 tcb1: timer@f800c000 {
92 compatible = "atmel,at91sam9x5-tcb";
93 reg = <0xf800c000 0x100>;
94 interrupts = <17 4>;
95 };
96
97 dma: dma-controller@ffffec00 {
98 compatible = "atmel,at91sam9g45-dma";
99 reg = <0xffffec00 0x200>;
100 interrupts = <20 4>;
101 };
102
103 pioA: gpio@fffff400 {
104 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
105 reg = <0xfffff400 0x100>;
106 interrupts = <2 4>;
107 #gpio-cells = <2>;
108 gpio-controller;
109 interrupt-controller;
110 };
111
112 pioB: gpio@fffff600 {
113 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
114 reg = <0xfffff600 0x100>;
115 interrupts = <2 4>;
116 #gpio-cells = <2>;
117 gpio-controller;
118 interrupt-controller;
119 };
120
121 pioC: gpio@fffff800 {
122 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
123 reg = <0xfffff800 0x100>;
124 interrupts = <3 4>;
125 #gpio-cells = <2>;
126 gpio-controller;
127 interrupt-controller;
128 };
129
130 pioD: gpio@fffffa00 {
131 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
132 reg = <0xfffffa00 0x100>;
133 interrupts = <3 4>;
134 #gpio-cells = <2>;
135 gpio-controller;
136 interrupt-controller;
137 };
138
139 dbgu: serial@fffff200 {
140 compatible = "atmel,at91sam9260-usart";
141 reg = <0xfffff200 0x200>;
142 interrupts = <1 4>;
143 status = "disabled";
144 };
145
146 usart0: serial@f801c000 {
147 compatible = "atmel,at91sam9260-usart";
148 reg = <0xf801c000 0x4000>;
149 interrupts = <5 4>;
150 atmel,use-dma-rx;
151 atmel,use-dma-tx;
152 status = "disabled";
153 };
154
155 usart1: serial@f8020000 {
156 compatible = "atmel,at91sam9260-usart";
157 reg = <0xf8020000 0x4000>;
158 interrupts = <6 4>;
159 atmel,use-dma-rx;
160 atmel,use-dma-tx;
161 status = "disabled";
162 };
163
164 usart2: serial@f8024000 {
165 compatible = "atmel,at91sam9260-usart";
166 reg = <0xf8024000 0x4000>;
167 interrupts = <7 4>;
168 atmel,use-dma-rx;
169 atmel,use-dma-tx;
170 status = "disabled";
171 };
172
173 usart3: serial@f8028000 {
174 compatible = "atmel,at91sam9260-usart";
175 reg = <0xf8028000 0x4000>;
176 interrupts = <8 4>;
177 atmel,use-dma-rx;
178 atmel,use-dma-tx;
179 status = "disabled";
180 };
181 };
182
183 nand0: nand@40000000 {
184 compatible = "atmel,at91rm9200-nand";
185 #address-cells = <1>;
186 #size-cells = <1>;
187 reg = < 0x40000000 0x10000000
188 0xffffe000 0x00000600
189 0xffffe600 0x00000200
190 0x00100000 0x00100000
191 >;
192 atmel,nand-addr-offset = <21>;
193 atmel,nand-cmd-offset = <22>;
194 gpios = <&pioD 5 0
195 &pioD 4 0
196 0
197 >;
198 status = "disabled";
199 };
200
201 usb0: ohci@00500000 {
202 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
203 reg = <0x00500000 0x00100000>;
204 interrupts = <22 4>;
205 status = "disabled";
206 };
207 };
208
209 i2c@0 {
210 compatible = "i2c-gpio";
211 gpios = <&pioA 30 0 /* sda */
212 &pioA 31 0 /* scl */
213 >;
214 i2c-gpio,sda-open-drain;
215 i2c-gpio,scl-open-drain;
216 i2c-gpio,delay-us = <2>; /* ~100 kHz */
217 #address-cells = <1>;
218 #size-cells = <0>;
219 status = "disabled";
220 };
221};
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
new file mode 100644
index 000000000000..f4e43e38f3a1
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -0,0 +1,84 @@
1/*
2 * at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9n12.dtsi"
11
12/ {
13 model = "Atmel AT91SAM9N12-EK";
14 compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9";
15
16 chosen {
17 bootargs = "mem=128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2";
18 };
19
20 memory {
21 reg = <0x20000000 0x10000000>;
22 };
23
24 clocks {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges;
28
29 main_clock: clock@0 {
30 compatible = "atmel,osc", "fixed-clock";
31 clock-frequency = <16000000>;
32 };
33 };
34
35 ahb {
36 apb {
37 dbgu: serial@fffff200 {
38 status = "okay";
39 };
40 };
41
42 nand0: nand@40000000 {
43 nand-bus-width = <8>;
44 nand-ecc-mode = "soft";
45 nand-on-flash-bbt;
46 status = "okay";
47 };
48 };
49
50 leds {
51 compatible = "gpio-leds";
52
53 d8 {
54 label = "d8";
55 gpios = <&pioB 4 1>;
56 linux,default-trigger = "mmc0";
57 };
58
59 d9 {
60 label = "d6";
61 gpios = <&pioB 5 1>;
62 linux,default-trigger = "nand-disk";
63 };
64
65 d10 {
66 label = "d7";
67 gpios = <&pioB 6 0>;
68 linux,default-trigger = "heartbeat";
69 };
70 };
71
72 gpio_keys {
73 compatible = "gpio-keys";
74 #address-cells = <1>;
75 #size-cells = <0>;
76
77 enter {
78 label = "Enter";
79 gpios = <&pioB 4 1>;
80 linux,code = <28>;
81 gpio-key,wakeup;
82 };
83 };
84};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index dd4ed748469a..6b3ef4339ae7 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -190,6 +190,44 @@
190 interrupts = <27 4>; 190 interrupts = <27 4>;
191 status = "disabled"; 191 status = "disabled";
192 }; 192 };
193
194 adc0: adc@f804c000 {
195 compatible = "atmel,at91sam9260-adc";
196 reg = <0xf804c000 0x100>;
197 interrupts = <19 4>;
198 atmel,adc-use-external;
199 atmel,adc-channels-used = <0xffff>;
200 atmel,adc-vref = <3300>;
201 atmel,adc-num-channels = <12>;
202 atmel,adc-startup-time = <40>;
203 atmel,adc-channel-base = <0x50>;
204 atmel,adc-drdy-mask = <0x1000000>;
205 atmel,adc-status-register = <0x30>;
206 atmel,adc-trigger-register = <0xc0>;
207
208 trigger@0 {
209 trigger-name = "external-rising";
210 trigger-value = <0x1>;
211 trigger-external;
212 };
213
214 trigger@1 {
215 trigger-name = "external-falling";
216 trigger-value = <0x2>;
217 trigger-external;
218 };
219
220 trigger@2 {
221 trigger-name = "external-any";
222 trigger-value = <0x3>;
223 trigger-external;
224 };
225
226 trigger@3 {
227 trigger-name = "continuous";
228 trigger-value = <0x6>;
229 };
230 };
193 }; 231 };
194 232
195 nand0: nand@40000000 { 233 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
index 14bc30705099..881bc3987844 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -55,83 +55,101 @@
55 55
56 gpio0: gpio@8012e000 { 56 gpio0: gpio@8012e000 {
57 compatible = "stericsson,db8500-gpio", 57 compatible = "stericsson,db8500-gpio",
58 "stmicroelectronics,nomadik-gpio"; 58 "st,nomadik-gpio";
59 reg = <0x8012e000 0x80>; 59 reg = <0x8012e000 0x80>;
60 interrupts = <0 119 0x4>; 60 interrupts = <0 119 0x4>;
61 supports-sleepmode; 61 supports-sleepmode;
62 gpio-controller; 62 gpio-controller;
63 #gpio-cells = <2>;
64 gpio-bank = <0>;
63 }; 65 };
64 66
65 gpio1: gpio@8012e080 { 67 gpio1: gpio@8012e080 {
66 compatible = "stericsson,db8500-gpio", 68 compatible = "stericsson,db8500-gpio",
67 "stmicroelectronics,nomadik-gpio"; 69 "st,nomadik-gpio";
68 reg = <0x8012e080 0x80>; 70 reg = <0x8012e080 0x80>;
69 interrupts = <0 120 0x4>; 71 interrupts = <0 120 0x4>;
70 supports-sleepmode; 72 supports-sleepmode;
71 gpio-controller; 73 gpio-controller;
74 #gpio-cells = <2>;
75 gpio-bank = <1>;
72 }; 76 };
73 77
74 gpio2: gpio@8000e000 { 78 gpio2: gpio@8000e000 {
75 compatible = "stericsson,db8500-gpio", 79 compatible = "stericsson,db8500-gpio",
76 "stmicroelectronics,nomadik-gpio"; 80 "st,nomadik-gpio";
77 reg = <0x8000e000 0x80>; 81 reg = <0x8000e000 0x80>;
78 interrupts = <0 121 0x4>; 82 interrupts = <0 121 0x4>;
79 supports-sleepmode; 83 supports-sleepmode;
80 gpio-controller; 84 gpio-controller;
85 #gpio-cells = <2>;
86 gpio-bank = <2>;
81 }; 87 };
82 88
83 gpio3: gpio@8000e080 { 89 gpio3: gpio@8000e080 {
84 compatible = "stericsson,db8500-gpio", 90 compatible = "stericsson,db8500-gpio",
85 "stmicroelectronics,nomadik-gpio"; 91 "st,nomadik-gpio";
86 reg = <0x8000e080 0x80>; 92 reg = <0x8000e080 0x80>;
87 interrupts = <0 122 0x4>; 93 interrupts = <0 122 0x4>;
88 supports-sleepmode; 94 supports-sleepmode;
89 gpio-controller; 95 gpio-controller;
96 #gpio-cells = <2>;
97 gpio-bank = <3>;
90 }; 98 };
91 99
92 gpio4: gpio@8000e100 { 100 gpio4: gpio@8000e100 {
93 compatible = "stericsson,db8500-gpio", 101 compatible = "stericsson,db8500-gpio",
94 "stmicroelectronics,nomadik-gpio"; 102 "st,nomadik-gpio";
95 reg = <0x8000e100 0x80>; 103 reg = <0x8000e100 0x80>;
96 interrupts = <0 123 0x4>; 104 interrupts = <0 123 0x4>;
97 supports-sleepmode; 105 supports-sleepmode;
98 gpio-controller; 106 gpio-controller;
107 #gpio-cells = <2>;
108 gpio-bank = <4>;
99 }; 109 };
100 110
101 gpio5: gpio@8000e180 { 111 gpio5: gpio@8000e180 {
102 compatible = "stericsson,db8500-gpio", 112 compatible = "stericsson,db8500-gpio",
103 "stmicroelectronics,nomadik-gpio"; 113 "st,nomadik-gpio";
104 reg = <0x8000e180 0x80>; 114 reg = <0x8000e180 0x80>;
105 interrupts = <0 124 0x4>; 115 interrupts = <0 124 0x4>;
106 supports-sleepmode; 116 supports-sleepmode;
107 gpio-controller; 117 gpio-controller;
118 #gpio-cells = <2>;
119 gpio-bank = <5>;
108 }; 120 };
109 121
110 gpio6: gpio@8011e000 { 122 gpio6: gpio@8011e000 {
111 compatible = "stericsson,db8500-gpio", 123 compatible = "stericsson,db8500-gpio",
112 "stmicroelectronics,nomadik-gpio"; 124 "st,nomadik-gpio";
113 reg = <0x8011e000 0x80>; 125 reg = <0x8011e000 0x80>;
114 interrupts = <0 125 0x4>; 126 interrupts = <0 125 0x4>;
115 supports-sleepmode; 127 supports-sleepmode;
116 gpio-controller; 128 gpio-controller;
129 #gpio-cells = <2>;
130 gpio-bank = <6>;
117 }; 131 };
118 132
119 gpio7: gpio@8011e080 { 133 gpio7: gpio@8011e080 {
120 compatible = "stericsson,db8500-gpio", 134 compatible = "stericsson,db8500-gpio",
121 "stmicroelectronics,nomadik-gpio"; 135 "st,nomadik-gpio";
122 reg = <0x8011e080 0x80>; 136 reg = <0x8011e080 0x80>;
123 interrupts = <0 126 0x4>; 137 interrupts = <0 126 0x4>;
124 supports-sleepmode; 138 supports-sleepmode;
125 gpio-controller; 139 gpio-controller;
140 #gpio-cells = <2>;
141 gpio-bank = <7>;
126 }; 142 };
127 143
128 gpio8: gpio@a03fe000 { 144 gpio8: gpio@a03fe000 {
129 compatible = "stericsson,db8500-gpio", 145 compatible = "stericsson,db8500-gpio",
130 "stmicroelectronics,nomadik-gpio"; 146 "st,nomadik-gpio";
131 reg = <0xa03fe000 0x80>; 147 reg = <0xa03fe000 0x80>;
132 interrupts = <0 127 0x4>; 148 interrupts = <0 127 0x4>;
133 supports-sleepmode; 149 supports-sleepmode;
134 gpio-controller; 150 gpio-controller;
151 #gpio-cells = <2>;
152 gpio-bank = <8>;
135 }; 153 };
136 154
137 usb@a03e0000 { 155 usb@a03e0000 {
@@ -153,7 +171,13 @@
153 reg = <0x80157000 0x1000>; 171 reg = <0x80157000 0x1000>;
154 interrupts = <46 47>; 172 interrupts = <46 47>;
155 #address-cells = <1>; 173 #address-cells = <1>;
156 #size-cells = <0>; 174 #size-cells = <1>;
175 ranges;
176
177 prcmu-timer-4@80157450 {
178 compatible = "stericsson,db8500-prcmu-timer-4";
179 reg = <0x80157450 0xC>;
180 };
157 181
158 ab8500@5 { 182 ab8500@5 {
159 compatible = "stericsson,ab8500"; 183 compatible = "stericsson,ab8500";
@@ -163,7 +187,7 @@
163 }; 187 };
164 188
165 i2c@80004000 { 189 i2c@80004000 {
166 compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c"; 190 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
167 reg = <0x80004000 0x1000>; 191 reg = <0x80004000 0x1000>;
168 interrupts = <0 21 0x4>; 192 interrupts = <0 21 0x4>;
169 #address-cells = <1>; 193 #address-cells = <1>;
@@ -171,7 +195,7 @@
171 }; 195 };
172 196
173 i2c@80122000 { 197 i2c@80122000 {
174 compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c"; 198 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
175 reg = <0x80122000 0x1000>; 199 reg = <0x80122000 0x1000>;
176 interrupts = <0 22 0x4>; 200 interrupts = <0 22 0x4>;
177 #address-cells = <1>; 201 #address-cells = <1>;
@@ -179,7 +203,7 @@
179 }; 203 };
180 204
181 i2c@80128000 { 205 i2c@80128000 {
182 compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c"; 206 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
183 reg = <0x80128000 0x1000>; 207 reg = <0x80128000 0x1000>;
184 interrupts = <0 55 0x4>; 208 interrupts = <0 55 0x4>;
185 #address-cells = <1>; 209 #address-cells = <1>;
@@ -187,7 +211,7 @@
187 }; 211 };
188 212
189 i2c@80110000 { 213 i2c@80110000 {
190 compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c"; 214 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
191 reg = <0x80110000 0x1000>; 215 reg = <0x80110000 0x1000>;
192 interrupts = <0 12 0x4>; 216 interrupts = <0 12 0x4>;
193 #address-cells = <1>; 217 #address-cells = <1>;
@@ -195,7 +219,7 @@
195 }; 219 };
196 220
197 i2c@8012a000 { 221 i2c@8012a000 {
198 compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c"; 222 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
199 reg = <0x8012a000 0x1000>; 223 reg = <0x8012a000 0x1000>;
200 interrupts = <0 51 0x4>; 224 interrupts = <0 51 0x4>;
201 #address-cells = <1>; 225 #address-cells = <1>;
@@ -270,5 +294,14 @@
270 interrupts = <0 100 0x4>; 294 interrupts = <0 100 0x4>;
271 status = "disabled"; 295 status = "disabled";
272 }; 296 };
297
298 external-bus@50000000 {
299 compatible = "simple-bus";
300 reg = <0x50000000 0x4000000>;
301 #address-cells = <1>;
302 #size-cells = <1>;
303 ranges = <0 0x50000000 0x4000000>;
304 status = "disabled";
305 };
273 }; 306 };
274}; 307};
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
new file mode 100644
index 000000000000..297e3baba71c
--- /dev/null
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -0,0 +1,26 @@
1/*
2 * Device Tree Source for the KZM9D board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10/dts-v1/;
11
12/include/ "emev2.dtsi"
13
14/ {
15 model = "EMEV2 KZM9D Board";
16 compatible = "renesas,kzm9d", "renesas,emev2";
17
18 memory {
19 device_type = "memory";
20 reg = <0x40000000 0x8000000>;
21 };
22
23 chosen {
24 bootargs = "console=ttyS1,115200n81";
25 };
26};
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
new file mode 100644
index 000000000000..eb504a6c0f4a
--- /dev/null
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -0,0 +1,63 @@
1/*
2 * Device Tree Source for the EMEV2 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "renesas,emev2";
15 interrupt-parent = <&gic>;
16
17 cpus {
18 cpu@0 {
19 compatible = "arm,cortex-a9";
20 };
21 cpu@1 {
22 compatible = "arm,cortex-a9";
23 };
24 };
25
26 gic: interrupt-controller@e0020000 {
27 compatible = "arm,cortex-a9-gic";
28 interrupt-controller;
29 #interrupt-cells = <3>;
30 reg = <0xe0028000 0x1000>,
31 <0xe0020000 0x0100>;
32 };
33
34 sti@e0180000 {
35 compatible = "renesas,em-sti";
36 reg = <0xe0180000 0x54>;
37 interrupts = <0 125 0>;
38 };
39
40 uart@e1020000 {
41 compatible = "renesas,em-uart";
42 reg = <0xe1020000 0x38>;
43 interrupts = <0 8 0>;
44 };
45
46 uart@e1030000 {
47 compatible = "renesas,em-uart";
48 reg = <0xe1030000 0x38>;
49 interrupts = <0 9 0>;
50 };
51
52 uart@e1040000 {
53 compatible = "renesas,em-uart";
54 reg = <0xe1040000 0x38>;
55 interrupts = <0 10 0>;
56 };
57
58 uart@e1050000 {
59 compatible = "renesas,em-uart";
60 reg = <0xe1050000 0x38>;
61 interrupts = <0 11 0>;
62 };
63};
diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts
new file mode 100644
index 000000000000..1ea9d34460a4
--- /dev/null
+++ b/arch/arm/boot/dts/ethernut5.dts
@@ -0,0 +1,84 @@
1/*
2 * ethernut5.dts - Device Tree file for Ethernut 5 board
3 *
4 * Copyright (C) 2012 egnite GmbH <info@egnite.de>
5 *
6 * Licensed under GPLv2.
7 */
8/dts-v1/;
9/include/ "at91sam9260.dtsi"
10
11/ {
12 model = "Ethernut 5";
13 compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2";
17 };
18
19 memory {
20 reg = <0x20000000 0x08000000>;
21 };
22
23 ahb {
24 apb {
25 dbgu: serial@fffff200 {
26 status = "okay";
27 };
28
29 usart0: serial@fffb0000 {
30 status = "okay";
31 };
32
33 usart1: serial@fffb4000 {
34 status = "okay";
35 };
36
37 macb0: ethernet@fffc4000 {
38 phy-mode = "rmii";
39 status = "okay";
40 };
41
42 usb1: gadget@fffa4000 {
43 atmel,vbus-gpio = <&pioC 5 0>;
44 status = "okay";
45 };
46 };
47
48 nand0: nand@40000000 {
49 nand-bus-width = <8>;
50 nand-ecc-mode = "soft";
51 nand-on-flash-bbt;
52 status = "okay";
53
54 gpios = <0
55 &pioC 14 0
56 0
57 >;
58
59 root@0 {
60 label = "root";
61 reg = <0x0 0x08000000>;
62 };
63
64 data@20000 {
65 label = "data";
66 reg = <0x08000000 0x38000000>;
67 };
68 };
69
70 usb0: ohci@00500000 {
71 num-ports = <2>;
72 status = "okay";
73 };
74 };
75
76 i2c@0 {
77 status = "okay";
78
79 pcf8563@50 {
80 compatible = "nxp,pcf8563";
81 reg = <0x51>;
82 };
83 };
84};
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
new file mode 100644
index 000000000000..70bffa929b65
--- /dev/null
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -0,0 +1,43 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx23.dtsi"
14
15/ {
16 model = "Freescale i.MX23 Evaluation Kit";
17 compatible = "fsl,imx23-evk", "fsl,imx23";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 ssp0: ssp@80010000 {
26 compatible = "fsl,imx23-mmc";
27 pinctrl-names = "default";
28 pinctrl-0 = <&mmc0_8bit_pins_a &mmc0_pins_fixup>;
29 bus-width = <8>;
30 wp-gpios = <&gpio1 30 0>;
31 status = "okay";
32 };
33 };
34
35 apbx@80040000 {
36 duart: serial@80070000 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&duart_pins_a>;
39 status = "okay";
40 };
41 };
42 };
43};
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
new file mode 100644
index 000000000000..8c5f9994f3fc
--- /dev/null
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -0,0 +1,295 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 };
22
23 cpus {
24 cpu@0 {
25 compatible = "arm,arm926ejs";
26 };
27 };
28
29 apb@80000000 {
30 compatible = "simple-bus";
31 #address-cells = <1>;
32 #size-cells = <1>;
33 reg = <0x80000000 0x80000>;
34 ranges;
35
36 apbh@80000000 {
37 compatible = "simple-bus";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x80000000 0x40000>;
41 ranges;
42
43 icoll: interrupt-controller@80000000 {
44 compatible = "fsl,imx23-icoll", "fsl,mxs-icoll";
45 interrupt-controller;
46 #interrupt-cells = <1>;
47 reg = <0x80000000 0x2000>;
48 };
49
50 dma-apbh@80004000 {
51 compatible = "fsl,imx23-dma-apbh";
52 reg = <0x80004000 2000>;
53 };
54
55 ecc@80008000 {
56 reg = <0x80008000 2000>;
57 status = "disabled";
58 };
59
60 bch@8000a000 {
61 reg = <0x8000a000 2000>;
62 status = "disabled";
63 };
64
65 gpmi@8000c000 {
66 reg = <0x8000c000 2000>;
67 status = "disabled";
68 };
69
70 ssp0: ssp@80010000 {
71 reg = <0x80010000 2000>;
72 interrupts = <15 14>;
73 fsl,ssp-dma-channel = <1>;
74 status = "disabled";
75 };
76
77 etm@80014000 {
78 reg = <0x80014000 2000>;
79 status = "disabled";
80 };
81
82 pinctrl@80018000 {
83 #address-cells = <1>;
84 #size-cells = <0>;
85 compatible = "fsl,imx23-pinctrl", "simple-bus";
86 reg = <0x80018000 2000>;
87
88 gpio0: gpio@0 {
89 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
90 interrupts = <16>;
91 gpio-controller;
92 #gpio-cells = <2>;
93 interrupt-controller;
94 #interrupt-cells = <2>;
95 };
96
97 gpio1: gpio@1 {
98 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
99 interrupts = <17>;
100 gpio-controller;
101 #gpio-cells = <2>;
102 interrupt-controller;
103 #interrupt-cells = <2>;
104 };
105
106 gpio2: gpio@2 {
107 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
108 interrupts = <18>;
109 gpio-controller;
110 #gpio-cells = <2>;
111 interrupt-controller;
112 #interrupt-cells = <2>;
113 };
114
115 duart_pins_a: duart@0 {
116 reg = <0>;
117 fsl,pinmux-ids = <0x11a2 0x11b2>;
118 fsl,drive-strength = <0>;
119 fsl,voltage = <1>;
120 fsl,pull-up = <0>;
121 };
122
123 mmc0_8bit_pins_a: mmc0-8bit@0 {
124 reg = <0>;
125 fsl,pinmux-ids = <0x2020 0x2030 0x2040
126 0x2050 0x0082 0x0092 0x00a2
127 0x00b2 0x2000 0x2010 0x2060>;
128 fsl,drive-strength = <1>;
129 fsl,voltage = <1>;
130 fsl,pull-up = <1>;
131 };
132
133 mmc0_pins_fixup: mmc0-pins-fixup {
134 fsl,pinmux-ids = <0x2010 0x2060>;
135 fsl,pull-up = <0>;
136 };
137 };
138
139 digctl@8001c000 {
140 reg = <0x8001c000 2000>;
141 status = "disabled";
142 };
143
144 emi@80020000 {
145 reg = <0x80020000 2000>;
146 status = "disabled";
147 };
148
149 dma-apbx@80024000 {
150 compatible = "fsl,imx23-dma-apbx";
151 reg = <0x80024000 2000>;
152 };
153
154 dcp@80028000 {
155 reg = <0x80028000 2000>;
156 status = "disabled";
157 };
158
159 pxp@8002a000 {
160 reg = <0x8002a000 2000>;
161 status = "disabled";
162 };
163
164 ocotp@8002c000 {
165 reg = <0x8002c000 2000>;
166 status = "disabled";
167 };
168
169 axi-ahb@8002e000 {
170 reg = <0x8002e000 2000>;
171 status = "disabled";
172 };
173
174 lcdif@80030000 {
175 reg = <0x80030000 2000>;
176 status = "disabled";
177 };
178
179 ssp1: ssp@80034000 {
180 reg = <0x80034000 2000>;
181 interrupts = <2 20>;
182 fsl,ssp-dma-channel = <2>;
183 status = "disabled";
184 };
185
186 tvenc@80038000 {
187 reg = <0x80038000 2000>;
188 status = "disabled";
189 };
190 };
191
192 apbx@80040000 {
193 compatible = "simple-bus";
194 #address-cells = <1>;
195 #size-cells = <1>;
196 reg = <0x80040000 0x40000>;
197 ranges;
198
199 clkctl@80040000 {
200 reg = <0x80040000 2000>;
201 status = "disabled";
202 };
203
204 saif0: saif@80042000 {
205 reg = <0x80042000 2000>;
206 status = "disabled";
207 };
208
209 power@80044000 {
210 reg = <0x80044000 2000>;
211 status = "disabled";
212 };
213
214 saif1: saif@80046000 {
215 reg = <0x80046000 2000>;
216 status = "disabled";
217 };
218
219 audio-out@80048000 {
220 reg = <0x80048000 2000>;
221 status = "disabled";
222 };
223
224 audio-in@8004c000 {
225 reg = <0x8004c000 2000>;
226 status = "disabled";
227 };
228
229 lradc@80050000 {
230 reg = <0x80050000 2000>;
231 status = "disabled";
232 };
233
234 spdif@80054000 {
235 reg = <0x80054000 2000>;
236 status = "disabled";
237 };
238
239 i2c@80058000 {
240 reg = <0x80058000 2000>;
241 status = "disabled";
242 };
243
244 rtc@8005c000 {
245 reg = <0x8005c000 2000>;
246 status = "disabled";
247 };
248
249 pwm@80064000 {
250 reg = <0x80064000 2000>;
251 status = "disabled";
252 };
253
254 timrot@80068000 {
255 reg = <0x80068000 2000>;
256 status = "disabled";
257 };
258
259 auart0: serial@8006c000 {
260 reg = <0x8006c000 0x2000>;
261 status = "disabled";
262 };
263
264 auart1: serial@8006e000 {
265 reg = <0x8006e000 0x2000>;
266 status = "disabled";
267 };
268
269 duart: serial@80070000 {
270 compatible = "arm,pl011", "arm,primecell";
271 reg = <0x80070000 0x2000>;
272 interrupts = <0>;
273 status = "disabled";
274 };
275
276 usbphy@8007c000 {
277 reg = <0x8007c000 0x2000>;
278 status = "disabled";
279 };
280 };
281 };
282
283 ahb@80080000 {
284 compatible = "simple-bus";
285 #address-cells = <1>;
286 #size-cells = <1>;
287 reg = <0x80080000 0x80000>;
288 ranges;
289
290 usbctrl@80080000 {
291 reg = <0x80080000 0x10000>;
292 status = "disabled";
293 };
294 };
295};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index a51a08fc2af9..2b0ff60247a4 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -27,22 +27,22 @@
27 status = "okay"; 27 status = "okay";
28 }; 28 };
29 29
30 uart@1000a000 { 30 serial@1000a000 {
31 fsl,uart-has-rtscts; 31 fsl,uart-has-rtscts;
32 status = "okay"; 32 status = "okay";
33 }; 33 };
34 34
35 uart@1000b000 { 35 serial@1000b000 {
36 fsl,uart-has-rtscts; 36 fsl,uart-has-rtscts;
37 status = "okay"; 37 status = "okay";
38 }; 38 };
39 39
40 uart@1000c000 { 40 serial@1000c000 {
41 fsl,uart-has-rtscts; 41 fsl,uart-has-rtscts;
42 status = "okay"; 42 status = "okay";
43 }; 43 };
44 44
45 fec@1002b000 { 45 ethernet@1002b000 {
46 status = "okay"; 46 status = "okay";
47 }; 47 };
48 48
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index bc5e7d5ddd54..2b1a166d41f9 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -59,28 +59,28 @@
59 status = "disabled"; 59 status = "disabled";
60 }; 60 };
61 61
62 uart1: uart@1000a000 { 62 uart1: serial@1000a000 {
63 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 63 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
64 reg = <0x1000a000 0x1000>; 64 reg = <0x1000a000 0x1000>;
65 interrupts = <20>; 65 interrupts = <20>;
66 status = "disabled"; 66 status = "disabled";
67 }; 67 };
68 68
69 uart2: uart@1000b000 { 69 uart2: serial@1000b000 {
70 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 70 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
71 reg = <0x1000b000 0x1000>; 71 reg = <0x1000b000 0x1000>;
72 interrupts = <19>; 72 interrupts = <19>;
73 status = "disabled"; 73 status = "disabled";
74 }; 74 };
75 75
76 uart3: uart@1000c000 { 76 uart3: serial@1000c000 {
77 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 77 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
78 reg = <0x1000c000 0x1000>; 78 reg = <0x1000c000 0x1000>;
79 interrupts = <18>; 79 interrupts = <18>;
80 status = "disabled"; 80 status = "disabled";
81 }; 81 };
82 82
83 uart4: uart@1000d000 { 83 uart4: serial@1000d000 {
84 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 84 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
85 reg = <0x1000d000 0x1000>; 85 reg = <0x1000d000 0x1000>;
86 interrupts = <17>; 86 interrupts = <17>;
@@ -183,14 +183,14 @@
183 status = "disabled"; 183 status = "disabled";
184 }; 184 };
185 185
186 uart5: uart@1001b000 { 186 uart5: serial@1001b000 {
187 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 187 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
188 reg = <0x1001b000 0x1000>; 188 reg = <0x1001b000 0x1000>;
189 interrupts = <49>; 189 interrupts = <49>;
190 status = "disabled"; 190 status = "disabled";
191 }; 191 };
192 192
193 uart6: uart@1001c000 { 193 uart6: serial@1001c000 {
194 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 194 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
195 reg = <0x1001c000 0x1000>; 195 reg = <0x1001c000 0x1000>;
196 interrupts = <48>; 196 interrupts = <48>;
@@ -206,7 +206,7 @@
206 status = "disabled"; 206 status = "disabled";
207 }; 207 };
208 208
209 fec: fec@1002b000 { 209 fec: ethernet@1002b000 {
210 compatible = "fsl,imx27-fec"; 210 compatible = "fsl,imx27-fec";
211 reg = <0x1002b000 0x4000>; 211 reg = <0x1002b000 0x4000>;
212 interrupts = <50>; 212 interrupts = <50>;
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
new file mode 100644
index 000000000000..ee520a529cb4
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -0,0 +1,114 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx28.dtsi"
14
15/ {
16 model = "Freescale i.MX28 Evaluation Kit";
17 compatible = "fsl,imx28-evk", "fsl,imx28";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 ssp0: ssp@80010000 {
26 compatible = "fsl,imx28-mmc";
27 pinctrl-names = "default";
28 pinctrl-0 = <&mmc0_8bit_pins_a
29 &mmc0_cd_cfg &mmc0_sck_cfg>;
30 bus-width = <8>;
31 wp-gpios = <&gpio2 12 0>;
32 status = "okay";
33 };
34
35 ssp1: ssp@80012000 {
36 compatible = "fsl,imx28-mmc";
37 bus-width = <8>;
38 wp-gpios = <&gpio0 28 0>;
39 status = "okay";
40 };
41 };
42
43 apbx@80040000 {
44 saif0: saif@80042000 {
45 pinctrl-names = "default";
46 pinctrl-0 = <&saif0_pins_a>;
47 status = "okay";
48 };
49
50 saif1: saif@80046000 {
51 pinctrl-names = "default";
52 pinctrl-0 = <&saif1_pins_a>;
53 fsl,saif-master = <&saif0>;
54 status = "okay";
55 };
56
57 i2c0: i2c@80058000 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&i2c0_pins_a>;
60 status = "okay";
61
62 sgtl5000: codec@0a {
63 compatible = "fsl,sgtl5000";
64 reg = <0x0a>;
65 VDDA-supply = <&reg_3p3v>;
66 VDDIO-supply = <&reg_3p3v>;
67
68 };
69 };
70
71 duart: serial@80074000 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&duart_pins_a>;
74 status = "okay";
75 };
76 };
77 };
78
79 ahb@80080000 {
80 mac0: ethernet@800f0000 {
81 phy-mode = "rmii";
82 pinctrl-names = "default";
83 pinctrl-0 = <&mac0_pins_a>;
84 status = "okay";
85 };
86
87 mac1: ethernet@800f4000 {
88 phy-mode = "rmii";
89 pinctrl-names = "default";
90 pinctrl-0 = <&mac1_pins_a>;
91 status = "okay";
92 };
93 };
94
95 regulators {
96 compatible = "simple-bus";
97
98 reg_3p3v: 3p3v {
99 compatible = "regulator-fixed";
100 regulator-name = "3P3V";
101 regulator-min-microvolt = <3300000>;
102 regulator-max-microvolt = <3300000>;
103 regulator-always-on;
104 };
105 };
106
107 sound {
108 compatible = "fsl,imx28-evk-sgtl5000",
109 "fsl,mxs-audio-sgtl5000";
110 model = "imx28-evk-sgtl5000";
111 saif-controllers = <&saif0 &saif1>;
112 audio-codec = <&sgtl5000>;
113 };
114};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
new file mode 100644
index 000000000000..4634cb861a59
--- /dev/null
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -0,0 +1,497 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
23 saif0 = &saif0;
24 saif1 = &saif1;
25 };
26
27 cpus {
28 cpu@0 {
29 compatible = "arm,arm926ejs";
30 };
31 };
32
33 apb@80000000 {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
37 reg = <0x80000000 0x80000>;
38 ranges;
39
40 apbh@80000000 {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 reg = <0x80000000 0x3c900>;
45 ranges;
46
47 icoll: interrupt-controller@80000000 {
48 compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
49 interrupt-controller;
50 #interrupt-cells = <1>;
51 reg = <0x80000000 0x2000>;
52 };
53
54 hsadc@80002000 {
55 reg = <0x80002000 2000>;
56 interrupts = <13 87>;
57 status = "disabled";
58 };
59
60 dma-apbh@80004000 {
61 compatible = "fsl,imx28-dma-apbh";
62 reg = <0x80004000 2000>;
63 };
64
65 perfmon@80006000 {
66 reg = <0x80006000 800>;
67 interrupts = <27>;
68 status = "disabled";
69 };
70
71 bch@8000a000 {
72 reg = <0x8000a000 2000>;
73 interrupts = <41>;
74 status = "disabled";
75 };
76
77 gpmi@8000c000 {
78 reg = <0x8000c000 2000>;
79 interrupts = <42 88>;
80 status = "disabled";
81 };
82
83 ssp0: ssp@80010000 {
84 reg = <0x80010000 2000>;
85 interrupts = <96 82>;
86 fsl,ssp-dma-channel = <0>;
87 status = "disabled";
88 };
89
90 ssp1: ssp@80012000 {
91 reg = <0x80012000 2000>;
92 interrupts = <97 83>;
93 fsl,ssp-dma-channel = <1>;
94 status = "disabled";
95 };
96
97 ssp2: ssp@80014000 {
98 reg = <0x80014000 2000>;
99 interrupts = <98 84>;
100 fsl,ssp-dma-channel = <2>;
101 status = "disabled";
102 };
103
104 ssp3: ssp@80016000 {
105 reg = <0x80016000 2000>;
106 interrupts = <99 85>;
107 fsl,ssp-dma-channel = <3>;
108 status = "disabled";
109 };
110
111 pinctrl@80018000 {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 compatible = "fsl,imx28-pinctrl", "simple-bus";
115 reg = <0x80018000 2000>;
116
117 gpio0: gpio@0 {
118 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
119 interrupts = <127>;
120 gpio-controller;
121 #gpio-cells = <2>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 };
125
126 gpio1: gpio@1 {
127 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
128 interrupts = <126>;
129 gpio-controller;
130 #gpio-cells = <2>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
133 };
134
135 gpio2: gpio@2 {
136 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
137 interrupts = <125>;
138 gpio-controller;
139 #gpio-cells = <2>;
140 interrupt-controller;
141 #interrupt-cells = <2>;
142 };
143
144 gpio3: gpio@3 {
145 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
146 interrupts = <124>;
147 gpio-controller;
148 #gpio-cells = <2>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
151 };
152
153 gpio4: gpio@4 {
154 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
155 interrupts = <123>;
156 gpio-controller;
157 #gpio-cells = <2>;
158 interrupt-controller;
159 #interrupt-cells = <2>;
160 };
161
162 duart_pins_a: duart@0 {
163 reg = <0>;
164 fsl,pinmux-ids = <0x3102 0x3112>;
165 fsl,drive-strength = <0>;
166 fsl,voltage = <1>;
167 fsl,pull-up = <0>;
168 };
169
170 mac0_pins_a: mac0@0 {
171 reg = <0>;
172 fsl,pinmux-ids = <0x4000 0x4010 0x4020
173 0x4030 0x4040 0x4060 0x4070
174 0x4080 0x4100>;
175 fsl,drive-strength = <1>;
176 fsl,voltage = <1>;
177 fsl,pull-up = <1>;
178 };
179
180 mac1_pins_a: mac1@0 {
181 reg = <0>;
182 fsl,pinmux-ids = <0x40f1 0x4091 0x40a1
183 0x40e1 0x40b1 0x40c1>;
184 fsl,drive-strength = <1>;
185 fsl,voltage = <1>;
186 fsl,pull-up = <1>;
187 };
188
189 mmc0_8bit_pins_a: mmc0-8bit@0 {
190 reg = <0>;
191 fsl,pinmux-ids = <0x2000 0x2010 0x2020
192 0x2030 0x2040 0x2050 0x2060
193 0x2070 0x2080 0x2090 0x20a0>;
194 fsl,drive-strength = <1>;
195 fsl,voltage = <1>;
196 fsl,pull-up = <1>;
197 };
198
199 mmc0_cd_cfg: mmc0-cd-cfg {
200 fsl,pinmux-ids = <0x2090>;
201 fsl,pull-up = <0>;
202 };
203
204 mmc0_sck_cfg: mmc0-sck-cfg {
205 fsl,pinmux-ids = <0x20a0>;
206 fsl,drive-strength = <2>;
207 fsl,pull-up = <0>;
208 };
209
210 i2c0_pins_a: i2c0@0 {
211 reg = <0>;
212 fsl,pinmux-ids = <0x3180 0x3190>;
213 fsl,drive-strength = <1>;
214 fsl,voltage = <1>;
215 fsl,pull-up = <1>;
216 };
217
218 saif0_pins_a: saif0@0 {
219 reg = <0>;
220 fsl,pinmux-ids =
221 <0x3140 0x3150 0x3160 0x3170>;
222 fsl,drive-strength = <2>;
223 fsl,voltage = <1>;
224 fsl,pull-up = <1>;
225 };
226
227 saif1_pins_a: saif1@0 {
228 reg = <0>;
229 fsl,pinmux-ids = <0x31a0>;
230 fsl,drive-strength = <2>;
231 fsl,voltage = <1>;
232 fsl,pull-up = <1>;
233 };
234 };
235
236 digctl@8001c000 {
237 reg = <0x8001c000 2000>;
238 interrupts = <89>;
239 status = "disabled";
240 };
241
242 etm@80022000 {
243 reg = <0x80022000 2000>;
244 status = "disabled";
245 };
246
247 dma-apbx@80024000 {
248 compatible = "fsl,imx28-dma-apbx";
249 reg = <0x80024000 2000>;
250 };
251
252 dcp@80028000 {
253 reg = <0x80028000 2000>;
254 interrupts = <52 53 54>;
255 status = "disabled";
256 };
257
258 pxp@8002a000 {
259 reg = <0x8002a000 2000>;
260 interrupts = <39>;
261 status = "disabled";
262 };
263
264 ocotp@8002c000 {
265 reg = <0x8002c000 2000>;
266 status = "disabled";
267 };
268
269 axi-ahb@8002e000 {
270 reg = <0x8002e000 2000>;
271 status = "disabled";
272 };
273
274 lcdif@80030000 {
275 reg = <0x80030000 2000>;
276 interrupts = <38 86>;
277 status = "disabled";
278 };
279
280 can0: can@80032000 {
281 reg = <0x80032000 2000>;
282 interrupts = <8>;
283 status = "disabled";
284 };
285
286 can1: can@80034000 {
287 reg = <0x80034000 2000>;
288 interrupts = <9>;
289 status = "disabled";
290 };
291
292 simdbg@8003c000 {
293 reg = <0x8003c000 200>;
294 status = "disabled";
295 };
296
297 simgpmisel@8003c200 {
298 reg = <0x8003c200 100>;
299 status = "disabled";
300 };
301
302 simsspsel@8003c300 {
303 reg = <0x8003c300 100>;
304 status = "disabled";
305 };
306
307 simmemsel@8003c400 {
308 reg = <0x8003c400 100>;
309 status = "disabled";
310 };
311
312 gpiomon@8003c500 {
313 reg = <0x8003c500 100>;
314 status = "disabled";
315 };
316
317 simenet@8003c700 {
318 reg = <0x8003c700 100>;
319 status = "disabled";
320 };
321
322 armjtag@8003c800 {
323 reg = <0x8003c800 100>;
324 status = "disabled";
325 };
326 };
327
328 apbx@80040000 {
329 compatible = "simple-bus";
330 #address-cells = <1>;
331 #size-cells = <1>;
332 reg = <0x80040000 0x40000>;
333 ranges;
334
335 clkctl@80040000 {
336 reg = <0x80040000 2000>;
337 status = "disabled";
338 };
339
340 saif0: saif@80042000 {
341 compatible = "fsl,imx28-saif";
342 reg = <0x80042000 2000>;
343 interrupts = <59 80>;
344 fsl,saif-dma-channel = <4>;
345 status = "disabled";
346 };
347
348 power@80044000 {
349 reg = <0x80044000 2000>;
350 status = "disabled";
351 };
352
353 saif1: saif@80046000 {
354 compatible = "fsl,imx28-saif";
355 reg = <0x80046000 2000>;
356 interrupts = <58 81>;
357 fsl,saif-dma-channel = <5>;
358 status = "disabled";
359 };
360
361 lradc@80050000 {
362 reg = <0x80050000 2000>;
363 status = "disabled";
364 };
365
366 spdif@80054000 {
367 reg = <0x80054000 2000>;
368 interrupts = <45 66>;
369 status = "disabled";
370 };
371
372 rtc@80056000 {
373 reg = <0x80056000 2000>;
374 interrupts = <28 29>;
375 status = "disabled";
376 };
377
378 i2c0: i2c@80058000 {
379 #address-cells = <1>;
380 #size-cells = <0>;
381 compatible = "fsl,imx28-i2c";
382 reg = <0x80058000 2000>;
383 interrupts = <111 68>;
384 status = "disabled";
385 };
386
387 i2c1: i2c@8005a000 {
388 #address-cells = <1>;
389 #size-cells = <0>;
390 compatible = "fsl,imx28-i2c";
391 reg = <0x8005a000 2000>;
392 interrupts = <110 69>;
393 status = "disabled";
394 };
395
396 pwm@80064000 {
397 reg = <0x80064000 2000>;
398 status = "disabled";
399 };
400
401 timrot@80068000 {
402 reg = <0x80068000 2000>;
403 status = "disabled";
404 };
405
406 auart0: serial@8006a000 {
407 reg = <0x8006a000 0x2000>;
408 interrupts = <112 70 71>;
409 status = "disabled";
410 };
411
412 auart1: serial@8006c000 {
413 reg = <0x8006c000 0x2000>;
414 interrupts = <113 72 73>;
415 status = "disabled";
416 };
417
418 auart2: serial@8006e000 {
419 reg = <0x8006e000 0x2000>;
420 interrupts = <114 74 75>;
421 status = "disabled";
422 };
423
424 auart3: serial@80070000 {
425 reg = <0x80070000 0x2000>;
426 interrupts = <115 76 77>;
427 status = "disabled";
428 };
429
430 auart4: serial@80072000 {
431 reg = <0x80072000 0x2000>;
432 interrupts = <116 78 79>;
433 status = "disabled";
434 };
435
436 duart: serial@80074000 {
437 compatible = "arm,pl011", "arm,primecell";
438 reg = <0x80074000 0x1000>;
439 interrupts = <47>;
440 status = "disabled";
441 };
442
443 usbphy0: usbphy@8007c000 {
444 reg = <0x8007c000 0x2000>;
445 status = "disabled";
446 };
447
448 usbphy1: usbphy@8007e000 {
449 reg = <0x8007e000 0x2000>;
450 status = "disabled";
451 };
452 };
453 };
454
455 ahb@80080000 {
456 compatible = "simple-bus";
457 #address-cells = <1>;
458 #size-cells = <1>;
459 reg = <0x80080000 0x80000>;
460 ranges;
461
462 usbctrl0: usbctrl@80080000 {
463 reg = <0x80080000 0x10000>;
464 status = "disabled";
465 };
466
467 usbctrl1: usbctrl@80090000 {
468 reg = <0x80090000 0x10000>;
469 status = "disabled";
470 };
471
472 dflpt@800c0000 {
473 reg = <0x800c0000 0x10000>;
474 status = "disabled";
475 };
476
477 mac0: ethernet@800f0000 {
478 compatible = "fsl,imx28-fec";
479 reg = <0x800f0000 0x4000>;
480 interrupts = <101>;
481 status = "disabled";
482 };
483
484 mac1: ethernet@800f4000 {
485 compatible = "fsl,imx28-fec";
486 reg = <0x800f4000 0x4000>;
487 interrupts = <102>;
488 status = "disabled";
489 };
490
491 switch@800f8000 {
492 reg = <0x800f8000 0x8000>;
493 status = "disabled";
494 };
495
496 };
497};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 9949e6060dee..de065b5976e6 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -17,10 +17,6 @@
17 model = "Freescale i.MX51 Babbage Board"; 17 model = "Freescale i.MX51 Babbage Board";
18 compatible = "fsl,imx51-babbage", "fsl,imx51"; 18 compatible = "fsl,imx51-babbage", "fsl,imx51";
19 19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory { 20 memory {
25 reg = <0x90000000 0x20000000>; 21 reg = <0x90000000 0x20000000>;
26 }; 22 };
@@ -40,7 +36,7 @@
40 status = "okay"; 36 status = "okay";
41 }; 37 };
42 38
43 uart3: uart@7000c000 { 39 uart3: serial@7000c000 {
44 fsl,uart-has-rtscts; 40 fsl,uart-has-rtscts;
45 status = "okay"; 41 status = "okay";
46 }; 42 };
@@ -166,6 +162,11 @@
166 }; 162 };
167 }; 163 };
168 }; 164 };
165
166 ssi2: ssi@70014000 {
167 fsl,mode = "i2s-slave";
168 status = "okay";
169 };
169 }; 170 };
170 171
171 wdog@73f98000 { /* WDOG1 */ 172 wdog@73f98000 { /* WDOG1 */
@@ -177,12 +178,12 @@
177 reg = <0x73fa8000 0x4000>; 178 reg = <0x73fa8000 0x4000>;
178 }; 179 };
179 180
180 uart1: uart@73fbc000 { 181 uart1: serial@73fbc000 {
181 fsl,uart-has-rtscts; 182 fsl,uart-has-rtscts;
182 status = "okay"; 183 status = "okay";
183 }; 184 };
184 185
185 uart2: uart@73fc0000 { 186 uart2: serial@73fc0000 {
186 status = "okay"; 187 status = "okay";
187 }; 188 };
188 }; 189 };
@@ -195,13 +196,20 @@
195 i2c@83fc4000 { /* I2C2 */ 196 i2c@83fc4000 { /* I2C2 */
196 status = "okay"; 197 status = "okay";
197 198
198 codec: sgtl5000@0a { 199 sgtl5000: codec@0a {
199 compatible = "fsl,sgtl5000"; 200 compatible = "fsl,sgtl5000";
200 reg = <0x0a>; 201 reg = <0x0a>;
202 clock-frequency = <26000000>;
203 VDDA-supply = <&vdig_reg>;
204 VDDIO-supply = <&vvideo_reg>;
201 }; 205 };
202 }; 206 };
203 207
204 fec@83fec000 { 208 audmux@83fd0000 {
209 status = "okay";
210 };
211
212 ethernet@83fec000 {
205 phy-mode = "mii"; 213 phy-mode = "mii";
206 status = "okay"; 214 status = "okay";
207 }; 215 };
@@ -218,4 +226,18 @@
218 gpio-key,wakeup; 226 gpio-key,wakeup;
219 }; 227 };
220 }; 228 };
229
230 sound {
231 compatible = "fsl,imx51-babbage-sgtl5000",
232 "fsl,imx-audio-sgtl5000";
233 model = "imx51-babbage-sgtl5000";
234 ssi-controller = <&ssi2>;
235 audio-codec = <&sgtl5000>;
236 audio-routing =
237 "MIC_IN", "Mic Jack",
238 "Mic Jack", "Mic Bias",
239 "Headphone Jack", "HP_OUT";
240 mux-int-port = <2>;
241 mux-ext-port = <3>;
242 };
221}; 243};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 6663986fe1c8..bfa65abe8ef2 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -86,7 +86,7 @@
86 status = "disabled"; 86 status = "disabled";
87 }; 87 };
88 88
89 uart3: uart@7000c000 { 89 uart3: serial@7000c000 {
90 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 90 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
91 reg = <0x7000c000 0x4000>; 91 reg = <0x7000c000 0x4000>;
92 interrupts = <33>; 92 interrupts = <33>;
@@ -102,6 +102,15 @@
102 status = "disabled"; 102 status = "disabled";
103 }; 103 };
104 104
105 ssi2: ssi@70014000 {
106 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
107 reg = <0x70014000 0x4000>;
108 interrupts = <30>;
109 fsl,fifo-depth = <15>;
110 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
111 status = "disabled";
112 };
113
105 esdhc@70020000 { /* ESDHC3 */ 114 esdhc@70020000 { /* ESDHC3 */
106 compatible = "fsl,imx51-esdhc"; 115 compatible = "fsl,imx51-esdhc";
107 reg = <0x70020000 0x4000>; 116 reg = <0x70020000 0x4000>;
@@ -171,14 +180,14 @@
171 status = "disabled"; 180 status = "disabled";
172 }; 181 };
173 182
174 uart1: uart@73fbc000 { 183 uart1: serial@73fbc000 {
175 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 184 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
176 reg = <0x73fbc000 0x4000>; 185 reg = <0x73fbc000 0x4000>;
177 interrupts = <31>; 186 interrupts = <31>;
178 status = "disabled"; 187 status = "disabled";
179 }; 188 };
180 189
181 uart2: uart@73fc0000 { 190 uart2: serial@73fc0000 {
182 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 191 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
183 reg = <0x73fc0000 0x4000>; 192 reg = <0x73fc0000 0x4000>;
184 interrupts = <32>; 193 interrupts = <32>;
@@ -235,7 +244,31 @@
235 status = "disabled"; 244 status = "disabled";
236 }; 245 };
237 246
238 fec@83fec000 { 247 ssi1: ssi@83fcc000 {
248 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
249 reg = <0x83fcc000 0x4000>;
250 interrupts = <29>;
251 fsl,fifo-depth = <15>;
252 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
253 status = "disabled";
254 };
255
256 audmux@83fd0000 {
257 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
258 reg = <0x83fd0000 0x4000>;
259 status = "disabled";
260 };
261
262 ssi3: ssi@83fe8000 {
263 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
264 reg = <0x83fe8000 0x4000>;
265 interrupts = <96>;
266 fsl,fifo-depth = <15>;
267 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
268 status = "disabled";
269 };
270
271 ethernet@83fec000 {
239 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 272 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
240 reg = <0x83fec000 0x4000>; 273 reg = <0x83fec000 0x4000>;
241 interrupts = <87>; 274 interrupts = <87>;
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 2dccce46ed81..5b8eafcdbeec 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -17,10 +17,6 @@
17 model = "Freescale i.MX53 Automotive Reference Design Board"; 17 model = "Freescale i.MX53 Automotive Reference Design Board";
18 compatible = "fsl,imx53-ard", "fsl,imx53"; 18 compatible = "fsl,imx53-ard", "fsl,imx53";
19 19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory { 20 memory {
25 reg = <0x70000000 0x40000000>; 21 reg = <0x70000000 0x40000000>;
26 }; 22 };
@@ -44,7 +40,7 @@
44 reg = <0x53fa8000 0x4000>; 40 reg = <0x53fa8000 0x4000>;
45 }; 41 };
46 42
47 uart1: uart@53fbc000 { 43 uart1: serial@53fbc000 {
48 status = "okay"; 44 status = "okay";
49 }; 45 };
50 }; 46 };
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 5bac4aa4800b..9c798034675e 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -17,10 +17,6 @@
17 model = "Freescale i.MX53 Evaluation Kit"; 17 model = "Freescale i.MX53 Evaluation Kit";
18 compatible = "fsl,imx53-evk", "fsl,imx53"; 18 compatible = "fsl,imx53-evk", "fsl,imx53";
19 19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory { 20 memory {
25 reg = <0x70000000 0x80000000>; 21 reg = <0x70000000 0x80000000>;
26 }; 22 };
@@ -75,7 +71,7 @@
75 reg = <0x53fa8000 0x4000>; 71 reg = <0x53fa8000 0x4000>;
76 }; 72 };
77 73
78 uart1: uart@53fbc000 { 74 uart1: serial@53fbc000 {
79 status = "okay"; 75 status = "okay";
80 }; 76 };
81 }; 77 };
@@ -99,7 +95,7 @@
99 }; 95 };
100 }; 96 };
101 97
102 fec@63fec000 { 98 ethernet@63fec000 {
103 phy-mode = "rmii"; 99 phy-mode = "rmii";
104 phy-reset-gpios = <&gpio7 6 0>; 100 phy-reset-gpios = <&gpio7 6 0>;
105 status = "okay"; 101 status = "okay";
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 5c57c8672c36..2d803a9a6949 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -17,10 +17,6 @@
17 model = "Freescale i.MX53 Quick Start Board"; 17 model = "Freescale i.MX53 Quick Start Board";
18 compatible = "fsl,imx53-qsb", "fsl,imx53"; 18 compatible = "fsl,imx53-qsb", "fsl,imx53";
19 19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory { 20 memory {
25 reg = <0x70000000 0x40000000>; 21 reg = <0x70000000 0x40000000>;
26 }; 22 };
@@ -33,6 +29,11 @@
33 status = "okay"; 29 status = "okay";
34 }; 30 };
35 31
32 ssi2: ssi@50014000 {
33 fsl,mode = "i2s-slave";
34 status = "okay";
35 };
36
36 esdhc@50020000 { /* ESDHC3 */ 37 esdhc@50020000 { /* ESDHC3 */
37 cd-gpios = <&gpio3 11 0>; 38 cd-gpios = <&gpio3 11 0>;
38 wp-gpios = <&gpio3 12 0>; 39 wp-gpios = <&gpio3 12 0>;
@@ -49,7 +50,7 @@
49 reg = <0x53fa8000 0x4000>; 50 reg = <0x53fa8000 0x4000>;
50 }; 51 };
51 52
52 uart1: uart@53fbc000 { 53 uart1: serial@53fbc000 {
53 status = "okay"; 54 status = "okay";
54 }; 55 };
55 }; 56 };
@@ -62,9 +63,11 @@
62 i2c@63fc4000 { /* I2C2 */ 63 i2c@63fc4000 { /* I2C2 */
63 status = "okay"; 64 status = "okay";
64 65
65 codec: sgtl5000@0a { 66 sgtl5000: codec@0a {
66 compatible = "fsl,sgtl5000"; 67 compatible = "fsl,sgtl5000";
67 reg = <0x0a>; 68 reg = <0x0a>;
69 VDDA-supply = <&reg_3p2v>;
70 VDDIO-supply = <&reg_3p2v>;
68 }; 71 };
69 }; 72 };
70 73
@@ -77,12 +80,88 @@
77 }; 80 };
78 81
79 pmic: dialog@48 { 82 pmic: dialog@48 {
80 compatible = "dialog,da9053", "dialog,da9052"; 83 compatible = "dlg,da9053-aa", "dlg,da9052";
81 reg = <0x48>; 84 reg = <0x48>;
85
86 regulators {
87 buck0 {
88 regulator-min-microvolt = <500000>;
89 regulator-max-microvolt = <2075000>;
90 };
91
92 buck1 {
93 regulator-min-microvolt = <500000>;
94 regulator-max-microvolt = <2075000>;
95 };
96
97 buck2 {
98 regulator-min-microvolt = <925000>;
99 regulator-max-microvolt = <2500000>;
100 };
101
102 buck3 {
103 regulator-min-microvolt = <925000>;
104 regulator-max-microvolt = <2500000>;
105 };
106
107 ldo4 {
108 regulator-min-microvolt = <600000>;
109 regulator-max-microvolt = <1800000>;
110 };
111
112 ldo5 {
113 regulator-min-microvolt = <600000>;
114 regulator-max-microvolt = <1800000>;
115 };
116
117 ldo6 {
118 regulator-min-microvolt = <1725000>;
119 regulator-max-microvolt = <3300000>;
120 };
121
122 ldo7 {
123 regulator-min-microvolt = <1725000>;
124 regulator-max-microvolt = <3300000>;
125 };
126
127 ldo8 {
128 regulator-min-microvolt = <1200000>;
129 regulator-max-microvolt = <3600000>;
130 };
131
132 ldo9 {
133 regulator-min-microvolt = <1200000>;
134 regulator-max-microvolt = <3600000>;
135 };
136
137 ldo10 {
138 regulator-min-microvolt = <1200000>;
139 regulator-max-microvolt = <3600000>;
140 };
141
142 ldo11 {
143 regulator-min-microvolt = <1200000>;
144 regulator-max-microvolt = <3600000>;
145 };
146
147 ldo12 {
148 regulator-min-microvolt = <1250000>;
149 regulator-max-microvolt = <3650000>;
150 };
151
152 ldo13 {
153 regulator-min-microvolt = <1200000>;
154 regulator-max-microvolt = <3600000>;
155 };
156 };
82 }; 157 };
83 }; 158 };
84 159
85 fec@63fec000 { 160 audmux@63fd0000 {
161 status = "okay";
162 };
163
164 ethernet@63fec000 {
86 phy-mode = "rmii"; 165 phy-mode = "rmii";
87 phy-reset-gpios = <&gpio7 6 0>; 166 phy-reset-gpios = <&gpio7 6 0>;
88 status = "okay"; 167 status = "okay";
@@ -122,4 +201,30 @@
122 linux,default-trigger = "heartbeat"; 201 linux,default-trigger = "heartbeat";
123 }; 202 };
124 }; 203 };
204
205 regulators {
206 compatible = "simple-bus";
207
208 reg_3p2v: 3p2v {
209 compatible = "regulator-fixed";
210 regulator-name = "3P2V";
211 regulator-min-microvolt = <3200000>;
212 regulator-max-microvolt = <3200000>;
213 regulator-always-on;
214 };
215 };
216
217 sound {
218 compatible = "fsl,imx53-qsb-sgtl5000",
219 "fsl,imx-audio-sgtl5000";
220 model = "imx53-qsb-sgtl5000";
221 ssi-controller = <&ssi2>;
222 audio-codec = <&sgtl5000>;
223 audio-routing =
224 "MIC_IN", "Mic Jack",
225 "Mic Jack", "Mic Bias",
226 "Headphone Jack", "HP_OUT";
227 mux-int-port = <2>;
228 mux-ext-port = <5>;
229 };
125}; 230};
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index c7ee86c2dfb5..08091029168e 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -17,10 +17,6 @@
17 model = "Freescale i.MX53 Smart Mobile Reference Design Board"; 17 model = "Freescale i.MX53 Smart Mobile Reference Design Board";
18 compatible = "fsl,imx53-smd", "fsl,imx53"; 18 compatible = "fsl,imx53-smd", "fsl,imx53";
19 19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory { 20 memory {
25 reg = <0x70000000 0x40000000>; 21 reg = <0x70000000 0x40000000>;
26 }; 22 };
@@ -35,11 +31,11 @@
35 }; 31 };
36 32
37 esdhc@50008000 { /* ESDHC2 */ 33 esdhc@50008000 { /* ESDHC2 */
38 fsl,card-wired; 34 non-removable;
39 status = "okay"; 35 status = "okay";
40 }; 36 };
41 37
42 uart3: uart@5000c000 { 38 uart3: serial@5000c000 {
43 fsl,uart-has-rtscts; 39 fsl,uart-has-rtscts;
44 status = "okay"; 40 status = "okay";
45 }; 41 };
@@ -76,7 +72,7 @@
76 }; 72 };
77 73
78 esdhc@50020000 { /* ESDHC3 */ 74 esdhc@50020000 { /* ESDHC3 */
79 fsl,card-wired; 75 non-removable;
80 status = "okay"; 76 status = "okay";
81 }; 77 };
82 }; 78 };
@@ -90,11 +86,11 @@
90 reg = <0x53fa8000 0x4000>; 86 reg = <0x53fa8000 0x4000>;
91 }; 87 };
92 88
93 uart1: uart@53fbc000 { 89 uart1: serial@53fbc000 {
94 status = "okay"; 90 status = "okay";
95 }; 91 };
96 92
97 uart2: uart@53fc0000 { 93 uart2: serial@53fc0000 {
98 status = "okay"; 94 status = "okay";
99 }; 95 };
100 }; 96 };
@@ -142,7 +138,7 @@
142 }; 138 };
143 }; 139 };
144 140
145 fec@63fec000 { 141 ethernet@63fec000 {
146 phy-mode = "rmii"; 142 phy-mode = "rmii";
147 phy-reset-gpios = <&gpio7 6 0>; 143 phy-reset-gpios = <&gpio7 6 0>;
148 status = "okay"; 144 status = "okay";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 5dd91b942c91..e3e869470cd3 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -88,7 +88,7 @@
88 status = "disabled"; 88 status = "disabled";
89 }; 89 };
90 90
91 uart3: uart@5000c000 { 91 uart3: serial@5000c000 {
92 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 92 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
93 reg = <0x5000c000 0x4000>; 93 reg = <0x5000c000 0x4000>;
94 interrupts = <33>; 94 interrupts = <33>;
@@ -104,6 +104,15 @@
104 status = "disabled"; 104 status = "disabled";
105 }; 105 };
106 106
107 ssi2: ssi@50014000 {
108 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
109 reg = <0x50014000 0x4000>;
110 interrupts = <30>;
111 fsl,fifo-depth = <15>;
112 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
113 status = "disabled";
114 };
115
107 esdhc@50020000 { /* ESDHC3 */ 116 esdhc@50020000 { /* ESDHC3 */
108 compatible = "fsl,imx53-esdhc"; 117 compatible = "fsl,imx53-esdhc";
109 reg = <0x50020000 0x4000>; 118 reg = <0x50020000 0x4000>;
@@ -173,14 +182,14 @@
173 status = "disabled"; 182 status = "disabled";
174 }; 183 };
175 184
176 uart1: uart@53fbc000 { 185 uart1: serial@53fbc000 {
177 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 186 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
178 reg = <0x53fbc000 0x4000>; 187 reg = <0x53fbc000 0x4000>;
179 interrupts = <31>; 188 interrupts = <31>;
180 status = "disabled"; 189 status = "disabled";
181 }; 190 };
182 191
183 uart2: uart@53fc0000 { 192 uart2: serial@53fc0000 {
184 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 193 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
185 reg = <0x53fc0000 0x4000>; 194 reg = <0x53fc0000 0x4000>;
186 interrupts = <32>; 195 interrupts = <32>;
@@ -226,7 +235,7 @@
226 status = "disabled"; 235 status = "disabled";
227 }; 236 };
228 237
229 uart4: uart@53ff0000 { 238 uart4: serial@53ff0000 {
230 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 239 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
231 reg = <0x53ff0000 0x4000>; 240 reg = <0x53ff0000 0x4000>;
232 interrupts = <13>; 241 interrupts = <13>;
@@ -241,7 +250,7 @@
241 reg = <0x60000000 0x10000000>; 250 reg = <0x60000000 0x10000000>;
242 ranges; 251 ranges;
243 252
244 uart5: uart@63f90000 { 253 uart5: serial@63f90000 {
245 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 254 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
246 reg = <0x63f90000 0x4000>; 255 reg = <0x63f90000 0x4000>;
247 interrupts = <86>; 256 interrupts = <86>;
@@ -290,7 +299,31 @@
290 status = "disabled"; 299 status = "disabled";
291 }; 300 };
292 301
293 fec@63fec000 { 302 ssi1: ssi@63fcc000 {
303 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
304 reg = <0x63fcc000 0x4000>;
305 interrupts = <29>;
306 fsl,fifo-depth = <15>;
307 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
308 status = "disabled";
309 };
310
311 audmux@63fd0000 {
312 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
313 reg = <0x63fd0000 0x4000>;
314 status = "disabled";
315 };
316
317 ssi3: ssi@63fe8000 {
318 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
319 reg = <0x63fe8000 0x4000>;
320 interrupts = <96>;
321 fsl,fifo-depth = <15>;
322 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
323 status = "disabled";
324 };
325
326 ethernet@63fec000 {
294 compatible = "fsl,imx53-fec", "fsl,imx25-fec"; 327 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
295 reg = <0x63fec000 0x4000>; 328 reg = <0x63fec000 0x4000>;
296 interrupts = <87>; 329 interrupts = <87>;
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index ce1c8238c897..db4c6096c562 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -17,19 +17,14 @@
17 model = "Freescale i.MX6 Quad Armadillo2 Board"; 17 model = "Freescale i.MX6 Quad Armadillo2 Board";
18 compatible = "fsl,imx6q-arm2", "fsl,imx6q"; 18 compatible = "fsl,imx6q-arm2", "fsl,imx6q";
19 19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait";
22 };
23
24 memory { 20 memory {
25 reg = <0x10000000 0x80000000>; 21 reg = <0x10000000 0x80000000>;
26 }; 22 };
27 23
28 soc { 24 soc {
29 aips-bus@02100000 { /* AIPS2 */ 25 aips-bus@02100000 { /* AIPS2 */
30 enet@02188000 { 26 ethernet@02188000 {
31 phy-mode = "rgmii"; 27 phy-mode = "rgmii";
32 local-mac-address = [00 04 9F 01 1B 61];
33 status = "okay"; 28 status = "okay";
34 }; 29 };
35 30
@@ -37,16 +32,20 @@
37 cd-gpios = <&gpio6 11 0>; 32 cd-gpios = <&gpio6 11 0>;
38 wp-gpios = <&gpio6 14 0>; 33 wp-gpios = <&gpio6 14 0>;
39 vmmc-supply = <&reg_3p3v>; 34 vmmc-supply = <&reg_3p3v>;
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_usdhc3_1>;
40 status = "okay"; 37 status = "okay";
41 }; 38 };
42 39
43 usdhc@0219c000 { /* uSDHC4 */ 40 usdhc@0219c000 { /* uSDHC4 */
44 fsl,card-wired; 41 non-removable;
45 vmmc-supply = <&reg_3p3v>; 42 vmmc-supply = <&reg_3p3v>;
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_usdhc4_1>;
46 status = "okay"; 45 status = "okay";
47 }; 46 };
48 47
49 uart4: uart@021f0000 { 48 uart4: serial@021f0000 {
50 status = "okay"; 49 status = "okay";
51 }; 50 };
52 }; 51 };
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 4663a4e5a285..e0ec92973e7e 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -22,8 +22,30 @@
22 }; 22 };
23 23
24 soc { 24 soc {
25 aips-bus@02000000 { /* AIPS1 */
26 spba-bus@02000000 {
27 ecspi@02008000 { /* eCSPI1 */
28 fsl,spi-num-chipselects = <1>;
29 cs-gpios = <&gpio3 19 0>;
30 status = "okay";
31
32 flash: m25p80@0 {
33 compatible = "sst,sst25vf016b";
34 spi-max-frequency = <20000000>;
35 reg = <0>;
36 };
37 };
38
39 ssi1: ssi@02028000 {
40 fsl,mode = "i2s-slave";
41 status = "okay";
42 };
43 };
44
45 };
46
25 aips-bus@02100000 { /* AIPS2 */ 47 aips-bus@02100000 { /* AIPS2 */
26 enet@02188000 { 48 ethernet@02188000 {
27 phy-mode = "rgmii"; 49 phy-mode = "rgmii";
28 phy-reset-gpios = <&gpio3 23 0>; 50 phy-reset-gpios = <&gpio3 23 0>;
29 status = "okay"; 51 status = "okay";
@@ -43,13 +65,23 @@
43 status = "okay"; 65 status = "okay";
44 }; 66 };
45 67
46 uart2: uart@021e8000 { 68 audmux@021d8000 {
69 status = "okay";
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_audmux_1>;
72 };
73
74 uart2: serial@021e8000 {
47 status = "okay"; 75 status = "okay";
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_serial2_1>;
48 }; 78 };
49 79
50 i2c@021a0000 { /* I2C1 */ 80 i2c@021a0000 { /* I2C1 */
51 status = "okay"; 81 status = "okay";
52 clock-frequency = <100000>; 82 clock-frequency = <100000>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_i2c1_1>;
53 85
54 codec: sgtl5000@0a { 86 codec: sgtl5000@0a {
55 compatible = "fsl,sgtl5000"; 87 compatible = "fsl,sgtl5000";
@@ -80,4 +112,18 @@
80 regulator-always-on; 112 regulator-always-on;
81 }; 113 };
82 }; 114 };
115
116 sound {
117 compatible = "fsl,imx6q-sabrelite-sgtl5000",
118 "fsl,imx-audio-sgtl5000";
119 model = "imx6q-sabrelite-sgtl5000";
120 ssi-controller = <&ssi1>;
121 audio-codec = <&codec>;
122 audio-routing =
123 "MIC_IN", "Mic Jack",
124 "Mic Jack", "Mic Bias",
125 "Headphone Jack", "HP_OUT";
126 mux-int-port = <1>;
127 mux-ext-port = <4>;
128 };
83}; 129};
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
new file mode 100644
index 000000000000..07509a181178
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -0,0 +1,53 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx6q.dtsi"
15
16/ {
17 model = "Freescale i.MX6Q SABRE Smart Device Board";
18 compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
19
20 memory {
21 reg = <0x10000000 0x40000000>;
22 };
23
24 soc {
25
26 aips-bus@02000000 { /* AIPS1 */
27 spba-bus@02000000 {
28 uart1: serial@02020000 {
29 status = "okay";
30 };
31 };
32 };
33
34 aips-bus@02100000 { /* AIPS2 */
35 ethernet@02188000 {
36 phy-mode = "rgmii";
37 status = "okay";
38 };
39
40 usdhc@02194000 { /* uSDHC2 */
41 cd-gpios = <&gpio2 2 0>;
42 wp-gpios = <&gpio2 3 0>;
43 status = "okay";
44 };
45
46 usdhc@02198000 { /* uSDHC3 */
47 cd-gpios = <&gpio2 0 0>;
48 wp-gpios = <&gpio2 1 0>;
49 status = "okay";
50 };
51 };
52 };
53};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 4905f51a106f..8c90cbac945f 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -165,7 +165,7 @@
165 status = "disabled"; 165 status = "disabled";
166 }; 166 };
167 167
168 uart1: uart@02020000 { 168 uart1: serial@02020000 {
169 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 169 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
170 reg = <0x02020000 0x4000>; 170 reg = <0x02020000 0x4000>;
171 interrupts = <0 26 0x04>; 171 interrupts = <0 26 0x04>;
@@ -177,19 +177,31 @@
177 interrupts = <0 51 0x04>; 177 interrupts = <0 51 0x04>;
178 }; 178 };
179 179
180 ssi@02028000 { /* SSI1 */ 180 ssi1: ssi@02028000 {
181 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
181 reg = <0x02028000 0x4000>; 182 reg = <0x02028000 0x4000>;
182 interrupts = <0 46 0x04>; 183 interrupts = <0 46 0x04>;
184 fsl,fifo-depth = <15>;
185 fsl,ssi-dma-events = <38 37>;
186 status = "disabled";
183 }; 187 };
184 188
185 ssi@0202c000 { /* SSI2 */ 189 ssi2: ssi@0202c000 {
190 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
186 reg = <0x0202c000 0x4000>; 191 reg = <0x0202c000 0x4000>;
187 interrupts = <0 47 0x04>; 192 interrupts = <0 47 0x04>;
193 fsl,fifo-depth = <15>;
194 fsl,ssi-dma-events = <42 41>;
195 status = "disabled";
188 }; 196 };
189 197
190 ssi@02030000 { /* SSI3 */ 198 ssi3: ssi@02030000 {
199 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
191 reg = <0x02030000 0x4000>; 200 reg = <0x02030000 0x4000>;
192 interrupts = <0 48 0x04>; 201 interrupts = <0 48 0x04>;
202 fsl,fifo-depth = <15>;
203 fsl,ssi-dma-events = <46 45>;
204 status = "disabled";
193 }; 205 };
194 206
195 asrc@02034000 { 207 asrc@02034000 {
@@ -346,6 +358,90 @@
346 compatible = "fsl,imx6q-anatop"; 358 compatible = "fsl,imx6q-anatop";
347 reg = <0x020c8000 0x1000>; 359 reg = <0x020c8000 0x1000>;
348 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; 360 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
361
362 regulator-1p1@110 {
363 compatible = "fsl,anatop-regulator";
364 regulator-name = "vdd1p1";
365 regulator-min-microvolt = <800000>;
366 regulator-max-microvolt = <1375000>;
367 regulator-always-on;
368 anatop-reg-offset = <0x110>;
369 anatop-vol-bit-shift = <8>;
370 anatop-vol-bit-width = <5>;
371 anatop-min-bit-val = <4>;
372 anatop-min-voltage = <800000>;
373 anatop-max-voltage = <1375000>;
374 };
375
376 regulator-3p0@120 {
377 compatible = "fsl,anatop-regulator";
378 regulator-name = "vdd3p0";
379 regulator-min-microvolt = <2800000>;
380 regulator-max-microvolt = <3150000>;
381 regulator-always-on;
382 anatop-reg-offset = <0x120>;
383 anatop-vol-bit-shift = <8>;
384 anatop-vol-bit-width = <5>;
385 anatop-min-bit-val = <0>;
386 anatop-min-voltage = <2625000>;
387 anatop-max-voltage = <3400000>;
388 };
389
390 regulator-2p5@130 {
391 compatible = "fsl,anatop-regulator";
392 regulator-name = "vdd2p5";
393 regulator-min-microvolt = <2000000>;
394 regulator-max-microvolt = <2750000>;
395 regulator-always-on;
396 anatop-reg-offset = <0x130>;
397 anatop-vol-bit-shift = <8>;
398 anatop-vol-bit-width = <5>;
399 anatop-min-bit-val = <0>;
400 anatop-min-voltage = <2000000>;
401 anatop-max-voltage = <2750000>;
402 };
403
404 regulator-vddcore@140 {
405 compatible = "fsl,anatop-regulator";
406 regulator-name = "cpu";
407 regulator-min-microvolt = <725000>;
408 regulator-max-microvolt = <1450000>;
409 regulator-always-on;
410 anatop-reg-offset = <0x140>;
411 anatop-vol-bit-shift = <0>;
412 anatop-vol-bit-width = <5>;
413 anatop-min-bit-val = <1>;
414 anatop-min-voltage = <725000>;
415 anatop-max-voltage = <1450000>;
416 };
417
418 regulator-vddpu@140 {
419 compatible = "fsl,anatop-regulator";
420 regulator-name = "vddpu";
421 regulator-min-microvolt = <725000>;
422 regulator-max-microvolt = <1450000>;
423 regulator-always-on;
424 anatop-reg-offset = <0x140>;
425 anatop-vol-bit-shift = <9>;
426 anatop-vol-bit-width = <5>;
427 anatop-min-bit-val = <1>;
428 anatop-min-voltage = <725000>;
429 anatop-max-voltage = <1450000>;
430 };
431
432 regulator-vddsoc@140 {
433 compatible = "fsl,anatop-regulator";
434 regulator-name = "vddsoc";
435 regulator-min-microvolt = <725000>;
436 regulator-max-microvolt = <1450000>;
437 regulator-always-on;
438 anatop-reg-offset = <0x140>;
439 anatop-vol-bit-shift = <18>;
440 anatop-vol-bit-width = <5>;
441 anatop-min-bit-val = <1>;
442 anatop-min-voltage = <725000>;
443 anatop-max-voltage = <1450000>;
444 };
349 }; 445 };
350 446
351 usbphy@020c9000 { /* USBPHY1 */ 447 usbphy@020c9000 { /* USBPHY1 */
@@ -386,7 +482,62 @@
386 }; 482 };
387 483
388 iomuxc@020e0000 { 484 iomuxc@020e0000 {
485 compatible = "fsl,imx6q-iomuxc";
389 reg = <0x020e0000 0x4000>; 486 reg = <0x020e0000 0x4000>;
487
488 /* shared pinctrl settings */
489 audmux {
490 pinctrl_audmux_1: audmux-1 {
491 fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
492 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
493 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
494 3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
495 };
496 };
497
498 i2c1 {
499 pinctrl_i2c1_1: i2c1grp-1 {
500 fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
501 196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */
502 };
503 };
504
505 serial2 {
506 pinctrl_serial2_1: serial2grp-1 {
507 fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
508 191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */
509 };
510 };
511
512 usdhc3 {
513 pinctrl_usdhc3_1: usdhc3grp-1 {
514 fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
515 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
516 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
517 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
518 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
519 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
520 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
521 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
522 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
523 1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
524 };
525 };
526
527 usdhc4 {
528 pinctrl_usdhc4_1: usdhc4grp-1 {
529 fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
530 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
531 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
532 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
533 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
534 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
535 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
536 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
537 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
538 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
539 };
540 };
390 }; 541 };
391 542
392 dcic@020e4000 { /* DCIC1 */ 543 dcic@020e4000 { /* DCIC1 */
@@ -422,7 +573,7 @@
422 reg = <0x0217c000 0x4000>; 573 reg = <0x0217c000 0x4000>;
423 }; 574 };
424 575
425 enet@02188000 { 576 ethernet@02188000 {
426 compatible = "fsl,imx6q-fec"; 577 compatible = "fsl,imx6q-fec";
427 reg = <0x02188000 0x4000>; 578 reg = <0x02188000 0x4000>;
428 interrupts = <0 118 0x04 0 119 0x04>; 579 interrupts = <0 118 0x04 0 119 0x04>;
@@ -527,7 +678,9 @@
527 }; 678 };
528 679
529 audmux@021d8000 { 680 audmux@021d8000 {
681 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
530 reg = <0x021d8000 0x4000>; 682 reg = <0x021d8000 0x4000>;
683 status = "disabled";
531 }; 684 };
532 685
533 mipi@021dc000 { /* MIPI-CSI */ 686 mipi@021dc000 { /* MIPI-CSI */
@@ -543,28 +696,28 @@
543 interrupts = <0 18 0x04>; 696 interrupts = <0 18 0x04>;
544 }; 697 };
545 698
546 uart2: uart@021e8000 { 699 uart2: serial@021e8000 {
547 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 700 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
548 reg = <0x021e8000 0x4000>; 701 reg = <0x021e8000 0x4000>;
549 interrupts = <0 27 0x04>; 702 interrupts = <0 27 0x04>;
550 status = "disabled"; 703 status = "disabled";
551 }; 704 };
552 705
553 uart3: uart@021ec000 { 706 uart3: serial@021ec000 {
554 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 707 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
555 reg = <0x021ec000 0x4000>; 708 reg = <0x021ec000 0x4000>;
556 interrupts = <0 28 0x04>; 709 interrupts = <0 28 0x04>;
557 status = "disabled"; 710 status = "disabled";
558 }; 711 };
559 712
560 uart4: uart@021f0000 { 713 uart4: serial@021f0000 {
561 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 714 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
562 reg = <0x021f0000 0x4000>; 715 reg = <0x021f0000 0x4000>;
563 interrupts = <0 29 0x04>; 716 interrupts = <0 29 0x04>;
564 status = "disabled"; 717 status = "disabled";
565 }; 718 };
566 719
567 uart5: uart@021f4000 { 720 uart5: serial@021f4000 {
568 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 721 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
569 reg = <0x021f4000 0x4000>; 722 reg = <0x021f4000 0x4000>;
570 interrupts = <0 30 0x04>; 723 interrupts = <0 30 0x04>;
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
new file mode 100644
index 000000000000..dc09a735b04a
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -0,0 +1,64 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4
5/ {
6 model = "D-Link DNS-320 NAS (Rev A1)";
7 compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x8000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200n8 earlyprintk";
16 };
17
18 ocp@f1000000 {
19 serial@12000 {
20 clock-frequency = <166666667>;
21 status = "okay";
22 };
23
24 serial@12100 {
25 clock-frequency = <166666667>;
26 status = "okay";
27 };
28
29 nand@3000000 {
30 status = "okay";
31
32 partition@0 {
33 label = "u-boot";
34 reg = <0x0000000 0x100000>;
35 read-only;
36 };
37
38 partition@100000 {
39 label = "uImage";
40 reg = <0x0100000 0x500000>;
41 };
42
43 partition@600000 {
44 label = "ramdisk";
45 reg = <0x0600000 0x500000>;
46 };
47
48 partition@b00000 {
49 label = "image";
50 reg = <0x0b00000 0x6600000>;
51 };
52
53 partition@7100000 {
54 label = "mini firmware";
55 reg = <0x7100000 0xa00000>;
56 };
57
58 partition@7b00000 {
59 label = "config";
60 reg = <0x7b00000 0x500000>;
61 };
62 };
63 };
64};
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
new file mode 100644
index 000000000000..c2a5562525d2
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -0,0 +1,59 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4
5/ {
6 model = "D-Link DNS-325 NAS (Rev A1)";
7 compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200n8 earlyprintk";
16 };
17
18 ocp@f1000000 {
19 serial@12000 {
20 clock-frequency = <200000000>;
21 status = "okay";
22 };
23
24 nand@3000000 {
25 status = "okay";
26
27 partition@0 {
28 label = "u-boot";
29 reg = <0x0000000 0x100000>;
30 read-only;
31 };
32
33 partition@100000 {
34 label = "uImage";
35 reg = <0x0100000 0x500000>;
36 };
37
38 partition@600000 {
39 label = "ramdisk";
40 reg = <0x0600000 0x500000>;
41 };
42
43 partition@b00000 {
44 label = "image";
45 reg = <0x0b00000 0x6600000>;
46 };
47
48 partition@7100000 {
49 label = "mini firmware";
50 reg = <0x7100000 0xa00000>;
51 };
52
53 partition@7b00000 {
54 label = "config";
55 reg = <0x7b00000 0x500000>;
56 };
57 };
58 };
59};
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
new file mode 100644
index 000000000000..ada0f0c23085
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -0,0 +1,44 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4
5/ {
6 model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
7 compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200n8 earlyprintk";
16 };
17
18 ocp@f1000000 {
19 serial@12000 {
20 clock-frequency = <200000000>;
21 status = "okay";
22 };
23
24 nand@3000000 {
25 status = "okay";
26
27 partition@0 {
28 label = "u-boot";
29 reg = <0x0000000 0x100000>;
30 };
31
32 partition@100000 {
33 label = "uImage";
34 reg = <0x0100000 0x600000>;
35 };
36
37 partition@700000 {
38 label = "root";
39 reg = <0x0700000 0xf900000>;
40 };
41
42 };
43 };
44};
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
new file mode 100644
index 000000000000..1ba75d4adecc
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -0,0 +1,26 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4
5/ {
6 model = "Iomega Iconnect";
7 compatible = "iom,iconnect-1.1", "iom,iconnect", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200n8 earlyprintk mtdparts=orion_nand:0xc0000@0x0(uboot),0x20000@0xa0000(env),0x300000@0x100000(zImage),0x300000@0x540000(initrd),0x1f400000@0x980000(boot)";
16 linux,initrd-start = <0x4500040>;
17 linux,initrd-end = <0x4800000>;
18 };
19
20 ocp@f1000000 {
21 serial@12000 {
22 clock-frequency = <200000000>;
23 status = "ok";
24 };
25 };
26};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 3474ef890945..926528b81baa 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -5,7 +5,7 @@
5 5
6 ocp@f1000000 { 6 ocp@f1000000 {
7 compatible = "simple-bus"; 7 compatible = "simple-bus";
8 ranges = <0 0xf1000000 0x1000000>; 8 ranges = <0 0xf1000000 0x4000000>;
9 #address-cells = <1>; 9 #address-cells = <1>;
10 #size-cells = <1>; 10 #size-cells = <1>;
11 11
@@ -32,5 +32,18 @@
32 reg = <0x10300 0x20>; 32 reg = <0x10300 0x20>;
33 interrupts = <53>; 33 interrupts = <53>;
34 }; 34 };
35
36 nand@3000000 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 cle = <0>;
40 ale = <1>;
41 bank-width = <1>;
42 compatible = "mrvl,orion-nand";
43 reg = <0x3000000 0x400>;
44 chip-delay = <25>;
45 /* set partition map and/or chip-delay in board dts */
46 status = "disabled";
47 };
35 }; 48 };
36}; 49};
diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts
new file mode 100644
index 000000000000..e8814fe0e277
--- /dev/null
+++ b/arch/arm/boot/dts/kizbox.dts
@@ -0,0 +1,138 @@
1/*
2 * kizbox.dts - Device Tree file for Overkiz Kizbox board
3 *
4 * Copyright (C) 2012 Boris BREZILLON <linux-arm@overkiz.com>
5 *
6 * Licensed under GPLv2.
7 */
8/dts-v1/;
9/include/ "at91sam9g20.dtsi"
10
11/ {
12
13 model = "Overkiz kizbox";
14 compatible = "overkiz,kizbox", "atmel,at91sam9g20", "atmel,at91sam9";
15
16 chosen {
17 bootargs = "panic=5 ubi.mtd=1 rootfstype=ubifs root=ubi0:root";
18 };
19
20 memory {
21 reg = <0x20000000 0x2000000>;
22 };
23
24 clocks {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges;
28
29 main_clock: clock@0 {
30 compatible = "atmel,osc", "fixed-clock";
31 clock-frequency = <18432000>;
32 };
33 };
34
35 ahb {
36 apb {
37 dbgu: serial@fffff200 {
38 status = "okay";
39 };
40
41 usart0: serial@fffb0000 {
42 status = "okay";
43 };
44
45 usart1: serial@fffb4000 {
46 status = "okay";
47 };
48
49 macb0: ethernet@fffc4000 {
50 phy-mode = "mii";
51 status = "okay";
52 };
53
54 };
55
56 nand0: nand@40000000 {
57 nand-bus-width = <8>;
58 nand-ecc-mode = "soft";
59 status = "okay";
60
61 bootloaderkernel@0 {
62 label = "bootloader-kernel";
63 reg = <0x0 0xc0000>;
64 };
65
66 ubi@c0000 {
67 label = "ubi";
68 reg = <0xc0000 0x7f40000>;
69 };
70
71 };
72
73 usb0: ohci@00500000 {
74 num-ports = <1>;
75 status = "okay";
76 };
77 };
78
79 i2c@0 {
80 status = "okay";
81
82 pcf8563@51 {
83 /* nxp pcf8563 rtc */
84 compatible = "nxp,pcf8563";
85 reg = <0x51>;
86 };
87
88 };
89
90 leds {
91 compatible = "gpio-leds";
92
93 led1g {
94 label = "led1:green";
95 gpios = <&pioB 0 1>;
96 linux,default-trigger = "none";
97 };
98
99 led1r {
100 label = "led1:red";
101 gpios = <&pioB 1 1>;
102 linux,default-trigger = "none";
103 };
104
105 led2g {
106 label = "led2:green";
107 gpios = <&pioB 2 1>;
108 linux,default-trigger = "none";
109 default-state = "on";
110 };
111
112 led2r {
113 label = "led2:red";
114 gpios = <&pioB 3 1>;
115 linux,default-trigger = "none";
116 };
117 };
118
119 gpio_keys {
120 compatible = "gpio-keys";
121 #address-cells = <1>;
122 #size-cells = <0>;
123
124 reset {
125 label = "reset";
126 gpios = <&pioB 30 1>;
127 linux,code = <0x100>;
128 gpio-key,wakeup;
129 };
130
131 mode {
132 label = "mode";
133 gpios = <&pioB 31 1>;
134 linux,code = <0x101>;
135 gpio-key,wakeup;
136 };
137 };
138}; \ No newline at end of file
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
new file mode 100644
index 000000000000..2d696866f71c
--- /dev/null
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -0,0 +1,292 @@
1/*
2 * NXP LPC32xx SoC
3 *
4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 compatible = "nxp,lpc3220";
18 interrupt-parent = <&mic>;
19
20 cpus {
21 cpu@0 {
22 compatible = "arm,arm926ejs";
23 };
24 };
25
26 ahb {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "simple-bus";
30 ranges = <0x20000000 0x20000000 0x30000000>;
31
32 /*
33 * Enable either SLC or MLC
34 */
35 slc: flash@20020000 {
36 compatible = "nxp,lpc3220-slc";
37 reg = <0x20020000 0x1000>;
38 status = "disable";
39 };
40
41 mlc: flash@200B0000 {
42 compatible = "nxp,lpc3220-mlc";
43 reg = <0x200B0000 0x1000>;
44 status = "disable";
45 };
46
47 dma@31000000 {
48 compatible = "arm,pl080", "arm,primecell";
49 reg = <0x31000000 0x1000>;
50 interrupts = <0x1c 0>;
51 };
52
53 /*
54 * Enable either ohci or usbd (gadget)!
55 */
56 ohci@31020000 {
57 compatible = "nxp,ohci-nxp", "usb-ohci";
58 reg = <0x31020000 0x300>;
59 interrupts = <0x3b 0>;
60 status = "disable";
61 };
62
63 usbd@31020000 {
64 compatible = "nxp,lpc3220-udc";
65 reg = <0x31020000 0x300>;
66 interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
67 status = "disable";
68 };
69
70 clcd@31040000 {
71 compatible = "arm,pl110", "arm,primecell";
72 reg = <0x31040000 0x1000>;
73 interrupts = <0x0e 0>;
74 status = "disable";
75 };
76
77 mac: ethernet@31060000 {
78 compatible = "nxp,lpc-eth";
79 reg = <0x31060000 0x1000>;
80 interrupts = <0x1d 0>;
81 };
82
83 apb {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "simple-bus";
87 ranges = <0x20000000 0x20000000 0x30000000>;
88
89 ssp0: ssp@20084000 {
90 compatible = "arm,pl022", "arm,primecell";
91 reg = <0x20084000 0x1000>;
92 interrupts = <0x14 0>;
93 };
94
95 spi1: spi@20088000 {
96 compatible = "nxp,lpc3220-spi";
97 reg = <0x20088000 0x1000>;
98 };
99
100 ssp1: ssp@2008c000 {
101 compatible = "arm,pl022", "arm,primecell";
102 reg = <0x2008c000 0x1000>;
103 interrupts = <0x15 0>;
104 };
105
106 spi2: spi@20090000 {
107 compatible = "nxp,lpc3220-spi";
108 reg = <0x20090000 0x1000>;
109 };
110
111 i2s0: i2s@20094000 {
112 compatible = "nxp,lpc3220-i2s";
113 reg = <0x20094000 0x1000>;
114 };
115
116 sd@20098000 {
117 compatible = "arm,pl180", "arm,primecell";
118 reg = <0x20098000 0x1000>;
119 interrupts = <0x0f 0>, <0x0d 0>;
120 };
121
122 i2s1: i2s@2009C000 {
123 compatible = "nxp,lpc3220-i2s";
124 reg = <0x2009C000 0x1000>;
125 };
126
127 uart3: serial@40080000 {
128 compatible = "nxp,serial";
129 reg = <0x40080000 0x1000>;
130 };
131
132 uart4: serial@40088000 {
133 compatible = "nxp,serial";
134 reg = <0x40088000 0x1000>;
135 };
136
137 uart5: serial@40090000 {
138 compatible = "nxp,serial";
139 reg = <0x40090000 0x1000>;
140 };
141
142 uart6: serial@40098000 {
143 compatible = "nxp,serial";
144 reg = <0x40098000 0x1000>;
145 };
146
147 i2c1: i2c@400A0000 {
148 compatible = "nxp,pnx-i2c";
149 reg = <0x400A0000 0x100>;
150 interrupts = <0x33 0>;
151 #address-cells = <1>;
152 #size-cells = <0>;
153 pnx,timeout = <0x64>;
154 };
155
156 i2c2: i2c@400A8000 {
157 compatible = "nxp,pnx-i2c";
158 reg = <0x400A8000 0x100>;
159 interrupts = <0x32 0>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 pnx,timeout = <0x64>;
163 };
164
165 i2cusb: i2c@31020300 {
166 compatible = "nxp,pnx-i2c";
167 reg = <0x31020300 0x100>;
168 interrupts = <0x3f 0>;
169 #address-cells = <1>;
170 #size-cells = <0>;
171 pnx,timeout = <0x64>;
172 };
173 };
174
175 fab {
176 #address-cells = <1>;
177 #size-cells = <1>;
178 compatible = "simple-bus";
179 ranges = <0x20000000 0x20000000 0x30000000>;
180
181 /*
182 * MIC Interrupt controller includes:
183 * MIC @40008000
184 * SIC1 @4000C000
185 * SIC2 @40010000
186 */
187 mic: interrupt-controller@40008000 {
188 compatible = "nxp,lpc3220-mic";
189 interrupt-controller;
190 reg = <0x40008000 0xC000>;
191 #interrupt-cells = <2>;
192 };
193
194 uart1: serial@40014000 {
195 compatible = "nxp,serial";
196 reg = <0x40014000 0x1000>;
197 };
198
199 uart2: serial@40018000 {
200 compatible = "nxp,serial";
201 reg = <0x40018000 0x1000>;
202 };
203
204 uart7: serial@4001C000 {
205 compatible = "nxp,serial";
206 reg = <0x4001C000 0x1000>;
207 };
208
209 rtc@40024000 {
210 compatible = "nxp,lpc3220-rtc";
211 reg = <0x40024000 0x1000>;
212 interrupts = <0x34 0>;
213 };
214
215 gpio: gpio@40028000 {
216 compatible = "nxp,lpc3220-gpio";
217 reg = <0x40028000 0x1000>;
218 /* create a private address space for enumeration */
219 #address-cells = <1>;
220 #size-cells = <0>;
221
222 gpio_p0: gpio-bank@0 {
223 gpio-controller;
224 #gpio-cells = <2>;
225 reg = <0>;
226 };
227
228 gpio_p1: gpio-bank@1 {
229 gpio-controller;
230 #gpio-cells = <2>;
231 reg = <1>;
232 };
233
234 gpio_p2: gpio-bank@2 {
235 gpio-controller;
236 #gpio-cells = <2>;
237 reg = <2>;
238 };
239
240 gpio_p3: gpio-bank@3 {
241 gpio-controller;
242 #gpio-cells = <2>;
243 reg = <3>;
244 };
245
246 gpi_p3: gpio-bank@4 {
247 gpio-controller;
248 #gpio-cells = <2>;
249 reg = <4>;
250 };
251
252 gpo_p3: gpio-bank@5 {
253 gpio-controller;
254 #gpio-cells = <2>;
255 reg = <5>;
256 };
257 };
258
259 watchdog@4003C000 {
260 compatible = "nxp,pnx4008-wdt";
261 reg = <0x4003C000 0x1000>;
262 };
263
264 /*
265 * TSC vs. ADC: Since those two share the same
266 * hardware, you need to choose from one of the
267 * following two and do 'status = "okay";' for one of
268 * them
269 */
270
271 adc@40048000 {
272 compatible = "nxp,lpc3220-adc";
273 reg = <0x40048000 0x1000>;
274 interrupts = <0x27 0>;
275 status = "disable";
276 };
277
278 tsc@40048000 {
279 compatible = "nxp,lpc3220-tsc";
280 reg = <0x40048000 0x1000>;
281 interrupts = <0x27 0>;
282 status = "disable";
283 };
284
285 key@40050000 {
286 compatible = "nxp,lpc3220-key";
287 reg = <0x40050000 0x1000>;
288 };
289
290 };
291 };
292};
diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts
new file mode 100644
index 000000000000..153a4b2d12b5
--- /dev/null
+++ b/arch/arm/boot/dts/mmp2-brownstone.dts
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/dts-v1/;
11/include/ "mmp2.dtsi"
12
13/ {
14 model = "Marvell MMP2 Aspenite Development Board";
15 compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";
16
17 chosen {
18 bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
19 };
20
21 memory {
22 reg = <0x00000000 0x04000000>;
23 };
24
25 soc {
26 apb@d4000000 {
27 uart3: uart@d4018000 {
28 status = "okay";
29 };
30 twsi1: i2c@d4011000 {
31 status = "okay";
32 };
33 rtc: rtc@d4010000 {
34 status = "okay";
35 };
36 };
37 };
38};
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
new file mode 100644
index 000000000000..80f74e256408
--- /dev/null
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -0,0 +1,220 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 aliases {
14 serial0 = &uart1;
15 serial1 = &uart2;
16 serial2 = &uart3;
17 serial3 = &uart4;
18 i2c0 = &twsi1;
19 i2c1 = &twsi2;
20 };
21
22 soc {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 compatible = "simple-bus";
26 interrupt-parent = <&intc>;
27 ranges;
28
29 axi@d4200000 { /* AXI */
30 compatible = "mrvl,axi-bus", "simple-bus";
31 #address-cells = <1>;
32 #size-cells = <1>;
33 reg = <0xd4200000 0x00200000>;
34 ranges;
35
36 intc: interrupt-controller@d4282000 {
37 compatible = "mrvl,mmp2-intc";
38 interrupt-controller;
39 #interrupt-cells = <1>;
40 reg = <0xd4282000 0x1000>;
41 mrvl,intc-nr-irqs = <64>;
42 };
43
44 intcmux4@d4282150 {
45 compatible = "mrvl,mmp2-mux-intc";
46 interrupts = <4>;
47 interrupt-controller;
48 #interrupt-cells = <1>;
49 reg = <0x150 0x4>, <0x168 0x4>;
50 reg-names = "mux status", "mux mask";
51 mrvl,intc-nr-irqs = <2>;
52 };
53
54 intcmux5: interrupt-controller@d4282154 {
55 compatible = "mrvl,mmp2-mux-intc";
56 interrupts = <5>;
57 interrupt-controller;
58 #interrupt-cells = <1>;
59 reg = <0x154 0x4>, <0x16c 0x4>;
60 reg-names = "mux status", "mux mask";
61 mrvl,intc-nr-irqs = <2>;
62 mrvl,clr-mfp-irq = <1>;
63 };
64
65 intcmux9: interrupt-controller@d4282180 {
66 compatible = "mrvl,mmp2-mux-intc";
67 interrupts = <9>;
68 interrupt-controller;
69 #interrupt-cells = <1>;
70 reg = <0x180 0x4>, <0x17c 0x4>;
71 reg-names = "mux status", "mux mask";
72 mrvl,intc-nr-irqs = <3>;
73 };
74
75 intcmux17: interrupt-controller@d4282158 {
76 compatible = "mrvl,mmp2-mux-intc";
77 interrupts = <17>;
78 interrupt-controller;
79 #interrupt-cells = <1>;
80 reg = <0x158 0x4>, <0x170 0x4>;
81 reg-names = "mux status", "mux mask";
82 mrvl,intc-nr-irqs = <5>;
83 };
84
85 intcmux35: interrupt-controller@d428215c {
86 compatible = "mrvl,mmp2-mux-intc";
87 interrupts = <35>;
88 interrupt-controller;
89 #interrupt-cells = <1>;
90 reg = <0x15c 0x4>, <0x174 0x4>;
91 reg-names = "mux status", "mux mask";
92 mrvl,intc-nr-irqs = <15>;
93 };
94
95 intcmux51: interrupt-controller@d4282160 {
96 compatible = "mrvl,mmp2-mux-intc";
97 interrupts = <51>;
98 interrupt-controller;
99 #interrupt-cells = <1>;
100 reg = <0x160 0x4>, <0x178 0x4>;
101 reg-names = "mux status", "mux mask";
102 mrvl,intc-nr-irqs = <2>;
103 };
104
105 intcmux55: interrupt-controller@d4282188 {
106 compatible = "mrvl,mmp2-mux-intc";
107 interrupts = <55>;
108 interrupt-controller;
109 #interrupt-cells = <1>;
110 reg = <0x188 0x4>, <0x184 0x4>;
111 reg-names = "mux status", "mux mask";
112 mrvl,intc-nr-irqs = <2>;
113 };
114 };
115
116 apb@d4000000 { /* APB */
117 compatible = "mrvl,apb-bus", "simple-bus";
118 #address-cells = <1>;
119 #size-cells = <1>;
120 reg = <0xd4000000 0x00200000>;
121 ranges;
122
123 timer0: timer@d4014000 {
124 compatible = "mrvl,mmp-timer";
125 reg = <0xd4014000 0x100>;
126 interrupts = <13>;
127 };
128
129 uart1: uart@d4030000 {
130 compatible = "mrvl,mmp-uart";
131 reg = <0xd4030000 0x1000>;
132 interrupts = <27>;
133 status = "disabled";
134 };
135
136 uart2: uart@d4017000 {
137 compatible = "mrvl,mmp-uart";
138 reg = <0xd4017000 0x1000>;
139 interrupts = <28>;
140 status = "disabled";
141 };
142
143 uart3: uart@d4018000 {
144 compatible = "mrvl,mmp-uart";
145 reg = <0xd4018000 0x1000>;
146 interrupts = <24>;
147 status = "disabled";
148 };
149
150 uart4: uart@d4016000 {
151 compatible = "mrvl,mmp-uart";
152 reg = <0xd4016000 0x1000>;
153 interrupts = <46>;
154 status = "disabled";
155 };
156
157 gpio@d4019000 {
158 compatible = "mrvl,mmp-gpio";
159 #address-cells = <1>;
160 #size-cells = <1>;
161 reg = <0xd4019000 0x1000>;
162 gpio-controller;
163 #gpio-cells = <2>;
164 interrupts = <49>;
165 interrupt-names = "gpio_mux";
166 interrupt-controller;
167 #interrupt-cells = <1>;
168 ranges;
169
170 gcb0: gpio@d4019000 {
171 reg = <0xd4019000 0x4>;
172 };
173
174 gcb1: gpio@d4019004 {
175 reg = <0xd4019004 0x4>;
176 };
177
178 gcb2: gpio@d4019008 {
179 reg = <0xd4019008 0x4>;
180 };
181
182 gcb3: gpio@d4019100 {
183 reg = <0xd4019100 0x4>;
184 };
185
186 gcb4: gpio@d4019104 {
187 reg = <0xd4019104 0x4>;
188 };
189
190 gcb5: gpio@d4019108 {
191 reg = <0xd4019108 0x4>;
192 };
193 };
194
195 twsi1: i2c@d4011000 {
196 compatible = "mrvl,mmp-twsi";
197 reg = <0xd4011000 0x1000>;
198 interrupts = <7>;
199 mrvl,i2c-fast-mode;
200 status = "disabled";
201 };
202
203 twsi2: i2c@d4025000 {
204 compatible = "mrvl,mmp-twsi";
205 reg = <0xd4025000 0x1000>;
206 interrupts = <58>;
207 status = "disabled";
208 };
209
210 rtc: rtc@d4010000 {
211 compatible = "mrvl,mmp-rtc";
212 reg = <0xd4010000 0x1000>;
213 interrupts = <1 0>;
214 interrupt-names = "rtc 1Hz", "rtc alarm";
215 interrupt-parent = <&intcmux5>;
216 status = "disabled";
217 };
218 };
219 };
220};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 9f72cd4cf308..5b4506c0a8c4 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -18,3 +18,52 @@
18 reg = <0x80000000 0x20000000>; /* 512 MB */ 18 reg = <0x80000000 0x20000000>; /* 512 MB */
19 }; 19 };
20}; 20};
21
22&i2c1 {
23 clock-frequency = <2600000>;
24
25 twl: twl@48 {
26 reg = <0x48>;
27 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
28 interrupt-parent = <&intc>;
29
30 vsim: regulator@10 {
31 compatible = "ti,twl4030-vsim";
32 regulator-min-microvolt = <1800000>;
33 regulator-max-microvolt = <3000000>;
34 };
35 };
36};
37
38/include/ "twl4030.dtsi"
39
40&i2c2 {
41 clock-frequency = <400000>;
42};
43
44&i2c3 {
45 clock-frequency = <100000>;
46
47 /*
48 * Display monitor features are burnt in the EEPROM
49 * as EDID data.
50 */
51 eeprom@50 {
52 compatible = "ti,eeprom";
53 reg = <0x50>;
54 };
55};
56
57&mmc1 {
58 vmmc-supply = <&vmmc1>;
59 vmmc_aux-supply = <&vsim>;
60 bus-width = <8>;
61};
62
63&mmc2 {
64 status = "disable";
65};
66
67&mmc3 {
68 status = "disable";
69};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index c6121357c1eb..99474fa5fac4 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -69,6 +69,60 @@
69 reg = <0x48200000 0x1000>; 69 reg = <0x48200000 0x1000>;
70 }; 70 };
71 71
72 gpio1: gpio@48310000 {
73 compatible = "ti,omap3-gpio";
74 ti,hwmods = "gpio1";
75 gpio-controller;
76 #gpio-cells = <2>;
77 interrupt-controller;
78 #interrupt-cells = <1>;
79 };
80
81 gpio2: gpio@49050000 {
82 compatible = "ti,omap3-gpio";
83 ti,hwmods = "gpio2";
84 gpio-controller;
85 #gpio-cells = <2>;
86 interrupt-controller;
87 #interrupt-cells = <1>;
88 };
89
90 gpio3: gpio@49052000 {
91 compatible = "ti,omap3-gpio";
92 ti,hwmods = "gpio3";
93 gpio-controller;
94 #gpio-cells = <2>;
95 interrupt-controller;
96 #interrupt-cells = <1>;
97 };
98
99 gpio4: gpio@49054000 {
100 compatible = "ti,omap3-gpio";
101 ti,hwmods = "gpio4";
102 gpio-controller;
103 #gpio-cells = <2>;
104 interrupt-controller;
105 #interrupt-cells = <1>;
106 };
107
108 gpio5: gpio@49056000 {
109 compatible = "ti,omap3-gpio";
110 ti,hwmods = "gpio5";
111 gpio-controller;
112 #gpio-cells = <2>;
113 interrupt-controller;
114 #interrupt-cells = <1>;
115 };
116
117 gpio6: gpio@49058000 {
118 compatible = "ti,omap3-gpio";
119 ti,hwmods = "gpio6";
120 gpio-controller;
121 #gpio-cells = <2>;
122 interrupt-controller;
123 #interrupt-cells = <1>;
124 };
125
72 uart1: serial@4806a000 { 126 uart1: serial@4806a000 {
73 compatible = "ti,omap3-uart"; 127 compatible = "ti,omap3-uart";
74 ti,hwmods = "uart1"; 128 ti,hwmods = "uart1";
@@ -113,5 +167,53 @@
113 #size-cells = <0>; 167 #size-cells = <0>;
114 ti,hwmods = "i2c3"; 168 ti,hwmods = "i2c3";
115 }; 169 };
170
171 mcspi1: spi@48098000 {
172 compatible = "ti,omap2-mcspi";
173 #address-cells = <1>;
174 #size-cells = <0>;
175 ti,hwmods = "mcspi1";
176 ti,spi-num-cs = <4>;
177 };
178
179 mcspi2: spi@4809a000 {
180 compatible = "ti,omap2-mcspi";
181 #address-cells = <1>;
182 #size-cells = <0>;
183 ti,hwmods = "mcspi2";
184 ti,spi-num-cs = <2>;
185 };
186
187 mcspi3: spi@480b8000 {
188 compatible = "ti,omap2-mcspi";
189 #address-cells = <1>;
190 #size-cells = <0>;
191 ti,hwmods = "mcspi3";
192 ti,spi-num-cs = <2>;
193 };
194
195 mcspi4: spi@480ba000 {
196 compatible = "ti,omap2-mcspi";
197 #address-cells = <1>;
198 #size-cells = <0>;
199 ti,hwmods = "mcspi4";
200 ti,spi-num-cs = <1>;
201 };
202
203 mmc1: mmc@4809c000 {
204 compatible = "ti,omap3-hsmmc";
205 ti,hwmods = "mmc1";
206 ti,dual-volt;
207 };
208
209 mmc2: mmc@480b4000 {
210 compatible = "ti,omap3-hsmmc";
211 ti,hwmods = "mmc2";
212 };
213
214 mmc3: mmc@480ad000 {
215 compatible = "ti,omap3-hsmmc";
216 ti,hwmods = "mmc3";
217 };
116 }; 218 };
117}; 219};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 9755ad5917f8..1efe0c587985 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -17,4 +17,75 @@
17 device_type = "memory"; 17 device_type = "memory";
18 reg = <0x80000000 0x40000000>; /* 1 GB */ 18 reg = <0x80000000 0x40000000>; /* 1 GB */
19 }; 19 };
20
21 leds {
22 compatible = "gpio-leds";
23 heartbeat {
24 label = "pandaboard::status1";
25 gpios = <&gpio1 7 0>;
26 linux,default-trigger = "heartbeat";
27 };
28
29 mmc {
30 label = "pandaboard::status2";
31 gpios = <&gpio1 8 0>;
32 linux,default-trigger = "mmc0";
33 };
34 };
35};
36
37&i2c1 {
38 clock-frequency = <400000>;
39
40 twl: twl@48 {
41 reg = <0x48>;
42 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
43 interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
44 interrupt-parent = <&gic>;
45 };
46};
47
48/include/ "twl6030.dtsi"
49
50&i2c2 {
51 clock-frequency = <400000>;
52};
53
54&i2c3 {
55 clock-frequency = <100000>;
56
57 /*
58 * Display monitor features are burnt in their EEPROM as EDID data.
59 * The EEPROM is connected as I2C slave device.
60 */
61 eeprom@50 {
62 compatible = "ti,eeprom";
63 reg = <0x50>;
64 };
65};
66
67&i2c4 {
68 clock-frequency = <400000>;
69};
70
71&mmc1 {
72 vmmc-supply = <&vmmc>;
73 bus-width = <8>;
74};
75
76&mmc2 {
77 status = "disable";
78};
79
80&mmc3 {
81 status = "disable";
82};
83
84&mmc4 {
85 status = "disable";
86};
87
88&mmc5 {
89 ti,non-removable;
90 bus-width = <4>;
20}; 91};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 63c6b2b2bf42..d08c4d137280 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -17,4 +17,144 @@
17 device_type = "memory"; 17 device_type = "memory";
18 reg = <0x80000000 0x40000000>; /* 1 GB */ 18 reg = <0x80000000 0x40000000>; /* 1 GB */
19 }; 19 };
20
21 vdd_eth: fixedregulator@0 {
22 compatible = "regulator-fixed";
23 regulator-name = "VDD_ETH";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
26 gpio = <&gpio2 16 0>; /* gpio line 48 */
27 enable-active-high;
28 regulator-boot-on;
29 };
30
31 leds {
32 compatible = "gpio-leds";
33 debug0 {
34 label = "omap4:green:debug0";
35 gpios = <&gpio2 29 0>; /* 61 */
36 };
37
38 debug1 {
39 label = "omap4:green:debug1";
40 gpios = <&gpio1 30 0>; /* 30 */
41 };
42
43 debug2 {
44 label = "omap4:green:debug2";
45 gpios = <&gpio1 7 0>; /* 7 */
46 };
47
48 debug3 {
49 label = "omap4:green:debug3";
50 gpios = <&gpio1 8 0>; /* 8 */
51 };
52
53 debug4 {
54 label = "omap4:green:debug4";
55 gpios = <&gpio2 18 0>; /* 50 */
56 };
57
58 user1 {
59 label = "omap4:blue:user";
60 gpios = <&gpio6 9 0>; /* 169 */
61 };
62
63 user2 {
64 label = "omap4:red:user";
65 gpios = <&gpio6 10 0>; /* 170 */
66 };
67
68 user3 {
69 label = "omap4:green:user";
70 gpios = <&gpio5 11 0>; /* 139 */
71 };
72 };
73};
74
75&i2c1 {
76 clock-frequency = <400000>;
77
78 twl: twl@48 {
79 reg = <0x48>;
80 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
81 interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
82 interrupt-parent = <&gic>;
83 };
84};
85
86/include/ "twl6030.dtsi"
87
88&i2c2 {
89 clock-frequency = <400000>;
90};
91
92&i2c3 {
93 clock-frequency = <400000>;
94
95 /*
96 * Temperature Sensor
97 * http://www.ti.com/lit/ds/symlink/tmp105.pdf
98 */
99 tmp105@48 {
100 compatible = "ti,tmp105";
101 reg = <0x48>;
102 };
103
104 /*
105 * Ambient Light Sensor
106 * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf
107 */
108 bh1780@29 {
109 compatible = "rohm,bh1780";
110 reg = <0x29>;
111 };
112};
113
114&i2c4 {
115 clock-frequency = <400000>;
116
117 /*
118 * 3-Axis Digital Compass
119 * http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf
120 */
121 hmc5843@1e {
122 compatible = "honeywell,hmc5843";
123 reg = <0x1e>;
124 };
125};
126
127&mcspi1 {
128 eth@0 {
129 compatible = "ks8851";
130 spi-max-frequency = <24000000>;
131 reg = <0>;
132 interrupt-parent = <&gpio2>;
133 interrupts = <2>; /* gpio line 34 */
134 vdd-supply = <&vdd_eth>;
135 };
136};
137
138&mmc1 {
139 vmmc-supply = <&vmmc>;
140 bus-width = <8>;
141};
142
143&mmc2 {
144 vmmc-supply = <&vaux1>;
145 bus-width = <8>;
146 ti,non-removable;
147};
148
149&mmc3 {
150 status = "disable";
151};
152
153&mmc4 {
154 status = "disable";
155};
156
157&mmc5 {
158 bus-width = <4>;
159 ti,non-removable;
20}; 160};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 3d35559e77bc..359c4979c8aa 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -104,6 +104,60 @@
104 <0x48240100 0x0100>; 104 <0x48240100 0x0100>;
105 }; 105 };
106 106
107 gpio1: gpio@4a310000 {
108 compatible = "ti,omap4-gpio";
109 ti,hwmods = "gpio1";
110 gpio-controller;
111 #gpio-cells = <2>;
112 interrupt-controller;
113 #interrupt-cells = <1>;
114 };
115
116 gpio2: gpio@48055000 {
117 compatible = "ti,omap4-gpio";
118 ti,hwmods = "gpio2";
119 gpio-controller;
120 #gpio-cells = <2>;
121 interrupt-controller;
122 #interrupt-cells = <1>;
123 };
124
125 gpio3: gpio@48057000 {
126 compatible = "ti,omap4-gpio";
127 ti,hwmods = "gpio3";
128 gpio-controller;
129 #gpio-cells = <2>;
130 interrupt-controller;
131 #interrupt-cells = <1>;
132 };
133
134 gpio4: gpio@48059000 {
135 compatible = "ti,omap4-gpio";
136 ti,hwmods = "gpio4";
137 gpio-controller;
138 #gpio-cells = <2>;
139 interrupt-controller;
140 #interrupt-cells = <1>;
141 };
142
143 gpio5: gpio@4805b000 {
144 compatible = "ti,omap4-gpio";
145 ti,hwmods = "gpio5";
146 gpio-controller;
147 #gpio-cells = <2>;
148 interrupt-controller;
149 #interrupt-cells = <1>;
150 };
151
152 gpio6: gpio@4805d000 {
153 compatible = "ti,omap4-gpio";
154 ti,hwmods = "gpio6";
155 gpio-controller;
156 #gpio-cells = <2>;
157 interrupt-controller;
158 #interrupt-cells = <1>;
159 };
160
107 uart1: serial@4806a000 { 161 uart1: serial@4806a000 {
108 compatible = "ti,omap4-uart"; 162 compatible = "ti,omap4-uart";
109 ti,hwmods = "uart1"; 163 ti,hwmods = "uart1";
@@ -155,5 +209,68 @@
155 #size-cells = <0>; 209 #size-cells = <0>;
156 ti,hwmods = "i2c4"; 210 ti,hwmods = "i2c4";
157 }; 211 };
212
213 mcspi1: spi@48098000 {
214 compatible = "ti,omap4-mcspi";
215 #address-cells = <1>;
216 #size-cells = <0>;
217 ti,hwmods = "mcspi1";
218 ti,spi-num-cs = <4>;
219 };
220
221 mcspi2: spi@4809a000 {
222 compatible = "ti,omap4-mcspi";
223 #address-cells = <1>;
224 #size-cells = <0>;
225 ti,hwmods = "mcspi2";
226 ti,spi-num-cs = <2>;
227 };
228
229 mcspi3: spi@480b8000 {
230 compatible = "ti,omap4-mcspi";
231 #address-cells = <1>;
232 #size-cells = <0>;
233 ti,hwmods = "mcspi3";
234 ti,spi-num-cs = <2>;
235 };
236
237 mcspi4: spi@480ba000 {
238 compatible = "ti,omap4-mcspi";
239 #address-cells = <1>;
240 #size-cells = <0>;
241 ti,hwmods = "mcspi4";
242 ti,spi-num-cs = <1>;
243 };
244
245 mmc1: mmc@4809c000 {
246 compatible = "ti,omap4-hsmmc";
247 ti,hwmods = "mmc1";
248 ti,dual-volt;
249 ti,needs-special-reset;
250 };
251
252 mmc2: mmc@480b4000 {
253 compatible = "ti,omap4-hsmmc";
254 ti,hwmods = "mmc2";
255 ti,needs-special-reset;
256 };
257
258 mmc3: mmc@480ad000 {
259 compatible = "ti,omap4-hsmmc";
260 ti,hwmods = "mmc3";
261 ti,needs-special-reset;
262 };
263
264 mmc4: mmc@480d1000 {
265 compatible = "ti,omap4-hsmmc";
266 ti,hwmods = "mmc4";
267 ti,needs-special-reset;
268 };
269
270 mmc5: mmc@480d5000 {
271 compatible = "ti,omap4-hsmmc";
272 ti,hwmods = "mmc5";
273 ti,needs-special-reset;
274 };
158 }; 275 };
159}; 276};
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
new file mode 100644
index 000000000000..0167e86314c0
--- /dev/null
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -0,0 +1,145 @@
1/*
2 * PHYTEC phyCORE-LPC3250 board
3 *
4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "lpc32xx.dtsi"
16
17/ {
18 model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
19 compatible = "phytec,phy3250", "nxp,lpc3250";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 device_type = "memory";
25 reg = <0 0x4000000>;
26 };
27
28 ahb {
29 mac: ethernet@31060000 {
30 phy-mode = "rmii";
31 use-iram;
32 };
33
34 /* Here, choose exactly one from: ohci, usbd */
35 ohci@31020000 {
36 transceiver = <&isp1301>;
37 status = "okay";
38 };
39
40/*
41 usbd@31020000 {
42 transceiver = <&isp1301>;
43 status = "okay";
44 };
45*/
46
47 clcd@31040000 {
48 status = "okay";
49 };
50
51 /* 64MB Flash via SLC NAND controller */
52 slc: flash@20020000 {
53 status = "okay";
54 #address-cells = <1>;
55 #size-cells = <1>;
56
57 mtd0@00000000 {
58 label = "phy3250-boot";
59 reg = <0x00000000 0x00064000>;
60 read-only;
61 };
62
63 mtd1@00064000 {
64 label = "phy3250-uboot";
65 reg = <0x00064000 0x00190000>;
66 read-only;
67 };
68
69 mtd2@001f4000 {
70 label = "phy3250-ubt-prms";
71 reg = <0x001f4000 0x00010000>;
72 };
73
74 mtd3@00204000 {
75 label = "phy3250-kernel";
76 reg = <0x00204000 0x00400000>;
77 };
78
79 mtd4@00604000 {
80 label = "phy3250-rootfs";
81 reg = <0x00604000 0x039fc000>;
82 };
83 };
84
85 apb {
86 i2c1: i2c@400A0000 {
87 clock-frequency = <100000>;
88
89 pcf8563: rtc@51 {
90 compatible = "nxp,pcf8563";
91 reg = <0x51>;
92 };
93
94 uda1380: uda1380@18 {
95 compatible = "nxp,uda1380";
96 reg = <0x18>;
97 power-gpio = <&gpio 0x59 0>;
98 reset-gpio = <&gpio 0x51 0>;
99 dac-clk = "wspll";
100 };
101 };
102
103 i2c2: i2c@400A8000 {
104 clock-frequency = <100000>;
105 };
106
107 i2cusb: i2c@31020300 {
108 clock-frequency = <100000>;
109
110 isp1301: usb-transceiver@2c {
111 compatible = "nxp,isp1301";
112 reg = <0x2c>;
113 };
114 };
115
116 ssp0: ssp@20084000 {
117 eeprom: at25@0 {
118 compatible = "atmel,at25";
119 };
120 };
121 };
122
123 fab {
124 tsc@40048000 {
125 status = "okay";
126 };
127 };
128 };
129
130 leds {
131 compatible = "gpio-leds";
132
133 led0 {
134 gpios = <&gpo_p3 1 1>; /* GPO_P3 1, GPIO 80, active low */
135 linux,default-trigger = "heartbeat";
136 default-state = "off";
137 };
138
139 led1 {
140 gpios = <&gpo_p3 14 1>; /* GPO_P3 14, GPIO 93, active low */
141 linux,default-trigger = "timer";
142 default-state = "off";
143 };
144 };
145};
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
index d32d5128f225..31a718696080 100644
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -18,13 +18,6 @@
18 i2c1 = &twsi2; 18 i2c1 = &twsi2;
19 }; 19 };
20 20
21 intc: intc-interrupt-controller@d4282000 {
22 compatible = "mrvl,mmp-intc", "mrvl,intc";
23 interrupt-controller;
24 #interrupt-cells = <1>;
25 reg = <0xd4282000 0x1000>;
26 };
27
28 soc { 21 soc {
29 #address-cells = <1>; 22 #address-cells = <1>;
30 #size-cells = <1>; 23 #size-cells = <1>;
@@ -32,6 +25,23 @@
32 interrupt-parent = <&intc>; 25 interrupt-parent = <&intc>;
33 ranges; 26 ranges;
34 27
28 axi@d4200000 { /* AXI */
29 compatible = "mrvl,axi-bus", "simple-bus";
30 #address-cells = <1>;
31 #size-cells = <1>;
32 reg = <0xd4200000 0x00200000>;
33 ranges;
34
35 intc: interrupt-controller@d4282000 {
36 compatible = "mrvl,mmp-intc";
37 interrupt-controller;
38 #interrupt-cells = <1>;
39 reg = <0xd4282000 0x1000>;
40 mrvl,intc-nr-irqs = <64>;
41 };
42
43 };
44
35 apb@d4000000 { /* APB */ 45 apb@d4000000 { /* APB */
36 compatible = "mrvl,apb-bus", "simple-bus"; 46 compatible = "mrvl,apb-bus", "simple-bus";
37 #address-cells = <1>; 47 #address-cells = <1>;
@@ -39,40 +49,65 @@
39 reg = <0xd4000000 0x00200000>; 49 reg = <0xd4000000 0x00200000>;
40 ranges; 50 ranges;
41 51
52 timer0: timer@d4014000 {
53 compatible = "mrvl,mmp-timer";
54 reg = <0xd4014000 0x100>;
55 interrupts = <13>;
56 };
57
42 uart1: uart@d4017000 { 58 uart1: uart@d4017000 {
43 compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; 59 compatible = "mrvl,mmp-uart";
44 reg = <0xd4017000 0x1000>; 60 reg = <0xd4017000 0x1000>;
45 interrupts = <27>; 61 interrupts = <27>;
46 status = "disabled"; 62 status = "disabled";
47 }; 63 };
48 64
49 uart2: uart@d4018000 { 65 uart2: uart@d4018000 {
50 compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; 66 compatible = "mrvl,mmp-uart";
51 reg = <0xd4018000 0x1000>; 67 reg = <0xd4018000 0x1000>;
52 interrupts = <28>; 68 interrupts = <28>;
53 status = "disabled"; 69 status = "disabled";
54 }; 70 };
55 71
56 uart3: uart@d4026000 { 72 uart3: uart@d4026000 {
57 compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; 73 compatible = "mrvl,mmp-uart";
58 reg = <0xd4026000 0x1000>; 74 reg = <0xd4026000 0x1000>;
59 interrupts = <29>; 75 interrupts = <29>;
60 status = "disabled"; 76 status = "disabled";
61 }; 77 };
62 78
63 gpio: gpio@d4019000 { 79 gpio@d4019000 {
64 compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio"; 80 compatible = "mrvl,mmp-gpio";
81 #address-cells = <1>;
82 #size-cells = <1>;
65 reg = <0xd4019000 0x1000>; 83 reg = <0xd4019000 0x1000>;
84 gpio-controller;
85 #gpio-cells = <2>;
66 interrupts = <49>; 86 interrupts = <49>;
67 interrupt-names = "gpio_mux"; 87 interrupt-names = "gpio_mux";
68 gpio-controller;
69 #gpio-cells = <1>;
70 interrupt-controller; 88 interrupt-controller;
71 #interrupt-cells = <1>; 89 #interrupt-cells = <1>;
90 ranges;
91
92 gcb0: gpio@d4019000 {
93 reg = <0xd4019000 0x4>;
94 };
95
96 gcb1: gpio@d4019004 {
97 reg = <0xd4019004 0x4>;
98 };
99
100 gcb2: gpio@d4019008 {
101 reg = <0xd4019008 0x4>;
102 };
103
104 gcb3: gpio@d4019100 {
105 reg = <0xd4019100 0x4>;
106 };
72 }; 107 };
73 108
74 twsi1: i2c@d4011000 { 109 twsi1: i2c@d4011000 {
75 compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c"; 110 compatible = "mrvl,mmp-twsi";
76 reg = <0xd4011000 0x1000>; 111 reg = <0xd4011000 0x1000>;
77 interrupts = <7>; 112 interrupts = <7>;
78 mrvl,i2c-fast-mode; 113 mrvl,i2c-fast-mode;
@@ -80,7 +115,7 @@
80 }; 115 };
81 116
82 twsi2: i2c@d4025000 { 117 twsi2: i2c@d4025000 {
83 compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c"; 118 compatible = "mrvl,mmp-twsi";
84 reg = <0xd4025000 0x1000>; 119 reg = <0xd4025000 0x1000>;
85 interrupts = <58>; 120 interrupts = <58>;
86 status = "disabled"; 121 status = "disabled";
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
new file mode 100644
index 000000000000..e92be5a474e7
--- /dev/null
+++ b/arch/arm/boot/dts/pxa910-dkb.dts
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/dts-v1/;
11/include/ "pxa910.dtsi"
12
13/ {
14 model = "Marvell PXA910 DKB Development Board";
15 compatible = "mrvl,pxa910-dkb", "mrvl,pxa910";
16
17 chosen {
18 bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
19 };
20
21 memory {
22 reg = <0x00000000 0x10000000>;
23 };
24
25 soc {
26 apb@d4000000 {
27 uart1: uart@d4017000 {
28 status = "okay";
29 };
30 twsi1: i2c@d4011000 {
31 status = "okay";
32 };
33 rtc: rtc@d4010000 {
34 status = "okay";
35 };
36 };
37 };
38};
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
new file mode 100644
index 000000000000..aebf32de73b4
--- /dev/null
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -0,0 +1,140 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 aliases {
14 serial0 = &uart1;
15 serial1 = &uart2;
16 serial2 = &uart3;
17 i2c0 = &twsi1;
18 i2c1 = &twsi2;
19 };
20
21 soc {
22 #address-cells = <1>;
23 #size-cells = <1>;
24 compatible = "simple-bus";
25 interrupt-parent = <&intc>;
26 ranges;
27
28 axi@d4200000 { /* AXI */
29 compatible = "mrvl,axi-bus", "simple-bus";
30 #address-cells = <1>;
31 #size-cells = <1>;
32 reg = <0xd4200000 0x00200000>;
33 ranges;
34
35 intc: interrupt-controller@d4282000 {
36 compatible = "mrvl,mmp-intc";
37 interrupt-controller;
38 #interrupt-cells = <1>;
39 reg = <0xd4282000 0x1000>;
40 mrvl,intc-nr-irqs = <64>;
41 };
42
43 };
44
45 apb@d4000000 { /* APB */
46 compatible = "mrvl,apb-bus", "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 reg = <0xd4000000 0x00200000>;
50 ranges;
51
52 timer0: timer@d4014000 {
53 compatible = "mrvl,mmp-timer";
54 reg = <0xd4014000 0x100>;
55 interrupts = <13>;
56 };
57
58 timer1: timer@d4016000 {
59 compatible = "mrvl,mmp-timer";
60 reg = <0xd4016000 0x100>;
61 interrupts = <29>;
62 status = "disabled";
63 };
64
65 uart1: uart@d4017000 {
66 compatible = "mrvl,mmp-uart";
67 reg = <0xd4017000 0x1000>;
68 interrupts = <27>;
69 status = "disabled";
70 };
71
72 uart2: uart@d4018000 {
73 compatible = "mrvl,mmp-uart";
74 reg = <0xd4018000 0x1000>;
75 interrupts = <28>;
76 status = "disabled";
77 };
78
79 uart3: uart@d4036000 {
80 compatible = "mrvl,mmp-uart";
81 reg = <0xd4036000 0x1000>;
82 interrupts = <59>;
83 status = "disabled";
84 };
85
86 gpio@d4019000 {
87 compatible = "mrvl,mmp-gpio";
88 #address-cells = <1>;
89 #size-cells = <1>;
90 reg = <0xd4019000 0x1000>;
91 gpio-controller;
92 #gpio-cells = <2>;
93 interrupts = <49>;
94 interrupt-names = "gpio_mux";
95 interrupt-controller;
96 #interrupt-cells = <1>;
97 ranges;
98
99 gcb0: gpio@d4019000 {
100 reg = <0xd4019000 0x4>;
101 };
102
103 gcb1: gpio@d4019004 {
104 reg = <0xd4019004 0x4>;
105 };
106
107 gcb2: gpio@d4019008 {
108 reg = <0xd4019008 0x4>;
109 };
110
111 gcb3: gpio@d4019100 {
112 reg = <0xd4019100 0x4>;
113 };
114 };
115
116 twsi1: i2c@d4011000 {
117 compatible = "mrvl,mmp-twsi";
118 reg = <0xd4011000 0x1000>;
119 interrupts = <7>;
120 mrvl,i2c-fast-mode;
121 status = "disabled";
122 };
123
124 twsi2: i2c@d4037000 {
125 compatible = "mrvl,mmp-twsi";
126 reg = <0xd4037000 0x1000>;
127 interrupts = <54>;
128 status = "disabled";
129 };
130
131 rtc: rtc@d4010000 {
132 compatible = "mrvl,mmp-rtc";
133 reg = <0xd4010000 0x1000>;
134 interrupts = <5 6>;
135 interrupt-names = "rtc 1Hz", "rtc alarm";
136 status = "disabled";
137 };
138 };
139 };
140};
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
new file mode 100644
index 000000000000..a7505a95a3b7
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -0,0 +1,22 @@
1/*
2 * Device Tree Source for the armadillo 800 eva board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12/include/ "skeleton.dtsi"
13
14/ {
15 model = "armadillo 800 eva";
16 compatible = "renesas,armadillo800eva";
17
18 memory {
19 device_type = "memory";
20 reg = <0x40000000 0x20000000>;
21 };
22};
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
new file mode 100644
index 000000000000..677fc603f8b3
--- /dev/null
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -0,0 +1,21 @@
1/*
2 * Device Tree Source for the sh7372 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "renesas,sh7372";
15
16 cpus {
17 cpu@0 {
18 compatible = "arm,cortex-a8";
19 };
20 };
21};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
new file mode 100644
index 000000000000..bcb911951978
--- /dev/null
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -0,0 +1,22 @@
1/*
2 * Device Tree Source for the KZM-A9-GT board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12/include/ "skeleton.dtsi"
13
14/ {
15 model = "KZM-A9-GT";
16 compatible = "renesas,kzm9g", "renesas,sh73a0";
17
18 memory {
19 device_type = "memory";
20 reg = <0x41000000 0x1e800000>;
21 };
22};
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index 359c6d679156..d99dc04f0d91 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -30,35 +30,35 @@
30 wakeup = <1>; 30 wakeup = <1>;
31 linux,code = <2>; 31 linux,code = <2>;
32 label = "userpb"; 32 label = "userpb";
33 gpios = <&gpio1 0>; 33 gpios = <&gpio1 0 0>;
34 }; 34 };
35 button@2 { 35 button@2 {
36 debounce_interval = <50>; 36 debounce_interval = <50>;
37 wakeup = <1>; 37 wakeup = <1>;
38 linux,code = <3>; 38 linux,code = <3>;
39 label = "userpb"; 39 label = "extkb1";
40 gpios = <&gpio4 23>; 40 gpios = <&gpio4 23 0>;
41 }; 41 };
42 button@3 { 42 button@3 {
43 debounce_interval = <50>; 43 debounce_interval = <50>;
44 wakeup = <1>; 44 wakeup = <1>;
45 linux,code = <4>; 45 linux,code = <4>;
46 label = "userpb"; 46 label = "extkb2";
47 gpios = <&gpio4 23>; 47 gpios = <&gpio4 24 0>;
48 }; 48 };
49 button@4 { 49 button@4 {
50 debounce_interval = <50>; 50 debounce_interval = <50>;
51 wakeup = <1>; 51 wakeup = <1>;
52 linux,code = <5>; 52 linux,code = <5>;
53 label = "userpb"; 53 label = "extkb3";
54 gpios = <&gpio5 1>; 54 gpios = <&gpio5 1 0>;
55 }; 55 };
56 button@5 { 56 button@5 {
57 debounce_interval = <50>; 57 debounce_interval = <50>;
58 wakeup = <1>; 58 wakeup = <1>;
59 linux,code = <6>; 59 linux,code = <6>;
60 label = "userpb"; 60 label = "extkb4";
61 gpios = <&gpio5 2>; 61 gpios = <&gpio5 2 0>;
62 }; 62 };
63 }; 63 };
64 64
@@ -73,17 +73,19 @@
73 soc-u9500 { 73 soc-u9500 {
74 74
75 external-bus@50000000 { 75 external-bus@50000000 {
76 compatible = "simple-bus"; 76 status = "okay";
77 reg = <0x50000000 0x10000000>; 77
78 #address-cells = <1>; 78 ethernet@0 {
79 #size-cells = <1>; 79 compatible = "smsc,lan9115";
80 ranges; 80 reg = <0 0x10000>;
81 81 interrupts = <12 0x1>;
82 ethernet@50000000 {
83 compatible = "smsc,9111";
84 reg = <0x50000000 0x10000>;
85 interrupts = <12>;
86 interrupt-parent = <&gpio4>; 82 interrupt-parent = <&gpio4>;
83
84 reg-shift = <1>;
85 reg-io-width = <2>;
86 smsc,force-internal-phy;
87 smsc,irq-active-high;
88 smsc,irq-push-pull;
87 }; 89 };
88 }; 90 };
89 91
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index ac3fb7558459..36321bceec46 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -7,64 +7,166 @@
7 compatible = "nvidia,cardhu", "nvidia,tegra30"; 7 compatible = "nvidia,cardhu", "nvidia,tegra30";
8 8
9 memory { 9 memory {
10 reg = < 0x80000000 0x40000000 >; 10 reg = <0x80000000 0x40000000>;
11 }; 11 };
12 12
13 serial@70006000 { 13 pinmux {
14 clock-frequency = < 408000000 >; 14 pinctrl-names = "default";
15 }; 15 pinctrl-0 = <&state_default>;
16 16
17 serial@70006040 { 17 state_default: pinmux {
18 status = "disable"; 18 sdmmc1_clk_pz0 {
19 }; 19 nvidia,pins = "sdmmc1_clk_pz0";
20 20 nvidia,function = "sdmmc1";
21 serial@70006200 { 21 nvidia,pull = <0>;
22 status = "disable"; 22 nvidia,tristate = <0>;
23 }; 23 };
24 24 sdmmc1_cmd_pz1 {
25 serial@70006300 { 25 nvidia,pins = "sdmmc1_cmd_pz1",
26 status = "disable"; 26 "sdmmc1_dat0_py7",
27 "sdmmc1_dat1_py6",
28 "sdmmc1_dat2_py5",
29 "sdmmc1_dat3_py4";
30 nvidia,function = "sdmmc1";
31 nvidia,pull = <2>;
32 nvidia,tristate = <0>;
33 };
34 sdmmc4_clk_pcc4 {
35 nvidia,pins = "sdmmc4_clk_pcc4",
36 "sdmmc4_rst_n_pcc3";
37 nvidia,function = "sdmmc4";
38 nvidia,pull = <0>;
39 nvidia,tristate = <0>;
40 };
41 sdmmc4_dat0_paa0 {
42 nvidia,pins = "sdmmc4_dat0_paa0",
43 "sdmmc4_dat1_paa1",
44 "sdmmc4_dat2_paa2",
45 "sdmmc4_dat3_paa3",
46 "sdmmc4_dat4_paa4",
47 "sdmmc4_dat5_paa5",
48 "sdmmc4_dat6_paa6",
49 "sdmmc4_dat7_paa7";
50 nvidia,function = "sdmmc4";
51 nvidia,pull = <2>;
52 nvidia,tristate = <0>;
53 };
54 dap2_fs_pa2 {
55 nvidia,pins = "dap2_fs_pa2",
56 "dap2_sclk_pa3",
57 "dap2_din_pa4",
58 "dap2_dout_pa5";
59 nvidia,function = "i2s1";
60 nvidia,pull = <0>;
61 nvidia,tristate = <0>;
62 };
63 };
27 }; 64 };
28 65
29 serial@70006400 { 66 serial@70006000 {
30 status = "disable"; 67 status = "okay";
68 clock-frequency = <408000000>;
31 }; 69 };
32 70
33 i2c@7000c000 { 71 i2c@7000c000 {
72 status = "okay";
34 clock-frequency = <100000>; 73 clock-frequency = <100000>;
35 }; 74 };
36 75
37 i2c@7000c400 { 76 i2c@7000c400 {
77 status = "okay";
38 clock-frequency = <100000>; 78 clock-frequency = <100000>;
39 }; 79 };
40 80
41 i2c@7000c500 { 81 i2c@7000c500 {
82 status = "okay";
42 clock-frequency = <100000>; 83 clock-frequency = <100000>;
84
85 /* ALS and Proximity sensor */
86 isl29028@44 {
87 compatible = "isil,isl29028";
88 reg = <0x44>;
89 interrupt-parent = <&gpio>;
90 interrupts = <88 0x04>; /*gpio PL0 */
91 };
43 }; 92 };
44 93
45 i2c@7000c700 { 94 i2c@7000c700 {
95 status = "okay";
46 clock-frequency = <100000>; 96 clock-frequency = <100000>;
47 }; 97 };
48 98
49 i2c@7000d000 { 99 i2c@7000d000 {
100 status = "okay";
50 clock-frequency = <100000>; 101 clock-frequency = <100000>;
102
103 wm8903: wm8903@1a {
104 compatible = "wlf,wm8903";
105 reg = <0x1a>;
106 interrupt-parent = <&gpio>;
107 interrupts = <179 0x04>; /* gpio PW3 */
108
109 gpio-controller;
110 #gpio-cells = <2>;
111
112 micdet-cfg = <0>;
113 micdet-delay = <100>;
114 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
115 };
116
117 tps62361 {
118 compatible = "ti,tps62361";
119 reg = <0x60>;
120
121 regulator-name = "tps62361-vout";
122 regulator-min-microvolt = <500000>;
123 regulator-max-microvolt = <1500000>;
124 regulator-boot-on;
125 regulator-always-on;
126 ti,vsel0-state-high;
127 ti,vsel1-state-high;
128 };
129 };
130
131 ahub {
132 i2s@70080400 {
133 status = "okay";
134 };
51 }; 135 };
52 136
53 sdhci@78000000 { 137 sdhci@78000000 {
138 status = "okay";
54 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 139 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
55 wp-gpios = <&gpio 155 0>; /* gpio PT3 */ 140 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
56 power-gpios = <&gpio 31 0>; /* gpio PD7 */ 141 power-gpios = <&gpio 31 0>; /* gpio PD7 */
142 bus-width = <4>;
57 }; 143 };
58 144
59 sdhci@78000200 { 145 sdhci@78000600 {
60 status = "disable"; 146 status = "okay";
61 }; 147 support-8bit;
62 148 bus-width = <8>;
63 sdhci@78000400 {
64 status = "disable";
65 }; 149 };
66 150
67 sdhci@78000400 { 151 sound {
68 support-8bit; 152 compatible = "nvidia,tegra-audio-wm8903-cardhu",
153 "nvidia,tegra-audio-wm8903";
154 nvidia,model = "NVIDIA Tegra Cardhu";
155
156 nvidia,audio-routing =
157 "Headphone Jack", "HPOUTR",
158 "Headphone Jack", "HPOUTL",
159 "Int Spk", "ROP",
160 "Int Spk", "RON",
161 "Int Spk", "LOP",
162 "Int Spk", "LON",
163 "Mic Jack", "MICBIAS",
164 "IN1L", "Mic Jack";
165
166 nvidia,i2s-controller = <&tegra_i2s1>;
167 nvidia,audio-codec = <&wm8903>;
168
169 nvidia,spkr-en-gpios = <&wm8903 2 0>;
170 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
69 }; 171 };
70}; 172};
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 6e8447dc0202..7de701365fce 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -6,46 +6,309 @@
6 model = "NVIDIA Tegra2 Harmony evaluation board"; 6 model = "NVIDIA Tegra2 Harmony evaluation board";
7 compatible = "nvidia,harmony", "nvidia,tegra20"; 7 compatible = "nvidia,harmony", "nvidia,tegra20";
8 8
9 memory@0 { 9 memory {
10 reg = < 0x00000000 0x40000000 >; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 pmc@7000f400 { 13 pinmux {
14 nvidia,invert-interrupt; 14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
32 "spia", "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
67 ddc {
68 nvidia,pins = "ddc";
69 nvidia,function = "i2c2";
70 };
71 dta {
72 nvidia,pins = "dta", "dtd";
73 nvidia,function = "sdio2";
74 };
75 dtb {
76 nvidia,pins = "dtb", "dtc", "dte";
77 nvidia,function = "rsvd1";
78 };
79 dtf {
80 nvidia,pins = "dtf";
81 nvidia,function = "i2c3";
82 };
83 gmc {
84 nvidia,pins = "gmc";
85 nvidia,function = "uartd";
86 };
87 gpu7 {
88 nvidia,pins = "gpu7";
89 nvidia,function = "rtck";
90 };
91 gpv {
92 nvidia,pins = "gpv", "slxa", "slxk";
93 nvidia,function = "pcie";
94 };
95 hdint {
96 nvidia,pins = "hdint", "pta";
97 nvidia,function = "hdmi";
98 };
99 i2cp {
100 nvidia,pins = "i2cp";
101 nvidia,function = "i2cp";
102 };
103 irrx {
104 nvidia,pins = "irrx", "irtx";
105 nvidia,function = "uarta";
106 };
107 kbca {
108 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
109 "kbce", "kbcf";
110 nvidia,function = "kbc";
111 };
112 lcsn {
113 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
114 "ld3", "ld4", "ld5", "ld6", "ld7",
115 "ld8", "ld9", "ld10", "ld11", "ld12",
116 "ld13", "ld14", "ld15", "ld16", "ld17",
117 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
118 "lhs", "lm0", "lm1", "lpp", "lpw0",
119 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
120 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
121 "lvs";
122 nvidia,function = "displaya";
123 };
124 owc {
125 nvidia,pins = "owc", "spdi", "spdo", "uac";
126 nvidia,function = "rsvd2";
127 };
128 pmc {
129 nvidia,pins = "pmc";
130 nvidia,function = "pwr_on";
131 };
132 rm {
133 nvidia,pins = "rm";
134 nvidia,function = "i2c1";
135 };
136 sdb {
137 nvidia,pins = "sdb", "sdc", "sdd";
138 nvidia,function = "pwm";
139 };
140 sdio1 {
141 nvidia,pins = "sdio1";
142 nvidia,function = "sdio1";
143 };
144 slxc {
145 nvidia,pins = "slxc", "slxd";
146 nvidia,function = "spdif";
147 };
148 spid {
149 nvidia,pins = "spid", "spie", "spif";
150 nvidia,function = "spi1";
151 };
152 spig {
153 nvidia,pins = "spig", "spih";
154 nvidia,function = "spi2_alt";
155 };
156 uaa {
157 nvidia,pins = "uaa", "uab", "uda";
158 nvidia,function = "ulpi";
159 };
160 uad {
161 nvidia,pins = "uad";
162 nvidia,function = "irda";
163 };
164 uca {
165 nvidia,pins = "uca", "ucb";
166 nvidia,function = "uartc";
167 };
168 conf_ata {
169 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
170 "cdev1", "cdev2", "dap1", "dtb", "gma",
171 "gmb", "gmc", "gmd", "gme", "gpu7",
172 "gpv", "i2cp", "pta", "rm", "slxa",
173 "slxk", "spia", "spib", "uac";
174 nvidia,pull = <0>;
175 nvidia,tristate = <0>;
176 };
177 conf_ck32 {
178 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
179 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
180 nvidia,pull = <0>;
181 };
182 conf_csus {
183 nvidia,pins = "csus", "spid", "spif";
184 nvidia,pull = <1>;
185 nvidia,tristate = <1>;
186 };
187 conf_crtp {
188 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
189 "dtc", "dte", "dtf", "gpu", "sdio1",
190 "slxc", "slxd", "spdi", "spdo", "spig",
191 "uda";
192 nvidia,pull = <0>;
193 nvidia,tristate = <1>;
194 };
195 conf_ddc {
196 nvidia,pins = "ddc", "dta", "dtd", "kbca",
197 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
198 "sdc";
199 nvidia,pull = <2>;
200 nvidia,tristate = <0>;
201 };
202 conf_hdint {
203 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
204 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
205 "lvp0", "owc", "sdb";
206 nvidia,tristate = <1>;
207 };
208 conf_irrx {
209 nvidia,pins = "irrx", "irtx", "sdd", "spic",
210 "spie", "spih", "uaa", "uab", "uad",
211 "uca", "ucb";
212 nvidia,pull = <2>;
213 nvidia,tristate = <1>;
214 };
215 conf_lc {
216 nvidia,pins = "lc", "ls";
217 nvidia,pull = <2>;
218 };
219 conf_ld0 {
220 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
221 "ld5", "ld6", "ld7", "ld8", "ld9",
222 "ld10", "ld11", "ld12", "ld13", "ld14",
223 "ld15", "ld16", "ld17", "ldi", "lhp0",
224 "lhp1", "lhp2", "lhs", "lm0", "lpp",
225 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
226 "lvs", "pmc";
227 nvidia,tristate = <0>;
228 };
229 conf_ld17_0 {
230 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
231 "ld23_22";
232 nvidia,pull = <1>;
233 };
234 };
235 };
236
237 i2s@70002800 {
238 status = "okay";
239 };
240
241 serial@70006300 {
242 status = "okay";
243 clock-frequency = <216000000>;
15 }; 244 };
16 245
17 i2c@7000c000 { 246 i2c@7000c000 {
247 status = "okay";
18 clock-frequency = <400000>; 248 clock-frequency = <400000>;
19 249
20 wm8903: wm8903@1a { 250 wm8903: wm8903@1a {
21 compatible = "wlf,wm8903"; 251 compatible = "wlf,wm8903";
22 reg = <0x1a>; 252 reg = <0x1a>;
23 interrupt-parent = <&gpio>; 253 interrupt-parent = <&gpio>;
24 interrupts = < 187 0x04 >; 254 interrupts = <187 0x04>;
25 255
26 gpio-controller; 256 gpio-controller;
27 #gpio-cells = <2>; 257 #gpio-cells = <2>;
28 258
29 micdet-cfg = <0>; 259 micdet-cfg = <0>;
30 micdet-delay = <100>; 260 micdet-delay = <100>;
31 gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; 261 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
32 }; 262 };
33 }; 263 };
34 264
35 i2c@7000c400 { 265 i2c@7000c400 {
266 status = "okay";
36 clock-frequency = <400000>; 267 clock-frequency = <400000>;
37 }; 268 };
38 269
39 i2c@7000c500 { 270 i2c@7000c500 {
271 status = "okay";
40 clock-frequency = <400000>; 272 clock-frequency = <400000>;
41 }; 273 };
42 274
43 i2c@7000d000 { 275 i2c@7000d000 {
276 status = "okay";
44 clock-frequency = <400000>; 277 clock-frequency = <400000>;
45 }; 278 };
46 279
47 i2s@70002a00 { 280 pmc {
48 status = "disable"; 281 nvidia,invert-interrupt;
282 };
283
284 usb@c5000000 {
285 status = "okay";
286 };
287
288 usb@c5004000 {
289 status = "okay";
290 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
291 };
292
293 usb@c5008000 {
294 status = "okay";
295 };
296
297 sdhci@c8000200 {
298 status = "okay";
299 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
300 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
301 power-gpios = <&gpio 155 0>; /* gpio PT3 */
302 bus-width = <4>;
303 };
304
305 sdhci@c8000600 {
306 status = "okay";
307 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
308 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
309 power-gpios = <&gpio 70 0>; /* gpio PI6 */
310 support-8bit;
311 bus-width = <8>;
49 }; 312 };
50 313
51 sound { 314 sound {
@@ -71,45 +334,4 @@
71 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ 334 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
72 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ 335 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
73 }; 336 };
74
75 serial@70006000 {
76 status = "disable";
77 };
78
79 serial@70006040 {
80 status = "disable";
81 };
82
83 serial@70006200 {
84 status = "disable";
85 };
86
87 serial@70006300 {
88 clock-frequency = < 216000000 >;
89 };
90
91 serial@70006400 {
92 status = "disable";
93 };
94
95 sdhci@c8000000 {
96 status = "disable";
97 };
98
99 sdhci@c8000200 {
100 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
101 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
102 power-gpios = <&gpio 155 0>; /* gpio PT3 */
103 };
104
105 sdhci@c8000400 {
106 status = "disable";
107 };
108
109 sdhci@c8000600 {
110 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
111 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
112 power-gpios = <&gpio 70 0>; /* gpio PI6 */
113 support-8bit;
114 };
115}; 337};
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 6c02abb469d4..bfeb117d5aea 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -6,11 +6,242 @@
6 model = "Toshiba AC100 / Dynabook AZ"; 6 model = "Toshiba AC100 / Dynabook AZ";
7 compatible = "compal,paz00", "nvidia,tegra20"; 7 compatible = "compal,paz00", "nvidia,tegra20";
8 8
9 memory@0 { 9 memory {
10 reg = <0x00000000 0x20000000>; 10 reg = <0x00000000 0x20000000>;
11 }; 11 };
12 12
13 pinmux {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata", "atc", "atd", "ate",
20 "dap2", "gmb", "gmc", "gmd", "spia",
21 "spib", "spic", "spid", "spie";
22 nvidia,function = "gmi";
23 };
24 atb {
25 nvidia,pins = "atb", "gma", "gme";
26 nvidia,function = "sdio4";
27 };
28 cdev1 {
29 nvidia,pins = "cdev1";
30 nvidia,function = "plla_out";
31 };
32 cdev2 {
33 nvidia,pins = "cdev2";
34 nvidia,function = "pllp_out4";
35 };
36 crtp {
37 nvidia,pins = "crtp";
38 nvidia,function = "crt";
39 };
40 csus {
41 nvidia,pins = "csus";
42 nvidia,function = "pllc_out1";
43 };
44 dap1 {
45 nvidia,pins = "dap1";
46 nvidia,function = "dap1";
47 };
48 dap3 {
49 nvidia,pins = "dap3";
50 nvidia,function = "dap3";
51 };
52 dap4 {
53 nvidia,pins = "dap4";
54 nvidia,function = "dap4";
55 };
56 ddc {
57 nvidia,pins = "ddc";
58 nvidia,function = "i2c2";
59 };
60 dta {
61 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
62 nvidia,function = "rsvd1";
63 };
64 dtf {
65 nvidia,pins = "dtf";
66 nvidia,function = "i2c3";
67 };
68 gpu {
69 nvidia,pins = "gpu", "sdb", "sdd";
70 nvidia,function = "pwm";
71 };
72 gpu7 {
73 nvidia,pins = "gpu7";
74 nvidia,function = "rtck";
75 };
76 gpv {
77 nvidia,pins = "gpv", "slxa", "slxk";
78 nvidia,function = "pcie";
79 };
80 hdint {
81 nvidia,pins = "hdint", "pta";
82 nvidia,function = "hdmi";
83 };
84 i2cp {
85 nvidia,pins = "i2cp";
86 nvidia,function = "i2cp";
87 };
88 irrx {
89 nvidia,pins = "irrx", "irtx";
90 nvidia,function = "uarta";
91 };
92 kbca {
93 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
94 nvidia,function = "kbc";
95 };
96 kbcb {
97 nvidia,pins = "kbcb", "kbcd";
98 nvidia,function = "sdio2";
99 };
100 lcsn {
101 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
102 "ld3", "ld4", "ld5", "ld6", "ld7",
103 "ld8", "ld9", "ld10", "ld11", "ld12",
104 "ld13", "ld14", "ld15", "ld16", "ld17",
105 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
106 "lhs", "lm0", "lm1", "lpp", "lpw0",
107 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
108 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
109 "lvs";
110 nvidia,function = "displaya";
111 };
112 owc {
113 nvidia,pins = "owc";
114 nvidia,function = "owr";
115 };
116 pmc {
117 nvidia,pins = "pmc";
118 nvidia,function = "pwr_on";
119 };
120 rm {
121 nvidia,pins = "rm";
122 nvidia,function = "i2c1";
123 };
124 sdc {
125 nvidia,pins = "sdc";
126 nvidia,function = "twc";
127 };
128 sdio1 {
129 nvidia,pins = "sdio1";
130 nvidia,function = "sdio1";
131 };
132 slxc {
133 nvidia,pins = "slxc", "slxd";
134 nvidia,function = "spi4";
135 };
136 spdi {
137 nvidia,pins = "spdi", "spdo";
138 nvidia,function = "rsvd2";
139 };
140 spif {
141 nvidia,pins = "spif", "uac";
142 nvidia,function = "rsvd4";
143 };
144 spig {
145 nvidia,pins = "spig", "spih";
146 nvidia,function = "spi2_alt";
147 };
148 uaa {
149 nvidia,pins = "uaa", "uab", "uda";
150 nvidia,function = "ulpi";
151 };
152 uad {
153 nvidia,pins = "uad";
154 nvidia,function = "spdif";
155 };
156 uca {
157 nvidia,pins = "uca", "ucb";
158 nvidia,function = "uartc";
159 };
160 conf_ata {
161 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
162 "cdev1", "cdev2", "dap1", "dap2", "dtf",
163 "gma", "gmb", "gmc", "gmd", "gme",
164 "gpu", "gpu7", "gpv", "i2cp", "pta",
165 "rm", "sdio1", "slxk", "spdo", "uac",
166 "uda";
167 nvidia,pull = <0>;
168 nvidia,tristate = <0>;
169 };
170 conf_ck32 {
171 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
172 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
173 nvidia,pull = <0>;
174 };
175 conf_crtp {
176 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
177 "dtc", "dte", "slxa", "slxc", "slxd",
178 "spdi";
179 nvidia,pull = <0>;
180 nvidia,tristate = <1>;
181 };
182 conf_csus {
183 nvidia,pins = "csus", "spia", "spib", "spid",
184 "spif";
185 nvidia,pull = <1>;
186 nvidia,tristate = <1>;
187 };
188 conf_ddc {
189 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
190 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
191 "spic", "spig", "uaa", "uab";
192 nvidia,pull = <2>;
193 nvidia,tristate = <0>;
194 };
195 conf_dta {
196 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
197 "spie", "spih", "uad", "uca", "ucb";
198 nvidia,pull = <2>;
199 nvidia,tristate = <1>;
200 };
201 conf_hdint {
202 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
203 "ld3", "ld4", "ld5", "ld6", "ld7",
204 "ld8", "ld9", "ld10", "ld11", "ld12",
205 "ld13", "ld14", "ld15", "ld16", "ld17",
206 "ldc", "ldi", "lhs", "lsc0", "lspi",
207 "lvs", "pmc";
208 nvidia,tristate = <0>;
209 };
210 conf_lc {
211 nvidia,pins = "lc", "ls";
212 nvidia,pull = <2>;
213 };
214 conf_lcsn {
215 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
216 "lm0", "lm1", "lpp", "lpw0", "lpw1",
217 "lpw2", "lsc1", "lsck", "lsda", "lsdi",
218 "lvp0", "lvp1", "sdb";
219 nvidia,tristate = <1>;
220 };
221 conf_ld17_0 {
222 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
223 "ld23_22";
224 nvidia,pull = <1>;
225 };
226 };
227 };
228
229 i2s@70002800 {
230 status = "okay";
231 };
232
233 serial@70006000 {
234 status = "okay";
235 clock-frequency = <216000000>;
236 };
237
238 serial@70006200 {
239 status = "okay";
240 clock-frequency = <216000000>;
241 };
242
13 i2c@7000c000 { 243 i2c@7000c000 {
244 status = "okay";
14 clock-frequency = <400000>; 245 clock-frequency = <400000>;
15 246
16 alc5632: alc5632@1e { 247 alc5632: alc5632@1e {
@@ -22,25 +253,23 @@
22 }; 253 };
23 254
24 i2c@7000c400 { 255 i2c@7000c400 {
256 status = "okay";
25 clock-frequency = <400000>; 257 clock-frequency = <400000>;
26 }; 258 };
27 259
28 i2c@7000c500 { 260 nvec {
29 status = "disable";
30 };
31
32 nvec@7000c500 {
33 #address-cells = <1>;
34 #size-cells = <0>;
35 compatible = "nvidia,nvec"; 261 compatible = "nvidia,nvec";
36 reg = <0x7000C500 0x100>; 262 reg = <0x7000c500 0x100>;
37 interrupts = <0 92 0x04>; 263 interrupts = <0 92 0x04>;
264 #address-cells = <1>;
265 #size-cells = <0>;
38 clock-frequency = <80000>; 266 clock-frequency = <80000>;
39 request-gpios = <&gpio 170 0>; 267 request-gpios = <&gpio 170 0>; /* gpio PV2 */
40 slave-addr = <138>; 268 slave-addr = <138>;
41 }; 269 };
42 270
43 i2c@7000d000 { 271 i2c@7000d000 {
272 status = "okay";
44 clock-frequency = <400000>; 273 clock-frequency = <400000>;
45 274
46 adt7461@4c { 275 adt7461@4c {
@@ -49,66 +278,31 @@
49 }; 278 };
50 }; 279 };
51 280
52 i2s@70002a00 { 281 usb@c5000000 {
53 status = "disable"; 282 status = "okay";
54 };
55
56 sound {
57 compatible = "nvidia,tegra-audio-alc5632-paz00",
58 "nvidia,tegra-audio-alc5632";
59
60 nvidia,model = "Compal PAZ00";
61
62 nvidia,audio-routing =
63 "Int Spk", "SPKOUT",
64 "Int Spk", "SPKOUTN",
65 "Headset Mic", "MICBIAS1",
66 "MIC1", "Headset Mic",
67 "Headset Stereophone", "HPR",
68 "Headset Stereophone", "HPL",
69 "DMICDAT", "Digital Mic";
70
71 nvidia,audio-codec = <&alc5632>;
72 nvidia,i2s-controller = <&tegra_i2s1>;
73 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
74 };
75
76 serial@70006000 {
77 clock-frequency = <216000000>;
78 }; 283 };
79 284
80 serial@70006040 { 285 usb@c5004000 {
81 status = "disable"; 286 status = "okay";
287 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
82 }; 288 };
83 289
84 serial@70006200 { 290 usb@c5008000 {
85 clock-frequency = <216000000>; 291 status = "okay";
86 };
87
88 serial@70006300 {
89 status = "disable";
90 };
91
92 serial@70006400 {
93 status = "disable";
94 }; 292 };
95 293
96 sdhci@c8000000 { 294 sdhci@c8000000 {
295 status = "okay";
97 cd-gpios = <&gpio 173 0>; /* gpio PV5 */ 296 cd-gpios = <&gpio 173 0>; /* gpio PV5 */
98 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 297 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
99 power-gpios = <&gpio 169 0>; /* gpio PV1 */ 298 power-gpios = <&gpio 169 0>; /* gpio PV1 */
100 }; 299 bus-width = <4>;
101
102 sdhci@c8000200 {
103 status = "disable";
104 };
105
106 sdhci@c8000400 {
107 status = "disable";
108 }; 300 };
109 301
110 sdhci@c8000600 { 302 sdhci@c8000600 {
303 status = "okay";
111 support-8bit; 304 support-8bit;
305 bus-width = <8>;
112 }; 306 };
113 307
114 gpio-keys { 308 gpio-keys {
@@ -127,8 +321,28 @@
127 321
128 wifi { 322 wifi {
129 label = "wifi-led"; 323 label = "wifi-led";
130 gpios = <&gpio 24 0>; 324 gpios = <&gpio 24 0>; /* gpio PD0 */
131 linux,default-trigger = "rfkill0"; 325 linux,default-trigger = "rfkill0";
132 }; 326 };
133 }; 327 };
328
329 sound {
330 compatible = "nvidia,tegra-audio-alc5632-paz00",
331 "nvidia,tegra-audio-alc5632";
332
333 nvidia,model = "Compal PAZ00";
334
335 nvidia,audio-routing =
336 "Int Spk", "SPKOUT",
337 "Int Spk", "SPKOUTN",
338 "Headset Mic", "MICBIAS1",
339 "MIC1", "Headset Mic",
340 "Headset Stereophone", "HPR",
341 "Headset Stereophone", "HPL",
342 "DMICDAT", "Digital Mic";
343
344 nvidia,audio-codec = <&alc5632>;
345 nvidia,i2s-controller = <&tegra_i2s1>;
346 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
347 };
134}; 348};
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index dbf1c5a171c2..89cb7f2acd92 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -7,112 +7,398 @@
7 compatible = "nvidia,seaboard", "nvidia,tegra20"; 7 compatible = "nvidia,seaboard", "nvidia,tegra20";
8 8
9 memory { 9 memory {
10 device_type = "memory"; 10 reg = <0x00000000 0x40000000>;
11 reg = < 0x00000000 0x40000000 >; 11 };
12
13 pinmux {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "spia",
32 "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp", "lm1";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
67 ddc {
68 nvidia,pins = "ddc", "owc", "spdi", "spdo",
69 "uac";
70 nvidia,function = "rsvd2";
71 };
72 dta {
73 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
74 nvidia,function = "vi";
75 };
76 dtf {
77 nvidia,pins = "dtf";
78 nvidia,function = "i2c3";
79 };
80 gmc {
81 nvidia,pins = "gmc";
82 nvidia,function = "uartd";
83 };
84 gmd {
85 nvidia,pins = "gmd";
86 nvidia,function = "sflash";
87 };
88 gpu {
89 nvidia,pins = "gpu";
90 nvidia,function = "pwm";
91 };
92 gpu7 {
93 nvidia,pins = "gpu7";
94 nvidia,function = "rtck";
95 };
96 gpv {
97 nvidia,pins = "gpv", "slxa", "slxk";
98 nvidia,function = "pcie";
99 };
100 hdint {
101 nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
102 "lsck", "lsda";
103 nvidia,function = "hdmi";
104 };
105 i2cp {
106 nvidia,pins = "i2cp";
107 nvidia,function = "i2cp";
108 };
109 irrx {
110 nvidia,pins = "irrx", "irtx";
111 nvidia,function = "uartb";
112 };
113 kbca {
114 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
115 "kbce", "kbcf";
116 nvidia,function = "kbc";
117 };
118 lcsn {
119 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
120 "lsdi", "lvp0";
121 nvidia,function = "rsvd4";
122 };
123 ld0 {
124 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
125 "ld5", "ld6", "ld7", "ld8", "ld9",
126 "ld10", "ld11", "ld12", "ld13", "ld14",
127 "ld15", "ld16", "ld17", "ldi", "lhp0",
128 "lhp1", "lhp2", "lhs", "lpp", "lsc0",
129 "lspi", "lvp1", "lvs";
130 nvidia,function = "displaya";
131 };
132 pmc {
133 nvidia,pins = "pmc";
134 nvidia,function = "pwr_on";
135 };
136 pta {
137 nvidia,pins = "pta";
138 nvidia,function = "i2c2";
139 };
140 rm {
141 nvidia,pins = "rm";
142 nvidia,function = "i2c1";
143 };
144 sdb {
145 nvidia,pins = "sdb", "sdc", "sdd";
146 nvidia,function = "sdio3";
147 };
148 sdio1 {
149 nvidia,pins = "sdio1";
150 nvidia,function = "sdio1";
151 };
152 slxc {
153 nvidia,pins = "slxc", "slxd";
154 nvidia,function = "spdif";
155 };
156 spid {
157 nvidia,pins = "spid", "spie", "spif";
158 nvidia,function = "spi1";
159 };
160 spig {
161 nvidia,pins = "spig", "spih";
162 nvidia,function = "spi2_alt";
163 };
164 uaa {
165 nvidia,pins = "uaa", "uab", "uda";
166 nvidia,function = "ulpi";
167 };
168 uad {
169 nvidia,pins = "uad";
170 nvidia,function = "irda";
171 };
172 uca {
173 nvidia,pins = "uca", "ucb";
174 nvidia,function = "uartc";
175 };
176 conf_ata {
177 nvidia,pins = "ata", "atb", "atc", "atd",
178 "cdev1", "cdev2", "dap1", "dap2",
179 "dap4", "dtf", "gma", "gmc", "gmd",
180 "gme", "gpu", "gpu7", "i2cp", "irrx",
181 "irtx", "pta", "rm", "sdc", "sdd",
182 "slxd", "slxk", "spdi", "spdo", "uac",
183 "uad", "uca", "ucb", "uda";
184 nvidia,pull = <0>;
185 nvidia,tristate = <0>;
186 };
187 conf_ate {
188 nvidia,pins = "ate", "csus", "dap3", "ddc",
189 "gpv", "owc", "slxc", "spib", "spid",
190 "spie";
191 nvidia,pull = <0>;
192 nvidia,tristate = <1>;
193 };
194 conf_ck32 {
195 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
196 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
197 nvidia,pull = <0>;
198 };
199 conf_crtp {
200 nvidia,pins = "crtp", "gmb", "slxa", "spia",
201 "spig", "spih";
202 nvidia,pull = <2>;
203 nvidia,tristate = <1>;
204 };
205 conf_dta {
206 nvidia,pins = "dta", "dtb", "dtc", "dtd";
207 nvidia,pull = <1>;
208 nvidia,tristate = <0>;
209 };
210 conf_dte {
211 nvidia,pins = "dte", "spif";
212 nvidia,pull = <1>;
213 nvidia,tristate = <1>;
214 };
215 conf_hdint {
216 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
217 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
218 "lvp0";
219 nvidia,tristate = <1>;
220 };
221 conf_kbca {
222 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
223 "kbce", "kbcf", "sdio1", "spic", "uaa",
224 "uab";
225 nvidia,pull = <2>;
226 nvidia,tristate = <0>;
227 };
228 conf_lc {
229 nvidia,pins = "lc", "ls";
230 nvidia,pull = <2>;
231 };
232 conf_ld0 {
233 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
234 "ld5", "ld6", "ld7", "ld8", "ld9",
235 "ld10", "ld11", "ld12", "ld13", "ld14",
236 "ld15", "ld16", "ld17", "ldi", "lhp0",
237 "lhp1", "lhp2", "lhs", "lm0", "lpp",
238 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
239 "lvs", "pmc", "sdb";
240 nvidia,tristate = <0>;
241 };
242 conf_ld17_0 {
243 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
244 "ld23_22";
245 nvidia,pull = <1>;
246 };
247 drive_sdio1 {
248 nvidia,pins = "drive_sdio1";
249 nvidia,high-speed-mode = <0>;
250 nvidia,schmitt = <0>;
251 nvidia,low-power-mode = <3>;
252 nvidia,pull-down-strength = <31>;
253 nvidia,pull-up-strength = <31>;
254 nvidia,slew-rate-rising = <3>;
255 nvidia,slew-rate-falling = <3>;
256 };
257 };
258 };
259
260 i2s@70002800 {
261 status = "okay";
262 };
263
264 serial@70006300 {
265 status = "okay";
266 clock-frequency = <216000000>;
12 }; 267 };
13 268
14 i2c@7000c000 { 269 i2c@7000c000 {
270 status = "okay";
15 clock-frequency = <400000>; 271 clock-frequency = <400000>;
16 272
17 wm8903: wm8903@1a { 273 wm8903: wm8903@1a {
18 compatible = "wlf,wm8903"; 274 compatible = "wlf,wm8903";
19 reg = <0x1a>; 275 reg = <0x1a>;
20 interrupt-parent = <&gpio>; 276 interrupt-parent = <&gpio>;
21 interrupts = < 187 0x04 >; 277 interrupts = <187 0x04>;
22 278
23 gpio-controller; 279 gpio-controller;
24 #gpio-cells = <2>; 280 #gpio-cells = <2>;
25 281
26 micdet-cfg = <0>; 282 micdet-cfg = <0>;
27 micdet-delay = <100>; 283 micdet-delay = <100>;
28 gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; 284 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
285 };
286
287 /* ALS and proximity sensor */
288 isl29018@44 {
289 compatible = "isil,isl29018";
290 reg = <0x44>;
291 interrupt-parent = <&gpio>;
292 interrupts = <202 0x04>; /* GPIO PZ2 */
293 };
294
295 gyrometer@68 {
296 compatible = "invn,mpu3050";
297 reg = <0x68>;
298 interrupt-parent = <&gpio>;
299 interrupts = <204 0x04>; /* gpio PZ4 */
29 }; 300 };
30 }; 301 };
31 302
32 i2c@7000c400 { 303 i2c@7000c400 {
33 clock-frequency = <400000>; 304 status = "okay";
305 clock-frequency = <100000>;
306
307 smart-battery@b {
308 compatible = "ti,bq20z75", "smart-battery-1.1";
309 reg = <0xb>;
310 ti,i2c-retry-count = <2>;
311 ti,poll-retry-count = <10>;
312 };
34 }; 313 };
35 314
36 i2c@7000c500 { 315 i2c@7000c500 {
316 status = "okay";
37 clock-frequency = <400000>; 317 clock-frequency = <400000>;
38 }; 318 };
39 319
40 i2c@7000d000 { 320 i2c@7000d000 {
321 status = "okay";
41 clock-frequency = <400000>; 322 clock-frequency = <400000>;
42 323
43 adt7461@4c { 324 temperature-sensor@4c {
44 compatible = "adt7461"; 325 compatible = "nct1008";
45 reg = <0x4c>; 326 reg = <0x4c>;
46 }; 327 };
47 };
48
49 i2s@70002a00 {
50 status = "disable";
51 };
52
53 sound {
54 compatible = "nvidia,tegra-audio-wm8903-seaboard",
55 "nvidia,tegra-audio-wm8903";
56 nvidia,model = "NVIDIA Tegra Seaboard";
57
58 nvidia,audio-routing =
59 "Headphone Jack", "HPOUTR",
60 "Headphone Jack", "HPOUTL",
61 "Int Spk", "ROP",
62 "Int Spk", "RON",
63 "Int Spk", "LOP",
64 "Int Spk", "LON",
65 "Mic Jack", "MICBIAS",
66 "IN1R", "Mic Jack";
67
68 nvidia,i2s-controller = <&tegra_i2s1>;
69 nvidia,audio-codec = <&wm8903>;
70
71 nvidia,spkr-en-gpios = <&wm8903 2 0>;
72 nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
73 };
74
75 serial@70006000 {
76 status = "disable";
77 };
78 328
79 serial@70006040 { 329 magnetometer@c {
80 status = "disable"; 330 compatible = "ak8975";
331 reg = <0xc>;
332 interrupt-parent = <&gpio>;
333 interrupts = <109 0x04>; /* gpio PN5 */
334 };
81 }; 335 };
82 336
83 serial@70006200 { 337 emc {
84 status = "disable"; 338 emc-table@190000 {
85 }; 339 reg = <190000>;
340 compatible = "nvidia,tegra20-emc-table";
341 clock-frequency = <190000>;
342 nvidia,emc-registers = <0x0000000c 0x00000026
343 0x00000009 0x00000003 0x00000004 0x00000004
344 0x00000002 0x0000000c 0x00000003 0x00000003
345 0x00000002 0x00000001 0x00000004 0x00000005
346 0x00000004 0x00000009 0x0000000d 0x0000059f
347 0x00000000 0x00000003 0x00000003 0x00000003
348 0x00000003 0x00000001 0x0000000b 0x000000c8
349 0x00000003 0x00000007 0x00000004 0x0000000f
350 0x00000002 0x00000000 0x00000000 0x00000002
351 0x00000000 0x00000000 0x00000083 0xa06204ae
352 0x007dc010 0x00000000 0x00000000 0x00000000
353 0x00000000 0x00000000 0x00000000 0x00000000>;
354 };
86 355
87 serial@70006300 { 356 emc-table@380000 {
88 clock-frequency = < 216000000 >; 357 reg = <380000>;
358 compatible = "nvidia,tegra20-emc-table";
359 clock-frequency = <380000>;
360 nvidia,emc-registers = <0x00000017 0x0000004b
361 0x00000012 0x00000006 0x00000004 0x00000005
362 0x00000003 0x0000000c 0x00000006 0x00000006
363 0x00000003 0x00000001 0x00000004 0x00000005
364 0x00000004 0x00000009 0x0000000d 0x00000b5f
365 0x00000000 0x00000003 0x00000003 0x00000006
366 0x00000006 0x00000001 0x00000011 0x000000c8
367 0x00000003 0x0000000e 0x00000007 0x0000000f
368 0x00000002 0x00000000 0x00000000 0x00000002
369 0x00000000 0x00000000 0x00000083 0xe044048b
370 0x007d8010 0x00000000 0x00000000 0x00000000
371 0x00000000 0x00000000 0x00000000 0x00000000>;
372 };
89 }; 373 };
90 374
91 serial@70006400 { 375 usb@c5000000 {
92 status = "disable"; 376 status = "okay";
377 nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
378 dr_mode = "otg";
93 }; 379 };
94 380
95 sdhci@c8000000 { 381 usb@c5004000 {
96 status = "disable"; 382 status = "okay";
383 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
97 }; 384 };
98 385
99 sdhci@c8000200 { 386 usb@c5008000 {
100 status = "disable"; 387 status = "okay";
101 }; 388 };
102 389
103 sdhci@c8000400 { 390 sdhci@c8000400 {
391 status = "okay";
104 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 392 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
105 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 393 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
106 power-gpios = <&gpio 70 0>; /* gpio PI6 */ 394 power-gpios = <&gpio 70 0>; /* gpio PI6 */
395 bus-width = <4>;
107 }; 396 };
108 397
109 sdhci@c8000600 { 398 sdhci@c8000600 {
399 status = "okay";
110 support-8bit; 400 support-8bit;
111 }; 401 bus-width = <8>;
112
113 usb@c5000000 {
114 nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
115 dr_mode = "otg";
116 }; 402 };
117 403
118 gpio-keys { 404 gpio-keys {
@@ -135,41 +421,25 @@
135 }; 421 };
136 }; 422 };
137 423
138 emc@7000f400 { 424 sound {
139 emc-table@190000 { 425 compatible = "nvidia,tegra-audio-wm8903-seaboard",
140 reg = < 190000 >; 426 "nvidia,tegra-audio-wm8903";
141 compatible = "nvidia,tegra20-emc-table"; 427 nvidia,model = "NVIDIA Tegra Seaboard";
142 clock-frequency = < 190000 >;
143 nvidia,emc-registers = < 0x0000000c 0x00000026
144 0x00000009 0x00000003 0x00000004 0x00000004
145 0x00000002 0x0000000c 0x00000003 0x00000003
146 0x00000002 0x00000001 0x00000004 0x00000005
147 0x00000004 0x00000009 0x0000000d 0x0000059f
148 0x00000000 0x00000003 0x00000003 0x00000003
149 0x00000003 0x00000001 0x0000000b 0x000000c8
150 0x00000003 0x00000007 0x00000004 0x0000000f
151 0x00000002 0x00000000 0x00000000 0x00000002
152 0x00000000 0x00000000 0x00000083 0xa06204ae
153 0x007dc010 0x00000000 0x00000000 0x00000000
154 0x00000000 0x00000000 0x00000000 0x00000000 >;
155 };
156 428
157 emc-table@380000 { 429 nvidia,audio-routing =
158 reg = < 380000 >; 430 "Headphone Jack", "HPOUTR",
159 compatible = "nvidia,tegra20-emc-table"; 431 "Headphone Jack", "HPOUTL",
160 clock-frequency = < 380000 >; 432 "Int Spk", "ROP",
161 nvidia,emc-registers = < 0x00000017 0x0000004b 433 "Int Spk", "RON",
162 0x00000012 0x00000006 0x00000004 0x00000005 434 "Int Spk", "LOP",
163 0x00000003 0x0000000c 0x00000006 0x00000006 435 "Int Spk", "LON",
164 0x00000003 0x00000001 0x00000004 0x00000005 436 "Mic Jack", "MICBIAS",
165 0x00000004 0x00000009 0x0000000d 0x00000b5f 437 "IN1R", "Mic Jack";
166 0x00000000 0x00000003 0x00000003 0x00000006 438
167 0x00000006 0x00000001 0x00000011 0x000000c8 439 nvidia,i2s-controller = <&tegra_i2s1>;
168 0x00000003 0x0000000e 0x00000007 0x0000000f 440 nvidia,audio-codec = <&wm8903>;
169 0x00000002 0x00000000 0x00000000 0x00000002 441
170 0x00000000 0x00000000 0x00000083 0xe044048b 442 nvidia,spkr-en-gpios = <&wm8903 2 0>;
171 0x007d8010 0x00000000 0x00000000 0x00000000 443 nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
172 0x00000000 0x00000000 0x00000000 0x00000000 >;
173 };
174 }; 444 };
175}; 445};
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
index 252476867b54..9de5636023f6 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -6,72 +6,301 @@
6 model = "Compulab TrimSlice board"; 6 model = "Compulab TrimSlice board";
7 compatible = "compulab,trimslice", "nvidia,tegra20"; 7 compatible = "compulab,trimslice", "nvidia,tegra20";
8 8
9 memory@0 { 9 memory {
10 reg = < 0x00000000 0x40000000 >; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 i2c@7000c000 { 13 pinmux {
14 clock-frequency = <400000>; 14 pinctrl-names = "default";
15 }; 15 pinctrl-0 = <&state_default>;
16 16
17 i2c@7000c400 { 17 state_default: pinmux {
18 clock-frequency = <400000>; 18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc", "gmb";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gme", "pta";
32 nvidia,function = "gmi";
33 };
34 cdev1 {
35 nvidia,pins = "cdev1";
36 nvidia,function = "plla_out";
37 };
38 cdev2 {
39 nvidia,pins = "cdev2";
40 nvidia,function = "pllp_out4";
41 };
42 crtp {
43 nvidia,pins = "crtp";
44 nvidia,function = "crt";
45 };
46 csus {
47 nvidia,pins = "csus";
48 nvidia,function = "vi_sensor_clk";
49 };
50 dap1 {
51 nvidia,pins = "dap1";
52 nvidia,function = "dap1";
53 };
54 dap2 {
55 nvidia,pins = "dap2";
56 nvidia,function = "dap2";
57 };
58 dap3 {
59 nvidia,pins = "dap3";
60 nvidia,function = "dap3";
61 };
62 dap4 {
63 nvidia,pins = "dap4";
64 nvidia,function = "dap4";
65 };
66 ddc {
67 nvidia,pins = "ddc";
68 nvidia,function = "i2c2";
69 };
70 dta {
71 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
72 nvidia,function = "vi";
73 };
74 dtf {
75 nvidia,pins = "dtf";
76 nvidia,function = "i2c3";
77 };
78 gmc {
79 nvidia,pins = "gmc", "gmd";
80 nvidia,function = "sflash";
81 };
82 gpu {
83 nvidia,pins = "gpu";
84 nvidia,function = "uarta";
85 };
86 gpu7 {
87 nvidia,pins = "gpu7";
88 nvidia,function = "rtck";
89 };
90 gpv {
91 nvidia,pins = "gpv", "slxa", "slxk";
92 nvidia,function = "pcie";
93 };
94 hdint {
95 nvidia,pins = "hdint";
96 nvidia,function = "hdmi";
97 };
98 i2cp {
99 nvidia,pins = "i2cp";
100 nvidia,function = "i2cp";
101 };
102 irrx {
103 nvidia,pins = "irrx", "irtx";
104 nvidia,function = "uartb";
105 };
106 kbca {
107 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
108 "kbce", "kbcf";
109 nvidia,function = "kbc";
110 };
111 lcsn {
112 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
113 "ld3", "ld4", "ld5", "ld6", "ld7",
114 "ld8", "ld9", "ld10", "ld11", "ld12",
115 "ld13", "ld14", "ld15", "ld16", "ld17",
116 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
117 "lhs", "lm0", "lm1", "lpp", "lpw0",
118 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
119 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
120 "lvs";
121 nvidia,function = "displaya";
122 };
123 owc {
124 nvidia,pins = "owc", "uac";
125 nvidia,function = "rsvd2";
126 };
127 pmc {
128 nvidia,pins = "pmc";
129 nvidia,function = "pwr_on";
130 };
131 rm {
132 nvidia,pins = "rm";
133 nvidia,function = "i2c1";
134 };
135 sdb {
136 nvidia,pins = "sdb", "sdc", "sdd";
137 nvidia,function = "pwm";
138 };
139 sdio1 {
140 nvidia,pins = "sdio1";
141 nvidia,function = "sdio1";
142 };
143 slxc {
144 nvidia,pins = "slxc", "slxd";
145 nvidia,function = "sdio3";
146 };
147 spdi {
148 nvidia,pins = "spdi", "spdo";
149 nvidia,function = "spdif";
150 };
151 spia {
152 nvidia,pins = "spia", "spib", "spic";
153 nvidia,function = "spi2";
154 };
155 spid {
156 nvidia,pins = "spid", "spie", "spif";
157 nvidia,function = "spi1";
158 };
159 spig {
160 nvidia,pins = "spig", "spih";
161 nvidia,function = "spi2_alt";
162 };
163 uaa {
164 nvidia,pins = "uaa", "uab", "uda";
165 nvidia,function = "ulpi";
166 };
167 uad {
168 nvidia,pins = "uad";
169 nvidia,function = "irda";
170 };
171 uca {
172 nvidia,pins = "uca", "ucb";
173 nvidia,function = "uartc";
174 };
175 conf_ata {
176 nvidia,pins = "ata", "atc", "atd", "ate",
177 "crtp", "dap2", "dap3", "dap4", "dta",
178 "dtb", "dtc", "dtd", "dte", "gmb",
179 "gme", "i2cp", "pta", "slxc", "slxd",
180 "spdi", "spdo", "uda";
181 nvidia,pull = <0>;
182 nvidia,tristate = <1>;
183 };
184 conf_atb {
185 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
186 "gma", "gmc", "gmd", "gpu", "gpu7",
187 "gpv", "sdio1", "slxa", "slxk", "uac";
188 nvidia,pull = <0>;
189 nvidia,tristate = <0>;
190 };
191 conf_ck32 {
192 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
193 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
194 nvidia,pull = <0>;
195 };
196 conf_csus {
197 nvidia,pins = "csus", "spia", "spib",
198 "spid", "spif";
199 nvidia,pull = <1>;
200 nvidia,tristate = <1>;
201 };
202 conf_ddc {
203 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
204 nvidia,pull = <2>;
205 nvidia,tristate = <0>;
206 };
207 conf_hdint {
208 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
209 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
210 "lvp0", "pmc";
211 nvidia,tristate = <1>;
212 };
213 conf_irrx {
214 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
215 "kbcc", "kbcd", "kbce", "kbcf", "owc",
216 "spic", "spie", "spig", "spih", "uaa",
217 "uab", "uad", "uca", "ucb";
218 nvidia,pull = <2>;
219 nvidia,tristate = <1>;
220 };
221 conf_lc {
222 nvidia,pins = "lc", "ls";
223 nvidia,pull = <2>;
224 };
225 conf_ld0 {
226 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
227 "ld5", "ld6", "ld7", "ld8", "ld9",
228 "ld10", "ld11", "ld12", "ld13", "ld14",
229 "ld15", "ld16", "ld17", "ldi", "lhp0",
230 "lhp1", "lhp2", "lhs", "lm0", "lpp",
231 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
232 "lvs", "sdb";
233 nvidia,tristate = <0>;
234 };
235 conf_ld17_0 {
236 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
237 "ld23_22";
238 nvidia,pull = <1>;
239 };
240 };
19 }; 241 };
20 242
21 i2c@7000c500 { 243 i2s@70002800 {
22 clock-frequency = <400000>; 244 status = "okay";
23 }; 245 };
24 246
25 i2c@7000d000 { 247 serial@70006000 {
26 status = "disable"; 248 status = "okay";
249 clock-frequency = <216000000>;
27 }; 250 };
28 251
29 i2s@70002800 { 252 i2c@7000c000 {
30 status = "disable"; 253 status = "okay";
254 clock-frequency = <400000>;
31 }; 255 };
32 256
33 i2s@70002a00 { 257 i2c@7000c400 {
34 status = "disable"; 258 status = "okay";
259 clock-frequency = <400000>;
35 }; 260 };
36 261
37 das@70000c00 { 262 i2c@7000c500 {
38 status = "disable"; 263 status = "okay";
39 }; 264 clock-frequency = <400000>;
40 265
41 serial@70006000 { 266 codec: codec@1a {
42 clock-frequency = < 216000000 >; 267 compatible = "ti,tlv320aic23";
43 }; 268 reg = <0x1a>;
269 };
44 270
45 serial@70006040 { 271 rtc@56 {
46 status = "disable"; 272 compatible = "emmicro,em3027";
273 reg = <0x56>;
274 };
47 }; 275 };
48 276
49 serial@70006200 { 277 usb@c5000000 {
50 status = "disable"; 278 status = "okay";
51 }; 279 };
52 280
53 serial@70006300 { 281 usb@c5004000 {
54 status = "disable"; 282 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
55 }; 283 };
56 284
57 serial@70006400 { 285 usb@c5008000 {
58 status = "disable"; 286 status = "okay";
59 }; 287 };
60 288
61 sdhci@c8000000 { 289 sdhci@c8000000 {
62 status = "disable"; 290 status = "okay";
63 }; 291 bus-width = <4>;
64
65 sdhci@c8000200 {
66 status = "disable";
67 }; 292 };
68 293
69 sdhci@c8000400 { 294 sdhci@c8000600 {
70 status = "disable"; 295 status = "okay";
296 cd-gpios = <&gpio 121 0>; /* gpio PP1 */
297 wp-gpios = <&gpio 122 0>; /* gpio PP2 */
298 bus-width = <4>;
71 }; 299 };
72 300
73 sdhci@c8000600 { 301 sound {
74 cd-gpios = <&gpio 121 0>; 302 compatible = "nvidia,tegra-audio-trimslice";
75 wp-gpios = <&gpio 122 0>; 303 nvidia,i2s-controller = <&tegra_i2s1>;
304 nvidia,audio-codec = <&codec>;
76 }; 305 };
77}; 306};
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index 2dcff8728e90..445343b0fbdd 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -7,41 +7,315 @@
7 compatible = "nvidia,ventana", "nvidia,tegra20"; 7 compatible = "nvidia,ventana", "nvidia,tegra20";
8 8
9 memory { 9 memory {
10 reg = < 0x00000000 0x40000000 >; 10 reg = <0x00000000 0x40000000>;
11 };
12
13 pinmux {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "spia",
32 "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp", "lm1";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
67 ddc {
68 nvidia,pins = "ddc", "owc", "spdi", "spdo",
69 "uac";
70 nvidia,function = "rsvd2";
71 };
72 dta {
73 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
74 nvidia,function = "vi";
75 };
76 dtf {
77 nvidia,pins = "dtf";
78 nvidia,function = "i2c3";
79 };
80 gmc {
81 nvidia,pins = "gmc";
82 nvidia,function = "uartd";
83 };
84 gmd {
85 nvidia,pins = "gmd";
86 nvidia,function = "sflash";
87 };
88 gpu {
89 nvidia,pins = "gpu";
90 nvidia,function = "pwm";
91 };
92 gpu7 {
93 nvidia,pins = "gpu7";
94 nvidia,function = "rtck";
95 };
96 gpv {
97 nvidia,pins = "gpv", "slxa", "slxk";
98 nvidia,function = "pcie";
99 };
100 hdint {
101 nvidia,pins = "hdint", "pta";
102 nvidia,function = "hdmi";
103 };
104 i2cp {
105 nvidia,pins = "i2cp";
106 nvidia,function = "i2cp";
107 };
108 irrx {
109 nvidia,pins = "irrx", "irtx";
110 nvidia,function = "uartb";
111 };
112 kbca {
113 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
114 "kbce", "kbcf";
115 nvidia,function = "kbc";
116 };
117 lcsn {
118 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
119 "lsdi", "lvp0";
120 nvidia,function = "rsvd4";
121 };
122 ld0 {
123 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
124 "ld5", "ld6", "ld7", "ld8", "ld9",
125 "ld10", "ld11", "ld12", "ld13", "ld14",
126 "ld15", "ld16", "ld17", "ldi", "lhp0",
127 "lhp1", "lhp2", "lhs", "lpp", "lpw0",
128 "lpw2", "lsc0", "lsc1", "lsck", "lsda",
129 "lspi", "lvp1", "lvs";
130 nvidia,function = "displaya";
131 };
132 pmc {
133 nvidia,pins = "pmc";
134 nvidia,function = "pwr_on";
135 };
136 rm {
137 nvidia,pins = "rm";
138 nvidia,function = "i2c1";
139 };
140 sdb {
141 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
142 nvidia,function = "sdio3";
143 };
144 sdio1 {
145 nvidia,pins = "sdio1";
146 nvidia,function = "sdio1";
147 };
148 slxd {
149 nvidia,pins = "slxd";
150 nvidia,function = "spdif";
151 };
152 spid {
153 nvidia,pins = "spid", "spie", "spif";
154 nvidia,function = "spi1";
155 };
156 spig {
157 nvidia,pins = "spig", "spih";
158 nvidia,function = "spi2_alt";
159 };
160 uaa {
161 nvidia,pins = "uaa", "uab", "uda";
162 nvidia,function = "ulpi";
163 };
164 uad {
165 nvidia,pins = "uad";
166 nvidia,function = "irda";
167 };
168 uca {
169 nvidia,pins = "uca", "ucb";
170 nvidia,function = "uartc";
171 };
172 conf_ata {
173 nvidia,pins = "ata", "atb", "atc", "atd",
174 "cdev1", "cdev2", "dap1", "dap2",
175 "dap4", "ddc", "dtf", "gma", "gmc",
176 "gme", "gpu", "gpu7", "i2cp", "irrx",
177 "irtx", "pta", "rm", "sdc", "sdd",
178 "slxc", "slxd", "slxk", "spdi", "spdo",
179 "uac", "uad", "uca", "ucb", "uda";
180 nvidia,pull = <0>;
181 nvidia,tristate = <0>;
182 };
183 conf_ate {
184 nvidia,pins = "ate", "csus", "dap3", "gmd",
185 "gpv", "owc", "spia", "spib", "spic",
186 "spid", "spie", "spig";
187 nvidia,pull = <0>;
188 nvidia,tristate = <1>;
189 };
190 conf_ck32 {
191 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
192 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
193 nvidia,pull = <0>;
194 };
195 conf_crtp {
196 nvidia,pins = "crtp", "gmb", "slxa", "spih";
197 nvidia,pull = <2>;
198 nvidia,tristate = <1>;
199 };
200 conf_dta {
201 nvidia,pins = "dta", "dtb", "dtc", "dtd";
202 nvidia,pull = <1>;
203 nvidia,tristate = <0>;
204 };
205 conf_dte {
206 nvidia,pins = "dte", "spif";
207 nvidia,pull = <1>;
208 nvidia,tristate = <1>;
209 };
210 conf_hdint {
211 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
212 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
213 nvidia,tristate = <1>;
214 };
215 conf_kbca {
216 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
217 "kbce", "kbcf", "sdio1", "uaa", "uab";
218 nvidia,pull = <2>;
219 nvidia,tristate = <0>;
220 };
221 conf_lc {
222 nvidia,pins = "lc", "ls";
223 nvidia,pull = <2>;
224 };
225 conf_ld0 {
226 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
227 "ld5", "ld6", "ld7", "ld8", "ld9",
228 "ld10", "ld11", "ld12", "ld13", "ld14",
229 "ld15", "ld16", "ld17", "ldi", "lhp0",
230 "lhp1", "lhp2", "lhs", "lm0", "lpp",
231 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
232 "lvp1", "lvs", "pmc", "sdb";
233 nvidia,tristate = <0>;
234 };
235 conf_ld17_0 {
236 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
237 "ld23_22";
238 nvidia,pull = <1>;
239 };
240 };
241 };
242
243 i2s@70002800 {
244 status = "okay";
245 };
246
247 serial@70006300 {
248 status = "okay";
249 clock-frequency = <216000000>;
11 }; 250 };
12 251
13 i2c@7000c000 { 252 i2c@7000c000 {
253 status = "okay";
14 clock-frequency = <400000>; 254 clock-frequency = <400000>;
15 255
16 wm8903: wm8903@1a { 256 wm8903: wm8903@1a {
17 compatible = "wlf,wm8903"; 257 compatible = "wlf,wm8903";
18 reg = <0x1a>; 258 reg = <0x1a>;
19 interrupt-parent = <&gpio>; 259 interrupt-parent = <&gpio>;
20 interrupts = < 187 0x04 >; 260 interrupts = <187 0x04>;
21 261
22 gpio-controller; 262 gpio-controller;
23 #gpio-cells = <2>; 263 #gpio-cells = <2>;
24 264
25 micdet-cfg = <0>; 265 micdet-cfg = <0>;
26 micdet-delay = <100>; 266 micdet-delay = <100>;
27 gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; 267 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
268 };
269
270 /* ALS and proximity sensor */
271 isl29018@44 {
272 compatible = "isil,isl29018";
273 reg = <0x44>;
274 interrupt-parent = <&gpio>;
275 interrupts = <202 0x04>; /*gpio PZ2 */
28 }; 276 };
29 }; 277 };
30 278
31 i2c@7000c400 { 279 i2c@7000c400 {
280 status = "okay";
32 clock-frequency = <400000>; 281 clock-frequency = <400000>;
33 }; 282 };
34 283
35 i2c@7000c500 { 284 i2c@7000c500 {
285 status = "okay";
36 clock-frequency = <400000>; 286 clock-frequency = <400000>;
37 }; 287 };
38 288
39 i2c@7000d000 { 289 i2c@7000d000 {
290 status = "okay";
40 clock-frequency = <400000>; 291 clock-frequency = <400000>;
41 }; 292 };
42 293
43 i2s@70002a00 { 294 usb@c5000000 {
44 status = "disable"; 295 status = "okay";
296 };
297
298 usb@c5004000 {
299 status = "okay";
300 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
301 };
302
303 usb@c5008000 {
304 status = "okay";
305 };
306
307 sdhci@c8000400 {
308 status = "okay";
309 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
310 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
311 power-gpios = <&gpio 70 0>; /* gpio PI6 */
312 bus-width = <4>;
313 };
314
315 sdhci@c8000600 {
316 status = "okay";
317 support-8bit;
318 bus-width = <8>;
45 }; 319 };
46 320
47 sound { 321 sound {
@@ -64,45 +338,7 @@
64 338
65 nvidia,spkr-en-gpios = <&wm8903 2 0>; 339 nvidia,spkr-en-gpios = <&wm8903 2 0>;
66 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 340 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
67 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ 341 nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
68 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ 342 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
69 }; 343 };
70
71 serial@70006000 {
72 status = "disable";
73 };
74
75 serial@70006040 {
76 status = "disable";
77 };
78
79 serial@70006200 {
80 status = "disable";
81 };
82
83 serial@70006300 {
84 clock-frequency = < 216000000 >;
85 };
86
87 serial@70006400 {
88 status = "disable";
89 };
90
91 sdhci@c8000000 {
92 status = "disable";
93 };
94
95 sdhci@c8000200 {
96 status = "disable";
97 };
98
99 sdhci@c8000400 {
100 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
101 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
102 power-gpios = <&gpio 70 0>; /* gpio PI6 */
103 };
104
105 sdhci@c8000600 {
106 support-8bit;
107 };
108}; 344};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 108e894a8926..c417d67e9027 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,207 +4,242 @@
4 compatible = "nvidia,tegra20"; 4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 pmc@7000f400 { 7 intc: interrupt-controller {
8 compatible = "nvidia,tegra20-pmc";
9 reg = <0x7000e400 0x400>;
10 };
11
12 intc: interrupt-controller@50041000 {
13 compatible = "arm,cortex-a9-gic"; 8 compatible = "arm,cortex-a9-gic";
9 reg = <0x50041000 0x1000
10 0x50040100 0x0100>;
14 interrupt-controller; 11 interrupt-controller;
15 #interrupt-cells = <3>; 12 #interrupt-cells = <3>;
16 reg = < 0x50041000 0x1000 >,
17 < 0x50040100 0x0100 >;
18 }; 13 };
19 14
20 pmu { 15 apbdma: dma {
21 compatible = "arm,cortex-a9-pmu";
22 interrupts = <0 56 0x04
23 0 57 0x04>;
24 };
25
26 apbdma: dma@6000a000 {
27 compatible = "nvidia,tegra20-apbdma"; 16 compatible = "nvidia,tegra20-apbdma";
28 reg = <0x6000a000 0x1200>; 17 reg = <0x6000a000 0x1200>;
29 interrupts = < 0 104 0x04 18 interrupts = <0 104 0x04
30 0 105 0x04 19 0 105 0x04
31 0 106 0x04 20 0 106 0x04
32 0 107 0x04 21 0 107 0x04
33 0 108 0x04 22 0 108 0x04
34 0 109 0x04 23 0 109 0x04
35 0 110 0x04 24 0 110 0x04
36 0 111 0x04 25 0 111 0x04
37 0 112 0x04 26 0 112 0x04
38 0 113 0x04 27 0 113 0x04
39 0 114 0x04 28 0 114 0x04
40 0 115 0x04 29 0 115 0x04
41 0 116 0x04 30 0 116 0x04
42 0 117 0x04 31 0 117 0x04
43 0 118 0x04 32 0 118 0x04
44 0 119 0x04 >; 33 0 119 0x04>;
45 }; 34 };
46 35
47 i2c@7000c000 { 36 ahb {
48 #address-cells = <1>; 37 compatible = "nvidia,tegra20-ahb";
49 #size-cells = <0>; 38 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
50 compatible = "nvidia,tegra20-i2c"; 39 };
51 reg = <0x7000C000 0x100>; 40
52 interrupts = < 0 38 0x04 >; 41 gpio: gpio {
53 }; 42 compatible = "nvidia,tegra20-gpio";
54 43 reg = <0x6000d000 0x1000>;
55 i2c@7000c400 { 44 interrupts = <0 32 0x04
56 #address-cells = <1>; 45 0 33 0x04
57 #size-cells = <0>; 46 0 34 0x04
58 compatible = "nvidia,tegra20-i2c"; 47 0 35 0x04
59 reg = <0x7000C400 0x100>; 48 0 55 0x04
60 interrupts = < 0 84 0x04 >; 49 0 87 0x04
50 0 89 0x04>;
51 #gpio-cells = <2>;
52 gpio-controller;
53 #interrupt-cells = <2>;
54 interrupt-controller;
61 }; 55 };
62 56
63 i2c@7000c500 { 57 pinmux: pinmux {
64 #address-cells = <1>; 58 compatible = "nvidia,tegra20-pinmux";
65 #size-cells = <0>; 59 reg = <0x70000014 0x10 /* Tri-state registers */
66 compatible = "nvidia,tegra20-i2c"; 60 0x70000080 0x20 /* Mux registers */
67 reg = <0x7000C500 0x100>; 61 0x700000a0 0x14 /* Pull-up/down registers */
68 interrupts = < 0 92 0x04 >; 62 0x70000868 0xa8>; /* Pad control registers */
69 }; 63 };
70 64
71 i2c@7000d000 { 65 das {
72 #address-cells = <1>; 66 compatible = "nvidia,tegra20-das";
73 #size-cells = <0>; 67 reg = <0x70000c00 0x80>;
74 compatible = "nvidia,tegra20-i2c-dvc";
75 reg = <0x7000D000 0x200>;
76 interrupts = < 0 53 0x04 >;
77 }; 68 };
78 69
79 tegra_i2s1: i2s@70002800 { 70 tegra_i2s1: i2s@70002800 {
80 compatible = "nvidia,tegra20-i2s"; 71 compatible = "nvidia,tegra20-i2s";
81 reg = <0x70002800 0x200>; 72 reg = <0x70002800 0x200>;
82 interrupts = < 0 13 0x04 >; 73 interrupts = <0 13 0x04>;
83 nvidia,dma-request-selector = < &apbdma 2 >; 74 nvidia,dma-request-selector = <&apbdma 2>;
75 status = "disable";
84 }; 76 };
85 77
86 tegra_i2s2: i2s@70002a00 { 78 tegra_i2s2: i2s@70002a00 {
87 compatible = "nvidia,tegra20-i2s"; 79 compatible = "nvidia,tegra20-i2s";
88 reg = <0x70002a00 0x200>; 80 reg = <0x70002a00 0x200>;
89 interrupts = < 0 3 0x04 >; 81 interrupts = <0 3 0x04>;
90 nvidia,dma-request-selector = < &apbdma 1 >; 82 nvidia,dma-request-selector = <&apbdma 1>;
91 }; 83 status = "disable";
92
93 das@70000c00 {
94 compatible = "nvidia,tegra20-das";
95 reg = <0x70000c00 0x80>;
96 };
97
98 gpio: gpio@6000d000 {
99 compatible = "nvidia,tegra20-gpio";
100 reg = < 0x6000d000 0x1000 >;
101 interrupts = < 0 32 0x04
102 0 33 0x04
103 0 34 0x04
104 0 35 0x04
105 0 55 0x04
106 0 87 0x04
107 0 89 0x04 >;
108 #gpio-cells = <2>;
109 gpio-controller;
110 #interrupt-cells = <2>;
111 interrupt-controller;
112 };
113
114 pinmux: pinmux@70000000 {
115 compatible = "nvidia,tegra20-pinmux";
116 reg = < 0x70000014 0x10 /* Tri-state registers */
117 0x70000080 0x20 /* Mux registers */
118 0x700000a0 0x14 /* Pull-up/down registers */
119 0x70000868 0xa8 >; /* Pad control registers */
120 }; 84 };
121 85
122 serial@70006000 { 86 serial@70006000 {
123 compatible = "nvidia,tegra20-uart"; 87 compatible = "nvidia,tegra20-uart";
124 reg = <0x70006000 0x40>; 88 reg = <0x70006000 0x40>;
125 reg-shift = <2>; 89 reg-shift = <2>;
126 interrupts = < 0 36 0x04 >; 90 interrupts = <0 36 0x04>;
91 status = "disable";
127 }; 92 };
128 93
129 serial@70006040 { 94 serial@70006040 {
130 compatible = "nvidia,tegra20-uart"; 95 compatible = "nvidia,tegra20-uart";
131 reg = <0x70006040 0x40>; 96 reg = <0x70006040 0x40>;
132 reg-shift = <2>; 97 reg-shift = <2>;
133 interrupts = < 0 37 0x04 >; 98 interrupts = <0 37 0x04>;
99 status = "disable";
134 }; 100 };
135 101
136 serial@70006200 { 102 serial@70006200 {
137 compatible = "nvidia,tegra20-uart"; 103 compatible = "nvidia,tegra20-uart";
138 reg = <0x70006200 0x100>; 104 reg = <0x70006200 0x100>;
139 reg-shift = <2>; 105 reg-shift = <2>;
140 interrupts = < 0 46 0x04 >; 106 interrupts = <0 46 0x04>;
107 status = "disable";
141 }; 108 };
142 109
143 serial@70006300 { 110 serial@70006300 {
144 compatible = "nvidia,tegra20-uart"; 111 compatible = "nvidia,tegra20-uart";
145 reg = <0x70006300 0x100>; 112 reg = <0x70006300 0x100>;
146 reg-shift = <2>; 113 reg-shift = <2>;
147 interrupts = < 0 90 0x04 >; 114 interrupts = <0 90 0x04>;
115 status = "disable";
148 }; 116 };
149 117
150 serial@70006400 { 118 serial@70006400 {
151 compatible = "nvidia,tegra20-uart"; 119 compatible = "nvidia,tegra20-uart";
152 reg = <0x70006400 0x100>; 120 reg = <0x70006400 0x100>;
153 reg-shift = <2>; 121 reg-shift = <2>;
154 interrupts = < 0 91 0x04 >; 122 interrupts = <0 91 0x04>;
123 status = "disable";
155 }; 124 };
156 125
157 emc@7000f400 { 126 i2c@7000c000 {
127 compatible = "nvidia,tegra20-i2c";
128 reg = <0x7000c000 0x100>;
129 interrupts = <0 38 0x04>;
158 #address-cells = <1>; 130 #address-cells = <1>;
159 #size-cells = <0>; 131 #size-cells = <0>;
160 compatible = "nvidia,tegra20-emc"; 132 status = "disable";
161 reg = <0x7000f400 0x200>;
162 }; 133 };
163 134
164 sdhci@c8000000 { 135 i2c@7000c400 {
165 compatible = "nvidia,tegra20-sdhci"; 136 compatible = "nvidia,tegra20-i2c";
166 reg = <0xc8000000 0x200>; 137 reg = <0x7000c400 0x100>;
167 interrupts = < 0 14 0x04 >; 138 interrupts = <0 84 0x04>;
139 #address-cells = <1>;
140 #size-cells = <0>;
141 status = "disable";
168 }; 142 };
169 143
170 sdhci@c8000200 { 144 i2c@7000c500 {
171 compatible = "nvidia,tegra20-sdhci"; 145 compatible = "nvidia,tegra20-i2c";
172 reg = <0xc8000200 0x200>; 146 reg = <0x7000c500 0x100>;
173 interrupts = < 0 15 0x04 >; 147 interrupts = <0 92 0x04>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 status = "disable";
174 }; 151 };
175 152
176 sdhci@c8000400 { 153 i2c@7000d000 {
177 compatible = "nvidia,tegra20-sdhci"; 154 compatible = "nvidia,tegra20-i2c-dvc";
178 reg = <0xc8000400 0x200>; 155 reg = <0x7000d000 0x200>;
179 interrupts = < 0 19 0x04 >; 156 interrupts = <0 53 0x04>;
157 #address-cells = <1>;
158 #size-cells = <0>;
159 status = "disable";
180 }; 160 };
181 161
182 sdhci@c8000600 { 162 pmc {
183 compatible = "nvidia,tegra20-sdhci"; 163 compatible = "nvidia,tegra20-pmc";
184 reg = <0xc8000600 0x200>; 164 reg = <0x7000e400 0x400>;
185 interrupts = < 0 31 0x04 >; 165 };
166
167 mc {
168 compatible = "nvidia,tegra20-mc";
169 reg = <0x7000f000 0x024
170 0x7000f03c 0x3c4>;
171 interrupts = <0 77 0x04>;
172 };
173
174 gart {
175 compatible = "nvidia,tegra20-gart";
176 reg = <0x7000f024 0x00000018 /* controller registers */
177 0x58000000 0x02000000>; /* GART aperture */
178 };
179
180 emc {
181 compatible = "nvidia,tegra20-emc";
182 reg = <0x7000f400 0x200>;
183 #address-cells = <1>;
184 #size-cells = <0>;
186 }; 185 };
187 186
188 usb@c5000000 { 187 usb@c5000000 {
189 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 188 compatible = "nvidia,tegra20-ehci", "usb-ehci";
190 reg = <0xc5000000 0x4000>; 189 reg = <0xc5000000 0x4000>;
191 interrupts = < 0 20 0x04 >; 190 interrupts = <0 20 0x04>;
192 phy_type = "utmi"; 191 phy_type = "utmi";
193 nvidia,has-legacy-mode; 192 nvidia,has-legacy-mode;
193 status = "disable";
194 }; 194 };
195 195
196 usb@c5004000 { 196 usb@c5004000 {
197 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 197 compatible = "nvidia,tegra20-ehci", "usb-ehci";
198 reg = <0xc5004000 0x4000>; 198 reg = <0xc5004000 0x4000>;
199 interrupts = < 0 21 0x04 >; 199 interrupts = <0 21 0x04>;
200 phy_type = "ulpi"; 200 phy_type = "ulpi";
201 status = "disable";
201 }; 202 };
202 203
203 usb@c5008000 { 204 usb@c5008000 {
204 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 205 compatible = "nvidia,tegra20-ehci", "usb-ehci";
205 reg = <0xc5008000 0x4000>; 206 reg = <0xc5008000 0x4000>;
206 interrupts = < 0 97 0x04 >; 207 interrupts = <0 97 0x04>;
207 phy_type = "utmi"; 208 phy_type = "utmi";
209 status = "disable";
210 };
211
212 sdhci@c8000000 {
213 compatible = "nvidia,tegra20-sdhci";
214 reg = <0xc8000000 0x200>;
215 interrupts = <0 14 0x04>;
216 status = "disable";
208 }; 217 };
209};
210 218
219 sdhci@c8000200 {
220 compatible = "nvidia,tegra20-sdhci";
221 reg = <0xc8000200 0x200>;
222 interrupts = <0 15 0x04>;
223 status = "disable";
224 };
225
226 sdhci@c8000400 {
227 compatible = "nvidia,tegra20-sdhci";
228 reg = <0xc8000400 0x200>;
229 interrupts = <0 19 0x04>;
230 status = "disable";
231 };
232
233 sdhci@c8000600 {
234 compatible = "nvidia,tegra20-sdhci";
235 reg = <0xc8000600 0x200>;
236 interrupts = <0 31 0x04>;
237 status = "disable";
238 };
239
240 pmu {
241 compatible = "arm,cortex-a9-pmu";
242 interrupts = <0 56 0x04
243 0 57 0x04>;
244 };
245};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 62a7b39f1c9a..2dcc09e784b5 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,183 +4,268 @@
4 compatible = "nvidia,tegra30"; 4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 pmc@7000f400 { 7 intc: interrupt-controller {
8 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
9 reg = <0x7000e400 0x400>;
10 };
11
12 intc: interrupt-controller@50041000 {
13 compatible = "arm,cortex-a9-gic"; 8 compatible = "arm,cortex-a9-gic";
9 reg = <0x50041000 0x1000
10 0x50040100 0x0100>;
14 interrupt-controller; 11 interrupt-controller;
15 #interrupt-cells = <3>; 12 #interrupt-cells = <3>;
16 reg = < 0x50041000 0x1000 >,
17 < 0x50040100 0x0100 >;
18 }; 13 };
19 14
20 pmu { 15 apbdma: dma {
21 compatible = "arm,cortex-a9-pmu";
22 interrupts = <0 144 0x04
23 0 145 0x04
24 0 146 0x04
25 0 147 0x04>;
26 };
27
28 apbdma: dma@6000a000 {
29 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 16 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
30 reg = <0x6000a000 0x1400>; 17 reg = <0x6000a000 0x1400>;
31 interrupts = < 0 104 0x04 18 interrupts = <0 104 0x04
32 0 105 0x04 19 0 105 0x04
33 0 106 0x04 20 0 106 0x04
34 0 107 0x04 21 0 107 0x04
35 0 108 0x04 22 0 108 0x04
36 0 109 0x04 23 0 109 0x04
37 0 110 0x04 24 0 110 0x04
38 0 111 0x04 25 0 111 0x04
39 0 112 0x04 26 0 112 0x04
40 0 113 0x04 27 0 113 0x04
41 0 114 0x04 28 0 114 0x04
42 0 115 0x04 29 0 115 0x04
43 0 116 0x04 30 0 116 0x04
44 0 117 0x04 31 0 117 0x04
45 0 118 0x04 32 0 118 0x04
46 0 119 0x04 33 0 119 0x04
47 0 128 0x04 34 0 128 0x04
48 0 129 0x04 35 0 129 0x04
49 0 130 0x04 36 0 130 0x04
50 0 131 0x04 37 0 131 0x04
51 0 132 0x04 38 0 132 0x04
52 0 133 0x04 39 0 133 0x04
53 0 134 0x04 40 0 134 0x04
54 0 135 0x04 41 0 135 0x04
55 0 136 0x04 42 0 136 0x04
56 0 137 0x04 43 0 137 0x04
57 0 138 0x04 44 0 138 0x04
58 0 139 0x04 45 0 139 0x04
59 0 140 0x04 46 0 140 0x04
60 0 141 0x04 47 0 141 0x04
61 0 142 0x04 48 0 142 0x04
62 0 143 0x04 >; 49 0 143 0x04>;
63 };
64
65 i2c@7000c000 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
69 reg = <0x7000C000 0x100>;
70 interrupts = < 0 38 0x04 >;
71 };
72
73 i2c@7000c400 {
74 #address-cells = <1>;
75 #size-cells = <0>;
76 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
77 reg = <0x7000C400 0x100>;
78 interrupts = < 0 84 0x04 >;
79 };
80
81 i2c@7000c500 {
82 #address-cells = <1>;
83 #size-cells = <0>;
84 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
85 reg = <0x7000C500 0x100>;
86 interrupts = < 0 92 0x04 >;
87 }; 50 };
88 51
89 i2c@7000c700 { 52 ahb: ahb {
90 #address-cells = <1>; 53 compatible = "nvidia,tegra30-ahb";
91 #size-cells = <0>; 54 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
92 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
93 reg = <0x7000c700 0x100>;
94 interrupts = < 0 120 0x04 >;
95 }; 55 };
96 56
97 i2c@7000d000 { 57 gpio: gpio {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
101 reg = <0x7000D000 0x100>;
102 interrupts = < 0 53 0x04 >;
103 };
104
105 gpio: gpio@6000d000 {
106 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; 58 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
107 reg = < 0x6000d000 0x1000 >; 59 reg = <0x6000d000 0x1000>;
108 interrupts = < 0 32 0x04 60 interrupts = <0 32 0x04
109 0 33 0x04 61 0 33 0x04
110 0 34 0x04 62 0 34 0x04
111 0 35 0x04 63 0 35 0x04
112 0 55 0x04 64 0 55 0x04
113 0 87 0x04 65 0 87 0x04
114 0 89 0x04 66 0 89 0x04
115 0 125 0x04 >; 67 0 125 0x04>;
116 #gpio-cells = <2>; 68 #gpio-cells = <2>;
117 gpio-controller; 69 gpio-controller;
118 #interrupt-cells = <2>; 70 #interrupt-cells = <2>;
119 interrupt-controller; 71 interrupt-controller;
120 }; 72 };
121 73
74 pinmux: pinmux {
75 compatible = "nvidia,tegra30-pinmux";
76 reg = <0x70000868 0xd0 /* Pad control registers */
77 0x70003000 0x3e0>; /* Mux registers */
78 };
79
122 serial@70006000 { 80 serial@70006000 {
123 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 81 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
124 reg = <0x70006000 0x40>; 82 reg = <0x70006000 0x40>;
125 reg-shift = <2>; 83 reg-shift = <2>;
126 interrupts = < 0 36 0x04 >; 84 interrupts = <0 36 0x04>;
85 status = "disable";
127 }; 86 };
128 87
129 serial@70006040 { 88 serial@70006040 {
130 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 89 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
131 reg = <0x70006040 0x40>; 90 reg = <0x70006040 0x40>;
132 reg-shift = <2>; 91 reg-shift = <2>;
133 interrupts = < 0 37 0x04 >; 92 interrupts = <0 37 0x04>;
93 status = "disable";
134 }; 94 };
135 95
136 serial@70006200 { 96 serial@70006200 {
137 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 97 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
138 reg = <0x70006200 0x100>; 98 reg = <0x70006200 0x100>;
139 reg-shift = <2>; 99 reg-shift = <2>;
140 interrupts = < 0 46 0x04 >; 100 interrupts = <0 46 0x04>;
101 status = "disable";
141 }; 102 };
142 103
143 serial@70006300 { 104 serial@70006300 {
144 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 105 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
145 reg = <0x70006300 0x100>; 106 reg = <0x70006300 0x100>;
146 reg-shift = <2>; 107 reg-shift = <2>;
147 interrupts = < 0 90 0x04 >; 108 interrupts = <0 90 0x04>;
109 status = "disable";
148 }; 110 };
149 111
150 serial@70006400 { 112 serial@70006400 {
151 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 113 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
152 reg = <0x70006400 0x100>; 114 reg = <0x70006400 0x100>;
153 reg-shift = <2>; 115 reg-shift = <2>;
154 interrupts = < 0 91 0x04 >; 116 interrupts = <0 91 0x04>;
117 status = "disable";
118 };
119
120 i2c@7000c000 {
121 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
122 reg = <0x7000c000 0x100>;
123 interrupts = <0 38 0x04>;
124 #address-cells = <1>;
125 #size-cells = <0>;
126 status = "disable";
127 };
128
129 i2c@7000c400 {
130 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
131 reg = <0x7000c400 0x100>;
132 interrupts = <0 84 0x04>;
133 #address-cells = <1>;
134 #size-cells = <0>;
135 status = "disable";
136 };
137
138 i2c@7000c500 {
139 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
140 reg = <0x7000c500 0x100>;
141 interrupts = <0 92 0x04>;
142 #address-cells = <1>;
143 #size-cells = <0>;
144 status = "disable";
145 };
146
147 i2c@7000c700 {
148 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
149 reg = <0x7000c700 0x100>;
150 interrupts = <0 120 0x04>;
151 #address-cells = <1>;
152 #size-cells = <0>;
153 status = "disable";
154 };
155
156 i2c@7000d000 {
157 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
158 reg = <0x7000d000 0x100>;
159 interrupts = <0 53 0x04>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 status = "disable";
163 };
164
165 pmc {
166 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
167 reg = <0x7000e400 0x400>;
168 };
169
170 mc {
171 compatible = "nvidia,tegra30-mc";
172 reg = <0x7000f000 0x010
173 0x7000f03c 0x1b4
174 0x7000f200 0x028
175 0x7000f284 0x17c>;
176 interrupts = <0 77 0x04>;
177 };
178
179 smmu {
180 compatible = "nvidia,tegra30-smmu";
181 reg = <0x7000f010 0x02c
182 0x7000f1f0 0x010
183 0x7000f228 0x05c>;
184 nvidia,#asids = <4>; /* # of ASIDs */
185 dma-window = <0 0x40000000>; /* IOVA start & length */
186 nvidia,ahb = <&ahb>;
187 };
188
189 ahub {
190 compatible = "nvidia,tegra30-ahub";
191 reg = <0x70080000 0x200
192 0x70080200 0x100>;
193 interrupts = <0 103 0x04>;
194 nvidia,dma-request-selector = <&apbdma 1>;
195
196 ranges;
197 #address-cells = <1>;
198 #size-cells = <1>;
199
200 tegra_i2s0: i2s@70080300 {
201 compatible = "nvidia,tegra30-i2s";
202 reg = <0x70080300 0x100>;
203 nvidia,ahub-cif-ids = <4 4>;
204 status = "disable";
205 };
206
207 tegra_i2s1: i2s@70080400 {
208 compatible = "nvidia,tegra30-i2s";
209 reg = <0x70080400 0x100>;
210 nvidia,ahub-cif-ids = <5 5>;
211 status = "disable";
212 };
213
214 tegra_i2s2: i2s@70080500 {
215 compatible = "nvidia,tegra30-i2s";
216 reg = <0x70080500 0x100>;
217 nvidia,ahub-cif-ids = <6 6>;
218 status = "disable";
219 };
220
221 tegra_i2s3: i2s@70080600 {
222 compatible = "nvidia,tegra30-i2s";
223 reg = <0x70080600 0x100>;
224 nvidia,ahub-cif-ids = <7 7>;
225 status = "disable";
226 };
227
228 tegra_i2s4: i2s@70080700 {
229 compatible = "nvidia,tegra30-i2s";
230 reg = <0x70080700 0x100>;
231 nvidia,ahub-cif-ids = <8 8>;
232 status = "disable";
233 };
155 }; 234 };
156 235
157 sdhci@78000000 { 236 sdhci@78000000 {
158 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 237 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
159 reg = <0x78000000 0x200>; 238 reg = <0x78000000 0x200>;
160 interrupts = < 0 14 0x04 >; 239 interrupts = <0 14 0x04>;
240 status = "disable";
161 }; 241 };
162 242
163 sdhci@78000200 { 243 sdhci@78000200 {
164 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 244 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
165 reg = <0x78000200 0x200>; 245 reg = <0x78000200 0x200>;
166 interrupts = < 0 15 0x04 >; 246 interrupts = <0 15 0x04>;
247 status = "disable";
167 }; 248 };
168 249
169 sdhci@78000400 { 250 sdhci@78000400 {
170 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 251 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
171 reg = <0x78000400 0x200>; 252 reg = <0x78000400 0x200>;
172 interrupts = < 0 19 0x04 >; 253 interrupts = <0 19 0x04>;
254 status = "disable";
173 }; 255 };
174 256
175 sdhci@78000600 { 257 sdhci@78000600 {
176 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 258 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
177 reg = <0x78000600 0x200>; 259 reg = <0x78000600 0x200>;
178 interrupts = < 0 31 0x04 >; 260 interrupts = <0 31 0x04>;
261 status = "disable";
179 }; 262 };
180 263
181 pinmux: pinmux@70000000 { 264 pmu {
182 compatible = "nvidia,tegra30-pinmux"; 265 compatible = "arm,cortex-a9-pmu";
183 reg = < 0x70000868 0xd0 /* Pad control registers */ 266 interrupts = <0 144 0x04
184 0x70003000 0x3e0 >; /* Mux registers */ 267 0 145 0x04
268 0 146 0x04
269 0 147 0x04>;
185 }; 270 };
186}; 271};
diff --git a/arch/arm/boot/dts/tny_a9260.dts b/arch/arm/boot/dts/tny_a9260.dts
new file mode 100644
index 000000000000..367a16dcd5ef
--- /dev/null
+++ b/arch/arm/boot/dts/tny_a9260.dts
@@ -0,0 +1,15 @@
1/*
2 * tny_a9260.dts - Device Tree file for Caloa TNY A9260 board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8/dts-v1/;
9/include/ "at91sam9260.dtsi"
10/include/ "tny_a9260_common.dtsi"
11
12/ {
13 model = "Calao TNY A9260";
14 compatible = "calao,tny-a9260", "atmel,at91sam9260", "atmel,at91sam9";
15};
diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi
new file mode 100644
index 000000000000..0e6d3de2e09e
--- /dev/null
+++ b/arch/arm/boot/dts/tny_a9260_common.dtsi
@@ -0,0 +1,83 @@
1/*
2 * tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/ {
10 chosen {
11 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs";
12 };
13
14 memory {
15 reg = <0x20000000 0x4000000>;
16 };
17
18 clocks {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges;
22
23 main_clock: clock@0 {
24 compatible = "atmel,osc", "fixed-clock";
25 clock-frequency = <12000000>;
26 };
27 };
28
29 ahb {
30 apb {
31 dbgu: serial@fffff200 {
32 status = "okay";
33 };
34 };
35
36 nand0: nand@40000000 {
37 nand-bus-width = <8>;
38 nand-ecc-mode = "soft";
39 nand-on-flash-bbt;
40 status = "okay";
41
42 at91bootstrap@0 {
43 label = "at91bootstrap";
44 reg = <0x0 0x20000>;
45 };
46
47 barebox@20000 {
48 label = "barebox";
49 reg = <0x20000 0x40000>;
50 };
51
52 bareboxenv@60000 {
53 label = "bareboxenv";
54 reg = <0x60000 0x20000>;
55 };
56
57 bareboxenv2@80000 {
58 label = "bareboxenv2";
59 reg = <0x80000 0x20000>;
60 };
61
62 oftree@80000 {
63 label = "oftree";
64 reg = <0xa0000 0x20000>;
65 };
66
67 kernel@a0000 {
68 label = "kernel";
69 reg = <0xc0000 0x400000>;
70 };
71
72 rootfs@4a0000 {
73 label = "rootfs";
74 reg = <0x4c0000 0x7800000>;
75 };
76
77 data@7ca0000 {
78 label = "data";
79 reg = <0x7cc0000 0x8340000>;
80 };
81 };
82 };
83};
diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts
new file mode 100644
index 000000000000..dee9c571306b
--- /dev/null
+++ b/arch/arm/boot/dts/tny_a9263.dts
@@ -0,0 +1,97 @@
1/*
2 * usb_a9263.dts - Device Tree file for Caloa USB A9293 board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only
7 */
8/dts-v1/;
9/include/ "at91sam9263.dtsi"
10
11/ {
12 model = "Calao TNY A9263";
13 compatible = "atmel,tny-a9263", "atmel,at91sam9263", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
17 };
18
19 memory {
20 reg = <0x20000000 0x4000000>;
21 };
22
23 clocks {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 main_clock: clock@0 {
29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <12000000>;
31 };
32 };
33
34 ahb {
35 apb {
36 dbgu: serial@ffffee00 {
37 status = "okay";
38 };
39
40 usb1: gadget@fff78000 {
41 atmel,vbus-gpio = <&pioB 11 0>;
42 status = "okay";
43 };
44 };
45
46 nand0: nand@40000000 {
47 nand-bus-width = <8>;
48 nand-ecc-mode = "soft";
49 nand-on-flash-bbt;
50 status = "okay";
51
52 at91bootstrap@0 {
53 label = "at91bootstrap";
54 reg = <0x0 0x20000>;
55 };
56
57 barebox@20000 {
58 label = "barebox";
59 reg = <0x20000 0x40000>;
60 };
61
62 bareboxenv@60000 {
63 label = "bareboxenv";
64 reg = <0x60000 0x20000>;
65 };
66
67 bareboxenv2@80000 {
68 label = "bareboxenv2";
69 reg = <0x80000 0x20000>;
70 };
71
72 oftree@80000 {
73 label = "oftree";
74 reg = <0xa0000 0x20000>;
75 };
76
77 kernel@a0000 {
78 label = "kernel";
79 reg = <0xc0000 0x400000>;
80 };
81
82 rootfs@4a0000 {
83 label = "rootfs";
84 reg = <0x4c0000 0x7800000>;
85 };
86
87 data@7ca0000 {
88 label = "data";
89 reg = <0x7cc0000 0x8340000>;
90 };
91 };
92 };
93
94 i2c@0 {
95 status = "okay";
96 };
97};
diff --git a/arch/arm/boot/dts/tny_a9g20.dts b/arch/arm/boot/dts/tny_a9g20.dts
new file mode 100644
index 000000000000..e1ab64c72dba
--- /dev/null
+++ b/arch/arm/boot/dts/tny_a9g20.dts
@@ -0,0 +1,15 @@
1/*
2 * tny_a9g20.dts - Device Tree file for Caloa TNY A9G20 board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8/dts-v1/;
9/include/ "at91sam9g20.dtsi"
10/include/ "tny_a9260_common.dtsi"
11
12/ {
13 model = "Calao TNY A9G20";
14 compatible = "calao,tny-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
15};
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
new file mode 100644
index 000000000000..22f4d1394ed3
--- /dev/null
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -0,0 +1,47 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Integrated Power Management Chip
11 */
12&twl {
13 compatible = "ti,twl4030";
14 interrupt-controller;
15 #interrupt-cells = <1>;
16
17 rtc {
18 compatible = "ti,twl4030-rtc";
19 interrupts = <11>;
20 };
21
22 vdac: regulator@0 {
23 compatible = "ti,twl4030-vdac";
24 regulator-min-microvolt = <1800000>;
25 regulator-max-microvolt = <1800000>;
26 };
27
28 vpll2: regulator@1 {
29 compatible = "ti,twl4030-vpll2";
30 regulator-min-microvolt = <1800000>;
31 regulator-max-microvolt = <1800000>;
32 };
33
34 vmmc1: regulator@2 {
35 compatible = "ti,twl4030-vmmc1";
36 regulator-min-microvolt = <1850000>;
37 regulator-max-microvolt = <3150000>;
38 };
39
40 twl_gpio: gpio {
41 compatible = "ti,twl4030-gpio";
42 gpio-controller;
43 #gpio-cells = <2>;
44 interrupt-controller;
45 #interrupt-cells = <1>;
46 };
47};
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
new file mode 100644
index 000000000000..3b2f3510d7eb
--- /dev/null
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -0,0 +1,86 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Integrated Power Management Chip
11 * http://www.ti.com/lit/ds/symlink/twl6030.pdf
12 */
13&twl {
14 compatible = "ti,twl6030";
15 interrupt-controller;
16 #interrupt-cells = <1>;
17
18 rtc {
19 compatible = "ti,twl4030-rtc";
20 interrupts = <11>;
21 };
22
23 vaux1: regulator@0 {
24 compatible = "ti,twl6030-vaux1";
25 regulator-min-microvolt = <1000000>;
26 regulator-max-microvolt = <3000000>;
27 };
28
29 vaux2: regulator@1 {
30 compatible = "ti,twl6030-vaux2";
31 regulator-min-microvolt = <1200000>;
32 regulator-max-microvolt = <2800000>;
33 };
34
35 vaux3: regulator@2 {
36 compatible = "ti,twl6030-vaux3";
37 regulator-min-microvolt = <1000000>;
38 regulator-max-microvolt = <3000000>;
39 };
40
41 vmmc: regulator@3 {
42 compatible = "ti,twl6030-vmmc";
43 regulator-min-microvolt = <1200000>;
44 regulator-max-microvolt = <3000000>;
45 };
46
47 vpp: regulator@4 {
48 compatible = "ti,twl6030-vpp";
49 regulator-min-microvolt = <1800000>;
50 regulator-max-microvolt = <2500000>;
51 };
52
53 vusim: regulator@5 {
54 compatible = "ti,twl6030-vusim";
55 regulator-min-microvolt = <1200000>;
56 regulator-max-microvolt = <2900000>;
57 };
58
59 vdac: regulator@6 {
60 compatible = "ti,twl6030-vdac";
61 };
62
63 vana: regulator@7 {
64 compatible = "ti,twl6030-vana";
65 };
66
67 vcxio: regulator@8 {
68 compatible = "ti,twl6030-vcxio";
69 };
70
71 vusb: regulator@9 {
72 compatible = "ti,twl6030-vusb";
73 };
74
75 v1v8: regulator@10 {
76 compatible = "ti,twl6030-v1v8";
77 };
78
79 v2v1: regulator@11 {
80 compatible = "ti,twl6030-v2v1";
81 };
82
83 clk32kg: regulator@12 {
84 compatible = "ti,twl6030-clk32kg";
85 };
86};
diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts
new file mode 100644
index 000000000000..296216058c11
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9260.dts
@@ -0,0 +1,23 @@
1/*
2 * usb_a9260.dts - Device Tree file for Caloa USB A9260 board
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8/dts-v1/;
9/include/ "at91sam9260.dtsi"
10/include/ "usb_a9260_common.dtsi"
11
12/ {
13 model = "Calao USB A9260";
14 compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9";
15
16 chosen {
17 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
18 };
19
20 memory {
21 reg = <0x20000000 0x4000000>;
22 };
23};
diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi
new file mode 100644
index 000000000000..e70d229baef5
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9260_common.dtsi
@@ -0,0 +1,117 @@
1/*
2 * usb_a926x.dts - Device Tree file for Caloa USB A926x board
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/ {
10 clocks {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges;
14
15 main_clock: clock@0 {
16 compatible = "atmel,osc", "fixed-clock";
17 clock-frequency = <12000000>;
18 };
19 };
20
21 ahb {
22 apb {
23 dbgu: serial@fffff200 {
24 status = "okay";
25 };
26
27 macb0: ethernet@fffc4000 {
28 phy-mode = "rmii";
29 status = "okay";
30 };
31
32 usb1: gadget@fffa4000 {
33 atmel,vbus-gpio = <&pioC 5 0>;
34 status = "okay";
35 };
36 };
37
38 nand0: nand@40000000 {
39 nand-bus-width = <8>;
40 nand-ecc-mode = "soft";
41 nand-on-flash-bbt;
42 status = "okay";
43
44 at91bootstrap@0 {
45 label = "at91bootstrap";
46 reg = <0x0 0x20000>;
47 };
48
49 barebox@20000 {
50 label = "barebox";
51 reg = <0x20000 0x40000>;
52 };
53
54 bareboxenv@60000 {
55 label = "bareboxenv";
56 reg = <0x60000 0x20000>;
57 };
58
59 bareboxenv2@80000 {
60 label = "bareboxenv2";
61 reg = <0x80000 0x20000>;
62 };
63
64 oftree@80000 {
65 label = "oftree";
66 reg = <0xa0000 0x20000>;
67 };
68
69 kernel@a0000 {
70 label = "kernel";
71 reg = <0xc0000 0x400000>;
72 };
73
74 rootfs@4a0000 {
75 label = "rootfs";
76 reg = <0x4c0000 0x7800000>;
77 };
78
79 data@7ca0000 {
80 label = "data";
81 reg = <0x7cc0000 0x8340000>;
82 };
83 };
84
85 usb0: ohci@00500000 {
86 num-ports = <2>;
87 status = "okay";
88 };
89 };
90
91 leds {
92 compatible = "gpio-leds";
93
94 user_led {
95 label = "user_led";
96 gpios = <&pioB 21 1>;
97 linux,default-trigger = "heartbeat";
98 };
99 };
100
101 gpio_keys {
102 compatible = "gpio-keys";
103 #address-cells = <1>;
104 #size-cells = <0>;
105
106 user_pb {
107 label = "user_pb";
108 gpios = <&pioB 10 1>;
109 linux,code = <28>;
110 gpio-key,wakeup;
111 };
112 };
113
114 i2c@0 {
115 status = "okay";
116 };
117};
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
new file mode 100644
index 000000000000..6fe05ccb6203
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -0,0 +1,131 @@
1/*
2 * usb_a9263.dts - Device Tree file for Caloa USB A9293 board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only
7 */
8/dts-v1/;
9/include/ "at91sam9263.dtsi"
10
11/ {
12 model = "Calao USB A9263";
13 compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
17 };
18
19 memory {
20 reg = <0x20000000 0x4000000>;
21 };
22
23 clocks {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 main_clock: clock@0 {
29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <12000000>;
31 };
32 };
33
34 ahb {
35 apb {
36 dbgu: serial@ffffee00 {
37 status = "okay";
38 };
39
40 macb0: ethernet@fffbc000 {
41 phy-mode = "rmii";
42 status = "okay";
43 };
44
45 usb1: gadget@fff78000 {
46 atmel,vbus-gpio = <&pioB 11 0>;
47 status = "okay";
48 };
49
50 };
51
52 nand0: nand@40000000 {
53 nand-bus-width = <8>;
54 nand-ecc-mode = "soft";
55 nand-on-flash-bbt;
56 status = "okay";
57
58 at91bootstrap@0 {
59 label = "at91bootstrap";
60 reg = <0x0 0x20000>;
61 };
62
63 barebox@20000 {
64 label = "barebox";
65 reg = <0x20000 0x40000>;
66 };
67
68 bareboxenv@60000 {
69 label = "bareboxenv";
70 reg = <0x60000 0x20000>;
71 };
72
73 bareboxenv2@80000 {
74 label = "bareboxenv2";
75 reg = <0x80000 0x20000>;
76 };
77
78 oftree@80000 {
79 label = "oftree";
80 reg = <0xa0000 0x20000>;
81 };
82
83 kernel@a0000 {
84 label = "kernel";
85 reg = <0xc0000 0x400000>;
86 };
87
88 rootfs@4a0000 {
89 label = "rootfs";
90 reg = <0x4c0000 0x7800000>;
91 };
92
93 data@7ca0000 {
94 label = "data";
95 reg = <0x7cc0000 0x8340000>;
96 };
97 };
98
99 usb0: ohci@00a00000 {
100 num-ports = <2>;
101 status = "okay";
102 };
103 };
104
105 leds {
106 compatible = "gpio-leds";
107
108 user_led {
109 label = "user_led";
110 gpios = <&pioB 21 0>;
111 linux,default-trigger = "heartbeat";
112 };
113 };
114
115 gpio_keys {
116 compatible = "gpio-keys";
117 #address-cells = <1>;
118 #size-cells = <0>;
119
120 user_pb {
121 label = "user_pb";
122 gpios = <&pioB 10 1>;
123 linux,code = <28>;
124 gpio-key,wakeup;
125 };
126 };
127
128 i2c@0 {
129 status = "okay";
130 };
131};
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index 7c2399c532e5..2dacb16ce4ae 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -7,6 +7,7 @@
7 */ 7 */
8/dts-v1/; 8/dts-v1/;
9/include/ "at91sam9g20.dtsi" 9/include/ "at91sam9g20.dtsi"
10/include/ "usb_a9260_common.dtsi"
10 11
11/ { 12/ {
12 model = "Calao USB A9G20"; 13 model = "Calao USB A9G20";
@@ -20,108 +21,7 @@
20 reg = <0x20000000 0x4000000>; 21 reg = <0x20000000 0x4000000>;
21 }; 22 };
22 23
23 clocks {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 main_clock: clock@0 {
29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <12000000>;
31 };
32 };
33
34 ahb {
35 apb {
36 dbgu: serial@fffff200 {
37 status = "okay";
38 };
39
40 macb0: ethernet@fffc4000 {
41 phy-mode = "rmii";
42 status = "okay";
43 };
44
45 usb1: gadget@fffa4000 {
46 atmel,vbus-gpio = <&pioC 5 0>;
47 status = "okay";
48 };
49 };
50
51 nand0: nand@40000000 {
52 nand-bus-width = <8>;
53 nand-ecc-mode = "soft";
54 nand-on-flash-bbt;
55 status = "okay";
56
57 at91bootstrap@0 {
58 label = "at91bootstrap";
59 reg = <0x0 0x20000>;
60 };
61
62 barebox@20000 {
63 label = "barebox";
64 reg = <0x20000 0x40000>;
65 };
66
67 bareboxenv@60000 {
68 label = "bareboxenv";
69 reg = <0x60000 0x20000>;
70 };
71
72 bareboxenv2@80000 {
73 label = "bareboxenv2";
74 reg = <0x80000 0x20000>;
75 };
76
77 kernel@a0000 {
78 label = "kernel";
79 reg = <0xa0000 0x400000>;
80 };
81
82 rootfs@4a0000 {
83 label = "rootfs";
84 reg = <0x4a0000 0x7800000>;
85 };
86
87 data@7ca0000 {
88 label = "data";
89 reg = <0x7ca0000 0x8360000>;
90 };
91 };
92
93 usb0: ohci@00500000 {
94 num-ports = <2>;
95 status = "okay";
96 };
97 };
98
99 leds {
100 compatible = "gpio-leds";
101
102 user_led {
103 label = "user_led";
104 gpios = <&pioB 21 1>;
105 linux,default-trigger = "heartbeat";
106 };
107 };
108
109 gpio_keys {
110 compatible = "gpio-keys";
111 #address-cells = <1>;
112 #size-cells = <0>;
113
114 user_pb {
115 label = "user_pb";
116 gpios = <&pioB 10 1>;
117 linux,code = <28>;
118 gpio-key,wakeup;
119 };
120 };
121
122 i2c@0 { 24 i2c@0 {
123 status = "okay";
124
125 rv3029c2@56 { 25 rv3029c2@56 {
126 compatible = "rv3029c2"; 26 compatible = "rv3029c2";
127 reg = <0x56>; 27 reg = <0x56>;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 08:16:19 -0400