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-rw-r--r--arch/arm/boot/dts/armada-370.dtsi52
1 files changed, 52 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 5831994a311b..9cf60b2ce864 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -159,5 +159,57 @@
159 0xd0018304 0x4>; 159 0xd0018304 0x4>;
160 status = "okay"; 160 status = "okay";
161 }; 161 };
162
163 pcie-controller {
164 compatible = "marvell,armada-370-pcie";
165 status = "disabled";
166 device_type = "pci";
167
168 #address-cells = <3>;
169 #size-cells = <2>;
170
171 bus-range = <0x00 0xff>;
172
173 reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>;
174
175 reg-names = "pcie0.0", "pcie1.0";
176
177 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
178 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
179 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
180 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
181
182 pcie@1,0 {
183 device_type = "pci";
184 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
185 reg = <0x0800 0 0 0 0>;
186 #address-cells = <3>;
187 #size-cells = <2>;
188 #interrupt-cells = <1>;
189 ranges;
190 interrupt-map-mask = <0 0 0 0>;
191 interrupt-map = <0 0 0 0 &mpic 58>;
192 marvell,pcie-port = <0>;
193 marvell,pcie-lane = <0>;
194 clocks = <&gateclk 5>;
195 status = "disabled";
196 };
197
198 pcie@2,0 {
199 device_type = "pci";
200 assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
201 reg = <0x1000 0 0 0 0>;
202 #address-cells = <3>;
203 #size-cells = <2>;
204 #interrupt-cells = <1>;
205 ranges;
206 interrupt-map-mask = <0 0 0 0>;
207 interrupt-map = <0 0 0 0 &mpic 62>;
208 marvell,pcie-port = <1>;
209 marvell,pcie-lane = <0>;
210 clocks = <&gateclk 9>;
211 status = "disabled";
212 };
213 };
162 }; 214 };
163}; 215};