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-rw-r--r--arch/arm/boot/dts/Makefile5
-rw-r--r--arch/arm/boot/dts/atlas6-evb.dts78
-rw-r--r--arch/arm/boot/dts/atlas6.dtsi668
-rw-r--r--arch/arm/boot/dts/bcm11351.dtsi8
-rw-r--r--arch/arm/boot/dts/da850-evm.dts70
-rw-r--r--arch/arm/boot/dts/da850.dtsi15
-rw-r--r--arch/arm/boot/dts/msm8660-surf.dts20
-rw-r--r--arch/arm/boot/dts/msm8960-cdp.dts22
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi98
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi1031
-rw-r--r--arch/arm/boot/dts/sama5d31ek.dts51
-rw-r--r--arch/arm/boot/dts/sama5d33ek.dts44
-rw-r--r--arch/arm/boot/dts/sama5d34ek.dts61
-rw-r--r--arch/arm/boot/dts/sama5d35ek.dts56
-rw-r--r--arch/arm/boot/dts/sama5d3xcm.dtsi91
-rw-r--r--arch/arm/boot/dts/sama5d3xdm.dtsi42
-rw-r--r--arch/arm/boot/dts/sama5d3xmb.dtsi166
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi157
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5.dts8
-rw-r--r--arch/arm/boot/dts/socfpga_vt.dts8
-rw-r--r--arch/arm/boot/dts/tegra114-dalmore.dts13
-rw-r--r--arch/arm/boot/dts/tegra114-pluto.dts13
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-512.dtsi13
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts13
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts13
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts13
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi13
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts13
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts13
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts13
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts13
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi13
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi2
-rw-r--r--arch/arm/boot/dts/tps6507x.dtsi47
36 files changed, 2881 insertions, 27 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 2be254709dcb..20358fb43450 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -33,6 +33,11 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
33dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb 33dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
34dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb 34dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
35dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb 35dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
36# sama5d3
37dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb
38dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
39dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
40dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
36 41
37dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 42dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
38dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb 43dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb
diff --git a/arch/arm/boot/dts/atlas6-evb.dts b/arch/arm/boot/dts/atlas6-evb.dts
new file mode 100644
index 000000000000..ab042ca8dea1
--- /dev/null
+++ b/arch/arm/boot/dts/atlas6-evb.dts
@@ -0,0 +1,78 @@
1/*
2 * DTS file for CSR SiRFatlas6 Evaluation Board
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/dts-v1/;
10
11/include/ "atlas6.dtsi"
12
13/ {
14 model = "CSR SiRFatlas6 Evaluation Board";
15 compatible = "sirf,atlas6-cb", "sirf,atlas6";
16
17 memory {
18 reg = <0x00000000 0x20000000>;
19 };
20
21 axi {
22 peri-iobg {
23 uart@b0060000 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart1_pins_a>;
26 };
27 spi@b00d0000 {
28 status = "okay";
29 pinctrl-names = "default";
30 pinctrl-0 = <&spi0_pins_a>;
31 spi@0 {
32 compatible = "spidev";
33 reg = <0>;
34 spi-max-frequency = <1000000>;
35 };
36 };
37 spi@b0170000 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&spi1_pins_a>;
40 };
41 i2c0: i2c@b00e0000 {
42 status = "okay";
43 pinctrl-names = "default";
44 pinctrl-0 = <&i2c0_pins_a>;
45 lcd@40 {
46 compatible = "sirf,lcd";
47 reg = <0x40>;
48 };
49 };
50
51 };
52 disp-iobg {
53 lcd@90010000 {
54 status = "okay";
55 pinctrl-names = "default";
56 pinctrl-0 = <&lcd_24pins_a>;
57 };
58 };
59 };
60 display: display@0 {
61 panels {
62 panel0: panel@0 {
63 panel-name = "Innolux TFT";
64 hactive = <800>;
65 vactive = <480>;
66 left_margin = <20>;
67 right_margin = <234>;
68 upper_margin = <3>;
69 lower_margin = <41>;
70 hsync_len = <3>;
71 vsync_len = <2>;
72 pixclock = <33264000>;
73 sync = <3>;
74 timing = <0x88>;
75 };
76 };
77 };
78};
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
new file mode 100644
index 000000000000..7d1a27949c13
--- /dev/null
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -0,0 +1,668 @@
1/*
2 * DTS file for CSR SiRFatlas6 SoC
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/include/ "skeleton.dtsi"
10/ {
11 compatible = "sirf,atlas6";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&intc>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 reg = <0x0>;
22 d-cache-line-size = <32>;
23 i-cache-line-size = <32>;
24 d-cache-size = <32768>;
25 i-cache-size = <32768>;
26 /* from bootloader */
27 timebase-frequency = <0>;
28 bus-frequency = <0>;
29 clock-frequency = <0>;
30 };
31 };
32
33 axi {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
37 ranges = <0x40000000 0x40000000 0x80000000>;
38
39 intc: interrupt-controller@80020000 {
40 #interrupt-cells = <1>;
41 interrupt-controller;
42 compatible = "sirf,prima2-intc";
43 reg = <0x80020000 0x1000>;
44 };
45
46 sys-iobg {
47 compatible = "simple-bus";
48 #address-cells = <1>;
49 #size-cells = <1>;
50 ranges = <0x88000000 0x88000000 0x40000>;
51
52 clks: clock-controller@88000000 {
53 compatible = "sirf,atlas6-clkc";
54 reg = <0x88000000 0x1000>;
55 interrupts = <3>;
56 #clock-cells = <1>;
57 };
58
59 reset-controller@88010000 {
60 compatible = "sirf,prima2-rstc";
61 reg = <0x88010000 0x1000>;
62 };
63
64 rsc-controller@88020000 {
65 compatible = "sirf,prima2-rsc";
66 reg = <0x88020000 0x1000>;
67 };
68 };
69
70 mem-iobg {
71 compatible = "simple-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 ranges = <0x90000000 0x90000000 0x10000>;
75
76 memory-controller@90000000 {
77 compatible = "sirf,prima2-memc";
78 reg = <0x90000000 0x10000>;
79 interrupts = <27>;
80 clocks = <&clks 5>;
81 };
82 };
83
84 disp-iobg {
85 compatible = "simple-bus";
86 #address-cells = <1>;
87 #size-cells = <1>;
88 ranges = <0x90010000 0x90010000 0x30000>;
89
90 lcd@90010000 {
91 compatible = "sirf,prima2-lcd";
92 reg = <0x90010000 0x20000>;
93 interrupts = <30>;
94 clocks = <&clks 34>;
95 display=<&display>;
96 /* later transfer to pwm */
97 bl-gpio = <&gpio 7 0>;
98 default-panel = <&panel0>;
99 };
100
101 vpp@90020000 {
102 compatible = "sirf,prima2-vpp";
103 reg = <0x90020000 0x10000>;
104 interrupts = <31>;
105 clocks = <&clks 35>;
106 };
107 };
108
109 graphics-iobg {
110 compatible = "simple-bus";
111 #address-cells = <1>;
112 #size-cells = <1>;
113 ranges = <0x98000000 0x98000000 0x8000000>;
114
115 graphics@98000000 {
116 compatible = "powervr,sgx510";
117 reg = <0x98000000 0x8000000>;
118 interrupts = <6>;
119 clocks = <&clks 32>;
120 };
121 };
122
123 dsp-iobg {
124 compatible = "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 ranges = <0xa8000000 0xa8000000 0x2000000>;
128
129 dspif@a8000000 {
130 compatible = "sirf,prima2-dspif";
131 reg = <0xa8000000 0x10000>;
132 interrupts = <9>;
133 };
134
135 gps@a8010000 {
136 compatible = "sirf,prima2-gps";
137 reg = <0xa8010000 0x10000>;
138 interrupts = <7>;
139 clocks = <&clks 9>;
140 };
141
142 dsp@a9000000 {
143 compatible = "sirf,prima2-dsp";
144 reg = <0xa9000000 0x1000000>;
145 interrupts = <8>;
146 clocks = <&clks 8>;
147 };
148 };
149
150 peri-iobg {
151 compatible = "simple-bus";
152 #address-cells = <1>;
153 #size-cells = <1>;
154 ranges = <0xb0000000 0xb0000000 0x180000>,
155 <0x56000000 0x56000000 0x1b00000>;
156
157 timer@b0020000 {
158 compatible = "sirf,prima2-tick";
159 reg = <0xb0020000 0x1000>;
160 interrupts = <0>;
161 };
162
163 nand@b0030000 {
164 compatible = "sirf,prima2-nand";
165 reg = <0xb0030000 0x10000>;
166 interrupts = <41>;
167 clocks = <&clks 26>;
168 };
169
170 audio@b0040000 {
171 compatible = "sirf,prima2-audio";
172 reg = <0xb0040000 0x10000>;
173 interrupts = <35>;
174 clocks = <&clks 27>;
175 };
176
177 uart0: uart@b0050000 {
178 cell-index = <0>;
179 compatible = "sirf,prima2-uart";
180 reg = <0xb0050000 0x1000>;
181 interrupts = <17>;
182 fifosize = <128>;
183 clocks = <&clks 13>;
184 };
185
186 uart1: uart@b0060000 {
187 cell-index = <1>;
188 compatible = "sirf,prima2-uart";
189 reg = <0xb0060000 0x1000>;
190 interrupts = <18>;
191 fifosize = <32>;
192 clocks = <&clks 14>;
193 };
194
195 uart2: uart@b0070000 {
196 cell-index = <2>;
197 compatible = "sirf,prima2-uart";
198 reg = <0xb0070000 0x1000>;
199 interrupts = <19>;
200 fifosize = <128>;
201 clocks = <&clks 15>;
202 };
203
204 usp0: usp@b0080000 {
205 cell-index = <0>;
206 compatible = "sirf,prima2-usp";
207 reg = <0xb0080000 0x10000>;
208 interrupts = <20>;
209 clocks = <&clks 28>;
210 };
211
212 usp1: usp@b0090000 {
213 cell-index = <1>;
214 compatible = "sirf,prima2-usp";
215 reg = <0xb0090000 0x10000>;
216 interrupts = <21>;
217 clocks = <&clks 29>;
218 };
219
220 dmac0: dma-controller@b00b0000 {
221 cell-index = <0>;
222 compatible = "sirf,prima2-dmac";
223 reg = <0xb00b0000 0x10000>;
224 interrupts = <12>;
225 clocks = <&clks 24>;
226 };
227
228 dmac1: dma-controller@b0160000 {
229 cell-index = <1>;
230 compatible = "sirf,prima2-dmac";
231 reg = <0xb0160000 0x10000>;
232 interrupts = <13>;
233 clocks = <&clks 25>;
234 };
235
236 vip@b00C0000 {
237 compatible = "sirf,prima2-vip";
238 reg = <0xb00C0000 0x10000>;
239 clocks = <&clks 31>;
240 };
241
242 spi0: spi@b00d0000 {
243 cell-index = <0>;
244 compatible = "sirf,prima2-spi";
245 reg = <0xb00d0000 0x10000>;
246 interrupts = <15>;
247 sirf,spi-num-chipselects = <1>;
248 cs-gpios = <&gpio 0 0>;
249 sirf,spi-dma-rx-channel = <25>;
250 sirf,spi-dma-tx-channel = <20>;
251 #address-cells = <1>;
252 #size-cells = <0>;
253 clocks = <&clks 19>;
254 status = "disabled";
255 };
256
257 spi1: spi@b0170000 {
258 cell-index = <1>;
259 compatible = "sirf,prima2-spi";
260 reg = <0xb0170000 0x10000>;
261 interrupts = <16>;
262 clocks = <&clks 20>;
263 status = "disabled";
264 };
265
266 i2c0: i2c@b00e0000 {
267 cell-index = <0>;
268 compatible = "sirf,prima2-i2c";
269 reg = <0xb00e0000 0x10000>;
270 interrupts = <24>;
271 #address-cells = <1>;
272 #size-cells = <0>;
273 clocks = <&clks 17>;
274 };
275
276 i2c1: i2c@b00f0000 {
277 cell-index = <1>;
278 compatible = "sirf,prima2-i2c";
279 reg = <0xb00f0000 0x10000>;
280 interrupts = <25>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 clocks = <&clks 18>;
284 };
285
286 tsc@b0110000 {
287 compatible = "sirf,prima2-tsc";
288 reg = <0xb0110000 0x10000>;
289 interrupts = <33>;
290 clocks = <&clks 16>;
291 };
292
293 gpio: pinctrl@b0120000 {
294 #gpio-cells = <2>;
295 #interrupt-cells = <2>;
296 compatible = "sirf,atlas6-pinctrl";
297 reg = <0xb0120000 0x10000>;
298 interrupts = <43 44 45 46 47>;
299 gpio-controller;
300 interrupt-controller;
301
302 lcd_16pins_a: lcd0@0 {
303 lcd {
304 sirf,pins = "lcd_16bitsgrp";
305 sirf,function = "lcd_16bits";
306 };
307 };
308 lcd_18pins_a: lcd0@1 {
309 lcd {
310 sirf,pins = "lcd_18bitsgrp";
311 sirf,function = "lcd_18bits";
312 };
313 };
314 lcd_24pins_a: lcd0@2 {
315 lcd {
316 sirf,pins = "lcd_24bitsgrp";
317 sirf,function = "lcd_24bits";
318 };
319 };
320 lcdrom_pins_a: lcdrom0@0 {
321 lcd {
322 sirf,pins = "lcdromgrp";
323 sirf,function = "lcdrom";
324 };
325 };
326 uart0_pins_a: uart0@0 {
327 uart {
328 sirf,pins = "uart0grp";
329 sirf,function = "uart0";
330 };
331 };
332 uart1_pins_a: uart1@0 {
333 uart {
334 sirf,pins = "uart1grp";
335 sirf,function = "uart1";
336 };
337 };
338 uart2_pins_a: uart2@0 {
339 uart {
340 sirf,pins = "uart2grp";
341 sirf,function = "uart2";
342 };
343 };
344 uart2_noflow_pins_a: uart2@1 {
345 uart {
346 sirf,pins = "uart2_nostreamctrlgrp";
347 sirf,function = "uart2_nostreamctrl";
348 };
349 };
350 spi0_pins_a: spi0@0 {
351 spi {
352 sirf,pins = "spi0grp";
353 sirf,function = "spi0";
354 };
355 };
356 spi1_pins_a: spi1@0 {
357 spi {
358 sirf,pins = "spi1grp";
359 sirf,function = "spi1";
360 };
361 };
362 i2c0_pins_a: i2c0@0 {
363 i2c {
364 sirf,pins = "i2c0grp";
365 sirf,function = "i2c0";
366 };
367 };
368 i2c1_pins_a: i2c1@0 {
369 i2c {
370 sirf,pins = "i2c1grp";
371 sirf,function = "i2c1";
372 };
373 };
374 pwm0_pins_a: pwm0@0 {
375 pwm {
376 sirf,pins = "pwm0grp";
377 sirf,function = "pwm0";
378 };
379 };
380 pwm1_pins_a: pwm1@0 {
381 pwm {
382 sirf,pins = "pwm1grp";
383 sirf,function = "pwm1";
384 };
385 };
386 pwm2_pins_a: pwm2@0 {
387 pwm {
388 sirf,pins = "pwm2grp";
389 sirf,function = "pwm2";
390 };
391 };
392 pwm3_pins_a: pwm3@0 {
393 pwm {
394 sirf,pins = "pwm3grp";
395 sirf,function = "pwm3";
396 };
397 };
398 pwm4_pins_a: pwm4@0 {
399 pwm {
400 sirf,pins = "pwm4grp";
401 sirf,function = "pwm4";
402 };
403 };
404 gps_pins_a: gps@0 {
405 gps {
406 sirf,pins = "gpsgrp";
407 sirf,function = "gps";
408 };
409 };
410 vip_pins_a: vip@0 {
411 vip {
412 sirf,pins = "vipgrp";
413 sirf,function = "vip";
414 };
415 };
416 sdmmc0_pins_a: sdmmc0@0 {
417 sdmmc0 {
418 sirf,pins = "sdmmc0grp";
419 sirf,function = "sdmmc0";
420 };
421 };
422 sdmmc1_pins_a: sdmmc1@0 {
423 sdmmc1 {
424 sirf,pins = "sdmmc1grp";
425 sirf,function = "sdmmc1";
426 };
427 };
428 sdmmc2_pins_a: sdmmc2@0 {
429 sdmmc2 {
430 sirf,pins = "sdmmc2grp";
431 sirf,function = "sdmmc2";
432 };
433 };
434 sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
435 sdmmc2_nowp {
436 sirf,pins = "sdmmc2_nowpgrp";
437 sirf,function = "sdmmc2_nowp";
438 };
439 };
440 sdmmc3_pins_a: sdmmc3@0 {
441 sdmmc3 {
442 sirf,pins = "sdmmc3grp";
443 sirf,function = "sdmmc3";
444 };
445 };
446 sdmmc5_pins_a: sdmmc5@0 {
447 sdmmc5 {
448 sirf,pins = "sdmmc5grp";
449 sirf,function = "sdmmc5";
450 };
451 };
452 i2s_pins_a: i2s@0 {
453 i2s {
454 sirf,pins = "i2sgrp";
455 sirf,function = "i2s";
456 };
457 };
458 i2s_no_din_pins_a: i2s_no_din@0 {
459 i2s_no_din {
460 sirf,pins = "i2s_no_dingrp";
461 sirf,function = "i2s_no_din";
462 };
463 };
464 i2s_6chn_pins_a: i2s_6chn@0 {
465 i2s_6chn {
466 sirf,pins = "i2s_6chngrp";
467 sirf,function = "i2s_6chn";
468 };
469 };
470 ac97_pins_a: ac97@0 {
471 ac97 {
472 sirf,pins = "ac97grp";
473 sirf,function = "ac97";
474 };
475 };
476 nand_pins_a: nand@0 {
477 nand {
478 sirf,pins = "nandgrp";
479 sirf,function = "nand";
480 };
481 };
482 usp0_pins_a: usp0@0 {
483 usp0 {
484 sirf,pins = "usp0grp";
485 sirf,function = "usp0";
486 };
487 };
488 usp1_pins_a: usp1@0 {
489 usp1 {
490 sirf,pins = "usp1grp";
491 sirf,function = "usp1";
492 };
493 };
494 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
495 usb0_upli_drvbus {
496 sirf,pins = "usb0_upli_drvbusgrp";
497 sirf,function = "usb0_upli_drvbus";
498 };
499 };
500 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
501 usb1_utmi_drvbus {
502 sirf,pins = "usb1_utmi_drvbusgrp";
503 sirf,function = "usb1_utmi_drvbus";
504 };
505 };
506 warm_rst_pins_a: warm_rst@0 {
507 warm_rst {
508 sirf,pins = "warm_rstgrp";
509 sirf,function = "warm_rst";
510 };
511 };
512 pulse_count_pins_a: pulse_count@0 {
513 pulse_count {
514 sirf,pins = "pulse_countgrp";
515 sirf,function = "pulse_count";
516 };
517 };
518 cko0_rst_pins_a: cko0_rst@0 {
519 cko0_rst {
520 sirf,pins = "cko0_rstgrp";
521 sirf,function = "cko0_rst";
522 };
523 };
524 cko1_rst_pins_a: cko1_rst@0 {
525 cko1_rst {
526 sirf,pins = "cko1_rstgrp";
527 sirf,function = "cko1_rst";
528 };
529 };
530 };
531
532 pwm@b0130000 {
533 compatible = "sirf,prima2-pwm";
534 reg = <0xb0130000 0x10000>;
535 clocks = <&clks 21>;
536 };
537
538 efusesys@b0140000 {
539 compatible = "sirf,prima2-efuse";
540 reg = <0xb0140000 0x10000>;
541 clocks = <&clks 22>;
542 };
543
544 pulsec@b0150000 {
545 compatible = "sirf,prima2-pulsec";
546 reg = <0xb0150000 0x10000>;
547 interrupts = <48>;
548 clocks = <&clks 23>;
549 };
550
551 pci-iobg {
552 compatible = "sirf,prima2-pciiobg", "simple-bus";
553 #address-cells = <1>;
554 #size-cells = <1>;
555 ranges = <0x56000000 0x56000000 0x1b00000>;
556
557 sd0: sdhci@56000000 {
558 cell-index = <0>;
559 compatible = "sirf,prima2-sdhc";
560 reg = <0x56000000 0x100000>;
561 interrupts = <38>;
562 bus-width = <8>;
563 clocks = <&clks 36>;
564 };
565
566 sd1: sdhci@56100000 {
567 cell-index = <1>;
568 compatible = "sirf,prima2-sdhc";
569 reg = <0x56100000 0x100000>;
570 interrupts = <38>;
571 status = "disabled";
572 clocks = <&clks 36>;
573 };
574
575 sd2: sdhci@56200000 {
576 cell-index = <2>;
577 compatible = "sirf,prima2-sdhc";
578 reg = <0x56200000 0x100000>;
579 interrupts = <23>;
580 status = "disabled";
581 clocks = <&clks 37>;
582 };
583
584 sd3: sdhci@56300000 {
585 cell-index = <3>;
586 compatible = "sirf,prima2-sdhc";
587 reg = <0x56300000 0x100000>;
588 interrupts = <23>;
589 status = "disabled";
590 clocks = <&clks 37>;
591 };
592
593 sd5: sdhci@56500000 {
594 cell-index = <5>;
595 compatible = "sirf,prima2-sdhc";
596 reg = <0x56500000 0x100000>;
597 interrupts = <39>;
598 status = "disabled";
599 clocks = <&clks 38>;
600 };
601
602 pci-copy@57900000 {
603 compatible = "sirf,prima2-pcicp";
604 reg = <0x57900000 0x100000>;
605 interrupts = <40>;
606 };
607
608 rom-interface@57a00000 {
609 compatible = "sirf,prima2-romif";
610 reg = <0x57a00000 0x100000>;
611 };
612 };
613 };
614
615 rtc-iobg {
616 compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
617 #address-cells = <1>;
618 #size-cells = <1>;
619 reg = <0x80030000 0x10000>;
620
621 gpsrtc@1000 {
622 compatible = "sirf,prima2-gpsrtc";
623 reg = <0x1000 0x1000>;
624 interrupts = <55 56 57>;
625 };
626
627 sysrtc@2000 {
628 compatible = "sirf,prima2-sysrtc";
629 reg = <0x2000 0x1000>;
630 interrupts = <52 53 54>;
631 };
632
633 pwrc@3000 {
634 compatible = "sirf,prima2-pwrc";
635 reg = <0x3000 0x1000>;
636 interrupts = <32>;
637 };
638 };
639
640 uus-iobg {
641 compatible = "simple-bus";
642 #address-cells = <1>;
643 #size-cells = <1>;
644 ranges = <0xb8000000 0xb8000000 0x40000>;
645
646 usb0: usb@b00e0000 {
647 compatible = "chipidea,ci13611a-prima2";
648 reg = <0xb8000000 0x10000>;
649 interrupts = <10>;
650 clocks = <&clks 40>;
651 };
652
653 usb1: usb@b00f0000 {
654 compatible = "chipidea,ci13611a-prima2";
655 reg = <0xb8010000 0x10000>;
656 interrupts = <11>;
657 clocks = <&clks 41>;
658 };
659
660 security@b00f0000 {
661 compatible = "sirf,prima2-security";
662 reg = <0xb8030000 0x10000>;
663 interrupts = <42>;
664 clocks = <&clks 7>;
665 };
666 };
667 };
668};
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index ad135885bd2a..8f71f40722b9 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -47,4 +47,12 @@
47 cache-unified; 47 cache-unified;
48 cache-level = <2>; 48 cache-level = <2>;
49 }; 49 };
50
51 timer@35006000 {
52 compatible = "bcm,kona-timer";
53 reg = <0x35006000 0x1000>;
54 interrupts = <0x0 7 0x4>;
55 clock-frequency = <32768>;
56 };
57
50}; 58};
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index f712fb607a42..c5834a6c5bf4 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -35,14 +35,84 @@
35 clock-frequency = <100000>; 35 clock-frequency = <100000>;
36 pinctrl-names = "default"; 36 pinctrl-names = "default";
37 pinctrl-0 = <&i2c0_pins>; 37 pinctrl-0 = <&i2c0_pins>;
38
39 tps: tps@48 {
40 reg = <0x48>;
41 };
38 }; 42 };
39 wdt: wdt@1c21000 { 43 wdt: wdt@1c21000 {
40 status = "okay"; 44 status = "okay";
41 }; 45 };
46 mmc0: mmc@1c40000 {
47 max-frequency = <50000000>;
48 bus-width = <4>;
49 status = "okay";
50 pinctrl-names = "default";
51 pinctrl-0 = <&mmc0_pins>;
52 };
42 }; 53 };
43 nand_cs3@62000000 { 54 nand_cs3@62000000 {
44 status = "okay"; 55 status = "okay";
45 pinctrl-names = "default"; 56 pinctrl-names = "default";
46 pinctrl-0 = <&nand_cs3_pins>; 57 pinctrl-0 = <&nand_cs3_pins>;
47 }; 58 };
59 vbat: fixedregulator@0 {
60 compatible = "regulator-fixed";
61 regulator-name = "vbat";
62 regulator-min-microvolt = <5000000>;
63 regulator-max-microvolt = <5000000>;
64 regulator-boot-on;
65 };
66};
67
68/include/ "tps6507x.dtsi"
69
70&tps {
71 vdcdc1_2-supply = <&vbat>;
72 vdcdc3-supply = <&vbat>;
73 vldo1_2-supply = <&vbat>;
74
75 regulators {
76 vdcdc1_reg: regulator@0 {
77 regulator-name = "VDCDC1_3.3V";
78 regulator-min-microvolt = <3150000>;
79 regulator-max-microvolt = <3450000>;
80 regulator-always-on;
81 regulator-boot-on;
82 };
83
84 vdcdc2_reg: regulator@1 {
85 regulator-name = "VDCDC2_3.3V";
86 regulator-min-microvolt = <1710000>;
87 regulator-max-microvolt = <3450000>;
88 regulator-always-on;
89 regulator-boot-on;
90 ti,defdcdc_default = <1>;
91 };
92
93 vdcdc3_reg: regulator@2 {
94 regulator-name = "VDCDC3_1.2V";
95 regulator-min-microvolt = <950000>;
96 regulator-max-microvolt = <1350000>;
97 regulator-always-on;
98 regulator-boot-on;
99 ti,defdcdc_default = <1>;
100 };
101
102 ldo1_reg: regulator@3 {
103 regulator-name = "LDO1_1.8V";
104 regulator-min-microvolt = <1710000>;
105 regulator-max-microvolt = <1890000>;
106 regulator-always-on;
107 regulator-boot-on;
108 };
109
110 ldo2_reg: regulator@4 {
111 regulator-name = "LDO2_1.2V";
112 regulator-min-microvolt = <1140000>;
113 regulator-max-microvolt = <1320000>;
114 regulator-always-on;
115 regulator-boot-on;
116 };
117 };
48}; 118};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 3ec1bda64356..3ade343f13cc 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -62,6 +62,15 @@
62 0x10 0x00002200 0x0000ff00 62 0x10 0x00002200 0x0000ff00
63 >; 63 >;
64 }; 64 };
65 mmc0_pins: pinmux_mmc_pins {
66 pinctrl-single,bits = <
67 /* MMCSD0_DAT[3] MMCSD0_DAT[2]
68 * MMCSD0_DAT[1] MMCSD0_DAT[0]
69 * MMCSD0_CMD MMCSD0_CLK
70 */
71 0x28 0x00222222 0x00ffffff
72 >;
73 };
65 }; 74 };
66 serial0: serial@1c42000 { 75 serial0: serial@1c42000 {
67 compatible = "ns16550a"; 76 compatible = "ns16550a";
@@ -107,6 +116,12 @@
107 reg = <0x21000 0x1000>; 116 reg = <0x21000 0x1000>;
108 status = "disabled"; 117 status = "disabled";
109 }; 118 };
119 mmc0: mmc@1c40000 {
120 compatible = "ti,da830-mmc";
121 reg = <0x40000 0x1000>;
122 interrupts = <16>;
123 status = "disabled";
124 };
110 }; 125 };
111 nand_cs3@62000000 { 126 nand_cs3@62000000 {
112 compatible = "ti,davinci-nand"; 127 compatible = "ti,davinci-nand";
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index 67f8670c4d6a..9bf49b3826ea 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -16,19 +16,13 @@
16 }; 16 };
17 17
18 timer@2000004 { 18 timer@2000004 {
19 compatible = "qcom,msm-gpt", "qcom,msm-timer"; 19 compatible = "qcom,scss-timer", "qcom,msm-timer";
20 interrupts = <1 1 0x301>; 20 interrupts = <1 0 0x301>,
21 reg = <0x02000004 0x10>; 21 <1 1 0x301>,
22 clock-frequency = <32768>; 22 <1 2 0x301>;
23 cpu-offset = <0x40000>; 23 reg = <0x02000000 0x100>;
24 }; 24 clock-frequency = <27000000>,
25 25 <32768>;
26 timer@2000024 {
27 compatible = "qcom,msm-dgt", "qcom,msm-timer";
28 interrupts = <1 0 0x301>;
29 reg = <0x02000024 0x10>,
30 <0x02000034 0x4>;
31 clock-frequency = <6750000>;
32 cpu-offset = <0x40000>; 26 cpu-offset = <0x40000>;
33 }; 27 };
34 28
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts
index c9b09a813a4b..2e4d87a125d6 100644
--- a/arch/arm/boot/dts/msm8960-cdp.dts
+++ b/arch/arm/boot/dts/msm8960-cdp.dts
@@ -15,20 +15,14 @@
15 < 0x02002000 0x1000 >; 15 < 0x02002000 0x1000 >;
16 }; 16 };
17 17
18 timer@200a004 { 18 timer@200a000 {
19 compatible = "qcom,msm-gpt", "qcom,msm-timer"; 19 compatible = "qcom,kpss-timer", "qcom,msm-timer";
20 interrupts = <1 2 0x301>; 20 interrupts = <1 1 0x301>,
21 reg = <0x0200a004 0x10>; 21 <1 2 0x301>,
22 clock-frequency = <32768>; 22 <1 3 0x301>;
23 cpu-offset = <0x80000>; 23 reg = <0x0200a000 0x100>;
24 }; 24 clock-frequency = <27000000>,
25 25 <32768>;
26 timer@200a024 {
27 compatible = "qcom,msm-dgt", "qcom,msm-timer";
28 interrupts = <1 1 0x301>;
29 reg = <0x0200a024 0x10>,
30 <0x0200a034 0x4>;
31 clock-frequency = <6750000>;
32 cpu-offset = <0x80000>; 26 cpu-offset = <0x80000>;
33 }; 27 };
34 28
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
new file mode 100644
index 000000000000..fe5c6f213271
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -0,0 +1,98 @@
1/*
2 * Device Tree Source for Renesas r8a7779
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Simon Horman
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 compatible = "renesas,r8a7779";
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 cpu@0 {
22 device_type = "cpu";
23 compatible = "arm,cortex-a9";
24 reg = <0>;
25 };
26 cpu@1 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a9";
29 reg = <1>;
30 };
31 cpu@2 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a9";
34 reg = <2>;
35 };
36 cpu@3 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a9";
39 reg = <3>;
40 };
41 };
42
43 gic: interrupt-controller@f0001000 {
44 compatible = "arm,cortex-a9-gic";
45 #interrupt-cells = <3>;
46 interrupt-controller;
47 reg = <0xf0001000 0x1000>,
48 <0xf0000100 0x100>;
49 };
50
51 i2c0: i2c@0xffc70000 {
52 #address-cells = <1>;
53 #size-cells = <0>;
54 compatible = "renesas,rmobile-iic";
55 reg = <0xffc70000 0x1000>;
56 interrupt-parent = <&gic>;
57 interrupts = <0 79 0x4>;
58 };
59
60 i2c1: i2c@0xffc71000 {
61 #address-cells = <1>;
62 #size-cells = <0>;
63 compatible = "renesas,rmobile-iic";
64 reg = <0xffc71000 0x1000>;
65 interrupt-parent = <&gic>;
66 interrupts = <0 82 0x4>;
67 };
68
69 i2c2: i2c@0xffc72000 {
70 #address-cells = <1>;
71 #size-cells = <0>;
72 compatible = "renesas,rmobile-iic";
73 reg = <0xffc72000 0x1000>;
74 interrupt-parent = <&gic>;
75 interrupts = <0 80 0x4>;
76 };
77
78 i2c3: i2c@0xffc73000 {
79 #address-cells = <1>;
80 #size-cells = <0>;
81 compatible = "renesas,rmobile-iic";
82 reg = <0xffc73000 0x1000>;
83 interrupt-parent = <&gic>;
84 interrupts = <0 81 0x4>;
85 };
86
87 thermal@ffc48000 {
88 compatible = "renesas,rcar-thermal";
89 reg = <0xffc48000 0x38>;
90 };
91
92 sata: sata@fc600000 {
93 compatible = "renesas,rcar-sata";
94 reg = <0xfc600000 0x2000>;
95 interrupt-parent = <&gic>;
96 interrupts = <0 100 0x4>;
97 };
98};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
new file mode 100644
index 000000000000..39b0458d365a
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -0,0 +1,1031 @@
1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC
4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 model = "Atmel SAMA5D3 family SoC";
15 compatible = "atmel,sama5d3", "atmel,sama5";
16 interrupt-parent = <&aic>;
17
18 aliases {
19 serial0 = &dbgu;
20 serial1 = &usart0;
21 serial2 = &usart1;
22 serial3 = &usart2;
23 serial4 = &usart3;
24 gpio0 = &pioA;
25 gpio1 = &pioB;
26 gpio2 = &pioC;
27 gpio3 = &pioD;
28 gpio4 = &pioE;
29 tcb0 = &tcb0;
30 tcb1 = &tcb1;
31 i2c0 = &i2c0;
32 i2c1 = &i2c1;
33 i2c2 = &i2c2;
34 ssc0 = &ssc0;
35 ssc1 = &ssc1;
36 };
37 cpus {
38 cpu@0 {
39 compatible = "arm,cortex-a5";
40 };
41 };
42
43 memory {
44 reg = <0x20000000 0x8000000>;
45 };
46
47 ahb {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 ranges;
52
53 apb {
54 compatible = "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
58
59 mmc0: mmc@f0000000 {
60 compatible = "atmel,hsmci";
61 reg = <0xf0000000 0x600>;
62 interrupts = <21 4 0>;
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
65 status = "disabled";
66 #address-cells = <1>;
67 #size-cells = <0>;
68 };
69
70 spi0: spi@f0004000 {
71 #address-cells = <1>;
72 #size-cells = <0>;
73 compatible = "atmel,at91sam9x5-spi";
74 reg = <0xf0004000 0x100>;
75 interrupts = <24 4 3>;
76 cs-gpios = <&pioD 13 0
77 &pioD 14 0 /* conflicts with SCK0 and CANRX0 */
78 &pioD 15 0 /* conflicts with CTS0 and CANTX0 */
79 &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */
80 >;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_spi0>;
83 status = "disabled";
84 };
85
86 ssc0: ssc@f0008000 {
87 compatible = "atmel,at91sam9g45-ssc";
88 reg = <0xf0008000 0x4000>;
89 interrupts = <38 4 4>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
92 status = "disabled";
93 };
94
95 can0: can@f000c000 {
96 compatible = "atmel,at91sam9x5-can";
97 reg = <0xf000c000 0x300>;
98 interrupts = <40 4 3>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_can0_rx_tx>;
101 status = "disabled";
102 };
103
104 tcb0: timer@f0010000 {
105 compatible = "atmel,at91sam9x5-tcb";
106 reg = <0xf0010000 0x100>;
107 interrupts = <26 4 0>;
108 };
109
110 i2c0: i2c@f0014000 {
111 compatible = "atmel,at91sam9x5-i2c";
112 reg = <0xf0014000 0x4000>;
113 interrupts = <18 4 6>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_i2c0>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 status = "disabled";
119 };
120
121 i2c1: i2c@f0018000 {
122 compatible = "atmel,at91sam9x5-i2c";
123 reg = <0xf0018000 0x4000>;
124 interrupts = <19 4 6>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_i2c1>;
127 #address-cells = <1>;
128 #size-cells = <0>;
129 status = "disabled";
130 };
131
132 usart0: serial@f001c000 {
133 compatible = "atmel,at91sam9260-usart";
134 reg = <0xf001c000 0x100>;
135 interrupts = <12 4 5>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_usart0>;
138 status = "disabled";
139 };
140
141 usart1: serial@f0020000 {
142 compatible = "atmel,at91sam9260-usart";
143 reg = <0xf0020000 0x100>;
144 interrupts = <13 4 5>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_usart1>;
147 status = "disabled";
148 };
149
150 macb0: ethernet@f0028000 {
151 compatible = "cnds,pc302-gem", "cdns,gem";
152 reg = <0xf0028000 0x100>;
153 interrupts = <34 4 3>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
156 status = "disabled";
157 };
158
159 isi: isi@f0034000 {
160 compatible = "atmel,at91sam9g45-isi";
161 reg = <0xf0034000 0x4000>;
162 interrupts = <37 4 5>;
163 status = "disabled";
164 };
165
166 mmc1: mmc@f8000000 {
167 compatible = "atmel,hsmci";
168 reg = <0xf8000000 0x600>;
169 interrupts = <22 4 0>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
172 status = "disabled";
173 #address-cells = <1>;
174 #size-cells = <0>;
175 };
176
177 mmc2: mmc@f8004000 {
178 compatible = "atmel,hsmci";
179 reg = <0xf8004000 0x600>;
180 interrupts = <23 4 0>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
183 status = "disabled";
184 #address-cells = <1>;
185 #size-cells = <0>;
186 };
187
188 spi1: spi@f8008000 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "atmel,at91sam9x5-spi";
192 reg = <0xf8008000 0x100>;
193 interrupts = <25 4 3>;
194 cs-gpios = <&pioC 25 0
195 &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */
196 &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */
197 &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */
198 >;
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_spi1>;
201 status = "disabled";
202 };
203
204 ssc1: ssc@f800c000 {
205 compatible = "atmel,at91sam9g45-ssc";
206 reg = <0xf800c000 0x4000>;
207 interrupts = <39 4 4>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
210 status = "disabled";
211 };
212
213 can1: can@f8010000 {
214 compatible = "atmel,at91sam9x5-can";
215 reg = <0xf8010000 0x300>;
216 interrupts = <41 4 3>;
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_can1_rx_tx>;
219 };
220
221 tcb1: timer@f8014000 {
222 compatible = "atmel,at91sam9x5-tcb";
223 reg = <0xf8014000 0x100>;
224 interrupts = <27 4 0>;
225 };
226
227 adc0: adc@f8018000 {
228 compatible = "atmel,at91sam9260-adc";
229 reg = <0xf8018000 0x100>;
230 interrupts = <29 4 5>;
231 pinctrl-names = "default";
232 pinctrl-0 = <
233 &pinctrl_adc0_adtrg
234 &pinctrl_adc0_ad0
235 &pinctrl_adc0_ad1
236 &pinctrl_adc0_ad2
237 &pinctrl_adc0_ad3
238 &pinctrl_adc0_ad4
239 &pinctrl_adc0_ad5
240 &pinctrl_adc0_ad6
241 &pinctrl_adc0_ad7
242 &pinctrl_adc0_ad8
243 &pinctrl_adc0_ad9
244 &pinctrl_adc0_ad10
245 &pinctrl_adc0_ad11
246 >;
247 atmel,adc-channel-base = <0x50>;
248 atmel,adc-channels-used = <0xfff>;
249 atmel,adc-drdy-mask = <0x1000000>;
250 atmel,adc-num-channels = <12>;
251 atmel,adc-startup-time = <40>;
252 atmel,adc-status-register = <0x30>;
253 atmel,adc-trigger-register = <0xc0>;
254 atmel,adc-use-external;
255 atmel,adc-vref = <3000>;
256 atmel,adc-res = <10 12>;
257 atmel,adc-res-names = "lowres", "highres";
258 status = "disabled";
259
260 trigger@0 {
261 trigger-name = "external-rising";
262 trigger-value = <0x1>;
263 trigger-external;
264 };
265 trigger@1 {
266 trigger-name = "external-falling";
267 trigger-value = <0x2>;
268 trigger-external;
269 };
270 trigger@2 {
271 trigger-name = "external-any";
272 trigger-value = <0x3>;
273 trigger-external;
274 };
275 trigger@3 {
276 trigger-name = "continuous";
277 trigger-value = <0x6>;
278 };
279 };
280
281 tsadcc: tsadcc@f8018000 {
282 compatible = "atmel,at91sam9x5-tsadcc";
283 reg = <0xf8018000 0x4000>;
284 interrupts = <29 4 5>;
285 atmel,tsadcc_clock = <300000>;
286 atmel,filtering_average = <0x03>;
287 atmel,pendet_debounce = <0x08>;
288 atmel,pendet_sensitivity = <0x02>;
289 atmel,ts_sample_hold_time = <0x0a>;
290 status = "disabled";
291 };
292
293 i2c2: i2c@f801c000 {
294 compatible = "atmel,at91sam9x5-i2c";
295 reg = <0xf801c000 0x4000>;
296 interrupts = <20 4 6>;
297 #address-cells = <1>;
298 #size-cells = <0>;
299 status = "disabled";
300 };
301
302 usart2: serial@f8020000 {
303 compatible = "atmel,at91sam9260-usart";
304 reg = <0xf8020000 0x100>;
305 interrupts = <14 4 5>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_usart2>;
308 status = "disabled";
309 };
310
311 usart3: serial@f8024000 {
312 compatible = "atmel,at91sam9260-usart";
313 reg = <0xf8024000 0x100>;
314 interrupts = <15 4 5>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_usart3>;
317 status = "disabled";
318 };
319
320 macb1: ethernet@f802c000 {
321 compatible = "cdns,at32ap7000-macb", "cdns,macb";
322 reg = <0xf802c000 0x100>;
323 interrupts = <35 4 3>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_macb1_rmii>;
326 status = "disabled";
327 };
328
329 sha@f8034000 {
330 compatible = "atmel,sam9g46-sha";
331 reg = <0xf8034000 0x100>;
332 interrupts = <42 4 0>;
333 };
334
335 aes@f8038000 {
336 compatible = "atmel,sam9g46-aes";
337 reg = <0xf8038000 0x100>;
338 interrupts = <43 4 0>;
339 };
340
341 tdes@f803c000 {
342 compatible = "atmel,sam9g46-tdes";
343 reg = <0xf803c000 0x100>;
344 interrupts = <44 4 0>;
345 };
346
347 dma0: dma-controller@ffffe600 {
348 compatible = "atmel,at91sam9g45-dma";
349 reg = <0xffffe600 0x200>;
350 interrupts = <30 4 0>;
351 #dma-cells = <1>;
352 };
353
354 dma1: dma-controller@ffffe800 {
355 compatible = "atmel,at91sam9g45-dma";
356 reg = <0xffffe800 0x200>;
357 interrupts = <31 4 0>;
358 #dma-cells = <1>;
359 };
360
361 ramc0: ramc@ffffea00 {
362 compatible = "atmel,at91sam9g45-ddramc";
363 reg = <0xffffea00 0x200>;
364 };
365
366 dbgu: serial@ffffee00 {
367 compatible = "atmel,at91sam9260-usart";
368 reg = <0xffffee00 0x200>;
369 interrupts = <2 4 7>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_dbgu>;
372 status = "disabled";
373 };
374
375 aic: interrupt-controller@fffff000 {
376 #interrupt-cells = <3>;
377 compatible = "atmel,sama5d3-aic";
378 interrupt-controller;
379 reg = <0xfffff000 0x200>;
380 atmel,external-irqs = <47>;
381 };
382
383 pinctrl@fffff200 {
384 #address-cells = <1>;
385 #size-cells = <1>;
386 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
387 ranges = <0xfffff200 0xfffff200 0xa00>;
388 atmel,mux-mask = <
389 /* A B C */
390 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
391 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
392 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
393 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
394 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
395 >;
396
397 /* shared pinctrl settings */
398 adc0 {
399 pinctrl_adc0_adtrg: adc0_adtrg {
400 atmel,pins =
401 <3 19 0x1 0x0>; /* PD19 periph A ADTRG */
402 };
403 pinctrl_adc0_ad0: adc0_ad0 {
404 atmel,pins =
405 <3 20 0x1 0x0>; /* PD20 periph A AD0 */
406 };
407 pinctrl_adc0_ad1: adc0_ad1 {
408 atmel,pins =
409 <3 21 0x1 0x0>; /* PD21 periph A AD1 */
410 };
411 pinctrl_adc0_ad2: adc0_ad2 {
412 atmel,pins =
413 <3 22 0x1 0x0>; /* PD22 periph A AD2 */
414 };
415 pinctrl_adc0_ad3: adc0_ad3 {
416 atmel,pins =
417 <3 23 0x1 0x0>; /* PD23 periph A AD3 */
418 };
419 pinctrl_adc0_ad4: adc0_ad4 {
420 atmel,pins =
421 <3 24 0x1 0x0>; /* PD24 periph A AD4 */
422 };
423 pinctrl_adc0_ad5: adc0_ad5 {
424 atmel,pins =
425 <3 25 0x1 0x0>; /* PD25 periph A AD5 */
426 };
427 pinctrl_adc0_ad6: adc0_ad6 {
428 atmel,pins =
429 <3 26 0x1 0x0>; /* PD26 periph A AD6 */
430 };
431 pinctrl_adc0_ad7: adc0_ad7 {
432 atmel,pins =
433 <3 27 0x1 0x0>; /* PD27 periph A AD7 */
434 };
435 pinctrl_adc0_ad8: adc0_ad8 {
436 atmel,pins =
437 <3 28 0x1 0x0>; /* PD28 periph A AD8 */
438 };
439 pinctrl_adc0_ad9: adc0_ad9 {
440 atmel,pins =
441 <3 29 0x1 0x0>; /* PD29 periph A AD9 */
442 };
443 pinctrl_adc0_ad10: adc0_ad10 {
444 atmel,pins =
445 <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */
446 };
447 pinctrl_adc0_ad11: adc0_ad11 {
448 atmel,pins =
449 <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */
450 };
451 };
452
453 can0 {
454 pinctrl_can0_rx_tx: can0_rx_tx {
455 atmel,pins =
456 <3 14 0x3 0x0 /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
457 3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
458 };
459 };
460
461 can1 {
462 pinctrl_can1_rx_tx: can1_rx_tx {
463 atmel,pins =
464 <1 14 0x2 0x0 /* PB14 periph B RX, conflicts with GCRS */
465 1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */
466 };
467 };
468
469 dbgu {
470 pinctrl_dbgu: dbgu-0 {
471 atmel,pins =
472 <1 30 0x1 0x0 /* PB30 periph A */
473 1 31 0x1 0x1>; /* PB31 periph A with pullup */
474 };
475 };
476
477 i2c0 {
478 pinctrl_i2c0: i2c0-0 {
479 atmel,pins =
480 <0 30 0x1 0x0 /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
481 0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
482 };
483 };
484
485 i2c1 {
486 pinctrl_i2c1: i2c1-0 {
487 atmel,pins =
488 <2 26 0x2 0x0 /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
489 2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
490 };
491 };
492
493 isi {
494 pinctrl_isi: isi-0 {
495 atmel,pins =
496 <0 16 0x3 0x0 /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
497 0 17 0x3 0x0 /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
498 0 18 0x3 0x0 /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
499 0 19 0x3 0x0 /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
500 0 20 0x3 0x0 /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
501 0 21 0x3 0x0 /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
502 0 22 0x3 0x0 /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
503 0 23 0x3 0x0 /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
504 2 30 0x3 0x0 /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
505 0 31 0x3 0x0 /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
506 0 30 0x3 0x0 /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
507 2 29 0x3 0x0 /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
508 2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
509 };
510 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
511 atmel,pins =
512 <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */
513 };
514 };
515
516 lcd {
517 pinctrl_lcd: lcd-0 {
518 atmel,pins =
519 <0 24 0x1 0x0 /* PA24 periph A LCDPWM */
520 0 26 0x1 0x0 /* PA26 periph A LCDVSYNC */
521 0 27 0x1 0x0 /* PA27 periph A LCDHSYNC */
522 0 25 0x1 0x0 /* PA25 periph A LCDDISP */
523 0 29 0x1 0x0 /* PA29 periph A LCDDEN */
524 0 28 0x1 0x0 /* PA28 periph A LCDPCK */
525 0 0 0x1 0x0 /* PA0 periph A LCDD0 pin */
526 0 1 0x1 0x0 /* PA1 periph A LCDD1 pin */
527 0 2 0x1 0x0 /* PA2 periph A LCDD2 pin */
528 0 3 0x1 0x0 /* PA3 periph A LCDD3 pin */
529 0 4 0x1 0x0 /* PA4 periph A LCDD4 pin */
530 0 5 0x1 0x0 /* PA5 periph A LCDD5 pin */
531 0 6 0x1 0x0 /* PA6 periph A LCDD6 pin */
532 0 7 0x1 0x0 /* PA7 periph A LCDD7 pin */
533 0 8 0x1 0x0 /* PA8 periph A LCDD8 pin */
534 0 9 0x1 0x0 /* PA9 periph A LCDD9 pin */
535 0 10 0x1 0x0 /* PA10 periph A LCDD10 pin */
536 0 11 0x1 0x0 /* PA11 periph A LCDD11 pin */
537 0 12 0x1 0x0 /* PA12 periph A LCDD12 pin */
538 0 13 0x1 0x0 /* PA13 periph A LCDD13 pin */
539 0 14 0x1 0x0 /* PA14 periph A LCDD14 pin */
540 0 15 0x1 0x0 /* PA15 periph A LCDD15 pin */
541 2 14 0x3 0x0 /* PC14 periph C LCDD16 pin */
542 2 13 0x3 0x0 /* PC13 periph C LCDD17 pin */
543 2 12 0x3 0x0 /* PC12 periph C LCDD18 pin */
544 2 11 0x3 0x0 /* PC11 periph C LCDD19 pin */
545 2 10 0x3 0x0 /* PC10 periph C LCDD20 pin */
546 2 15 0x3 0x0 /* PC15 periph C LCDD21 pin */
547 4 27 0x3 0x0 /* PE27 periph C LCDD22 pin */
548 4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */
549 };
550 };
551
552 macb0 {
553 pinctrl_macb0_data_rgmii: macb0_data_rgmii {
554 atmel,pins =
555 <1 0 0x1 0x0 /* PB0 periph A GTX0, conflicts with PWMH0 */
556 1 1 0x1 0x0 /* PB1 periph A GTX1, conflicts with PWML0 */
557 1 2 0x1 0x0 /* PB2 periph A GTX2, conflicts with TK1 */
558 1 3 0x1 0x0 /* PB3 periph A GTX3, conflicts with TF1 */
559 1 4 0x1 0x0 /* PB4 periph A GRX0, conflicts with PWMH1 */
560 1 5 0x1 0x0 /* PB5 periph A GRX1, conflicts with PWML1 */
561 1 6 0x1 0x0 /* PB6 periph A GRX2, conflicts with TD1 */
562 1 7 0x1 0x0>; /* PB7 periph A GRX3, conflicts with RK1 */
563 };
564 pinctrl_macb0_data_gmii: macb0_data_gmii {
565 atmel,pins =
566 <1 19 0x2 0x0 /* PB19 periph B GTX4, conflicts with MCI1_CDA */
567 1 20 0x2 0x0 /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
568 1 21 0x2 0x0 /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
569 1 22 0x2 0x0 /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
570 1 23 0x2 0x0 /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
571 1 24 0x2 0x0 /* PB24 periph B GRX5, conflicts with MCI1_CK */
572 1 25 0x2 0x0 /* PB25 periph B GRX6, conflicts with SCK1 */
573 1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */
574 };
575 pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
576 atmel,pins =
577 <1 8 0x1 0x0 /* PB8 periph A GTXCK, conflicts with PWMH2 */
578 1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */
579 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */
580 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */
581 1 16 0x1 0x0 /* PB16 periph A GMDC */
582 1 17 0x1 0x0 /* PB17 periph A GMDIO */
583 1 18 0x1 0x0>; /* PB18 periph A G125CK */
584 };
585 pinctrl_macb0_signal_gmii: macb0_signal_gmii {
586 atmel,pins =
587 <1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */
588 1 10 0x1 0x0 /* PB10 periph A GTXER, conflicts with RF1 */
589 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */
590 1 12 0x1 0x0 /* PB12 periph A GRXDV, conflicts with PWMH3 */
591 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */
592 1 14 0x1 0x0 /* PB14 periph A GCRS, conflicts with CANRX1 */
593 1 15 0x1 0x0 /* PB15 periph A GCOL, conflicts with CANTX1 */
594 1 16 0x1 0x0 /* PB16 periph A GMDC */
595 1 17 0x1 0x0 /* PB17 periph A GMDIO */
596 1 27 0x2 0x0>; /* PB27 periph B G125CKO */
597 };
598
599 };
600
601 macb1 {
602 pinctrl_macb1_rmii: macb1_rmii-0 {
603 atmel,pins =
604 <2 0 0x1 0x0 /* PC0 periph A ETX0, conflicts with TIOA3 */
605 2 1 0x1 0x0 /* PC1 periph A ETX1, conflicts with TIOB3 */
606 2 2 0x1 0x0 /* PC2 periph A ERX0, conflicts with TCLK3 */
607 2 3 0x1 0x0 /* PC3 periph A ERX1, conflicts with TIOA4 */
608 2 4 0x1 0x0 /* PC4 periph A ETXEN, conflicts with TIOB4 */
609 2 5 0x1 0x0 /* PC5 periph A ECRSDV,conflicts with TCLK4 */
610 2 6 0x1 0x0 /* PC6 periph A ERXER, conflicts with TIOA5 */
611 2 7 0x1 0x0 /* PC7 periph A EREFCK, conflicts with TIOB5 */
612 2 8 0x1 0x0 /* PC8 periph A EMDC, conflicts with TCLK5 */
613 2 9 0x1 0x0>; /* PC9 periph A EMDIO */
614 };
615 };
616
617 mmc0 {
618 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
619 atmel,pins =
620 <3 9 0x1 0x0 /* PD9 periph A MCI0_CK */
621 3 0 0x1 0x1 /* PD0 periph A MCI0_CDA with pullup */
622 3 1 0x1 0x1>; /* PD1 periph A MCI0_DA0 with pullup */
623 };
624 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
625 atmel,pins =
626 <3 2 0x1 0x1 /* PD2 periph A MCI0_DA1 with pullup */
627 3 3 0x1 0x1 /* PD3 periph A MCI0_DA2 with pullup */
628 3 4 0x1 0x1>; /* PD4 periph A MCI0_DA3 with pullup */
629 };
630 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
631 atmel,pins =
632 <3 5 0x1 0x1 /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
633 3 6 0x1 0x1 /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
634 3 7 0x1 0x1 /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
635 3 8 0x1 0x1>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
636 };
637 };
638
639 mmc1 {
640 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
641 atmel,pins =
642 <1 24 0x1 0x0 /* PB24 periph A MCI1_CK, conflicts with GRX5 */
643 1 19 0x1 0x1 /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
644 1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
645 };
646 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
647 atmel,pins =
648 <1 21 0x1 0x1 /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
649 1 22 0x1 0x1 /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
650 1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
651 };
652 };
653
654 mmc2 {
655 pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
656 atmel,pins =
657 <2 15 0x1 0x0 /* PC15 periph A MCI2_CK, conflicts with PCK2 */
658 2 10 0x1 0x1 /* PC10 periph A MCI2_CDA with pullup */
659 2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */
660 };
661 pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
662 atmel,pins =
663 <2 12 0x1 0x0 /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
664 2 13 0x1 0x0 /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
665 2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
666 };
667 };
668
669 nand0 {
670 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
671 atmel,pins =
672 <4 21 0x1 0x1 /* PE21 periph A with pullup */
673 4 22 0x1 0x1>; /* PE22 periph A with pullup */
674 };
675 };
676
677 pioA: gpio@fffff200 {
678 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
679 reg = <0xfffff200 0x100>;
680 interrupts = <6 4 1>;
681 #gpio-cells = <2>;
682 gpio-controller;
683 interrupt-controller;
684 #interrupt-cells = <2>;
685 };
686
687 pioB: gpio@fffff400 {
688 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
689 reg = <0xfffff400 0x100>;
690 interrupts = <7 4 1>;
691 #gpio-cells = <2>;
692 gpio-controller;
693 interrupt-controller;
694 #interrupt-cells = <2>;
695 };
696
697 pioC: gpio@fffff600 {
698 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
699 reg = <0xfffff600 0x100>;
700 interrupts = <8 4 1>;
701 #gpio-cells = <2>;
702 gpio-controller;
703 interrupt-controller;
704 #interrupt-cells = <2>;
705 };
706
707 pioD: gpio@fffff800 {
708 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
709 reg = <0xfffff800 0x100>;
710 interrupts = <9 4 1>;
711 #gpio-cells = <2>;
712 gpio-controller;
713 interrupt-controller;
714 #interrupt-cells = <2>;
715 };
716
717 pioE: gpio@fffffa00 {
718 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
719 reg = <0xfffffa00 0x100>;
720 interrupts = <10 4 1>;
721 #gpio-cells = <2>;
722 gpio-controller;
723 interrupt-controller;
724 #interrupt-cells = <2>;
725 };
726
727 spi0 {
728 pinctrl_spi0: spi0-0 {
729 atmel,pins =
730 <3 10 0x1 0x0 /* PD10 periph A SPI0_MISO pin */
731 3 11 0x1 0x0 /* PD11 periph A SPI0_MOSI pin */
732 3 12 0x1 0x0 /* PD12 periph A SPI0_SPCK pin */
733 3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */
734 };
735 };
736
737 spi1 {
738 pinctrl_spi1: spi1-0 {
739 atmel,pins =
740 <2 22 0x1 0x0 /* PC22 periph A SPI1_MISO pin */
741 2 23 0x1 0x0 /* PC23 periph A SPI1_MOSI pin */
742 2 24 0x1 0x0 /* PC24 periph A SPI1_SPCK pin */
743 2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */
744 };
745 };
746
747 ssc0 {
748 pinctrl_ssc0_tx: ssc0_tx {
749 atmel,pins =
750 <2 16 0x1 0x0 /* PC16 periph A TK0 */
751 2 17 0x1 0x0 /* PC17 periph A TF0 */
752 2 18 0x1 0x0>; /* PC18 periph A TD0 */
753 };
754
755 pinctrl_ssc0_rx: ssc0_rx {
756 atmel,pins =
757 <2 19 0x1 0x0 /* PC19 periph A RK0 */
758 2 20 0x1 0x0 /* PC20 periph A RF0 */
759 2 21 0x1 0x0>; /* PC21 periph A RD0 */
760 };
761 };
762
763 ssc1 {
764 pinctrl_ssc1_tx: ssc1_tx {
765 atmel,pins =
766 <1 2 0x2 0x0 /* PB2 periph B TK1, conflicts with GTX2 */
767 1 3 0x2 0x0 /* PB3 periph B TF1, conflicts with GTX3 */
768 1 6 0x2 0x0>; /* PB6 periph B TD1, conflicts with TD1 */
769 };
770
771 pinctrl_ssc1_rx: ssc1_rx {
772 atmel,pins =
773 <1 7 0x2 0x0 /* PB7 periph B RK1, conflicts with EREFCK */
774 1 10 0x2 0x0 /* PB10 periph B RF1, conflicts with GTXER */
775 1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */
776 };
777 };
778
779 uart0 {
780 pinctrl_uart0: uart0-0 {
781 atmel,pins =
782 <2 29 0x1 0x0 /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
783 2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
784 };
785 };
786
787 uart1 {
788 pinctrl_uart1: uart1-0 {
789 atmel,pins =
790 <0 30 0x2 0x0 /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
791 0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
792 };
793 };
794
795 usart0 {
796 pinctrl_usart0: usart0-0 {
797 atmel,pins =
798 <3 17 0x1 0x0 /* PD17 periph A */
799 3 18 0x1 0x1>; /* PD18 periph A with pullup */
800 };
801
802 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
803 atmel,pins =
804 <3 15 0x1 0x0 /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
805 3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
806 };
807 };
808
809 usart1 {
810 pinctrl_usart1: usart1-0 {
811 atmel,pins =
812 <1 28 0x1 0x0 /* PB28 periph A */
813 1 29 0x1 0x1>; /* PB29 periph A with pullup */
814 };
815
816 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
817 atmel,pins =
818 <1 26 0x1 0x0 /* PB26 periph A, conflicts with GRX7 */
819 1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */
820 };
821 };
822
823 usart2 {
824 pinctrl_usart2: usart2-0 {
825 atmel,pins =
826 <4 25 0x2 0x0 /* PE25 periph B, conflicts with A25 */
827 4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */
828 };
829
830 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
831 atmel,pins =
832 <4 23 0x2 0x0 /* PE23 periph B, conflicts with A23 */
833 4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */
834 };
835 };
836
837 usart3 {
838 pinctrl_usart3: usart3-0 {
839 atmel,pins =
840 <4 18 0x2 0x0 /* PE18 periph B, conflicts with A18 */
841 4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */
842 };
843
844 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
845 atmel,pins =
846 <4 16 0x2 0x0 /* PE16 periph B, conflicts with A16 */
847 4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */
848 };
849 };
850 };
851
852 pmc: pmc@fffffc00 {
853 compatible = "atmel,at91rm9200-pmc";
854 reg = <0xfffffc00 0x120>;
855 };
856
857 rstc@fffffe00 {
858 compatible = "atmel,at91sam9g45-rstc";
859 reg = <0xfffffe00 0x10>;
860 };
861
862 pit: timer@fffffe30 {
863 compatible = "atmel,at91sam9260-pit";
864 reg = <0xfffffe30 0xf>;
865 interrupts = <3 4 5>;
866 };
867
868 watchdog@fffffe40 {
869 compatible = "atmel,at91sam9260-wdt";
870 reg = <0xfffffe40 0x10>;
871 status = "disabled";
872 };
873
874 rtc@fffffeb0 {
875 compatible = "atmel,at91rm9200-rtc";
876 reg = <0xfffffeb0 0x30>;
877 interrupts = <1 4 7>;
878 };
879 };
880
881 usb0: gadget@00500000 {
882 #address-cells = <1>;
883 #size-cells = <0>;
884 compatible = "atmel,at91sam9rl-udc";
885 reg = <0x00500000 0x100000
886 0xf8030000 0x4000>;
887 interrupts = <33 4 2>;
888 status = "disabled";
889
890 ep0 {
891 reg = <0>;
892 atmel,fifo-size = <64>;
893 atmel,nb-banks = <1>;
894 };
895
896 ep1 {
897 reg = <1>;
898 atmel,fifo-size = <1024>;
899 atmel,nb-banks = <3>;
900 atmel,can-dma;
901 atmel,can-isoc;
902 };
903
904 ep2 {
905 reg = <2>;
906 atmel,fifo-size = <1024>;
907 atmel,nb-banks = <3>;
908 atmel,can-dma;
909 atmel,can-isoc;
910 };
911
912 ep3 {
913 reg = <3>;
914 atmel,fifo-size = <1024>;
915 atmel,nb-banks = <2>;
916 atmel,can-dma;
917 };
918
919 ep4 {
920 reg = <4>;
921 atmel,fifo-size = <1024>;
922 atmel,nb-banks = <2>;
923 atmel,can-dma;
924 };
925
926 ep5 {
927 reg = <5>;
928 atmel,fifo-size = <1024>;
929 atmel,nb-banks = <2>;
930 atmel,can-dma;
931 };
932
933 ep6 {
934 reg = <6>;
935 atmel,fifo-size = <1024>;
936 atmel,nb-banks = <2>;
937 atmel,can-dma;
938 };
939
940 ep7 {
941 reg = <7>;
942 atmel,fifo-size = <1024>;
943 atmel,nb-banks = <2>;
944 atmel,can-dma;
945 };
946
947 ep8 {
948 reg = <8>;
949 atmel,fifo-size = <1024>;
950 atmel,nb-banks = <2>;
951 };
952
953 ep9 {
954 reg = <9>;
955 atmel,fifo-size = <1024>;
956 atmel,nb-banks = <2>;
957 };
958
959 ep10 {
960 reg = <10>;
961 atmel,fifo-size = <1024>;
962 atmel,nb-banks = <2>;
963 };
964
965 ep11 {
966 reg = <11>;
967 atmel,fifo-size = <1024>;
968 atmel,nb-banks = <2>;
969 };
970
971 ep12 {
972 reg = <12>;
973 atmel,fifo-size = <1024>;
974 atmel,nb-banks = <2>;
975 };
976
977 ep13 {
978 reg = <13>;
979 atmel,fifo-size = <1024>;
980 atmel,nb-banks = <2>;
981 };
982
983 ep14 {
984 reg = <14>;
985 atmel,fifo-size = <1024>;
986 atmel,nb-banks = <2>;
987 };
988
989 ep15 {
990 reg = <15>;
991 atmel,fifo-size = <1024>;
992 atmel,nb-banks = <2>;
993 };
994 };
995
996 usb1: ohci@00600000 {
997 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
998 reg = <0x00600000 0x100000>;
999 interrupts = <32 4 2>;
1000 status = "disabled";
1001 };
1002
1003 usb2: ehci@00700000 {
1004 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1005 reg = <0x00700000 0x100000>;
1006 interrupts = <32 4 2>;
1007 status = "disabled";
1008 };
1009
1010 nand0: nand@60000000 {
1011 compatible = "atmel,at91rm9200-nand";
1012 #address-cells = <1>;
1013 #size-cells = <1>;
1014 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1015 0xffffc070 0x00000490 /* SMC PMECC regs */
1016 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
1017 0x00100000 0x00100000 /* ROM code */
1018 0x70000000 0x10000000 /* NFC Command Registers */
1019 0xffffc000 0x00000070 /* NFC HSMC regs */
1020 0x00200000 0x00100000 /* NFC SRAM banks */
1021 >;
1022 interrupts = <5 4 6>;
1023 atmel,nand-addr-offset = <21>;
1024 atmel,nand-cmd-offset = <22>;
1025 pinctrl-names = "default";
1026 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
1027 atmel,pmecc-lookup-table-offset = <0x10000 0x18000>;
1028 status = "disabled";
1029 };
1030 };
1031};
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts
new file mode 100644
index 000000000000..fa5d216f1db7
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d31ek.dts
@@ -0,0 +1,51 @@
1/*
2 * sama5d31ek.dts - Device Tree file for SAMA5D31-EK board
3 *
4 * Copyright (C) 2013 Atmel,
5 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "sama5d3xmb.dtsi"
11/include/ "sama5d3xdm.dtsi"
12
13/ {
14 model = "Atmel SAMA5D31-EK";
15 compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
16
17 ahb {
18 apb {
19 spi0: spi@f0004000 {
20 status = "okay";
21 };
22
23 ssc0: ssc@f0008000 {
24 status = "okay";
25 };
26
27 i2c0: i2c@f0014000 {
28 status = "okay";
29 };
30
31 i2c1: i2c@f0018000 {
32 status = "okay";
33 };
34
35 macb1: ethernet@f802c000 {
36 status = "okay";
37 };
38 };
39 };
40
41 leds {
42 d3 {
43 label = "d3";
44 gpios = <&pioE 24 0>;
45 };
46 };
47
48 sound {
49 status = "okay";
50 };
51};
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts
new file mode 100644
index 000000000000..c38c9433d7a5
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d33ek.dts
@@ -0,0 +1,44 @@
1/*
2 * sama5d33ek.dts - Device Tree file for SAMA5D33-EK board
3 *
4 * Copyright (C) 2013 Atmel,
5 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "sama5d3xmb.dtsi"
11/include/ "sama5d3xdm.dtsi"
12
13/ {
14 model = "Atmel SAMA5D33-EK";
15 compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
16
17 ahb {
18 apb {
19 spi0: spi@f0004000 {
20 status = "okay";
21 };
22
23 ssc0: ssc@f0008000 {
24 status = "okay";
25 };
26
27 i2c0: i2c@f0014000 {
28 status = "okay";
29 };
30
31 i2c1: i2c@f0018000 {
32 status = "okay";
33 };
34
35 macb0: ethernet@f0028000 {
36 status = "okay";
37 };
38 };
39 };
40
41 sound {
42 status = "okay";
43 };
44};
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
new file mode 100644
index 000000000000..d2739f8d7ae9
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -0,0 +1,61 @@
1/*
2 * sama5d34ek.dts - Device Tree file for SAMA5D34-EK board
3 *
4 * Copyright (C) 2013 Atmel,
5 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "sama5d3xmb.dtsi"
11/include/ "sama5d3xdm.dtsi"
12
13/ {
14 model = "Atmel SAMA5D34-EK";
15 compatible = "atmel,sama5d34ek", "atmel,sama5ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
16
17 ahb {
18 apb {
19 spi0: spi@f0004000 {
20 status = "okay";
21 };
22
23 ssc0: ssc@f0008000 {
24 status = "okay";
25 };
26
27 can0: can@f000c000 {
28 status = "okay";
29 };
30
31 i2c0: i2c@f0014000 {
32 status = "okay";
33 };
34
35 i2c1: i2c@f0018000 {
36 status = "okay";
37
38 24c256@50 {
39 compatible = "24c256";
40 reg = <0x50>;
41 pagesize = <64>;
42 };
43 };
44
45 macb0: ethernet@f0028000 {
46 status = "okay";
47 };
48 };
49 };
50
51 leds {
52 d3 {
53 label = "d3";
54 gpios = <&pioE 24 0>;
55 };
56 };
57
58 sound {
59 status = "okay";
60 };
61};
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts
new file mode 100644
index 000000000000..a488fc4e9777
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d35ek.dts
@@ -0,0 +1,56 @@
1/*
2 * sama5d35ek.dts - Device Tree file for SAMA5D35-EK board
3 *
4 * Copyright (C) 2013 Atmel,
5 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "sama5d3xmb.dtsi"
11
12/ {
13 model = "Atmel SAMA5D35-EK";
14 compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
15
16 ahb {
17 apb {
18 spi0: spi@f0004000 {
19 status = "okay";
20 };
21
22 can0: can@f000c000 {
23 status = "okay";
24 };
25
26 i2c1: i2c@f0018000 {
27 status = "okay";
28 };
29
30 macb0: ethernet@f0028000 {
31 status = "okay";
32 };
33
34 isi: isi@f0034000 {
35 status = "okay";
36 };
37
38 macb1: ethernet@f802c000 {
39 status = "okay";
40 };
41 };
42 };
43
44 gpio_keys {
45 compatible = "gpio-keys";
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 pb_user1 {
50 label = "pb_user1";
51 gpios = <&pioE 27 0>;
52 linux,code = <0x100>;
53 gpio-key,wakeup;
54 };
55 };
56};
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
new file mode 100644
index 000000000000..1f8ed404626c
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -0,0 +1,91 @@
1/*
2 * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module
3 *
4 * Copyright (C) 2013 Atmel,
5 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/include/ "sama5d3.dtsi"
10
11/ {
12 compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5";
13
14 chosen {
15 bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs";
16 };
17
18 memory {
19 reg = <0x20000000 0x20000000>;
20 };
21
22 clocks {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges;
26
27 main_clock: clock@0 {
28 compatible = "atmel,osc", "fixed-clock";
29 clock-frequency = <12000000>;
30 };
31 };
32
33 ahb {
34 apb {
35 macb0: ethernet@f0028000 {
36 phy-mode = "rgmii";
37 };
38 };
39
40 nand0: nand@60000000 {
41 nand-bus-width = <8>;
42 nand-ecc-mode = "hw";
43 atmel,has-pmecc;
44 atmel,pmecc-cap = <4>;
45 atmel,pmecc-sector-size = <512>;
46 atmel,has-nfc;
47 atmel,use-nfc-sram;
48 nand-on-flash-bbt;
49 status = "okay";
50
51 at91bootstrap@0 {
52 label = "at91bootstrap";
53 reg = <0x0 0x40000>;
54 };
55
56 bootloader@40000 {
57 label = "bootloader";
58 reg = <0x40000 0x80000>;
59 };
60
61 bootloaderenv@c0000 {
62 label = "bootloader env";
63 reg = <0xc0000 0xc0000>;
64 };
65
66 dtb@180000 {
67 label = "device tree";
68 reg = <0x180000 0x80000>;
69 };
70
71 kernel@200000 {
72 label = "kernel";
73 reg = <0x200000 0x600000>;
74 };
75
76 rootfs@800000 {
77 label = "rootfs";
78 reg = <0x800000 0x0f800000>;
79 };
80 };
81 };
82
83 leds {
84 compatible = "gpio-leds";
85
86 d2 {
87 label = "d2";
88 gpios = <&pioE 25 1>; /* PE25, conflicts with A25, RXD2 */
89 };
90 };
91};
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi
new file mode 100644
index 000000000000..4b8830eb2060
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3xdm.dtsi
@@ -0,0 +1,42 @@
1/*
2 * sama5d3dm.dtsi - Device Tree file for SAMA5 display module
3 *
4 * Copyright (C) 2013 Atmel,
5 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/ {
11 ahb {
12 apb {
13 i2c1: i2c@f0018000 {
14 qt1070: keyboard@1b {
15 compatible = "qt1070";
16 reg = <0x1b>;
17 interrupt-parent = <&pioE>;
18 interrupts = <31 0x0>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_qt1070_irq>;
21 };
22 };
23
24 adc0: adc@f8018000 {
25 status = "disabled";
26 };
27
28 tsadcc: tsadcc@f8018000 {
29 status = "okay";
30 };
31
32 pinctrl@fffff200 {
33 board {
34 pinctrl_qt1070_irq: qt1070_irq {
35 atmel,pins =
36 <4 31 0x0 0x5>; /* PE31 GPIO with pull up deglith */
37 };
38 };
39 };
40 };
41 };
42};
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
new file mode 100644
index 000000000000..661d7ca9c309
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -0,0 +1,166 @@
1/*
2 * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board
3 *
4 * Copyright (C) 2013 Atmel,
5 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/include/ "sama5d3xcm.dtsi"
10
11/ {
12 compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
13
14 ahb {
15 apb {
16 mmc0: mmc@f0000000 {
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
19 status = "okay";
20 slot@0 {
21 reg = <0>;
22 bus-width = <4>;
23 cd-gpios = <&pioD 17 0>;
24 };
25 };
26
27 spi0: spi@f0004000 {
28 m25p80@0 {
29 compatible = "atmel,at25df321a";
30 spi-max-frequency = <50000000>;
31 reg = <0>;
32 };
33 };
34
35 /*
36 * i2c0 conflicts with ISI:
37 * disable it to allow the use of ISI
38 * can not enable audio when i2c0 disabled
39 */
40 i2c0: i2c@f0014000 {
41 wm8904: wm8904@1a {
42 compatible = "wm8904";
43 reg = <0x1a>;
44 };
45 };
46
47 usart1: serial@f0020000 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
50 status = "okay";
51 };
52
53 isi: isi@f0034000 {
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_isi &pinctrl_isi_pck_as_mck &pinctrl_isi_power &pinctrl_isi_reset>;
56 };
57
58 mmc1: mmc@f8000000 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
61 status = "okay";
62 slot@0 {
63 reg = <0>;
64 bus-width = <4>;
65 cd-gpios = <&pioD 18 0>;
66 };
67 };
68
69 adc0: adc@f8018000 {
70 pinctrl-names = "default";
71 pinctrl-0 = <
72 &pinctrl_adc0_adtrg
73 &pinctrl_adc0_ad0
74 &pinctrl_adc0_ad1
75 &pinctrl_adc0_ad2
76 &pinctrl_adc0_ad3
77 &pinctrl_adc0_ad4
78 >;
79 status = "okay";
80 };
81
82 macb1: ethernet@f802c000 {
83 phy-mode = "rmii";
84 };
85
86 pinctrl@fffff200 {
87 board {
88 pinctrl_mmc0_cd: mmc0_cd {
89 atmel,pins =
90 <3 17 0x0 0x5>; /* PD17 GPIO with pullup deglitch */
91 };
92
93 pinctrl_mmc1_cd: mmc1_cd {
94 atmel,pins =
95 <3 18 0x0 0x5>; /* PD18 GPIO with pullup deglitch */
96 };
97
98 pinctrl_pck0_as_audio_mck: pck0_as_audio_mck {
99 atmel,pins =
100 <3 30 0x2 0x0>; /* PD30 periph B */
101 };
102
103 pinctrl_isi_reset: isi_reset-0 {
104 atmel,pins =
105 <4 24 0x0 0x0>; /* PE24 gpio */
106 };
107
108 pinctrl_isi_power: isi_power-0 {
109 atmel,pins =
110 <4 29 0x0 0x0>; /* PE29 gpio */
111 };
112
113 pinctrl_usba_vbus: usba_vbus {
114 atmel,pins =
115 <3 29 0x0 0x4>; /* PD29 GPIO with deglitch */
116 };
117 };
118 };
119
120 dbgu: serial@ffffee00 {
121 status = "okay";
122 };
123
124 watchdog@fffffe40 {
125 status = "okay";
126 };
127 };
128
129 usb0: gadget@00500000 {
130 atmel,vbus-gpio = <&pioD 29 0>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_usba_vbus>;
133 status = "okay";
134 };
135
136 usb1: ohci@00600000 {
137 num-ports = <3>;
138 atmel,vbus-gpio = <&pioD 25 0
139 &pioD 26 1
140 &pioD 27 1
141 >;
142 status = "okay";
143 };
144
145 usb2: ehci@00700000 {
146 status = "okay";
147 };
148 };
149
150 sound {
151 compatible = "atmel,sama5d3ek-wm8904";
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_pck0_as_audio_mck>;
154
155 atmel,model = "wm8904 @ SAMA5D3EK";
156 atmel,audio-routing =
157 "Headphone Jack", "HPOUTL",
158 "Headphone Jack", "HPOUTR",
159 "IN2L", "Line In Jack",
160 "IN2R", "Line In Jack",
161 "IN1L", "Mic";
162
163 atmel,ssc-controller = <&ssc0>;
164 atmel,audio-codec = <&wm8904>;
165 };
166};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 7e8769bd5977..16a6e13e08b4 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -81,6 +81,163 @@
81 }; 81 };
82 }; 82 };
83 83
84 clkmgr@ffd04000 {
85 compatible = "altr,clk-mgr";
86 reg = <0xffd04000 0x1000>;
87
88 clocks {
89 #address-cells = <1>;
90 #size-cells = <0>;
91
92 osc: osc1 {
93 #clock-cells = <0>;
94 compatible = "fixed-clock";
95 };
96
97 main_pll: main_pll {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 #clock-cells = <0>;
101 compatible = "altr,socfpga-pll-clock";
102 clocks = <&osc>;
103 reg = <0x40>;
104
105 mpuclk: mpuclk {
106 #clock-cells = <0>;
107 compatible = "altr,socfpga-perip-clk";
108 clocks = <&main_pll>;
109 fixed-divider = <2>;
110 reg = <0x48>;
111 };
112
113 mainclk: mainclk {
114 #clock-cells = <0>;
115 compatible = "altr,socfpga-perip-clk";
116 clocks = <&main_pll>;
117 fixed-divider = <4>;
118 reg = <0x4C>;
119 };
120
121 dbg_base_clk: dbg_base_clk {
122 #clock-cells = <0>;
123 compatible = "altr,socfpga-perip-clk";
124 clocks = <&main_pll>;
125 fixed-divider = <4>;
126 reg = <0x50>;
127 };
128
129 main_qspi_clk: main_qspi_clk {
130 #clock-cells = <0>;
131 compatible = "altr,socfpga-perip-clk";
132 clocks = <&main_pll>;
133 reg = <0x54>;
134 };
135
136 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
137 #clock-cells = <0>;
138 compatible = "altr,socfpga-perip-clk";
139 clocks = <&main_pll>;
140 reg = <0x58>;
141 };
142
143 cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
144 #clock-cells = <0>;
145 compatible = "altr,socfpga-perip-clk";
146 clocks = <&main_pll>;
147 reg = <0x5C>;
148 };
149 };
150
151 periph_pll: periph_pll {
152 #address-cells = <1>;
153 #size-cells = <0>;
154 #clock-cells = <0>;
155 compatible = "altr,socfpga-pll-clock";
156 clocks = <&osc>;
157 reg = <0x80>;
158
159 emac0_clk: emac0_clk {
160 #clock-cells = <0>;
161 compatible = "altr,socfpga-perip-clk";
162 clocks = <&periph_pll>;
163 reg = <0x88>;
164 };
165
166 emac1_clk: emac1_clk {
167 #clock-cells = <0>;
168 compatible = "altr,socfpga-perip-clk";
169 clocks = <&periph_pll>;
170 reg = <0x8C>;
171 };
172
173 per_qspi_clk: per_qsi_clk {
174 #clock-cells = <0>;
175 compatible = "altr,socfpga-perip-clk";
176 clocks = <&periph_pll>;
177 reg = <0x90>;
178 };
179
180 per_nand_mmc_clk: per_nand_mmc_clk {
181 #clock-cells = <0>;
182 compatible = "altr,socfpga-perip-clk";
183 clocks = <&periph_pll>;
184 reg = <0x94>;
185 };
186
187 per_base_clk: per_base_clk {
188 #clock-cells = <0>;
189 compatible = "altr,socfpga-perip-clk";
190 clocks = <&periph_pll>;
191 reg = <0x98>;
192 };
193
194 s2f_usr1_clk: s2f_usr1_clk {
195 #clock-cells = <0>;
196 compatible = "altr,socfpga-perip-clk";
197 clocks = <&periph_pll>;
198 reg = <0x9C>;
199 };
200 };
201
202 sdram_pll: sdram_pll {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 #clock-cells = <0>;
206 compatible = "altr,socfpga-pll-clock";
207 clocks = <&osc>;
208 reg = <0xC0>;
209
210 ddr_dqs_clk: ddr_dqs_clk {
211 #clock-cells = <0>;
212 compatible = "altr,socfpga-perip-clk";
213 clocks = <&sdram_pll>;
214 reg = <0xC8>;
215 };
216
217 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
218 #clock-cells = <0>;
219 compatible = "altr,socfpga-perip-clk";
220 clocks = <&sdram_pll>;
221 reg = <0xCC>;
222 };
223
224 ddr_dq_clk: ddr_dq_clk {
225 #clock-cells = <0>;
226 compatible = "altr,socfpga-perip-clk";
227 clocks = <&sdram_pll>;
228 reg = <0xD0>;
229 };
230
231 s2f_usr2_clk: s2f_usr2_clk {
232 #clock-cells = <0>;
233 compatible = "altr,socfpga-perip-clk";
234 clocks = <&sdram_pll>;
235 reg = <0xD4>;
236 };
237 };
238 };
239 };
240
84 gmac0: stmmac@ff700000 { 241 gmac0: stmmac@ff700000 {
85 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 242 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
86 reg = <0xff700000 0x2000>; 243 reg = <0xff700000 0x2000>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 3ae8a83a0875..2495958f1016 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -33,6 +33,14 @@
33 }; 33 };
34 34
35 soc { 35 soc {
36 clkmgr@ffd04000 {
37 clocks {
38 osc1 {
39 clock-frequency = <25000000>;
40 };
41 };
42 };
43
36 timer0@ffc08000 { 44 timer0@ffc08000 {
37 clock-frequency = <100000000>; 45 clock-frequency = <100000000>;
38 }; 46 };
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 1036eba40bbf..0bf035d607f0 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -33,6 +33,14 @@
33 }; 33 };
34 34
35 soc { 35 soc {
36 clkmgr@ffd04000 {
37 clocks {
38 osc1 {
39 clock-frequency = <10000000>;
40 };
41 };
42 };
43
36 timer0@ffc08000 { 44 timer0@ffc08000 {
37 clock-frequency = <7000000>; 45 clock-frequency = <7000000>;
38 }; 46 };
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index a30aca62658a..6ebc1b704190 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -18,4 +18,17 @@
18 pmc { 18 pmc {
19 nvidia,invert-interrupt; 19 nvidia,invert-interrupt;
20 }; 20 };
21
22 clocks {
23 compatible = "simple-bus";
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 clk32k_in: clock {
28 compatible = "fixed-clock";
29 reg=<0>;
30 #clock-cells = <0>;
31 clock-frequency = <32768>;
32 };
33 };
21}; 34};
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
index 9bea8f57aa47..5deb8692b350 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -18,4 +18,17 @@
18 pmc { 18 pmc {
19 nvidia,invert-interrupt; 19 nvidia,invert-interrupt;
20 }; 20 };
21
22 clocks {
23 compatible = "simple-bus";
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 clk32k_in: clock {
28 compatible = "fixed-clock";
29 reg=<0>;
30 #clock-cells = <0>;
31 clock-frequency = <32768>;
32 };
33 };
21}; 34};
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index e4ddeddcd437..c0b527d15fda 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -101,6 +101,8 @@
101 pmc { 101 pmc {
102 compatible = "nvidia,tegra114-pmc"; 102 compatible = "nvidia,tegra114-pmc";
103 reg = <0x7000e400 0x400>; 103 reg = <0x7000e400 0x400>;
104 clocks = <&tegra_car 261>, <&clk32k_in>;
105 clock-names = "pclk", "clk32k_in";
104 }; 106 };
105 107
106 iommu { 108 iommu {
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index cb73e62d61a9..4e3afdef28a8 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -447,6 +447,19 @@
447 cd-gpios = <&gpio 23 1>; /* gpio PC7 */ 447 cd-gpios = <&gpio 23 1>; /* gpio PC7 */
448 }; 448 };
449 449
450 clocks {
451 compatible = "simple-bus";
452 #address-cells = <1>;
453 #size-cells = <0>;
454
455 clk32k_in: clock {
456 compatible = "fixed-clock";
457 reg=<0>;
458 #clock-cells = <0>;
459 clock-frequency = <32768>;
460 };
461 };
462
450 sound { 463 sound {
451 compatible = "nvidia,tegra-audio-wm9712-colibri_t20", 464 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
452 "nvidia,tegra-audio-wm9712"; 465 "nvidia,tegra-audio-wm9712";
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 1f79c0debb05..ae9d5a20834e 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -451,6 +451,19 @@
451 bus-width = <8>; 451 bus-width = <8>;
452 }; 452 };
453 453
454 clocks {
455 compatible = "simple-bus";
456 #address-cells = <1>;
457 #size-cells = <0>;
458
459 clk32k_in: clock {
460 compatible = "fixed-clock";
461 reg=<0>;
462 #clock-cells = <0>;
463 clock-frequency = <32768>;
464 };
465 };
466
454 kbc { 467 kbc {
455 status = "okay"; 468 status = "okay";
456 nvidia,debounce-delay-ms = <2>; 469 nvidia,debounce-delay-ms = <2>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 9db36da8e023..fd60940e4063 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -447,6 +447,19 @@
447 bus-width = <8>; 447 bus-width = <8>;
448 }; 448 };
449 449
450 clocks {
451 compatible = "simple-bus";
452 #address-cells = <1>;
453 #size-cells = <0>;
454
455 clk32k_in: clock {
456 compatible = "fixed-clock";
457 reg=<0>;
458 #clock-cells = <0>;
459 clock-frequency = <32768>;
460 };
461 };
462
450 gpio-keys { 463 gpio-keys {
451 compatible = "gpio-keys"; 464 compatible = "gpio-keys";
452 465
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 715a8b8dd9cd..4ee700a33ca5 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -595,6 +595,19 @@
595 bus-width = <8>; 595 bus-width = <8>;
596 }; 596 };
597 597
598 clocks {
599 compatible = "simple-bus";
600 #address-cells = <1>;
601 #size-cells = <0>;
602
603 clk32k_in: clock {
604 compatible = "fixed-clock";
605 reg=<0>;
606 #clock-cells = <0>;
607 clock-frequency = <32768>;
608 };
609 };
610
598 gpio-keys { 611 gpio-keys {
599 compatible = "gpio-keys"; 612 compatible = "gpio-keys";
600 613
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 6e9d91fc6195..c19025725918 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -471,6 +471,19 @@
471 status = "okay"; 471 status = "okay";
472 }; 472 };
473 473
474 clocks {
475 compatible = "simple-bus";
476 #address-cells = <1>;
477 #size-cells = <0>;
478
479 clk32k_in: clock {
480 compatible = "fixed-clock";
481 reg=<0>;
482 #clock-cells = <0>;
483 clock-frequency = <32768>;
484 };
485 };
486
474 regulators { 487 regulators {
475 compatible = "simple-bus"; 488 compatible = "simple-bus";
476 489
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 98f3e44f2a51..a9f3f06580f5 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -330,6 +330,19 @@
330 bus-width = <4>; 330 bus-width = <4>;
331 }; 331 };
332 332
333 clocks {
334 compatible = "simple-bus";
335 #address-cells = <1>;
336 #size-cells = <0>;
337
338 clk32k_in: clock {
339 compatible = "fixed-clock";
340 reg=<0>;
341 #clock-cells = <0>;
342 clock-frequency = <32768>;
343 };
344 };
345
333 poweroff { 346 poweroff {
334 compatible = "gpio-poweroff"; 347 compatible = "gpio-poweroff";
335 gpios = <&gpio 191 1>; /* gpio PX7, active low */ 348 gpios = <&gpio 191 1>; /* gpio PX7, active low */
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 4aef56f2d96a..f544806e9618 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -531,6 +531,19 @@
531 bus-width = <8>; 531 bus-width = <8>;
532 }; 532 };
533 533
534 clocks {
535 compatible = "simple-bus";
536 #address-cells = <1>;
537 #size-cells = <0>;
538
539 clk32k_in: clock {
540 compatible = "fixed-clock";
541 reg=<0>;
542 #clock-cells = <0>;
543 clock-frequency = <32768>;
544 };
545 };
546
534 regulators { 547 regulators {
535 compatible = "simple-bus"; 548 compatible = "simple-bus";
536 #address-cells = <1>; 549 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 5762188c60ad..258cf945f515 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -520,6 +520,19 @@
520 bus-width = <8>; 520 bus-width = <8>;
521 }; 521 };
522 522
523 clocks {
524 compatible = "simple-bus";
525 #address-cells = <1>;
526 #size-cells = <0>;
527
528 clk32k_in: clock {
529 compatible = "fixed-clock";
530 reg=<0>;
531 #clock-cells = <0>;
532 clock-frequency = <32768>;
533 };
534 };
535
523 kbc { 536 kbc {
524 status = "okay"; 537 status = "okay";
525 nvidia,debounce-delay-ms = <20>; 538 nvidia,debounce-delay-ms = <20>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index ad64c8cc9da7..fc7febc2b386 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -418,6 +418,8 @@
418 pmc { 418 pmc {
419 compatible = "nvidia,tegra20-pmc"; 419 compatible = "nvidia,tegra20-pmc";
420 reg = <0x7000e400 0x400>; 420 reg = <0x7000e400 0x400>;
421 clocks = <&tegra_car 110>, <&clk32k_in>;
422 clock-names = "pclk", "clk32k_in";
421 }; 423 };
422 424
423 memory-controller@7000f000 { 425 memory-controller@7000f000 {
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 0a2cd24df853..6248b2445b32 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -268,6 +268,19 @@
268 bus-width = <8>; 268 bus-width = <8>;
269 }; 269 };
270 270
271 clocks {
272 compatible = "simple-bus";
273 #address-cells = <1>;
274 #size-cells = <0>;
275
276 clk32k_in: clock {
277 compatible = "fixed-clock";
278 reg=<0>;
279 #clock-cells = <0>;
280 clock-frequency = <32768>;
281 };
282 };
283
271 regulators { 284 regulators {
272 compatible = "simple-bus"; 285 compatible = "simple-bus";
273 #address-cells = <1>; 286 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 3e2d21018a5b..65bf2b63174e 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -322,6 +322,19 @@
322 bus-width = <8>; 322 bus-width = <8>;
323 }; 323 };
324 324
325 clocks {
326 compatible = "simple-bus";
327 #address-cells = <1>;
328 #size-cells = <0>;
329
330 clk32k_in: clock {
331 compatible = "fixed-clock";
332 reg=<0>;
333 #clock-cells = <0>;
334 clock-frequency = <32768>;
335 };
336 };
337
325 regulators { 338 regulators {
326 compatible = "simple-bus"; 339 compatible = "simple-bus";
327 #address-cells = <1>; 340 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 9491edf1a067..9fe7a92b4c85 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -427,6 +427,8 @@
427 pmc { 427 pmc {
428 compatible = "nvidia,tegra30-pmc"; 428 compatible = "nvidia,tegra30-pmc";
429 reg = <0x7000e400 0x400>; 429 reg = <0x7000e400 0x400>;
430 clocks = <&tegra_car 218>, <&clk32k_in>;
431 clock-names = "pclk", "clk32k_in";
430 }; 432 };
431 433
432 memory-controller { 434 memory-controller {
diff --git a/arch/arm/boot/dts/tps6507x.dtsi b/arch/arm/boot/dts/tps6507x.dtsi
new file mode 100644
index 000000000000..4c326e591e5a
--- /dev/null
+++ b/arch/arm/boot/dts/tps6507x.dtsi
@@ -0,0 +1,47 @@
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Integrated Power Management Chip
11 * http://www.ti.com/lit/ds/symlink/tps65070.pdf
12 */
13
14&tps {
15 compatible = "ti,tps6507x";
16
17 regulators {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 vdcdc1_reg: regulator@0 {
22 reg = <0>;
23 regulator-compatible = "VDCDC1";
24 };
25
26 vdcdc2_reg: regulator@1 {
27 reg = <1>;
28 regulator-compatible = "VDCDC2";
29 };
30
31 vdcdc3_reg: regulator@2 {
32 reg = <2>;
33 regulator-compatible = "VDCDC3";
34 };
35
36 ldo1_reg: regulator@3 {
37 reg = <3>;
38 regulator-compatible = "LDO1";
39 };
40
41 ldo2_reg: regulator@4 {
42 reg = <4>;
43 regulator-compatible = "LDO2";
44 };
45
46 };
47};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-08 14:39:24 -0500